Crystal oscillator
►HCSL Output
Please contact us about available frequencies.
Storage as single product.
P:0 C to +70 C ,R:-5 C to +85 C ,S:-20 C to +70 C
G: 50 10-6 ,H: 100 10-6
at outputs crossing point
Output load condition (HCSL)
Between 0.175 V and 0.525 V of output
Time at minimum supply voltage to be 0 s
Offset frequency: 12 kHz to
20 MHz
+25 C, First year, VCC=2.5 V,3.3 V
Product Name EG-2121 CA 250.000000MHz P G P A
(Standard form) ① ② ③ ④⑤⑥⑦
①Model ②Package type ③Frequency
④Output/Symmetry ⑤Frequency tolerance ⑥Operating temperature
⑦Frequency aging (A*1: Frequency tolerance include aging, N*2: Frequency tolerance exclude aging)
*1 This includes initial frequency tolerance, temperature variation, supply voltage variation, reflow drift, and aging(+25 C,10 years).
*2 This includes initial frequency tolerance, temperature variation, supply voltage variation, and reflow drift(except aging).
(⑤⑥⑦: GRA, GSA are not available)
(⑤⑥: As for LV-PECL and LVDS output, for 53.125 MHz f0 < 100 MHz only HP is available)
(RMS of total distribution)
Accumulated Jitter() n=2 to 50000 cycles
* Tested using a DTS-2075 Digital timing system made by WAVECREST with jitter analysis software VISI6. : Differential LV-PECL, LVDS output
* Based on SIA-3100C signal integrity analyzer made from WAVECREST. : HCSL output
40 % to 60 %(f0 > 350 MHz)
45 % to 55 %(f0 350 MHz)
48 % to 52 %(f0 175 MHz)
48 % to 52 %(f0 350 MHz)
40 % to 60 %(f0 > 350 MHz)
45 % to 55 %(f0 350 MHz)
48 % to 52 %(f0 175 MHz)
#3 is connected to the cover.
OE pin = HIGH : Specified frequency output.
OE pin = LOW : Output is high impedance
To maintain stable operation, provide a 0.01uF to
0.1uF by-pass capacitor at a location as near as
possible to the power source terminal of the
crystal product (between Vcc - GND).