DP8405(DP8402A - DP8405) - National Semiconductor

TL/F/8535

DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel

Error Detection and Correction Circuits (EDAC’s)

PRELIMINARY

August 1989

DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel

Error Detection and Correction Circuits (EDAC’s)

General Description

The DP8402A, DP8403, DP8404 and DP8405 devices are

32-bit parallel error detection and correction circuits

(EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404

and DP8405 600-mil packages. The EDACs use a modified

Hamming code to generate a 7-bit check word from a 32-bit

data word. This check word is stored along with the data

word during the memory write cycle. During the memory

read cycle, the 39-bit words from memory are processed by

the EDACs to determine if errors have occurred in memory.

Single-bit errors in the 32-bit data word are flagged and cor-

rected.

Single-bit errors in the 7-bit check word are flagged, and the

CPU sends the EDAC through the correction cycle even

though the 32-bit data word is not in error. The correction

cycle will simply pass along the original 32-bit data word in

this case and produce error syndrome bits to pinpoint the

error-generating location.

Double bit errors are flagged but not corrected. These er-

rors may occur in any two bits of the 39-bit word from mem-

ory (two errors in the 32-bit data word, two errors in the 7-bit

check word, or one error in each word). The gross-error

condition of all lows or all highs from memory will be detect-

ed. Otherwise, errors in three or more bits of the 39-bit word

are beyond the capabilities of these devices to detect.

Read-modify-write (byte-control) operations can be per-

formed with the DP8402A and DP8403 EDACs by using out-

put latch enable, LEDBO, and the individual OEB0 thru

OEB3 byte control pins.

Diagnostics are performed on the EDACs by controls and

internal paths that allow the user to read the contents of the

DB and CB input latches. These will determine if the failure

occurred in memory or in the EDAC.

Features

YDetects and corrects single-bit errors

YDetects and flags double-bit errors

YBuilt-in diagnostic capability

YFast write and read cycle processing times

YByte-write capability . . . DP8402A and DP8403

YFully pin and function compatible with TI’s

SN74ALS632A thru SN74ALS635 series

System Environment

TL/F/8535–1

TRI-STATEÉis a registered trademark of National Semiconductor Corp.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Simplified Functional Block and Connection Diagrams

TL/F/8535–2

Device Package Byte-Write Output

DP8402A 52-pin yes TRI-STATEÉ

DP8403 52-pin yes Open-Collector

DP8404 48-pin no TRI-STATE

DP8405 48-pin no Open-Collector

Dual-In-Line Packages

TL/F/8535–10

Top View

TL/F/8535–3

Top View

Plastic Chip Carrier

TL/F/8535–11

Top View

Order Number DP8402AV

See NS Package Number V68A

Order Number DP8402AD,

DP8403D, DP8404D or DP8405D

See NS Package Number D48A or D52A

Mode Definitions

DESCRIPTIONPIN NAMEMODE

S1 S0 MODE OPERATION

0 L L WRITE Input dataword and output

checkword

1 L H DIAGNOSTICS Input various data words

against latched

checkword/output valid

error flags.

2 H L READ & FLAG Input dataword and output

error flags

3 H H CORRECT Latched input data and

checkword/output

corrected data and

syndrome code

Pin Definitions

S0, S1 Control of EDAC mode, see preceding

Mode Definitions

DB0 thru DB31 I/O port for 32 bit dataword.

CB0 thru CB6 I/O port for 7 bit checkword. Also output

port for the syndrome error code during

error correction mode.

OEB0 thru Dataword output buffer enable. When high,

OEB3 output buffers are at TRI-STATE. Each pin

(DP8402A, controls 8 I/O ports. OEB0 controls DB0

DP8403) thru DB7, OEB1 controls DB8 thru DB15,

OEB2 controls DB16 thru DB23 and OEB3

controls DB24 thru DB31.

LEDBO Data word output Latch enable. When high

(DP8402A, it inhibits input to the Latch. Operates on all

DP8403) 32 bits of the dataword.

OEDB TRI-STATE control for the data I/O port.

(DP8404, When high output buffers are at

DP8405) TRI-STATE.

OECB Checkword output buffer enable. When

high the output buffers are in TRI-STATE

mode.

ERR Single error output flag, a low indicates at

least a single bit error.

MERR Multiple error output flag, a low indicates

two or more errors present.

PCC Pin Definitions DP8402A

pin 1 VCC pin 35 OECB

2 LEDBO 36 CB3

3 MERR 37 CB2

4 ERR 38 CB1

5 DB0 39 CB0

6 DB1 40 DB16

7 DB2 41 DB17

8NC 42NC

9NC 43NC

10 NC 44 DB18

11 DB3 45 DB19

12 DB4 46 DB20

13 DB5 47 DB21

14 OEBO 48 OEB2

15 DB6 49 DB22

16 DB7 50 DB23

17 GND 51 GND

18 GND 52 GND

19 DB8 53 DB24

20 DB9 54 DB25

21 OEB1 55 OEB3

22 DB10 56 DB26

23 DB11 57 DB27

24 DB12 58 DB28

25 DB13 59 NC

26 DB14 60 NC

27 NC 61 NC

28 NC 62 NC

29 NC 63 DB29

30 DB15 64 DB30

31 NC 65 DB31

32 CB6 66 S0

33 CB5 67 S1

34 CB4 68 VCC

TABLE I. Write Control Function

Memory EDAC Control DB Control DB Output Latch CB Error Flags

Cycle Function S1 S0 Data I/O OEBn or DP8402A, DP8403 Check I/O Control ERR MERR

OEDB LEDBO OECB

Write Generate L L Input H X Output LHH

check word check bits²

²See Table II for details on check bit generation.

Memory Write Cycle Details

During a memory write cycle, the check bits (CB0 thru CB6)

are generated internally in the EDAC by seven 16-input pari-

ty generators using the 32-bit data word as defined in Table

2. These seven check bits are stored in memory along with

the original 32-bit data word. This 32-bit word will later be

used in the memory read cycle for error detection and cor-

rection.

TABLE II. Parity Algorithm

Check Word 32-Bit Data Word

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CB0XXXX XXXX X XXXXXX X

CB1 XXXXXXXX XXXXX XX

CB2XXXXXXXXXXXXXXXXX

CB3 XXX XXX XX XXX XXX XX

CB4 XX XXXXXX XX XXXXXX

CB5 XXXXXXXX XXXXXXXX

CB6 XXXXXXXX XXXXXXXX

The seven check bits are parity bits derived from the matrix of data bits as indicated by ‘‘X’’ for each bit.

Check bits 0, 1, 2 are odd parity or the exclusive NORing of the ‘‘X’’ed bits for the particular check bit. Check bits 3, 4, 5, 6 are even parity or the exclusive ORing of

the ‘‘X’’ed bits for the particular check bit.

Memory Read Cycle (Error

Detection & Correction Details)

During a memory read cycle, the 7-bit check word is re-

trieved along with the actual data. In order to be able to

determine whether the data from the memory is acceptable

to use as presented on the bus, the error flags must be

tested to determine if they are at the high level.

The first case in Table III represents the normal, no-error

conditions. The EDAC presents highs on both flags. The

next two cases of single-bit errors give a high on MERR and

a low on ERR, which is the signal for a correctable error,

and the EDAC should be sent through the correction cycle.

The last three cases of double-bit errors will cause the

EDAC to signal lows on both ERR and MERR, which is the

interrupt indication for the CPU.

TABLE III. Error Function

Total Number of Errors Error Flags Data Correction

32-Bit Data Word 7-Bit Check Word ERR MERR

0 0 H H Not applicable

1 0 L H Correction

0 1 L H Correction

1 1 L L Interrupt

2 0 L L Interrupt

0 2 L L Interrupt

The DP8402 check bit syndrome matrix can be seen in TA-

BLE II. The horizontal rows of this matrix generate the

check bits by selecting different combinations of data bits,

indicated by ‘‘X’’s in the matrix, and generating parity from

them. For instance, parity check bit ‘‘0’’ is generated by

EXCLUSIVE NORing the following data bits together; 31,

29, 28, 26, 21, 19, 18, 17, 14, 11, 9, 8, 7, 6, 4, and 0. For

example, the data word ‘‘00000001H’’ would generate the

check bits CB6– 0 e48H (Check bits 0, 1, 2 are odd parity

and check bits 3, 4, 5, 6 are even parity).

During a WRITE operation (mode 0) the data enters the

DP8402 and check bits are generated at the check bit in-

put/output port. Both the data word and the check bits are

then written to memory.

During a READ operation (mode 2, error detection) the data

and check bits that were stored in memory, now possibly in

error, are input through the data and check bit I/O ports.

New check bits are internally generated from the data word.

These new check bits are then compared, by an EXCLU-

SIVE NOR operation, with the original check bits that were

stored in memory. The EXCLUSIVE NOR of the original

check bits, that were stored in memory, with the new check

bits is called the syndrome word. If the original check bits

are the same as the new check bits, a no error condition,

then a syndrome word of all ones is produced and both

error flags (ERR and MERR) will be high. The DP8402 ma-

trix encodes errors as follows:

TABLE IV. Read, Flag, and Correct Function

Memory EDAC Control DB Control DB Output Latch CB Error Flags

Cycle Function S1 S0 Data I/O OEBn or DP8402A, DP8403 Check I/O Control ERR MERR

OEDB LEDBO OECB

Read Read & flag H L Input H X Input H Enabled²

Latch input Input Input

Read data and check H H data H L check word H Enabled²

bits latched latched

Output Output Output

Read corrected data H H corrected L X syndrome L Enabled²

& syndrome bits data word bits³

²See Table III for error description.

³See Table V for error location.

Memory Read Cycle (Error Detection & Correction Details) (Continued)

1) Single data bit errors cause 3 or 5 bits in the syndrome

word to go low. The columns of the check bit syndrome

matrix (TABLE II) are the syndrome words for all single bit

data errors in the 32 bit word (also see TABLE V). The

data bit in error corresponds to the column in the check

bit syndrome matrix that matches the syndrome word.

For instance, the syndrome word indicating that data bit

31 is in error would be (CB6-CB0) e‘‘0001010’’, see the

column for data bit 31 in TABLE II, or see TABLE V.

During mode 3 (S0 eS1 e1) the syndrome word is

decoded, during single data bit errors, and used to invert

the bit in error thus correcting the data word. The correct-

ed word is made available on the data I/O port (DB0 thru

DB31), the check word I/O port (CB0 thru CB6) presents

the 7-bit syndrome error code. This syndrome error code

can be used to locate the bad memory chip.

2) A single check bit error will cause that particular check bit

to go low in the syndrome word.

3) A double bit error will cause an even number of bits in the

syndrome word to go low. The syndrome word will then

be the EXCLUSIVE NOR of the two individual syndrome

words corresponding to the 2 bits in error. The two-bit

error is not correctable since the parity tree can only

identify single bit errors.

If any of the bits in the syndrome word are low the ‘‘ERR’’

flag goes low. The ‘‘MERR’’ (dual error) flag goes low during

any double bit error conditions. (See Table III).

Three or more simultaneous bit errors can cause the EDAC

to believe that no error, a correctable error, or an uncorrect-

able error has occurred and will produce erroneous results

in all three cases. It should be noted that the gross-error

conditions of all lows and all highs will be detected.

TABLE V. Syndrome Decoding

Syndrome Bits Error

6543210

LLLLLLL unc

LLLLLLH2-bit

L L L L L H L 2-bit

LLL L LHH unc

L L L L H L L 2-bit

LLLLHLH unc

LLL LHHL unc

L L L L H H H 2-bit

L L L H L L L 2-bit

LLLHLLH unc

LLLHLHLDB31

LLLHLHH 2-bit

LLLHHLL unc

L L L H H L H 2-bit

L L L H H H L 2-bit

LLLHHHHDB30

LLHLLLL 2-bit

LLHL L LH unc

L L H L L H L DB29

L L H L L H H 2-bit

LLHLHLLDB28

LLHLHLH 2-bit

L L H L H H L 2-bit

L L H L H H H DB27

LLHHL L LDB26

LLHHL LH 2-bit

LLHHLHL 2-bit

L L H H L H H DB25

LLHHHL L 2-bit

LLHHHLHDB24

LLHHHHL unc

LLHHHHH 2-bit

CB X eerror in check bit X

DB Y eerror in data bit Y

2-bit edouble-bit error

unc euncorrectable multibit error

Syndrome Bits Error

6543210

L H L L L L L 2-bit

LHLLLLH unc

LHLLLHL DB7

L H L L L H H 2-bit

L H L L H L L DB6

L H L L H L H 2-bit

L H L L H H L 2-bit

LHL LHHH DB5

LHLHLLL DB4

L H L H L L H 2-bit

L H L H L H L 2-bit

LHLHLHH DB3

L H L H H L L 2-bit

LHLHHLH DB2

LHLHHHL unc

L H L H H H H 2-bit

LHHL L L L DB0

L H H L L L H 2-bit

L H H L L H L 2-bit

LHHL LHH unc

L H H L H L L 2-bit

LHHLHLH DB1

LHHLHHL unc

L H H L H H H 2-bit

LHHHL L L 2-bit

LHHHL LH unc

LHHHLHL unc

LHHHLHH 2-bit

LHHHHL L unc

LHHHHLH 2-bit

LHHHHHL 2-bit

LHHHHHH CB6

Syndrome Bits Error

6543210

H L L L L L L 2-bit

HLLLLLH unc

HLLLLHL unc

H L L L L H H 2-bit

H L L L H L L unc

H L L L H L H 2-bit

H L L L H H L 2-bit

HLL LHHH unc

HLLHLLL unc

H L L H L L H 2-bit

H L L H L H L 2-bit

H L L H L H H DB15

H L L H H L L 2-bit

HLLHHLH unc

H L L H H H L DB14

H L L H H H H 2-bit

HLHL L L L unc

H L H L L L H 2-bit

H L H L L H L 2-bit

H L H L L H H DB13

H L H L H L L 2-bit

H L H L H L H DB12

H L H L H H L DB11

H L H L H H H 2-bit

HLHHL L L 2-bit

HLHHL LHDB10

HLHHLHL DB9

HLHHLHH 2-bit

HLHHHL L DB8

HLHHHLH 2-bit

HLHHHHL 2-bit

HLHHHHH CB5

Syndrome Bits Error

6543210

HHLLLLL unc

HHLLLLH 2-bit

H H L L L H L 2-bit

H H L L L H H DB23

H H L L H L L 2-bit

HHLLHLHDB22

H H L L H H L DB21

H H L L H H H 2-bit

H H L H L L L 2-bit

HHLHLLHDB20

HHLHLHLDB19

HHLHLHH 2-bit

H H L H H L L DB18

H H L H H L H 2-bit

H H L H H H L 2-bit

HHLHHHH CB4

HHHLLLL 2-bit

H H H L L L H DB16

HHHL LHL unc

H H H L L H H 2-bit

HHHLHLLDB17

HHHLHLH 2-bit

H H H L H H L 2-bit

HHHLHHH CB3

HHHHL L L unc

HHHHL LH 2-bit

HHHHLHL 2-bit

HHHHLHH CB2

HHHHHL L 2-bit

HHHHHLH CB1

HHHHHHL CB0

HHHHHHH none

TABLE VI. Read-Modify-Write Function

DB OUTPUT

MEMORY EDAC FUNCTION CONTROL BYTEn²OEBn²LATCH CHECK I/O CB ERROR FLAG

CYCLE S1 S0 LEDBO CONTROL ERR MERR

Read Read & Flag H L Input H X Input H Enabled

Input Input

Read Latch input data H H data H L check word H Enabled

& check bits latched latched

Latch corrected Output Hi-Z H

Read data word into H H data HH

Output Enabled

output latch word Syndrome L

latched bits

Input

Modify appropriate modified H

Modify byte or bytes & LL

BYTE0 HOutput LHH

/write generate new Ouput check word

check word unchanged L

BYTE0

²OEB0 controls DB0–DB7(BYTE0), OEB1 controls DB8–DB15 (BYTE1), OEB2 controls DB16–DB23 (BYTE2), OEB3 controls DB24–DB31 (BYTE3).

Read-Modify-Write (Byte Control)

Operations

The DP8402A and DP8403 devices are capable of byte-

write operations. The 39-bit word from memory must first be

latched into the DB and CB input latches. This is easily ac-

complished by switching from the read and flag mode (S1 e

H, SO eL) to the latch input mode (S1 eH, S0 eH). The

EDAC will then make any corrections, if necessary, to the

data word and place it at the input of the output data latch.

This data word must then be latched into the output data

latch by taking LEDBO from a low to a high.

Byte control can now be employed on the data word

through the OEB0 through OEB3 controls. OEB0 controls

DB0– DB7 (byte 0), OEB1 controls DB8– DB15 (byte 1),

OEB2 controls DB16– DB23 (byte 2), and OEB3 controls

DB24– DB31 (byte 3). Placing a high on the byte control will

disable the output and the user can modify the byte. If a low

is placed on the byte control, then the original byte is al-

lowed to pass onto the data bus unchanged. If the original

data word is altered through byte control, a new check word

must be generated before it is written back into memory.

This is easily accomplished by taking control S1 and S0 low.

Table VI lists the read-modify-write functions.

Diagnostic Operations

The DP8402A thru DP8405 are capable of diagnostics that

allow the user to determine whether the EDAC or the mem-

ory is failing. The diagnostic function tables will help the

user to see the possibilities for diagnostic control.

In the diagnostic mode (S1 eL, S0 eH), the checkword is

latched into the input latch while the data input remains

transparent. This lets the user apply various data words

against a fixed known checkword. If the user applies a diag-

nostic data word with an error in any bit location, the ERR

flag should be low. If a diagnostic data word with two errors

in any bit location is applied, the MERR flag should be low.

After the checkword is latched into the input latch, it can be

verified by taking OECB low. This outputs the latched

checkword. With the DP8402A and DP8403, the diagnostic

data word can be latched into the output data latch and

verified. It should be noted that the DP8404 and DP8405 do

not have this pass-through capability because they do not

contain an output data latch. By changing from the diagnos-

tic mode (S1 eL, S0 eH) to the correction mode (S1 eH,

S0 eH), the user can verify that the EDAC will correct the

diagnostic data word. Also, the syndrome bits can be pro-

duced to verify that the EDAC pinpoints the error location.

Table VII DP8402A and DP8403 and Table VIII DP8404 and

DP8405 list the diagnostic functions.

TABLE VII. DP8402A, DP8403 Diagnostic Function

DB BYTE DB OUTPUT CB ERROR FLAGS

EDAC FUNCTION

CONTROL

DATA I/O CONTROL LATCH CHECK I/O CONTROL ERR MERR

S1 S0 OEBn LEDBO OECB

Read & flag H L Input correct HX

Input correct HHH

data word check bits

Latch input check Input Input

word while data L H diagnostic H L check bits H Enabled

input latch remains data word²latched

transparent

Latch diagnostic Input Output latched L

data word into L H diagnostic H H check bits Enabled

output latch data word²Hi-Z H

Latch diagnostic Input Output

data word into H H diagnostic H H syndrome L Enabled

input latch data word bits

latched Hi-Z H

Output

Output diagnostic Output syndrome L

data word & H H diagnostic L H bits Enabled

syndrome bits data word Hi-Z H

Output corrected Output Output

diagnostic data HH

corrected LL

syndrome L Enabled

word & output diagnostic bits

syndrome bits data word Hi-Z H

²Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data word will contain errors in

two bit locations.

TABLE VIII. DP8404, DP8405 Diagnostic Function

EDAC FUNCTION CONTROL DATA I/O DB CONTROL CHECK I/O DB CONTROL ERROR FLAGS

S1 S0 OEDB OECB ERR MERR

Read & flag H L Input correct HInput correct HHH

data word check bits

Latch input check Input Input

bits while data L H diagnostic H check bits H Enabled

input latch remains data word²latched

transparent

Input

Output input L H diagnostic H Output input L Enabled

check bits data word²check bits

Latch diagnostic Input Output L

data into H H diagnostic Hsyndrome bits Enabled

input latch data word Hi-Z H

latched

Output corrected Output corrected Output L

diagnostic H H diagnostic L syndrome bits Enabled

data word data word Hi-Z H

²Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data word will contain errors in

two bit locations.

DP8402A, DP8403 Logic Diagram (Positive Logic)

TL/F/8535–4

DP8404, DP8405 Logic Diagram (Positive Logic)

TL/F/8535–5

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Over Operating Free-Air Temperature Range (unless otherwise noted)

Supply Voltage, VCC (See Note 1) 7V

Input Voltage: CB and DB 5.5V

All Others 7V

Operating Free-Air Temperature: Military b55§Ctoa

125§C

Commercial 0§to a70§C

Storage Temperature Range b65§Ctoa

150§C

Recommended Operating Conditions

Symbol Parameter Conditions Military Commercial Units

Min Typ Max Min Typ Max

VCC Supply Voltage 4.5 5 5.5 4.5 5 5.5 V

VIH High-Level Input Voltage 2 2 V

VIL Low-Level Input Voltage 0.8 0.8 V

IOH High-Level Output Current ERR Or MERR b0.4 b0.4 mA

DB Or CB DP8402A, DP8404 b1b2.6

IOL Low-Level Output Current ERR Or MERR 48

DB or CB 12 24

twPulse Duration LEDBO Low 25 25 ns

(1) Data And Check Word Before S0

15 10

(S1 eH)

(2) SO High Before LEDBO

(S1 eH)²45 45

(3) LEDBO High Before The Earlier 00

of S0

or S1

tsu Setup Time (4) LEDBO High Before S1

(S0 eH) 0 0 ns

(5) Diagnostic Data Word Before S1

15 10

(S0 eH)

(6) Diagnostic Check Word Before 15 10

The Later Of S1

or S0

(7) Diagnostic Data Word Before 25 20

LEDBO

(S1 eL and S0 eH)³

(8) Read-Mode, S0 Low And S1 High 35 30

(9) Data And Check Word After 20 15

(S1 eH)

thHold Time (10) Data Word After S1

(S0 eH) 20 15 ns

(11) Check Word After The Later 20 15

of S1

or S0

(12) Diagnostic Data Word After 00

LEDBO

(S1 eL And S0 eH)³

tcorr Correction Time (see

Figure 1

)*65 58 ns

TAOperating Free-Air Temperature b55 125 0 70 §C

*This specification may be interpreted as the maximum delay to guarantee valid corrected data at the output and includes the tsu setup delay.

²These times ensure that corrected data is saved in the output data latch.

³These times ensure that the diagnostic data word is saved in the output data latch.

DP8402A, DP8404 Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)

Symbol Parameter Test Conditions Military Commercial Units

Min Typ²Max Min Typ²Max

VIK VCC e4.5V, IIeb

18 mA b1.5 b1.5 V

All outputs VCC e4.5V to 5.5V, IOH eb0.4 mA VCCb2V

CCb2

VOH DB or CB VCC e4.5V, IOH eb

1 mA 2.4 3.3 V

VCC e4.5V, IOH eb

2.6 mA 2.4 3.2

ERR or MERR VCC e4.5V, IOL e4 mA 0.25 0.4 0.25 0.4

VOL

VCC e4.5V, IOL e8 mA 0.35 0.5 V

DB or CB VCC e4.5V, IOL e12 mA 0.25 0.4 0.25 0.4

VCC e4.5V, IOL e24 mA 0.35 0.5

S0 or S1 VCC e5.5V, VIe7V 0.1 0.1 mA

All others VCC e5.5V, VIe5.5V 0.1 0.1

IIH

S0 or S1 VCC e5.5V, VIe2.7V 20 20

All others³20 20

IIL

S0 or S1 VCC e5.5V, VIe0.4V

b0.4 b0.4 mA

All others³b0.1 b0.1

IOõVCC e5.5V, VOe2.25V b30 b112 b30 b112 mA

ICC VCC e5.5V, (See Note 1) 150 250 150 250 mA

DP8403, DP8405 Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)

Symbol Parameter Test Conditions Military Commercial Units

Min Typ²Max Min Typ²Max

VIK VCC e4.5V, IIeb

18 mA b1.5 b1.5 V

VOH ERR or MERR VCC e4.5V to 5.5V, IOH eb

0.4 mA VCCb2V

CCb2V

OH DB or CB VCC e4.5V, VOH e5.5V 0.1 0.1 mA

ERR or MERR VCC e4.5V, IOL e4 mA 0.25 0.4 0.25 0.4

VOL

VCC e4.5V, IOL e8 mA 0.35 0.5 V

DB or CB VCC e4.5V, IOL e12 mA 0.25 0.4 0.25 0.4

VCC e4.5V, IOL e24 mA 0.35 0.5

S0 or S1 VCC e5.5V, VIe7V mA

All others VCC e5.5V, VIe5.5V

IIH

S0 or S1 VCC e5.5V, VIe2.7V mA

All others³

IIL

S0 or S1 VCC e5.5V, VIe0.4V mA

All others³

IOõERR or MERR VCC e5.5V, VOe2.25V b30 b112 b30 b112 mA

ICC VCC e5.5V, (See Note 1) 150 150 mA

²All typical values are at VCC e5V, TAea

25§C.

³For I/O ports (QAthrough QH), the parameters IIH and IIL include the off-state output current.

õThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

Note 1: ICC is measured with S0 and S1 at 4.5V and all CB and DB pins grounded.

DP8402A Switching Characteristics

VCC e4.5V to 5.5V, CLe50 pF, TAeMin to Max (unless otherwise noted)

Symbol From To Test Conditions Military Commercial Units

(Input) (Output) Min Max Min Max

tpd

DB and CB ERR S1 eH, S0 eL, RLe500X10 43 10 40 ns

DB ERR S1 eL, S0 eH, RLe500X10 43 10 40

tpd

DB and CB MERR S1 eH, S0 eL, RLe500X15 67 15 55 ns

DB MERR S1 eL, S0 eH, RLe500X15 67 15 55

tpd S0

and S1

CB R1 eR2 e500X10 60 10 48 ns

tpd DB CB S1 eL, S0 eL, R1 eR2 e500X10 60 10 48 ns

tpd LEDB0

DB S1 eX, S0 eH, R1 eR2 e500X7 35 7 30 ns

tpd S1

CB S0 eH, R1 eR2 e500X10 60 10 50 ns

ten OECB

CB S0 eH, S1 eX, R1 eR2 e500X2 30 2 25 ns

tdis OECB

CB S0 eH, S1 eX, R1 eR2 e500X2 30 2 25 ns

ten OEB0 thru OEB3

DB S0 eH, S1 eX, R1 eR2 e500X2 30 2 25 ns

tdis OEB0 thru OEB3

DB S0 eH, S1 eX, R1 eR2 e500X2 30 2 25 ns

DP8403 Switching Characteristics

VCC e4.5V to 5.5V, CLe50 pF, TAeMin to Max (unless otherwise noted)

Symbol From To Test Conditions Military Commercial Units

(Input) (Output) Min Typ²Max Min Typ²Max

tpd

DB and CB ERR S1 eH, S0 eL, RLe500X26 26 ns

DB ERR S1 eL, S0 eH, RLe500X26 26

tpd DB and CB MERR S1 eH, S0 eL, RLe500X40 40 ns

S1 eL, S0 eH, RLe500X40 40

tpd S0

and S1

CB RLe680X40 40 ns

tpd DB CB S1 eL, S0 eL, RLe680X40 40 ns

tpd LEDB0

DB S1 eX, S0 eH, RLe680X26 26 ns

tpd S1

CB S0 eH, RLe680X40 40 ns

tPLH OECB

CB S1 eX, S0 eH, RLe680X24 24 ns

tPHL OECB

CB S1 eX, S0 eH, RLe680X24 24 ns

tPLH OEB0 thru OEB3

DB S1 eX, S0 eH, RLe680X24 24 ns

tPHL OEB0 thru OEB3

DB S1 eX, S0 eH, RLe680X24 24 ns

²All typical values are at VCC e5V, TAea

25§C.

DP8404 Switching Characteristics, VCC e4.5V to 5.5V, CLe50 pF, TAeMin to Max

Symbol From To Test Conditions Military Commercial Units

(Input) (Output) Min Typ²Max Min Typ²Max

tpd DB and CB ERR S1 eH, S0 eL, RLe500X26 26 ns

S1 eL, S0 eH, RLe500X26 26

tpd DB and CB MERR S1 eH, S0 eL, RLe500X40 40 ns

S1 eL, S0 eH, RLe500X40 40

tpd S0

and S1

CB R1 eR2 e500X35 35 ns

tpd DB CB S1 eL, S0 eL, R1 eR2 e500X35 35 ns

tpd S1

CB S0 eH, R1 eR2 e500X35 35 ns

ten OECB

CB S1 eX, S0 eH, R1 eR2 e500X18 18 ns

tdis OECB

CB S1 eX, S0 eH, R1 eR2 e500X18 18 ns

ten OECB

DB S1 eX, S0 eH, R1 eR2 e500X18 18 ns

tdis OECB

DB S1 eX, S0 eH, R1 eR2 e500X18 18 ns

DP8405 Switching Characteristics, VCC e4.5V to 5.5V, CLe50 pF, TAeMin to Max

Symbol From To Test Conditions Military Commercial Units

(Input) (Output) Min Typ²Max Min Typ²Max

tpd

DB and CB ERR S1 eH, S0 eL, RLe500X26 26 ns

DB ERR S1 eL, S0 eH, RLe500X26 26

tpd DB and CB MERR S1 eH, S0 eL, RLe500X40 40 ns

S1 eL, S0 eH, RLe500X40 40

tpd S0

and S1

CB RLe680X40 40 ns

tpd DB CB S1 eL, S0 eL, RLe680X40 40 ns

tpd S1

DB S0 eH, RLe680X40 40 ns

tPLH OECB

CB S1 eX, S0 eH, RLe500X24 24 ns

tPHL OECB

CB S1 eX, S0 eH, RLe680X24 24 ns

tPLH OEDB

DB S1 eX, S0 eH, RLe680X24 24 ns

tPHL OEDB

DB S1 eX, S0 eH, RLe680X24 24 ns

²All typical values are at VCC e5V, TAea

25§C.

Switching Waveforms

TL/F/8535–6

FIGURE 1. Read, Flag, and Correct Mode

TL/F/8535–7

FIGURE 2. Read, Correct Modify Mode

Switching Waveforms (Continued)

TL/F/8535–8

FIGURE 3. Diagnostic Mode

DP8402A Interfaced to the DP8418/19/28/29 System Diagram

TL/F/8535–9

DP8402A Interfaced to the DP8420A/21A/22A System Diagram

Tl/F/8535–12

Physical Dimensions inches (millimeters)

Hermetic Dual-In-Line (D)

Order Number DP8402AD or DP8403D

NS Package Number D52A

DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel

Error Detection and Correction Circuits (EDAC’s)

Physical Dimensions inches (millimeters) (Continued)

Lit. Ý103062

Plastic Chip Carrier (V)

Order Number DP8402AV

NS Package Number V68A

48 Lead Hermetic DIP (D)

Order Number DP8404D or DP8405D

NS Package Number D48A

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1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

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