32bit TX System RISC TX19 Family TMP19A44FDA/FE/F10XBG Rev1.3 01-Apr-2010 TMP19A44 Contents 1. Overview and Features 1-1 2. Pin Layout and Pin Functions 2-1 2.1 Pin Layout (Top view) 2.2 Pin Numbers and Names 2.3 Pin Names and Functions 2.4 Pin Names and Power Supply Pins 2.5 Pin Numbers and Power Supply Pins 2-1 2-2 2-3 2-11 2-11 3. Processor Core 3-1 3.1 Reset Operation 3-1 4-1 4. Memory Map 4-1 4.1 Memory Map 4-1 4-2 4-3 4.1.1 TMP19A44F10XBG 4.1.2 TMP19A44FEXBG 4.1.3 TMP19A44FDAXBG 4-3 4.2 Internal RAM 5. Clock/Standby Control (CG) 5-1 5-3 5.1 Clock System Block Diagram 5-3 5.1.1 Main System Clock 5-4 5-5 5.2 Clock Gear 5.3 CG Registers 5-5 5-6 5-7 5-8 5-9 5-10 5.3.1 System Control Registers 5.3.2 Oscillator Control Register 5.3.3 Standby Control Register 5.3.4 PLL Select Register 5.3.5 System Clock Select Register 5.3.6 Reset Flag Register 5-11 5.4 System Clock Controller 5.4.1 Initial Values after Reset 5.4.2 Oscillation Stabilization Time 5.4.3 System Clock Pin Output Function 5.4.4 Reducing the Oscillator Driving Capability 5.5 Prescaler Clock Controller 5.6 Clock Multiplication Circuit (PLL) 5.7 Standby Controller 5.7.1 Standby Mode 5.7.2 CG Operations in Each Mode 5.7.3 Block Operations in Each Mode 5.7.4 Releasing the Standby State 5.7.5 STOP Mode 5.7.6 Recovery from the STOP or SLEEP Mode TMP19A44(rev1.3)-i 5-11 5-11 5-12 5-13 5-13 5-13 5-14 5-14 5-15 5-15 5-16 5-18 5-19 TMP19A44 6-1 6. Exceptions/Interrupts 6-2 6.1 Overview 6-2 6-3 6-4 6.1.1 Exceptions and Interrupts 6.1.2 Types 6.1.3 Process Flow 6.2 Reset Exception/ Non-maskable Interrupt (NMI) 6-12 6-12 6-13 6.2.1 Factors 6.2.2 Reset Exception/ NMI Handling 6-15 6.3 General Exceptions 6-15 6-16 6.3.1 Factors 6.3.2 General Exception Handling 6-18 6.4 Software Interrupt 6-18 6-20 6.4.1 Factors 6.4.2 Software Interrupt Handling 6-22 6.5 Hardware Interrupt 6-23 6-29 6.5.1 Interrupt Factors 6.5.2 Hardware Interrupt Handling 6-45 6.6 Registers 6-45 6-47 6-56 6-67 6.6.1 Register Map 6.6.2 CP0 Register 6.6.3 Clock Generator Register 6.6.4 Interrupt Controller Register 7-1 7. Input/Output Ports 7-2 7-4 7-6 7-9 7-14 7-19 7-24 7-30 7-33 7-36 7-41 7-45 7-51 7-57 7-64 7-66 7-69 7-71 7-74 7-78 7.1 Port 0 (P00 through P07) 7.2 Port 1 (P10 through P17) 7.3 Port 2 (P20 through P27) 7.4 Port 3 (P30 through P37) 7.5 Port 4 (P40 through P47) 7.6 Port 5 (P50 through P57) 7.7 Port 6 (P60 through P67) 7.8 Port 7 (P70 through P77) 7.9 Port 8 (P80 through P87) 7.10 Port 9 (P90 through P97) 7.11 Port A (PA0 through PA7) 7.12 Port B (PB0 to PB7) 7.13 Port C (PC0 to PC7) 7.14 Port D (PD0 to PD7) 7.15 Port E (PE0 through PE7) 7.16 Port F (PF0 through PF7) 7.17 Port G (PG0 through PG7) 7.18 Port H (PH0 through PH7) 7.19 Port I (PI0 through PI7) 7.20 Port J (PJ0 through PJ7) TMP19A44(rev1.3)-ii TMP19A44 8-1 8. External Bus Interface 8.1 Address and Data Pins 8.2 Data Format 8.3 External Bus Operations (Separate Bus Mode) 8.4 External Bus Operations (Multiplexed Bus Mode) 8.5 Bus Arbitration 9. The Chip Selector and Wait Controller 8-2 8-3 8-9 8-17 8-24 9-1 9-1 9.1 Specifying Address Spaces 9.1.1 Base and Mask Address Setting Registers 9.1.2 How to Define Start Addresses and Address Spaces 9.2 The Chip Selector and Wait Controller 9-1 9-4 9-7 10-1 10. DMA Controller (DMAC) 10-1 10-2 10.1 Features 10.2 Configuration 10.2.1 Internal Connections of the TMP19A44 10.2.2 DMAC Internal Blocks 10.2.3 Snoop Function 10-2 10-3 10-3 10-4 10.3 Registers 10.3.1 DMA Control Register (DCR) 10.3.2 Channel Control Registers (CCRn) 10.3.3 Request Select Register (RSR) 10.3.4 Channel Status Registers (CSRn) 10.3.5 Source Address Registers (SARn) 10.3.6 Destination Address Register (DARn) 10.3.7 Byte Count Registers (BCRn) 10.3.8 DMA Transfer Control Register (DTCRn) 10.3.9 Data Holding Register (DHR) 10-6 10-8 10-11 10-12 10-14 10-15 10-16 10-17 10-18 10-19 10.4 Functions 10-19 10-22 10-25 10-26 10-27 10.4.1 Overview 10.4.2 Transfer Request 10.4.3 Address Mode 10.4.4 Channel Operation 10.4.5 Order of Priority of Channels 10-28 10.5 Timing Diagrams 10.5.1 Dual Address Mode 10.5.2 DREQn-Initiated Transfer Mode 10-28 10-30 10-34 10.6 Case of Data Transfer 11. 16-bit Timer/Event Counters (TMRBs) 11.1 Block Diagram of Each Channel 11.2 Register Description 11-1 11-3 11-4 11-4 11.2.1 TMRB registers 11.3 Description of Operations for Each Circuit 11.3.1 Prescaler 11.3.2 Up-counter (UC0) and Time Up-counter Registers (TB0UC) 11.3.3 Timer Registers (TB0RG0, TB0RG1) 11.3.4 Capture Registers (TB0CP0, TB0CP1) 11.3.5 Capture TMP19A44(rev1.3)-iii 11-6 11-6 11-9 11-9 11-10 11-10 TMP19A44 11-10 11-10 11.3.6 Comparators (CP0, CP1) 11.3.7 Timer Flip-flop (TB0FF0) 11.4 Registers 11.5 Description of Operations for Each Mode 11.5.1 16-bit Interval Timer Mode 11.5.2 16-bit Event Counter Mode 11.5.3 16-bit PPG (Programmable Square Wave) Output Mode 11.5.4 Timer Synchronization Mode 11.6 Applications using the Capture Function 12. 32-bit Input Capture (TMRC) 12.1 TMRC Block Diagram 12.2 Description for Operations of Each Circuit 11-11 11-19 11-19 11-19 11-20 11-22 11-23 12-1 12-1 12-2 12-2 12-6 12-6 12-6 12-7 12-7 12.2.1 Prescaler 12.2.2 Noise Removal Circuit 12.2.3 32-bit Time Base Timer (TBT) 12.2.4 Edge Detection Circuit 12.2.5 32-bit Capture Register 12.2.6 32-bit Compare Register 12-8 12.3 Register Description 13 Two-phase Pulse Input Counter (PHCNT) 13-1 13-1 13-3 13-4 13-6 13.1 Overview 13.2 Block Diagram (PHCNT0) 13.3 Operation Mode 13.4 Registers 13.4.1 RUN register (PHCnRUN) 13.4.2 Control register (PHCnCR) 13.4.3 Timer Enable Register (PHCnEN) 13.4.4 Status register (PHCnFLG) 13.4.5 Compare register 0 (PHCnCMP0) 13.4.6 Compare register 1 (PHCnCMP1) 13.4.7 Counter Read Register (PHCnCNT) 13-6 13-7 13-8 13-9 13-10 13-10 13-11 13-12 13-12 13.5 Up-and-down counter 13.6 Interrupt 14-1 14. Serial Channel (SIO) 14-1 14.1 Features 14-1 14-2 14.1.1 Operation Modes 14.1.2 Data Format 14-3 14.2 Block Diagram (Channel 0) 14-4 14-8 14-8 14-8 14-8 14-10 14-10 14-12 14-12 14-14 14.2.1 Baud Rate Generator 14.2.2 Serial Clock Generation Circuit 14.2.3 Receive Counter 14.2.4 Receive Control Unit 14.2.5 Receive Buffer 14.2.6 Receive FIFO Buffer 14.2.7 Receive FIFO Operation 14.2.8 Transmit Counter 14.2.9 Transmit Control Unit 14.2.10 Transmit Buffer TMP19A44(rev1.3)-iv TMP19A44 14.2.11 Transmit FIFO Buffer 14.2.12 Transmit FIFO Operation 14.2.13 Parity Control Circuit 14.2.14 Error Flag 14.2.15 Direction of Data Transfer 14.2.16 Stop Bit Length 14.2.17 Status Flag 14.2.18 Configurations of Send/Receive Buffers 14.2.19 software reset 14.2.20 Signal Generation Timing 14-15 14-15 14-17 14-17 14-18 14-18 14-18 14-18 14-19 14-19 14-20 14.3 Register Description 14.3.1 Operation of Each Channel 14.3.2 Detailed Description of Registers 14.4 Operation of Each Circuit (Channel 0) 14-20 14-21 14-34 14-34 14-37 14.4.1 Prescaler 14.4.2 Serial Clock Generation Block 15-1 15. Serial Channel (HSIO) 15-1 15.1 Features 15-1 15-2 15.1.1 Operation Modes 15.1.2 Data Format 15.2 Block Diagram (Channel 0) 15.3 Register Description 15-3 15-4 15.3.1 Operation of Each Channel 15-4 15.4 Operation of Each Circuit (Channel 0) 15-33 15-33 15.4.1 Serial Clock Generation Block 16. Serial Bus Interface (SBI) 16.1 Configuration 16.2 Control 16.3 I2C Bus Mode Data Formats 16.4 Control Registers in the I2C Bus Mode 16.5 Control Registers in the I2C Bus Mode 16.5.1 Setting the Acknowledgement Mode 16.5.2 Setting the Number of Bits per Transfer 16.5.3 Serial Clock 16.5.4 Slave Addressing and Address Recognition Mode 16.5.5 Configuring the SBI as a Master or a Slave 16.5.6 Configuring the SBI as a Transmitter or a Receiver 16.5.7 Generating Start and Stop Conditions 16.5.8 Interrupt Service Request and Release 16.5.9 Serial Bus Interface Operating Modes 16.5.10 Lost-arbitration Detection Monitor 16.5.11 Slave Address Match Detection Monitor 16.5.12 General-call Detection Monitor 16.5.13 Last Received Bit Monitor 16.5.14 Software Reset 16.5.15 Serial Bus Interface Data Buffer Register (SBIDBR) 16.5.16 I2C Bus Address Register (I2CAR) 16.5.17 IDLE Setting Register (SBIBR0) 16.6 Data Transfer Procedure in the I2C Bus Mode TMP19A44(rev1.3)-v 16-1 16-1 16-2 16-2 16-3 16-11 16-11 16-11 16-11 16-12 16-12 16-13 16-13 16-14 16-14 16-14 16-15 16-15 16-15 16-16 16-16 16-16 16-16 16-17 TMP19A44 16.6.1 Device Initialization 16.6.2 Generating the Start Condition and a Slave Address 16.6.3 Transferring a Data Word 16.6.4 Generating the Stop Condition 16.6.5 Repeated Start Procedure 16.7 Control in the Clock-synchronous 8-bit SIO Mode 16-17 16-17 16-18 16-23 16-24 16-25 16-28 16-31 16.7.1 Serial Clock 16.7.2 Transfer Modes 17-1 17. Analog/Digital Converter 17-2 17.1 Control Register 17-2 17-5 17.1.1 Unit A, Unit B 17.1.2 Unit C 17-15 17-16 17.2 Conversion Clock 17.3 Description of Operations 17.3.1 Analog Reference Voltage 17.3.2 Selecting the Analog Input Channel 17.3.3 Starting A/D Conversion 17.3.4 A/D Conversion Modes and A/D Conversion Completion Interrupts 17.3.5 High-priority Conversion Mode 17.3.6 A/D Monitor Function 17.3.7 Storing and Reading A/D Conversion Results 17.3.8 Data Polling 18. Watchdog Timer (Runaway Detection Timer) 17-16 17-16 17-17 17-18 17-21 17-21 17-21 17-23 18-1 18-1 18-2 18-3 18.1 Configuration 18.2 Watchdog Timer Interrupt 18.3 Control Registers 18.3.1 Watchdog Timer Mode Register (WDMOD) 18.3.2 Watchdog Timer Control Register (WDCR) 18-3 18-3 18.4 Operation Description 18-5 19. Real Time Clock (RTC) 19-1 19-1 19-1 19-2 19.1 Functions 19.2 Block Diagram 19.3 Registers 19.3.1 Control Register 19.3.2 Detailed Description of Control Register 19-2 19-3 19-10 19.4 Operational description 19-10 19-13 19.4.1 Clock Operation 19.4.2 Alarm function 20-1 20. Key-on Wakeup Circuit 20.1 Outline 20.2 Key-on Wakeup Operation 20.3 Pull-up Function 20.4 Key Input Detection Timing 20.5 Detection of Key Input Interrupts and Clearance of Requests 20.6 Setting example TMP19A44(rev1.3)-vi 20-1 20-1 20-2 20-4 20-7 20-9 TMP19A44 21. ROM Correction Function 21-1 21.1 Features 21.2 Description of Operations 21.3 Registers 21-1 21-1 21-4 22. Table of Special Function Registers 1 Little-endian mode 2 Big-endian mode 22-1 22-2 22-28 23-1 23. JTAG Interface 23.1 Boundary Scan Overview 23.2 JTAG Interface Signals 23.3 JTAG Controller and Registers 23.3.1 Instruction Register 23.3.2 Bypass Register 23.3.3 Boundary Scan Register 23.3.4 Test Access Port (TAP) 23.3.5 TAP Controller 23.3.6 Controller Reset 23.3.7 State Transitions of the TAP Controller 23.4 Instructions Supported by the JTAG Controller Cells 23.4.1 EXTEST Instruction 23.4.2 SAMPLE and PRELOAD Instructions 23.4.3 BYPASS Instruction 23-1 23-2 23-3 23-3 23-4 23-5 23-5 23-6 23-6 23-7 23-11 23-11 23-12 23-13 23-13 23.5 Points to Note 24. Flash Memory Operation 24-1 24-1 24.1 Flash Memory 24.1.1 Features 24.1.2 Block Diagram of the Flash Memory Section 24-2 24-2 24-3 24.2 Operation Mode 24.2.1 Reset Operation 24.2.2 User Boot mode(Single chip mode) 24.2.3 Single Boot Mode 24.3 On-board Programming of Flash Memory (Rewrite/Erase) 24-4 24-5 24-12 24-29 24-29 24.3.1 Flash Memory 25. Various protecting functions 25.1 Overview 25.2 Features 25.3 Protecting Functions 25.4 Definition of operations/ terms 25.5 Registers TMP19A44(rev1.3)-vii 25-1 25-1 25-1 25-1 25-5 25-6 TMP19A44 26-1 26. Backup module 26-1 26-1 26-1 26-2 26-3 26.1 Features 26.2 Overview 26.3 Operation in Backup Mode 26.4 Block Diagram 26.5 Registers 26-3 26-4 26.5.1 Standby Control Register 26.5.2 Reset Flag Register 26-5 26-6 26.6 Return Circuit 26.7 Transition flowchart 27. Electrical Characteristics 27.1 Absolute Maximum Ratings 27.2 DC ELECTRICAL CHARACTERISTICS (1/3) 27.3 DC ELECTRICAL CHARACTERISTICS (2/3) 27.4 DC ELECTRICAL CHARACTERISTICS (3/3) 27.5 10-bit ADC Electrical Characteristics 27.6 AC Electrical Characteristic 27-1 27-1 27-2 27-3 27-3 27-5 27-6 27-6 27-13 27.6.1 Separate Bus mode 27.6.2 Multiplex Bus mode 27.7 Transfer with DMA Request 27.8 Serial Channel Timing 27.9 High Speed Serial Channel Timing 27.10 SBI Timing 27.11 Event Counter 27.12 Timer Capture 27.13 General Interrupts 27.14 STOP /SLEEP/SLOW Wake-up Interrupts 27.15 SCOUT Pin 27.16 Bus Request and Bus Acknowledge Signals 27.17 KWUP Input 27.18 Dual Pulse Input 27.19 ADTRG input 27.20 EJTAG 27-22 27-23 27-24 27-25 27-27 27-27 27-27 27-27 27-27 27-28 27-29 27-29 27-29 27-30 28-1 28. PKG TMP19A44(rev1.3)-viii TMP19A44 32-bit RISC Microprocessor - TX19 Family TMP19A44F10XBG/FEXBG /FDAXBG 1. Overview and Features The TX19 family is a high-performance 32-bit RISC processor series that TOSHIBA originally developed by integrating the MIPS16TMASE (Application Specific Extension), which is an extended instruction set of high code efficiency. TMP19A44 is a 32-bit RISC microprocessor with a TX19A/H1 processor core and various peripheral functions integrated into one package. It can operate at low voltage with low power consumption. Features of TMP19A44 are as follows: (1) TX19A/H1 processor core (refer to the separate volume "19A/ H1 Architecture" for details. 1) 2) Improved code efficiency and operating performance have been realized through the use of two ISA (Instruction Set Architecture) modes - 16- and 32-bit ISA modes. * The 16-bit ISA mode instructions are compatible with the MIPS16TMASE instructions of superior code efficiency at the object level. * The 32-bit ISA mode instructions are compatible with the TX39 instructions of superior operating performance at the object level. Both high performance and low power dissipation have been achieved. z High performance * Almost all instructions can be executed with one clock. * High performance is possible via a three-operand operation instruction. * 3-stage pipeline * Built-in high-speed memory * DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock. * On-board floating-point unit (FPU) z Low power consumption 3) * Optimized design using a low power consumption library * Standby function that stops the operation of the processor core High-speed interrupt response suitable for real-time control * Independency of the entry address * Automatic generation of factor-specific vector addresses * Automatic update of interrupt mask levels Overview and Features TMP19A44 (rev1.3) 1-1 2010-04-01 TMP19A44 * (2) Internal program memory and data memory Product name Built-in Flash ROM TMP19A44F10XBG 1024Kbyte Built-in RAM * Backup Ram 64Kbyte (16K) TMP19A44FEXBG 768Kbyte 64Kbyte TMP19A44FDAXBG 512Kbyte 32Kbyte (16K) (8K) *: Includes back-up RAM. * ROM correction function: 8 word x 12 blocks (3) External memory expansion * Expandable to 16 megabytes (for both programs and data) * External data bus: Separate bus/ multiplexed bus Chip select/wait controller (4) DMA controller : Coexistence of 8- and 16-bit widths is possible. : 4 channels : 8 channels (8 interrupt factors) * Activated by an interrupt or software * Data to be transferred to internal memory, internal I/O, external memory, and external I/O (5) 16-bit timer : 18 channels * 16-bit interval timer mode * 16-bit event counter mode * 16-bit PPG output (every 4 channels, synchronous outputs are possible) * Input capture mode * 2-phase pulse input counter function (4 channels assigned to perform this function): Multiplicationby-4 mode (6) 2-phase pulse input counter * : 6 channels Interrupt function (quadruple/ normal/ compare). Counting available in normal and stop modes Overview and Features TMP19A44 (rev1.3) 1-2 2010-04-01 TMP19A44 (7) 32-bit timer * 32-bit input capture register : 4 channels * 32-bit compare register : 8 channels * 32-bit time base timer : 1 channel (8) Real time clock (RTC) : 1 channel * Clock (hour, minute and second) * Calendar (Month, week, date and leap year) * Time correction or 30 seconds (by software) * Alarm (Alarm output) * Alarm interrupt (9) Watchdog timer * : 1 channel 26-stage binary counter (10) General-purpose serial interface * Selectable between the UART mode and the synchronization mode (with 4-byte FIFO) (11) High-speed serial interface * : 3 channels Selectable between the UART mode and the high-speed synchronization mode (with 32 byte FIFO) (12) Serial bus interface * : 3 channels : 1 channel 2 Selectable between the I C bus mode and the clock synchronization mode (13) 10-bit A/D converter (with S/H) : 16 channels * Start by an external trigger, and the internal timer activated by a trigger * Fixed channel/scan mode * Single/repeat mode * Top-priority conversion mode * AD monitor function: 6 channels (2ch for each unit) * Conversion time 1.15 sec(@ 40/ 80MHz) * 3 units: 4ch, 4ch, 8ch * Synchronous start of 2 units: available by external trigger (14) Key-on wakeup * : 32 channels Dynamic pull-up (15) Interrupt function * CPU: 2 factors ................... software interrupt instruction * Internal: 68 factors............. The order of precedence can be set over 7 levels (except for the watchdog timer interrupt). * External: 64 factors .......... The order of precedence can be set over 7 levels. Because 32 factors are associated with KWUP, the number of interrupt factors is one. (16) Input and output ports ............... 160 terminals (17) Standby function * Four standby modes (IDLE, SLEEP, STOP and BACKUP SLEEP, BACKUP STOP) * Sub clock: Slow, sleep and backup modes (32.768kHz) Overview and Features TMP19A44 (rev1.3) 1-3 2010-04-01 TMP19A44 (18) Clock generator * Built-in PLL (multiplied by 8) * Clock gear function: The high-speed clock can be divided into 8/8, 4/8, 2/8, 1/8, or 1/16. * T0: fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 (19) Endian: Bi-endian (big-endian/little-endian) (20) Maximum operating frequency * 80 MHz (PLL multiplied by 8) (21) Operating voltage range * Regulator equipped, single power supply, 2.7-3.6V input. * I/O and ADC: 2.7 V to 3.6 V (22) Temperature range * -20~85 degrees (operating range) * 0~70 degrees (during Flash writing/ erasing) (23) Package P-FBGA241-1212-0.65 (12 mm x 12 mm, 0.65 mm pitch) (24) Backup mode Enable to operate: * RAM 16/ 8KB * I/O * 2-phase counter: 6 channels * KWUP (with dynamic pull-up): 32 channels * External interrupt INT * Clock count Overview and Features TMP19A44 (rev1.3) 1-4 2010-04-01 TMP19A44 TX19 Processor Core TX19A/H1 CPU MAC/FPU EJTAG 1024/768/512Kbyte Flash ROM 48/48/24Kbyte RAM Clock Generator (CG) DMAC (8ch) INTC External bus interface HSIO/UART (3ch) GBUS RAM 16/16/8Kbyte KWUP (32ch) RTC (with calendar) 2-phase pulse input PHCNT (6ch) I/O bus interface (32bit) PORT0 to PORT6 (also function as external bus I/F) 16-bit TMRB 0 to 11(18ch) SIO/UART 0 to 2 (3ch) PORT7 to PORT8 (also function to receive ADC inputs) I2C/SIO (1ch) 10-bit ADC (4ch) 10-bit ADC (4ch) PORT9 to PORTJ (also function as functional pins) 10-bit ADC (8ch) WDT 32-bit TMRC TBT (1ch) CAP (4ch) CMP (8ch) Fig. 1-1 TMP19A44 Block Diagram Overview and Features TMP19A44 (rev1.3) 1-5 2010-04-01 TMP19A44 2. Pin Layout and Pin Functions This section shows the pin layout of TMP19A44 and describes the names and functions of input and output pins. 2.1 Pin Layout (Top view) Fig. 2-1 shows the pin layout of TMP19A44. A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 A11 A12 A13 A14 A15 A16 A17 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 E1 D2 E2 D3 E3 D4 E4 D5 E5 D6 E6 D7 E7 D8 E8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 G1 H1 J1 K1 L1 M1 G2 H2 J2 K2 L2 M2 G3 H3 J3 K3 L3 M3 G4 H4 J4 K4 L4 M4 G5 H5 J5 K5 L5 M5 N1 P1 R1 T1 U1 N2 P2 R2 T2 U2 N3 P3 R3 T3 U3 N4 P4 R4 T4 U4 N5 P5 R5 T5 U5 F13 F14 F15 F16 F17 G13 H13 J13 K13 L13 M13 N6 P6 R6 T6 U6 N7 P7 R7 T7 U7 N8 P8 R8 T8 U8 G14 H14 J14 K14 L14 M14 G15 H15 J15 K15 L15 M15 G16 H16 J16 K16 L16 M16 G17 H17 J17 K17 L17 M17 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 R9 R10 R11 R12 R13 R14 T9 T10 T11 T12 T13 T14 U9 U10 U11 U12 U13 U14 N15 P15 R15 T15 U15 N16 P16 R16 T16 U16 N17 P17 R17 T17 U17 Fig. 2-1 Pin Layout (P-FBGA193) Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-1 2010-04-01 TMP19A44 2.2 Pin Numbers and Names Table 2-1 shows the pin numbers and names of TMP19A44. Table 2-1 Pin numbers and names Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name A1 NC C15 DVSS G1 VREFLB L16 PJ6/INT6 R3 TEST0 A2 P84/AINC4 C16 PH5/INT1D/TBBIN1 G2 AVSSB L17 PJ5/INT17 R4 P02/D2/AD2 A3 P81/AINC1 C17 TDI/RXD0 G3 DVSS M1 PC0/TBTIN/KEY30 R5 P05/D5/AD5 A4 P83/AINC3 D1 P73/INT11/AINA3 G4 P90/HTXD0 M2 PC1/TCOUT0 R6 P10/D8/AD8/A8 A5 VREFHC D2 P72/INT10/AINA2 G5 NC M3 PC2/TCOUT1 R7 P14/D12/AD12/A12 A6 PF3/KEY19/DACK4 D3 P70/AINA0 G13 NC M4 PC3/TCOUT2 R8 P20/A16/A0/TB1IN0 A7 PE6/KEY14 D4 AVSSC G14 PI4/ADTRGC M5 NC R9 P23/A19/A3/TB2IN1 A8 PE1/KEY09 D5 DVSS G15 PI3/PHC5IN1 M13 DVCC3 R10 P27/A23/A7/TB5IN1 A9 PD4/TBCOUT D6 PF6/KEY22/TCOUT6 G16 PI2/PHC5IN0 M14 PJ4/INT16 R11 P42/CS2/KEY26 A10 PD0/HTXD2 D7 PF1/KEY17/DACK0 G17 DINT M15 PJ3/INT15 R12 P45/BUSMD A11 PA4/INT4/TB6IN0 D8 PE4/KEY12 H1 DVCC3 M16 PJ2/INT14 R13 P50/A0/INTC A12 BVCC3 D9 PD7/ADTRGB H2 P91/HRXD0 M17 PJ1/TB11IN1 R14 P53/A3/INTF A13 XT2 D10 PD3/TBBOUT H3 P92/HSCLK0/HCTS0 N1 PC4/SO/SDA R15 TEST3 A14 XT1 D11 PA7/PHC2IN1 H4 P93/TB9OUT N2 PC5/SI/SCL R16 P61/A9/RXD0/INTA A15 X2 D12 PA3/INT3/PHC1IN1 H5 NC N3 PC6/SCK R17 P60/A8/TXD0 A16 X1 D13 PH4/INT1C/TBBIN0 H13 NC N4 DVCC3 T1 P34/BUSRQ/TBEOUT A17 NC D14 TEST4 H14 NC N5 DVSS T2 TEST1 B1 P85/AINC5 D15 PH3/INT1B/TBAIN1 H15 PI1/PHC4IN1 N6 NC T3 P36/RW/TC2IN B2 VREFLC D16 RESET H16 PI0/PHC4IN0 N7 NC T4 P01/D1/AD1 B3 P82/AINC2 D17 TDO/TXD0 H17 EJE N8 NC T5 P04/D4/AD4 B4 P80/AINC0 E1 P75/AINB1 J1 P94/TXD2 N9 DVSS T6 P07/D7/AD7 B5 AVCC3C E2 P74/AINB0 J2 P95/RXD2 N10 NC T7 P13/D11/AD11/A11 B6 PF4/KEY20/TCOUT4 E3 AVCC3B J3 P96/SCLK2/CTS2 N11 NC T8 P17/D15/AD15/A15 B7 PE7/KEY15 E4 AVCC3A J4 P97/TBAOUT N12 REGTEST3 T9 P22/A18/A2/TB2IN0 B8 PE2/KEY10 E5 VREFLA J5 DVCC3 N13 DVSS T10 P26/A22/A6/TB5IN0 B9 PD5/TBDOUT E6 PF7/KEY23/TCOUT7 J13 DVCC3 N14 PJ0/TB11IN0 T11 P41/CS1/KEY25 B10 PD2/HSCLK2/HCTS2 E7 PF2/KEY18/DREQ4 J14 PG7/KEY07 N15 P67/A15/TB5OUT T12 P44/SCOUT B11 PA5/INT5/TB6IN1 E8 PE5/KEY13 J15 PG6/KEY06 N16 P66/A14/SCLK1/CTS1 T13 P47/TBFOUT B12 PA1/INT1/PHC0IN1 E9 PE0/KEY08 J16 PG5/KEY05 N17 P65/A13/RXD1/INTB T14 P52/A2/INTE B13 PA0/INT0/PHC0IN0 E10 DVSS J17 DVCC3 P1 P30/RD T15 P55/A5/TB1OUT B14 DVCC3 E11 REGTEST0 K1 PB2/TB6OUT P2 P31/WR T16 DVSS B15 REGTEST2 E12 DVCC3 K2 PB4/HTXD1 P3 PC7/TCOUT3 T17 P57/A7/TB3OUT/KEY29 B16 CVSS E13 DVSS K3 PB3/TB7OUT P4 DVSS U1 NC B17 TRST E14 PH2/INT1A/TBAIN0 K4 PB1/PHC3IN1 P5 DVCC3 U2 P35/BUSAK/TC1IN C1 P86/AINC6/INT8 E15 PH1/INT19/TB9IN1 K5 NC P6 P11/D9/AD9/A9 U3 P37/ALE/TC3IN C2 P71/AINA1 E16 PH0/INT18/TB9IN0 K13 NC P7 P15/D13/AD13/A13 U4 P00/D0/AD0 C3 AVSSA E17 TMS K14 PG4/KEY04 P8 P21/A17/A1/TB1IN1 U5 P03/D3/AD3 C4 P87/AINC7/INT9 F1 P77/AINB3/INT13 K15 PG3/KEY03 P9 P24/A20/A4/TB3IN0 U6 P06/D6/AD6 C5 DVCC3 F2 P76/AINB2/INT12 K16 PG2/KEY02 P10 DVCC3 U7 P12/D10/AD10/A10 C6 PF5/KEY21/TCOUT5 F3 VREFHB K17 PG1/KEY01 P11 DVCC3 U8 P16/D14/AD14/A14 C7 PF0/KEY16/DREQ0 F4 VREFHA L1 PB5/HRXD1 P12 BOOT U9 DVSS C8 PE3/KEY11 F5 NC L2 PB7/TB8OUT P13 REGTEST1 U10 P25/A21/A5/TB3IN1 C9 PD6/KEY31/ADTRGA F6 NC L3 PB6/HSCLK1/HCTS1 P14 TEST2 U11 P40/CS0/KEY24 C10 PD1/HRXD2 F13 NC L4 PB0/PHC3IN0 P15 P64/A12/TXD1 U12 P43/CS3/KEY27 C11 PA6/PHC2IN0 F14 PI7/ADTRGSNC L5 NC P16 P63/A11/TB4OUT U13 P46/ENDIAN C12 PA2/INT2/PHC1IN0 F15 PI6/TB11OUT L13 NC P17 P62/A10/SCLK0/CTS0 U14 P51/A1/INTD C13 PH7/INT1F/TBDIN1 F16 PI5/TB10OUT L14 PG0/KEY00 R1 P32/HWR/TC0IN U15 P54/A4/TB0OUT C14 PH6/INT1E/TBDIN0 F17 TCK L15 PJ7/INT7 R2 P33/WAIT/RDY U16 P56/A6/TB2OUT/KEY28 U17 NC Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-2 2010-04-01 TMP19A44 2.3 Pin Names and Functions Table 2-2 through Table 2-9 show the names and functions of input and output pins. Table 2-2 Pin names and functions (1/8) Pin name P00~P07 No. of pins 8 D0~D7 AD0~D7 P10~P17 D8~D15 AD8~AD15 I/O I/O I/O 8 A8~A15 P20~P27 Input/ output I/O I/O I/O O 8 A16~A23 A0~A7 I/O TB1IN0,TB1IN1 O O I TB2IN0,TB2IN1 I TB3IN0,TB3IN1 I TB5IN0,TB5IN1 I P30 P-up Port 1: Input/output port that allows input/output to be set in units of bits Data (upper): Data bus 8 to 15 (separate bus mode) Address data (upper): Address data bus 8 to 15 (multiplexed bus mode) Address: Address bus 8 to 15 (multiplexed bus mode) P-up Port 2: Input/output port that allows input/output to be set in units of bits Address: Address bus 15 to 23 (separate bus mode) Address: Address bus 0 to 7 (multiplexed bus mode) 16-bit timer 1 input 0,1: For inputting the count/capture trigger of a 16-bit timer 1 16-bit timer 2 input 0,1: For inputting the count/capture trigger of a 16-bit timer 2 16-bit timer 3 input 0,1: For inputting the count/capture trigger of a 16-bit timer 3 16-bit timer 5 input 0,1: For inputting the count/capture trigger of a 16-bit timer 5 P-up 1 I/O O Port 31: Port used exclusively for output Write: Strobe signal for writing data of D0 to D7 pins P-up 1 I/O O P-up I Port 32: Input/output port Write upper-pin data: Strobe signal for writing data of D8 to D15 pins For inputting the capture trigger for 32-bit timer I/O I I Port 33: Input/output port Wait: Pin for requesting CPU to put a bus in a wait state Ready: Pin for notifying CPU that a bus is ready P-up HWR TC0IN P33 Port 0: Input/output port that allows input/output to be set in units of bits Data (lower): Data bus 0 to 7 (separate bus mode) Address data (lower): Address data bus 0 to 7 (multiplexed bus mode) I/O O WR P32 1 WAIT RDY BUSRQ TBEOUT O Port 34: Input/output port Bus request: Signal requesting CPU to allow an external master to take the bus control authority 16-bit timer E output: Pin for outputting 16-bit timer E I/O O Port 35: Input/output port Bus acknowledge: Signal notifying that CPU has released the P35 1 Port 30: Port used exclusively for output RD Output Read: Strobe signal for reading external memory I/O I P34 Programma ble Pull up/ Pull down 1 RD P31 Function 1 BUSAK bus control authority in response to BUSRQ P-up P-up For inputting the capture trigger for 32-bit timer R/W I/O O P-up TC2IN I Port 36: Input/output port Read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle. For inputting the capture trigger for 32-bit timer Port 37: Input/output port Address latch enable (address latch is enabled only if access to external memory (multiplexed bus mode) is taking place). For inputting the capture trigger for 32-bit timer P-up P36 P37 ALE TC3IN 1 1 I/O O I Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-3 Programma ble Open Drain Output P-up I TC1IN Schmitt trigger 2010-04-01 TMP19A44 Table 2-3 Pin names and functions (2/8) Pin name P40 No. of pins CS0 I/O O KEY24 I P41 1 Input/ output CS1 I/O O KEY25 I P42 1 CS2 I/O O KEY26 I P43 1 P46 ENDIAN 1 P47 TBFOUT P50~P53 1 4 A0~A3 INTC~INTF P54,P55 A4,A5 TB0OUT TB1OUT P56,P57 A6,A7 TB2OUT TB3OUT KEY28,KEY29 Port 41: Input/output port Chip select 1: "0" is output if the address is in a designated address area. KEY on wake up input 25: (Dynamic pull up is selectable) P-up filter I/O I Port 45: Input/output port Pin for setting an external bus mode: This pin functions as a multiplexed bus by sampling the "H (DVCC3) level" at the rise of a reset signal. It also functions as a separate bus by sampling "L" at the rise of a reset signal. When performing a reset operation, pull it up or down according to a bus mode to be used. Input with Schmitt trigger. (After a reset operation is performed, it can be used as a port.) P-up Port 46: Input/output port This pin is used to set a mode. It performs a big-endian operation by sampling the "H (DVCC3) level" at the rise of a reset signal, and performs a little-endian operation by sampling "L" at the rise of a reset signal. When performing a reset operation, pull it up or down according to the type of endian to be used. (After a reset operation is performed, it can be used as a port.) P-up Port 5: Input/output port that allows input/output to be set in units of bits Address: Address buses 0 to 3 (separate bus mode) Interrupt request pins C to F: Selectable between "H" level, "L" level, rising edge, and falling edge P-up Port 5: Input/output port that allows input/output to be set in units of bits Address: Address buses 4 and 5 (separate bus mode) 16-bit timer 0 output: Pin for outputting a 16-bit timer 0 16-bit timer 1 output: Pin for outputting a 16-bit timer 1 P-up Port 5: Input/output port that allows input/output to be set in units of bits Address: Address buses 6 and 7 (separate bus mode) 16-bit timer 2 output: Pin for outputting a 16-bit timer 2 16-bit timer 3 output: Pin for outputting a 16-bit timer 3 KEY on wake up input 28 and 29: (Dynamic pull up is selectable) P-up TMP19A44 (rev1.3) 2-4 w/ noise filter I/O Pin Layout and Pin Functions w/ noise filter P-up O O O I w/ noise filter Port 47: Input/output port 16-bit timer F output: Pin for outputting a 16-bit timer F I/O w/ noise filter I/O O I/O w/ noise filter P-up I/O I Programma ble Open Drain Output Port 44: Input/output port System clock output: Selectable between high- and low-speed clock outputs, as in the case of CPU O O O 2 w/ noise I/O O O I 2 P-up P-up I 1 Port 40: Input/output port Chip select 0: "0" is output if the address is in a designated address area. KEY on wake up input 24: (Dynamic pull up is selectable) Port 43: Input/output port Chip select 3: "0" is output if the address is in a designated address area. KEY on wake up input 27: (Dynamic pull up is selectable) KEY27 P45 BUSMD Schmitt trigger P-up CS3 1 Programma ble Pull up/ Pull down Port 42: Input/output port Chip select 2: "0" is output if the address is in a designated address area. KEY on wake up input 26: (Dynamic pull up is selectable) I/O O P44 SCOUT 1 Function w/ noise filter w/ noise filter 2010-04-01 TMP19A44 Table 2-4 Pin names and functions (3/8) Pin name No. of pins P60 A8 TXD0 1 P61 A9 RXD0 INTA 1 P62 A10 SCLK0 CTS0 1 P63 1 A11 TB4OUT P64 A12 TXD1 1 P65 A13 RXD1 INTB 1 P66 A14 SCLK1 CTS1 1 P67 1 A15 TB5OUT Input/ output Function Programma ble Pull up/ Pull down I/O O O Port 60: Input/output port Address: Address bus 8 (separate bus mode) Sending serial data 0: Open drain output pin depending on the program used I/O O I I Port 61: Input/output port Address: Address bus 9 (separate bus mode) Receiving serial data 0 Interrupt request pin A: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. P-up I/O O I/O I Port 62: Input/output port Address: Address bus 10 (separate bus mode) Serial clock input/output 0 Handshake input pin Open drain output pin depending on the program used P-up I/O O O Port 63: Input/output port that allows input/output to be set in units of bits Address: Address bus 11 (separate bus mode) 16-bit timer 4 output: Pin for outputting a 16-bit timer 4 P-up I/O O O Port 64: Input/output port Address: Address bus 12 (separate bus mode) Sending serial data 1 P-up I/O O I I Port 65: Input/output port Address: Address bus 13 (separate bus mode) Receiving serial data 1 Interrupt request pin B: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. P-up I/O O I/O I Port 6: Input/output port Address: Address buses 14 (separate bus mode) Serial clock input/output 1 Handshake input pin P-up I/O O O Port 67: Input/output port that allows input/output to be set in units of bits Address: Address buses 15 (separate bus mode) 16-bit timer 5 output: Pin for outputting a 16-bit timer 5 P-up P72,P73 AINA2,AINA3 INT10,11 2 I I I Port 7: Port used exclusively for input Analog input: Input from A/D converter (unit A) Interrupt request pins 10 and 11: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. P-up w/ noise w/ noise filter P74,P75 AINB0,AINB1 2 I I Port 7: Port used exclusively for input Analog input: Input from A/D converter (unit B) P-up P76,P77 AINB2,AINB3 INT12,13 2 I I I Port 7: Port used exclusively for input Analog input: Input from A/D converter (unit B) Interrupt request pins 12 and 13: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. P-up TMP19A44 (rev1.3) 2-5 filter P-up Pin Layout and Pin Functions Port 7: Port used exclusively for input Analog input: Input from A/D converter (unit A) Port 8: Port used exclusively for input Analog input: Input from A/D converter (unit C) w/ noise filter I I I I 2 6 Programma ble Open Drain Output P-up P70,P71 AINA0,AINA1 P80~P85 AINC0~ AINC5 Schmitt trigger w/ noise filter P-up 2010-04-01 TMP19A44 Table 2-5 Pin names and functions (4/8) Pin name P86,P87 No. of pins 2 AINC6,AINC7 Input/ output Function I Port 8: Port used exclusively for input I Analog input: Input from A/D converter (unit C) INT8,9 Interrupt request pins 8 and 9: Selectable between "H" level, "L" level, Programma ble Pull up/ Pull down Schmitt trigger P-up w/ noise Programma ble Open Drain Output filter rising edge, falling edge, and both rising and falling edges. P90 1 HTXD0 P91 I/O O 1 HRXD0 I/O I Port 90: Input/output port Sending serial data 0 at high speeds Port 91: Input/output port Receiving serial data 0 at high speeds P-up P-up w/ noise filter P92 I/O Port 91: Input/output port HSCLK0 I/O High-speed serial clock input/output 0 HCTS0 I Handshake input pin I/O Port 93: Input/output port that allows input/output to be set in units of P93 1 1 P-up bits TB9OUT P94 O 1 TXD2 P95 I/O O 1 RXD2 I/O I P-up 16-bit timer 9 output: Pin for outputting a 16-bit timer 9 Port 94: Input/output port Sending serial data 2 Port 95: Input/output port Receiving serial data 2 P-up P-up w/ noise filter P96 I/O Port 96: Input/output port SCLK2 I/O Serial clock input/output 2 CTS2 I Handshake input pin I/O Port 97: Input/output port that allows input/output to be set in units of O bits P97 1 1 TBAOUT P-up P-up 16-bit timer A output: Pin for outputting a 16-bit timer A PA0 I/O Port A0: Input/output port PHC0IN0 1 I 2-phase pulse input counter 0 input 0 INT0 I Interrupt request pin 0: Selectable between "H" level, "L" level, rising P-up w/ noise filter edge, falling edge, and both rising and falling edges. PA1 I/O Port A1: Input/output port PHC0IN1 1 I 2-phase pulse input counter 0 input 1 INT1 I Interrupt request pin 1: Selectable between "H" level, "L" level, rising P-up w/ noise filter edge, falling edge, and both rising and falling edges. PA2 I/O Port A2: Input/output port PHC1IN0 1 I 2-phase pulse input counter 1 input 0 INT2 I Interrupt request pin 0: Selectable between "H" level, "L" level, rising P-up w/ noise filter edge, falling edge, and both rising and falling edges. PA3 I/O Port A3: Input/output port PHC1IN1 1 I 2-phase pulse input counter 1 input 1 INT3 I Interrupt request pin 1: Selectable between "H" level, "L" level, rising P-up w/ noise filter edge, falling edge, and both rising and falling edges. PA4 1 TB6IN0 I/O Port A4: Input/output port I 16-bit timer 6 input 0: For inputting the capture trigger of a 16-bit timer 6 Interrupt request pin 0: Selectable between "H" level, "L" level, rising INT4 PA5 1 TB6IN1 I edge, falling edge, and both rising and falling edges. I/O Port A5: Input/output port I 16-bit timer 6 input 1: For inputting the capture trigger of a 16-bit timer 6 Interrupt request pin 1: Selectable between "H" level, "L" level, rising INT5 PA6 1 PHC2IN0 PA7 PHC2IN1 1 I edge, falling edge, and both rising and falling edges. I/O Port A6: Input/output port I 2-phase pulse input counter 2 input 0 I/O Port A7: Input/output port I 2-phase pulse input counter 2 input 1 Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-6 P-up w/ noise filter P-up w/ noise filter P-up P-up 2010-04-01 TMP19A44 Table 2-6 Pin names and functions (5/8) Pin name PB0 No. of pins 1 Input/ output I/O PHC3IN0 Function Programma ble Pull up/ Pull down Schmitt trigger P-up w/ noise Port B0: Input/output port I 2-phase pulse input counter 3 input 0 I/O Port B1: Input/output port I 2-phase pulse input counter 3 input 1 Programma ble Open Drain Output filter PB1 1 PHC3IN1 P-up w/ noise filter PB2,PB3 2 I/O Port B: Input/output port that allows input/output to be set in units of bits 16-bit timer 6 output: Pin for outputting a 16-bit timer 6 TB6OUT O TB7OUT O PB4 1 I/O HTXD1 PB5 O 1 I/O HRXD1 I 16-bit timer 7 output: Pin for outputting a 16-bit timer 7 Port B4: Input/output port Sending serial data 1 at high speeds P-up Port B5: Input/output port Receiving serial data 0 at high speeds P-up P-up w/ noise filter PB6 I/O Port B6: Input/output port HSCLK1 I/O Sending/ receiving serial data 1 at high speeds HCTS1 I Handshake input pin I/O Port B: Input/output port that allows input/output to be set in units of bits PB7 1 1 16-bit timer 8 output: Pin for outputting a 16-bit timer 8 TB8OUT PC0 P-up P-up O 1 TBTIN I/O Port C0: Input/output port I 32-bit time base timer input: For inputting a 32-bit time base timer KEY on wake up input 30: (Dynamic pull up is selectable) P-up w/ noise filter KEY30 PC1~PC3 3 I/O Port C: Input/output port that allows input/output to be set in units of bits Outputting 32-bit timer if the result of a comparison is a match O TCOUT0~ O TCOUT2 1 PC4 SO I/O Port C4: Input/output port O Pin for sending data if the serial bus interface operates in the SIO mode Pin for sending and receiving data if the serial bus interface operates in SDA PC5 P-up 1 SI I/O the I2C mode I/O Port C5: Input/output port I Pin for receiving data if the serial bus interface operates in the SIO w/ noise filter P-up mode I/O SCL P-up w/ noise filter Pin for inputting and outputting a clock if the serial bus interface operates in the I2C mode PC6 1 SCK I/O Port C6: Input/output port I/O Pin for inputting and outputting a clock if the serial bus interface P-up operates in the I2C mode PC7 1 I/O Port C: Input/output port that allows input/output to be set in units of bits Outputting 32-bit timer if the result of a comparison is a match TCOUT3 PD0 1 HTXD2 PD1 P-up O 1 HRXD2 I/O Port D0: Input/output port O Sending serial data 2 at high speeds I/O Port D1: Input/output port I receiving serial data 2 at high speeds I/O Port D2: Input/output port HSCLK2 I/O High-speed serial clock input/output 2 HCTS2 I Handshake input pin I/O Port D3 to D5: Input/output port that allows input/output to be set in units P-up P-up w/ noise filter PD2 PD3~PD5 1 3 of bits TBBOUT~ O 16-bit timer B/ C/ D output: Pin for outputting a 16-bit timer B/ C/ D P-up P-up TBDOUT Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-7 2010-04-01 TMP19A44 Table 2-7 Pin names and functions (6/8) Pin name No. of pins PD6 1 Input/ output I/O Function Programma ble Pull up/ Pull down Port D6: Input/output port that allows input/output to be set in units of P-up I Pin for starting A/D trigger or A/D converter (unit A) from an external w/ noise filter source KEY31 PD7 1 I KEY on wake up input 31: (Dynamic pull up is selectable) I/O Port D6: Input/output port that allows input/output to be set in units of P-up I w/ noise filter bits ADTRGB Programma ble Open Drain Output bits ADTRGA Schmitt trigger Pin for starting A/D trigger or A/D converter (unit B) from an external source PE0~PE7 8 I/O KEY on wake up input 08 to 15: (Dynamic pull up is selectable) KEY08~KEY15 PF0, PF2 Port E: Input/output port that allows input/output to be set in units of bits P-up filter I 2 I/O Port F: Input/output port that allows input/output to be set in units of bits DMA request signals 0 and 4: For inputting the request to transfer data DREQ0,4 I KEY16, KEY18 I by DMA from an external I/O device to DMAC0 or DMAC4 P-up 2 I/O Port F: Input/output port that allows input/output to be set in units of bits DMA request signals 0 and 4: For inputting the request to transfer data DACK0,4 O KEY17, KEY19 I by DMA from an external I/O device to DMAC0 or DMAC4 P-up 4 I/O Port F: Input/output port that allows input/output to be set in units of bits KEY on wake up input 20 to 23: (Dynamic pull up is selectable) KEY20~KEY23 I TCOUT4~TCOU O w/ noise filter KEY on wake up input 16 to 19: (Dynamic pull up is selectable) PF4-PF7 w/ noise filter KEY on wake up input 16 to 19: (Dynamic pull up is selectable) PF1, PF3 w/ noise Outputting 32-bit timer if the result of a comparison is a match P-up w/ noise filter T7 PG0~PG7 8 I/O KEY on wake up input 00 to 07: (Dynamic pull up is selectable) KEY00-KEY07 PH0~PH7 Port G: Input/output port that allows input/output to be set in units of bits P-up filter I 8 I/O w/ noise Port H: Input/output port that allows input/output to be set in units of bits Interrupt request pins 18 to 1F: Selectable between "H" level, "L" level, INT18~INT1F I TB9IN0, TB9IN1 I rising edge, falling edge, and both rising and falling edges 16-bit timer 9 input 0,1: For inputting the count/capture trigger of a 16-bit timer 9 16-bit timer A input 0,1: For inputting the count/capture trigger of a P-up filter 16-bit timer A TBAIN0,TBAIN1 I TBBIN0,TBBIN1 I TBDIN0,TBDIN1 I 16-bit timer D I/O Port I0: Input/output port w/ noise 16-bit timer B input 0,1: For inputting the count/capture trigger of a 16-bit timer B 16-bit timer D input 0,1: For inputting the count/capture trigger of a PI0 1 PHC4IN0 PI1 1 PHC4IN1 PI2 1 PHC5IN0 PI3 1 PHC5IN1 I 2-phase pulse input counter 4 input 0 I/O Port I1: Input/output port I 2-phase pulse input counter 4 input 1 I/O Port I2: Input/output port I 2-phase pulse input counter 5 input 0 I/O Port I3: Input/output port I 2-phase pulse input counter 5 input 1 I/O Port I4: Input/output port I Pin for starting A/D trigger or A/D converter from an external source P-up w/ noise filter P-up w/ noise filter P-up w/ noise filter P-up w/ noise filter PI4 ADTRGC 1 Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-8 P-up 2010-04-01 TMP19A44 Table 2-8 Pin names and functions (7/8) Pin name No. of pins PI5,6 TB10OUT TB11OUT 2 PI7 ADTRGSNC 1 PJ0,1 2 TB11IN0,TB11I Input/ output EJE 6 1 Programma ble Pull up/ Pull down I/O O O Port I5, I6: Input/output port 16-bit timer 10 output: Pin for outputting a 16-bit timer 10 16-bit timer 11 output: Pin for outputting a 16-bit timer 11 P-up I/O I Port I7: Input/output port Pin for starting A/D trigger or A/D converter from an external source P-up I/O I Port I5, I6: Input/output port 16-bit timer 11 input 0,1: For inputting the count/capture trigger of a 16-bit timer 11 P-up Port J2to J7 : Input/output port Interrupt request pins 6, 7 and 14 to 17: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges P-up EJTAG enable: Signal for DSU-ICE P-up N1 PJ2~PJ7 INT14-17,6,7 Function I/O I Schmitt trigger Programm able Open Drain Output w/ noise filter w/ noise filter w/ noise filter TCK SCLK 1 TMS 1 I I/O Test clock input: Signal for testing DSU-ICE Serial clock input/output P-up I Test mode select input: Signal for testing DSU-ICE P-up w/ noise filter DINT 1 I Signal for DSU-ICE P-up TDI RXD0 1 I I Test data input: Signal for DSU-ICE Receiving serial data 0 P-up TDO TXD0 1 O O Test data output: Signal for testing DSU-ICE Sending serial data 0 TRST 1 I Test data input: Signal for testing DSU-ICE RESET 1 I Reset: Initializing LSI P-down P-up w/ noise filter X1 1 I Pin for connecting a high-speed oscillator (X1: Input with Schmitt trigger) X2 1 O Pin for connecting a high-speed oscillator XT1 1 I Pin for connecting a low-speed oscillator (XT1: Input with Schmitt trigger) XT2 BOOT 1 1 O Pin for connecting a low-speed oscillator I Pin for setting a single boot mode: This pin goes into single boot mode by sampling "L" at the rise of a reset signal. It is used to overwrite internal flash memory. By sampling "H (DVCC3) level" at the rise of a reset signal, it performs a normal operation. This pin should be pulled up under normal operating conditions. Pull it up when resetting. VREFHA~C 3 I Pin (H) for supplying the A/D converter with a reference power supply Connect this pin to AVCCA3 to 3C if the A/D converter is not used. VREFLA~C 3 I Pin (L) for supplying the A/D converter with a reference power supply Connect this pin to GND if the A/D converter is not used. AVCC3A~C 3 Pin for supplying the A/D converter with a power supply. Connect it to a power supply even if the A/D converter is not used.(DVCC3) AVSSA~C 3 A/D converter GND pin (0 V). Connect this pin to GND even if the A/D converter is not used. Pin (L) for supplying the A/D converter with a reference power supply Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-9 P-up 2010-04-01 TMP19A44 Table 2-9 Pin names and functions (8/8) Pin name No. of pins Input/ output I Function TEST0 1 TEST1 1 TEST pin: Set to OPEN. TEST pin: Set to OPEN. TEST2 1 TEST pin: Set to OPEN. TEST3 1 TEST pin: Set to OPEN. (Please do not put the positive voltage.) TEST4 1 CVSS 1 I Oscillator GND pin (0 V) DVCC3 13 Power supply pin: 3 V power supply DVSS 11 Power supply pin: GND pin (0 V) NC 26 Non-connection pin Pin Layout and Pin Functions TEST pin: To be fixed to DVCC3 TMP19A44 (rev1.3) 2-10 Programma ble Pull up/ Pull down Schmitt trigger Programm able Open Drain Output 2010-04-01 TMP19A44 2.4 Pin Names and Power Supply Pins Table 2-10 Pin names and Power Supplies 2.5 Pin name P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P73 P74-P77 P80-P87 P90-P97 PA0-PA7 PB0-PB7 PC0-PC7 Power supply DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 AVCC3A AVCC3B AVCC3C DVCC3 DVCC3 DVCC3 DVCC3 PD0-PD7 DVCC3 PE0-PE7 DVCC3 Power supply DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 1.5V X1X2 (internally) XT1, XT2 DVCC3 Pin name PF0-PF7 PG0-PG7 PH0-PH7 PI0-PI7 PJ0-PJ7 EJE TRST TDI TDO TMS TCK DINT RESET BOOT Pin Numbers and Power Supply Pins Table 2-11 Pin Numbers and Power Supplies Power supply Pin number Voltage range A12, B14, C5, E12, H1, J5, J13, J17, DVCC3 M13, N4, P5, P10, P11 2.7V-3.6V AVCC3A E4 AVCC3B E3 AVCC3C B5 Pin Layout and Pin Functions TMP19A44 (rev1.3) 2-11 2010-04-01 TMP19A44 3. Processor Core The TMP19A44 has a high-performance 32-bit processor core (TX19A/H1 processor core). For information on the operations of this processor core, please refer to the "TX19A/H1 Architecture." This chapter describes the functions unique to the TMP19A44 that are not explained in that document. 3.1 Reset Operation 3.1.1 Initial state The internal circuits, register settings and pin status of the TMP19A44 are undefined right after the power-on. The state continues until the RESET pin receives low level input after all the power supply voltage is applied. 3.1.2 Operation As the precondition, ensure that an internal high-frequency oscillator provides stable oscillation while power supply voltage is in the operating range. To reset the TMP19A44, input RESET signal at low level "0" for a minimum duration of 12 system clocks (1.2ms with external 10MHz oscillator). 3.1.3 Cancellation When the reset is canceled, the system control coprocessor (CP0) and the internal I/O register of the TX19A/H1 processor core are initialized. Note that the clock gear enters 1/1 mode and the PLL multiplication circuit stops after canceling the reset. Therefore, setting for the PLL operation is required. After the reset exception handling is executed, the program branches off to the exception handler. The address to which the program branches off to (address where exception handling starts) is called an exception vector address. This exception vector address of a reset exception (for example, nonmaskable interrupt) is 0xBFC0_0000 (virtual address). The register of the internal I/O is initialized. The port pin (including the pin that can also be used by the internal I/O) is set to a general-purpose input or output port mode. (Note 1) Set the RESET pin to "0" before turning the power on. Perform the reset after the power supply voltage has stabilized sufficiently within the operating range. (Note 2) After turning the power on, make sure that the power supply voltage and oscillation have stabilized, wait for 500 s or longer, and perform the reset. (Note 3) In the FLASH program, the reset period of 0.5 uS or longer is required independently of the system clock. (Note 4) The reset operation can alter the internal RAM state, but does not alter data in the backup RAM except for backup RAM. Processor Core TMP19A44 (rev1.3) 3-1 2010-04-01 TMP19A44 4. Memory Map 4.1 Memory Map 4.1.1 TMP19A44F10XBG 0xFFFF FFFF Virtual address Physical address 16 MB reserved 16 MB reserved Kseg2 (1 GB) Kseg2 (cash enabled) Built-in RAM area 0xFFFF FFFF (48 KB) 0xFF00 0000 0xBFCF FFFF 0xBFC0 0000 0xA000 0000 Built-in RAM area 0xFFFF 4000 (16 KB) 0xFFFF 0000 Inaccessible 16 MB reserved Kseg1 (cash disabled) Kseg0 (2 GB) Reserved for debugging (2 MB) Kseg0 (cash enabled) Inaccessible 0x8000 0000 Internal I/O Internal ROM area 0x400F FFFF projection 0x4000 0000 Inaccessible Internal ROM 0x1FCF FFFF 0x1FC0 0000 0x000F FFFF 0xFF20 0000 0xFF00 7FFF 16 MB reserved Kuseg (cash enabled) 0xFF3F FFFF 512 MB 0x0000 0000 0xFF00 0000 0x1FCF FFFF User program area Maskable interrupt area Exception vector area 0x1FC0 0400 0x1FC0 0000 Fig. 4-1 Memory Map (Note 1) The internal ROM is mapped to: 0x1FC0_0000-0x1FCF_FFFF (1024 KB) The internal RAM is mapped to: 0xFFFF_4000-0xFFFF_FFFF (48 KB) (Note 2) The amount of back up RAM installed is 16KB. 0xFFFF_0000-0xFFFF_3FFF (Back up RAM) (Note 3) Do not place an instruction in the last four words of a physical area. Internal ROM: 0x1FCF_FFF0-0x1FCF_FFFF (256 KB) (Note 4) The mirror region cannot be used for ROM correction. Memory Map TMP19A44 (rev1.3) 4-1 2010-04-01 TMP19A44 4.1.2 TMP19A44FEXBG 0xFFFF FFFF Virtual address Physical address 16 MB reserved 16 MB reserved Kseg2 (1 GB) Kseg2 (cash enabled) Built-in RAM area 0xFFFF FFFF (48 KB) 0xFF00 0000 0xBFCB FFFF 0xBFC0 0000 0xA000 0000 Built-in RAM area 0xFFFF 4FFF (16 KB) 0xFFFF 0000 Inaccessible 16 MB reserved Kseg1 (cash disabled) Kseg0 (2 GB) Reserved for debugging (2 MB) Kseg0 (cash enabled) Inaccessible 0x8000 0000 Internal I/O Internal ROM area 0x400F FFFF projection 0x4000 0000 Inaccessible Internal ROM 0x1FCB FFFF 0x1FC0 0000 0x000B FFFF 0xFF20 0000 0xFF00 7FFF 16 MB reserved Kuseg (cash enabled) 0xFF3F FFFF 512 MB 0x0000 0000 0xFF00 0000 0x1FCB FFFF User program area Maskable interrupt area Exception vector area 0x1FC0 0400 0x1FC0 0000 Fig. 4-2 Memory Map (Note 1) The internal ROM is mapped to: 0x1FC0_0000-0x1FCB_FFFF (768 KB) The internal RAM is mapped to: 0xFFFF_4000-0xFFFF_FFFF (48 KB) (Note 2) The amount of back up RAM installed is 16KB. 0xFFFF_0000-0xFFFF_3FFF (Back up RAM) (Note 3) Do not place an instruction in the last four words of a physical area. Internal ROM: 0x1FCB_FFF0-0x1FCB_FFFF (256 KB) (Note 4) The mirror region cannot be used for ROM correction. Memory Map TMP19A44 (rev1.3) 4-2 2010-04-01 TMP19A44 4.1.3 TMP19A44FDAXBG 0xFFFF FFFF Virtual address Physical address 16 MB reserved 16 MB reserved Kseg2 (1 GB) Kseg2 (cash enabled) Built-in RAM area 0xFFFF FFFF (24 KB) 0xFF00 0000 0xBFC7 FFFF 0xBFC0 0000 0xA000 0000 Inaccessible Built-in RAM area (8 KB) 0xFFFF 0000 16 MB reserved Inaccessible Kseg1 (cash disabled) Kseg0 (2 GB) Reserved for debugging (2 MB) Kseg0 (cash enabled) Inaccessible 0x8000 0000 Internal I/O Internal ROM area 0x400F FFFF projection 0x4000 0000 Inaccessible Internal ROM 0x1FC7 FFFF 0x1FC0 0000 0x0007FFFF 0xFF3F FFFF 0xFF20 0000 0xFF00 7FFF 16 MB reserved Kuseg (cash enabled) 0xFFFF A000 0xFFFF 1FFF 512 MB 0x0000 0000 0xFF00 0000 0x1FC7 FFFF User program area Maskable interrupt area Exception vector area 0x1FC0 0400 0x1FC0 0000 Fig. 4-3 Memory Map (Note 5) The internal ROM is mapped to: 0x1FC0_0000~0x1FC7_FFFF (512KB) The internal RAM is mapped to: 0xFFFF_A000~0xFFFF_FFFF (24KB) (Note 6) The amount of back up RAM installed is 8KB. 0xFFFF_00000xFFFF_1FFF (Back up RAM) (Note 7) Do not place an instruction in the last four words of a physical area. Internal ROM: 0x1FC7_FFF0-0x1FC7_FFFF (256 KB) (Note 8) The mirror region cannot be used for ROM correction. 4.2 Internal RAM TMP19A44 is equipped with accessible work RAM (48K/24K) and back-up RAM (16K/8KB). The work RAM and back-up RAM are available for program area and data area. The data in the work RAM is initialized by reset. The data in the back-up RAM remains intact as long as stable electrical potential is provided from a power supply unit (BVCC3) even when reset is executed. To access the back-up RAM in normal mode, 4 clocks are required. Memory Map TMP19A44 (rev1.3) 4-3 2010-04-01 TMP19A44 5. Clock/Standby Control (CG) The system operation modes contain the standby modes in which the processor core operations are stopped to reduce power consumption. (c) State Transition Diagram of BACKUP Mode Fig. 5.1 State Transition Diagram of Each Operation Mode is shown below. Reset Reset has been performed Instruction IDLE mode (CPU stop) (I/O selective operation) Interrupt NORMAL mode (fc/gear value) Instruction STOP mode (Entire circuit stop) Interrupt (a) State Transition Diagram of Single Clock Mode Reset Reset has been performed Instruction IDLE mode (CPU stop) (I/O selective operation) NORMAL mode (fc/gear value) Interrupt Instruction Interrupt Instruction SLEEP mode (fs only) Instruction Instruction Interrupt SLOW mode (fs) Interrupt Interrupt STOP mode (Entire circuit stop) Instruction (b) State Transition Diagram of Dual Clock Mode Reset * Main power on Reset has been performed. Instruction IDLE mode (CPU stop) Interrupt (I/O selection operation) Instruction SLEEP mode (fs only) Interrupt Instruction NORMAL mode (fc/gear value) Instruction SLOW mode (fs) Interrupt Instruction Interrupt Interrupt STOP mode Instruction Instruction BACKUP STOP mode BACKUP SLEEP mode (fs only) (c) State Transition Diagram of BACKUP Mode Fig. 5.1 State Transition Diagram of Each Operation Mode *: CG is not initialized when the mode is shifted from backup to normal. Clock/Standby Control TMP19A44(rev1.3) 5-1 2010-04-01 TMP19A44 External reset Reset has been perfor med. NORMAL mode PLL OFF fosc = fc = fsys fperiph = fsys/2 Fig. 5.2 Default State of the System Clock osc pll c s gear sys periph : Clock frequency to be input via the X1 and X2 pins : Clock frequency multiplied (multiplied by 8) by the PLL : High-frequency clock frequency : Low-frequency clock frequency : Clock frequency selected by the system control register SYSCR1<GEAR2:0> in the clock generator : System clock frequency : Clock frequency selected by SYSCR1<FPSEL> (Clock to be input to the peripheral I/O prescaler) Clock/Standby Control TMP19A44(rev1.3) 5-2 2010-04-01 TMP19A44 5.1 Clock System Block Diagram 5.1.1 Main System Clock * Allows for oscillator connection or external clock input. * Clock gear (1/2, 1/4, 1/8 and 1/16) (After reset: 1/1) * Input frequency Input frequency Maximum operating frequency Minimum operating frequency 80 MHz 4 MHz * 8~10MHz * PLL is on: Clock gear 1/8 (default) is used when 8 MHz (MIN) is input. PLL is off: 1/2 or 1/1 is selectable. Input frequency (low frequency) Input frequency range 30KHz~34 KHz Maximum operating frequency 34 kHz (Note) (Precautions for switching the high-speed clock gear) Switching of clock gear is executed when a value is written to the SYSCR1<GEAR2:0> register. There are cases where switching does not occur immediately after the change in the register setting but the original clock gear is used for execution of instructions. If it is necessary to use the new clock for execution of the instructions following to the clock gear switching instruction, insert a dummy instruction (to execute a write cycle). To use the clock gear, ensure that you make the time setting such that Tn of the prescaler output from each block in the peripheral I/O is calibrated to Tn<fsys/2 (Tn becomes slower than fsys/2). Do not switch the clock gear during operation of the timer counter or other peripheral I/O. Clock/Standby Control TMP19A44(rev1.3) 5-3 2010-04-01 TMP19A44 5.2 Clock Gear * The high-speed clock is divided into 3/4, 1/2, 1/4 or 1/8. * The internal I/O prescaler clock T0: fperiph/2, fperiph/4, fperiph/8, fperiph/16 and fperiph/32 After reset: fperiph/32 * The PLLSEL register controls PLL on/off. PLL stops after reset. OSCCR0<WPSEL> SYSCR1 <FPSEL> OSCCR0<WUEF> OSCCR0<WUPT1 : 0> fper iph (To peripheral I/O) fgear Warm-up timer OSCCR1 <XTEN> fc XT1 Low speed oscillator XT2 fs fs fsys PLLSEL <PLLSEL> OSCCR1 <XEN> X1 High speed X2 oscillator 1/2 1/8 fosc 1/2 1/4 1/8 1/16 CKSEL <SYSCK> SYSCR0 <GEAR2 : 0> After reset: 1/1 fpll = fosc x 8 IInput to peripheral I/O prescaler TMRB/C, SIO, SBI T0 fperiph 1/16 ADC conversion cloc k PLL f<PLLON> 1/4 1/32 SYSCR1 <PRC K2:0> CPU/G-BusI/O CPU,R OM,RAM, DMAC, INTC, HSIO, PHTCNT,K WUP fsys Peripheral I/O SBI 1/4 1/2 SYSCR2 <SCOSEL1:0> Peripheral I/O ADC, TMRB/C, SIO, SBI, WDT, PORT, RTC SCOUT fs Fig. 5.3 Clock and Standby Related Block Diagram Clock/Standby Control TMP19A44(rev1.3) 5-4 2010-04-01 TMP19A44 5.3 CG Registers 5.3.1 System Control Registers 7 LITTLE BIG SYSCR0 (0xFF00_1900) (0xFF00_1903) Bit symbol Read/Write After reset Function LITTLE BIG SYSCR1 (0xFF00_1901) (0xFF00_1902) LITTLE BIG SYSCR2 (0xFF00_1902) (0xFF00_1901) 22 4 3 0 0 0 13 12 FPSEL R/W 0 Select fperiph 0 11 R 0 This can be read as "0". 2 1 0 GEAR2 GEAR1 GEAR0 R/W R/W R/W 0 0 0 Select gear of high-speed clock (fc) 000: fc 100: fc/2 001: reserved 101: fc/4 010: reserved 110: fc/8 011: reserved 111: fc/16 10 9 PRCK2 PRCK1 R/W R/W 0 0 Select prescaler clock 000: fperiph/2 100: fperiph/32 001: fperiph/4 101: Reserved 010: fperiph/8 110: Reserved 011: fperiph/16 111: Reserved 0:fgear 1:fc 20 19 18 0 0 0 0 29 28 27 26 21 R 0 0 This can be read as "0". 31 Bit symbol Read/Write After reset Function 14 R 0 0 This can be read as "0". 23 Bit symbol Read/Write After reset Function 5 R 0 0 This can be read as "0". 15 Bit symbol Read/Write After reset Function 6 30 17 16 SCOSEL1 SCOSEL0 R/W R/W 0 1 Select SCOUT output 00:fs 01:fsys/2 10:fsys 11:T0 25 24 R 0 This can be read as "0". <Bit 2:0><GEAR 2:0> : Selects gear of high-speed clock (fc) <Bit 10:8><PRCK 2:0> : Selects prescaler clock to peripheral I/O. <Bit 12><FPSEL> : Selects fperiph source clock. <Bit 16:17><SCOSEL1:0> : Enables to output specified clock from SCOUT pin P44. Clock/Standby Control 8 PRCK0 R/W 0 TMP19A44(rev1.3) 5-5 2010-04-01 TMP19A44 5.3.2 OSCCR0 LITTLE 0xFF00_1904) BIG 0xFF00_1907) OSCCR1 LITTLE 0xFF00_1905) BIG 0xFF00_1906) Oscillator Control Register 7 6 5 4 3 2 1 0 Bit symbol WUPT2 WUPT1 WUPT0 WUPSEL PLLON WUEF WUEON Read/Write R R/W R/W R/W R/W R/W R W After reset 0 0 0 1 0 0 0 0 Control of PLL operation Status of Function This can be Select oscillator warm-up time Warm-up warm-up warm-up read as "0". counter timer (WUP) timer (WUP) 0: Stop X1 is selected XT1 is selected for oscillator for oscillator 1: Oscillating 000: No warm-up 0: X1 6 001: Setting prohibited 2 / Input frequency1: XT1 0: warm-up 13 7 010: 2 /Input frequency 2 / Input frequency 0: don't care completed 14 8 011: 2 /Input frequency 2 / Input frequency Starting 1: Warm-up is in 1: 15 15 100: 2 /Input frequency 2 /Input frequency warm-up progress 16 16 101: 2 /Input frequency 2 /Input frequency 110,111: Setting prohibited 15 14 13 12 11 10 9 8 Bit symbol DRVOSCL DRVOSCH XTEN XEN Read/Write R R R/W R/W R R R/W R/W After reset 0 0 0 0 0 0 0 1 High-speed High-speed This can be This can be Low-speed Function This can be This can be Low-speed oscillator oscillator oscillator oscillator read as "0". read as "0". read as "0". read as "0". current current control control 0: Stop 0: Stop 1 : Oscillating 1: Oscillating 0: High 0: High capability capability 1:Low 1:Low capability capability 23 22 21 20 19 18 17 16 Bit symbol Read/Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 Bit symbol Read/Write After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 <Bit 0><WUEON> : Enables to start oscillator warm-up timer. *Set this bit independently after setting other bits in the register. <Bit 1><WUEF> : Indicates status of warm-up timer for oscillator. <Bit 2><PLLON> : Selects PLL multiplying circuit operation. It stops after reset. Reconfiguration is required. <Bit 3><WUPSEL> : Selects oscillator to warm-up. <Bit 6:4><WUT2:0> : Selects oscillator warm-up time. <Bit 8><XEN> : Selects high-speed oscillator operation. <Bit 8><XTEN> : Selects low-speed oscillator operation. <Bit 12><DRVOSCH> : Selects current for high-speed oscillator. The <DRVOSCH> bit is cleared to "0" (large current) when the mode is shifted from STOP to normal even if the bit is set to "1" (small current) in shifting to STOP mode. Reconfigure the bit if needed. : Selects current for low-speed oscillator. The <DRVOSCL> bit is cleared to "0" (large current) when the mode is shifted from STOP to normal even if the bit is set to "1" (small current) in shifting to STOP mode. Reconfigure the bit if needed. <Bit 13><DRVOSCL> Clock/Standby Control TMP19A44(rev1.3) 5-6 2010-04-01 TMP19A44 5.3.3 Standby Control Register 7 CR0 LITTLE (0xFF00_1908) BIG (0xFF00_190B) Bit symbol Read/Write After reset Function CR1 LITTLE (0xFF00_1909) (0xFF00_190A) BIG CR2 LITTLE BIG (0xFF00_190A) (0xFF00_1909) 3 14 13 12 11 R 0 This can be read as "0". 22 21 2 1 STBY2 STBY1 R/W R/W 0 1 Select standby mode 20 19 18 28 27 26 This can be read as "0". 30 29 0 STBY0 R/W 1 000: Reserved 001: STOP 010: SLEEP 011: IDLE 100: Reserved 101: Backup STOP 110: Backup SLEEP 111: Reserved 10 9 RXTEN R/W 0 Low-speed oscillator after the STOP mode is released R 0 31 Bit symbol Read/Writ e After reset 4 This can be read as "0". 23 Bit symbol Read/Write After reset Function 5 R 0 15 Bit symbol Read/Write After reset Function 6 8 RXEN R/W 1 High-speed oscillator after the STOP mode is released 0: Stop 1: Oscillating 17 PTKEEP R/W 0 0:Varies depending on the port condition 1: Fixed to the port condition shifted from 0 to 1 25 0: Stop 1: Oscillating 16 DRVE R/W 0 0: Not to drive the pin even in the STOP mode. 1: Drive the pin even in the STOP mode. 24 R This can be read as "0". <Bit 2:0><STBY2:0> : Selects standby mode. <Bit 8><RXEN> : Selects high-speed oscillator operation after releasing STOP mode. <Bit 9><RXTEN> : Selects low-speed oscillator operation after releasing STOP mode. <Bit 16><DRVE> : Selects pin drive condition in STOP mode. This setting is invalid in backup mode. <Bit 17><PTKEEP> : Specifies port condition. Clock/Standby Control TMP19A44(rev1.3) 5-7 2010-04-01 TMP19A44 5.3.4 PLLSEL (0xFF00_190C) PLL Select Register Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 0 0 R 0 This can be read as "0". 0 0 0 15 14 13 0 0 0 23 22 21 0 0 0 31 30 29 0 0 0 <Bit 0><PLLSEL> Clock/Standby Control 12 11 R 0 0 This can be read as "0". 20 19 R 0 0 This can be read as "0". 28 27 R 0 0 This can be read as "0". 0 PLLSEL R/W 0 Select PLL 10 9 0: X1 1: PLL 8 0 0 0 18 17 16 0 0 0 26 25 24 0 0 0 : Enable or disable clock multiplied by PLL. "X1" is used after reset. Reconfiguration is required if you use PLL.. TMP19A44(rev1.3) 5-8 2010-04-01 TMP19A44 5.3.5 CKSEL (0xFF00_1910) System Clock Select Register Bit symbol Read/Write After reset Function 7 6 0 0 5 4 R 0 0 This can be read as "0". 3 2 0 0 1 SYSCK R/W 0 Select system clock 0 SYSCKFLG R 0 System clock status flag 0: High-speed (fc) 1: Low-speed (fs) Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function 15 14 13 0 0 0 23 22 21 0 0 0 31 30 29 0 0 0 12 11 R 0 0 This can be read as "0". 20 19 R 0 0 This can be read as "0". 28 27 R 0 0 This can be read as "0". 10 9 0: High-speed (fc) 1: Low-speed (fs) (stable and identical to <SYSCK>) 8 0 0 0 18 17 16 0 0 0 26 25 24 0 0 0 <Bit 0><SYSCKFLG> : Indicates status when system clock is switched. To make the <SYSCK> setting for switching oscillator valid, there is a time lag. If <SYSCLKFLG> recognizes the oscillator specified in <SYSCK>, the switching is completed. <Bit 1><SYSCK> : Enables to select system clock. To change <SYSCK> setting, set <XEN> and <XTEN> of the OSCCR1 register to "1" beforehand. Clock/Standby Control TMP19A44(rev1.3) 5-9 2010-04-01 TMP19A44 5.3.6 Reset Flag Register 7 RSTFLG (0xFF00_191C) Bit symbol Read/Write After reset Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function 5 4 PrRSTF R/W 0 0 R 0 Function Bit symbol Read/Write After reset Function 6 0 This can be read as "0". 15 14 13 0 0 0 23 22 21 0 0 0 31 30 29 0 0 0 3 BUPRSTF 2 WDTRSTF 1 PINRSTF 0 PONRSTF R/W R/W R/W R/W 0 0 0 1 Pr reset flag Backup reset flag WDT reset flag RESET pin flag Power-on reset flag 0: "0" is written 0: "0" is written 0: "0" is written 0: "0" is written 0: "0" is written 1:Reset from Pr reset 1:Reset from backup reset 1:Reset from WDT 11 10 9 8 0 0 0 18 17 16 0 0 0 26 25 24 0 0 0 12 R 0 0 This can be read as "0". 20 19 R 0 0 This can be read as "0". 28 27 R 0 0 This can be read as "0". <Bit 0><PONRSTF> : Power on reset sets this bit to "1". <Bit 1><PINRSTF> : Reset from RESET pin sets this bit to "1". <Bit 2><WDTRSTF> : Reset by WDT sets this bit to "1". <Bit 3><BUPRSTF> : Returning from backup mode sets this bit to "1". 1:Rest from RESET pin 1:Rest from power-on reset This register is initialized only by power-on reset in. Clock/Standby Control TMP19A44(rev1.3) 5-10 2010-04-01 TMP19A44 5.4 System Clock Controller 5.4.1 Initial Values after Reset Reset initializes the system clock controller as follows. High-speed oscillator : ON (oscillating) Low-speed oscillator : ON (oscillating) PLL (phase locked loop circuit) : OFF (stop) High-speed clock gear : fc (no frequency dividing) For example, when a 10-MHz oscillator is connected to the X1 or X2 pin, fsys becomes 10MHz after reset. 5.4.2 Oscillation Stabilization Time (Switching between the NORMAL and SLOW modes) The warm-up timer is provided to confirm the oscillation stability of the oscillator when it is connected to the oscillator connection pin. The warm-up time can be selected by setting the OSCCR0<WUPT2:0> depending on the characteristics of the oscillator. The OSCCR0<WUEON><WUEF> are used to confirm the start and completion of warm-up through software (instruction). After the completion of warm-up is confirmed, switch the system clock (CKSEL<SYSCK>). When clock switching occurs, the current system clock can be checked by monitoring the CKSEL<SYSCKFLG>. (c) State Transition Diagram of BACKUP Mode Fig. 5.1 shows the warm-up time when switching occurs. Table 5.1 Warm-up Time (fosc=10 MHz, fs=32.768 kHz) Warm-up time options High-speed clock (fosc) Low-speed clock (fs) OSCCR0<WUPT 2:0> OSCCR0<WUPSEL>="0" OSCCR0<WUPSEL>="1" 000 001 010 011 100 101 110 111 (Note 1) (Note 2) 2 / input frequency No warm-up No warm-up 6 Setting prohibited 213/ input frequency 214/ input frequency 215/ input frequency 216/ input frequency 409.6s 1.953ms 819.2s 27/ input frequency 3.906ms 1.638ms 28/ input frequency 7.813ms 3.277ms 6.554ms Setting prohibited Setting prohibited 215/ input frequency 216/ input frequency 217/ input frequency Setting prohibited 1.0s 2.0s 4.0s Warm-up is not required when an oscillator is used for the clock and providing stable oscillation. The warm-up timer operates according to the oscillation clock, and it can contain errors if there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be taken as approximate time. Clock/Standby Control TMP19A44(rev1.3) 5-11 2010-04-01 TMP19A44 <Example 1> Transition from the NORMAL mode to the SLOW mode OSCCR0<WUPT2:0>"xx": Select the warm-up time OSCCR0<WUPSEL>"1": Warm-up time XT1 OSCCR1<XTEN>"1": Enable the low-speed oscillation (fs) OSCCR0<WUEON>"1": Start the warm-up timer (WUP) OSCCR0<WUEF>Read: Wait until the state becomes "0" (WUP is finished) CKSEL<SYSCK>"1": Switch the system clock to low speed (fs) CKSEL<SYSCKFLG>Read: Confirm that the current state is "1" (the current system clock is fs) OSCCR1<XEN>"0": Disable the high-speed oscillation (fosc) <Example 2> Transition from the SLOW mode to the NORMAL mode OSCCR0<WUPT2:0>"xx": Select the warm-up time OSCCR0<WUPSEL>"0": Warm-up time X1 OSCCR1<XEN>"1": Enable the high-speed oscillation (fosc) OSCCR0<WUEF>"1": Start the warm-up timer (WUP) OSCCR0<WUEF>Read: Wait until the state becomes "0" (WUP is finished) CKSEL<SYSCK>"0": Switch the system clock to high speed (fgear) CKSEL<SYSCKFLG>Read: Confirm that the current state is "0" (the current system clock is fgear) OSCCR1<XTEN>"0": Disable the low-speed oscillation (fs) (Note 1) In the SLOW mode, the CPU operate with the low-speed clock, and the INTC, the real time clock timer, the IO port, the EBIF (external bus interface) and the PHTCNT,KWUP are operable. Stop other internal peripheral functions before the system enters the SLOW mode. (Note 2) Before switching the system clock, ensure that the clock is properly switched by reading the CKSEL<SYSCKFLG> bit. 5.4.3 System Clock Pin Output Function The system clock fsys and fsys/2, prescaler input clock for peripheral I/O T0 and low-speed clock fs can be output from the P44/SCOUT pin. By setting the port 4 related registers, P4CR<P44C> to "1" and P4FC1<P44F> to "1," the P44/SCOUT pin becomes the SCOUT output pin. The output clock is selected by setting the SYSCR2<SCOSEL1:0>. Table 5.2 shows the pin states in each standby mode when the P44/SCOUT pin is set to the SCOUT output. Table 5.2 SCOUT Output State in Each Standby Mode Mode SCOUT selection NORMAL SLOW <SCOSEL1:0> = "00" <SCOSEL1:0> = "01" Output the fsys/2 clock. <SCOSEL1:0> = "10" Output the fsys clock. <SCOSEL1:0> = "11" Output the T0 clock. Standby mode IDLE SLEEP STOP Output the fs clock. Fixed to "0" or "1". (Note) The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed. (Note) The system clock cannot be output from SCOUT in backup mode. Clock/Standby Control TMP19A44(rev1.3) 5-12 2010-04-01 TMP19A44 5.4.4 Reducing the Oscillator Driving Capability This function is intended for restricting oscillation noise generated from the oscillator and reducing the power dissipation of the oscillator when it is connected to the oscillator connection pin. Setting the OSCCR1<DRVOSCH> to "1" reduces the driving capability of the high-speed oscillator (low capability). This is reset to the default setting "0." When the power is turned on, oscillation starts with the normal driving capability (high capability). This is automatically set to the high driving capability state (<DRVOSCH> ="0") whenever the oscillator starts oscillation due to mode transition. z Reducing the driving capability of the high-speed oscillator fOSC X1 pin C1 Enable oscillation Oscillator OSCCR1<DRVOSCH> C2 X2 pin Fig. 5.4 Oscillator Driving Capability 5.5 Prescaler Clock Controller Each internal I/O (TMRB0-11, SIO0-2, HSIO0-2 and SBI0) has a prescaler for dividing a clock. The clock T0 to be input to each prescaler is obtained by selecting the "fperiph" clock at the SYSCR1<FPSEL> and then dividing the clock according to the setting of SYSCR1<PRCK2:0>. After the controller is reset, fperiph/2 is selected as T0. 5.6 Clock Multiplication Circuit (PLL) This circuit outputs the fpll clock that is multiplied by eight of the high-speed oscillator output clock, fosc. This lowers the oscillator input frequency while increasing the internal clock speed. Clock/Standby Control TMP19A44(rev1.3) 5-13 2010-04-01 TMP19A44 5.7 Standby Controller The TX19A/ H1 core has several low-consumption modes. To shift to the STOP, SLEEP, IDLE (Halt or Doze) or backup mode, set the RP bit in the CPO status register, and then execute the WAIT instruction. Before shifting to the mode, you need to select the standby mode at the system control register STBYCR0<STBY2:0>. The features of the IDLE, SLEEP, STOP and backup modes are described below. 5.7.1 Standby Mode 5.7.1.1 IDLE Mode Only the CPU is stopped in this mode. The internal I/O has one bit of the ON/OFF setting register for operation in the IDLE mode in the register of each module. This enables operation settings for the IDLE mode. When the internal I/O has been set not to operate in the IDLE mode, it stops operation and holds the state when the system enters the IDLE mode. Table 5.3 Internal I/O setting registers for the IDLE mode (Note 1) Internal I/O IDLE Mode Setting Register TMRB0~11 TBxRUN<I2TBx> TMRC TCCR<I2TBT> SIO0~3 SCxMOD1<I2Sx> HSIO0~3 HSCxMOD1<I2Sx> I2C/SIO(SBI) SBIBR1<I2SBIx> A/D converter A~C ADMOD1<I2AD> WDT WDMOD<I2WDT> The Halt mode is activated by setting the RP bit in the status register to "0," executing the WAIT command and shifting to the standby mode. In this mode, the TX19A/ H1 processor core stops the processer operation while holding the status of the pipeline. The TX19A/H1 gives no response to the bus control authority request from the internal DMA, so the bus control authority is maintained in this mode. (Note 2) The Doze mode is activated by setting the RP bit in the status register to "1" and shifting to the standby mode. In this mode, the TX19A/ H1 processor core stops the processer operation while holding the status of the pipeline. The TX19A/ H1 can respond to the bus control authority request given from the outside of the processor core. SLEEP: Only the internal low-speed oscillator, the clock timer, the 2-phase pulse input counter and the KWUP (dynamic pull-up circuit) operate. STOP: All the internal circuits are brought to a stop. The standby mode selection Status<RP > of CP0 is selected by the combination. Please do not execute the WAIT instruction in the setting of "X" in the following table. RESERVED STOP SLEEP IDLE BACKUP STOP BACKUP SLEEP Clock/Standby Control STBY 2:0 OTHER 001 010 011 101 110 HALT RP=0 X STOP SLEEP HALT BACKUP STOP BACKUP SLEEP TMP19A44(rev1.3) 5-14 DOZE RP=1 X X X DOZE X X 2010-04-01 TMP19A44 5.7.2 CG Operations in Each Mode Table 5.4 Status of CG in Each Operation Mode Clock source Oscillator Oscillatio n circuit PLL Normal { { { { Slow { x Partial supply (Note) { Idle (Halt) { { Selectable x Idle (Doze) { { Selectable { Sleep/ Backup Fs only x Clock timer, 2-phase pulse input counter and KWUP x Stop/ Backup x x x x Mode Clock supply to peripheral I/O Clock supply to CPU {: ON or clock supply x: OFF or no clock supply (Note) Peripheral functions that can work in the SLOW mode: INTC, external bus interface, IO port, clock timer, 2-phase pulse input counter and KWUP 5.7.3 Block Operations in Each Mode Table 5.5 Block Operating Status in Each Operation Mode NORMAL SLOW IDLE (Doze) IDLE (Halt) SLEEP STOP SLEEP Backup STOP Backup TX19A/H1 processor core DMAC INTC External bus I/F IO port { { { { { { { { { { x { { { { x x { x x x x x x x x x x x x x x x x x x x x x x ADC SIO HSIO I2C TMRB TMRC WDT { { { { { { { x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x { { { { {Static pull-up { (fs only) { { {Static pull-up Block 2-phase pulse input counter Dynamic pull-up (KWUP) ON/OFF selectable for each module { { { { { RTC { { { { { x { x CG { { { { { x { x High-speed oscillator (fc) { (Note) { { x x x x Low-speed oscillator (fs) { { { { { x { x {:ON x:OFF (Note) When the system enters the SLOW mode, the high-speed oscillator must be stopped by setting the OSCCR1<XEN>. Clock/Standby Control TMP19A44(rev1.3) 5-15 2010-04-01 TMP19A44 5.7.4 Releasing the Standby State The standby state can be released by an interrupt request when the interrupt level is higher than the interrupt mask level, or by the reset. The standby release source that can be used is determined by a combination of the standby mode and the state of the interrupt mask register <IM15:8> assigned to the status register in the system control coprocessor (CPO) of the TX19A / H1 processor core. Details are shown in Table 5.6. z Release by an interrupt request Operations of releasing the standby state using an interrupt request vary depending on the interrupt enabled state. If the interrupt level specified before the system enters the standby mode is equal to or higher than the value of the interrupt mask register, an interrupt handling operation is executed by the trigger after the standby is released, and the processing is started at the instruction next to the standby shift instruction (WAIT instruction). If the interrupt request level is lower than the value of the interrupt mask register, the processing is started with the instruction next to the standby shift instruction (WAIT instruction) without executing an interrupt handling operation. (The interrupt request flag is maintained at "1.") For a non-maskable interrupt, an interrupt handling is executed after the standby state is released irrespectively of the mask register value. z Release by the reset Any standby state can be released by the reset. Note that releasing of the STOP mode requires sufficient reset time to allow the oscillator operation to become stable. Please refer to "6. Interrupts" for details of interrupts for STOP, SLEEP and SLEEP release and ordinary interrupts. Table 5.6 Standby Release Sources and Standby Release Operations (Interrupt level)>(Interrupt mask) Interrupt accepting state Standby mode INTWDT Interrupt enabled EI= "1" IDLE SLEEP/ Standby mode (programmable) B-Sleep x { { x x { x INT0~BINT10~1B Interrupt Standby release source KWUP00~31 INTRTC PHCNT0~5 Interrupt disabled EI= "0" IDLE SLEEP/ Standby mode (programmable) B-Sleep INTTB0~11 x x x x INTRX0~2,INTTX0~2 x x x x x x x x x x x x x x x x HINTRX0~2,HINTTX0~2 INTS0 INTAD/INTADHP/INTADM RESET : Starts the interrupt handling after the standby mode is released. (The LSI is initialized by the reset.) : Starts the processing at the address next to the standby instruction (without executing the interrupt handling) after the standby mode is released. x: Cannot be used for releasing the standby mode Clock/Standby Control TMP19A44(rev1.3) 5-16 2010-04-01 TMP19A44 (Note 1) The standby mode is released after the warm-up time has elapsed. (Note 2) To release the standby mode by using the level mode interrupt in the interruptible state, keep the level until the interrupt handling is started. Changing the level before then will prevent the interrupt processing from starting properly. (Note 3) To recover from the standby mode when the CPU has disabled the acceptance of interrupts, set the interrupt level higher than the interrupt mask (Interrupt level > Interrupt mask). If the interrupt level is equal to or lower than the interrupt mask (Interrupt level Interrupt mask), the system cannot recover from the standby mode. Clock/Standby Control TMP19A44(rev1.3) 5-17 2010-04-01 TMP19A44 5.7.5 STOP Mode In the STOP mode, all the internal circuits, including the internal oscillators, are brought to a stop. The pin states in the STOP mode vary depending on the setting of the STBYCR2<DRVE>. Table 5.7 shows the pin states in the STOP mode. When the STOP mode is released, the system clock output is started after the elapse of warm-up time at the warm-up counter to allow the internal oscillators to stabilize. After the STOP mode is released, the system returns to the operation mode that was active immediately before the STOP mode (NORMAL or SLOW), and starts the operation. It is necessary to make these settings before the instruction to enter the STOP mode is executed. Specify the warm-up time at the OSCCR0<WUPT2:0>. (Note 1) (Note 2) To shift from the NORMAL mode to the STOP mode on the TMP19A44, do not set the OSCCR0<WUPT2:0> to "000" for the warm-up time setting. The internal system recovery time cannot be satisfied when the system recovers from the STOP mode. To shift from the SLOW mode to the STOP mode (high-speed clock is stopped) be sure to set OSCCR0<WUPT2:0>"110" during warm-up time. The setting in <DRVE> is valid in STOP mode. It is invalid in backup mode. Table 5.7 Warm-up Settings for Transitions of Operation Modes Transition of operation mode Warm-up setting NORMALSLOW Required (Note) SLOWNORMAL Required (Note) NORMALIDLE NORMAL Not required NORMALSLEEP NORMAL Required NORMALSTOP NORMAL Required SLOW IDLESLOW X SLOW SLEEPSLOW Not required SLOWSTOP SLOW Required NORMALBackup SLEEPNORMAL Required NORMAL Backup STOP NORMAL Required SLOW Backup SLEEP SLOW Required SLOW Backup STOP SLOW Required Clock/Standby Control TMP19A44(rev1.3) 5-18 2010-04-01 TMP19A44 5.7.6 1. Recovery from the STOP or SLEEP Mode Transition of operation modes: NORMAL STOP NORMAL System clock off fsys (High-speed clock) mode NORMAL STOP NORMAL CG (High-speed clock) Start of high-speed clock oscillation Warm-up (W-up) End of warm-up Start of warm-up Table 5.8 Warm-up time Selection of warm-up time Warm-up time OSCCR0<WUPT 2:0> (fosc = 10.0MHz) 000 001(212/inputfrequency) 010(213/inputfrequency) 011(214/inputfrequency) 100(215/inputfrequency) 101(216/inputfrequency) 110 (Setting prohibited) 111 (Setting prohibited) Clock/Standby Control No warm-up 409.6s 819.2s 1.638ms 3.277ms 6.554ms TMP19A44(rev1.3) 5-19 2010-04-01 TMP19A44 2. Transition of operation modes: NORMAL SLEEP NORMAL fsys (High-speed clock) mode System clock off NORMAL SLEEP NORMAL CG (High-speed clock) CG (Low-speed clock) Warm-up (W-up) Low-speed clock (fs) continues oscillation Start of high-speed clock oscillation Start of warm-up End of warm-up Table 5.9 Warm-up Time Selection of warm-up time Warm-up time OSCCR0<WUPT 2:0> (fosc = 10.0MHz) 000 001 (212/ input frequency) 010 (213/ input frequency) 011 (214/ input frequency) 100 (215/ input frequency) 101 (216/ input frequency) 110 (Setting prohibited) 111 (Setting prohibited) Clock/Standby Control No warm-up 409.6s 819.2s 1.638ms 3.277ms 6.554ms TMP19A44(rev1.3) 5-20 2010-04-01 TMP19A44 3. Transition of operation modes: SLOW STOP SLOW fsys (Low-speed clock) mode System clock off SLOW STOP SLOW CG (Low-speed clock) Start of low-speed clock oscillation Start of warm-up Warm-up (W-up) End of warm-up Table 5.10 Warm-up Time Selection of warm-up time Warm-up time OSCCR0<WUPT 2:0> (fs = 32.768kHz) 000 001 (212/ input frequency) 010 (213/ input frequency) 011 (214/ input frequency) 100 (215/ input frequency) 101 (216/ input frequency) 110 (217/ input frequency) 111 (Setting prohibited) 4. No warm-up 1.953ms 3.906ms 7.813ms 1.0s 2.0s 4.0s Transition of operation modes: SLOW SLEEP SLOW fsys (Low-speed clock) mode System clock off SLOW SLEEP SLOW CG (fs) (Low-speed clock) (Note) The low-speed clock (fs) continues oscillation. There is no need to make a warm-up setting. Clock/Standby Control TMP19A44(rev1.3) 5-21 2010-04-01 TMP19A44 6. Exceptions/Interrupts This chapter describes types, factors and process flow of exceptions/ interrupts. "6.1 Overview" describes types of factors, generation mechanism and process flow. The section 6.2 or later describes details unique to each factor. Exceptions/ interrupts have close relation to the CPU core architecture. Refer to "TX19A/H1 architecture" if needed. Exceptions/Interrupts TMP19A44(rev1.3) 6-1 2010-04-01 TMP19A44 6.1 Overview This section roughly describes features, types and process flow of exceptions and interrupts. Please refer to the section 6.2 or later for details. 6.1.1 Exceptions and Interrupts Exceptions and interrupts request the CPU to stop the ongoing processing and execute other processing. Interrupts are classified into general interrupt and debug interrupt. 6.1.1.1 Exceptions features General exception is caused by an abnormal condition or an instruction to generate an exception. Debug exception is used when debugging. 6.1.1.2 Interrupts features Interrupts are classified into two types. One is maskable hardware interrupt of which factor is hardware-generated (i.e. interrupt request signal from external pin or peripheral IP). Another is Maskable software interrupt that is caused by software. They are generically named as maskable interrupts. The features of the mast able interrupts are as follows: Prioritization according to interrupt level The 19A44 can handle multiple interrupts according to the seven programmable interrupt priority levels. By setting a mask level, an interrupt of which level is lower than the specified can be masked. Shadow register A register bank "Shadow Register Set" enables high-speed response to an interrupt without storing the contents to the genera purpose register (GPR). DMAC activation An interrupt can be used as DMAC activator. It requires settings in the interrupt controller. Hereinafter general interrupts and debug interrupts are referred to as "exception", maskable interrupts are referred to as "interrupt". If maskable interrupt factors are divided into software-generated or hardware-generated, we call them "software interrupt" or "hardware interrupt" respectively. Exceptions/Interrupts TMP19A44(rev1.3) 6-2 2010-04-01 TMP19A44 6.1.2 Types The following lists general exceptions, debug exceptions and interrupts. For more details, see "TX19A/H1architecture". (1) General exceptions Reset exception Non-maskable interrupt (NMI) Address error exception (instruction fetch) Address error exception (load/store) Bus error exception (instruction fetch) Bus error exception (load/ store) Co-processor unusable exception Reserved instruction exception Integer overflow exception Trap exception System call exception Breakpoint exception (2) Debug exception Single step exception Debug breakpoint exception (3) Interrupts Software interrupts Hardware interrupts Exceptions/Interrupts TMP19A44(rev1.3) 6-3 2010-04-01 TMP19A44 6.1.3 Process Flow The following shows how an exception/ interrupt is handled. indicates hardware handling. indicates software handling. Details are described in the later section. Processing Exception/ interrupt request Details See Exception/ interrupt request is made. 6.2.3.1 Detecting exception/ interrupt The CPU detects the exception/ interrupt. 6.2.3.2 Handling exception/ interrupt The CPU/ INTC/ CG handle the exception/ interrupt. 6.2.3.3 CPU branches off to exception handler The CPU branches off to an appropriate exception vector address according to the exception/ interrupt detected. 6.2.3.4 Program for the exception handler. 6.2.3.5 Configure to return to the formerly-processed program from the exception handler. 6.2.3.6 Executing exception handler program Returning to normal program Exceptions/Interrupts TMP19A44(rev1.3) 6-4 2010-04-01 TMP19A44 6.1.3.1 Generation of exception/ interrupt request An exception or an interrupt request is generated by various factors (i. e. instruction executed by the CPU, external interrupt pin and peripheral I/O) (1) Exception request An exception request is mainly caused by an abnormal condition detected during executing an instruction. The following list categorized the types of the exceptions into four groups: "Requests not from the CPU", "Abnormal conditions during instructions", "Instructions to generate exceptions" and "Debug register setting". Table 6.1 Exception types and factors Requests not from the CPU Reset signal Reset exception WDT Non-maskable interrupt (NMI External NMI pin Abnormal conditions during instructions Address error exception (instruction fetch/ load/ store Instruction fetch from the address undesignated. Bus error exception (instruction fetch/ load/ store Instruction fetch from the unused area Reading operand in the address undesignated. Reading operand in the unused area Co-processor unusable exception Executing co-processor instruction without setting the CU bit of the status register in the co-processor. Integer overflow exception Overflow of ADD, ADDI or SUB instruction result Reserved instruction exception Executing undefined instruction code Instructions to generate exceptions System call exception Executing SYSCALL instruction Debug breakpoint exception Executing SDBBP instruction Breakpoint exception Executing BREAK instruction Trap exception Executing TGE, TGEU, TLT, TLTU, TEQ TNE, TGEI, TGEIU, TLTI, TLTIU, TEQI and TNEI instructions. Debug register setting Single step exception Setting SSt bit in the Debug register (2) Interrupt request An interrupt request is caused by software (software interrupt), an external pin or a peripheral IP (hardware interrupt) To make interrupt request, setting of the CP0 register, CG and interrupt controller are required. Details are described in "6.5 Hardware interrupt". Exceptions/Interrupts TMP19A44(rev1.3) 6-5 2010-04-01 TMP19A44 6.1.3.2 Exceptions/ interrupts detection (1) Priority There are cases that multiple exceptions and interrupts are detected simultaneously. To handle the situation, the CPU executes an exception of an interrupt with the highest priority. The priority of the exceptions/ interrupts is shown below. Table 6.2 Exceptions/ interrupts priority (when detected simultaneously) Priority Exceptions/ interrupts Higher Reset exception Single step exception Non-maskable interrupt (NMI) Hardware interrupts Software interrupts Address error exception (instruction fetch) Bus error exception (instruction fetch/ store) Debug breakpoint exception Co-processor unusable exception Reserved instruction exception Integer overflow exception Trap exception System call exception Breakpoint exception Address error exception (load/store) Lower Bus error exception (data access) (Note) When a hardware interrupt and a software interrupt are detected simultaneously, a maskablehardware interrupt is executed. Exceptions/Interrupts TMP19A44(rev1.3) 6-6 2010-04-01 TMP19A44 6.1.3.3 Exceptions/ interrupt handling (1) Filed change When an exception/ interrupt is detected, related fields in the CP0 register of the CPU, the interrupt controller registers and the CG registers are changed. The condition after the change differs depending on the exception/ interrupt detected as shown in the table below. Exceptions/Interrupts TMP19A44(rev1.3) 6-7 2010-04-01 TMP19A44 Table 6.3 Register filed change Factor Interrupts Other exceptions Non-maskable interrupt (NMI) Reset Field Register CP0 register Status RP BEV NMI ERL 0 1 0 1 1 1 - - EXL - - 1 1 BD - - 1/0 1/0 CE[1:0] - - - ExcCod e - - - (Cop No) Code PC PC - Cod e - - - - PC PC - - - (Addr) - CSS - - - PSS Reg Set No Reg Set No Reg Set No Reg Set No Reg Set No CMASK - - - Level PMASK - - - Level Cause Error EPC EPC Bad VAddr SSCR Meaning Low-power consumption mode is setselect Halt/Doze. Exception handler address has been changed. NMI is generated. Reset/ NMI is generated. Interrupt prohibited when this bit is set. Exception (other than reset/NMI) is generated. Interrupt prohibited when this bit is set. 1: exception/ interrupt is generated in the slot of branch instruction. 0: others This bit changes only when the EXL bit of the status register is "0". Co-processor number referred when co-processor unusable exception is generated. Code according to exception/ interrupt. Program counter of an instruction executed when a factor is detected. It indicates program counter of branch instruction when a factor is detected in the branch instruction slot. Virtual address considered to be an error when an address error exception is generated. Register set number. When the SSD bit of the SSCR registerbit to enable the shadow registeris "0" (enabled), an interrupt changes the CSS bit to select The shadow register corresponding to the detected interrupt level. (the shadow register switching) CSS contents set before an interrupt is stored in PSS. Interrupt controller ILEV CMASK: detected interrupt level PMASK: CMASK value before interrupt generation "-" indicates no change. Factors shown with are changed by specific exceptions. Other than the registers shown above, the NMIFLG register setting changes when non-maskable interrupt is detected and the IVR register setting of the interrupt controller is changed when maskable interrupt is detected. These changes are described in "6.2 Reset exception/ non-maskable interrupt" and "6.5 Hardware interrupt". This table excludes the changes related to debug exceptions. See "TX19A/H1 architecture" for these changes. Exceptions/Interrupts TMP19A44(rev1.3) 6-8 2010-04-01 TMP19A44 6.1.3.4 Branch to Exception handler The CPU branches off to the exception vector address (exception handler) in detecting an exception/ interrupt. The exception vector addresses differ depending on the exceptions/ interrupts or the settings in the CP0 register Status<BEV> bit and Cause<IV> bit. The Status<BEV> bit is set to "1" after reset. If you set the exception vector address to the internal ROM, do not change the bit from "1". The Cause<IV> bit is undefined after reset. Setting this bit to "1" is required. By setting this bit to "1" the vector addresses of interrupt exceptions and other exceptions can be distinguished. The following table lists the vector addresses. Table 6.4 Exception vector address (virtual) Exceptions/ interrupts 6.1.3.5 Status<BEV>=0 Status<BEV>=1 RESET,NMI 0xBFC0_0000 0xBFC0_0000 Debug exception 0xBFC0_0480 0xBFC0_0480 Interrupt (Cause<IV>=0) 0x8000_0180 0xBFC0_0380 Interrupt (Cause<IV>=1) 0x8000_0200 0xBFC0_0400 Other exceptions 0x8000_0180 0xBFC0_0380 Execution of Exception Handler Program The exception handler executes exception/ interrupt processing. The processing varies depending on the exception/ interrupt generated. You need to program the exception handler. When using the exception handler for interrupts, processing (i.e. clearing interrupt request) may be required in order to prevent the same interrupt from occurring. See "6.5 hardware interrupt" for details. Exceptions/Interrupts TMP19A44(rev1.3) 6-9 2010-04-01 TMP19A44 6.1.3.6 Returning from Exceptions/ interrupts You can refer to the exception/ interrupt generation program counter stored in the ErrorEPC/ EPC of the CP0 register when returning from the exception handler to the program previously executed. Please note that the same exception/ interrupt may occur once again at that time. (1) Returning with ERET instruction To return from an exception handler of general exception/ interrupt, you can use the ERET instruction. By executing the ERET instruction, the normal operation restarts from the address stored in the Error EPCEPC of the CP0 register, and the CP register automatically goes back to the pre-exception/interrupt state. If you set the rewritable ErrorEPCEPC with the return address in advance, the normal operation restarts from the desired address by executing the ERET instruction. The ERET instruction operates differently according to the setting of Status<ERL> and <EXL> bits as shown below. When ERL=1 (Reset/ NMI is generated) Status<ERL> "0" SSCR<CSS> "PSS" Branch off to Address stored in ErrorEPC EXL=1 (general exception/ interrupt other than reset/NMI is generated) Status<EXL> "0" SSCR<CSS> "PSS" Branch off to Address store in EPC (Note) The ERET instruction copies the values in SSCR<CSS> to SSCR<PSS> regardless of the exception/interrupt to be executed. If SSD bit is "0" and a shadow register is available. When an exception is generated, "CSS" is copied to "PSS", however, CSS remains intact. That is, "CSS" values remain intact during and after handling exception. SSD SSCR 0 CSS PSS X 2 Exception is generated 0 2 2 0 2 5 ERET execution 0 2 2 0 2 2 Exception is generated Exceptions/Interrupts TMP19A44(rev1.3) 6-10 Interrupt is generated ( level 5) ERET execution Interrupt is generated 2010-04-01 TMP19A44 (2) Interrupt Level Register (ILEV) The following is required only for a hardware interrupt. If the interrupt occurs, its interrupt level is set to ILEV<CSS> of the ILEV register in INTC as a mask level. Write "0" to ILEV<MLEV> to shift to the level of the previous interrupt because it does not automatically shift by an ERET instruction. If you want to set a new value to ILEV<CMASK>, set "1" to ILEV<MLEV> and write a value to ILEV<CMASK> simultaneously. (3) Returning without ERET instruction You can return from exception handler to a normal program without using an ERET instruction. In this case, settings of in Status<ERL>, Status<EXL> and SSCR<CSS> are the same as when the exception/ interrupt is generated. Change the settings if needed. Exceptions/Interrupts TMP19A44(rev1.3) 6-11 2010-04-01 TMP19A44 6.2 Reset Exception/ Non-maskable Interrupt (NMI) A reset exception and non-maskable interrupt are branch off to the same reset exception vector address. When both a reset exception and NMI can be used, check the CP0 register to distinguish which one is generated. 6.2.1 Factors Reset exception and NMI have factors shown below. 6.2.1.1 Factors of Reset Exception External reset pin Setting an external reset pin to "L" and shift it to "H" generates a reset exception. WDT WDT can generate a reset exception. See "Chapter 18 Watchdog timer" for details. 6.2.1.2 Factors of NMI External NMI pin Setting an external NMI pin to "L" generates NMI. (TMP19A44 has no external NMI pin. WDT WDT can generate NMI. See "Chapter 18 Watchdog timer" for details. Write bus error When an operand write bus cycle results in a bus error, NMI is generated instead of a bus error exception. Exceptions/Interrupts TMP19A44(rev1.3) 6-12 2010-04-01 TMP19A44 6.2.2 Reset Exception/ NMI Handling 6.2.2.1 Flowchart The following shows how a reset exception and NMI are handled. indicates hardware handling. indicates software handling. Details Processing Reset exception/ NMI factor is generated CPU detects reset exception/ NMI A reset exception/ NMI factor is generated. The CPU detects reset exception/ NMI. The CPU/ CG handles the reset exception/ NMI. Reset exception All the special function registers of the peripherals are initialized. CPU/ CG handles reset exception/ NMI. The following bits in the CP0 register are automatically set. CP0: Status<ERL> "1" CP0: ErrorEPC "PC of exception"(Note) CP0: Status<BEV> "1" CP0: Status<NMI> "0" CP0: Status<RP> "0" Register set number CP0: SSCR<PSS> (when exception occurs) NMI The following bits in the automatically set. CP0: Status<ERL> CP0: ErrorEPC CP0: Status<NMI> CP0: Cause<BD> CG: CP0: CPU branches off to exception handler Exceptions/Interrupts CP0 register and CG are NMIFLG SSCR<PSS> "1" "PC of exception" (Note) "1" "1/0" (Note) "1 is set to corresponding bit" Register set number (when exception occurs) The CPU branches off to the reset exception vector address (0xBFC0_0000). TMP19A44(rev1.3) 6-13 2010-04-01 TMP19A44 Details Processing Execute exception handler program Returning to preceding program Program for the exception handler. Configure to return to the preceding program from the exception handler. (Note) Cause<BD> bit of the CP0 register is set to -"1": when an exception is generated by an instruction in a jump/ branch slot. -"0": other than the above. ErrorEPC normally stores PC of the instruction causes an exception. It stores PC of a jump/ branch instruction when an exception is generated by an instruction in a jump/ branch slot. 6.2.2.2 How to Distinguish Reset Exception and Non-maskable Interrupt A reset exception and non-maskable interrupt are branch off to the same reset exception vector address. To distinguish which one is generated, refer to the Status<NMI> bit of the CP0 register. Indicating "0" means reset exception is generated. Indicating "1" means non-maskable interrupt is generated. This bit is not changed by other exceptions/ interrupts. A non-maskable interrupt has multiple interrupt factors. To distinguish which factor is used, refer to the NMIFLG register in the CG register. 6.2.2.3 Status<EXL> Bit of the CP0 Register If "1" is set to the Status<EXL> bit, interrupts are prohibited. "1" is set to the Status<EXL> bit due to exception handling of the CPU when a reset exception/ non-maskable interrupt occurs. This bit is automatically cleared to "0" when returning from an exception handler by executing the ERET instruction. To execute an interrupt while handling an exception, set "0". 6.2.2.4 PC Stored in the ErrorEPC The ErrorEPC register in the CP0 register stores PC of the instruction causes an exception. As for a reset exception right after power-on, a value stored in the register is undefined since the PC value is undefined. 6.2.2.5 Return from Exception Handler See "6.1.3.6 Returning from Exceptions/ interrupts". Exceptions/Interrupts TMP19A44(rev1.3) 6-14 2010-04-01 TMP19A44 6.3 General Exceptions This section describes general exceptions other than reset exceptions/ NMIs. General exceptions are as follows: Address error exception (instruction fetch) Address error exception (load/store) Bus error exception (instruction fetch) Bus error exception (load) Co-processor unusable exception Reserved instruction exception Integer overflow exception Trap exception System call exception Breakpoint exception 6.3.1 Factors General exceptions are generated when a certain instructions are executed or errors (i. e. in correct instruction fetch ) are detected . See TX19A/H1 architecture for details of conditions that each exception is generated. Exceptions/Interrupts TMP19A44(rev1.3) 6-15 2010-04-01 TMP19A44 6.3.2 General Exception Handling 6.3.2.1 Flowchart The following shows how a hardware interrupt is handled. indicates hardware handling. indicates software handling. Details Processing General exception factor is generated. The CPU detects interrupt The interrupt factor is generated. The CPU detects the interrupt. The CPU handles the interrupt. The following bits in the CP0 register are automatically set. CPU Handles interrupt CPU branches off to exception handler Execute exception handler program Returning to preceding program CP0: Status<EXL> CP0: EPC CP0: CP0: CP0: Cause<BD> Cause<ExcCode> BadVAddr CP0: SSCR<PSS> "1" "PC of exception"(Note 1) "1/0"(Note 1) Exception factor code Error address (Note 2) Register set number (when exception occurs) The CPU branches off to the exception vector address (0xBFC0_0380). Program for the exception handler. Configure to return to the preceding program from the exception handler. (Note 1) Cause<BD> bit of the CP0 register is set to -"1": when an exception is generated by an instruction in a jump/ branch slot. -"0": other than the above. ErrorEPC normally stores PC of the instruction causes an exception. It stores PC of a jump/ branch instruction when an exception is generated by an instruction in a jump/ branch slot. (Note 2) An error virtual address is stored when an address error exception occurs. Exceptions/Interrupts TMP19A44(rev1.3) 6-16 2010-04-01 TMP19A44 6.3.2.2 When General Exception Occurs Generation of general exceptions other than a trap exception, a system call exception and a break point exception means abnormal condition is detected. When abnormal condition is detected, reset process is taken in most cases. When a general exception (excluding reset exceptions/ NMI) other than a bus error exception (instruction fetch and data access) occurs, EPC stores PC that causes the exception. Therefore, if ERET is used for returning to normal operation, the same exception may occur. 6.3.2.3 Return from Exception Handler See section "6.1.3.6 Returning from Exceptions/ Interrupts". Exceptions/Interrupts TMP19A44(rev1.3) 6-17 2010-04-01 TMP19A44 6.4 Software Interrupt Software interrupt, which has two factors, occurs by setting the CP0 register. A software interrupt has the same priority as a hardware interrupt. These interrupts may occur simultaneously and use the same exception handler. 6.4.1 Factors 6.4.1.1 Condition of Generating Interrupt A software interrupt factor is recognized when the following three settings are configured in the CP0 register. At least 3 clocks are required to generate the interrupt after the factor is generated. 1) Status<IM>[1:0] (interrupt mask) is "1". 2) Cause<IP>[1:0] (interrupt request) is "1". 3) Status<IE> (interrupt enable bit) is "1". The Status<IM>[1:0] and Cause<IP>[1:0] need to be used together. If IM is "1", IP must be "1", and if IM is "0", IP must be "0". IE bit is to enable an interrupt and used for both software and hardware interrupts. 6.4.1.2 Condition of not Generating Interrupt Even if the three settings shown above are completed, a software interrupt cannot be generated under the following conditions. The factor is suspended until the condition is changed as interrupt-acceptable. Status<ERL> or Status<EXL> bit is set Status<ERL> bit is set to "1" when reset or NMI occurs. Status<EXL> bit is set to "1" when an interrupt or a general exception other than reset / NMI occurs. After an exception or an interrupt is generated, software interrupts are prohibited. Both Status<ERL> and Status<EXL> bits are rewritable. Writing these bits to "0"using exception handler program enables software interrupts. These bits automatically return to "0" when returning from exception handler by ERET instruction. In debug mode In debug mode, which is defined as duration from debug exception generation to returning by DRET instruction, a software interrupt is ignored. The CPU is stalled When the CPU is stalled for any reason, a software interrupt is not generated. Exceptions/Interrupts TMP19A44(rev1.3) 6-18 2010-04-01 TMP19A44 6.4.1.3 Clearing Factors A software interrupt factor is held unless the register settings are rewritten. In the exception handler, Status<EXL> of the CP0 register is set to "1". Therefore, another software interrupt is not generated. A software interrupt is recognized again if Status<EXL> is cleared to "0" when EXL bit is rewritten during exception handling or returning from exception handler by ERET. To clear a software interrupt factor, clear one of the Status<IM>, Cause<IP> and Status<IE> bits to "0". Status<IE> is a bit to enable both software and hardware interrupts. Clearing this bit to "0" disables both interrupts. 6.4.1.4 Reading IVR Register Read the IVR register of INTC after a software interrupt is generated. "4" can be read. Until the IVR is read, no hardware interrupt from INTC is accepted. 6.4.1.5 Return from Exception Handler See "6.1.3.6 Returning from Exception/ Interrupts". Exceptions/Interrupts TMP19A44(rev1.3) 6-19 2010-04-01 TMP19A44 6.4.2 Software Interrupt Handling 6.4.2.1 Flowchart The following shows how a software interrupt is handled. indicates hardware handling. indicates software handling. Details Processing Set the following bits in the CP0 register. Status<IM>[1:0] Interrupt factor is generated Cause<IP>[1:0] Status<IE> The CPU detects the interrupt. Detection is unavailable in the following conditions. -Status<ERL> or Status<EXL> bit is set CPU detects interrupt -In debug mode -The CPU is stalled. At least 3 clocks are required to detect the interrupt after the factor is generated. The CPU handles the interrupt. The following bits in the CP0 register are automatically set. CPU handles interrupt CP0: CP0: CP0: Status[EXL] ErrorEPC Cause[BD] "1" "PC of exception"(Note) "1/0"(Note) The CPU branches off to the exception vector address. An interrupt vector address differs depending on combination of the BEV bit in the Status register and the IV bit in the Cause register. CPU branches off to exception handler Exceptions/Interrupts BEV=0 BEV=1 IV=0 0x8000_0180 0xBFC0_0380 IV=1 0x8000_0200 0xBFC0_0400 TMP19A44(rev1.3) 6-20 2010-04-01 TMP19A44 Details Processing Program for the exception handler. Clear the interrupt factor if needed. Read INTC IVR register. Execute exception handler program Configure to return to the preceding program from the exception handler. Returning to preceding program (Note) Cause<BD> bit of the CP0 register is set to -"1": when an exception is generated by an instruction in a jump/ branch slot. -"0": other than the above. ErrorEPC normally stores PC of the instruction causes an exception. It stores PC of a jump/ branch instruction when an exception is generated by an instruction in a jump/ branch slot. 6.4.2.2 Interrupt Factor Indication A software interrupt uses the same exception handler as a hardware interrupt. These interrupts may occur simultaneously. In this case, a hardware interrupt has a priority if a shadow register is available. The Cause<IP>[4:0] and Status<IM>[4:0] of the CP0 register indicate an interrupt factor. If any of the Cause<IP>[1:0] indicates "1", it is the software interrupt factor. If any of the Cause<IP>[4:2] indicates "1", it is the hardware interrupt factor. Detecting both interrupts simultaneously enables both factors. The Status<IM>[4:0] and Cause<IP>[4:0] can mask a factor. They need to be used together. A factor is not recognized even if the Cause<IP> is set to "1" when corresponding Status<IM> is "0". The Cause<IP>[4:2] bits do not indicate an individual interrupt factor. It indicates interrupt level of a hardware interrupt. See "6.5 Hardware Interrupt" for details of hardware interrupt. Exceptions/Interrupts TMP19A44(rev1.3) 6-21 2010-04-01 TMP19A44 6.5 Hardware Interrupt A hardware interrupt is generated when INTC notifies the CPU of an interrupt level. INTC controls interrupt factors, prioritizes them and notifies the CPU of the level of the highest priority. Interrupt factors that can be used for clearing standby mode is transmitted to INTC via CG. Therefore, setting of CG is also required. This section describes route, factors, and settings of hardware interrupts. How to handle multiple interrupts and how to use an interrupt as a DMAC factor are also described. Exceptions/Interrupts TMP19A44(rev1.3) 6-22 2010-04-01 TMP19A44 6.5.1 Interrupt Factors 6.5.1.1 Interrupt Route Fig. 6.1 shows an interrupt request route. Peripheral IP INTC Port External interrupt pin Notifying interrupt CP Interrupt request Accepting interrupt Interrupt request Port External interrupt pin Clearing Standby mode CG Peripheral IP Fig. 6.1 Interrupt Route 6.5.1.2 Generation of Factors A hardware interrupt is requested from external pins assigned to interrupt factors, peripheral IP and INTC. External pins To use external pins as interrupt pins, configure the port control register. Peripheral IP To generate an interrupt from peripheral IP, configure the appropriate peripheral IP so that it can output an interrupt. See chapters of each IP for details. INTC INTC can generate an interrupt factor by setting a register. This function is caller software set. To generate an interrupt, set the active state to "L" level and any desired interrupt level. To clear the factor, set the active state other than "L" level and set the interrupt level to "0". See "6.5.2.2 Preparation (5) Preconfiguration 3 (software set)" for details. Exceptions/Interrupts TMP19A44(rev1.3) 6-23 2010-04-01 TMP19A44 6.5.1.3 Transmission of Factors An interrupt request that is not used to clear standby mode is directly transmitted to INTC. An interrupt request that is used to clear standby mode is transmitted to INTC via CG. Using or not using a factor for clearing standby mode can be set in the CG control register. 6.5.1.4 Request Acceptance Upon detecting interrupt factors, INTC notifies the CPU of the interrupt factor with the highest priority according to the priority order. The CPU recognizes the incoming interrupt level as a hardware interrupt factor, and notifies INTC that the interrupt request is accepted unless other exceptions with higher priorities are received. Exceptions/Interrupts TMP19A44(rev1.3) 6-24 2010-04-01 TMP19A44 6.5.1.5 List of Interrupt Factors Table 6.5 shows the list of interrupt factors. Table 6.5 List of Hardware Interrupt Factors No. Interrupt Factors 1 (No interrupt factor) Software interrupt 2 3 IVR Activation trigger 0x000 0x004 INT0 0x008 INT1 0x00C Selectable (Note 1) 4 INT2 0x010 5 INT3 0x014 6 INT4 0x018 7 INT5 0x01C 8 INT6 0x020 9 INT7 0x024 10 INT8 0x028 0 Control register Interrupt CG controller Interrupt pin (Returning from standby) IMC00 IMCGA PA0 PA1 IMC01 PA2 PA3 IMCGB PA4 PA5 IMC02 PJ6 PJ7 IMCGC P86 11 INT9 0x02C 12 INTA 0x030 13 INTB 0x034 14 INTC 0x038 15 INTD 0x03C 16 INTE 0x040 17 INTF 0x044 18 KWUP 0x048 "H" level 19 INT10 0x04C 20 INT11 0x050 Selectable (Note 1) 21 INT12 0x054 22 INT13 0x058 23 INT14 0x05C 24 INT15 0x060 25 INT16 0x064 26 INT17 0x068 27 INT18 0x06C 28 INT19 0x070 29 INT1A 0x074 PH2 30 INT1B 0x078 PH3 31 INT1C 0x07C 32 INT1D 0x080 33 INT1E 0x084 34 INT1F 35 INTRX0 : Serial reception (channel.0) 0x08C 36 INTTX0 : Serial transmission (channel.0) 0x090 37 INTRX1 : Serial reception (channel.1) 0x094 38 INTTX1 : Serial transmission (channel.1) 0x098 39 INTRX2 : Serial reception (channel.2) 0x09C 40 INTTX2 : Serial transmission (channel.2) 0x0A0 HINTRX0 : High-speed (Hchannel.0) reception 0x0A4 HINTTX0 :High-speed serial (Hchannel.0) transmission 0x0A8 HINTRX1 : High-speed (Hchannel.1) 41 42 43 Exceptions/Interrupts : Key-on wake-up P87 IMC03 P61 P65 IMC04 IMCGD 32 pins IMCGF P72 IMC05 P73 P76 P77 IMCG10 IMC06 PJ2 PJ3 PJ4 PJ5 IMCG11 IMC07 PH0 PH1 IMC08 0x088 serial serial reception Rising edge (Note 1) IMC09 IMC0A 0x0AC TMP19A44(rev1.3) 6-25 2010-04-01 TMP19A44 No. 44 45 46 47 48 49 50 51 52 53 Interrupt Factors IVR HINTTX1 : High-speed serial transmission (Hchannel.1) 0x0B0 HINTRX2 : High-speed (Hchannel.2) reception 0x0B4 HINTTX2 : High-speed serial transmission (Hchannel.2) 0x0B8 INTSBI0 : Serial bus interface 0 0x0BC INTADHPA : Highest priority AD conversion complete interrupt A 0x0C0 INTADMA : AD conversion monitoring function interrupt A 0x0C4 INTADHPB : Highest priority AD conversion complete interrupt B 0x0C8 INTADMB : AD conversion monitoring function interrupt B 0x0CC INTADHPC : Highest priority AD conversion complete interrupt C 0x0D0 serial 54 INTTB0 : AD conversion monitoring function interrupt C : 16bitTMRB 0 55 INTTB1 : 16bitTMRB 1 0x0DC 56 INTTB2 : 16bitTMRB 2 0x0E0 57 INTTB3 : 16bitTMRB 3 0x0E4 58 INTTB4 : 16bitTMRB 4 0x0E8 59 INTTB5 : 16bitTMRB 5 0x0EC 60 INTTB6 : 16bitTMRB 6 0x0F0 61 INTTB7 : 16bitTMRB 7 0x0F4 62 INTTB8 : 16bitTMRB 8 0x0F8 63 INTTB9 : 16bitTMRB 9 0x0FC 64 INTTBA : 16bitTMRB A 0x100 65 INTTBB : 16bitTMRB B 0x104 66 INTTBC : 16bitTMRB C 0x108 67 INTTBD : 16bitTMRB D 0x10C 68 INTTBE : 16bitTMRB E 0x110 69 INTTBF : 16bitTMRB F 0x114 70 INTADA : A/D conversion completion A 0x118 71 INTADB : A/D conversion completion B 0x11C 72 INTADC INTTB10 : A/D conversion completion C : 16bitTMRB 10 0x120 73 74 INTTB11 : 16bitTMRB 11 0x128 75 PHCNT0 : Two-phase pulse input counter 0 0x12C 76 PHCNT1 : Two-phase pulse input counter 1 0x130 77 PHCNT2 : Two-phase pulse input counter 2 0x134 78 PHCNT3 : Two-phase pulse input counter 3 0x138 79 PHCNT4 : Two-phase pulse input counter 4 0x13C 80 PHCNT5 : Two-phase pulse input counter 5 0x140 81 INTCAP0 : Input capture 0 0x144 82 INTCAP1 : Input capture 1 0x148 83 INTCAP2 : Input capture 2 0x14C 84 : Input capture 3 : Compare 0 0x150 85 INTCAP3 INTCMP0 86 INTCMP1 : Compare 1 0x158 87 INTCMP2 : Compare 2 0x15C INTADMC Exceptions/Interrupts Activation trigger Rising edge (Note 1) Control register Interrupt CG controller Interrupt pin (Returning from standby) IMC0B IM0C IM0D 0x0D4 0x0D8 IM0E IM0F IM10 IM11 IM12 0x124 IMCGD IM13 PA0/PA1 PA2/PA3 IMCGE PA6/PA7 PB0/PB1 PI0/PI1 IM14 PI2/PI3 IM15 0x154 TMP19A44(rev1.3) 6-26 2010-04-01 TMP19A44 No. Interrupt Factors IVR 88 INTCMP3 : Compare 3 0x160 89 INTCMP4 : Compare 4 0x164 90 INTCMP5 : Compare 5 0x168 91 INTCMP6 : Compare 6 0x16C 92 INTCMP7 : Compare 7 0x170 93 INTTBT : Overflow 0x174 94 INTRTC : Real time clock timer INTDMA0 : DMA transfer (channel.0) completion 0x17C INTDMA1 : DMA transfer (channel.1) completion 0x180 INTDMA2 : DMA transfer (channel.2) completion INTDMA3 : DMA transfer (channel.3) completion 0x188 INTDMA4 : DMA transfer (channel.4) completion 0x18C INTDMA5 : DMA transfer (channel.5) completion 0x190 INTDMA6 : DMA transfer (channel.6) completion 0x194 INTDMA7 : DMA transfer (channel.7) completion 95 96 97 98 99 100 101 102 Activation trigger Control register Interrupt CG controller Interrupt pin (Returning from standby) IM16 IM17 0x178 IMCGD "L" level IM18 0x184 "L" level IM19 0x198 103 Software set 0x19C 104 Reserved 0x1A0 105 Reserved 0x1A4 106 Reserved 0x1A8 107 Reserved 0x1AC 108 Reserved 0x1B0 109 Reserved 0x1B4 110 Reserved 0x1B8 111 Reserved 0x1BC 112 Reserved 0x1C0 113 Reserved 0x1C4 114 Reserved 0x1C8 115 Reserved 0x1CC 116 Reserved 0x1D0 117 Reserved 0x1D4 118 Reserved 0x1D8 119 Reserved 0x1DC 120 Reserved 0x1E0 121 Reserved 0x1E4 122 Reserved 0x1E8 123 Reserved 0x1EC 124 Reserved 0x1F0 125 Reserved 0x1F4 126 Reserved 0x1F8 127 Reserved 0x1FC (Note 1) Set "H" level when you use the factor as a standby clear interrupt. Exceptions/Interrupts TMP19A44(rev1.3) 6-27 2010-04-01 TMP19A44 6.5.1.6 Priority Each of interrupt factors can be individually set to one of the seven interrupt priority levels by INTC. The interrupt level to be applied is set by IMC<IL> of INTC. "7" is the highest priority level. If multiple factors are generated simultaneously, an interrupt with the highest priority based on the interrupt level is selected. If multiple factors with the same interrupt level are generated simultaneously, an interrupt with the smaller interrupt number is prioritized. In addition to the individual interrupt level, set an interrupt level of the entire INTC in the ILEV<CMASK> bit of the INTC controller register. Interrupts with the lower priority than the specified in the ILEV<CMASK> bit are suspended. Default setting of the ILEV<CMASK>bit is 000". This setting enables all the interrupt levels. 6.5.1.7 Active State The active state indicates which change in signal of an interrupt factor triggers an interrupt. It can be set in the IMC<EIM> bit of the interrupt controller register. The active state is selectable from the "H" level, "L" level, rising or falling edge but some interrupt factors designate a certain level. As for the interrupt factors with specific conditions, configure as they are. You can select a condition for the factor of which activation trigger in the Table is "Selectable". To use an interrupt to clear standby mode, the active state must be set to "H" level. See the next section for details. 6.5.1.8 Factors for clearing standby mode The interrupts that can be used for clearing standby mode are shown in the Table 6.5 together with the corresponding CG control register name. To use an interrupt for clearing standby mode, enable the IMCG<INTEN> bit of the CG register and set an active state to the IMCG<EMCG> bit. The active state is selectable from the "H" level, "L" level, rising edge, falling edge or both edges. When using an interrupt for clearing standby mode, an active state of the IMC<EIM> bit in the INTC controller register must be set to "H". Setting the active state to "H" level allows INTC to receive a signal in "H" level after CG detects an interrupt. 6.5.1.9 DMAC activation by interrupt An interrupt factor can be used to activate DAMC. In this case, no interrupt is generated. By setting the IMC<DM> bit of the INTC register to "1", a request to start transfer is output to DMAC if the active level condition is satisfied. To use an interrupt as the DMAC activation, the corresponding DMAC channel must be set in IMC<ILC>. DREQFLG of the DMAC register is used to clear or monitor a transfer request. Reading this register can check whether a transfer is requested or not. Writing "1" to a bit that corresponding to the DMAC channel can clear an transfer request. See "Chapter 10 DMA Controller" for details. Exceptions/Interrupts TMP19A44(rev1.3) 6-28 2010-04-01 TMP19A44 6.5.2 Hardware Interrupt Handling 6.5.2.1 Flowchart The following shows how a hardware interrupt is handled. indicates hardware handling. indicates software handling. A hardware interrupt factor is generated by hardware or software. Details See Set the CPU coprocessor register and the INTC register to detect an interrupt. 6.5.2.2 Processing Preparation Set the clock generator as well if the interrupt is made to clear the standby mode. Common setting Settings for detection CPU coprocessor register INTC register Setting to clear standby mode Clock generator Execute an appropriate setting to send the interrupt signal depending on the interrupt type. Settings for sending interrupt signal Setting for interrupt from the external pin Port Setting for interrupt from peripheral IP Peripheral IP (See chapters of relevant IP for details.) Interrupt factor is generated Exceptions/Interrupts The interrupt factor is generated. TMP19A44(rev1.3) 6-29 2010-04-01 TMP19A44 Details Processing Not clearing standby mode See Clearing standby mode 6.5.2.3 CG detects interrupt (factor to clear standby mode) The interrupt, which is used for clearing the standby modes, is connected to INTC via the clock generator. Detection by CG INTC detects the interrupt according to the setting in the INTC IMC register. 6.5.2.4 INTC detects interrupt Detection by INTC The CPU is notified of the interrupt factor with the highest priority according to the priority order. The CPU detects the interrupt. CPU detects interrupt 6.5.2.5 Detection is unavailable in the following conditions. Detection by CPU -Status<ERL> or Status<EXL> bit is set -In debug mode -The CPU is stalled. The CPU handles the interrupt. CPU Handles interrupt 6.5.2.6 Update the field related to the CP0register. Switch a shadow register set. Output a signal to accept interrupt to INTC. CPU processing The CPU branches off to the exception vector address. CPU branches off to exception handler Exceptions/Interrupts An interrupt vector address differs depending on combination of the BEV bit in the Status register and the IV bit in the Cause register. BEV=0 BEV=1 IV=0 0x8000_0180 0xBFC0_0380 IV=1 0x8000_0200 0xBFC0_0400 TMP19A44(rev1.3) 6-30 2010-04-01 TMP19A44 Details Processing Execute exception handler program Returning to preceding program 6.5.2.2 Program for the exception handler. Clear the interrupt factor if needed. See 6.5.2.7 Exception handler Configure to return to the preceding program from the exception handler. Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following order basically. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the interrupt by the CPU. To configure the clock generator and INTC, you must follow the order indicated here not to cause any unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt in the clock generator and INTC, and then enable the interrupt. The following sections are listed in the order of interrupt handling and describe how to configure them. (1) Disabling interrupt by CPU (2) CPU registers setting (3) Preconfiguration 1 (Interrupt from external pin) (4) Preconfiguration 2 (interrupt from peripheral IP) (5) Preconfiguration 3 (software) (6) Configuring the clock generator (standby clear factor only) (7) Configuring INTC (8) Enabling interrupt by CPU Exceptions/Interrupts TMP19A44(rev1.3) 6-31 2010-04-01 TMP19A44 (1) Disabling interrupt by CPU To make the CPU for not accepting any interrupt, write "0" to the Status<IE> bit of the CP0 register. This bit is set to be interrupt-disabled after reset. CPU register Status<IE> "0" (interrupt disabled) The following shows how to make IE bit "0". 1. Set "0" to the Status<IE> bit of the CP0 register by 32 bit ISA MTC0 instruction. 2. Set "0" to the IER bit of the CP0 register by 32 bit ISA MTC0 instruction. 3. Set "0" to the Status<IE> bit of the CP0 register by 16 bit ISA MTC0 instruction. 4. Execute 16 bit ISA DI instruction. You can select one of them. We recommend No. 2 and No. 4 that prevent code increase and enable high-speed processing. (2) CPU registers setting Configure the CP0 register. By setting the Cause<IV> bit to "1" the vector addresses of interrupt exceptions and other exceptions can be distinguished. Write "1" to the Status<IM4:2> bits to enable an interrupt from INTC. Clear the SSCR<SSD> bit to "0" when using a shadow register. CPU register Cause<IV> "1" Status<IM> "111" SSCR<SSD> "0" (3) Preconfiguration 1 (Interrupt from external pin) Set the port of the corresponding pin. Setting PnFCx [m] of the corresponding port function register to "1" allows the pin to be used as the function pin. Clearing PnCR [m] to "0" allows the pin to be used as the input port. Port register PnFCx<PnmFx> "1" PnCR<PnmC> "0" (Note) Exceptions/Interrupts n: port number m: corresponding bit x: function register number TMP19A44(rev1.3) 6-32 2010-04-01 TMP19A44 (4) Preconfiguration 2 (interrupt from peripheral IP) The setting varies depending on the IP to be used. See chapters of relevant IP for details. (5) Preconfiguration 3 (software set) The software set interrupt is requested by setting the IMC register of INTC. Set the active state to "L" level. You can set any interrupt level. This factor is recognized upon setting the register. Set the active state and interrupt level as appropriate. Interrupt controller register IMC19<EIM671:670> "00" ("L" level) IMC19<IL672:670> Interrupt level (6) Configuring the clock generator (standby factor only) You can omit this step unless the interrupt is used to clear standby. You need to configure active state and enabling interrupt for an interrupt to clear the standby mode with the IMCG register of the clock generator. The IMCG register is capable of configuring each factor. Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt. To clear corresponding interrupt request, write value corresponding to the interrupt to be used to the ICRCG register. See "6.6.3.2 INTCG Clear Register" for each value. Clock generator register IMCGn<EMCGm> Active state EICRCG<ICRCG> Value corresponding to the interrupt to be used IMCGn<INTmEN> "1" (interrupt enabled) (Note) n: register number m: number assigned to interrupt factor Exceptions/Interrupts TMP19A44(rev1.3) 6-33 2010-04-01 TMP19A44 (7) Configuring INTC With INTC, mask levels of the entire INTC, a base address of interrupt vector table and an active state and an interrupt level of each factor are configurable. An interrupt level to be detected by INTC can be set in the ILEV register. An interrupt factor with the lower interrupt level than the level set in ILEV<CMASK> is suspended. "0" is set as a default level. In this condition, all the interrupt levels can be detected. To change the level, write "1" to ILEV<MLEV> at the same time when writing the level to ILEV<CMASK>. INTC register ILEV<CMASK> Interrupt mask level ILEV<MLEV> "1" Set a base address of an interrupt vector table to IVR [31:9] of the IVR resister. Prepare the table in the address configured. INTC register IVR[31:9] Interrupt handler base address Clear an interrupt factor already held in INTC to generate an interrupt in appropriate timing. To clear the factor, write IVR of the interrupt you want to execute to the INTCLR register. INTC register INTCLR<EICLR> IVR Set an active state and an interrupt level to IMC register with which the setting for each factor is available. Some interrupt factors designate a certain active state. See the IMC register section for details. Set "H" level when using an interrupt to clear standby mode. Set "L" level when using software set. INTC register IMCn<EIMm> Active state IMCn<ILm> Interrupt level Exceptions/Interrupts TMP19A44(rev1.3) 6-34 2010-04-01 TMP19A44 (8) Enabling interrupt by CPU Enable the interrupt by the CPU. Set Status<IE> to "1". CPU register Status<IE> "1" The following shows how to make IE bit "1". 1. Set "1" to the Status<IE> bit of the CP0 register by 32 bit ISA MTC0 instruction. 2. Set a value other than "0" to the IER bit of the CP0 register by 32 bit ISA MTC0 instruction. 3. Set "1" to the Status<IE> bit of the CP0 register by 16 bit ISA MTC0 instruction. 4. Execute 16 bit ISA EI instruction. You can select one of them. We recommend No. 2 and No. 4 that prevent code increase and enable high-speed processing. 6.5.2.3 Detection by CG If the interrupt is used for clearing the standby mode, the interrupt factor is detected by a trigger for an active state specified in the clock generator, and notified to INTC. The interrupt factor that enters active state triggered by a rising or falling edge is held in the clock generator after detection. However, if a signal in "H" or "L" level is specified as the trigger to enter the active state, the CPU considers that the interrupt factor is cleared upon exiting from the active state. Therefore, the active state needs to be kept until the interrupt is detected. The interrupt detected by the clock generator is notified to INTC with a signal in "H" level. Therefore, you need to set INTC so that the interrupt to clear standby is activated by a "H" signal. Exceptions/Interrupts TMP19A44(rev1.3) 6-35 2010-04-01 TMP19A44 6.5.2.4 Detection by INTC INTC handles an interrupt in the following procedure. (1) INTC detects interrupts according to active state specified per factor. An interrupt factor with the highest priority of the interrupt level and interrupt number is selected. A factor, of which active state is rising or falling edge, is kept in the INTC after its detection. A factor, of which active state is "H" or "L" level, is considered to be cleared if its level is changed from the active state. Keep its active state until an interrupt is detected. (2) INTC compares the interrupt level of the selected factor with the level specified in the ILEV<CMASK>. If the selected factor has the higher interrupt level, INTC notifies the CPU of the interrupt level. (3) When the CPU detects the interrupt, it sends a signal, which indicates the interrupt is accepted, to INTC. If an interrupt with the higher priority is detected before the CPU sends the signal, an interrupt level is replaced by it. (4) After receiving the signal, INTC sets the IVR to the IVR register and the interrupt level to the CMASK of the ILEV register. (5) INTC holds the information of the interrupt detected until the IVR is read. An interrupt factor with the higher priority is suspended. ... Interrupt signal Level (1)Priority judgment (2) Comparison Level>CMASK (3) Level notification CPU (5) Level is fixed by interrupt acceptance signal and released by reading IVR. (4)Interrupt acceptance CMASK IVR IVR Exceptions/Interrupts TMP19A44(rev1.3) 6-36 2010-04-01 TMP19A44 6.5.2.5 Detection by CPU (1) Factors of hardware interrupt A hardware interrupt factor is recognized by the CPU when the following three settings are configured. 1) Status<IM> (interrupt mask) is "111". 2) Status<IE> (interrupt enable bit) is "1". 3) Interrupt level notified from INTC is more than "1". (2) Condition of not Generating Interrupt Even if the three settings shown above are completed, a hardware interrupt cannot be generated under the following conditions. The factor is suspended until the condition is changed as interrupt-acceptable. 1) Status<ERL> or Status<EXL> bit is set Status<ERL> bit is set to "1" when reset or NMI occurs. Status<EXL> bit is set to "1" when an interrupt or a general exception other than reset / NMI occurs. After an exception or an interrupt is generated, hardware interrupts are prohibited. Both Status<ERL> and Status<EXL> bits are rewritable. Writing these bits to "0"using exception handler program enables hardware interrupts. These bits automatically return to "0" when returning from exception handler by ERET instruction. 2) In debug mode In debug mode, which is defined as duration from debug exception generation to returning by DRET instruction, a hardware interrupt is ignored. 3) The CPU is stalled When the CPU is stalled for any reason, a hardware interrupt is not generated. Exceptions/Interrupts TMP19A44(rev1.3) 6-37 2010-04-01 TMP19A44 6.5.2.6 CPU processing On detecting the interrupt, the CPU updates appropriate field in the CP0 register and branches off to the exception handler. (1) Change in CP0 Register Generating an interrupt changes the following values in the CP0 register. CP0 register Status<EXL> "1" (Interrupt prohibited) Cause<BD> Exception/ interrupt occurs in a branch slot: "1" Others: "0" Cause<ExcCode> Code according to exception/ interrupt Ex) Interrupt: "0y00000" EPC PC of the instruction being executed when interrupt is generated. SSCR<CSS> Same value as the interrupt level (note) Interrupt level value is set as the new register set number. SSCR<PSS> CSS value of the pre-interrupt (*) Shadow register set number of the pre-interrupt (Note) CSS and PSS change only when SSD of the SSCR register is set to "1" (using shadow register). Exceptions/Interrupts TMP19A44(rev1.3) 6-38 2010-04-01 TMP19A44 (2) Shadow Register Set Switching By clearing SSCR<SSD> to "0", the shadow registers can be used and the register set is switched to that has the same number as the interrupt level. Some registers are not switched. The following illustrates the shadow registers. Shadow Register Set No. 0 1 2 3 4 5 6 7 r0 r26 (k0) r27 (k1) r28 (gp) r29 (sp) Exceptions/Interrupts r29 (sp) r1 (at) r1 (at) r1 (at) r1 (at) r1 (at) r1 (at) r1 (at) r1 (at) r2 (v0) r2 (v0) r2 (v0) r2 (v0) r2 (v0) r2 (v0) r2 (v0) r2 (v0) r3 (v1) r3 (v1) r3 (v1) r3 (v1) r3 (v1) r3 (v1) r3 (v1) r3 (v1) r4 (a0) r3 (a0) r4 (a0) r4 (a0) r4 (a0) r4 (a0) r4 (a0) r4 (a0) r5 (a1) r5 (a1) r5 (a1) r5 (a1) r5 (a1) r5 (a1) r5 (a1) r5 (a1) r6 (a2) r6 (a2) r6 (a2) r6 (a2) r6 (a2) r6 (a2) r6 (a2) r6 (a2) r7 (a3) r7 (a3) r7 (a3) r7 (a3) r7 (a3) r7 (a3) r7 (a3) r7 (a3) r8 (t0) r8 (t0) r8 (t0) r8 (t0) r8 (t0) r8 (t0) r8 (t0) r8 (t0) r9 (t1) r9 (t1) r9 (t1) r9 (t1) r9 (t1) r9 (t1) r9 (t1) r9 (t1) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r10 (t2) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r11 (t3) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r12 (t4) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r13 (t5) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r14 (t6) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r15 (t7) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r16 (s0) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r17 (s1) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r18 (s2) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r19 (s3) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r20 (s4) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r21 (s5) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r22 (s6) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r23 (s7) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r24 (t8) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r25 (t9) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r30 (fp) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) r31 (ra) TMP19A44(rev1.3) 6-39 2010-04-01 TMP19A44 (3) Branch to the Exception Handler An interrupt vector address differs depending on combination of the Status<BEV> bit and the Cause<IV> bit. Status<BEV> is set to "1" after reset. Keep the setting if you set an exception vector address in the internal ROM. The Cause<IV> bit is undefined after reset. Setting this bit to "1" is required. By setting this bit to "1" the vector addresses of interrupt exceptions and other exceptions can be distinguished. BEV = 0 BEV = 1 IV = 0 0x8000_0180 0xBFC0_0380 IV = 1 0x8000_0200 0xBFC0_0400 (4) Interrupt Acceptance Signal When the CPU detects the interrupt, it sends a signal, which indicates the interrupt is accepted, to INTC. By the signal, INTC holds the interrupt level and interrupt number that have the highest priority at that time. See "6.5.2.3 Detection by CG" for INTC operation. Exceptions/Interrupts TMP19A44(rev1.3) 6-40 2010-04-01 TMP19A44 6.5.2.7 Exception Handler The exception handler requires user programming. We describe how to judge and clear a factor here. The procedure is as follows: (1) Judging factor (2) Clearing interrupt request (INTC) (3) Branch to Interrupt Handler (4) Clearing Interrupt Factor (5) Interrupt Handler Processing (6) Returning from Exception Handler (1) Judging factor The registers used for judging a factor are shown below. CP0 register Cause<IP>[4:2] Hardware interrupt level "000": No hardware interrupt factor Cause<IP>[1:0] Write "1" for using software interrupt. "00": No software interrupt factor INTC IVR[8:0] Value according to factors (See factor list) The Cause<IP>[4:0] indicates an interrupt factor. If any of the Cause<IP>[1:0] indicates "1", it is the software interrupt factor. If any of the Cause<IP>[4:2] indicates "1", it is the hardware interrupt factor. Detecting both interrupts simultaneously enables both factors. If an interrupt is generated from hardware, the IVR register of INTC indicates the factor. Value is set to IVR[8:0] according to a factor. See factor list for details. Exceptions/Interrupts TMP19A44(rev1.3) 6-41 2010-04-01 TMP19A44 (2) Clearing interrupt request (INTC) By the signal from the CPU, INTC fixes a request level. INTC clears the request sent to the CPU by setting a value of IVR[8:0] to INTCLR register. INTC INTCLR[8:0] Value of IVR[8:0] according to factor (See factor list) Upon clearing the request, an interrupt with the highest priority that suspended in INTC is requested to the CPU. When the CPU branches off to the exception handler, "1" is set to the Status<EXL> bit, and next interrupts are prohibited. The setting to use multiple interrupts is described in "6.6.2.7Multiple Interrupts". (3) Branch to Interrupt Handler If the start address of the interrupt handler table is set in IVR [31:9] of the interrupt controller register, the values specified in IVR [31:0] can be used as the start address. The CPU branches off to the address. (4) Clearing Interrupt Factor As for an interrupt detected by a level, an interrupt request exists unless the factor is cleared. Clearing the factor is required. As for an interrupt detected by an edge, an interrupt factor is cleared by setting the corresponding interrupt IVR to the INTCLR register. When the next valid edge is detected, a new factor is recognized. See (2) Clearing interrupt request (INTC). (5) Interrupt Handler Processing Usually an interrupt handler save the required register and handles interrupts. If the shadow register set is enabled (SSCR<SSD> of the CP0 register is "0"), contents in the general purpose register except for r26, r27, r28 and r29Shadow Register Set Number 1~7 are automatically saved. Save by the user program is not needed. Save the contents of the Status, EPC, SSCR, HI, LO, Cause and Config registers, if needed. General exceptions are acceptable if interrupts are prohibited. We recommend saving the contents of the general purpose register and CP0 register, which may be rewritten by general interrupts, even if multiple interrupts are not used. (6) Returning from Exception Handler See "6.1.3.6 Returning from Exception/ Interrupts". Exceptions/Interrupts TMP19A44(rev1.3) 6-42 2010-04-01 TMP19A44 6.5.2.8 Multiple Interrupts In "multiple interrupts" processing, an interrupt with higher interrupt level is processed while an interrupt is being processed. When an interrupt request is accepted, ILEV <CMASK> of INTC is automatically updated to the interrupt level of the interrupt accepted. It enables an interrupt with the higher interrupt level than the current one. (1) Preconfiguration To execute multiple interrupts, the contents in the following registers must be saved before enabling the interrupts. If not, these registers are overwritten by the second and subsequent interrupts. CP0 register EPC PC of the interrupt generated SSCR Shadow register control Status CPU status In addition to the registers shown above, save the contents of the HI, LO, Cause and Config registers if needed. (2) Enabling Multiple Interrupts When an interrupt is accepted, Status <EXL> of the CP0 register is set to "1" disabling further interrupts. Clearing the bit to "0" enables an interrupt. (3) Returning from Multiple Interrupt After returning from the multiple interrupts handler, the CPU restarts the suspended interrupt from where the interrupt is discontinued. Set Status<EXL> of the CP0 register to "1" to disable interrupts. It can prevent a new interrupt from occurring before returning from the multiple interrupts. Otherwise, original interrupt data may be destroyed. (4) Proper use of Status <EXL> and Status <IE> Status<EXL> and Status<IE> control to enable or disable the multiple interrupts. Status <EXL> is set to "1" upon interrupt generation and cleared to "0" by the ERET instruction. Interrupts must be prohibited while saving the register contents described in (1) and returning from multiple interrupts described in (3). Usually, interrupts can be prohibited with Status<EXL> controlled by hardware. Status <IE> is used for other general interrupt enable/disable control functions. The following describes how the multiple interrupts are handled. Exceptions/Interrupts TMP19A44(rev1.3) 6-43 2010-04-01 TMP19A44 cStatus<IE>=1 Interrupts can be enabled by setting Status <IE> of the CP0 register to "1" while Status <EXL> is set to "0." This optional setting is made by the software program when it is necessary. d Interrupt Generation When an interrupt is generated, Status <EXL> of the CP0 register is set to "1" disabling further interrupts. This process is automatically performed by hardware. e Status <EXL> = 0 If multiple interrupts are to be enabled, it is necessary to set Status <EXL> of the CP0 register to "0" to enable interrupts after relevant registers are saved. If interrupts are enabled before saving registers, a higher priority level interrupt could corrupt the register data. This optional setting is made by the software program when it is necessary. f Multiple Interrupts Enabled This is the period multiple interrupts are enabled. Interrupts with a level higher than the present interrupt level (ILEV <CMASK>) are to be accepted. If it is desired to disable interrupts during this period, set Status <IE> of the CP0 register to "0." g Status <EXL> = 1 If multiple interrupts are enabled, it is necessary to set Status <EXL> of the CP0 register to "1" to disable interrupts before returning relevant register values. If registers are saved before disabling interrupts, a higher priority level interrupt could corrupt the register data. This optional setting is made by the software program when it is necessary. h ERET Instruction This instruction returns the system to the state before the interrupt generation. If this instruction is executed while Status <EXL> of the CP0 register is set to "1," the Status <EXL> will be automatically set to "0" and interrupt is enabled (provided that Status <IE> of the CP0 register is set to "1"). i Status<IE>=0 Interrupts can be disabled by setting Status <IE> of the CP0 register to "0." This optional setting is made by the software program when it is necessary. Exceptions/Interrupts TMP19A44(rev1.3) 6-44 2010-04-01 TMP19A44 6.6 Registers The CP0 register, the clock generator register and the interrupt controller register are used for exceptions/ interrupts. To access to the CP0 register, you need to specify a register number with a system control co-processor (CP0) instruction. The clock generator register and the interrupt controller register have own addresses. To access to the registers, you need specify the address with load/ store instruction. The following shows the addresses of each register. 6.6.1 Register Map CP0 register BadVAddr Bad virtual address register No. 8 Status Status register No. 12 Cause Cause register No. 13 EPC Exception program counter register No. 14 ErrorEPC Error exception program counter register No. 30 SSCR Shadow register set control register No. 22 (SEL0) No. 9 (SEL6) IER Interrupt enable register No. 9 Clock generator registers IMCGA CG interrupt mode control register A 0xFF00_1720 IMCGB CG interrupt mode control register B 0xFF00_1724 IMCGC CG interrupt mode control register C 0xFF00_1728 IMCGD CG interrupt mode control register D 0xFF00_172C IMCGE CG interrupt mode control register E 0xFF00_1730 ICRCG CG interrupt request clear register 0xFF00_1714 NMIFLG NMI flag register 0xFF00_1718 RSTFLG Reset flag register 0xFF00_171C Exceptions/Interrupts TMP19A44(rev1.3) 6-45 2010-04-01 TMP19A44 Interrupt controller register IVR Interrupt vector register 0xFF00_1080 ILEV Interrupt level register 0xFF00_110C IMC00 Interrupt mode control register 00 0xFF00_1000 IMC01 Interrupt mode control register 01 0xFF00_1004 IMC02 Interrupt mode control register 02 0xFF00_1008 IMC03 Interrupt mode control register 03 0xFF00_100C IMC04 Interrupt mode control register 04 0xFF00_1010 IMC05 Interrupt mode control register 05 0xFF00_1014 IMC06 Interrupt mode control register 06 0xFF00_1018 IMC07 Interrupt mode control register 07 0xFF00_101C IMC08 Interrupt mode control register 08 0xFF00_1020 IMC09 Interrupt mode control register 09 0xFF00_1024 IMC0A Interrupt mode control register 0A 0xFF00_1028 IMC0B Interrupt mode control register 0B 0xFF00_102C IMC0C Interrupt mode control register 0C 0xFF00_1030 IMC0D Interrupt mode control register 0D 0xFF00_1034 IMC0E Interrupt mode control register 0E 0xFF00_1038 IMC0F Interrupt mode control register 0F 0xFF00_103C IMC10 Interrupt mode control register 10 0xFF00_1040 IMC11 Interrupt mode control register 11 0xFF00_1044 IMC12 Interrupt mode control register 12 0xFF00_1048 IMC13 Interrupt mode control register 13 0xFF00_104C IMC14 Interrupt mode control register 14 0xFF00_1050 IMC15 Interrupt mode control register 15 0xFF00_1054 IMC16 Interrupt mode control register 16 0xFF00_1058 IMC17 Interrupt mode control register 17 0xFF00_105C IMC18 Interrupt mode control register 18 0xFF00_1060 IMC19 Interrupt mode control register 19 0xFF00_1064 INTCLR Interrupt request clear register 0xFF00_10C0 DREQFLG DMA request clear flag register 0xFF00_10C4 Exceptions/Interrupts TMP19A44(rev1.3) 6-46 2010-04-01 TMP19A44 6.6.2 CP0 Register 6.6.2.1 VadVAddr Register When an address error exception (AdEL or AdES) occurs, the BadVaddr (Bad Virtual Address) register stores its virtual address. 7 6 5 4 3 2 VadVAddr bit Symbol BadVAddr (No.8) Read/Write After reset Function R Undefined Virtual address of an address error exceptionbit 7~0 15 14 bit Symbol 23 22 bit Symbol Read/Write After reset Function 11 10 9 8 21 20 19 18 17 16 25 24 BadVAddr R Undefined Virtual address of an address error exceptionbit 23~16 31 Exceptions/Interrupts 12 0 BadVAddr R Undefined Virtual address of an address error exceptionbit 15~8 Read/Write After reset Function bit Symbol Read/Write After reset Function 13 1 30 29 28 27 26 BadVAddr R Undefined Virtual address of an address error exceptionbit 31~24 TMP19A44(rev1.3) 6-47 2010-04-01 TMP19A44 6.6.2.2 Status Register 7 6 5 4 Status bit Symbol KX SX (No.12) Read/Write After reset Function R 0 R 0 "0" is read. UX R 0 UM R/W 0 3 2 1 0 ERL EXL IE R R/W 0 1 Operating "0" is read. Error R/W 0 R/W 0 Exception Level: Level: Set when Set when a Reset or an exception NMI exception other than is taken. Reset and (Note 1) NMI exception s is taken. (Note 2) Mode: 0: Kernel mode 1: User mode Write "0". bit Symbol 15 14 13 12 11 10 9 8 IM7 IM6 R/W 0 IM5 R/W 0 IM4 IM3 IM2 IM1 R/W 0 R/W 0 R/W 0 R/W 0 IM0 R/W 0 Read/Write R/W After reset 0 Function Write "000". Interrupt Mask: (for hardware Interrupt Mask: (for interrupt) software interrupt) Write "111". 23 22 bit Symbol PX BEV Read/Write R R/W After reset 0 1 Function "0" is read. Vector 21 20 TS R 0 "0" is read. SR R 0 address for Bootstrap Exception 1: Set in internal ROM 0: Set in external memory (Note 4) 31 30 29 28 bit Symbol CU3 CU2 Read/Write After reset R/W Undefine d CP3 availability 0: Unavailabl e 1: Available Write "0". R/W Undefine d CP2 availability 0: Unavailabl e 1: Available Write "0". CU1 R/W Undefine d CP1 availability 0: Unavailabl e 1: Available Write "1" for using FPU. Function Exceptions/Interrupts Interrupt Enable: 0: Interrupts are disabled. 1: Interrupts are enabled. (Note 3) Write "1". 19 18 NMI R/W R 0 0 "0" is read. NMI interrupt 1: Generated 0: Not generated (Note 5) 17 16 Impl R 0 0 27 26 25 24 CU0 RP FR RE MX R/W Undefine d CP0 availability 0: Unavailabl e 1: Available (Note 6) R/W 0 R 0 R 0 R 0 Low-power "0" is read. consumptio n mode 0: Halt 1: Doze Specifies core mode in IDLE mode. TMP19A44(rev1.3) 6-48 "0" is read. "0" is read. 2010-04-01 TMP19A44 (Note 1) When this bit is set: The processor is running is Kernel mode. Interrupts are disabled. The ERET instruction will use the return address held in the ErrorEPC register. (Note 2) When this bit is set: The processor is running in Kernel mode. Interrupts are disabled. The EPC register and the BD bit in the Cause register will not be updated if another exception is taken. (Note 3) The IE bit is not automatically set or cleared by the interrupt response sequence or the ERET instruction. (This bit is cleared upon reset.) (Note 4) An interrupt vector address differs depending on combination of the BEV bit in the Status register and the IV bit in the Cause register. IV = 0 IV = 1 BEV = 0 0x8000_0180 0x8000_0200 BEV = 1 0xBFC0_0380 0xBFC0_0400 (Note 5) Writing 0 clears this bit. Writing 1 to this bit is ignored. (Note 6) Write "1" when using CP0 in user mode. In Kernel mode, CP0 is always available, regardless of the value of the CU0 bit. Exceptions/Interrupts TMP19A44(rev1.3) 6-49 2010-04-01 TMP19A44 6.6.2.3 Cause Register The Cause register indicates the cause of the last exception. 7 Cause bit Symbol (No.13) Read/Write After reset Function 6 5 4 3 2 1 0 0 "0" is read. 0 ExcCode R R 0 0 0 0 0 "0" is read. Exception code 00000: Interrupt (software and hardware) 00100: Address Error (instruction fetch or load) 00101: Address Error (store access) 00110: Bus Error (instruction fetch) 00111: Bus Error (data access: load) 01000: System Call exception 01001: Breakpoint exception 01010: Reserved Instruction exception 01011: Coprocessor Unusable exception 01100: Integer Overflow exception 01101: Trap exception R 0 15 14 13 12 11 10 9 8 bit Symbol IP7 IP3 IP2 IP1 R Undefine d IP5 R Undefine d IP4 Read/Write After reset IP6 R Undefine d R Undefine d R Undefine d R Undefine d R/W Undefine d IP0 R/W Undefine d Function Interrupt Request (Hardware) Interrupt (Software) Interrupt level is set in IP[4:2] when hardware interrupt is requested. Request Write "1" for using software interrupt. bit Symbol Read/Write After reset Function 23 22 21 20 19 IV R/W Undefine d Interrupt vector 1:Different from exception vector 0:Same as exception vector (Note 1) WP R 0 0 0 0 31 30 bit Symbol BD Read/Write After reset R Undefine d Function 18 17 16 0 0 0 27 26 25 24 0 0 0 0 R "0" is read. R 0 29 28 CE1 CE0 R Undefined R Set when "0" is read. an exception occurred in a jump or branch delay slot. Indicates the "0" is read. coprocessor unit number referenced when a Coprocessor Unusable exception was taken. (Note 2) (Note 3) (Note 1) An interrupt vector address differs depending on combination of the BEV bit in the Status register and the IV bit in the Cause register. See Note 4 in the Status register section. (Note 2) The processor updates the BD bit only if the EXL bit is 0 when an interrupt or exception occurred. (Note 3) The value in this field is undefined for any other exception. Exceptions/Interrupts TMP19A44(rev1.3) 6-50 2010-04-01 TMP19A44 6.6.2.4 EPC Register Reading/ writing is available with the EPC register. When an exception/ instruction other than RESET/ NMI occurs, the EPC register stores its address. (If the instruction in the branch slot causes an exception/ interrupt, the address of the precedent branch instruction is stored. ) When an exception/ instruction other than RESET/ NMI is generated, Status<EXL> bit is set to "1". If "1" is set, the normal operation restarts from the address set in the EPC register in executing ERET instruction. The processor does not write to the EPC register when the EXL bit in the Status register is set to "1". 7 6 5 4 3 2 EPC bit Symbol EPC (No.14) Read/Write After reset Function R/W Undefined Exception Program Counterbit 7~0 15 14 bit Symbol 23 22 bit Symbol Read/Write After reset Function 11 10 9 8 21 20 19 18 17 16 25 24 EPC R/W Undefined Exception Program Counterbit 23~16 31 Exceptions/Interrupts 12 0 EPC R/W Undefined Exception Program Counterbit 15~8 Read/Write After reset Function bit Symbol Read/Write After reset Function 13 1 30 29 28 27 26 EPC R/W Undefined Exception Program Counterbit 31~24 TMP19A44(rev1.3) 6-51 2010-04-01 TMP19A44 6.6.2.5 ErrorEPC Register Reading/ writing is available with the EPC register. When an exception/ instruction other than RESET/ NMI occurs, the EPC register stores its address. (If the instruction in the branch slot causes an exception/ interrupt, the address of the precedent branch instruction is stored). When an exception/ instruction other than RESET/ NMI is generated, Status<EXL> bit is set to "1". If "1" is set, the normal operation restarts from the address set in the EPC register in executing ERET instruction. 7 6 5 4 3 2 ErrorEPC bit Symbol ErrorEPC (No.30) Read/Write After reset Function R/W Undefined Error Exception Program Counterbit 7~0 15 14 bit Symbol 23 22 bit Symbol Read/Write After reset Function 11 10 9 8 21 20 19 18 17 16 25 24 ErrorEPC R/W Undefined Error Exception Program Counterbit 23~16 31 Exceptions/Interrupts 12 0 ErrorEPC R/W Undefined Error Exception Program Counterbit 15~8 Read/Write After reset Function bit Symbol Read/Write After reset Function 13 1 30 29 28 27 26 ErrorEPC R/W Undefined Error Exception Program Counterbit 31~24 TMP19A44(rev1.3) 6-52 2010-04-01 TMP19A44 6.6.2.6 Shadow Register Set Control Register: SSCR Register 7 SSCR bit Symbol (No.22 or 9:SEL6) Read/Write After reset 0 Function "0" is read. 15 6 5 4 R bit Symbol Read/Write After reset Function 0 0 14 13 12 R 0 0 0 23 22 21 20 0 0 0 0 0 CSS0 0 11 10 9 8 PSS3 PSS2 PSS1 PSS0 19 18 17 16 0 0 0 0 27 26 25 24 R "0" is read. 30 29 28 SSD Read/Write R/W After reset 1 Function Shadow Register Set 0: Enabled 1: Disabled Exceptions/Interrupts 1 CSS1 R/W Undefined Previous Shadow Register Set x000: Main GPRs x001: Shadow Register 1 x010: Shadow Register 2 x011: Shadow Register 3 x100: Shadow Register 4 x101: Shadow Register 5 x110: Shadow Register 6 x111: Shadow Register 7 0 "0" is read. 31 bit Symbol 2 CSS2 R/W 0 0 0 Current Shadow Register Set x000: Main GPRs x001: Shadow Register 1 x010: Shadow Register 2 x011: Shadow Register 3 x100: Shadow Register 4 x101: Shadow Register 5 x110: Shadow Register 6 x111: Shadow Register 7 0 bit Symbol Read/Write After reset Function 3 CSS3 R 0 "0" is read. TMP19A44(rev1.3) 6-53 2010-04-01 TMP19A44 (Note 1) When the processor accepts an interrupt request from the interrupt controller, the value of the CSS field is copied to the PSS field, and the CSS field is updated with the value of the new interrupt request level. (Note 2) On an ERET, the value of the PSS field is restored to the CSS field. (Note 3) The instruction that modifies the contents of the SSCR register must be followed by two NOPs to avoid pipeline hazards. Ex.) MTC0 r18, SSCR NOP NOP ADD r19, r12, r13 (Note 4) When the SSD bit is set, the Shadow Register Set is not updated by any interruptions. (Note 5) When the SSD bit is set, only shadow set 0 is accessible, and the value of the CSS field is ignored. (Note 6) The following shows how the SSCR register operates in generating an interrupt or in returning from an interrupt. Before interrupt PSS CSS xxx 2 Interrupt level = 5 After interrupt 2 5 After returning from interrupt 2 2 (ERET instruction) Exceptions/Interrupts TMP19A44(rev1.3) 6-54 2010-04-01 TMP19A44 6.6.2.7 IER Register The IER register is used to set or clear the IE bit in the Status register. Writing "0" to the IER register causes the IE bit in the Status register to be cleared. Writing a value other than "0" to the IER register causes the IE bit to be set. 7 6 5 4 3 2 IER bit Symbol IER (No.9:SEL7) Read/Write After reset Function R/W Undefined Interrupt Enable Registerbit 7~0 15 14 bit Symbol 23 22 bit Symbol Read/Write After reset Function 11 10 9 8 21 20 19 18 17 16 25 24 IER R/W Undefined Interrupt Enable Registerbit 23~16 31 Exceptions/Interrupts 12 0 IER R/W Undefined Interrupt Enable Registerbit 15~8 Read/Write After reset Function bit Symbol Read/Write After reset Function 13 1 30 29 28 27 26 IER R/W Undefined Interrupt Enable Registerbit 31~24 TMP19A44(rev1.3) 6-55 2010-04-01 TMP19A44 6.6.3 Clock Generator Register 6.6.3.1 INTCG register (STOP/SLEEP/IDLE clear interrupt) 7 IMCGA bit Symbol Read/Write After reset Function 15 23 After reset Function Read/Write After reset Function 3 2 EMST0 1 EMST0 0 14 13 12 11 10 EMCG1 2 EMCG1 1 EMCG1 0 EMST1 1 EMST1 0 22 21 20 19 18 EMCG22 EMCG2 1 EMCG2 0 EMST2 1 EMST2 0 R R/W R 30 EMCG3 2 1 0 INT0EN R R/W 0 0 "0" is read. INT0 clear input 0: Disable 1: Enable 9 8 INT1EN R R/W 0 0 "0" is read. INT1 clear input 0: Disable 1: Enable 17 16 INT2EN R 0 0 1 0 0 0 "0" is read. Active state setting of INT2 standby Active state of INT2 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges 31 bit Symbol 4 EMCG0 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT1 standby Active state of INT1 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges bit Symbol Read/Write 5 EMCG0 1 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT0 standby Active state of INT0 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges bit Symbol Read/Write After reset Function 6 EMCG0 2 29 28 27 26 EMCG3 1 EMCG3 0 EMST3 1 EMST3 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT3 standby Active state of INT3 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges R/W 0 0 "0" is read. INT2 clear input 0: Disable 1: Enable 25 24 INT3EN R R/W 0 0 "0" is read. INT3 clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-56 2010-04-01 TMP19A44 7 IMCGB bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 3 2 EMST4 1 EMST4 0 14 13 12 11 10 EMCG52 EMCG5 1 EMCG5 0 EMST5 1 EMST5 0 22 21 20 19 18 EMCG62 EMCG6 1 EMCG6 0 EMST6 1 EMST6 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT6 standby Active state of INT6 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges 31 bit Symbol 4 EMCG4 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT5 standby Active state of INT5 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges 23 Read/Write After reset Function 5 EMCG4 1 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT4 standby Active state of INT4 standby clear request clear request (101~111: setting prohibited) 00: 000: "L" level 01: Rising edge 001: "H" level 10: Falling edge 010: Falling edge 11: Both edges 011: Rising edge 100: Both edges bit Symbol Read/Write After reset Function 6 EMCG4 2 30 29 28 27 26 EMCG7 2 EMCG7 1 EMCG7 0 EMST7 1 EMST7 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT7 standby Active state of INT7 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges 1 0 INT4EN R R/W 0 0 "0" is read. INT4 clear input 0: Disable 1: Enable 9 8 INT5EN R R/W 0 0 "0" is read. INT5 clear input 0: Disable 1: Enable 17 16 INT6EN R R/W 0 0 "0" is read. INT6 Clear input 0: Disable 1: Enable 25 24 INT7EN R R/W 0 0 "0" is read. INT7 Clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-57 2010-04-01 TMP19A44 7 IMCGC bit Symbol Read/Write After reset Function 15 23 After reset Function Read/Write After reset Function 3 2 EMST8 1 EMST8 0 14 13 12 11 10 EMCG9 2 EMCG9 1 EMCG9 0 EMST9 1 EMST9 0 22 21 20 19 18 EMCGA 2 EMCGA 1 EMCGA 0 EMSTA 1 EMSTA 0 R R/W R 1 0 INT8EN R R/W 0 0 "0" is read. INT8 clear input 0: Disable 1: Enable 9 8 INT9EN R R/W 0 0 "0" is read. INT9 clear input 0: Disable 1: Enable 17 16 INTAEN R 0 0 1 0 0 0 "0" is read. Active state setting of INTA standby Active state of INTA clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges 31 bit Symbol 4 EMCG8 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT9 standby Active state of INT9 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges bit Symbol Read/Write 5 EMCG8 1 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INT8 standby Active state of INT8 clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges bit Symbol Read/Write After reset Function 6 EMCG8 2 30 29 28 27 26 EMCGB 2 EMCGB 1 EMCGB 0 EMSTB 1 EMSTB 0 R R/W R 0 0 1 0 0 0 "0" is read. Active state setting of INTB standby Active state of INTB clear request. (101~111: setting standby clear request prohibited) 000: "L" level 00: 001: "H" level 01: Rising edge 010: Falling edge 10: Falling edge 011: Rising edge 11: Both edges 100: Both edges R/W 0 0 "0" is read. INTA clear input 0: Disable 1: Enable 25 24 INTBEN R R/W 0 0 "0" is read. INTB clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-58 2010-04-01 TMP19A44 7 IMCGD bit Symbol Read/Write After reset Function 6 5 4 EMCGC 2 EMCGC 1 EMCGC 0 R R/W 0 0 1 0 "0" is read. Active state setting of KWUP standby clear request. 3 2 1 R Undefined value is read. R R/W 0 0 "0" is read. KWUP clear input Set it as shown below. 001: "H" level 15 bit Symbol Read/Write After reset Function 0: Disable 1: Enable 14 13 12 EMCGD 2 EMCGD 1 EMCGD 0 R R/W 0 0 1 0 "0" is read. Active state setting of INTRTC standby clear request. 11 10 9 bit Symbol Read/Write After reset Function R Undefined value is read. R R/W 0 0 "0" is read. INTRTC clear input 0: Disable 1: Enable 22 21 20 EMCGE 2 EMCGE 1 EMCGE 0 R 19 18 17 R R Undefined value is read. R/W 0 0 "0" is read. PHCNT0 clear input Set it as shown below. 011: Rising edge 31 Read/Write After reset Function R 16 PHCNT0 EN R/W 0 0 1 0 "0" is read. Active state setting of PHCNT0 standby clear request. bit Symbol 8 INTRTCE N Set it as shown below. 010: Falling edge 23 0 KWUPE N 0: Disable 1: Enable 30 29 28 EMCGF 2 EMCGF 1 EMCGF 0 27 25 24 PHCNT1 EN R/W 0 0 1 0 "0" is read. Active state setting of PHCNT1 standby clear request. 26 R Undefined value is read. Set it as shown below. 011: Rising edge R R/W 0 0 "0" is read. PHCNT1 clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-59 2010-04-01 TMP19A44 7 IMCGE bit Symbol Read/Write After reset Function 6 5 4 EMCG1 02 EMCG1 01 EMCG1 00 R R/W 0 0 1 0 "0" is read. Active state setting of PHCNT2 standby clear request. 3 2 1 R Undefined value is read. R R/W 0 0 "0" is read. PHCNT2 clear input Set it as shown below. 011: Rising edge 15 bit Symbol Read/Write After reset Function 0: Disable 1: Enable 14 13 12 EMCG1 12 EMCG1 11 EMCG1 10 R R/W 0 0 1 0 "0" is read. Active state setting of PHCNT3 standby clear request. 11 10 9 bit Symbol Read/Write After reset Function R Undefined value is read. R R/W 0 0 "0" is read. PHCNT3 clear input 0: Disable 1: Enable 22 21 20 EMCG1 22 EMCG1 21 EMCG1 20 R 19 18 17 R R Undefined value is read. R/W 0 0 "0" is read. PHCNT4 clear input Set it as shown below. 011: Rising edge 31 Read/Write After reset Function R 16 PHCNT4 EN R/W 0 0 1 0 "0" is read. Active state setting of PHCNT4 standby clear request. bit Symbol 8 PHCNT3 EN Set it as shown below. 011: Rising edge 23 0 PHCNT2 EN 0: Disable 1: Enable 30 29 28 EMCG1 32 EMCG1 31 EMCG1 30 27 25 24 PHCNT5 EN R/W 0 0 1 0 "0" is read. Active state setting of PHCNT5 standby clear request. 26 R Undefined value is read. Set it as shown below. 011: Rising edge R R/W 0 0 "0" is read. PHCNT5 clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-60 2010-04-01 TMP19A44 7 IMCGF bit Symbol Read/Write After reset Function 15 23 After reset Function Read/Write After reset Function 3 2 EMCG1 42 EMCG1 41 EMCG1 40 EMST1 41 EMST1 40 R 0 0 Active state of INT10 standby clear request 14 13 12 11 10 EMCG1 51 EMCG1 50 EMST1 51 EMST1 50 R 0 0 Active state of INT11 standby clear request 22 21 20 19 18 EMCG1 61 EMCG1 60 EMST1 61 EMST1 60 R/W R R R/W 0 0 "0" is read. INT10 clear input 0: Disable 1: Enable 9 8 INT11E N R R/W 0 0 "0" is read. INT11 clear input 0: Disable 1: Enable 17 16 INT12E N R 0 0 Active state of INT12 standby clear request R/W 0 0 "0" is read. INT12 clear input 00: 01: Rising edge 10: Falling edge 11: Both edges 30 29 28 27 26 EMCG1 72 EMCG1 71 EMCG1 70 EMST1 71 EMST1 70 R R/W 0 0 1 0 "0" is read. Active state setting of INT13 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 0 INT10E N 00: 01: Rising edge 10: Falling edge 11: Both edges EMCG16 2 0 0 1 0 "0" is read. Active state setting of INT12 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 1 00: 01: Rising edge 10: Falling edge 11: Both edges EMCG1 52 R 31 bit Symbol 4 R R/W 0 0 1 0 "0" is read. Active state setting of INT11 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges bit Symbol Read/Write 5 R R/W 0 0 1 0 "0" is read. Active state setting of INT10 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges bit Symbol Read/Write After reset Function 6 R 0 0 Active state of INT13 standby clear request 00: 01: Rising edge 10: Falling edge 11: Both edges 0: Disable 1: Enable 25 24 INT13E N R R/W 0 0 "0" is read. INT13 clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-61 2010-04-01 TMP19A44 7 IMCG10 bit Symbol Read/Write After reset Function 15 23 Read/Write After reset Function 3 2 EMST1 81 EMST1 80 R 0 0 Active state of INT14 standby clear request 14 13 12 11 10 EMCG1 91 EMCG1 90 EMST1 91 EMST1 90 R 0 0 Active state of INT15 standby clear request 22 21 20 19 18 EMCG1 A1 EMCG1 A0 EMST1 A1 EMST1 A0 R 0 0 Active state of INT16 standby clear request R R/W 0 0 "0" is read. INT14 clear input 0: Disable 1: Enable 9 29 28 27 26 EMCG1 B2 EMCG1 B1 EMCG1 B0 EMST1 B1 EMST1 B0 R 0 0 Active state of INT17 standby clear request 00: 01: Rising edge 10: Falling edge 11: Both edges 8 INT15EN R R/W 0 0 "0" is read. INT15 clear input 0: Disable 1: Enable 17 16 INT16E N R R/W 0 0 "0" is read. INT16 clear input 00: 01: Rising edge 10: Falling edge 11: Both edges 30 0 INT14E N 00: 01: Rising edge 10: Falling edge 11: Both edges EMCG1A 2 R R/W 0 0 1 0 "0" is read. Active state setting of INT17 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 1 00: 01: Rising edge 10: Falling edge 11: Both edges EMCG19 2 R R/W 0 0 1 0 "0" is read. Active state setting of INT16 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 31 bit Symbol 4 EMCG1 80 R R/W 0 0 1 0 "0" is read. Active state setting of INT15 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges bit Symbol Read/Write After reset Function 5 EMCG1 81 R R/W 0 0 1 0 "0" is read. Active state setting of INT14 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges bit Symbol Read/Write After reset Function 6 EMCG1 82 0: Disable 1: Enable 25 24 INT17EN R R/W 0 0 "0" is read. INT17 clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-62 2010-04-01 TMP19A44 7 IMCG11 bit Symbol Read/Write After reset Function 15 23 After reset Function Read/Write After reset Function 3 2 EMST1 C1 EMST1 C0 R 0 0 Active state of INT18 standby clear request 14 13 12 11 10 EMCG1 D1 EMCG1 D0 EMST1 D1 EMST1 D0 R 0 0 Active state of INT19 standby clear request 22 21 20 19 18 EMCG1 E1 EMCG1 E0 EMST1 E1 EMST1 E0 R/W R R R/W 0 0 "0" is read. INT18 clear input 0: Disable 1: Enable 9 8 INT19E N R R/W 0 0 "0" is read. INT19 clear input 0: Disable 1: Enable 17 16 INT1AE N R 0 0 Active state of INT1A standby clear request R/W 0 0 "0" is read. INT1A clear input 00: 01: Rising edge 10: Falling edge 11: Both edges 30 29 28 27 26 EMCG1 F2 EMCG1 F1 EMCG1 F0 EMST1 F1 EMST1 F0 R R/W 0 0 1 0 "0" is read. Active state setting of INT1B standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 0 INT18EN 00: 01: Rising edge 10: Falling edge 11: Both edges EMCG1 E2 0 0 1 0 "0" is read. Active state setting of INT1A standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 1 00: 01: Rising edge 10: Falling edge 11: Both edges EMCG1 D2 R 31 bit Symbol 4 EMCG1 C0 R R/W 0 0 1 0 "0" is read. Active state setting of INT19 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges bit Symbol Read/Write 5 EMCG1 C1 R R/W 0 0 1 0 "0" is read. Active state setting of INT18 standby clear request. (101~111: setting prohibited) 000: "L" level 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges bit Symbol Read/Write After reset Function 6 EMCG1 C2 R 0 0 Active state of INT1B standby clear request 00: 01: Rising edge 10: Falling edge 11: Both edges 0: Disable 1: Enable 25 24 INT1BE N R R/W 0 0 "0" is read. INT1B clear input 0: Disable 1: Enable (Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing standby. (Note 2) Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-63 2010-04-01 TMP19A44 Be sure to set active state of the clear request if interrupt is enabled for clearing the STOP/ IDLE / SLEEP standby modes. (Note 1) When using interrupts, be sure to follow the sequence of actions shown below: 1) If shared with other general ports, enable the target interrupt input. 2) Set conditions such as active state upon initialization. 3) Clear interrupt requests. 4) Enable interrupts. (Note 2) Settings must be performed while interrupts are disabled. (Note 3) For clearing the STOP modes with TMP19A44, 32 interrupt factors (INT0 through INTB INT10 through INT1B, PHCNT0 through PHCNT5 and KWUP) are available. You can use CG for selecting edge/level of active state and judging whether the aforementioned factors are to be used for clearing the STOP/ SLEEP/ IDLE modes. (Note 4) Among the above 12 factors to be assigned as the STOP/IDLE mode clear request interrupts, INT0 to INTF and INT10 to INT1F can be used as a normal interrupt without setting CG. Select level or edge with INTC. Setting CG is required when using an interrupt of both edges. The interrupt factors excluding other than the assigned as the STOP/ IDLE clear request factors need to be set to the INTC block. Exceptions/Interrupts TMP19A44(rev1.3) 6-64 2010-04-01 TMP19A44 6.6.3.2 INTCG Clear Register 7 ICRCG 6 5 bit Symbol 3 2 1 0 ICRCG3 ICRCG2 W ICRCG1 ICRCG0 0 0 0 0 0 R Read/Write After reset Function 4 ICRCG4 0 "0" is read. 15 Clear interrupt request. "0" is read. 14 13 0_0000: INT0 0_1000: INT8 0_0001: INT1 0_1001: INT9 1_0000: PHCNT2 1_1000: INT14 1_0001: PHCNT3 1_1001: INT15 0_0010: INT2 0_1010: INTA 1_0010: PHCNT4 1_1010: INT16 0_0011: INT3 0_1011: INTB 1_0011: PHCNT5 1_1011: INT17 0_0100: INT4 0_1100: KWUP 0_0101: INT5 0_1101: INTRTC 1_0101: INT11 1_1101: INT19 1_0100: INT10 1_1100: INT18 0_0110: INT6 0_1110: PHCNT0 1_0110: INT12 1_1110: INT1A 0_0111: INT7 0_1111: PHCNT1 1_0111: INT13 1_1111: INT1B 12 11 10 9 8 18 17 16 26 25 24 bit Symbol Read/Write R 0 After reset "0" is read. Function 23 22 21 20 31 30 29 28 19 bit Symbol Read/Write After reset "0" is read. Function 27 bit Symbol Read/Write After reset Function R 0 "0" is read. (Note) The following describes how to clear an interrupt request of the above 32 factors assigned to STOP/SLEEP/IDLE clear request. a) If the factor is used to clear an interrupt. KWUP: use KWUPCLR. INT0 through INTB, INT10 through INT1B, INTRTC and PHCNT0 through PHCNT5: use the ICRCG register in the CGblockshown above. b) If the factor is used to clear an interrupt. Clear the interrupt factor by INTCLR. Exceptions/Interrupts TMP19A44(rev1.3) 6-65 2010-04-01 TMP19A44 6.6.3.3 NMI Flag Register NMIFLG 7 6 5 4 0 0 0 3 2 1 0 NMIFLG0 0 0 0 0 bit Symbol Read/Write After reset Function R 0 "0" is read. NMI factor generation flag 0: not applicable 1: generated from WDT 15 14 13 12 0 0 0 0 11 10 9 8 0 0 0 0 19 18 17 16 0 0 0 0 27 26 25 24 0 0 0 0 bit Symbol R Read/Write After reset "0" is read. Function 23 22 21 20 0 0 0 0 bit Symbol R Read/Write After reset "0" is read. Function 31 30 29 28 0 0 0 0 bit Symbol R Read/Write After reset Function "0" is read. (Note) <NMIFLG0> are cleared to "0" when they are read. Exceptions/Interrupts TMP19A44(rev1.3) 6-66 2010-04-01 TMP19A44 6.6.4 Interrupt Controller Register 6.6.4.1 Interrupt Vector Registers (IVR) For an interrupt generated, the IVR register indicates the interrupt vector address of the corresponding interrupt factor. When an interrupt request is accepted, the corresponding value as listed in Table 6.5 is set to IVR [8:0]. By setting the base address of interrupt vectors to IVR [31:7], a read/write register, simply reading the IVR value can provide the corresponding interrupt vector address. Interrupt Vector Register IVR bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function Exceptions/Interrupts 7 IVR7 6 IVR6 5 IVR5 4 IVR4 0 0 0 0 3 IVR3 2 IVR2 0 0 1 IVR1 0 IVR0 0 0 R The vector of the interrupt factor generated is set. 15 IVR15 14 IVR14 13 IVR13 0 0 0 12 IVR12 R/W 0 Always reads "0". 11 IVR11 10 IVR10 9 IVR9 0 0 0 8 IVR8 R 0 The vector of the interrupt factor generate d is set. 23 IVR23 22 IVR22 21 IVR21 0 0 0 31 IVR31 30 IVR30 29 IVR29 0 0 0 20 19 IVR20 IVR19 R/W 0 0 18 IVR18 17 IVR17 16 IVR16 0 0 0 28 27 IVR28 IVR27 R/W 0 0 26 IVR26 25 IVR25 24 IVR24 0 0 0 TMP19A44(rev1.3) 6-67 2010-04-01 TMP19A44 6.6.4.2 Interrupt Level Register (ILEV) ILEV is the register to control the interrupt level to be used by INTC in notifying interrupt requests to the TX19A/ H1 processor core. Interrupts with interrupt levels not higher than ILEV <CMASK> are suspended. The interrupt priority level "7" is the highest priority and "1" the lowest. Note that any interrupt with interrupt level 0 is not suspended. When a new interrupt is generated, the corresponding interrupt level is stored in <CMASK> and any previously stored values are incremented in mask levels such that the previous CMASK is saved in PMASK0 and PMASK0 is saved in PMASK1 and so on. For writing a new value to <CMASK>, set "1" to <MLEV> and write <CMASK> simultaneously. Writing a new value to <PMASKx> cannot be made. When <MLEV> is set to "0," the interrupt mask levels in the register shift back to the previous state such that PMASK0 is moved to CMASK and PMASK1 is moved to PMASK0, and so on. The last <PMASK6> is set to "000." If it is used in returning from an interrupt process, be sure to set <MLEV> to "0" before executing the ERET instruction. <MLEV> always reads "0." Interrupt Level Register ILEV bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 7 6 0 5 PMASK0 R 000 4 3 0 Interrupt mask level (previous) 0 15 14 13 PMASK2 2 1 CMASK R/W 000 0 Interrupt mask level (current) 12 11 10 9 PMASK1 8 R 0 000 0 Interrupt mask level (previous) 23 22 21 PMASK4 2 000 Interrupt mask level (previous) 20 19 18 17 PMASK3 1 16 R 0 000 0 Interrupt mask level (previous) 31 MLEV W 0 0: Return mask level 30 29 PMASK6 4 28 27 R 0 000 Interrupt mask level (previous) 6 000 Interrupt mask level (previous) 26 25 PMASK5 3 24 000 Interrupt mask level (previous) 5 1: Change CMASK (Note 1) This register must be 32-bit accessed. (Note 2) Please set the mask level and <MLEV> individually. (Note 3) Be sure to read the IVR value before changing the ILEV value. If the ILEV value is changed before reading IVR, an unexpected interrupt request may be generated. (Note 4) Bit manipulation instructions cannot be used to access this register. Exceptions/Interrupts TMP19A44(rev1.3) 6-68 2010-04-01 TMP19A44 Interrupt is generated. PMAS PMAS PMAS PMAS PMAS PMAS PMAS CMAS PMAS PMAS PMAS PMAS PMAS PMAS PMAS CMAS PMAS PMAS PMAS PMAS PMAS PMAS PMAS CMAS New interrupt level "000" <MLEV>=0 6.6.4.3 Interrupt mode control register (IMCxx) IMCxx is comprised of <Ilxxx>, which determines the interrupt levels of individual interrupt factors, <DMxx>, which is used to set activation factors of DMA transfer, and <EIMXX>, which determines active state of interrupt requests. Exceptions/Interrupts TMP19A44(rev1.3) 6-69 2010-04-01 TMP19A44 IMC00 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 22 21 20 19 18 17 16 EIM020 DM02 IL022 IL021 IL020 bit Symbol Read/Write After reset Function R "0" is read. bit Symbol Read/Write After reset Function R "0" is read. 23 bit Symbol Read/Write After reset Function EIM021 R R/W R/W 0 0 0 0 "0" is read. Selects active state of Set as DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 11: Rising edge 1: Interrupt CG setting "01". number 2 R R/W 0 0 0 0 "0" is read. If DM02 = 0, select the interrupt level for interrupt number 2 (INT0). 000: Disable Interrupt 001-111: 1-7 If DM02 = 1, select the DMAC channel. 000 to 111: 0 to 7 is set as the activation factor. 31 bit Symbol Read/Write After reset Function 30 EIM031 R R/W 29 28 EIM030 DM03 R/W 0 0 0 0 "0" is read. Selects active state of Set as DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 3 CG setting "01". is set as the activation factor. Exceptions/Interrupts TMP19A44(rev1.3) 6-70 27 R 26 25 24 IL032 IL031 IL030 R/W 0 0 0 0 "0" is read. If DM03 = 0, select the interrupt level for interrupt number 3 (INT1). 000: Disable Interrupt 001-111: 1-7 If DM03 = 1, select the DMAC channel. 000 to 111: 0 to 7 2010-04-01 TMP19A44 7 IMC01 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM041 EIM040 DM04 R/W 0 3 R/W 0 0 Set as "0" is read. Selects active state of DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: 11: Rising edge Interrupt CG setting "01". number 3 bit Symbol Read/Write After reset Function 14 EIM051 R 13 12 EIM050 DM05 R/W 000 to 111: 0 to 7 11 R/W Read/Write R After reset 0 Function 22 21 20 EIM061 EIM060 DM06 R/W 0 19 R/W Read/Write After reset Function R 0 "0" is read. 30 29 28 EIM070 DM07 R/W IL051 IL050 R/W 18 17 16 IL062 IL061 IL060 R/W 0 0 0 0 "0" is read. If DM6 = 0, select the interrupt level for interrupt number 6 (INT4). 000: Disable Interrupt 001-111: 1-7 If DM6 = 1, select the DMAC channel. 000 to 111: 0 to 7 27 R 26 25 24 IL072 IL071 IL070 R/W 0 0 0 0 "0" is read. If DM7 = 0, select the interrupt level for interrupt number 7 (INT5). 000: Disable Interrupt 001-111: 1-7 If DM7 = 1, select the DMAC channel. the activation factor. Exceptions/Interrupts IL052 R R/W 0 0 0 Selects active state of Set as DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 3 CG setting "01". is set as 8 000 to 111: 0 to 7 0 EIM071 9 0 0 0 0 "0" is read. If DM5 = 0, select the interrupt level for interrupt number 5 (INT3). 000: Disable Interrupt 001-111: 1-7 If DM5 = 1, select the DMAC channel. the activation factor. 31 10 R 0 "0" is read. Selects active state of Set as DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 3 CG setting "01". is set as bit Symbol R/W 0 0 0 If DM4 = 0, "0" is read. select the interrupt level for interrupt number 4 (INT2). 000: Disable Interrupt 001-111: 1-7 If DM4 = 1, select the DMAC channel. the activation factor. 23 0 IL040 0 0 0 0 0 "0" is read. Selects active state of Set as DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 3 CG setting "01". is set as bit Symbol 1 IL041 R is set as the activation factor. 15 2 IL042 TMP19A44(rev1.3) 6-71 000 to 111: 0 to 7 2010-04-01 TMP19A44 7 IMC02 bit Symbol Read/Write After reset Function 6 EIM081 R 0 "0" is read. 5 4 EIM080 DM08 R/W R/W 3 2 1 0 IL082 IL081 IL080 R R/W 0 0 0 0 0 0 0 Selects active state of Set as "0" is read. If DM8 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 8 (INT6). 00: "L" level factor. 0: Non000: Disable Interrupt 01: "H" level activation 001-111: 1-7 10: Falling edge factor If DM8 = 1, 1: 11: Rising edge select the DMAC channel. Interrupt CG setting "01". number 8 is 000 to 111: 0 to 7 set as the activation factor. 15 bit Symbol Read/Write R After reset 0 Function "0" is read. 14 13 12 EIM091 EIM090 DM09 R/W 0 R/W 11 10 9 8 IL092 IL091 IL090 R R/W 0 0 0 0 0 0 Selects active state of Set as "0" is read. If DM9 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 9 (INT7). 00: "L" level factor. 0: Non000: Disable Interrupt 01: "H" level activation 001-111: 1-7 10: Falling edge factor If DM9 = 1, 1: Interrupt 11: Rising edge select the DMAC channel. number 9 is CG setting "01". set as the 000 to 111: 0 to 7 activation factor. 23 bit Symbol Read/Write R After reset 0 Function 22 21 20 EIM0A1 EIM0A0 DM0A R/W 0 R/W 19 18 17 16 IL0A2 IL0A1 IL0A0 R R/W 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DMA = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 10 (INT8). 00: "L" level factor. 0: Non000: Disable Interrupt 01: "H" level activation 001-111: 1-7 10: Falling edge factor If DMA = 1, 1: Interrupt 11: Rising edge select the DMAC channel. number 10 CG setting "01". is set as the 000 to 111: 0 to 7 activation factor. 31 bit Symbol Read/Write After reset Function 30 EIM0B1 R 0 "0" is read. R/W 29 28 EIM0B0 DM0B R/W TMP19A44(rev1.3) 6-72 26 25 24 IL0B2 IL0B1 IL0B0 R 0 0 0 0 Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 11 CG setting "01". is set as the activation factor. Exceptions/Interrupts 27 R/W 0 If DMB = 0, 0 0 select the interrupt level for interrupt number 11 (INT9). 000: Disable Interrupt 001-111: 1-7 If DMB = 1, select the DMAC channel. 000 to 111: 0 to 7 2010-04-01 TMP19A44 7 IMC03 bit Symbol Read/Write After reset Function 6 EIM0C1 R 5 4 EIM0C0 DM0C R/W R/W 3 is set as the activation factor. 15 Read/Write R After reset 0 Function 14 13 12 EIM0D1 EIM0D0 DM0D R/W 0 R/W 11 0 activation factor. 23 Read/Write R After reset 0 Function 22 21 20 EIM0E1 EIM0E0 DM0E R/W 0 R/W 19 0 activation factor. bit Symbol Read/Write After reset Function 30 EIM0F1 R R/W 29 28 EIM0F0 DM0F R/W Exceptions/Interrupts 27 TMP19A44(rev1.3) 6-73 IL0C1 IL0C0 R/W 0 If DMC = 0, 0 0 select the interrupt level for interrupt number 12 (INTA). 000: Disable Interrupt 001-111: 1-7 If DMC = 1, select the DMAC channel. 000 to 111: 0 to 7 10 9 8 IL0D2 IL0D1 IL0D0 R/W 0 If DMD = 0, 0 0 select the interrupt level for interrupt number 13 (INTB). 000: Disable Interrupt 001-111: 1-7 If DMD = 1, select the DMAC channel. 000 to 111: 0 to 7 18 17 16 IL0E2 IL0E1 IL0E0 R/W 0 If DME = 0, 0 0 select the interrupt level for interrupt number 14 (INTC). 000: Disable Interrupt 001-111: 1-7 If DME = 1, select the DMAC channel. 000 to 111: 0 to 7 26 25 24 IL0F2 IL0F1 IL0F0 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 15 CG setting "01". is set as the activation factor. IL0C2 R 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 14 CG setting "01". is set as the 31 0 R 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 13 CG setting "01". is set as the bit Symbol 1 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: 11: Rising edge Interrupt CG setting "01". number 12 bit Symbol 2 R/W 0 If DMF = 0, 0 0 select the interrupt level for interrupt number 15 (INTD). 000: Disable Interrupt 001-111: 1-7 If DMF = 1, select the DMAC channel. 000 to 111: 0 to 7 2010-04-01 TMP19A44 7 IMC04 bit Symbol Read/Write After reset Function 6 EIM101 R 0 "0" is read. 5 4 EIM100 DM10 R/W R/W 3 15 0 0 0 0 Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: 11: Rising edge Interrupt CG setting "01". number 16 is Read/Write R After reset 0 Function 14 13 12 EIM111 EIM110 DM11 R/W 0 R/W 11 0 activation factor. 23 Read/Write R After reset 0 Function 22 21 20 EIM121 EIM120 DM12 R/W 0 R/W 19 0 activation factor. bit Symbol Read/Write After reset Function 30 EIM131 R 0 "0" is read. R/W 29 28 EIM130 DM13 R/W 27 IL101 IL100 R/W 0 If DM10 = 0, 0 0 select the interrupt level for interrupt number 16 (INTE). 000: Disable Interrupt 001-111: 1-7 If DM10 = 1, select the DMAC channel. 000 to 111: 0 to 7 10 9 8 IL112 IL111 IL110 R/W 0 If DM11 = 0, 0 0 select the interrupt level for interrupt number 17 (INTF). 000: Disable Interrupt 001-111: 1-7 If DM11 = 1, select the DMAC channel. 000 to 111: 0 to 7 18 17 16 IL122 IL121 IL120 R/W 0 If DM12 = 0, 0 0 select the interrupt level for interrupt number 18 (KWUP). 000: Disable Interrupt 001-111: 1-7 If DM12 = 1, select the DMAC channel. 000 to 111: 0 to 7 26 25 24 IL132 IL131 IL130 R 0 0 0 0 Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 19 CG setting "01". is set as the activation factor. IL102 R 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 18 CG setting "01". is set as the 31 0 R 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 17 CG setting "01". is set as the bit Symbol 1 R set as the activation factor. bit Symbol 2 R/W 0 If DM13= 0, 0 0 select the interrupt level for interrupt number 19 (INT10). 000: Disable Interrupt 001-111: 1-7 If DM13 = 1, select the DMAC channel. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-74 2010-04-01 TMP19A44 7 IMC05 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM141 EIM140 DM14 R/W 0 R/W 3 0 set as the activation factor. bit Symbol Read/Write After reset Function 14 EIM151 R 13 12 EIM150 DM15 R/W R/W 11 activation factor. bit Symbol Read/Write After reset Function 22 EIM161 R 21 20 EIM160 DM16 R/W R/W 19 activation factor. 31 Read/Write After reset Function R 30 29 28 EIM171 EIM170 DM17 R/W R/W 27 0 0 select the interrupt level for interrupt number 20 (INT11). 000: Disable Interrupt 001-111: 1-7 If DM14 = 1, select the DMAC channel. 000 to 111: 0 to 7 10 9 8 IL152 IL151 IL150 R/W 0 If DM15 = 0, 0 0 select the interrupt level for interrupt number 21 (INT12). 000: Disable Interrupt 001-111: 1-7 If DM15 = 1, select the DMAC channel. 000 to 111: 0 to 7 18 17 16 IL162 IL161 IL160 R/W 0 If DM16 = 0, 0 0 select the interrupt level for interrupt number 22 (INT13). 000: Disable Interrupt 001-111: 1-7 If DM16 = 1, select the DMAC channel. 000 to 111: 0 to 7 26 25 24 IL172 IL171 IL170 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 23 is CG setting "01". set as the activation factor. R/W 0 If DM14 = 0, R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 22 CG setting "01". is set as the bit Symbol 0 IL140 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 21 CG setting "01". is set as the 23 1 IL141 R 0 0 Set as "0" is read. Selects active state of "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: 11: Rising edge Interrupt CG setting "01". number 20 is 15 2 IL142 R/W 0 If DM17 = 0, 0 0 select the interrupt level for interrupt number 23 (INT14). 000: Disable Interrupt 001-111: 1-7 If DM17 = 1, select the DMAC channel. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-75 2010-04-01 TMP19A44 7 IMC06 bit Symbol Read/Write R After reset 0 Function "0" is read. 6 5 4 EIM181 EIM180 DM18 R/W 0 R/W 3 0 0 Set as Selects active state of "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: 11: Rising edge Interrupt CG setting "01". number 24 bit Symbol Read/Write After reset Function 14 EIM191 R 0 "0" is read. 13 12 EIM190 DM19 R/W R/W 1 0 IL181 IL180 R 0 is set as the activation factor. 15 2 IL182 11 R/W 0 If DM18 = 0, 0 0 select the interrupt level for interrupt number 24 (INT15). 000: Disable Interrupt 001-111: 1-7 If DM18 = 1, select the DMAC channel. 000 to 111: 0 to 7 10 9 8 IL192 IL191 IL190 R R/W 0 0 0 0 0 0 0 Selects active state of Set as "0" is read. If DM19 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 25 (INT16). 00: "L" level factor. 0: Non000: Disable Interrupt 01: "H" level activation 001-111: 1-7 10: Falling edge factor If DM19 = 1, 1: Interrupt 11: Rising edge select the DMAC channel. number 25 CG setting "01". is set as the 000 to 111: 0 to 7 activation factor. 23 bit Symbol Read/Write After reset Function 22 EIM1A1 R 0 "0" is read. 21 20 EIM1A0 DM1A R/W R/W 19 18 17 16 IL1A2 IL1A1 IL1A0 R R/W 0 0 0 0 0 0 0 Selects active state of Set as "0" is read. If DM1A = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 26 (INT17). 00: "L" level factor. 0: Non000: Disable Interrupt 01: "H" level activation 001-111: 1-7 10: Falling edge factor If DM1A = 1, 1: Interrupt 11: Rising edge select the DMAC channel. number 26 CG setting "01". is set as the 000 to 111: 0 to 7 activation factor. 31 bit Symbol Read/Write After reset Function R 0 "0" is read. 30 29 28 EIM1B1 EIM1B0 DM1B R/W R/W 27 25 24 IL1B1 IL1B0 R 0 0 0 0 Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 27 CG setting "01". is set as the activation factor. 26 IL1B2 R/W 0 If DM1B = 0, 0 0 select the interrupt level for interrupt number 27 (INT18). 000: Disable Interrupt 001-111: 1-7 If DM1B = 1, select the DMAC channel. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-76 2010-04-01 TMP19A44 7 IMC07 bit Symbol Read/Write After reset Function 6 EIM1C1 R 5 4 EIM1C0 DM1C R/W R/W 3 activation factor. 15 Read/Write R After reset 0 Function 14 13 12 EIM1D1 EIM1D0 DM1D R/W 0 R/W 11 0 activation factor. 23 Read/Write R After reset 0 Function 22 21 20 EIM1E1 EIM1E0 DM1E R/W 0 R/W 19 0 activation factor. bit Symbol Read/Write After reset Function 30 EIM1F1 R R/W 29 28 EIM1F0 DM1F R/W 27 IL1C1 IL1C0 R/W 0 If DM1C = 0, 0 0 select the interrupt level for interrupt number 28 (INT19). 000: Disable Interrupt 001-111: 1-7 If DM1C = 1, select the DMAC channel. 000 to 111: 0 to 7 10 9 8 IL1D2 IL1D1 IL1D0 R/W 0 If DM1D = 0, 0 0 select the interrupt level for interrupt number 29 (INT1A). 000: Disable Interrupt 001-111: 1-7 If DM1D = 1, select the DMAC channel. 000 to 111: 0 to 7 18 17 16 IL1E2 IL1E1 IL1E0 R/W 0 If DM1E = 0, 0 0 select the interrupt level for interrupt number 30 (INT1B). 000: Disable Interrupt 001-111: 1-7 If DM1E = 1, select the DMAC channel. 000 to 111: 0 to 7 26 25 24 IL1F2 IL1F1 IL1F0 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 31 is set as the activation factor. IL1C2 R 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 30 is CG setting "01". set as the 31 0 R 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 29 is CG setting "01". set as the bit Symbol 1 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge number 28 is CG setting "01". set as the bit Symbol 2 R/W 0 If DM1F = 0, 0 0 select the interrupt level for interrupt number 31 (INT1C). 000: Disable Interrupt 001-111: 1-7 If DM1F = 1, select the DMAC channel. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-77 2010-04-01 TMP19A44 7 IMC08 bit Symbol Read/Write After reset Function 6 EIM201 R 5 4 EIM200 DM20 R/W R/W 3 number 32 is set as the activation factor. 15 Read/Write R After reset 0 Function 14 13 12 EIM211 EIM210 DM21 R/W 0 R/W 11 Read/Write R After reset 0 Function 22 21 20 EIM221 EIM220 DM26 R/W 0 R/W 19 number 34 is set as the activation factor. bit Symbol Read/Write After reset Function EIM231 R R/W 29 28 EIM230 DM23 R/W IL200 R/W 0 If DM20= 0, 0 0 select the interrupt level for interrupt number 32 (INT1D). 000: Disable Interrupt 001-111: 1-7 If DM20 = 1, select the DMAC channel. 10 9 8 IL212 IL211 IL210 R/W 0 If DM21 = 0, 0 0 select the interrupt level for interrupt number 33 (INT1E). 000: Disable Interrupt 001-111: 1-7 If DM21 = 1, select the DMAC channel. 18 17 16 IL222 IL221 IL220 R 0 30 IL201 000 to 111: 0 to 7 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge 31 IL202 R 0 number 33 is set as the activation factor. 23 0 000 to 111: 0 to 7 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge bit Symbol 1 R 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. DMAC interrupt request. activation 00: "L" level factor. 0: Non01: "H" level activation 10: Falling edge factor 1: Interrupt 11: Rising edge bit Symbol 2 R/W 0 If DM22 = 0, 0 0 select the interrupt level for interrupt number 34 (INT1F). 000: Disable Interrupt 001-111: 1-7 If DM22 = 1, select the DMAC channel. 000 to 111: 0 to 7 27 R 26 25 24 IL232 IL231 IL230 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM23 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 35 (INTRX0). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM23 = 1, 1: Interrupt select the DMAC channel. number 35 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-78 2010-04-01 TMP19A44 7 IMC09 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM241 EIM240 DM24 R/W 0 R/W 3 bit Symbol Function R 14 EIM251 R 13 12 EIM250 DM25 R/W R/W 11 bit Symbol Function 22 EIM261 R 31 Function 8 IL252 IL251 IL250 R/W 21 20 EIM260 DM26 R/W R/W select the DMAC channel. 19 18 17 16 IL262 IL261 IL260 R R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM26 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 38 (INTTX1). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM26 = 1, 1: Interrupt select the DMAC channel. number 38 is bit Symbol After reset 9 R set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM25 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 37 (INTRX1). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM25 = 1, 1: Interrupt 23 After reset R/W 000 to 111: 0 to 7 number 37 is set as the activation factor. Read/Write 0 IL240 0 0 0 0 0 Set as If DM24 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt interrupt request. activation number 36 (INTTX0). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM24 = 1, 1: Interrupt select the DMAC channel. number 36 is 15 After reset 1 IL241 0 set as the activation factor. Read/Write 2 IL242 R 30 29 28 EIM271 EIM270 DM27 R/W R/W 000 to 111: 0 to 7 27 R 26 25 24 IL272 IL271 IL270 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM27 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 39 (INTRX2). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM27 = 1, 1: Interrupt select the DMAC channel. number 39 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-79 2010-04-01 TMP19A44 7 IMC0A bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM281 EIM280 DM28 R/W 0 R/W 3 bit Symbol Function R 14 EIM291 R 0 13 12 EIM290 DM29 R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 23 bit Symbol After reset Function 11 22 EIM2A1 R 0 0 EIM2A0 DM2A R/W 0 31 bit Symbol After reset Function 29 28 EIM2B0 DM2B 0 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". IL291 IL290 R/W 000 to 111: 0 to 7 19 18 17 16 IL2A2 IL2A1 IL2A0 R R/W 0 0 0 0 "0" is read. If DM2A = 0, select the interrupt level for interrupt number 42 (HINTTX0). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM2A = 1, 1: Interrupt select the DMAC channel. number 42 is 30 R/W IL292 0 Set as DMAC activation factor. EIM2B1 R 8 0 0 0 0 "0" is read. If DM29 = 0, select the interrupt level for interrupt number 41 (HINTRX0). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM29 = 1, 1: Interrupt select the DMAC channel. number 41 is 20 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 9 0 Set as DMAC activation factor. 21 R/W 10 R set as the activation factor. Read/Write R/W 000 to 111: 0 to 7 set as the activation factor. Read/Write 0 IL280 0 0 0 0 0 Set as If DM28 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt interrupt request. activation number 40 (INTTX2). 11: Rising edge factor. Non000: Disable Interrupt Be sure to set "11". 0: activation 001-111: 1-7 factor If DM28 = 1, 1: Interrupt select the DMAC channel. number 40 is 15 After reset 1 IL281 0 set as the activation factor. Read/Write 2 IL282 000 to 111: 0 to 7 27 R 26 25 24 IL2B2 IL2B1 IL2B0 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM2B = 0, select the interrupt level for interrupt number 43 (HINTRX1). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM2B = 1, 1: Interrupt select the DMAC channel. number 43 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-80 2010-04-01 TMP19A44 IMC0B bit Symbol EIM2C1 Read/Write R After reset 0 Function EIM2C0 R/W 0 DM2C R/W IL2C2 R 0 0 0 0 0 Set as If DM2C = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt interrupt request. activation number 44 (HINTTX1). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM2C = 1, 1: Interrupt select the DMAC channel. number 44 15 bit Symbol After reset Function 14 EIM2D1 R 13 12 EIM2D0 DM2D R/W R/W 000 to 111: 0 to 7 11 bit Symbol Function 22 EIM2E1 R bit Symbol After reset IL2D2 IL2D1 IL2D0 R/W 21 20 EIM2E0 DM2E R/W R/W 19 18 17 16 IL2E2 IL2E1 IL2E0 R R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM2E = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 46 (HINTTX2). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM2E = 1, 1: Interrupt select the DMAC channel. number 46 31 Function 8 000 to 111: 0 to 7 is set as the activation factor. Read/Write 9 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM2D = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 45 (HINTRX2). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM2D = 1, 1: Interrupt select the DMAC channel. number 45 23 After reset 10 R is set as the activation factor. Read/Write IL2C0 R/W 0 is set as the activation factor. Read/Write IL2C1 30 EIM2F1 R R/W 29 28 EIM2F0 DM2F R/W 000 to 111: 0 to 7 27 R 26 25 24 IL2F2 IL2F1 IL2F0 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM2F = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 47 (INTS0). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM2F = 1, 1: Interrupt select the DMAC channel. number 47 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-81 2010-04-01 TMP19A44 7 IMC0C bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM301 EIM300 DM30 R/W 0 R/W 3 bit Symbol Function R 14 EIM311 R 13 12 EIM310 DM31 R/W R/W 11 bit Symbol Function 22 EIM321 R 31 Function 8 IL312 IL311 IL310 R/W 21 20 EIM320 DM32 R/W R/W 000 to 111: 0 to 7 19 18 17 16 IL322 IL321 IL320 R R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM32 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 50 (INTADHPB). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM32 = 1, 1: Interrupt select the DMAC channel. number 50 bit Symbol After reset 9 R is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM31 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 49 (INTADMA). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM31 = 1, 1: Interrupt select the DMAC channel. number 49 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL300 0 0 0 0 0 Set as If DM30 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt interrupt request. activation number 48 (INTADHPA). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM30 = 1, 1: Interrupt select the DMAC channel. number 48 15 After reset 1 IL301 0 is set as the activation factor. Read/Write 2 IL302 R 30 29 28 EIM331 EIM330 DM33 R/W R/W 000 to 111: 0 to 7 27 R 26 25 24 IL332 IL331 IL330 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM33 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 51 (INTADMB). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM33 = 1, 1: Interrupt select the DMAC channel. number 51 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-82 2010-04-01 TMP19A44 7 IMC0D bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM341 EIM340 DM34 R/W 0 R/W 3 bit Symbol Function R 14 EIM351 R 13 12 EIM350 DM35 R/W R/W 11 bit Symbol Function 22 EIM361 R 0 21 20 EIM360 DM36 R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 31 bit Symbol After reset Function 9 8 IL352 IL351 IL350 R R/W 000 to 111: 0 to 7 19 29 28 EIM370 DM37 0 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 16 IL362 IL361 IL360 R/W 0 0 0 0 "0" is read. If DM36 = 0, select the interrupt level for interrupt number 54 (INTTB0). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM36 = 1, 1: Interrupt select the DMAC channel. number 54 30 R/W 17 0 Set as DMAC activation factor. EIM371 R 18 R is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM35 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 53 (INTADMC). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM35 = 1, 1: Interrupt select the DMAC channel. number 53 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL340 0 0 0 Set as If DM34 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt request. activation interrupt number 52 (INTADHPC). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM34 = 1, 1: Interrupt select the DMAC channel. number 52 is 15 After reset 1 IL341 0 set as the activation factor. Read/Write 2 IL342 000 to 111: 0 to 7 27 R 26 25 24 IL372 IL371 IL370 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM37 = 0, select the interrupt level for interrupt number 55 (INTTB1). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM37 = 1, 1: Interrupt select the DMAC channel. number 55 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-83 2010-04-01 TMP19A44 7 IMC0E bit Symbol Read/Write After reset Function 6 EIM381 R 5 4 EIM380 DM38 R/W R/W 3 15 Read/Write R After reset 0 23 Read/Write R After reset 0 14 13 12 EIM391 EIM390 DM39 R/W 0 R/W 11 IL380 R/W for 10 9 8 IL392 IL391 IL390 R R/W 0 22 21 20 EIM3A1 EIM3A0 DM3A R/W 0 R/W 000 to 111: 0 to 7 19 18 17 16 IL3A2 IL3A1 IL3A0 R R/W 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM3A = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 58 (INTTB4). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM3A = 1, 1: Interrupt select the DMAC channel. number 58 is set as the activation factor. 31 bit Symbol Function IL381 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM39 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 57 (INTTB3). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM39 = 1, 1: Interrupt select the DMAC channel. number 57 bit Symbol After reset IL382 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM38 = 0, DMAC select the interrupt level interrupt request. activation interrupt number 56 (INTTB2). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM38 = 1, 1: Interrupt select the DMAC channel. number 56 is bit Symbol Function 1 R set as the activation factor. Function 2 30 EIM3B1 R 0 29 28 EIM3B0 DM3B R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 000 to 111: 0 to 7 27 R 26 25 24 IL3B2 IL3B1 IL3B0 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM3B = 0, select the interrupt level for interrupt number 59 (INTTB5). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM3B = 1, 1: Interrupt select the DMAC channel. number 59 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-84 2010-04-01 TMP19A44 7 IMC0F bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM3C1 EIM3C0 DM3C R/W 0 R/W 3 bit Symbol Function R 14 EIM3D1 R 13 12 EIM3D0 DM3D R/W R/W bit Symbol Function 11 22 EIM3E1 R 0 21 20 EIM3E0 DM3E R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 31 bit Symbol After reset Function 10 9 8 IL3D2 IL3D1 IL3D0 R R/W 000 to 111: 0 to 7 19 29 28 EIM3F0 DM3F 0 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 16 IL3E2 IL3E1 IL3E0 R/W 0 0 0 0 "0" is read. If DM3E = 0, select the interrupt level for interrupt number 62 (INTTB8). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM3E = 1, 1: Interrupt select the DMAC channel. number 62 30 R/W 17 0 Set as DMAC activation factor. EIM3F1 R 18 R is set as the activation factor. Read/Write for 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM3D = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 61 (INTTB7). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM3D = 1, 1: Interrupt select the DMAC channel. number 61 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL3C0 0 0 0 Set as If DM3C = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level interrupt request. activation interrupt number 60 (INTTB6). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM3C = 1, 1: Interrupt select the DMAC channel. number 60 is 15 After reset 1 IL3C1 0 set as the activation factor. Read/Write 2 IL3C2 000 to 111: 0 to 7 27 R 26 25 24 IL3F2 IL3F1 IL3F0 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM3F = 0, select the interrupt level for interrupt number 63 (INTTB9). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM3F = 1, 1: Interrupt select the DMAC channel. number 63 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-85 2010-04-01 TMP19A44 7 IMC10 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM401 EIM400 DM40 R/W 0 R/W 3 bit Symbol Function R 14 EIM411 R 13 12 EIM410 DM41 R/W R/W 11 bit Symbol Function 22 EIM421 R 31 Function 8 IL412 IL411 IL410 R/W 21 20 EIM420 DM42 R/W R/W 000 to 111: 0 to 7 19 18 17 16 IL422 IL421 IL420 R R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM42 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 66 (INTTBC). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM42 = 1, 1: Interrupt select the DMAC channel. number 66 bit Symbol After reset 9 R is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM41 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 65 (INTTBB). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM41 = 1, 1: Interrupt select the DMAC channel. number 65 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL400 0 0 0 0 0 Set as If DM40 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt interrupt request. activation number 64 (INTTBA). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM40 = 1, 1: Interrupt select the DMAC channel. number 64 15 After reset 1 IL401 0 is set as the activation factor. Read/Write 2 IL402 R 30 29 28 EIM431 EIM430 DM43 R/W R/W 000 to 111: 0 to 7 27 R 26 25 24 IL432 IL431 IL430 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM43 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 67 (INTTBD). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM43 = 1, 1: Interrupt select the DMAC channel. number 67 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-86 2010-04-01 TMP19A44 7 IMC11 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM441 EIM440 DM44 R/W 0 R/W 3 bit Symbol Function R 14 EIM451 R 13 12 EIM450 DM45 R/W R/W bit Symbol Function 11 22 EIM461 R 0 21 20 EIM460 DM46 R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 31 bit Symbol After reset Function 10 9 8 IL452 IL451 IL450 R R/W 000 to 111: 0 to 7 19 29 28 EIM470 DM47 0 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 16 IL462 IL461 IL460 R/W 0 0 0 0 "0" is read. If DM46 = 0, select the interrupt level for interrupt number 70 (INTADA). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM46 = 1, 1: Interrupt select the DMAC channel. number 70 30 R/W 17 0 Set as DMAC activation factor. EIM471 R 18 R is set as the activation factor. Read/Write for 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM45 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 69 (INTTBF). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM45 = 1, 1: Interrupt select the DMAC channel. number 69 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL440 0 0 0 Set as If DM44 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level interrupt request. activation interrupt number 68 (INTTBE). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM44 = 1, 1: Interrupt select the DMAC channel. number 68 is 15 After reset 1 IL441 0 set as the activation factor. Read/Write 2 IL442 000 to 111: 0 to 7 27 R 26 25 24 IL472 IL471 IL470 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM47 = 0, select the interrupt level for interrupt number 71 (INTADB). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM47 = 1, 1: Interrupt select the DMAC channel. number 71 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-87 2010-04-01 TMP19A44 7 IMC12 bit Symbol Read/Write After reset Function 6 EIM481 R 5 4 EIM480 DM48 R/W R/W 3 15 Read/Write R After reset 0 23 Read/Write R After reset 0 14 13 12 EIM491 EIM490 DM49 R/W 0 R/W 11 IL480 R/W 10 IL492 R 9 8 IL491 IL490 R/W 0 22 21 20 EIM4A1 EIM4A0 DM4A R/W 0 R/W 000 to 111: 0 to 7 19 18 IL4A2 R 17 16 IL4A1 IL4A0 R/W 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM4A = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 74 (INTTB11). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM4A = 1, 1: Interrupt select the DMAC channel. number 74 is set as the activation factor. 31 bit Symbol Function IL481 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM49 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 73 (INTTB10). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM49 = 1, 1: Interrupt select the DMAC channel. number 73 bit Symbol After reset IL482 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM48 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 72 (INTADC). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM48 = 1, 1: Interrupt select the DMAC channel. number 72 bit Symbol Function 1 R is set as the activation factor. Function 2 30 EIM4B1 R 0 29 28 EIM4B0 DM4B R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 000 to 111: 0 to 7 27 26 IL4B2 R 25 24 IL4B1 IL4B0 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM4B = 0, select the interrupt level for interrupt number 75 (PHCNT0). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM4B = 1, 1: Interrupt select the DMAC channel. number 75 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-88 2010-04-01 TMP19A44 7 IMC13 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM4C1 EIM4C0 DM4C R/W 0 R/W 3 bit Symbol Function R 14 EIM4D1 R 13 12 EIM4D0 DM4D R/W R/W 11 bit Symbol Function IL4D2 R 22 EIM4E1 R 0 21 20 EIM4E0 DM4E R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 31 bit Symbol After reset Function 9 8 IL4D1 IL4D0 R/W 000 to 111: 0 to 7 19 IL4E2 0 "0" is read. 29 28 EIM4F0 DM4F 0 R/W 0 Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 16 IL4E1 IL4E0 R/W 0 0 0 0 "0" is read. If DM4E = 0, select the interrupt level for interrupt number 78 (PHCNT3). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM4E = 1, 1: Interrupt select the DMAC channel. number 78 30 R/W 17 0 Set as DMAC activation factor. EIM4F1 R 18 R is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM4D = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 77 (PHCNT2). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM4D = 1, 1: Interrupt select the DMAC channel. number 77 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL4C0 0 0 0 Set as If DM4C = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt request. activation interrupt number 76 (PHCNT1). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM4C = 1, 1: Interrupt select the DMAC channel. number 76 is 15 After reset 1 IL4C1 0 set as the activation factor. Read/Write 2 IL4C2 000 to 111: 0 to 7 27 26 IL4F2 R 25 24 IL4F1 IL4F0 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM4F = 0, select the interrupt level for interrupt number 79 (PHCNT4). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM4F = 1, 1: Interrupt select the DMAC channel. number 79 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-89 2010-04-01 TMP19A44 7 IMC14 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM501 EIM500 DM50 R/W 0 R/W 3 bit Symbol Function R 14 EIM511 R 13 12 EIM510 DM51 R/W R/W 11 bit Symbol Function 22 EIM521 R 31 Function 8 IL512 IL511 IL510 R/W 21 20 EIM520 DM52 R/W R/W 000 to 111: 0 to 7 19 18 17 16 IL522 IL521 IL520 R R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM52 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 82 (INTCAP1). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM52 = 1, 1: Interrupt select the DMAC channel. number 82 bit Symbol After reset 9 R is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM51 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 81 (INTCAP0). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM51 = 1, 1: Interrupt select the DMAC channel. number 81 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL500 0 0 0 0 0 Set as If DM50 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt interrupt request. activation number 80 (PHCNT5). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM51 = 1, 1: Interrupt select the DMAC channel. number 80 15 After reset 1 IL501 0 is set as the activation factor. Read/Write 2 IL502 R 30 29 28 EIM531 EIM530 DM53 R/W R/W 000 to 111: 0 to 7 27 R 26 25 24 IL532 IL531 IL530 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM53 = 0, DMAC select the interrupt level for interrupt interrupt request. activation number 83 (INTCAP2). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM53 = 1, 1: Interrupt select the DMAC channel. number 83 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-90 2010-04-01 TMP19A44 7 IMC15 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM541 EIM540 DM54 R/W 0 R/W 3 bit Symbol Function R 14 EIM551 R 13 12 EIM550 DM55 R/W R/W 11 bit Symbol Function 22 EIM561 R 0 21 20 EIM560 DM56 R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 31 bit Symbol After reset Function 9 8 IL552 IL551 IL550 R R/W 000 to 111: 0 to 7 19 29 28 EIM570 DM57 0 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 16 IL562 IL561 IL560 R/W 0 0 0 0 "0" is read. If DM56 = 0, select the interrupt level for interrupt number 86 (INTCMP1). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM56 = 1, 1: Interrupt select the DMAC channel. number 88 30 R/W 17 0 Set as DMAC activation factor. EIM571 R 18 R is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM55 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 85 (INTCMP0). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM55 = 1, 1: Interrupt select the DMAC channel. number 85 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL540 0 0 0 Set as If DM54 = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt request. activation interrupt number 84 (INTCAP3). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM54 = 1, 1: Interrupt select the DMAC channel. number 84 is 15 After reset 1 IL541 0 set as the activation factor. Read/Write 2 IL542 000 to 111: 0 to 7 27 R 26 25 24 IL572 IL571 IL570 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM57 = 0, select the interrupt level for interrupt number 87 (INTCMP2). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM57 = 1, 1: Interrupt select the DMAC channel. number 87 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-91 2010-04-01 TMP19A44 7 IMC16 bit Symbol Read/Write After reset Function 6 EIM581 R 5 4 EIM580 DM58 R/W R/W 3 15 Read/Write R After reset 0 23 Read/Write R After reset 0 14 13 12 EIM591 EIM590 DM59 R/W 0 R/W 11 IL580 R/W 10 IL592 R 9 8 IL591 IL590 R/W 0 22 21 20 EIM5A1 EIM5A0 DM5A R/W 0 R/W 000 to 111: 0 to 7 19 18 IL5A2 R 17 16 IL5A1 IL5A0 R/W 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM5A = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 90 (INTCMP5). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM5A = 1, 1: Interrupt select the DMAC channel. number 90 is set as the activation factor. 31 bit Symbol Function IL581 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM59 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 89 (INTCMP4). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM59 = 1, 1: Interrupt select the DMAC channel. number 89 bit Symbol After reset IL582 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM58 = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 88 (INTCMP3). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM58 = 1, 1: Interrupt select the DMAC channel. number 88 bit Symbol Function 1 R is set as the activation factor. Function 2 30 EIM5B1 R 0 29 28 EIM5B0 DM5B R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 11: Rising edge Be sure to set "11". 000 to 111: 0 to 7 27 26 IL5B2 R 25 24 IL5B1 IL5B0 R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM5B = 0, select the interrupt level for interrupt number 91 (INTCMP6). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM5B = 1, 1: Interrupt select the DMAC channel. number 91 is set as the activation factor. 000 to 111: 0 to 7 (Note) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. Exceptions/Interrupts TMP19A44(rev1.3) 6-92 2010-04-01 TMP19A44 7 IMC17 bit Symbol Read/Write R After reset 0 Function 6 5 4 EIM5C1 EIM5C0 DM5C R/W 0 R/W 3 bit Symbol Function R 14 EIM5D1 R 13 12 EIM5D0 DM5D R/W R/W 11 bit Symbol Function IL5D2 R 22 EIM5E1 R 0 21 20 EIM5E0 DM5E R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 10: Falling edge Be sure to set "10". 31 bit Symbol After reset Function 9 8 IL5D1 IL5D0 R/W 000 to 011: 0 to 3 100 to 111: 4 to 7 19 R 0 "0" is read. 30 29 EIM5F1 EIM5F0 R/W 18 17 16 IL5E2 IL5E1 IL5E0 R R/W 0 Set as DMAC activation factor. 0 0 0 0 "0" is read. If DM5E = 0, select the interrupt level for interrupt number 94 (INTRTC). 0: Non000: Disable Interrupt activation 001-111: 1-7 factor If DM5E = 1, 1: Interrupt select the DMAC channel. number 94 is set as the activation factor. Read/Write 10 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Set as "0" is read. If DM5D = 0, DMAC select the interrupt level for interrupt request. activation interrupt number 93 (INTTBT). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM5D = 1, 1: Interrupt select the DMAC channel. number 93 23 After reset R/W 000 to 111: 0 to 7 is set as the activation factor. Read/Write 0 IL5C0 0 0 0 Set as If DM5C = 0, "0" is read. Selects active state of "0" is read. DMAC select the interrupt level for interrupt request. activation interrupt number 92 (INTCMP7). 11: Rising edge factor. 0: Non000: Disable Interrupt Be sure to set "11". activation 001-111: 1-7 factor If DM5C = 1, 1: Interrupt select the DMAC channel. number 92 is 15 After reset 1 IL5C1 0 set as the activation factor. Read/Write 2 IL5C2 28 000 to 011: 0 to 7 27 26 IL5F2 R/W R 25 24 IL5F1 IL5F0 R/W 0 0 0 0 0 0 0 Selects active state of Be sure to "0" is read. If DM5F = 0, select the interrupt level for interrupt request. set "0". interrupt number 95 (INTDMA0). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 (Note 1) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. (Note 2) The access to the DMAC register by DMAC is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-93 2010-04-01 TMP19A44 7 IMC18 bit Symbol Read/Write After reset Function 5 EIM601 R 4 3 R/W R EIM600 R/W 15 Read/Write R After reset 0 23 14 13 EIM611 EIM610 R/W 12 11 R/W R 0 0 0 22 21 20 19 EIM621 EIM620 0 Read/Write R R/W R After reset 0 0 0 0 0 31 30 29 28 27 R/W R After reset Function 0 IL602 IL601 IL600 R/W 10 9 8 IL612 IL611 IL610 R/W R/W 18 17 16 IL622 IL621 IL620 R/W 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM62 = 0, select the interrupt level for interrupt interrupt request. set "0". number 98 (INTDMA3). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 bit Symbol Read/Write 1 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM61 = 0, select the interrupt level for interrupt interrupt request. set "0". number 97 (INTDMA2). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 bit Symbol Function 2 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM60 = 0, select the interrupt level for interrupt interrupt request. set "0". number 96 (INTDMA1). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 bit Symbol Function 6 EIM631 R R/W EIM630 26 25 24 IL632 IL631 IL630 R/W 0 0 0 0 0 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM63 = 0, select the interrupt level for interrupt interrupt request. set "0". number 99 (INTDMA4). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 (Note 1) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. (Note 2) The access to the DMAC register by DMAC is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-94 2010-04-01 TMP19A44 7 IMC19 bit Symbol Read/Write After reset Function Read/Write R After reset 0 23 Read/Write R After reset 0 31 Function R/W R EIM640 R/W 2 1 0 IL642 IL641 IL640 R/W 14 13 EIM651 EIM650 R/W 12 11 R/W R 0 0 0 22 21 20 19 EIM661 EIM660 0 10 9 8 IL652 IL651 IL650 R/W R/W 0 R/W R 0 0 27 30 29 28 EIM671 EIM670 DM67 R 0 0 18 17 16 IL662 IL661 IL660 R/W 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM66 = 0, select the interrupt level for interrupt request. set "0". interrupt number 102 (INTDMA7). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 bit Symbol After reset 3 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM65 = 0, select the interrupt level for interrupt request. set "0". interrupt number 101 (INTDMA6). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 bit Symbol Read/Write 4 0 0 0 0 0 0 "0" is read. Selects active state of Be sure to "0" is read. If DM64 = 0, select the interrupt level for interrupt request. set "0". interrupt number 100 (INTDMA5). 00: "L" level 000: Disable Interrupt Be sure to set "00". 001-111: 1-7 15 Function 5 EIM641 R bit Symbol Function 6 R/W 0 R/W 0 "0" is read. Selects active state of interrupt request. 00: "L" level Be sure to set "00". 0 Set as DMAC activation factor. 0: Nonactivation factor 1: Interrupt number 103 is set as the activation factor. R 26 25 24 IL672 IL671 IL670 R/W 0 0 0 0 "0" is read. If DM67 = 0, select the interrupt level for interrupt number 103 (software set). 000: Disable Interrupt 001-111: 1-7 If DM67 = 1, select the DMAC channel. 000 to 011: 0 to 7 (Note 1) Default values of <EIMxx0:1> are different from the values to be used. Properly set them to the specified values before use. (Note 2) The access to the DMAC register by DMAC is prohibited. Exceptions/Interrupts TMP19A44(rev1.3) 6-95 2010-04-01 TMP19A44 (Note 1) Please ensure that the type of active state is selected before enabling an interrupt request. (Note 2) When making interrupt requests as DMAC activation factors, please ensure that you put the DMAC into standby mode after setting the INTC. (Note 3) An active condition must be changed after an interrupt output of the corresponding device becomes negate especially when you change it to the level detection. (1) IL Set to "0" if it is set to "Excluding 0" (2) Change Detection condition (EIM) (3) INTCLR Clear pertinent interrupt. (4) IL Set to" Excluding 0". Exceptions/Interrupts TMP19A44(rev1.3) 6-96 2010-04-01 TMP19A44 6.6.4.4 Interrupt Request Clear Registers (INTCLR) Setting the IVR [8:0] for the corresponding interrupt factor into the INTCLR register enables to clear any interrupt request being suspended. Do not clear an interrupt request before reading the IVR value. When an interrupt request is cleared, the IVR value is also cleared and the interrupt factor cannot be determined anymore. IVR <IVR8:0> value setting to clear the interrupt request INTCLR bit Symbol 7 6 5 4 EICLR7 EICLR6 EICLR5 EICLR4 Read/Write After reset Function 3 2 1 0 EICLR3 EICLR2 EICLR1 EICLR0 0 0 0 0 R/W 0 0 0 0 Set the IVR <IVR8:0> value that corresponds to the interrupt request that you would like to clear. 15 14 13 12 11 10 9 bit Symbol 8 EICLR8 Read/Write R After reset 0 Function R/W 0 "0" is read. 23 22 21 20 Set the IVR <IVR8:0> value that correspond s to the interrupt request that you would like to clear. 19 18 17 16 26 25 24 bit Symbol Read/Write R After reset 0 Function "0" is read. 31 30 29 28 27 bit Symbol Read/Write R After reset 0 Function "0" is read. (Note 1) This register must be 16-bit accessed. (Note 2) In order to maintain interrupt factors regardless of the active state setting of INTC IMCx <EIMxx>, clear the interrupt request in any case whether in "H" level, "L" level, rising edge, or falling edge. (Note 3) Bit manipulation instructions cannot be used to access this register. (Note 4) External transfer requests due to DMAC interrupt factors are not cleared. Once an external transfer request is accepted, it will not be canceled until the DMA transfer is executed. Therefore, any unnecessary external transfer request should be cleared by executing DMA transfer, by disabling interrupts using IMCx <ILxxx> or by canceling the corresponding DMAC activation factors using IMCx<DMxx> before accepting such external transfer requests. Exceptions/Interrupts TMP19A44(rev1.3) 6-97 2010-04-01 TMP19A44 6.6.4.5 DMAC Transfer Request Clear Registers (DREQFLG) Setting the DREQ [7:0] for the corresponding factor into the DREQFLG register enables to clear any DMAC transfer request. DREQ [7:0] value setting to clear the DMAC transfer request DREQFLG bit Symbol 7 6 DREQ7 DREQ6 5 DREQ5 4 3 DREQ4 DREQ3 2 1 0 DREQ2 DREQ1 DREQ0 (0xFF00_10C4) Read/Write After reset R/W 1 1 Function 1 1 1 1 1 1 10 9 8 18 17 16 26 25 24 Corresponding DMAC transfer request is cleared. 15 14 13 12 11 bit Symbol Read/Write R 0 After reset Function "0" is read. 23 22 21 20 19 bit Symbol Read/Write R After reset 0 Function "0" is read. 31 30 29 28 27 bit Symbol Read/Write R After reset 0 Function "0" is read. Reading 0: DMAC transfer is requested. 1: DMAC transfer is not requested. Writing 0: Invalid 1 :DMAC transfer request is cleared. Exceptions/Interrupts TMP19A44(rev1.3) 6-98 2010-04-01 TMP19A44 7. Input/Output Ports Port Registers Px : Port register To read/ write port data. PxCR : Control register To control input/output * Need to enable the input with PxIE register even when input is set. PxFRn : Function register To set functions. An assigned function can be activated by setting "1". PxOD : Open drain control register To switch the input of a register that can be set as programmable open drain. PxPUP : Pull up control register To control program pull ups. PxIE : Input control enable register Input/Output Ports TMP19A44 (rev1.3) 7-1 2010-04-01 TMP19A44 7.1 Port 0 (P00 through P07) The port 0 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P0CR. A reset allows all bits of P0CR to be cleared to "0" and the port 0 to be put in input mode. Besides the general-purpose input/output function, the port 0 performs other functions: D0 through D7 function as a data bus and AD0 through AD7 function as an address data bus. If the BUSMD pin (port P45) is set to "L" level during a reset, the port 0 is put in separate bus mode (D0 to D7). If it is set to "H" level during a reset, the port 0 is put in multiplexed mode (AD0 to AD7). Address/ data output enable Drive disabled during STOP/ RESET External bus opening PORT KEEP Latch P0PUP (Pull-up control) Latch 1 P0CR Internal data bus (direction control) 0 RESET P0FC1 (function control) Latch D0~D7/ AD0~AD7 1 P0 (output latch) Port 0 P00~P07 (D0~D7) (AD0~AD7) 0 External read D0~D7 P0 read Latch P0 read External read Fig. 7.1 Port 0 (P00 through P07) Input/Output Ports TMP19A44 (rev1.3) 7-2 2010-04-01 TMP19A44 Port 0 register 7 6 5 4 P07 P06 P05 P04 3 2 1 0 P03 P02 P01 P00 P0 Bit Symbol (0xFF00_4000) Read/Write R/W After reset Input mode (output latch register is cleared to "0.") 7 P0CR Bit Symbol (0xFF00_4004) Read/Write After reset Function P07C 0 (0xFF00_402C) Bit Symbol P05C P04C 0 0 0 P07F Port 0 function register 1 6 5 4 P06F P05F P04F Function Input/Output Ports 1 0 P03C P02C P01C P00C 0 0 0 0 3 2 1 0 P03F P02F P01F P00F 0 0 0 R/W 0 0 0 0 0 0: PORT 1:External bus Port 0 Pull-up control register 6 5 4 3 2 1 0 PE03 PE02 PE01 PE00 PE07 PE06 PE05 PE04 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Read/Write After reset 2 0: Input 1: Output (When an external area is accessed, D7-0 or AD7-0 is used and this register is cleared to "0.") 7 P0PE P06C 3 R/W 7 P0FC1 Bit Symbol (0xFF00_4008 Read/Write ) After reset Function Port 0 control register 6 5 4 R/W TMP19A44 (rev1.3) 7-3 2010-04-01 TMP19A44 7.2 Port 1 (P10 through P17) The port 1 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P1CR and the function registers P1FC1 and P1FC2. A reset allows all bits of the output latch P1, P1CR and P1FC to be cleared to "0" and the port 1 to be put in input mode. Besides the general-purpose input/output function, the port 1 performs other functions: D8 through D15 function as a data bus, AD8 through AD15 function as an address data bus, and A8 through A15 function as an address bus. To access external memory, registers P1CR and P1FC must be provisioned to allow the port 1 to function as either an address bus or an address data bus. If the BUSMD pin (port 45) is set to "L" level during a reset, the port 1 is put in separate bus mode (D8 to D15). If it is set to "H" level during a reset, the port 1 is put in multiplexed mode (AD8 to AD15 or A8 to A15). Drive disabled during STOP/RESET Address/ data Output enable PORT KEEP External bus opening Latch P1PUP (Pull-up control) Latch 1 P1CR (direction control) 0 0 RESET 1 P1FC1 Internal data bus (function control) P1FC2 P1 (output latch) 0 D8~ D15 1 0 P1 read Port 1 P10~P17 (D8~D15) (AD8~AD15/A8~A15) Latch P1 read A8~ A15 1 Latch (function control) External read Fig. 7.2 Port 1 (P10 through P17) Input/Output Ports TMP19A44 (rev1.3) 7-4 2010-04-01 TMP19A44 Port 1 register 7 6 5 4 P17 P16 P15 P14 3 2 1 0 P13 P12 P11 P10 P1 Bit Symbol (0xFF00_4040) Read/Write R/W After reset Input mode (output latch register is cleared to "0.") 7 P1CR Bit Symbol (0xFF00_4004) Read/Write After reset P17C Port 1 control register 6 5 4 P16C P15C 0 Bit Symbol Read/Write After reset 0 0 P17F After reset P16F P15F 0 0 0 Bit Symbol Read/Write After reset Function Input/Output Ports P12C P11C P10C 0 0 0 0 1 0 P14F 3 P13F 0 2 P12F 0 Port 1 function register 2 6 5 4 P17F2 P16F2 P15F2 0 0 0 P11F P10F 0 0 0 2 1 0 P12F2 P11F2 P10F2 0 0 0 3 2 1 0 PE13 PE12 PE11 PE10 3 P14F2 P13F2 R/W 0 0 0: PORT 1: External bus 7 (0xFF00_406C) P13C 0: PORT 1: External bus Function P1PUP 0 R/W 7 Bit Symbol Read/Write 0 Port 1 function register 1 6 5 4 Function P1FC2 (0xFF00_404 C) 1 0: Output disabled 1: Output enabled 7 (0xFF00_4048) 2 R/W Function P1FC P14C 3 PE17 Port 1 Pull-up control register 6 5 4 PE16 PE15 PE14 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up TMP19A44 (rev1.3) 7-5 2010-04-01 TMP19A44 7.3 Port 2 (P20 through P27) The port 2 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P2CR and the function register P2FC1, P2FC2 and P2FC3. A reset allows all bits of the output latch P2 to be set to "1," all bits of P2CR, P2FC1, P2FC2 and P2FC3 to be cleared to "0," and the port 2 to be put in output disabled mode. The port 2 also performs a 16-bit timer input function. This function is enabled by setting the corresponding bit of P2FC3 to "1" and the corresponding bits of P2CR, P2FC1 and P2FC2 to "0." A reset allows P2CR, P2FC1, P2FC2 and P2FC3 to be cleared to "0" and the port 2 to function as an input port. Besides the general-purpose input/output port function, the port 2 performs another function: A0 through A7 function as one address bus and A16 through A23 function as the other address bus. To access external memory, registers P2CR and P2FC must be provisioned to allow the port 2 to function as an address bus. If the BUSMD pin (port P45) is set to "L" level during a reset, the port 2 is put in separate mode (A16 to A23). If it is set to "H" level during a reset, the port 2 is put in multiplexed mode (A0 through A7 or A16 through A23). Input/Output Ports TMP19A44 (rev1.3) 7-6 2010-04-01 TMP19A44 PORT KEEP P2PUP Latch Drive disabled during STOP/ RESET External bus opening (output control) 0 Latch P2CR (output control) 1 P2FC1 RESET (function control) P2FC2 A0~A7 A16~A2 1 1 Latch (function control) Port 2 P20~P27 (A0~A7/A16~A23 TB1IN0,TB1IN1 TB2IN0,TB2IN1 TB3IN0,TB3IN1 TB5IN0,TB5IN1) P2 (output latch) 0 0 (function control) Latch Internal data bus P2FC3 P2IE (input control) 0 P2 read 1 Fig. 7.3 Port 2 (P20 through P27) Input/Output Ports TMP19A44 (rev1.3) 7-7 2010-04-01 TMP19A44 Port 2 register 7 6 5 4 P27 P26 P25 P24 3 2 1 0 P23 P22 P21 P20 P2 Bit Symbol (0xFF00_4080) Read/Write R/W After reset Input mode (output latch register is set to "1.") P2CR Bit Symbol (0xFF00_4084) Read/Write After reset Port 2 control register 5 4 7 6 P27C P26C 0 0 Bit Symbol Read/Write After reset Function Bit Symbol (0xFF00_408C) Read/Write After reset 0 P23C P22C P21C P20C 0 0 0 0 0 0 Port 2 function register 1 6 5 4 P27F P26F P25F P24F 3 2 1 0 P23F P22F P21F P20F 0 0 R/W 0 0 0 0 0 0 0: Port 1: External bus 0: Port 1: External bus 0: Port 1: External bus 0: Port 1: External bus 0: Port 1: External bus 0: Port 1: External bus 7 P2FC2 1 0: Output disabled 1: Output enabled 7 (0xFF00_4088) P24C 2 R/W Function P2FC1 P25C 3 P27F2 Port 2 function register 2 6 5 4 P26F2 P25F2 P24F2 0: Port 0: Port 1: External 1: External bus bus 3 2 1 0 P23F2 P22F2 P21F2 P20F2 0 0 0 0 R/W 0 0 0 Function 0 0: Port 1: External bus Port 2 function register 3 P2FC3 (0xFF00_4090) 7 6 5 4 3 2 1 0 Bit Symbol Read/Write P27F3 P26F3 P25F3 P24F3 P23F3 P22F3 P21F3 P20F3 After reset Function 0 0:PORT 1:TB5IN1 0 0:PORT 1:TB3IN1 0 0:PORT 1:TB3IN0 0 0 0:PORT 0:PORT 1:TB2IN0 1:TB1IN1 0 0:PORT 1:TB1IN0 R/W 7 P2PUP Bit Symbol (0xFF00_40AC) Read/Write After reset Function PE27 0 0:PORT 1:TB5IN0 0 0:PORT 1:TB2IN1 Port 2 pull-up control register 6 5 4 PE26 PE25 PE24 3 2 1 0 PE23 PE22 PE21 PE20 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIE23 PIE22 PIE21 PIE20 Port 2 input enable control register P2IE (0xFF00_40B8) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIE27 PIE26 PIE25 PIE24 R/W 0 Input 0: Disabled 1: Enabled 0 0 0 0 Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled TMP19A44 (rev1.3) 7-8 0 Input 0: Disabled 1: Enabled 0 0 Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.4 Port 3 (P30 through P37) The port 3 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P3CR and the function registers P3FC1 and P3FC2. Besides the input/output port function, the port 3 performs other functions: P34 outputs a 16-bit timer, and P32, P35 through P37 perform the 32-bit capture and trigger input function. These functions are enabled by setting the corresponding bit of P3FC2 to "1." A reset allows P3CR, P3FC1 and P3FC2 to be cleared to "0" and the port 3 to function as an input port. Input is disabled right after reset. To enable input, set the corresponding bit of P3IE to "1". In addition to above functions, a function of inputting and outputting the control and status signals of CPU is provided. If the P30 pin is set to RD signal output mode (<P30F>="1"), the RD strobe is output only when an external address area is accessed. Likewise, if the P31 pin is set to WR signal output mode (<P31F>="1"), the WR strobe is output only when an external address area is accessed. External bus opening 0 P3PUP (output control) PORT KEEP Latch Drive disabled during STOP/ RESET 1 0 P3CR (output control) Latch External bus opening 1 P3FC1 RESET (function control) P3 (output latch) Latch Internal data bus 1 RD,WR Port 3 P30,P31 (RD,WR) 0 Latch P3IE (input control) 0 P3 read 1 Fig. 7.4 Port 3 (P30, P31) Input/Output Ports TMP19A44 (rev1.3) 7-9 2010-04-01 TMP19A44 External bus opening 0 P3PUP (output control) Latch Drive disabled during STOP/ RESET PORT KEEP 1 External bus opening Latch 0 P3CR (output control) 1 P3FC1 RESET (function control) HWR,BUSAK, R/W,ALE 1 Latch Internal data bus P3 (output latch) 0 Latch P3IE (input control) P3FC2 (function control) P3 read 0 1 TC0IN~TC3IN Fig. 7.5 Port 3 (P32, P35 through P37) Input/Output Ports TMP19A44 (rev1.3) 7-10 2010-04-01 TMP19A44 Drive disabled during STOP/ RESET PORT KEEP Latch P3PUP (output control) Latch P3CR (output control) RESET P3FC1 (function control) Latch P3 Port 3 P33 (WAIT/RDY) (output latch) Latch Internal data bus P3IE (Input control) 0 1 P3 read WAIT 0 RDY 1 Fig. 7.6 Port 3 (P33) Input/Output Ports TMP19A44 (rev1.3) 7-11 2010-04-01 TMP19A44 Drive disabled during STOP/ RESET PORT KEEP Latch P3PUP (output control) Latch PC (output control) RESET P3FC2 (function control) P3 Latch 1 TBEOUT Port 3 P34 (BUSRQ/TBEOUT) 0 (output latch) (funcion control) Latch Internal data bus P3FC P3IE (input control) 0 P3 read 1 BUSREQ Fig. 7.7 Port 3 (P34) Input/Output Ports TMP19A44 (rev1.3) 7-12 2010-04-01 TMP19A44 Port 3 register P3 (0xFF00_40C0) Bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 R/W Input mode To be determined according to the bus mode (*1) 1 (*1) Default setting of the bit is determined according to the bus mode P45(BUSMD. L (separate bus): 1 H (multiplex bus): 0 Port 3 control register 6 5 4 7 P3CR Bit Symbol (0xFF00_40C4) Read/Write After reset Function P37C P36C P35C P34C 3 2 1 0 P33C P32C P31C P30C 0 0 0 0 R/W To be determined according to the bus mode (*2) 0 0 0 0: Input 1: Output (*1) Default setting of the bit is determined according to the bus mode P45(BUSMD. L (separate bus): 0 H (multiplex bus): 1 7 P3FC Bit Symbol (0xFF00_4008) Read/Write After reset Function P37F Port 3 function register 1 6 5 4 P36F P35F P34F 3 2 1 0 P33F P32F P31F P30F R/W 0 0 0 0 0 0 0 0 0: PORT 0: PORT 0: PORT 0: PORT 0: PORT 0: PORT 0: PORT 1: ALE 1: R / W 1: BUSAK 1: BUSRQ 0: PORT/ WAIT 1:RDY 1: HWR 1: WR 1: RD Port 3 function register 2 P3FC2 Bit Symbol (0xFF00_40CC) Read/Write After reset Function 7 6 5 4 3 2 1 0 P37F P36F P35F P34F P32F 0 0: PORT 1: TC3IN 0 0: PORT 1: TC2IN R/W 7 P3PUP (0xFF00_40EC) Bit Symbol 0 0: PORT 1: TC1IN R R/W 0 0 0 0: PORT "0" is read. 0: PORT 1: TBEOUT 1: TC0IN Port 3 pull-up control register 6 5 4 Function "0" is read. 3 2 1 0 PE33 PE32 PE31 PE30 PE37 PE36 PE35 PE34 0 0 0 0 0 0 0 0 Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up 0: Off 1: Pull-Up 0: Off 1: Pull-Up 0: Off 1: Pull-Up 0: Off 1: Pull-Up 0: Off 1: Pull-Up 0: Off 1: Pull-Up 0: Off 1: Pull-Up 0: Off 1: Pull-Up Read/Write After reset R 0 R/W Port 3 input enable control register P3IE (0xFF00_40F8) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 3 2 1 0 PIE37 PIE36 PIE35 PIE34 PIE33 PIE32 PIE31 PIE30 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled R/W 0 0 Input Input 0: 0: Disabled Disabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-13 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.5 Port 4 (P40 through P47) The port 4 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P4CR and the function register P4FC. Besides the general-purpose input/output port function, the port 4 performs other functions: P40 through P43 output the chip select signal ( CS0 to CS3 ) and input the key-on wake-up, P44 functions as the SCOUT output pin for outputting internal clocks, and P47 outputs a 16-bit timer. By making necessary settings during a reset, P45 functions as a BUSMD pin for setting external bus modes, and P46 as an ENDIAN setting pin. External bus opening control 0 DPUP Latch Drive disabled during STOP/ RESET PORT KEEP P4PUP (Output control) 0 1 External bus opening Latch 0 P4CR 1 (Output control) 1 RESET P4FC1 (function control) CS0~CS3 Latch Internal data bus 1 Port 4 P40~P43 (CS0~CS3, KEY24~27) P4 0 (output latch) P4FC2 Control 1 DPUP Latch (function control) P4IE 0 (input control) 0 P4 read 1 KEY24~KEY27 Fig. 7.8 Port 4(P40 through P43) Input/Output Ports TMP19A44 (rev1.3) 7-14 2010-04-01 TMP19A44 Drive disabled during STOP/ RESET PORT KEEP Latch P4PUP (output control) Latch P4CR (output control) RESET P4FC1 (function control) SCOUT 1 Latch Internal data bus P4 (output latch) 0 Port 4 P44(SCOUT) Latch P4IE (input control) 0 P4 read 1 Fig. 7.9 Port 4 (P44) Input/Output Ports TMP19A44 (rev1.3) 7-15 2010-04-01 TMP19A44 PORT KEEP Latch Drive disabled during STOP/ RESET P4PUP (output control) Latch P4CR (output control) RESET Latch P4 Latch Internal data bus (output latch) Port 4 P45,P46 (BUSMD, ENDIAN) P4IE (input control) 0 P4 read 1 Fig. 7.10 Port 4 (P45,P46) Input/Output Ports TMP19A44 (rev1.3) 7-16 2010-04-01 TMP19A44 P4PUP PORT KEEP Latch Drive disabled during STOP/ RESET (output control) Latch P4CR (output control) RESET P4FC1 (function control) TBFOUT 1 Latch P4 0 Latch Internal data bus (output latch) Port 4 P47(TBFOUT) P4IE (input control) 0 P4 read 1 Fig. 7.11 Port 4 (P47) Input/Output Ports TMP19A44 (rev1.3) 7-17 2010-04-01 TMP19A44 Port 4 register P4 Bit Symbol (0xFF00_4100) 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port 4 control register P4CR Bit Symbol (0xFF00_4104) Read/Write After reset 7 6 5 4 P47C P46C P45C P44C 3 2 1 0 P43C P42C P41C P40C 0 0 0 0 R/W 0 0 0 0 0: Input 1: Output Port 4 function register 1 7 P4FC1 (0xFF00_4108) Bit Symbol Read/Write After reset Function P47F R/W 0 0: PORT 1: TBFOUT 6 5 4 3 P46F P45F P44F P43F R 0 "0" is read. 0 0 0: PORT 0: PORT 1: SCOUT 1: CS3 2 P42F R/W 0 0: PORT 1: CS2 1 0 P41F P40F 0 0: PORT 1: CS1 0 0: PORT 1: CS0 Port 4 function register P4FC2 Bit Symbol (0xFF00_410C) Read/Write After reset Function 7 6 5 4 3 2 1 0 P43F P42F P41F P40F 0 0 0 0 0: PORT 1: KEY27 0: PORT 1: KEY26 R 0 0 R/W "0" is read. 0 0 0: PORT 1: KEY25 0: PORT 1: KEY24 Port 4 pull-up control register P4PUP Bit Symbol (0xFF00_412C) Read/Write After reset Function 7 6 5 4 3 2 1 0 PE47 PE46 PE45 PE44 PE43 PE42 PE41 PE40 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIE43 PIE42 PIE41 PIE40 0 0 0 Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Port 4 input enable control register P4IE (0xFF00_4138) 7 6 5 4 Bit Symbol Read/Write PIE47 PIE46 PIE45 PIE44 After reset 0 Function Input/Output Ports R/W Input 0: Disabled 1: Enabled 0 0 0 0 Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled TMP19A44 (rev1.3) 7-18 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.6 Port 5 (P50 through P57) The port 5 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P5CR and the function registers P5FC1, P5FC2 and P5FC3. A reset allows all bits of the output latch P5 to be set to "1," all bits of P5CR, P5FC1, P5FC2 and P5FC3 to be cleared to "0," and the port 5 to be put in input mode. Besides the input/output port function, the port 5 performs other functions: P50 through P53 input external interrupts, P54 through P57 output a 16-bit timer, and P56 and P57 input the key-on wake-up. These functions are enabled by setting the corresponding bit of P5FC to "1." The port 5 also functions as an address bus (A0 through A7). To access external memory, P5CR and P5FC must be provisioned to allow the port 5 to function as an address bus. This address bus function can be used only in separate bus mode. (To put the port 5 in separate bus mode, the BUSMD pin (port 45) must be set to "L" level during a reset.) Input/Output Ports TMP19A44 (rev1.3) 7-19 2010-04-01 TMP19A44 Drive disabled during STOP/ RESET PORT KEEP h c t a L P5PUP (output control) 0 h c t a L P5CR (output control) External bus opening 1 RESET P5FC1 (function control) Internal data bus P5 Latch 1 A0~A3 (output latch) 0 Port 5 P50~P53 (A0/ INTC~A3/INTF) P5FC2 (function control) h c t a L P5IE (input control) 0 P5 read 1 INTC~INTF Fig. 7.12 Port 5 (P50 through P53) Input/Output Ports TMP19A44 (rev1.3) 7-20 2010-04-01 TMP19A44 PORT KEEP Drive disabled during STOP/ RESET Latch P5PUP (output control) Latch 0 P5CR (output control) External bus opening 1 RESET P5FC1 (function control) P5FC2 (function control) A4,A5 P5 (output latch) 0 Latch TB0OU T 1 TB1OU T 1 0 Port 5 P54,P55 (A4/ TB0OUT A5/TB1OUT) Latch Internal data bus P5IE (input control) 0 1 Internal data bus P5 read Fig. 7.13 Port 5 (P54, P55) Input/Output Ports TMP19A44 (rev1.3) 7-21 2010-04-01 TMP19A44 PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 P5PUP (output control) 0 (output control) External bus opening Latch 0 P5CR 1 RESET P5FC1 (function control) P5FC2 (function control) 1 P5 0 Port 5 P56,P57 (A6/ TB2OUT/KEY28 A7/TB3OUT/KEY2 9) 0 P5FC3 control 1 DPUP (function control) Latch Internal data bus (output latch) 1 Latch TB2OU T TB3OU T A6,A7 P5IE 0 (input control) 0 P5 read 1 KEY28,KEY29 Fig. 7.14 Port 5 (P56, P57) Input/Output Ports TMP19A44 (rev1.3) 7-22 2010-04-01 TMP19A44 Port 5 register 7 6 5 4 P57 P56 P55 P54 3 2 1 0 P53 P52 P51 P50 P5 Bit Symbol (0xFF00_4140) Read/Write R/W After reset Input mode (output latch register is set to "1.") Port 5 control register P5CR Bit Symbol (0xFF00_4144) Read/Write After reset 7 6 5 4 3 2 1 0 P57C P56C P55C P54C P53C P52C P51C P50C 0 0 0 0 3 2 1 0 P53F P52F P51F P50F 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port 5 function register 1 P5FC1 Bit Symbol (0xFF00_4148) Read/Write After reset 7 6 5 4 P57F P56F P55F P54F R/W 0 0 0 Function 0 0: Port 1: external bus Port 5 function register 2 P5FC2 (0xFF00_414C) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 P57F2 P56F2 P55F2 P54F2 P53F2 P52F2 P51F2 P50F2 R/W 0 0 0 0 0 0:PORT 0:PORT 0:PORT 0:PORT 0:PORT 1:TB3OUT 1:TB2OUT 1:TB1OUT 1:TB0OUT 1:INTF 0 0:PORT 1:INTE 0 0:PORT 1:INTD 0 0:PORT 1:INTC Port 5 function register 3 P5FC3 Bit Symbol (0xFF00_4150) Read/Write After reset Function 7 6 P57F3 P56F3 5 4 3 2 0 R 0 R/W 0 0:PORT 1:KEY29 0:PORT 1:KEY28 1 0 "0" is read. Port 5 pull-up control register P5PE (0xFF00_416C) Bit Symbol 7 6 5 4 3 2 1 0 PE57 PE56 PE55 PE54 PE53 PE52 PE51 PE50 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIE53 PIE52 PIE51 PIE50 0 0 Read/Write After reset Function R/W Port 5 Input enable control register P5IE (0xFF00_4178) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIE57 PIE56 PIE55 PIE54 R/W 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: 0: disabled disabled 1: Enabled 1: Enabled 0 0 Input 0: disabled 1: Enabled Input 0: disabled 1: Enabled TMP19A44 (rev1.3) 7-23 0 Input 0: disabled 1: Enabled Input Input 0: disabled 0: 1: Enabled disabled 1: Enabled 2010-04-01 TMP19A44 7.7 Port 6 (P60 through P67) The port 6 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P6CR and the function registers P6FC1, P6FC2 and P6FC3. A reset allows all bits of the output latch P6 to be set to "1," all bits of P6CR, P6FC1, P6FC2 andP6FC3 to be cleared to "0," and the port 6 to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of P6IE to "1". Besides the input/output port function, the port 6 performs other functions: P60 and P64 output SIO data, P61 and P65 input SIO data, P62 and P66 input and output SIO CLK or input CTS, P61 and P65 input external interrupts, and P63 and P67 output a 16-bit timer. The port 6 also functions as an address bus (A8 through A15). To access external memory, P6CR and P6FC1 must be provisioned to allow the port 6 to function as an address bus. The address bus function can be used only in separate bus mode. (To put the port 6 in separate bus mode, the BUSMD pin (port 45) must be set to "L" level during a reset.) Input/Output Ports TMP19A44 (rev1.3) 7-24 2010-04-01 TMP19A44 PORT KEEP Drive disabled during STOP/ RESET Latch P6PUP (output control) Latch 0 P6CR (output control) External bus opening 1 RESET P6FC1 (function control) P6FC2 (function control) 1 1 0 0 Port 6 P60,P64 (A8/TXD0,A12/TXD 1) Latch Internal data bus (output latch) TXD0, TXD1 Latch P6 A8,A12 P6OD (open drain control) Latch P6IE (input control) 0 P6 read 1 Fig. 7.15 Port 6 (P60, P64) Input/Output Ports TMP19A44 (rev1.3) 7-25 2010-04-01 TMP19A44 PORT KEEP Drive disabled during STOP/ RESET Latch P6PUP (output control) Latch 0 P6CR (output control) External bus opening 1 RESET P6FC1 (function control) P6FC2 (function control) A9,A13 Internal data bus (output latch) Latch P6 1 0 Port 6 P61,P65 (A9/RXD0/INTA, A13/RXD1/INTB) P6FC3 (function control) Latch P6IE (input control) 0 P6 read 1 RXD0, RXD1 INTA, INTB Fig. 7.16 Port 6 (P61, P65) Input/Output Ports TMP19A44 (rev1.3) 7-26 2010-04-01 TMP19A44 PORT KEEP P6PUP Latch Drive disabled during STOP/ RESET (output cotnrol) (output control) External bus opening Latch 0 P6CR 1 RESET P6FC1 (function control) P6FC3 (function control) (output latch) SCLK0, SCLK1 1 1 0 0 Latch P6 A9,A13 Latch Internal data bus Port 6 P62,P66 (A10/SCLK0/CTS0, A14/ SCLK1/CTS1) P6OD (open drain control) P6FC2 (function control) Latch P6IE (input control) 0 P6 read 1 SCLK0, SCLK1 /CTS0, /CTS1 Fig. 7.17 Port 6(P62, P66) Input/Output Ports TMP19A44 (rev1.3) 7-27 2010-04-01 TMP19A44 PORT KEEP Latch Drive disabled during STOP/ RESET P6PUP (output control) Latch 0 P6CR (output control) External bus opening 1 RESET P6FC1 (function control) P6FC2 TB4OUT TB5OUT P6 1 1 (output latch) 0 0 Latch A11,A15 (function control) Port 6 P63,P67 (A11/TB4OUT, A15/TB5OUT) Latch Internal data bus P6IE (input control) 0 P6 read 1 Fig. 7.18 Port 6 (P63, P67) Input/Output Ports TMP19A44 (rev1.3) 7-28 2010-04-01 TMP19A44 Port 6 register 7 6 5 4 P67 P66 P65 P64 3 2 1 0 P63 P62 P61 P60 P6 Bit Symbol (0xFF00_4180) Read/Write R/W After reset Input mode (output latch register is set to "1.") Port 6 control register P6CR Bit Symbol (0xFF00_4184) Read/Write After reset 7 6 5 4 3 2 1 0 P67C P66C P65C P64C P63C P62C P61C P60C 0 0 0 0 0 0 3 2 1 0 P63F P62F P61F P60F 0 0 0 0 3 2 1 0 P63F2 P62F2 P61F2 P60F2 R/W 0 0 Function 0: Input 1: Output Port 6 function register 1 P6FC1 Bit Symbol (0xFF00_4188) Read/Write After reset 7 6 5 4 P67F P66F P65F P64F R/W 0 0 0 Function 0 0: PORT 1:External bus Port 6 function register 2 P6FC2 Bit Symbol (0xFF00_418C) Read/Write After reset Function 7 6 5 4 P67F2 P66F2 P65F2 P64F2 R/W 0 0 0 0 0 0 0 0 0:PORT 1:TB5OU T 0:PORT 1:SCLK1 0:PORT 1:RXD1 0:PORT 1: TXD1 0:PORT 1:TB4OUT 0:PORT 1:SCLK0 0:PORT 1:RXD0 0:PORT 1: TXD0 7 6 5 4 3 2 1 0 P66F3 P65F3 P62F3 P61F3 Port 6 function register 3 P6FC3 Bit Symbol (0xFF00_4190) Read/Write After reset Function R R/W 0 0 0 "0" is read. "0" is read. 0:PORT R 0 R/W "0" is read. 1:INTB R 0 0 0:PORT 1:CTS0 0:PORT 1:INTA "0" is read. 2 P62ODE 1 0 P60ODE R/W 0 Port 6 open drain control register 7 P6ODE Bit Symbol (0xFF00_ 41A8) Read/Write After reset Function R 0 "0" is read. 6 P66ODE R/W 0 0: CMOS 1: Open drain 5 R 0 "0" is read. 4 P64ODE R/W 0 0: CMOS 1: Open drain 3 R 0 "0" is read. R/W 0 0: CMOS 1: Open drain R 0 "0" is read. 0: CMOS 1: Open drain Port 6 pull-up control register P6PUP Bit Symbol (0xFF00_41AC) Read/Write After reset Function Input/Output Ports 7 6 5 4 PE67 PE66 PE65 PE64 3 2 1 0 PE63 PE62 PE61 PE60 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up TMP19A44 (rev1.3) 7-29 2010-04-01 TMP19A44 7.8 Port 7 (P70 through P77) The port 7 is an 8-bit, analog input port for the A/D converter (unit A and B). Although P72 P73, P76 and P77 form part of the analog input port, they also perform another function of inputting external interrupt. Drive disabled during STOP/ RESET PORT KEEP Latch P7PUP (input control) Latch Internal data bus P7IE Port 7 P70,P71,P74,P75 (AINA0,1,AINB0,1) (input control) P7 read AINA0,1AINIB0,1 Fig. 7.19 Port 7 (P70, P71, P74 and P75) Input/Output Ports TMP19A44 (rev1.3) 7-30 2010-04-01 TMP19A44 Drive disabled during STOP/ RESET PORT KEEP Latch Internal data bus P7PUP (input control) P7FC2 (function control) Latch P7IE (input control) Port 7 P72,P73,P76,P77 (AINA2,3,AINB2,3 INT10,11,INT12,13) P7 read INT10,INT11 INT12,INT13 AINA2,3 AINB2,3 Fig. 7.20 Port 7 (P72, P73, P76 and P77) Input/Output Ports TMP19A44 (rev1.3) 7-31 2010-04-01 TMP19A44 7 6 P77 P76 Port 7 register 5 4 P75 P74 3 2 1 0 P73 P72 P71 P70 P7 Bit Symbol (0xFF00_41C0) Read/Write R After reset Input mode Port 7 function register 2 P7FC2 Bit Symbol (0xFF00_41CC) Read/Write After reset Function 7 6 5 4 3 2 1 0 P77F2 P76F2 P77F2 P76F2 R/W (0xFF00_41EC) Bit Symbol 0 0 0:PORT 1: INTC13 0:PORT 1: INTC12 "0" is read. Function After reset Function Input/Output Ports 0 Port 7 pull-up control register 6 5 4 "0" is read. 3 2 1 0 PE73 PE72 PE71 PE70 PE77 PE76 PE75 PE74 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 2 1 0 PIE72 PIE71 PIE70 0 0 R/W 7 Bit Symbol Read/Write R 0 0:PORT 0:PORT 1: INTC11 1: INTC10 Read/Write After reset P7IE (0xFF00_41F 8) R/W 0 7 P7PUP R 0 PIE77 Port 7 Input enable control register 6 5 4 3 PIE76 PIE75 PIE74 PIE73 R/W 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: 0: disabled disabled 1: Enabled 1: Enabled 0 0 Input 0: disabled 1: Enabled Input 0: disabled 1: Enabled TMP19A44 (rev1.3) 7-32 0 Input 0: disabled 1: Enabled Input Input 0: disabled 0: 1: Enabled disabled 1: Enabled 2010-04-01 TMP19A44 7.9 Port 8 (P80 through P87) The port 8 is an 8-bit, analog input port for the A/D converter (unit C). Besides this analog input port function, P86 and P87 input external interrupts. Drive disabled during PORT KEEP STOP/ RESET Latch P8PUP (input control) Latch Internal data bus P8IE Port 8 P80~P85 (AINC0~5) (input control) P8 read AINC0~AIN5 Fig. 7.21 Port 8 (P80 through P85) Input/Output Ports TMP19A44 (rev1.3) 7-33 2010-04-01 TMP19A44 PORT KEEP Latch Drive disabled during STOP/ RESET P8PUP (input control) Latch Internal data bus P8FC2 (function control) P8IE Port 8 P86,P87 (AINC6/INT8, AINC7/INT9) (input control) P8 read INT8,INT9 AINC6,7 Fig. 7.22 Port 8 (P86, P87) Input/Output Ports TMP19A44 (rev1.3) 7-34 2010-04-01 TMP19A44 Port 8 register P8 (0xFF00_4200) Bit Symbol 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 Read/Write R After reset Input mode Port 8 function register 2 P8FC2 Bit Symbol (0xFF00_420C) Read/Write After reset Function 7 6 5 4 3 2 1 0 P87F2 P86F2 R/W 0 0 0:PORT 0:PORT 1: INTC9 1: INTC8 R 0 "0" is read. Port 8 pull-up control register P8PUP (0xFF00_422C) Bit Symbol 7 6 5 4 3 2 1 0 PE87 PE86 PE85 PE84 PE83 PE82 PE81 PE80 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIE83 PIE82 PIE81 PIE80 0 0 Read/Write After reset Function R/W Port 8 Input enable control register P8IE (0xFF00_4238) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIE87 PIE86 PIE85 PIE84 R/W 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: 0: disabled disabled 1: Enabled 1: Enabled 0 0 Input 0: disabled 1: Enabled Input 0: disabled 1: Enabled TMP19A44 (rev1.3) 7-35 0 Input 0: disabled 1: Enabled Input Input 0: disabled 0: 1: Enabled disabled 1: Enabled 2010-04-01 TMP19A44 7.10 Port 9 (P90 through P97) The port 9 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register P9CR and the function registers P9FC1 and P9FC2. A reset allows all bits of the output latch P9 to be set to "1," all bits of P9CR, P9FC1 and P9FC2 to be cleared to "0," and the port 9 to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of P9IE to "1". Besides the input/output port function, the port 9 performs other functions: P90 and P94 output HSIO/SI0 data, P92 and P96 inputs and outputs SI0 CLK or inputs CTS, and P93 and P97 output a 16-bit timer. PORT KEEP P9PUP Latch Drive disabled during STOP/ RESET (output control) Latch P9CR (output control) RESET (function control) P9 1 HTXD0, TXD2 Latch Internal data bus P9FC1 (output latch) (open drain control) Latch 0 P9OD Port 9 P90(HTXD0) P94(TXD2) Latch P9IE (input control) 0 P9 read 1 Fig. 7.23 Port 9 (P90, P94) Input/Output Ports TMP19A44 (rev1.3) 7-36 2010-04-01 TMP19A44 PORT KEEP P9PUP Latch Drive disabled during STOP/ RESET (output control) Latch P9CR (output control) RESET P9FC1 (function control) Latch P9 (output latch) Port 9 P91(HRXD0), P95(RXD2) Latch Internal data bus P9IE (input control) 0 P9 read 1 HRXD0 ,RXD2 Fig. 7.24 Port 9 (P91, P95) Input/Output Ports TMP19A44 (rev1.3) 7-37 2010-04-01 TMP19A44 PORT KEEP P9PUP Latch Drive disabled during STOP/ RESET (output control) Latch P9CR (output control) RESET P9FC1 (function control) P9FC2 (function control) (output latch) Latch Internal data bus P9 HSCLK0, 1 SCLK2 0 Port 9 P92 (HSCLK0/ HCTS0), P96(SCLK2/ CTS2) Latch P9OD (open drain control) Latch P9IE (input control) 0 P9 read 1 HSCLK0, SCLK2 Fig. 7.25 Port 9 (P92, P96) Input/Output Ports TMP19A44 (rev1.3) 7-38 2010-04-01 TMP19A44 PORT KEEP P9PUP Latch Drive disabled during STOP/ RESET (output control) Latch P9CR (output control) RESET P9FC1 P9 TB9OUT, 1 TBAOUT (output latch) Latch Internal data bus (function control) 0 Port 9 P93(TB9OUT) , P97(TBAOUT ) Latch P9IE (input control) 0 P9 read 1 Fig. 7.26 Port 9 (P93, P97) Input/Output Ports TMP19A44 (rev1.3) 7-39 2010-04-01 TMP19A44 Port 9 register P9 (0xFF00_4240) Bit Symbol 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port 9 control register P9CR Bit Symbol (0xFF00_4244) Read/Write After reset 7 6 5 4 P97C P96C P95C P94C 3 2 1 0 P93C P92C P91C P90C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port 9 function register 1 P9FC1 Bit Symbol (0xFF00_4248) Read/Write After reset Function 7 6 5 4 3 2 1 0 P97F P96F P95F P94F P93F P92F P91F P90F 0 0:PORT 1:TB9OUT 0 0:PORT 1:HSCLK 0 0 0:PORT 1:HRXD0 0 0:PORT 1:HTXD0 0 R/W 0 0:PORT 1:TBAOU T 0 0:PORT 1:SCLK2 0 0:PORT 1:RXD2 0 0:PORT 1:TXD2 7 6 5 4 3 2 1 P92F Port 9 function register 2 P9FC2 Bit Symbol P96F (0xFF00_424C) Read/Write R R/W R R/W R After reset Function 0 "0" is read. 0 0:PORT 1:CTS2 0 "0" is read. 0 0:PORT 1:HCTS0 0 "0" is read. Port 9 open drain control register P9ODE (0xFF00_4268) 7 6 5 4 3 2 1 0 Bit Symbol Read/Write R P96ODE R/W R P94ODE R/W R P92ODE R/W R P90ODE R/W After reset Function 0 "0" Is read. 0 0 "0" Is read. 0 0 "0" Is read. 0 0 "0" Is read. 0: CMOS 1: Open drain 0: CMOS 1: Open drain 0: CMOS 1: Open drain 0 0: CMOS 1: Open drain Port 9 pull-up control register P9PUP Bit Symbol (0xFF00_426C) Read/Write After reset Function 7 6 5 4 3 2 1 0 PE97 PE96 PE95 PE94 PE93 PE92 PE91 PE90 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIE93 PIE92 PIE91 PIE90 Port 9 Input enable control register P9IE (0xFF00_4278) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIE97 PIE96 PIE95 PIE94 R/W 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: 0: disabled disabled 1: Enabled 1: Enabled 0 Input 0: disabled 1: Enabled TMP19A44 (rev1.3) 7-40 0 Input 0: disabled 1: Enabled 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: disabled 0: 1: Enabled disabled 1: Enabled 2010-04-01 TMP19A44 7.11 Port A (PA0 through PA7) The port A is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PACR and the function registers PAFC1 and PAFC2. A reset allows all bits of the output latch PA to be set to "1," all bits of PACR, PAFC1 and PAFC2 to be cleared to "0," and the port A to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PAIE to "1". Besides the input/output port function, the port A performs other functions: PA0 through PA5 input external interrupts, PA0 through PA3, PA6 and PA7 count two-phase pulse input, and PA6 and PA7 input 16-bit timer. PORT KEEP Latch Drive disabled during STOP/ RESET PAPUP (output control) Latch PACR (output control) RESET PAFC1 (function control) PAFC2 (function control) Latch PA (output latch) Port A PA0~PA3 (IN0~INT/PC0N0,PHC0I 1,PHCIN0,PHC1I1 Latch Internal data bus PAIE (input control) 1 PA read PHC0IN0,PHC0IN1, PHC1IN0,PHC1IN1 INT0~INT3 Fig. 7.27 Port A (PA0 through PA3) Input/Output Ports TMP19A44 (rev1.3) 7-41 2010-04-01 TMP19A44 PORT KEEP Latch Drive disabled during STOP/ RESET PAPUP (output control) Latch PACR (output control) Internal data bus RESET PAFC1 (function control) PAFC2 (function control) Latch PA (output latch) Port A PA4,PA5 (INT4,INT5/ TB6IN0,TB6IN1) Latch PAIE (input control) 0 PA read 1 TB6IN0,TB6IN1 INT4,INT5 Fig. 7.28 Port A (PA4, PA5) Input/Output Ports TMP19A44 (rev1.3) 7-42 2010-04-01 TMP19A44 PORT KEEP PAPUP Latch Drive disabled during STOP/ RESET (output control) Latch Internal data bus PACR (output control) RESET PAFC1 (function control) Latch PA (output latch) Port A PA6, PA7 (PHC2IN0,PHC2IN1 ) Latch PAIE (input control) 0 1 PA read PHC2IN0, PHC2IN1 Fig. 7.29 Port A (PA6,PA7) Input/Output Ports TMP19A44 (rev1.3) 7-43 2010-04-01 TMP19A44 Port A register PA (0xFF00_4280) Bit Symbol 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port A control register PACR Bit Symbol (0xFF00_4284) Read/Write After reset 7 6 5 4 PA7C PA6C PA5C PA4C 3 2 1 0 PA3C PA2C PA1C PA0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port A function register 1 PAFC1 (0xFF00_4288) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F 0 0:PORT 1:PHC2IN 0 0 0:PORT 1:PHC2IN 0 0 0:PORT 1:INT5 0 0:PORT 1:INT2 0 0:PORT 1:INT1 0 0:PORT 1:INT0 7 6 5 4 3 2 1 0 PA5F2 PA4F2 PA3F2 PA2F2 PA1F2 PA0F2 0 0:PORT 1:PHC1IN 0 0 0:PORT 1:PHC0IN 1 0 0:PORT 1:PHC0IN 0 3 2 1 0 PEA3 PEA2 PEA1 PEA0 R/W 0 0 0:PORT 0:PORT 1:INT4 1:INT3 Port A function register 2 PAFC2 Bit Symbol (0xFF00_428C) Read/Write After reset Function 0 0 0:PORT 1:TB6IN1 "0" is read. R/W 0 0 0:PORT 0:PORT 1:TB6IN0 1:PHC1IN 1 Port A pull-up control register PAPE Bit Symbol (0xFF00_42AC) Read/Write After reset Function 7 6 5 4 PEA7 PEA6 PEA5 PEA4 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Port A Input enable control register PAIE (0xFF00_42B8) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 3 2 1 0 PIEA7 PIEA6 PIEA5 PIEA4 PIEA3 PIEA2 PIEA1 PIEA0 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: 0: disabled disabled 1: Enabled 1: Enabled R/W 0 0 Input Input 0: 0: disabled disabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-44 0 Input 0: disabled 1: Enabled 0 0 Input Input 0: disabled 0: 1: Enabled disabled 1: Enabled 2010-04-01 TMP19A44 7.12 Port B (PB0 to PB7) Port B is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PBCR and the function registers PBFC1 and PBFC2. A reset allows all bits of the output latch PB to be set to "1," all bits of PBCR, PBFC1 and PBFC2 to be cleared to "0," and the port B to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PBIE to "1". Besides the input/output port function, the port B performs other functions: PB2, PB3 and PB7 output 16-bit timer, PB4 outputs HSIO data, PB5 inputs HSIO data, PB6 inputs and outputs HSIO HCLK or input HCTS, and PB0 and PB1 perform a two-phase pulse input counter function with a dial input function. PORT KEEP PBPUP Latch Drive disabled during STOP/ RESET (output control) Latch PBCR (output control) RESET PBFC1 (function control) Latch PB Internal data bus (output latch) Port B PB0, PB1 (PHC3IN0,PHC3IN 1) Latch PBIE (input control) 0 PB read 1 PHC3IN0, PHC3IN1 Fig. 7.30 Port B (PB0, PB1) Input/Output Ports TMP19A44 (rev1.3) 7-45 2010-04-01 TMP19A44 PORT KEEP PBPUP Latch Drive disabled during STOP/ RESET (output control) Latch PBCR (output control) RESET PBFC1 PB TB6OUT, TB7OUT, TB8OUT 1 Latch Internal data bus (function control) (output latch) 0 Port B PB2,PB3,PB7 (TB6OUT,TB7OUT, TB8OUT) Latch PBIE (input control) 0 PB read 1 Fig. 7.31 Port B (PB2, PB3, PB7) Input/Output Ports TMP19A44 (rev1.3) 7-46 2010-04-01 TMP19A44 PORT KEEP PBPUP Latch Drive disabled during STOP/ RESET (output control) Latch PBCR (output control) RESET PBFC1 (function control) 1 Latch Internal data bus HTXD1 PB (output latch) PBOD (open drain control) Latch 0 Port B PB4(HTXD1) Latch PBIE (input control) 0 PB read 1 Fig. 7.32 Port B (PB4) Input/Output Ports TMP19A44 (rev1.3) 7-47 2010-04-01 TMP19A44 PORT KEEP PBPUP Latch Drive disabled during STOP/ RESET (output control) Latch PBCR (output control) RESET PBFC1 (function control) Latch Internal data bus PB (output latch) Port B PB5(HRXD1) Latch PBIE (input control) 0 PB read 1 HRXD1 Fig. 7.33 Port B (PB5) Input/Output Ports TMP19A44 (rev1.3) 7-48 2010-04-01 TMP19A44 PORT KEEP PBPUP Latch Drive disabled during STOP/ RESET (output control) Latch PBCR (output control) RESET PBFC1 (function control) PBFC2 HSCLK1 1 Latch PB (output latch) 0 Latch Internal data bus (function control) PBOD (open drain control) Latch PBIE (input control) 0 PB read 1 HSCLK1 HCTS1 Fig. 7.34 Port B (PB6) Input/Output Ports TMP19A44 (rev1.3) 7-49 2010-04-01 TMP19A44 Port B register PB (0xFF00_42C0) Bit Symbol 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port B control register PBCR Bit Symbol (0xFF00_42C4) Read/Write After reset 7 6 5 4 PB7C PB6C PB5C PB4C 3 2 1 0 PB3C PB2C PB1C PB0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port B function register 1 PBFC1 Bit Symbol (0xFF00_42C8) Read/Write After reset Function 7 6 5 4 3 2 1 0 PB7F PB6F PB5F PB4F PB3F PB2F PB1F PB0F 0 0:PORT 1:TB6OU T 0 0:PORT 1PHC3IN1 0 0:PORT 1: PHC3IN0 R/W 0 0:PORT 1:TB8OU T 0 0:PORT 1: HSCLK0 0 0:PORT 1:HRXD1 0 0 0:PORT 0:PORT 1: HTXD1 1:TB7OUT Port B function register 2 7 6 5 4 3 2 1 0 PBFC2 Bit Symbol PB6F2 (0xFF00_42CC) Read/Write After reset Function R 0 "0" is read. R/W 0 0:PORT 1:/HCTS0 R 0 "0" is read. Port B open drain control register PBODE (0xFF00_42E8) 7 6 5 4 3 2 1 0 PB6ODE R/W R PB4ODE R/W Read/Write R After reset Function 0 "0" is read. 0 0 "0" is read. 0 Bit Symbol 0: CMOS 1: Open drain R 0 "0" is read. 0: CMOS 1: Open drain Port B pull-up control register PBPUP Bit Symbol (0xFF00_42EC) Read/Write After reset Function Input/Output Ports 7 6 5 4 PEB7 PEB6 PEB5 PEB4 3 2 1 0 PEB3 PEB2 PEB1 PEB0 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up TMP19A44 (rev1.3) 7-50 2010-04-01 TMP19A44 7.13 Port C (PC0 to PC7) Port C is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PCCR and the function registers PCFC1 and PCFC2. A reset allows all bits of the output latch PC to be set to "1," all bits of PCCR, PCFC1 and PCFC2 to be cleared to "0," and the port C to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PCIE to "1". Besides the input/output port function, the port C performs other functions: PC0 inputs external clock sources into a 32-bit time base timer and inputs the key-on wake-up, PC1 through PC3 and PC7 perform the 32-bit compare output function, and PC4 through PC6 input and output SBI. PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 PCPUP 0 (output control) Latch PCCR (output control) RESET PCFC1 (function control) Latch PC Port C PC0 (TBTIN/KEY30) (output latch) control 1 DPUP Latch Internal data bus PCFC2 (function control) PCIE 0 (input control) 0 PC read 1 TBTIN KEY30 Fig. 7.35 Port C (PC0) Input/Output Ports TMP19A44 (rev1.3) 7-51 2010-04-01 TMP19A44 PORT KEEP PCPUP Latch Drive disabled during STOP/ RESET (output control) Latch PCCR (output control) RESET PCFC1 TCOUT0~TC1 OUT3 PC (output latch) Latch Internal data bus (function control) 0 Port C PC1~PC3,PC7 (TCOUT0~TCOUT3 ) Latch PCIE (input control) 0 PC read 1 Fig. 7.36 Port C (PC1 through PC3, PC7) Input/Output Ports TMP19A44 (rev1.3) 7-52 2010-04-01 TMP19A44 PORT KEEP PCPUP Latch Drive disabled during STOP/ RESET (output control) Latch PCCR (output control) RESET Internal data bus PCFC1 (function control) SDA/SO 1 Latch PC (output latch) Port C PC4(SO/SDA) 0 Latch PCOD (open drain control) Latch PCIE (input control) 0 1 PC read SDA Fig. 7.37 Port C (PC4) Input/Output Ports TMP19A44 (rev1.3) 7-53 2010-04-01 TMP19A44 PORT KEEP PCPUP Latch Drive disabled during STOP/ RESET (output control) Latch PCCR (output control) RESET PCFC1 (function control) 1 Latch Internal data bus SCL0 PC (output latch) Port C PC5(SI/ SCL) 0 Latch PCOD (open drain control) Latch PCIE (input control) 0 PC read 1 SI/SCL Fig. 7.38 Port C(PC5) Input/Output Ports TMP19A44 (rev1.3) 7-54 2010-04-01 TMP19A44 PCPUP PORT KEEP Latch Drive disabled during STOP/ RESET (output control) Latch PCR (output control) RESET PCFC1 (function control) 1 Latch Internal data bus SCK0 PC (output latch) Port C PC6(SCK) 0 Latch PCOD (open drain control) Latch PCIE (input control) 0 PC read 1 SCK Fig. 7.39 Port C (PC6) Input/Output Ports TMP19A44 (rev1.3) 7-55 2010-04-01 TMP19A44 Port C register PC (0xFF00_4300) Bit Symbol 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port C control register PCCR Bit Symbol (0xFF00_4304) Read/Write After reset 7 6 5 4 PC7C PC6C PC5C PC4C 3 2 1 0 PC3C PC2C PC1C PC0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port C function register 1 PCFC1 Bit Symbol (0xFF00_4308) Read/Write After reset Function 7 6 5 4 3 2 1 0 PC7F PC6F PC5F PC4F PC3F PC2F PC1F PC0F 0 0:PORT 1:TCOUT 3 0 0:PORT 1:SCK 0 0:PORT 1:SI /SCL 0 0:PORT 1:TCOUT 1 0 0:PORT 1:TCOUT0 0 0:PORT 1: TBTIN 7 6 5 4 3 2 1 0 PC0F2 R/W 0 0 0:PORT 0:PORT 1:SO 1:TCOUT 2 /SDA Port C function register 2 PCFC2 Bit Symbol (0xFF00_430C) Read/Write After reset R 0 Function R/W 0 "0" is read. 0:PORT 1: /KEY30 Port C open drain control register PCODE Bit Symbol (0xFF00_4328) Read/Write After reset Function 7 6 5 4 3 2 1 0 R 0 "0" is read. PC6ODE PC4ODE 0 PC5ODE R/W 0 0: CMOS 1: Open drain 0: CMOS 1: Open drain 0: CMOS 1: Open drain R 0 "0" is read. 0 Port C pull-up control register PCPE (0xFF00_432C) Bit Symbol 7 6 5 4 3 2 1 0 PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIEC3 PIEC2 PIEC1 PIEC0 Read/Write After reset Function R/W Port C input enable control register PCIE (0xFF00_4338) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIEC7 PIEC6 PIEC5 PIEC4 R/W 0 Input 0: Disabled 1: Enabled 0 0 0 0 Input Input Input Input 0: 0: 0: 0: Disabled Disabled Disabled Disabled 1: Enabled 1: Enabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-56 0 Input 0: Disabled 1: Enabled 0 0 Input Input 0: 0: Disabled Disabled 1: Enabled 1: Enabled 2010-04-01 TMP19A44 7.14 Port D (PD0 to PD7) The port D is a general-purpose, 7-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PDCR and the function registers PDFC1 and PDFC2. A reset allows all bits of the output latch PD to be set to "1," all bits of PDCR, PDFC1 and PDFC2 to be cleared to "0," and the port D to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PDIE to "1". Besides the input port function, the port D performs other functions: PD0 outputs HSIO data, PD1 inputs HSIO data, PD2 inputs and outputs HSIO HCLK or inputs HCTS, PD3, PD4 and PD5 output a 16-bit timer, and PD6 inputs the key-on wake-up, PD6 and PD7 input A/D triggers into the A/D converter. PORT KEEP PDPUP Latch Drive disabled during STOP/ RESET (output control) Latch PDCR (output control) RESET PDFC1 (function control) Internal data bus HTXD2 1 Latch PD (output latch) Port D PD0(HTXD2) 0 Latch PDOD (open drain control) Latch PDIE (input control) 0 PD read 1 Fig. 7.40 Port D (PD0) Input/Output Ports TMP19A44 (rev1.3) 7-57 2010-04-01 TMP19A44 PORT KEEP PDPUP Latch Drive disabled during STOP/ RESET (output control) Latch PDCR (output control) RESET PDFC1 (function control) Latch Internal data bus PD (output latch) Port D PD1(HRXD2) Latch PDIE (input control) 0 PD read 1 HRXD2 Fig. 7.41 Port D (PD1) Input/Output Ports TMP19A44 (rev1.3) 7-58 2010-04-01 TMP19A44 PORT KEEP PDPUP Latch Drive disabled during STOP/ RESET (output control) Latch PDCR (output control) RESET PDFC1 (function control) PDFC2 (function control) 1 HSCLK2 Latch Internal data bus PD (output latch) Port D PD2(HSCLK2/ HCTS2) 0 PDOD (open drain control) Latch PDIE (input control) 0 PD read 1 HSCLK2 HCTS2 Fig. 7.42 Port D (PD2) Input/Output Ports TMP19A44 (rev1.3) 7-59 2010-04-01 TMP19A44 PORT KEEP PDPUP Latch Drive disabled during STOP/ RESET (output control) Latch PDCR (output control) RESET PDFC1 (function control) PD (output latch) TBBOUT~TBD OUT 0 Latch Internal data bus 1 Port D PD3~PD5 (TBBOUT~TBDOUT) Latch PDIE (input control) 0 PD read Input/Output Ports 1 Fig. 7.43 Port D (PD3 through PD5) TMP19A44 (rev1.3) 7-60 2010-04-01 TMP19A44 PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 PDPUP 0 (output control) Latch PDCR (output control) RESET PDFC1 (function control) PDFC2 (function control) Port D PD6 (KEY31/ADTRGA) Latch (output latch) DPUP control Latch Internal data bus PD 1 PDIE (input control) 0 PD read 1 ADTRGA KEY31 Fig. 7.44 Port D (PD6) Input/Output Ports TMP19A44 (rev1.3) 7-61 2010-04-01 TMP19A44 PORT KEEP PDPUP Latch Drive disabled during STOP/ RESET (output control) Latch PDCR (output control) RESET PDFC1 (function control) Latch PD (output latch) Port D PD7 (ADTRGB) Latch PDIE (input control) 0 1 PD read ADTRGB Fig. 7.45 Port D (PD7) Input/Output Ports TMP19A44 (rev1.3) 7-62 2010-04-01 TMP19A44 Port D register PD (0xFF00_4340) Bit Symbol 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port D control register PDCR Bit Symbol (0xFF00_4344) Read/Write After reset 7 6 5 4 PD7C PD6C PD5C PD4C 3 2 1 0 PD3C PD2C PD1C PD0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port D function register 1 PDFC1 Bit Symbol (0xFF00_4348) Read/Write After reset Function 7 6 5 4 3 2 1 0 PD7F PD6F PD5F PD4F PD3F PD2F PD1F PD0F 0 0:PORT 1:ADTRG 0 0:PORT 1:/KEY31 0 0:PORT 1:TBDOU T 0 0:PORT 1:HSCLK2 0 0:PORT 1:HRXD2 0 0:PORT 1:HTXD2 7 6 5 4 3 2 1 0 PD2F2 R/W 0 0 0:PORT 0:PORT 1:TBCOU 1:TBBOU T T Port D function register 2 PDFC2 Bit Symbol PD6F2 (0xFF00_434C) Read/Write After reset Function R 0 "0" is read. R/W 0 0:PORT 1:ADTRG R 0 "0" is read. R/W 0 0:PORT 1: /HCTS2 R 0 "0" is read. Port D open drain control register PDODE (0xFF00_4368) Bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 R 0 PD2ODE R/W 0 R 0 PD0ODE R/W 0 0: CMOS 1: Open drain "0" is read. 0: CMOS 1: Open drain 3 2 1 0 PED3 PED2 PED1 PED0 Function "0" is read. Port D pull-up control register PDPUP (0xFF00_436C) Bit Symbol Read/Write After reset Function 7 6 5 4 PED7 PED6 PED5 PED4 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIED3 PIED2 PIED1 PIED0 Port D Input enable control register PDIE (0xFF00_4378) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIED7 PIED6 PIED5 PIED4 R/W 0 0 0 0 0 0 0 0 Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled Input 0: Disabled 1: Enabled TMP19A44 (rev1.3) 7-63 2010-04-01 TMP19A44 7.15 Port E (PE0 through PE7) The port E is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PECR and the function register PEFC1. A reset allows all bits of the output latch PE to be set to "1," all bits of PECR and PEFC to be cleared to "0," and the port E to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PEIE to "1". Besides the input/output port function, the port E performs the key-on wake-up input function. PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 PEPUP (output control) 0 Latch PECR (output control) RESET PEFC1 (function control) Latch Port E PE0~7 (KEY08~KEY15) (output latch) DPUP control Latch Internal data bus PE 1 PEIE (input control) 0 1 PE read KEY08~KEY15 Fig. 7.46 Port E (PE0 through PE7) Input/Output Ports TMP19A44 (rev1.3) 7-64 2010-04-01 TMP19A44 Port E register PE (0xFF00_4380) Bit Symbol 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port E control register PECR Bit Symbol (0xFF00_4384) Read/Write After reset 7 6 5 4 PE7C PE6C PE5C PE4C 3 2 1 0 PE3C PE2C PE1C PE0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port E function register 1 PEFC1 (0xFF00_4388) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PE7F PE6F PE5F PE4F PE3F PE2F PE1F PE0F 0 0:PORT 1:KEY15 0 0:PORT 1:KEY14 0 0:PORT 1:KEY13 0 0:PORT 1:KEY10 0 0:PORT 1:KEY09 0 0:PORT 1:KEY08 R/W 0 0 0:PORT 0:PORT 1:KEY12 1:KEY11 Port E pull-up control register PEPUP (0xFF00_43AC) Bit Symbol 7 6 5 4 3 2 1 0 PEE7 PEE6 PEE5 PEE4 PEE3 PEE2 PEE1 PEE0 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIEE3 PIEE2 PIEE1 PIEE0 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled Read/Write After reset Function R/W Port E Input enable control register PEIE (0xFF00_43B8) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIEE7 PIEE6 PIEE5 PIEE4 R/W 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled TMP19A44 (rev1.3) 7-65 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.16 Port F (PF0 through PF7) The port F is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PFCR and the function registers PFFC1 and PFFC2. A reset allows all bits of the output latch PF to be set to "1," all bits of PFCR, PFFC1 and PFFC2 to be cleared to "0," and the port F to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PFIE to "1". Besides the input/output port function, the port F inputs external clock source of 32-bit time base timer and performs the key-on wake-up input function, PF1 through PF3 and PC7 perform a 32-bit timer compare output function and PC4 through PC6 perform SBI input/ output function.. PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 PFPUP (output control) 0 Latch PFCR (output control) RESET PFFC1 (function control) PFFC2 Latch PF (output latch) 1 DPUP control Latch Internal data bus (function control) Port F PF0,PF2 (KEY16/DREQ0, KEY18/DREQ4) PFIE 0 (input control) 0 1 PF read DREQ0,DREQ4 KEY16,18 Fig. 7.47 Port F (PF0, PF2) Input/Output Ports TMP19A44 (rev1.3) 7-66 2010-04-01 TMP19A44 PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 PFPUP 0 (output control) Latch PFCR (output control) RESET PFFC1 (function control) PFFC2 (function control) DACK0,4 1 PF (output latch) 0 Latch 1 DPUP control Latch Internal data bus TCOUT4~TC OUT7 Port F PF1,PF3~ PF7 (KEY17/DACK0, KEY19/DACK4, KEY20/TCOUT4 ~KEY23/TCOUT7) PFIE (input control) 0 PF read 1 KEY17,19~KEY23 Fig. 7.48 Port F (PF1, PF3 through PF7) Input/Output Ports TMP19A44 (rev1.3) 7-67 2010-04-01 TMP19A44 Port F register 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PF Bit Symbol (0xFF00_43C0) Read/Write R/W After reset Input mode (output latch register is set to "1.") Port F control register PFCR Bit Symbol (0xFF00_43C4) Read/Write After reset 7 6 5 4 PF7C PF6C PF5C PF4C 3 2 1 0 PF3C PF2C PF1C PF0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port F function register 1 PFFC1 (0xFF00_43C8) 7 6 5 4 3 2 1 0 Bit Symbol Read/Write PF7F PF6F PF5F PF4F PF3F PF2F PF1F PF0F After reset Function 0 0:PORT 1:/ KEY23 0 0:PORT 1:/KEY19 0 0:PORT 1:/KEY18 0 0:PORT 1:/KEY17 0 0:PORT 1:/KEY16 R/W 0 0 0:PORT 0:PORT 1:/ KEY22 1:/KEY21 0 0:PORT 1:/KEY20 Port F function register 2 PFFC2 (0xFF00_43CC) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PF7F PF6F PF5F PF4F PF3F PF2F PF1F PF0F 0 0:PORT 1:TCOUT 7 0 0:PORT 1:TCOUT 6 0 0:PORT 1:DREQ4 0 0:PORT 1:DACK0 0 0:PORT 1:DREQ0 R/W 0 0 0 0:PORT 0:PORT 0:PORT 1:TCOUT5 1:TCOUT 1:DACK4 4 Port F pull-up control register PFPE Bit Symbol (0xFF00_43EC) Read/Write After reset Function 7 6 5 4 3 2 1 0 PEF7 PEF6 PEF5 PEF4 PEF3 PEF2 PEF1 PEF0 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Port F input enable control register PFIE (0xFF00_43F8) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 3 2 1 0 PIEF7 PIEF6 PIEF5 PIEF4 PIEF3 PIEF2 PIEF1 PIEF0 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled R/W 0 0 Input Input 0: 0: Disabled Disabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-68 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.17 Port G (PG0 through PG7) The port G is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PGCR and the function register PGFC1. A reset allows all bits of the output latch PG to set to "1," all bits of PGCR and PGFC1 to be cleared to "0," and the port G to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PGIE to "1". Besides the input/output port function, the port G performs the key-on wake-up input function. PORT KEEP DPUP control Latch Drive disabled during STOP/ RESET 1 PGPUP (output control) 0 Latch PGCR (output control) RESET PGFC1 (function control) Port G PG0~7 (KEY00~KEY07) Latch (output latch) DPUP control Latch Internal data bus PG 1 PGIE (input control) 0 PG read 1 KEY00~KEY07 Fig. 7.49 Port G (PG0 through PG7) Input/Output Ports TMP19A44 (rev1.3) 7-69 2010-04-01 TMP19A44 Port G register PG (0xFF00_4400) Bit Symbol 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port G control register PGCR Bit Symbol (0xFF00_4404) Read/Write After reset 7 6 5 4 PG7C PG6C PG5C PG4C 3 2 1 0 PG3C PG2C PG1C PG0C 0 0 0 0 R/W 0 0 0 Function 0 0: Input 1: Output Port G function register 1 PGFC1 (0xFF00_4408) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PG7F PG6F PG5F PG4F PG3F PG2F PG1F PG0F 0 0:PORT 1:KEY07 0 0:PORT 1:KEY06 0 0:PORT 1:KEY05 0 0:PORT 1:KEY02 0 0:PORT 1:KEY01 0 0:PORT 1:KEY00 3 2 1 0 PEG3 PEG2 PEG1 PEG0 R/W 0 0 0:PORT 0:PORT 1:KEY04 1:KEY03 Port G pull-up control register PGPUP Bit Symbol (0xFF00_442C) Read/Write After reset Function 7 6 5 4 PEG7 PEG6 PEG5 PEG4 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Port G input enable control register PGIE Bit Symbol (0xFF00_4438) Read/Write After reset Function Input/Output Ports 7 6 5 4 3 2 1 0 PIEG7 PIEG6 PIEG5 PIEG4 PIEG3 PIEG2 PIEG1 PIEG0 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled R/W 0 0 Input Input 0: 0: Disabled Disabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-70 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.18 Port H (PH0 through PH7) The port H is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PHCR and the function registers PHFC1 and PHFC2. A reset allows all bits of the output latch PH to be set to "1," all bits of PHCR to be cleared to "0," and the port H to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PHIE to "1". Besides the port function, the port H inputs external interrupts and a 16-bit timer. PORT KEEP PHPUP Latch Drive disabled during STOP/ RESET (output control) Latch PHCR (output control) RESET PHFC1 (function control) Latch Internal data bus PHFC2 (function control) PH (output latch) Port H PH0~PH3 (INT18~INT1B/ TB9IN0,TB9IN1 TBAIN0,TBAIN1) Latch PHIE (input control) 0 PH read 1 TB9IN0,TB9IN1, TBAIN0,TBAIN1 INT18~INT1B Fig. 7.50 Port H (PH0 through PH3) Input/Output Ports TMP19A44 (rev1.3) 7-71 2010-04-01 TMP19A44 PORT KEEP PHPUP (output control) h c t a L Drive disabled during STOP/ RESET h c t a L PHCR (output control) RESET PHFC1 (function control) PHFC2 (function control) h c t a L (output latch) h c t a L Internal data bus PH Port H PH4~PH7 (INT1C~INT1F/ TBBIN0,TBBIN1 TBDIN0,TBDIN1) PHIE (input control) 0 PH read 1 TBBIN0,TBBIN1, TBDIN0,TBDIN1 INT1C~INT1F Fig. 7.51 Port H (PH4 thorough PH7) Input/Output Ports TMP19A44 (rev1.3) 7-72 2010-04-01 TMP19A44 Port H register PH (0xFF00_4440) Bit Symbol 7 6 5 4 3 2 1 0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Read/Write R/W After reset Input mode (output latch register is set to "1.") Port H control register PHCR Bit Symbol (0xFF00_4444) Read/Write After reset 7 6 5 4 PH7C PH6C PH5C PH4C 3 2 1 0 PH3C PH2C PH1C PH0C 0 0 0 0 W 0 0 0 Function 0 0: Input 1: Output Port H function register 1 PHFC1 (0xFF00_4448) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PH7F PH6F PH5F PH4F PH3F PH2F PH1F PH0F 0 0:PORT 1:INT1F 0 0:PORT 1:INT1E 0 0:PORT 1:INT1D 0 0:PORT 1:INT1A 0 0:PORT 1:INT19 0 0:PORT 1:INT18 7 6 5 4 3 2 1 0 PH7F2 PH6F2 PH5F2 PH4F2 PH3F2 PH2F2 PH1F2 PH0F2 0 0:PORT 1:TBAIN1 0 0:PORT 1:TBAIN0 0 0:PORT 1:TB9IN1 0 0:PORT 1:TB9IN0 3 2 1 0 PEH3 PEH2 PEH1 PEH0 R/W 0 0 0:PORT 0:PORT 1:INT1C 1:INT1B Port H function register 2 PHFC2 (0xFF00_444C) Bit Symbol Read/Write After reset Function R/W 0 0:PORT 1:TBDIN1 0 0:PORT 1:TBDIN0 0 0:PORT 1:TBBIN1 0 0:PORT 1:TBBIN0 Port H pull-up control register PHPUP Bit Symbol (0xFF00_446C) Read/Write After reset Function 7 6 5 4 PEH7 PEH6 PEH5 PEH4 R/W 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up 3 2 1 0 PIEH3 PIEH2 PIEH1 PIEH0 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled Port H input enable control register PHIE (0xFF00_4478) Bit Symbol Read/Write After reset Function Input/Output Ports 7 6 5 4 PIEH7 PIEH6 PIEH5 PIEH4 R/W 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled TMP19A44 (rev1.3) 7-73 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.19 Port I (PI0 through PI7) The port I is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PICR and the function register PIFC1. A reset allows all bits of the output latch PI to be set to "1," all bits of PICR to be cleared to "0," and the port I to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PIIE to "1". Besides the port function, the port I performs other functions: PI0 through PI3 input two-phase pulse, PI4 and PI7 input A/D triggers into the A/D converter., PI5 and PI6 output a 16-bit timer. PORT KEEP PIPUP Latch Drive disabled during STOP/ RESET (output control) Latch PICR (output control) RESET PIFC1 (function control) Latch (output latch) Port I PI0~PI3 (PHC4IN0,PHC4IN1, PHC5IN0,PHC5IN1) Latch Internal data bus PI PIIE (input control) 0 PI read 1 PHC4IN0,PHC4IN1, PHC5IN0,PHC5IN1 Fig. 7.52 Port I (PI0 through PI3) Input/Output Ports TMP19A44 (rev1.3) 7-74 2010-04-01 TMP19A44 PORT KEEP PIPUP (output control) h c t a L Drive disabled during STOP/ RESET h c t a L PICR (output control) RESET PIFC1 (function control) h c t a L (output latch) Port I PI4,PI7 (ADTRGC ADTRGSNC) h c t a L Internal data bus PI PIIE (input control) 0 PI read 1 ADTRGCADTRGSNC Fig. 7.53 Port I (PI4, PI7) Input/Output Ports TMP19A44 (rev1.3) 7-75 2010-04-01 TMP19A44 PORT KEEP PIPUP Latch Drive disabled during STOP/ RESET (output control) Latch PICR (output control) RESET PIFC1 (function control) Latch Internal data bus PI 1 TB10OUT, TB11OUT (output latch) 0 Port I PI5,PI6 (TB10OUT,TB11OUT) Latch PIIE (input control) 0 PI read 1 Fig. 7.54 Port I (PI5, PI6) Input/Output Ports TMP19A44 (rev1.3) 7-76 2010-04-01 TMP19A44 Port I register PI (0xFF00_4480) Bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 R/W Input mode (output latch register is set to "1.") Port I control register 7 6 5 4 3 2 1 0 PICR Bit Symbol PI7C PI6C PI5C PI4C PI3C PI2C PI1C PI0C (0xFF00_4484) Read/Write After reset Function 0 0 0 0 0 0 R/W 0 0 0: Input 1: Output Port I function register 1 PIFC1 (0xFF00_4488) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PI7F PI6F PI5F PI4F PI3F PI2F PI1F PI0F 0 0:PORT 1:PHC5IN 0 0 0:PORT 1:PHC4IN 1 0 0:PORT 1:PHC4IN 0 0 0:PORT 1:ADTRG SNC 0 0 0:PORT 0:PORT 1:TB11OU 1:TB10OU T T R/W 0 0 0:PORT 0:PORT 1:ADTRG 1:PHC5IN 1 C Port I pull-up control register PIPUP (0xFF00_44AC) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PEI7 PEI6 PEI5 PEI4 PEI3 PEI2 PEI1 PEI0 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up R/W Port I input enable control register PIIE Bit Symbol (0xFF00_44B8) Read/Write After reset Function Input/Output Ports 7 6 5 4 3 2 1 0 PIEI7 PIEI6 PIEI5 PIEI4 PIEI3 PIEI2 PIEI1 PIEI0 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled R/W 0 0 Input Input 0: 0: Disabled Disabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-77 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 7.20 Port J (PJ0 through PJ7) The port J is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits by using the control register PJCR and the function register PJFC1. A reset allows all bits of the output latch PJ to be set to "1," all bits of PJCR to be cleared to "0," and the port J to be put in input mode. Input is disabled right after reset. To enable input, set the corresponding bit of PJIE to "1". Besides the port function, the port J performs other functions: PJ0 and PJ1 input a 16-bit timer PJ2 through PJ7 input external interrupts. PORT KEEP PJPUP Latch Drive disabled during STOP/ RESET (output control) Latch PJCR (output control) RESET PJFC1 (function control) Latch Internal data bus PJ (output latch) Port J PJ0,PJ1 (TB11IN0,TB11IN1) Latch PJIE (input control) 0 1 PJ read TB11IN0,TB11IN1 Fig. 7.55 Port J (PJ0, PJ1) Input/Output Ports TMP19A44 (rev1.3) 7-78 2010-04-01 TMP19A44 PORT KEEP Latch PJPUP (output control) Latch PJCR (output control) RESET PJFC1 (function control) Latch Internal data bus PJ (output latch) Port J PJ2~PJ7 (INT14~INT17, INT6,INT7) Latch PJIE (input control) 0 PJ read 1 INT14~INT17,INT6,INT7 Fig. 7.56 Port J (PJ2 through PJ7) Input/Output Ports TMP19A44 (rev1.3) 7-79 2010-04-01 TMP19A44 Port J register PJ (0xFF00_44C0) Bit Symbol Read/Write After reset 7 6 5 4 3 2 1 0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 R/W Input mode (output latch register is set to "1.") Port J control register 7 6 5 4 3 2 1 0 PJCR Bit Symbol PJ7C PJ6C PJ5C PJ4C PJ3C PJ2C PJ1C PJ0C (0xFF00_44C4) Read/Write After reset Function 0 0 0 0 0 0 R/W 0 0 0: Input 1: Output Port J function register 1 PJFC1 (0xFF00_44C8) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F 0 0 0 0 0 0 0 0 0:PORT 1:INT7 0:PORT 1:INT6 0:PORT 1:INT17 0:PORT 1:INT16 0:PORT 1:INT15 0:PORT 1:INT14 0:PORT 1:TB11IN1 0:PORT 1:TB11IN 0 R/W Port J pull-up control register PJPUP (0xFF00_44EC) Bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 PEJ7 PEJ6 PEJ5 PEJ4 PEJ3 PEJ2 PEJ1 PEJ0 0 0 0 0 0 0 0 0 Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up Pull-up 0: Off 1: Pull-Up R/W Port J input enable control register PJIE Bit Symbol (0xFF00_44F8) Read/Write After reset Function Input/Output Ports 7 6 5 4 3 2 1 0 PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled 0 Input 0: Disabled 1: Enabled R/W 0 0 Input Input 0: 0: Disabled Disabled 1: Enabled 1: Enabled TMP19A44 (rev1.3) 7-80 0 Input 0: Disabled 1: Enabled 2010-04-01 TMP19A44 8. External Bus Interface The TMP19A44 has a built-in external bus interface function to connect to external memory, I/Os, etc. This interface consists of an external bus interface circuit (EBIF), a chip selector (CS) and a wait controller. The chip selector and wait controller designate mapping addresses in a 4-block address space and also control wait states and data bus widths (8- or 16-bit) in these and other external address spaces. The external bus interface circuit (EBIF) controls the timing of external buses based on the chip selector and wait controller settings. The EBIF also controls the dynamic bus sizing and the bus arbitration with the external bus master. z External bus mode Selectable address, data separator bus mode and multiplex mode z Wait function This function can be enabled for each block. * A wait of up to 15 clocks can be automatically inserted. * A wait can be inserted via the WAIT / RDY pin. z Data bus width Either an 8- or 16-bit width can be set for each block. z Recovery cycle (read/write) If an external bus cycle is in progress, a dummy cycle of up to 4 clocks can be inserted and this dummy cycle can be specified for each block. z Recovery cycle (chip selector) When an external bus is selected, a dummy cycle of up to 8 clocks can be inserted and this dummy cycle can be specified for each block. z Bus arbitration function External Bus Interface TMP19A44 (rev1.3) 8-1 2010-04-01 TMP19A44 8.1 Address and Data Pins (1) Address and data pin settings The TMP19A44 can be set to either separate bus or multiplexed bus mode. Setting the BUSMD pin (port P45) to the "L" level (DVSS) at a reset activates the separate bus mode, and setting the pin to the "H" level (DVCC3) activates the multiplexed bus mode. Port pins 0, 1, 2, 5 and 6, which are to be connected to external devices (memory), are used as address buses, data buses and address/data buses. Table 8.1 shows these. Table 8.1 Bus Mode, Address and Data Pins Port Port Port Port Port Port 0 (P00 to P07) 1 (P10 to P17) 2 (P20 to P27) 3 (P37) 5 (P50 to P57) 6 (P60 to P67) Separate BUSMD (P45) ="L" Multiplex BUSMD (P45) ="H" D0-D7 D8-D15 A16-A23 General-purpose port A0-A7 A8-A15 AD0-AD7 AD8-AD15/A8-A15 A0-A7/A16-A23 ALE General-purpose port General-purpose port Each port is put into input mode after a reset. To access an external device, set the address and data bus functions by using the port control register (PnCR) and the port function register (PnFCm), and set the input enable register (PnIE). External Bus Interface TMP19A44 (rev1.3) 8-2 2010-04-01 TMP19A44 8.2 Data Format Internal registers and external bus interfaces of the TMP19A44 are configured as described below. (1) Big-endian mode c Word access * 16-bit bus width Internal registers D31 AA BB CC D00 DD address x0 x1 x2 x3 AABB MSB LSB A1=0 CCDD A1=1 8-bit bus width Internal registers D31 AA BB CC D00 DD d External buses address x0 x1 x2 x3 External buses AA x0 BB x1 CC x2 DD x3 Half word access * 16-bit bus width Internal registers External buses address D31 AA x0 D00 BB x1 AABB MSB LSB address D31 CC x2 D00 DD x3 External Bus Interface CCDD MSB LSB TMP19A44 (rev1.3) 8-3 2010-04-01 TMP19A44 * 8-bit bus width Internal registers External buses address D31 AA x0 D00 BB x1 Internal registers AA x0 BB x1 External buses address D31 CC x2 D00 DD x3 e CC x2 DD x3 Byte access * 16-bit bus width Internal registers External buses address D31 AA MSB LSB D00 AA x0 address D31 BB MSB LSB D00 BB x1 address D31 CC MSB LSB D00 CC x2 address D31 DD MSB LSB D00 DD x3 External Bus Interface TMP19A44 (rev1.3) 8-4 2010-04-01 TMP19A44 8-bit bus width Internal registers External buses address D31 AA D00 AA x0 address D31 BB D00 BB x1 address D31 CC D00 CC x2 address D31 DD D00 DD x3 External Bus Interface TMP19A44 (rev1.3) 8-5 2010-04-01 TMP19A44 (2) Little-endian mode c Word access * 16-bit bus width Internal registers D31 DD CC BB D00 AA * address x3 x2 x1 x0 AABB CCDD LSB MSB A1=0 A1=1 8-bit bus width Internal registers D31 DD CC BB D00 AA d External buses address x3 x2 x1 x0 External buses AA BB CC DD x0 x1 x2 x3 Half word access * 16-bit bus width Internal registers External buses address D31 BB x1 D00 AA x0 AABB LSB MSB address D31 DD x3 D00 CC x2 External Bus Interface CCDD LSB MSB TMP19A44 (rev1.3) 8-6 2010-04-01 TMP19A44 * 8-bit bus width Internal registers External buses address D31 BB x1 D00 AA x0 Internal registers AA x0 BB x1 External buses address D31 DD x3 D00 CC x2 e CC x2 DD x3 Byte access * 16-bit bus width Internal registers External buses address D31 AA LSB MSB LSB BB MSB CC LSB MSB LSB DD MSB D00 AA x0 address D31 D00 BB x1 address D31 D00 CC x2 address D31 D00 DD x3 External Bus Interface TMP19A44 (rev1.3) 8-7 2010-04-01 TMP19A44 * 8-bit bus width Internal registers External buses address D31 AA D00 AA x0 address D31 BB D00 BB x1 address D31 CC D00 CC x2 address D31 DD D00 DD x3 External Bus Interface TMP19A44 (rev1.3) 8-8 2010-04-01 TMP19A44 8.3 External Bus Operations (Separate Bus Mode) This section describes various bus timing values. The timing diagram shown below assumes that the address buses are A23 through A0 and that the data buses are D15 through D0. (1) Basic bus operation The external bus cycle of the TMP19A44 basically consists of three clock pulses and a wait can be inserted as mentioned later. The basic clock of an external bus cycle is the same as the internal system clock. Fig. 8.1 shows read bus timing and Fig. 8.2 shows write bus timing. If internal areas are accessed, address buses remain unchanged as shown in these figures. Additionally, data buses are in a state of high impedance and control signals such as RD and WR do not become active. tsys CSn A [23:0] D [15:0] Address HOLD DATA Output High - Z No output of RD RD External access Internal access Fig. 8.1 Read Operation Timing Diagram tsys CSn A [23:0] D [15:0] Address HOLD DATA WR Output High - Z No output of WR External access Internal access Fig. 8.2 Write Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-9 2010-04-01 TMP19A44 (2) Wait timing A wait cycle can be inserted for each block by using the chip selector (CS) and wait controller. The following three types of wait can be inserted: c A wait of up to 15 clocks can be automatically inserted. d A wait can be inserted via the WAIT pin (from 2+2N through 15+2N). Note: 2N/4N is the number of external waits that can be inserted. e A wait can be inserted via the RDY pin (from 2+2N through 15+2N). Note: 2N/4N is the number of external waits that can be inserted. The setting of the number of waits to be automatically inserted and the setting of the external wait input can be made using the chip selector and wait controller registers, BmnCS<BnW>. Fig. 8.3 through Fig. 8.10 show the timing diagrams in which waits have been inserted. tsys address A[23:0] address data data D[15:0] RD 0 wait 1 wait Fig. 8.3 Read Operation Timing Diagram (0 Wait and 1 Wait Automatically Inserted) tsys A[23:0] address data D[15:0] RD 5 waits Fig. 8.4 Read Operation Timing Diagram (5 Waits Automatically Inserted) External Bus Interface TMP19A44 (rev1.3) 8-10 2010-04-01 TMP19A44 Fig. 8.5 shows the read operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the separate bus mode. tsys fsys 0 wait A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /RD /WAIT 3 waits automatically inserted + 2N (N=1) 2 waits automatically inserted 2N_WAIT A[23:0] D[15:0] /RD /WAIT 3 waits automatically inserted 2N_WAIT 2 waits automatically inserted + 2N (N=2) A[23:0] D[15:0] /RD /WAIT 2 waits automatically inserted 2N_WAIT z --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.5 Read Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-11 2010-04-01 TMP19A44 Fig. 8.6 shows the write operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the separate bus mode. tsys fsys 0 wait A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted + 2N (N=1) 2 waits automatically inserted A[23:0] D[15:0] /WR /WAIT 3 waits automatically inserted + 2N (N=1) 2 waits automatically inserted 2N_WAIT A[23:0] D[15:0] /WR /WAIT 3 waits automatically inserted 2N_WAIT 2 waits automatically inserted + 2N (N=2) A[23:0] D[15:0] /WR /WAIT 2 waits automatically inserted 2N_WAIT z --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.6 Write Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-12 2010-04-01 TMP19A44 By setting the bit 3<P33F> of port 3 function register P3FC to "1," the WAIT input pin (P33) can also serve as the RDY input pin. The RDY input is input to the external bus interface circuit as the logical reverse of the WAIT input. The number of waits is specified by the chip selector and wait controller register, BmnCS<BnW>. Fig. 8.7 shows the RDY inputs and the number of waits. tsys fsys 2 waits automatically inserted A[23:0] D[15:0] /RD /RDY 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:0] D[15:0] /RD /RDY 2 waits automatically inserted 2N_WAIT z --- External RDY sampling point External RDY sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.7 RDY Input and Wait Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-13 2010-04-01 TMP19A44 (3) Time that it takes before ALE is asserted When the external bus of the TMP19A44 is used as a multiplexed bus, the ALE width (assert time) can be specified by using the system control register BUSCR<ALESEL1:0> in the CG. In the case of a separate bus mode, ALE is not output, but the time from when an address is established to the assertion of the RD or WR signal is different depending on the BUSCR<ALESEL1:0>. During a reset, <ALESEL 1:0> = "1" is set and the RD or WR signal is asserted as a point of two system (internal) clocks after an address is established. If <ALESEL 1:0> is cleared to "0," the RD or WR signal is asserted at a point of one system (internal) clock after an address is established. This assert setting cannot be established for each block in an external area and the same setting is commonly used in an external address space. tsys A[23:0] address D[15:0] data address data RD <ALESEL>="0" <ALESEL>="1" Fig. 8.8 ALE Assert Ttiming in Separate Bus Mode External Bus Interface TMP19A44 (rev1.3) 8-14 2010-04-01 TMP19A44 (4) Recovery time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS<BnWCV> (write recovery cycle) and <BnRCV> (read recovery cycle). As for dummy cycle, none, one, two or four system clocks (internal) can be specified for each block. Fig. 8.9 shows the timing of recovery time insertion. tsys CS A[23:0] address next address RD WR No recovery cycle CS A[23:0] address next address RD WR 1 recovery cycle 2 recovery cycles Fig. 8.9 Timing of Recovery Time Insertion in Separate Bus Mode External Bus Interface TMP19A44 (rev1.3) 8-15 2010-04-01 TMP19A44 (5) Chip selector recovery time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS<BnCSCV>. As for the number of dummy cycles, none, one, two three, four, six and eight system clocks (internal) can be specified for each block. Fig. 8.10 shows the timing of recovery time insertion. tsys CS A[23:0] address next address RD WR No recovery cycle 1 recovery cycle Fig. 8.10 Timing of Chip Selector Recovery Time Insertion External Bus Interface TMP19A44 (rev1.3) 8-16 2010-04-01 TMP19A44 8.4 External Bus Operations (Multiplexed Bus Mode) This section describes various bus timing values. The timing diagram shown below assumes that the address buses are A23 through A16 and that the address/data buses are AD15 through AD0. (1) Basic bus operation The external bus cycle of the TMP19A44 basically consists of three clock pulses and a wait can be inserted as mentioned later. The basic clock of an external bus cycle is the same as the internal system clock. Fig. 8.11 shows read bus timing and Fig. 8.12 shows write bus timing. If internal areas are accessed, address buses remain unchanged and the ALE does not output latch pulse as shown in these figures. Additionally, address/data buses are in a state of high impedance and control signals such as RD and WR do not become active. tsys CSn A [23:16] Higher-order address HOLD AD [15:0] ADR DATA ALE Output Hi - Z No output of ALE No output of RD RD External access Internal access Fig. 8.11 Read Operation Timing Diagram tsys CSn A [23:16] AD [15:0] Higher-order address HOLD ADR DATA Output Hi - Z ALE No output of ALE WR No output of WR External area Internal area Fig. 8.12 Write Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-17 2010-04-01 TMP19A44 (2) Wait Timing A wait cycle can be inserted for each block by using the chip selector (CS) and wait controller. The following three types of wait can be inserted: c A wait of up to 15 clocks can be automatically inserted. d A wait can be inserted via the WAIT pin (from 2+2N through 15+2N). Note: 2N/4N is the number of external waits that can be inserted. e A wait can be inserted via the RDY pin (from 2+2N through 15+2N). Note: 2N/4N is the number of external waits that can be inserted. BmnCS<BnW>,BUSCR<WAITSMP> The setting of the number of waits to be automatically inserted and the setting of the external wait input can be made using the chip selector and wait controller registers, BmnCS<BnW>. External Bus Interface TMP19A44 (rev1.3) 8-18 2010-04-01 TMP19A44 Fig. 8.13 shows the read operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the multiplexed bus mode. tsys fsys 0 wait A[23:16] Higher-order address AD[15:0] Lower-order address Data ALE /RD /WAIT 2 waits automatically inserted A[23:16] Higher-order address AD[15:0] Data Lower-order address ALE /RD /WAIT 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:16] Higher-order address AD[15:0] Data Lower-order address ALE /RD /WAIT 2 waits automatically inserted 2N_WAIT 3 waits automatically inserted + 2N (N=1) A[23:16] Higher-order address AD[15:0] Data Lower-order address ALE /RD /WAIT 3 waits automatically inserted 2N_WAIT 2 waits automatically inserted + 2N (N=2) A[23:16] AD[15:0] Higher-order address Data Lower-order address ALE /RD /WAIT 2 waits automatically inserted 2N_WAIT z --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.13 Read Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-19 2010-04-01 TMP19A44 Fig. 8.14 shows the write operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the multiplexed bus mode. tsys fsys 0 wait A[23:16] Higher-order address AD[15:0] Data Lower-order address ALE /WR /WAIT 2 waits automatically inserted A[23:16] Higher-order address AD[15:0] Data Lower-order address ALE /WR /WAIT 2 waits automatically inserted 2 waits automatically inserted + 2N (N=1) A[23:16] Higher-order address AD[15:0] Data Lower-order address ALE /WR /WAIT 2 waits automatically inserted 2N_WAIT 3 waits automatically inserted + 2N (N=1) A[23:16] Higher-order address AD[15:0] Lower-order address Data ALE /WR /WAIT 2N_WAIT 2 waits automatically inserted 2 waits automatically inserted + 2N (N=2) A[23:16] AD[15:0] Higher-order address Lower-order address Data ALE /WR /WAIT 2 waits automatically inserted 2N_WAIT z --- External wait sampling point External wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2N_wait cycle is finished as shown above. The same applies to combinations of other numbers of waits. Fig. 8.14 Write Operation Timing Diagram External Bus Interface TMP19A44 (rev1.3) 8-20 2010-04-01 TMP19A44 (3) Time that it takes before ALE is asserted One of system clocks of 1 to 4 can be selected as the time that it takes before ALE is asserted. The setting bit is located in the system clock control register. The default is 2 clocks. This assert setting cannot be established for each block in an external area and the same setting is commonly used in an external address space. tsys ALE (ALESEL = 0) 1 clock AD [15:0] (ALESEL = 1) 2 clocks AD [15:0] Fig. 8.15 Time That It Takes Before ALE Is Asserted Fig. 8.16 shows the timing when the ALE is 1 clock or 2 clocks. When the ALE is 1 clock or 2 clocks tsys fsys A[23:16] AD[15:0] Higher-order address Lower-order address Data Higher-order address Data ALE /RD Fig. 8.16 Read Operation Timing Diagram (When the ALE is 1 Clock or 2 Clocks) External Bus Interface TMP19A44 (rev1.3) 8-21 2010-04-01 TMP19A44 (4) Read and Write Recovery Time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS<BnWCV> (write recovery cycle) and <BnRCV> (read recovery cycle). As for the number of dummy cycles, none, one, two or four system clocks (internal) can be specified for each block. Fig. 8.17 shows the timing of recovery time insertion. When read/write recovery is inserted (ALE width:1fsys) tsys fsys A[23:16] AD[15:0] Higher-order address Lower-order address Data Higher-order address Lower-order address Higher-order address Lower-order address Data Data ALE /CS /RD,/WR Dummy cycle Normal cycle 1 recovery cycle Dummy cycle 2 recovery cycles Fig. 8.17 Timing of Recovery Time Insertion External Bus Interface TMP19A44 (rev1.3) 8-22 2010-04-01 TMP19A44 (5) Chip selector recovery time If access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. The dummy cycle insertion setting can be made in the chip selector and wait controller registers, BmnCS<BnCSCV>. As for the number of dummy cycles, one system clock (internal) can be specified for each block. Fig. 8.18 shows the timing of recovery time insertion. When chip selector recovery is inserted (ALE width:1fsys) tsys fsys A[23:16] AD[15:0] Higher-order address Data Lower-order address Higher-order address Lower-order address Data ALE /CS /RD,/WR Dummy cycle Normal cycle Chip selector recovery cycle Fig. 8.18 Timing of Recovery Time Insertion External Bus Interface TMP19A44 (rev1.3) 8-23 2010-04-01 TMP19A44 8.5 Bus Arbitration The TMP19A44 can be connected to an external bus master. The arbitration of bus control authority with the external bus master is executed by using the two signals, BUSRQ and BUSAK . The external bus master can acquire control authority for TMP19A44 external buses only, and cannot acquire control authority for internal buses. (1) Accessible range of external bus master The external bus master can acquire control authority for TMP19A44 external buses only, and cannot acquire control authority for internal buses (G-BUS). Therefore, the external bus master cannot access the internal memories or the internal I/O. The arbitration of bus control authority for external buses is executed by the external bus interface circuit (EBIF), and this is independent of the CPU and the internal DMAC. Even when the external bus master holds the external bus control authority, the CPU and the internal DMAC can access the internal ROM, RAM and registers. On the other hand, if the CPU or the internal DMAC tries to access an external memory when the external bus master holds the external bus control authority, the CPU or the internal DMAC has to wait until the external bus master releases the bus. For this reason, if the BUSRQ remains active, the TMP19A44 can lock. (2) Acquisition of bus control authority The external bus master requests the TMP19A44 for bus control authority by asserting the BUSRQ signal. The TMP19A44 samples the BUSRQ signal at the break of external bus cycles on the internal buses (GBUS) and determines whether or not to give the bus control authority to the external bus master. When it gives the bus control authority to the external bus master, it asserts the BUSAK signal. At the same time, it makes address buses, data buses and bus control signals ( RD and WR ) in a state of high impedance. (The internal pull-up is enabled for the R/ W , HWR and CSx .) Depending on the relationship between the size of data to be loaded or stored and the external memory bus width, two or more bus cycles can occur in response to a single data transfer (bus sizing). In this case, the end of the last bus cycle is the break of external bus cycles. If access to external areas occurs consecutively on the TMP19A44, a dummy cycle can be inserted. Again, requests for buses are accepted at the break of external bus cycles on the internal buses (G-BUS). During a dummy cycle, the next external bus cycle is already started on the internal buses. Therefore, even if the BUSRQ signal is asserted during a dummy cycle, the bus is not released until the next external bus cycle is completed. Keep asserting the BUSRQ signal until the bus control authority is released. Fig. 8.19 shows the timing of acquiring bus control authority by the external bus master. External Bus Interface TMP19A44 (rev1.3) 8-24 2010-04-01 TMP19A44 c d e tsys Internal address External address TMP19A4 4 external access TMP19A44 ext ernal ac ces s TMP19A44 external access External bus master cycle TMP19A44 external access BU SRQ BU SAK c BUSRQ is at the "H" level. d The TMP19A44 recognizes that the BUSRQ is at the "L" level, and releases the bus at the end of the bus cycle. e When the bus is completed, the TMP19A44 asserts BUSAK . The external bus master recognizes that the BUSAK is at the "L" level, and acquires the bus control authority to start bus operations. Fig. 8.19 Bus Control Authority Acquisition Timing (3) Release of bus control authority The external bus master releases the bus control authority when it becomes unnecessary. If the external bus master no longer needs the bus control authority that it has held, it negates the BUSRQ signal and returns the bus control authority to the TMP19A44. Fig. 8.20 shows the timing of releasing unnecessary bus control authority. c de tsys Internal address External address TMP19A4 4 external access TMP19A44 exter nal access TMP19A44 external access External bus mas ter cy cle TMP19A44 exter na l access BUSRQ BUSAK c The external bus master has the bus control authority. d The external bus master deasserts the BUSRQ , as it no longer requires the bus control authority. e The TMP19A44 recognizes that the BUSRQ is at the "H" level, and deasserts the BUSAK . Fig. 8.20 Timing of Releasing Bus Control Authority External Bus Interface TMP19A44 (rev1.3) 8-25 2010-04-01 TMP19A44 9. The Chip Selector and Wait Controller The TMP19A44 can be connected to external devices (I/O devices, ROM and SRAM). 4-block address spaces (CS0 through CS3) can be established in the TMP19A44 and three parameters can be specified for each 4-block address and other address spaces: data bus width, the number of waits and the number of dummy cycles. CS0 through CS3 (also used as P40 through P43) are the output pins corresponding to spaces CS0 through CS3. These pins generate chip selector signals (for ROM and SRAM) to each space when the CPU designates an address in which spaces CS0 through CS3 are selected. For chip selector signals to be generated, however, the port 4 controller register (P4CR) and the port 4 function registers (P4FC1 and P4FC2) must be set appropriately. The specification of the spaces CS0 through CS3 is to be performed with a combination of base addresses (BAn, n=0 to 3) and mask addresses (MAn, n=0 to 3) using the base and mask address setting registers (BMA0 through BMA3). Meanwhile, master enable, data bus width, the number of waits and the number of dummy cycles for each address space are specified in the chip selector and wait controller registers (B01CS, B23CS). A bus wait request pin ( WAIT /RDY) is provided as an input pin to control the status of these settings. 9.1 Specifying Address Spaces Spaces CS0 through CS3 are specified using the base and mask address setting registers (BMA0 through BMA3). In each bus cycle, a comparison is made to see if each address on the bus is located in the space CS0 through CS3. If the result of a comparison is a match, it is considered that the designated CS space has been accessed and chip selector signals are output from pins CS0 through CS3 and the operations specified by the chip selector and wait controller registers (B01CS and B23CS) are executed. (Refer to "9.2 The Chip Selector and Wait Controller.") 9.1.1 Base and Mask Address Setting Registers Fig. 9.1 show base and mask address setting registers. For base addresses (BA0 through BA3), a start address in the space CS0 through CS3 is specified. In each bus cycle, the chip selector and wait controller compare values in their registers with addresses and those addresses with address bits masked by the mask address (MA0 through MA3) are not compared. The size of an address space is determined by the mask address setting. (1) Base addresses Base address BAn specifies the higher-order 16 bits (A31 through A16) of the start address. The lowerorder 16 bits (A15 to A0) of the start address are always set to "0." Therefore, the start address begins with 0x0000_0000H and increases in 64 kilobyte units. shows the relationship between the start address and the BAn value. (2) Mask addresses Mask address (MAn) specifies which address bit value is to be compared. The address on the bus that corresponds to the bit for which "0" is written on the address mask MAn is to be included in address comparison to determine if the address is in the area of the CS0 to CS3 spaces. The bit for which "1" is written is not included in address comparison. CS0 to CS3 spaces have different address bits that can be masked by MA0 to MA3. CS0 space and CS1 space: A29 through A14 CS2 space and CS3 space: A30 through A15 (Note 1) Address settings must be made using physical addresses. (Note 2) CS areas must not be set in the internal area (0xFF00_0000~0xFFFF_FFFF). The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-1 2010-04-01 TMP19A44 Base and mask address setting registers BMA0 (0xFFFF_E400) to BMA3 (0xFFFF_E40C) 7 BMA0 (0xFF00_1400) Bit symbol Read/Write After reset Function 1 0 23 Bit symbol Read/Write After reset Function 0 31 Bit symbol Read/Write After reset Function 0 7 BMA1 (0xFF00_1404) Bit symbol Read/Write After reset Function 1 0 23 Bit symbol Read/Write After reset Function 0 31 Bit symbol Read/Write After reset Function (Note) 4 3 2 1 0 1 1 1 1 1 1 1 CS0 space size setting 0: Address for comparison 14 13 12 11 10 9 8 MA0 R/W 0 0 0 0 0 1 1 Make sure that you write "0." CS0 space size setting 0: Address for comparison 22 21 20 19 18 17 16 BA0 R/W 0 0 0 0 0 0 0 A23 to A16 to be set as a start address 30 29 28 27 26 25 24 BA0 R/W 0 0 0 0 0 0 0 A31 to A24 to be set as a start address 6 5 4 3 2 1 0 MA1 R/W 15 Bit symbol Read/Write After reset Function 5 MA0 R/W 15 Bit symbol Read/Write After reset Function 6 0 1 1 1 1 1 1 1 CS1 space size setting 0: Address for comparison 14 13 12 11 10 9 8 MA1 R/W 0 0 0 0 0 1 1 Make sure that you write "0." CS1 space size setting 0: Address for comparison 22 21 20 19 18 17 16 BA1 R/W 0 0 0 0 0 0 0 A23 to A16 to be set as a start address 30 29 28 27 26 25 24 BA1 R/W 0 0 0 0 0 0 0 A31 to A24 to be set as a start address Make sure that you write "0" for bits 10 through 15 for BMA0 and BMA1. The size of both the CS0 and CS1 spaces can be a minimum of 16 KB to a maximum of 1 GB. The external address space of the TMP19A44 is 16 MB and so bits 10 through 15 must be set to "0" as addresses A24 through A29 are not masked. Fig. 9.1 Base and Mask Address Setting Registers (BMA0, BMA1) The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-2 2010-04-01 TMP19A44 7 BMA2 (0xFF00_1408) Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function BMA3 (0xFF00_140C) Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function (Note) 6 5 4 3 2 1 0 1 1 9 8 1 1 17 16 0 0 25 24 0 0 1 0 1 1 9 8 1 1 17 16 0 0 25 24 0 0 MA2 R/W 1 1 15 14 0 0 23 22 0 0 31 30 0 0 7 6 1 1 1 1 CS0 space size setting 0: Address for comparison 13 12 11 10 MA2 R/W 0 0 0 0 Make sure that you write "0." 21 20 19 18 BA2 R/W 0 0 0 0 A23 to A16 to be set as a start address 29 28 27 26 BA2 R/W 0 0 0 0 A31 to A24 to be set as a start address 5 4 3 2 MA3 R/W 1 1 15 14 0 0 23 22 0 0 31 30 0 0 1 1 1 1 CS1 space size setting 0: Address for comparison 13 12 11 10 MA3 R/W 0 0 0 0 Make sure that you write "0." 21 20 19 18 BA3 R/W 0 0 0 0 A23 to A16 to be set as a start address 29 28 27 26 BA3 R/W 0 0 0 0 A31 to A24 to be set as a start address Make sure that you write "0" for bits 9 through 15 for BMA2 and BMA3. The size of both the CS2 and CS3 spaces can be a minimum of 32 KB to a maximum of 2 GB. The external address space of the TMP19A44 is 16 MB and so bits 9 through 15 must be set to "0" as addresses A24 through A30 are not masked. Fig. 9.2 Base and Mask Address Setting Registers (BMA2, BMA3) The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-3 2010-04-01 TMP19A44 Address Start address 0xFFFF_FFFF Base address value (BAn) 0xFFFF_0000 FFFFH 0x0006_0000 0006H 0x0005_0000 0005H 0x0004_0000 0004H 0x0003_0000 0003H 0x0002_0000 0002H 0x0001_0000 0001H 0x0000_0000 0000H 64 KB 0x0000_0000 Fig. 9.3 Start and Base Address Register Values 9.1.2 How to Define Start Addresses and Address Spaces * To specify a space of 64 KB starting at 0xC000_0000 in the CS0 space, the base and mask address registers must be programmed as shown below. 31 16 15 0 BA0 MA0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 0 0 3 Values to be set in the base and mask address registers (BMA0) In the base address (BA0), specify "0xC000" that corresponds to higher 16 bits of a start address, while in the mask address (MA0), specify whether a comparison of addresses in the space A29 through A14 is to be made or not. A comparison of A31 and A30 will definitely be made and to ensure a comparison of A29 through A24, set bits 15 to 10 of the mask address (MA0) to "0." This setting allows A31 through A16 to be compared with the value specified as a start address. Therefore, a space of 64 KB from 0xC000_0000 to 0xC000_FFFF is designated as a CS0 space and the CS0 signal is asserted if there is a match with an address on the bus. The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-4 2010-04-01 TMP19A44 To specify a space of 1 MB starting at 0x1FD0_0000 in the CS2 space, the base and mask address registers must be programmed as shown below. 31 16 15 0 BA2 MA2 0 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 F D 0 0 0 1 F Values to be set in the base and mask address registers (BMA2) In the base address (BA2), specify "0x1FD0" that corresponds to higher 16 bits of a start address, while in the mask address (MA2), specify whether a comparison of addresses in the space A30 through A15 is to be made or not. A comparison of A31 will definitely be made and to ensure a comparison of A30 through A20, set bits 15 to 5 of the mask address (MA2) to "0." This setting allows A31 through A20 to be compared with the value specified as a start address. As A19 through A0 are masked, a space of 1 MB from 0x1FD0_0000 to 0x1FDF_FFFF is designated as a CS2 space. After a reset, the CS0 through CS3 spaces are disabled, while the whole CS2 space (4 GB) is enabled as an address space. The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-5 2010-04-01 TMP19A44 Table 9.1 shows the relationship between CS space and space sizes. If two or more address spaces are specified simultaneously, a space or spaces with a smaller space number will be given priority in space selection. Example: 0xC000_0000 as a start address of the CS0 space with a space size of 16 KB 0xC000_0000 as a start address of the CS1 space with a space size of 64 KB CS1 space CS0 space 0xC000_FFFF 0xC000_3F 0xC000_3F 0xC000_00 0xC000_00 If a space of 0xC000_0000 to 0xC000_3FFF is accessed, the CS0 space is selected. Table 9.1 CS Space and Space Sizes Size (bytes) CS space CS0 CS1 CS2 CS3 16 K 32 K 64 K { { { { { { { { { { 128 K 256 K 512 K { { { { { { { { { { { { 1M 2M 4M 8M 16 M { { { { { { { { { { { { { { { { { { { { The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-6 2010-04-01 TMP19A44 9.2 The Chip Selector and Wait Controller The chip selector and wait controller registers are shown from the next page. For each address space (spaces CS0 through CS3 and other address spaces), each chip selector and wait controller register (B01CS through B23CS) can be programmed to set master enable or disable, to select data bus width, to specify the number of waits and to insert dummy cycles. If two or more address spaces are specified simultaneously, a space or spaces with a smaller space number will be given priority in space selection (order of priority: CS0>CS1>CS2>CS3>EXCS). The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-7 2010-04-01 TMP19A44 7 B01CS bit Symbol R (0xFF00_1480) Read/Write After reset 0 "0" is Function 6 5 R/W 0 B0BUS R/W 1 read. Write "0". 15 14 Select data bus width 0: 8bit 1: 16bit 13 4 0 3 2 1 0 0 B0W R/W 0 0 1 Specify the number of waits. (automatic WAIT insertion) 0_0000:0WAIT 0_0100:4WAIT 0_1000:8WAIT 0_1100:12WAIT 0_0001:1WAIT 0_0101:5WAIT 0_1001:9WAIT 0_1101:13WAIT 0_0010:2WAIT 0_0110:6WAIT 0_1010:10WAIT 0_1110:14WAIT 0_0011:3WAIT 0_0111:7WAIT 0_1011:11WAIT 0_1111:15WAIT (External wait input) x=2,4 1_0010: (2+ xN) WAIT 1_1001: ( 9+ xN) WAIT 1_0011: (3+ xN) WAIT 1_1010: (10+ xN) WAIT 1_0100: (4+ xN) WAIT 1_1011: (11+ xN) WAIT 1_0101: (5+ xN) WAIT 1_1100: (12+ xN) WAIT 1_0110: (6+ xN) WAIT 1_1101: (13+ xN) WAIT 1_0111: (7+ xN) WAIT 1_1110: (14+ xN) WAIT 1_1000: (8+ xN) WAIT 1_1111: (15+ xN) WAIT 12 11 bit Symbol B0CSCV B0WCV R/W R/W Read/Write After reset 0 0 0 1 0 Specify the number of Specify the number of dummy Function cycles to be inserted. (CS0 recovery time) 000: Setting prohibited 001: 1 cycle 010~ 111: Setting prohibited 23 bit Symbol R Read/Write After reset 0 "0" is Function 22 21 R/W 0 B1BUS R/W 1 Write read "0". . 31 bit Symbol Read/Write After reset Function 0 Select data bus width. 0: 8bit 1: 16bit 30 29 dummy cycles to be inserted. (write, recovery time) 00: Setting prohibited 01: 1 cycle 1x: Setting prohibited 20 0 28 B1WCV R/W 0 8 0 B0E R/W 0 B0RCV R/W 1 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: Setting prohibited 01: 1 cycle 1x: Setting prohibited Enable or disable CS0. 0: Disable 1: Enable 19 18 17 16 0 B1W R/W 0 0 1 27 R/W 0 9 Specify the number of waits. (automatic WAIT insertion) 0_0000:0WAIT 0_0100:4WAIT 0_1000:8WAIT 0_1100:12WAIT 0_0001:1WAIT 0_0101:5WAIT 0_1001:9WAIT 0_1101:13WAIT 0_0010:2WAIT 0_0110:6WAIT 0_1010:10WAIT 0_1110:14WAIT 0_0011:3WAIT 0_0111:7WAIT 0_1011:11WAIT 0_1111:15WAIT (external WAIT input) x=2,4 1_0010: (2+xN) WAIT 1_1001: (9+xN) WAIT 1_0011: (3+xN) WAIT 1_1010: (10+xN) WAIT 1_0100: (4+xN) WAIT 1_1011: (11+xN) WAIT 1_0101: (5+xN) WAIT 1_1100: (12+xN) WAIT 1_0110: (6+xN) WAIT 1_1101: (13+xN) WAIT 1_0111: (7+xN) WAIT 1_1110: (14+xN) WAIT 1_1000: (8+xN) WAIT 1_1111: (15+xN) WAIT B1CSCV Specify the number of dummy cycles to be inserted. (CS1 recovery time) 000: Setting prohibited 100: 4 cycles 001: 1 cycle 101: 6 cycles 010: 2 cycles 110: 8 cycles 011: 3 cycles 111: Setting prohibited 10 1 26 25 24 0 B1E R/W 0 B1RCV R/W 0 Specify the number of dummy cycles to be inserted. (write, recovery time) 00: Setting prohibited 01: 1 cycle 10: 2 cycles 11: 4 cycles 1 Specify the number of dummy cycles to be inserted. 00: Setting prohibited 01: 1 cycle 10: 2 cycles 11: 4 cycles Enable or disable CS1 0: Disable 1: Enable Fig. 9.4 Chip Selector and Wait Controller Registers 0, 1 The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-8 2010-04-01 TMP19A44 7 6 R R/W 0 "0" is read. 0 Write "0". bit Symbol B23CS (0xFF00_1484) Read/Write After reset Function 5 4 3 B2BUS 23 bit Symbol R Read/Write After reset 0 "0" is read. Function 22 R/W 0 Write "0". 21 B3BUS R/W 1 Select data bus width 0: 8bit 1: 16bit R/W dummy cycles to be inserted. (write, recovery time) 00: Setting prohibited 01: 1 cycle 10: 2 cycles 11: 4 cycles 20 19 0 0 10 9 B2RCV R/W 1 0 1 8 B2E R/W 0 Enable or Specify the number of disable dummy cycles to be CS2 inserted. (read, recovery time) 0: Disable 1: Enable 00: Setting prohibited 01: 1 cycle 10: 2 cycles 11: 4 cycles 18 B3W R/W 0 17 16 0 1 Specify the number of waits. (automatic WAIT insertion) 0_0000:0WAIT 0_0100:4WAIT 0_1000:8WAIT 0_1100:12WAIT 0_0001:1WAIT 0_0101:5WAIT 0_1001:9WAIT 0_1101:13WAIT 0_0010:2WAIT 0_0110:6WAIT 0_1010:10WAIT 0_1110:14WAIT 0_0011:3WAIT 0_0111:7WAIT 0_1011:11WAIT 0_1111:15WAIT (External wait input) x=2,4 1_0010: (2+ xN) WAIT 1_1001: ( 9+ xN) WAIT 1_0011: (3+ xN) WAIT 1_1010: (10+ xN) WAIT 1_0100: (4+ xN) WAIT 1_1011: (11+ xN) WAIT 1_0101: (5+ xN) WAIT 1_1100: (12+ xN) WAIT 1_0110: (6+ xN) WAIT 1_1101: (13+ xN) WAIT 1_0111: (7+ xN) WAIT 1_1110: (14+ xN) WAIT 1_1000: (8+ xN) WAIT 1_1111: (15+ xN) WAIT 31 30 29 28 27 bit Symbol B3CSCV B3WCV R/W R/W Read/Write After reset 0 0 0 1 0 Specify the number of dummy cycles Specify the number of Function to be inserted. (CS3 recovery time) 000: Setting prohibited 100: 4 cycles 001: 1 cycle 101: 6 cycles 010: 2 cycles 110: 8 cycles 011: 3 cycles 111: Setting prohibited 0 0 0 0 0 Specify the number of waits. (automatic WAIT insertion) 0_0000:0WAIT 0_0100:4WAIT 0_1000:8WAIT 0_1100:12WAIT 0_0001:1WAIT 0_0101:5WAIT 0_1001:9WAIT 0_1101:13WAIT 0_0010:2WAIT 0_0110:6WAIT 0_1010:10WAIT 0_1110:14WAIT 0_0011:3WAIT 0_0111:7WAIT 0_1011:11WAIT 0_1111:15WAIT (External wait input) x=2,4 1_0010: (2+xN) WAIT 1_1001: ( 9+ xN) WAIT 1_0011: (3+ xN) WAIT 1_1010: (10+ xN) WAIT 1_0100: (4+ xN) WAIT 1_1011: (11+ xN) WAIT 1_0101: (5+ xN) WAIT 1_1100: (12+ xN) WAIT 1_0110: (6+ xN) WAIT 1_1101: (13+ xN) WAIT 1_0111: (7+ xN) WAIT 1_1110: (14+ xN) WAIT 1_1000: (8+ xN) WAIT 1_1111: (15+ xN) WAIT 15 14 13 12 11 bit Symbol B2CSCV B2WCV R/W R/W Read/Write After reset 0 0 0 1 0 Specify the number of dummy cycles Specify the number of Function to be inserted. (CS2 recovery time) 000: Setting prohibited 100: 4 cycles 001: 1 cycle 101: 6 cycles 010: 2 cycles 110: 8 cycles 011: 3 cycles 111: Setting prohibited 1 B2W R/W 1 Select data bus width 0: 8bit 1: 16bit 2 dummy cycles to be inserted. (write, recovery time) 00: Setting prohibited 01: 1 cycle 10: 2 cycles 11: 4 cycles 26 25 B3RCV R/W 1 0 Specify the number of dummy cycles to be inserted. (read, recovery time) 00: Setting prohibited 01: 1 cycle 10: 2 cycles 11: 4 cycles 24 B3E R/W 0 Enable or disable CS3. 0: Disable 1: Enable Fig. 9.5 Chip Selector and Wait Controller Registers 2, 3 The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-9 2010-04-01 TMP19A44 9.3 Bus Control Register Fig. 9.6 shows the bus control register BUSCR that is capable of setting ALE width and the number of WAIT sampling. 7 BUSCR bit Symbol (0xFF00_14C0) Read/Write After reset 0 Function "0" is read. 6 0 5 R 0 4 3 0 0 2 WAITSMP R/W 0 Specify the number of waits to be sampled 0: 2N 1: 4N 15 14 13 12 0 0 0 23 22 0 31 bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 11 1 0 ALESEL R/W 0 1 Multiplex bus 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles Separate bus 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 10 9 8 R 0 0 "0" is read. 0 0 0 21 20 18 17 16 0 0 R 0 0 "0" is read. 0 0 0 30 29 28 26 25 24 0 0 0 19 27 R 0 0 0 0 0 "0" is read. Fig. 9.6 Bus Control Register <ALESEL1:0>: Setting for ALE width cycle differs depending on a bus to be used: separate bus or multiplex bus. <WAITSMP>: Sampling point of WAIT input can be changed according to operating frequency. Recommended value 2N: fsys = 4MHz~40MHz 4N: fsys = 40MHz~80MHz The Chip Selector and Wait Controller TMP19A44 (rev1.3) 9-10 2010-04-01 TMP19A44 10. DMA Controller (DMAC) The TMP19A44 has a built-in 8-channel DMA Controller (DMAC). 10.1 Features The DMAC of the TMP19A44 has the following features: (1) DMA with 8 independent channels (eight interrupt factors, INTDMA0 through INTDMA7) (2) Two types of requests for bus control authority: With and without snoop requests (3) Transfer requests: Internal requests (software initiated)/external requests (external interrupts, interrupt requests given by internal peripheral I/Os, and requests given by the DREQ pin) Requests given by the DREQ pin: Level mode (4) Transfer mode: Dual address mode (5) Transfer devices: Memory space transfer (6) Device size: 32-bit memory (8 or 16 bits can be specified using the CS/WAIT controller); I/O of 8, 16 or 32 bits (7) Address changes: Increase, decrease, fixed, irregular increase, irregular decrease (8) Channel priority: Fixed (in ascending order of channel numbers) (9) Endian switchover function DMA Controller (DMAC) TMP19A44 (rev1.3) 10-1 2010-04-01 TMP19A44 10.2 Configuration 10.2.1 Internal Connections of the TMP19A44 Fig. 10.1 shows the internal connections with the DMAC in the TMP19A44. DREQ [4,0] DACK [4,0] Port function control DACK [7 : 0]* Interrupt controller INTDREQ [7 : 0]* TX19A processor core (external request) Notification to release bus control authority DMAC BUSGNT External interrupt request Internal I/O interrupt request * BUSREQ * Request for bus control authority Request to release bus control authority Notification of bus control authority ownership Control Address BUSREL * HAVEIT * Data (Note) In Fig. 10.1, signals indicated by * are internal signals. Fig. 10.1 DMAC Connections in the TMP19A44 The DMAC has eight DMA channels. Each of these channels handles the data transfer request signal (INTDREOn) from the interrupt controller and the acknowledgment signal (DACKn) generated in response to INTDREOn, where "n" is a channel number from 0 to 7. External pins (DREQ0 and DREQ4) are internally wired to allow them to function as pins of the port F. To use them as pins of the port F, they must be selected by setting the function control register PFFC to an appropriate setting. Pins, DACK0 and DACK4, handle the data transfer request and acknowledge signal output supplied through external pins, DREQ0 and DREQ4. Channel 0 is given higher priority than channel 1, channel 1 higher priority than channel 2 and channel 2 higher priority than channel 3. Subsequent channels are given priority in the same manner. The TX19A/ H1 processor core has a snoop function. Using the snoop function, the TX19A/ H1 processor core opens the core's data bus to the DMAC, thus allowing the DMAC to access the internal ROM and RAM linked to the core. The DMAC is capable of determining whether or not to use this snoop function. For further information on the snoop function, refer to 10.2.3 "Snoop Function." Two types of bus control authority (SREQ and GREQ) are available to the DMAC and which type of control right to use depends on the use or nonuse of the snoop function. GREQ is a request for bus control authority if the DMAC does not use the snoop function, while SREQ is a request for bus control authority if the DMAC uses the snoop function. SREQ is given higher priority than GREQ. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-2 2010-04-01 TMP19A44 10.2.2 DMAC Internal Blocks Fig. 10.2 shows the internal blocks of the DMAC. Channel 3 Channel 2 Channel 1 Channel 0 0 31 Source address register (SARx) Destination address register (DARx) Byte count register (BSRx) Channel control register (CCRx) Channel status register (CSRx) DMA transfer control register (DTCRx) (x0~3) DMA control register (DCR) Request select register (RSR) Data holding register (DHR) Fig. 10.2 DMAC Internal Blocks 10.2.3 Snoop Function The TX19A/ H1 processor core has a snoop function. If the snoop function is activated, the TX19A/ H1 processor core opens the core's data bus to the DMAC and suspends its own operation until the DMAC withdraws a request for bus control authority. If the snoop function is enabled, the DMAC can access the internal RAM and ROM and therefore designate the RAM or ROM as a source or destination. If the snoop function is not used, the DMAC cannot access the internal RAM or ROM. However, the GBus is opened to the DMAC. If the TX19A/ H1 processor core attempts to access memory space 1by way of the G-Bus and if the DMAC does not accept a bus control release request, bus operations cannot be executed and, as a result, the pipeline stalls. (Note) If the snoop function is not used, the TX19A/ H1 processor core does not open the data bus to the DMAC. If the data bus is closed and the internal RAM or ROM is designated as a DMAC source or destination, an acknowledgment signal will not be returned in response to a DMAC transfer bus cycle and, as a result, the bus will lock. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-3 2010-04-01 TMP19A44 10.3 Registers The DMAC has fifty-one 32-bit registers. Table 10.1 shows the register map of the DMAC. Table 10.1 DMAC Registers (1 of 2) Address 0xFF00_1200 0xFF00_1204 0xFF00_1208 0xFF00_120C 0xFF00_1210 0xFF00_1218 0xFF00_1220 0xFF00_1224 0xFF00_1228 0xFF00_122C 0xFF00_1230 0xFF00_1238 0xFF00_1240 0xFF00_1244 0xFF00_1248 0xFF00_124C 0xFF00_1250 0xFF00_1258 0xFF00_1260 0xFF00_1264 0xFF00_1268 0xFF00_126C 0xFF00_1270 0xFF00_1278 0xFF00_1280 0xFF00_1284 0xFF00_1288 0xFF00_128C 0xFF00_1290 0xFF00_1298 0xFF00_12A0 0xFF00_12A4 0xFF00_12A8 0xFF00_12AC 0xFF00_12B0 0xFF00_12B8 0xFF00_12C0 0xFF00_12C4 0xFF00_12C8 0xFF00_12CC 0xFF00_12D0 0xFF00_12D8 DMA Controller (DMAC) Register symbol CCR0 CSR0 SAR0 DAR0 BCR0 DTCR0 CCR1 CSR1 SAR1 DAR1 BCR1 DTCR1 CCR2 CSR2 SAR2 DAR2 BCR2 DTCR2 CCR3 CSR3 SAR3 DAR3 BCR3 DTCR3 CCR4 CSR4 SAR4 DAR4 BCR4 DTCR4 CCR5 CSR5 SAR5 DAR5 BCR5 DTCR5 CCR6 CSR6 SAR6 DAR6 BCR6 DTCR6 Register name Channel control register (ch. 0) Channel status register (ch. 0) Source address register (ch. 0) Destination address register (ch. 0) Byte count register (ch. 0) DMA transfer control register (ch. 0) Channel control register (ch. 1) Channel status register (ch. 1) Source address register (ch. 1) Destination address register (ch. 1) Byte count register (ch. 1) DMA transfer control register (ch. 1) Channel control register (ch. 2) Channel status register (ch. 2) Source address register (ch. 2) Destination address register (ch. 2) Byte count register (ch. 2) DMA transfer control register (ch. 2) Channel control register (ch. 3) Channel status register (ch. 3) Source address register (ch. 3) Destination address register (ch. 3) Byte count register (ch. 3) DMA transfer control register (ch. 3) Channel control register (ch. 4) Channel status register (ch. 4) Source address register (ch. 4) Destination address register (ch. 4) Byte count register (ch. 4) DMA transfer control register (ch. 4) Channel control register (ch. 5) Channel status register (ch. 5) Source address register (ch. 5) Destination address register (ch. 5) Byte count register (ch. 5) DMA transfer control register (ch. 5) Channel control register (ch. 6) Channel status register (ch. 6) Source address register (ch. 6) Destination address register (ch. 6) Byte count register (ch. 6) DMA transfer control register (ch. 6) TMP19A44 (rev1.3) 10-4 2010-04-01 TMP19A44 Table 10.2 DMAC Registers (2 of 2) 0xFF00_12E0 0xFF00_12E 0xFF00_12E8 0xFF00_12EC 0xFF00_12F0 0xFF00_12F8 0xFF00_1300 0xFF00_1304 0xFF00_130C DMA Controller (DMAC) CCR7 CSR7 SAR7 DAR7 BCR7 DTCR7 DCR RSR DHR Channel control register (ch. 7) Channel status register (ch. 7) Source address register (ch. 7) Destination address register (ch. 7) Byte count register (ch. 7) DMA transfer control register (ch. 7) DMA control register (DMAC) Request select register (DMAC) Data holding register (DMAC) TMP19A44 (rev1.3) 10-5 2010-04-01 TMP19A44 10.3.1 DCR (0xFF00_1300) DMA Control Register (DCR) bit Symbol Read/Write After reset Function 7 6 5 4 Rst7 Rst6 Rst5 Rst4 15 14 13 3 2 1 0 Rst2 Rst1 Rst0 11 10 9 8 19 18 17 16 27 26 25 24 Rst3 W 0 See detailed description. 12 bit Symbol Read/Write After reset Function W 0 23 22 21 20 bit Symbol Read/Write After reset Function W 0 31 bit Symbol Read/Write After reset Function 30 29 28 Rstall W 0 See detailed description. Bit Mnemonic 31 Rstall Reset all Performs a software reset of the DMAC. If the Rstall bit is set to 1, the values of all the internal registers of the DMAC are reset to their initial values. All transfer requests are canceled and all eight channels go into an idle state. 0: Don't care 1: Initializes the DMAC 7 Rst7 Reset 7 Performs a software reset of the DMAC channel 7. If the Rst7 bit is set to 1, internal registers of the DMAC channel 7 and a corresponding bit of the channel 7 of the RSR register are reset to their initial values. The transfer request of the channel 7 is canceled and the channel 7 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 7 6 Rst6 Reset 6 Performs a software reset of the DMAC channel 6. If the Rst6 bit is set to 1, internal registers of the DMAC channel 6 and a corresponding bit of the channel 6 of the RSR register are reset to their initial values. The transfer request of the channel 6 is canceled and the channel 6 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 6 5 Rst5 Reset 5 Performs a software reset of the DMAC channel 5. If the Rst5 bit is set to 1, internal registers of the DMAC channel 5 and a corresponding bit of the channel 5 of the RSR register are reset to their initial values. The transfer request of the channel 5 is canceled and the channel 5 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 5 DMA Controller (DMAC) Field name Description TMP19A44 (rev1.3) 10-6 2010-04-01 TMP19A44 Bit Mnemonic Field name Description 4 Rst4 Reset 4 Performs a software reset of the DMAC channel 4. If the Rst4 bit is set to 1, internal registers of the DMAC channel 4 and a corresponding bit of the channel 4 of the RSR register are reset to their initial values. The transfer request of the channel 4 is canceled and the channel 4 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 4 3 Rst3 Reset 3 Performs a software reset of the DMAC channel 3. If the Rst3 bit is set to 1, internal registers of the DMAC channel 3 and a corresponding bit of the channel 3 of the RSR register are reset to their initial values. The transfer request of the channel 3 is canceled and the channel 3 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 3 2 Rst2 Reset 2 Performs a software reset of the DMAC channel 2. If the Rst2 bit is set to 1, internal registers of the DMAC channel 2 and a corresponding bit of the channel 2 of the RSR register are reset to their initial values. The transfer request of the channel 2 is canceled and the channel 2 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 2 1 Rst1 Reset 1 Performs a software reset of the DMAC channel 1. If the Rst1 bit is set to 1, internal registers of the DMAC channel 1 and a corresponding bit of the channel 1 of the RSR register are reset to their initial values. The transfer request of the channel 1 is canceled and the channel 1 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 1 0 Rst0 Reset 0 Performs a software reset of the DMAC channel 0. If the Rst0 bit is set to 1, internal registers of the DMAC channel 0 and a corresponding bit of the channel 0 of the RSR register are reset to their initial values. The transfer request of the channel 0 is canceled and the channel 0 goes into an idle state. 0: Don't care 1: Initializes the DMAC channel 0 Fig. 10.3 DMA Control Register (DCR) When software is reset, the CCRn,CSRn,SARn,DARn,DTCRn,DCR,RSR register is initialized. The BCRn,DHR register is not initialized. (Note 1) If a write to the DCR register occurs during a software reset right after the last round of DMA transfer is completed, the interrupt to stop DMA transfer is not canceled although the channel register is initialized. (Note 2) An attempt to execute a write (software reset) to the DCR register by DMA transfer must be strictly avoided. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-7 2010-04-01 TMP19A44 10.3.2 Channel Control Registers (CCRn) 7 CCRn bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 5 4 DAC R/W 3 2 1 TrSiz R/W 0 See detailed description. 0 DPS R/W 15 14 13 12 11 10 9 8 R/W ExR R/W PosE R/W Lev R/W SReq R/W RelEn R/W SIO R/W SAC R/W 18 17 16 R/W Big R/W 1 R/W 0 0 See detailed description. Always set this bit to "0." 23 22 NIEn R/W AblEn R/W 1 21 R/W See detailed description. 31 bit Symbol Read/Write After reset Function 6 SAC DIO R/W R/W 0 0 Always set See this bit to detailed "0." description . 30 29 20 19 R/W R/W 0 Always set this bit to "0." 28 27 Str W See detailed Always description. set this bit to "0." 26 25 24 W 0 See detailed description. Always set this bit to "0." Fig. 10.4 Channel Control Registers (CCRn) (1 of 2) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-8 2010-04-01 TMP19A44 Bit Mnemonic 31 Str Field name 24 NIEn (Reserved) 23 22 AbIEn Abnormal completion interrupt enable 21 (Reserved) Normal Completion Interrupt Enable (initial value: 1) 1: Normal completion interrupt enable 0: Normal completion interrupt disable Abnormal Completion Interrupt Enable (initial value: 1) 1: Abnormal completion interrupt enable 0: Abnormal completion interrupt disable This is a reserved bit. Although it's initial value is "1," always set this bit to "0." 20 (Reserved) This is a reserved bit. Always set this bit to "0." 19 (Reserved) This is a reserved bit. Always set this bit to "0." 18 Big (Reserved) This is a reserved bit. Always set this bit to "0." 17 Big-endian 16 (Reserved) Big Endian (initial value: 1) 1: A channel operates by big-endian 0: A channel operates by little-endian This is a reserved bit. Always set this bit to "0." 15 ExR (Reserved) This is a reserved bit. Always set this bit to "0." 14 External request mode 13 PosE Positive edge External Request Mode (initial value: 0) Selects a transfer request mode. (only for 0ch and 4ch) 1: External transfer request (interrupt request or external DREQn request) 0: Internal transfer request (software initiated) Positive Edge (initial value: 0) The effective level of the transfer request signal INTDREQn or DREQn is specified. This function is valid only if the transfer request is an external transfer request (if the ExR bit is 1). If it is an internal transfer request (if the ExR bit is 0), the PosE value is ignored. Because the INTDREQn and DREQn signals are active at "L" level, make sure that this PosE bit is set to "0." 1: Setting prohibited 0: The falling edge of the INTDREQn or DREQn signal or the "L" level is effective. The DACKn is active at "L" level. 12 Lev Level mode 11 SReq Channel start Normal completion interrupt enable Snoop request DMA Controller (DMAC) Description Start (initial value:-) Starts channel operation. If this bit is set to 1, the channel goes into a standby mode and starts to transfer data in response to a transfer request. Only a write of 1 is valid to the Str bit and a write of 0 is ignored. A read always returns a 0. 1: Starts channel operation This is a reserved bit. Always set this bit to "0." Level Mode (initial value: 0) Specifies which is used to recognize the external transfer request, signal level or signal change. This setting is valid only if a transfer request is the external transfer request (if the ExR bit is 1). If the internal transfer request is specified as a transfer request (if the ExR bit is 0), the value of the Lev bit is ignored. Because the INTDREQn signal is active at "L" level, make sure that you set the Lev bit to "1." The state of active DREQn is determined by the Lev bit setting. 1: Level mode The level of the DREQn signal is recognized as a data transfer request. (The "L" level is recognized if the PosE bit is 0. 0: Edge mode A change in the DREQn signal is recognized as a data transfer request. (A falling edge is recognized if the PosE bit is 0.) Snoop Request (initial value: 0) The use of the snoop function is specified by asserting the bus control request mode. If the snoop function is used, the snoop function of the TX19A/ H1 processor core is enabled and the DMAC can use the data bus of the TX19A /H1 processor core. If the snoop function is not used, the snoop function of the TX19A/ H1 processor core does not work. 1: Use snoop function (SREQ) 0: Do not use snoop function (GREQ) TMP19A44 (rev1.3) 10-9 2010-04-01 TMP19A44 Bit Mnemonic Field name 10 RelEn Bus control release request enable 9 SIO Transfer type selection 8:7 SAC Source address count 6 5:4 DIO DAC (Reserved) Destination address count 3:2 TrSiz Transfer unit 1:0 DPS Device port size Description Release Request Enable (initial value: 0) Acknowledgment of the bus control release request made by the TX19A/ H1 processor core is specified. This function is valid only if GREQ is generated. If SREQ is generated, the TX19A/ H1 processor core cannot make a bus control release request and, therefore, this function cannot be used. 1: The bus control release request is acknowledged if the DMAC has control of the bus. If the TX19A/ H1 processor core issues a bus control release request, the DMAC relinquishes control of the bus to the TX19A/ H1 processor core during a pause in bus operation. 0: The bus control release request is not acknowledged. Transfer type selection: (initial value: 0) 1 Single transfer 0: Continuous transfer (Data is transferred successively until BCRx becomes "0") Source Address Count (initial value: 00) Specifies the manner of change in a source address. 1x: Address fixed 01: Address decrease 00: Address increase This is a reserved bit. Always set this bit to "0". Destination Address Count (initial value: 00) Specifies the manner of change in a destination address. 1x: Address fixed 01: Address decrease 00: Address increase Transfer Size (initial value: 00) Specifies the amount of data to be transferred in response to one transfer request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) *This needs to be set to the same size as that of the device port size (DPS). Device Port Size (initial value: 00) Specifies the bus width of an I/O device designated as a source or destination device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) *This needs to be set to the same size as that of the transfer unit (TrSiz). Fig. 10.4 Channel Control Registers (CCRn) (2 of 2) (Note 1) The CCRn register setting must be completed before the DMAC is put into a standby mode. (Note 2) In executing continuous data transfer, a value set in DPS becomes invalid. (Note 3) Set the mode first and then set the <Str> bit. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-10 2010-04-01 TMP19A44 10.3.3 Request Select Register (RSR) 7 RSR (0xFF00_1304) 6 5 bit Symbol Read/Write 4 2 1 0 ReqS4 ReqS0 R/W After reset Function R/W 0 Always set this bit to "0." 15 14 13 See detailed description. 12 bit Symbol Read/Write After reset Function Always set this bit to "0." See detailed description. 11 10 9 8 19 18 17 16 27 26 25 24 0 23 22 21 20 bit Symbol Read/Write After reset Function 0 31 30 29 bit Symbol Read/Write After reset Function (Note) 3 28 0 Bit Mnemonic Field name 4 ReqS4 Request select (ch.4) 0 ReqS0 Request select (ch.0) Description Request Select (initial value: 0) Selects a source of the external transfer request for the DMA channel 4. 1: Request made by DREQ4 0: Request made by the interrupt controller (INTC) Request Select (initial value: 0) Selects a source of the external transfer request for the DMA channel 0. 1: Request made by DREQ0 0: Request made by the interrupt controller (INTC) Make sure that you write "0" to bits 1 through 3 and 5 through 7 of the RSR register. Fig. 10.5 DMA Control Register (RSR) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-11 2010-04-01 TMP19A44 10.3.4 Channel Status Registers (CSRn) 7 CSRn 6 5 4 bit Symbol Read/Write After reset Function 1 0 R/W Always set this bit to "0." 14 13 12 bit Symbol Read/Write After reset Function 11 10 9 8 17 16 25 24 0 23 22 NC R/W AbC R/W See detailed description. 31 bit Symbol Read/Write After reset Function 2 0 15 bit Symbol Read/Write After reset Function 3 21 20 19 18 R/W BES R BED R Conf R Always set this bit to "0." 30 29 0 See detailed description. 28 27 26 Act R 0 See detailed description. Fig. 10.6 Channel Status Register (CSRn) (1 of 2) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-12 2010-04-01 TMP19A44 Bit Mnemonic Field name 31 Act Channel active 23 NC Normal completion 22 AbC Abnormal completion 21 (Reserved) 20 BES 19 BED Destination bus error 18 Conf Configuration error 2:0 Source bus error (Reserved) Description Channel Active (initial value: 0) Indicates whether the channel is in a standby mode: 1: In a standby mode 0: Not in a standby mode Normal Completion (initial value: 0) Indicates normal completion of channel operation. If an interrupt at normal completion is permitted by the CCR register, the DMAC requests an interrupt when the NC bit becomes 1. This setting can be cleared by writing 0 to the NC bit. If a request for an interrupt at normal completion was previously issued, the request is canceled if the NC bit becomes 0. If an attempt is made to set the Str bit to 1 when the NC bit is 1, an error occurs. To start the next transfer, the NC bit must be cleared to 0. A write of 1 will be ignored. 1: Channel operation has been completed normally. 0: Channel operation has not been completed normally. Abnormal Completion (initial value: 0) Indicates abnormal completion of channel operation. If an interrupt at abnormal completion is permitted by the CCR register, the DMAC requests an interrupt when the AbC bit becomes 1. This setting can be cleared by writing 0 to the AbC bit. If a request for an interrupt at abnormal completion was previously issued, the request is canceled if the AbC bit becomes 0. Additionally, if the AbC bit is cleared to 0, each of the BES, BED and Conf bits are cleared to 0. If an attempt is made to set the Str bit to 1 when the AbC bit is 1, an error occurs. To start the next transfer, the AbC bit must be cleared to 0. A write of 1 will be ignored. 1: Channel operation has been completed abnormally. 0: Channel operation has not been completed abnormally. This is a reserved bit. Always set this bit to "0." Source Bus Error (initial value: 0) 1: A bus error has occurred when the source was accessed. 0: A bus error has not occurred when the source was accessed. Destination Bus Error (initial value: 0) 1: A bus error has occurred when the destination was accessed. 0: A bus error has not occurred when the destination was accessed. Configuration Error (initial value: 0) 1: A configuration error has occurred. 0: A configuration error has not occurred. These three bits are reserved bits. Always set them to "0." Fig. 10.6 Channel Status Register (CSRn) (2 of 2) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-13 2010-04-01 TMP19A44 10.3.5 SARn Source Address Registers (SARn) 7 6 5 bit Symbol Read/Write After reset Function SAddr7 SAddr6 SAddr5 15 14 13 bit Symbol Read/Write After reset Function SAddr15 SAddr14 SAddr13 23 22 21 bit Symbol Read/Write After reset Function SAddr23 SAddr22 SAddr21 31 30 29 bit Symbol Read/Write After reset Function SAddr31 SAddr30 SAddr29 Bit Mnemonic 31 : 0 SAddr 4 3 SAddr4 SAddr3 R/W Indeterminate See detailed description. 12 11 SAddr12 SAddr11 R/W Indeterminate See detailed description. 20 19 SAddr20 SAddr19 R/W Indeterminate See detailed description. 28 27 SAddr28 SAddr27 R/W Indeterminate See detailed description. Field name Source address 2 1 0 SAddr2 SAddr1 SAddr0 10 9 8 SAddr10 SAddr9 SAddr8 18 17 16 SAddr18 SAddr17 SAddr16 26 25 24 SAddr26 SAddr25 SAddr24 Description Source Address (initial value: -) Specifies the address of the source from which data is transferred using a physical address. This address changes according to the SAC and TrSiz settings of CCRn and the SACM setting of DTCRn. Fig. 10.7 Source Address Register (SARn) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-14 2010-04-01 TMP19A44 10.3.6 DARn Destination Address Register (DARn) 7 6 5 4 3 2 1 0 bit Symbol Read/Write After reset Function DAddr7 DAddr6 DAddr5 DAddr4 DAddr3 DAddr2 DAddr1 DAddr0 15 14 13 bit Symbol Read/Write After reset Function DAddr15 DAddr14 DAddr13 23 22 21 bit Symbol Read/Write After reset Function DAddr23 DAddr22 DAddr21 31 30 29 bit Symbol Read/Write After reset Function DAddr31 DAddr30 DAddr29 R/W Indeterminate See detailed description. Bit Mnemonic 31 : 0 DAddr 12 20 19 DAddr20 DAddr19 R/W Indeterminate See detailed description. 28 27 DAddr28 DAddr27 R/W Indeterminate See detailed description. Field name Destination address 11 DAddr12 DAddr11 R/W Indeterminate See detailed description. 10 9 8 DAddr10 DAddr9 DAddr8 18 17 16 DAddr18 DAddr17 DAddr16 26 25 24 DAddr26 DAddr25 DAddr24 Description Destination Address (initial value: -) Specifies the address of the destination to which data is transferred using a physical address. This address changes according to the DAC and TrSiz settings of CCRn and the DACM setting of DTCRn. Fig. 10.8 Destination Address Register (DARn) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-15 2010-04-01 TMP19A44 10.3.7 BCRn Byte Count Registers (BCRn) 7 6 5 4 3 2 1 0 bit Symbol Read/Write After reset Function BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 15 14 13 12 11 10 9 8 bit Symbol Read/Write After reset Function BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 23 22 21 20 19 18 17 16 bit Symbol Read/Write After reset Function BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16 26 25 24 R/W Indeterminate See detailed description. R/W Indeterminate See detailed description. R/W Indeterminate See detailed description. 31 30 bit Symbol Read/Write After reset Function 29 28 27 0 Bit Mnemonic 23 : 0 BC Field name Byte count Description Byte Count (initial value: 0) Specifies the number of bytes of data to be transferred. The address decreases by the number of pieces of data transferred (a value specified by TrSiz of CCRn). Fig. 10.9 Byte Count Register (BCRn) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-16 2010-04-01 TMP19A44 10.3.8 DMA Transfer Control Register (DTCRn) 7 DTCRn 6 5 bit Symbol Read/Write After reset Function 4 3 2 DACM R/W 0 See detailed description. 15 14 13 12 bit Symbol Read/Write After reset Function 1 0 SACM R/W See detailed description. 11 10 9 8 19 18 17 16 27 26 25 24 0 23 22 21 20 bit Symbol Read/Write After reset Function 0 31 30 29 bit Symbol Read/Write After reset Function 28 0 Bit Mnemonic Field name 5:3 DACM Destination address count mode 2:0 SACM Source address count mode Description Destination Address Count Mode Specifies the count mode of the destination address. 000: Counting begins from bit 0 001: Counting begins from bit 4 010: Counting begins from bit 8 011: Counting begins from bit 12 100: Counting begins from bit 16 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Source Address Count Mode Specifies the count mode of the source address. 000: Counting begins from bit 0 001: Counting begins from bit 4 010: Counting begins from bit 8 011: Counting begins from bit 12 100: Counting begins from bit 16 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Fig. 10.10 DMA Transfer Control Register (DTCRn) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-17 2010-04-01 TMP19A44 10.3.9 DHR (0xFF00_130C) Data Holding Register (DHR) 7 6 5 4 3 2 1 0 bit Symbol Read/Write After reset Function DOT7 DOT6 DOT5 DOT4 DOT3 DOT2 DOT1 DOT0 15 14 13 12 11 10 9 8 bit Symbol Read/Write After reset Function DOT15 DOT14 DOT13 DOT12 DOT11 DOT10 DOT9 DOT8 23 22 21 20 19 18 17 16 bit Symbol Read/Write After reset Function DOT23 DOT22 DOT21 DOT20 DOT19 DOT18 DOT17 DOT16 31 30 29 28 27 26 25 24 bit Symbol Read/Write After reset Function DOT31 DOT30 DOT29 DOT28 DOT27 DOT26 DOT25 DOT24 R/W Indeterminate See detailed description. R/W Indeterminate See detailed description. R/W Indeterminate See detailed description. R/W Indeterminate See detailed description. Bit Mnemonic 31 : 0 DOT Field name Data on transfer Description Data on Transfer (initial value: 0) Data that is read from the source in a dual-address data transfer mode Fig. 10.11 Data Holding Register (DHR) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-18 2010-04-01 TMP19A44 10.4 Functions The DMAC is a 32-bit DMA controller capable of transferring data in a system using the TX19A/ H1 processor core at high speeds without routing data via the core. 10.4.1 Overview (1) Source and destination The DMAC handles data transfers from memory to memory. A device from which data is transferred is called a source device and a device to which data is transferred is called a destination device. Memory can be designated as a source or destination device. The differences between memory and I/O devices are in the way they are accessed. When accessing an I/O device, the DMAC asserts a DACKn signal. Because there is only one line per channel that carries a DACKn signal, the number of I/O devices accessible during data transfer is limited to one. Therefore, data cannot be transferred between I/O devices. An interrupt factor can be attached to a transfer request to be sent to the DMAC. If an interrupt factor is generated, the interrupt controller (INTC) issues a request to the DMAC (the TX19A/ H1 processor core is not notified of the interrupt request. For details, see description on Interrupts.). The request issued by the INTC is cleared by the DACKn signal. Therefore, a request made to the DMAC is cleared after completion of each data transfer (transfer of the amount of data specified by TrSiz). On the other hand, during a continuous transfer, the DACKn signal is asserted only when the number of bytes transferred (value set in the BCRn register) becomes "0." Therefore, one transfer request allows data to be transferred successively without a pause. For example, if data is transferred between a internal I/O and the internal (external) memory of the TMP19A44, a request made by the internal I/O to the DMAC is cleared after completion of each data transfer and the transfer operation is always put in a standby mode for the next transfer request if the number of bytes transferred (value set in the BCRn register) does not become "0." Therefore, the DMA transfer operation continues until the value of the BCRn register becomes "0." (2) Bus control arbitration (bus arbitration) In response to a transfer request made inside the DMAC, the DMAC requests the TX19A/ H1 processor core to arbitrate bus control authority. When a response signal is returned from the core, the DMAC acquires bus control authority and executes a data transfer bus cycle. In acquiring bus control for the DMAC, use or nonuse of the data bus of the TX19A/ H1 processor core can be specified; specifically either snoop mode or non-snoop mode can be specified for each channel by using bit 11 (SReq) of the CCRn register. There are cases in which the TX19A/ H1 processor core requests the release of bus control authority. Whether or not to respond to this request can be specified for each channel by using the bit 10 (RelEn) of the CCRn register. However, this function can only be used in non-snoop mode (GREQ). In snoop mode (SREQ), the TX19A/ H1 processor core cannot request the release of bus control and, therefore, this function cannot be used. When there are no more transfer requests, the DMAC releases control of the bus. (Note 1) Do not bring the TX19A to a halt when the DMAC is in operation. (Note 2) To put the TX19A into IDLE (doze) mode when the snoop function is being used, you must first stop the DMAC. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-19 2010-04-01 TMP19A44 (3) Transfer request modes Two transfer request modes are used for the DMAC: an internal transfer request mode and an external transfer request mode. In the internal transfer request mode, a transfer request is generated inside the DMAC. Setting a start bit (Str bit of the channel control register CCRn) in the internal register of the DMAC to "1" generates a transfer request, and the DMAC starts to transfer data. In the external transfer request mode, after a start bit is set to "1," a transfer request is generated when a transfer request signal INTDREQn output by the INTC is input, or when a transfer request signal DREQn output by an external device is input. For the DMAC, two modes are provided: the level mode in which a transfer request is generated when the "L" level of the INTDREQn signal is detected and a mode in which a transfer request is generated when the falling edge or "L" level of the DREQn signal is detected. (4) Address mode For the DMAC of the TMP19A44, only one address mode is provided: a dual address mode. A single address mode is not available. In the dual address mode, both single and continuous transfers are available. Source and destination device addresses are output by the DMAC. To access an I/O device, the DMAC asserts the DACKn signal. In the dual address mode, two bus operations, a read and a write, are executed. Data that is read from a source device for transfer is first put into the data holding register (DHR) inside the DMAC and then written to a destination device. (5) Channel operation The DMAC has eight channels (channels 0 through 7). A channel is activated and put into a standby mode by setting a start (Str) bit in the channel control register (CCRn) to "1." If a transfer request is generated when a channel is in a standby mode, the DMAC acquires bus control authority and transfers data. If there is no transfer request, the DMAC releases bus control authority and goes into a standby mode. If data transfer has been completed, a channel is put in an idle state. Data transfer is completed either normally or abnormally (e.g. occurrence of errors). An interrupt signal can be generated upon completion of data transfer. Fig. 10.12 shows the state transitions of channel operation. Bus control authority not acquired Wait Start Bus control authority not acquired Bus control authority acquired Idle Transfer completed Transfer Bus control authority acquired Fig. 10.12 Channel Operation State Transition DMA Controller (DMAC) TMP19A44 (rev1.3) 10-20 2010-04-01 TMP19A44 (6) Combinations of transfer modes The DMAC can transfer data by combining each transfer mode as follows: Transfer request Edge/level Address mode "L" level (INTDREQn) Internal External "L" level (DREQn) Falling edge (DREQn) External Transfer method Continuous Single Dual Continuous Single (7) Address changes Address changes are broadly classified into three types: increases, decreases and fixed. The type of address change can be specified for each source and destination address by using SAC and DAC in the CCRn register. For a memory device, an increase, decrease or fixed can be specified. If a single transfer is selected as a source or destination device, SAC or DAC in the CCRn register must be set to "fixed." If address increase or decrease is selected, the bit position for counting can be specified using SACM or DACM in the DTCRn register. To specify the bit position for counting a source address, SACM must be used, while DACM must be used to specify the bit position for a destination address. Any of the bits 0, 4, 8, 12 and 16 can be specified as the bit position for address counting. If 0 is selected, an address normally increases or decreases. By selecting bits 4, 8, 12 or 16, it is possible to increase or decrease an address irregularly. Examples of address changes are shown below. Example 1: Monotonic increase for a source device and irregular increase for a destination device SAC: Address increase DAC: Address increase TrSiz: Transfer unit 32 bits Source address: 0xA000_1000 Destination address: 0xB000_0000 SACM: 000 counting to begin from bit 0 of the address counter DACM: 001 counting to begin from bit 4 of the address counter 1st Source 0xA000_1000 Destination 0xB000_0000 2nd 0xA000_1004 0xB000_0010 3rd 0xA000_1008 0xB000_0020 4th 0xA000_100C 0xB000_0030 ... DMA Controller (DMAC) ... TMP19A44 (rev1.3) 10-21 2010-04-01 TMP19A44 Example 2: Irregular decrease for a source device and monotonic decrease for a destination device SAC: Address decrease DAC: Address decrease TrSiz: Transfer unit 16 bits Source address: Initial value 0xA000_1000 Destination address: 0xB000_0000 SACM: 010 counting to begin from bit 8 of the address counter DACM: 000 counting to begin from bit 0 of the address counter 1st Source 0xA000_1000 Destination 0xB000_0000 2nd 0x9FFF_FF00 0xAFFF_FFFE 3rd 0x9FFF_FE00 0xAFFF_FFFC 4th 0x9FFF_FD00 0xAFFF_FFFA ... 10.4.2 ... Transfer Request For the DMAC to transfer data, a transfer request must be issued to the DMAC. There are two types of transfer request: an internal transfer request and an external transfer request. Either of these transfer requests can be selected and specified for each channel. Whichever is selected, the DMAC acquires bus control authority and starts to transfer data if the transfer request is generated after the start of channel operation. * Internal transfer request If the Str bit of CCR is set to "1" when the ExR bit of CCRn is "0," a transfer request is generated immediately. This transfer request is called an internal transfer request. The internal transfer request is valid until the channel operation is completed. Therefore, data can be transferred continuously if either of two events shown below does not occur: * A transition to a channel of higher priority * A shift of bus control authority to another bus master of higher priority * External transfer request If the ExR bit of CCRn is "1," setting the Str bit of CCR to "1" allows a channel to go into a standby mode. The INTC or an external device then generates the INTDREQn or DREQn signal for this channel to notify the DMAC of a transfer request, and a transfer request is generated. This transfer request is called an external transfer request. The external transfer request is used for a single and a continuous transfer. The TMP19A44 recognizes the transfer request signal by detecting the "L" level of the INTDREQn signal or by detecting the falling edge or "L" level of the DREQn signal. The unit of data to be transferred in response to one transfer request is specified in the TrSiz field of CCRn, and 32, 16 or 8 bits can be selected. Transfer requests using INTDREQn and DREQn are described in detail on the next page. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-22 2010-04-01 TMP19A44 c A transfer request made by the interrupt controller (INTC) A transfer request made by the interrupt controller is cleared using the DACKn signal. This DACKn signal is asserted only if a bus cycle for single transfer or the number of bytes (value set in the BCRn register) transferred at continuous transfer becomes "0." Therefore, at the single transfer, the amount of data specified by TrSiz is transferred only once because INTDREQn is cleared upon completion of one data transfer from one transfer request. On the other hand, at the continuous transfer, it can be transferred successively in response to a transfer request because INTDREQn is not cleared until the number of bytes transferred (value set in the BCRn register) becomes "0." Note that if the DMAC acknowledges an interrupt set in INTDREQn and if this interrupt is cleared by the INTC before DMA transfer begins, there is a possibility that DMA transfer might be executed once after the interrupt is cleared, depending on the timing. d A transfer request made by an external device External pins (DREQ0 and DREQ4) are internally wired to allow them to function as pins of the port 5 and the port A. These pins can be selected by setting the function control register PFFC to an appropriate setting. In the edge mode, the DREQn signal must be negated and then asserted for each transfer request to create an effective edge. In the level mode, however, successive transfer requests can be recognized by maintaining an effective level. At the continuous transfer, only the "L" level mode can be used. At the single transfer, only the falling edge mode can be used. - Level mode In the level mode, the DMAC detects the "L" level of the DREQn signal upon the rising of the internal system clock. If it detects the "L" level of the DREQn signal when a channel is in a standby mode, it goes into transfer mode and starts to transfer data. To use the DREQn signal at an active level, the PosE bit (bit 13) of the CCRn register must be set to "0." The DACKn signal is active at the "L" level, as in the case of the DREQn signal. If an external circuit asserts the DREQn signal, the DREQn signal must be maintained at the "L" level until the DACKn signal is asserted. If the DREQn signal is negated before the DACKn signal is asserted, a transfer request may not be recognized. If the DREQn signal is not at the "L" level, the DMAC judges that there is no transfer request, and starts a transfer operation for other channels or releases bus control authority and goes into a standby mode. The unit of a transfer request is specified in the TrSiz field (<bit3:2>) of the CCRn register. DREQn Transfer data A[31:1] DACKn Fig. 10.13 Transfer Request Timing (Level Mode) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-23 2010-04-01 TMP19A44 - Edge mode In the edge mode, the DMAC detects the falling edge of the DREQn signal. If it detects the falling edge of the DREQn signal upon the rising of the internal system clock (the case in which the "L" level is detected upon the rising of the system clock although it was not detected upon the rising of the previous system clock) when a channel is in a standby mode, it judges that there is a transfer request, goes into transfer mode, and starts a transfer operation. To detect the falling edge of the DREQn signal, the PosE bit (bit 13) of the CCRn register must be set to "0," and the Lev bit (bit 12) must also be set to "0." The DACKn signal is active at the "L" level. If the falling edge of the DREQn signal is detected after the DACKn signal is asserted, the next data is transferred without a pause. If there is no falling edge of the DREQn signal after the DACKn signal is asserted, the DMAC judges that there is no transfer request, and starts a transfer operation for other channels or goes into a standby mode after releasing bus control authority. The unit of a transfer request is specified in the TrSiz field (<bit3:2>) of the CCRn register. DREQn A[31:1] Transfer data Transfer data DACKn Fig. 10.14 Transfer Request Timing (Edge Mode) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-24 2010-04-01 TMP19A44 10.4.3 Address Mode In the address mode, whether the DMAC executes data transfers by outputting addresses to both source and destination devices or it does by outputting addresses to either a source device or a destination device is specified. The former is called the dual address mode, and the latter is called the single address mode. For TMP19A44 only the dual address mode is available. In the dual address mode, The DMAC first performs a read of the source device by storing the data output by the source device in one of its registers (DHR). It then executes a write on the destination device by writing the stored data to the device, thereby completing the data transfer. DMAC Source device Address c Address bus d Data c Data bus d Destination device Fig. 10.15 Basic Concept of Data Transfer in the Dual Address Mode The unit of data to be transferred by the DMAC is the amount of data (32, 16 or 8 bits) specified in the TrSiz field of the CCRn. One unit of data is transferred each time a transfer request is acknowledged. In the dual address mode, the unit of data is read from the source device, put into the DHR and written to the destination device. Access to memory takes place when the specified unit of data is transferred. If access to external memory takes place, 16-bit access takes place twice if the unit of data is set to 32 bits and if the bus width set in the CS wait controller is 16 bits. Likewise, if the unit of data is set to 32 bits and if the bus width set in the CS wait controller is 8 bits, 8-bit access takes place four times. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-25 2010-04-01 TMP19A44 10.4.4 Channel Operation A channel is activated if the Str bit of the CCRn of a channel is set to "1." If a channel is activated, an activation check is conducted and if no error is detected, the channel is put into a standby mode. If a transfer request is generated when a channel is in a standby mode, the DMAC acquires bus control authority and starts to transfer data. Channel operation is completed either normally or abnormally (forced termination or occurrence of an error). Either normal completion or abnormal completion is indicated to the CSRn. Start of channel operation A channel is activated if the Str bit of the CCRn is set to "1." When a channel is activated, a configuration error check is conducted and if no error is detected, the channel is put into a standby mode. If an error is detected, the channel is deactivated and this state of completion is considered to be abnormal completion. When a channel goes into a standby mode, the Act bit of the CSRn of that channel becomes "1." If a channel is programmed to start operation in response to an internal transfer request, a transfer request is generated immediately and the DMAC acquires bus control authority and starts to transfer data. If a channel is programmed to start operation in response to an external transfer request, the DMAC acquires bus control authority after INTDREQn or DREQn is asserted, and starts to transfer data. Completion of channel operation A channel completes operation either normally or abnormally and either one of these states is indicated to the CSRn. If an attempt is made to set the Str bit of the CCRn register to "1" when the NC or AbC bit of the CSRn register is "1," channel operation does not start and the completion of operation is considered to be abnormal completion. Normal completion Channel operation is considered to have been completed normally in the case shown below. For channel operation to be considered to have been completed normally, the transfer of a unit of data (value specified in the TrSiz field of CCRn) must be completed successfully. * When the contents of BCRn become 0 and data transfer is completed Abnormal completion Cases of abnormal completion of DMAC operation are as follows: * Completion due to a configuration error A configuration error occurs if there is a mistake in the DMA transfer setting. Because a configuration error occurs before data transfer begins, values specified in SARn, DARn and BCRn remain the same as when they were initially specified. If channel operation is completed abnormally due to a configuration error, the AbC bit of the CSRn is set to "1," along with the Conf bit. Causes of a configuration error are as follows: - The Str bit of CCRn was set to "1" when the NC bit or AbC bit of CSRn was "1." - A value that is not an integer multiple of the unit of data was set for BCRn. - A value that is not an integer multiple of the unit of data was set for SARn or DARn. - The Str bit of CCRn was set to "1" when the BCRn value was "0." DMA Controller (DMAC) TMP19A44 (rev1.3) 10-26 2010-04-01 TMP19A44 * Completion due to a bus error If the DMAC operation has been completed abnormally due to a bus error, the AbC bit of CSRn is set to "1" and the BES or BED bit of CSRn is set to "1." - (Note) A bus error was detected during data transfer. If the DMAC operation has been completed abnormally due to a bus error, BCR, SAR and DAR values cannot be guaranteed. If a bus error persists, refer to 21. "List of Functional Registers" which appear later in this document. 10.4.5 Order of Priority of Channels Concerning the four channels of the DMAC, the smaller the channel number assigned to each channel, the higher the priority. If a transfer request is generated to channels 0 and 1 simultaneously, a transfer request for channel 0 is processed with higher priority and the transfer operation is performed accordingly. When the transfer request for channel 0 is cleared, the transfer operation for channel 1 is performed if the transfer request still exists (An internal transfer request is retained if it is not cleared. The interrupt controller retains an external transfer request if the active state for an interrupt request assigned to DMA requests in the interrupt controller is set to edge mode. However, the interrupt controller does not retain an external transfer request if the active state is set to level mode. If the active state for an interrupt request assigned to DMA requests in the interrupt controller is set to level mode, it is necessary to continue asserting the interrupt request signal). If a transfer request is generated when data is being transferred through channel 1, a channel transition occurs at channel 0, that is, data transfer through channel 1 is temporarily suspended and data transfer through channel 0 is started. When the transfer request for channel 0 is cleared, data transfer through channel 1 resumes. Channel transitions occur upon the completion of data transfers (when the writing of all data in the DHR has been completed). Interrupts Upon completion of a channel operation, the DMAC can generate interrupt requests ( INTDMAn : DMA transfer completion interrupt) to the TX19A/ H1 processor core with two types of interrupts available: a normal completion interrupt and an abnormal completion interrupt. INTDMA0 : 0ch, INTDMA1: 1ch, INTDMA 2 : 2ch, INTDMA 3 : 3ch INTDMA 4 : 4ch, INTDMA5 : 5ch, INTDMA 6 : 6ch, INTDMA7 : 7ch * Normal completion interrupt If a channel operation is completed normally, the NC bit of CSRn is set to "1." If a normal completion interrupt is authorized for the NIEn bit of the CCRn, the DMAC requests the TX19A/ H1 processor core to authorize an interrupt. * Abnormal completion interrupt If a channel operation is completed abnormally, the AbC bit of CSRn is set to "1." If an abnormal completion interrupt is authorized for the AbIEn bit of the CCRn, the DMAC requests the TX19A/ H1 processor core to authorize an interrupt. (Note) The DMA transfer completion interrupt comes in two types: INTDMA0 for 0ch through 3ch and INTDMA1 for 4ch through 7ch. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-27 2010-04-01 TMP19A44 10.5 Timing Diagrams DMAC operations are synchronous to the rising edges of the internal system clock. 10.5.1 Dual Address Mode * Continuous transfer Fig. 10.16 shows an example of the timing with which 16-bit data is transferred from one external memory (16-bit width) to another (16-bit width). Data is actually transferred successively until BCRn becomes "0." tsys A [23 : 0] CS0 CS1 RD WR / HWR D [15 : 0] Data Read Data Write Fig. 10.16 Dual Address Mode (continuous) * Single transfer (1) Fig. 10.17 shows an example of the timing with which data is transferred from one external memory to another if the unit of data to be transferred is set to 16 bits and if the device port size is set to 16 bits. tsys A [23 : 0] CS0 CS1 RD WR D [15 : 0] Data Read Data Write Data Write Fig. 10.17 Dual Address Mode (single transfer) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-28 2010-04-01 TMP19A44 * Single transfer (2) Fig. 10.18 shows an example of the timing with which data is transferred from an I/O device to memory if the unit of data to be transferred is set to 16 bits and if the device port size is set to 8 bits. tsys A [23 : 0] CS0 CS1 RD WR / HWR D [15 : 0] Data Read Data Data Read Write Fig. 10.18 Dual Address Mode (single transfer) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-29 2010-04-01 TMP19A44 10.5.2 DREQn-Initiated Transfer Mode * Data transfer from internal RAM to external memory (multiplexed bus, 5-wait insertion, level mode) Fig. 10.19 shows two timing cycles in which 16-bit data is transferred twice from internal RAM to external memory (16-bit width). 5 waits (7+) clock Internal system clock DREQn DACKn ALE A [23:16] Add Add AD [15:0] Data Add Data RD WR HWR CSn R/W Fig. 10.19 Level Mode (from Internal RAM to External Memory) * Data transfer from external memory to internal RAM (multiplexed bus, 5-wait insertion, level mode) Fig. 10.20 shows two timing cycles in which 16-bit data is transferred twice from external memory (16-bit width) to internal RAM. 5 waits (7+) clock Internal system clock DREQ DACKn ALE Add A [23:16] Add AD [15:0] Data Add Data RD WR HWR CSn R/W Fig. 10.20 Level Mode (from External Memory to Internal RAM) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-30 2010-04-01 TMP19A44 * Data transfer from internal RAM to external memory (separate bus, 5-wait insertion, level mode) Fig. 10.21 shows two timing cycles in which 16-bit data is transferred twice from internal RAM to external memory (16-bit width). (7+) clock 5 waits Internal system clock DREQn DACKn A [23:0] Add Data D [15:0] Data RD WR HWR CSn R/W Fig. 10.21 Level Mode (Internal RAM to External Memory) * Data transfer from external memory to internal RAM (separate bus, 5-wait insertion, level mode) Fig. 10.22 shows two timing cycles in which 16-bit data is transferred twice from external memory (16-bid width) to internal RAM. (7+) clock 5 waits Internal system clock DREQ DACKn A [23:0] Add A [15:0] Data Data RD WR HWR CSn R/W Fig. 10.22 Level Mode (from External Memory to Internal RAM) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-31 2010-04-01 TMP19A44 * Data transfer from internal RAM to external memory (multiplexed bus, 5-wait insertion, edge mode) Fig. 10.23 shows one timing cycle in which 16-bit data is transferred once from internal RAM to external memory (16-bit width). (7+) clock 5 waits Internal system clock DREQn DACKn ALE Add A [23:16] Add AD [15:0] Data RD WR HWR CSn R/W Fig. 10.23 Edge Mode (from Internal RAM to External Memory) * Data transfer from external memory to internal RAM (multiplexed bus, 5-wait insertion, edge mode) Fig. 10.24 shows one timing cycle in which 16-bit data is transferred once from external memory (16-bit width) to internal RAM. (7+) clock 5 waits Internal system clock DREQn DACKn ALE Add A [23:16] Add AD [15:0] Data RD WR HWR CSn R/W Fig. 10.24 Edge Mode (from External Memory to Internal RAM) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-32 2010-04-01 TMP19A44 * Data transfer from internal RAM to external memory (separate bus, 5-wait insertion, edge mode) Fig. 10.25 shows one timing cycle in which 16-bit data is transferred once from internal RAM to external memory (16-bit width). (7+) clock 5 waits Internal system clock DREQn DACKn Add A [23:0] Data D [15:0] RD WR HWR CSn R/W Fig. 10.25 Edge Mode (from Internal RAM to External Memory) * Data transfer from external memory to internal RAM (separate bus, 5-wait insertion, edge mode) Fig. 10.26 shows one timing cycle in which 16-bit data is transferred once from external memory (16-bit width) to internal RAM. (7+) clock 5 waits Internal system clock DREQn DACKn Add A [23:0] Data D [15:0] RD WR HWR CSn R/W Fig. 10.26 Edge Mode (from External Memory to Internal RAM) DMA Controller (DMAC) TMP19A44 (rev1.3) 10-33 2010-04-01 TMP19A44 10.6 Case of Data Transfer The settings described below relate to a case in which serial data received (SCnBUF) is transferred to the internal RAM by DMA transfer. DMA (ch.0) is used to transfer data. The DMA0 is activated by a receive interrupt generated by SIO1. <DMA setting> * Channel used: 0 * Source address: SC1BUF * Destination: (Physical address) 0xFFFF_A000 * Number of bytes transferred: 256 bytes <Serial channel setting> * Data length 8 bits: UART * Serial channel: 1 ch * Transfer rate: 9600 bps <SIO ch.1 setting> IMC09 x111, x000 /* assigned to DMC0 activation factor * / INTCLR 0x098 /* IVR [8:0], INTRX1 interrupt factor * / SC1MOD0 0x29 /* UART mode, 8-bit length, baud rate generator * / SC1CR 0x00 BR1CR 0x1F /*T4, N=15*/ DCR 0x8000_0000 /* DMA reset * / IMC17 x000, x000 /* disable interrupt * / INTCLR 0x17C /* IVR [8:0] value * / IMC17 x000, x100 /* level = 4 (any given value) */ DTCR0 0x0000_0000 /* DACM = 000 * / <DMA0 setting> /* SACM = 000 * / SAR0 0xFF00_4C44 /* physical address of SC1BUF */ DAR0 0xFFFF_9800 /* physical address of destination to which data is transferred */ BCR0 0x0000_00FF /* 256 (number of bytes transferred) / CCR0 0x80C0_5B0F /* DMA ch.0 setting */ (Contents) 31 27 23 19 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 15 11 7 3 0 1 0 1 1 x 1 1 x 0 0 0 1 1 1 1 DMA Controller (DMAC) TMP19A44 (rev1.3) 10-34 2010-04-01 TMP19A44 10.7 DMAC Transfer Request Clear Registers (DREQFLG) Setting the DREQ [7:0] for the corresponding factor into the DREQFLG register enables to clear any DMAC transfer request. DREQ [7:0] value setting to clear the DMAC transfer request 7 DREQFLG 6 5 4 3 2 1 0 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQ0 bit Symbol DREQ7 Read/Write After reset Function 1 1 15 14 (0xFF00_10C4) R/W 1 1 1 1 Corresponding DMAC transfer request is cleared. 13 12 11 10 bit Symbol Read/Write After reset Function 1 1 9 8 R 0 23 22 21 "0" is read. 20 19 18 17 16 29 R 0 "0" is read. 28 27 26 25 24 bit Symbol Read/Write After reset Function 31 30 bit Symbol Read/Write After reset Function R 0 "0" is read. Reading 0: DMAC transfer is requested. 1: DMAC transfer is not requested. Writing 0: Invalid 1 :DMAC transfer request is cleared. DMA Controller (DMAC) TMP19A44 (rev1.3) 10-35 2010-04-01 TMP19A44 11. 16-bit Timer/Event Counters (TMRBs) Each of the eighteen channels (TMRB0 through TMR11) has a multi-functional, 16-bit timer/event counter. TMRBs operate in the following four operation modes: * 16-bit interval timer mode * 16-bit event counter mode * 16-bit programmable square-wave output (PPG) mode (simultaneous output in units of four channels can be programmed) * Timer synchronous mode The use of the capture function allows TMRBs to operate in three other modes: * Frequency measurement mode * Pulse width measurement mode * Time difference measurement mode Each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer flip-flop and its associated control circuit. Timer operation modes and the timer flip-flop are controlled by a 13-byte register. Each channel (TMRB0 through TMRB11) functions independently and while the channels operate in the same way, there are differences in their specifications as shown in Table 11.1. Therefore, the operational descriptions here are for TMRB0 only. The channels shown below are used as the capture or start trigger. (1) The flip-flop output of TMRB 0, TMRB 8 and TMRB 10 can be used as the capture trigger of other channels. TB0OUT => available for TMRB 1 through TMRB 7 TB8OUT => available for TMRB 9 through TMRB F TB10OUT => available for TMRB 11 (2) The start trigger of the timer synchronous mode (with TBxRUN) TMRB0 => can start TMRB 0 through TMRB 3 synchronously TMRB4 => can start TMRB 4 through TMRB 7 synchronously TMRB8 => can start TMRB 8, 9, A and B synchronously TMRBC => can start TMRB C through TMRB F synchronously TMRB10 => can start TMRB 10 through TMRB 11 synchronously 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-1 2010-04-01 TMP19A44 Table 11.1 Differences in the Specifications of TMRB Modules External pins Channel Specification External clock/ capture trigger pins input Internal signals Timer flip-flop output Timer for capture triggers pin Timer for synchronous start TMRB0 TB0OUT(shared with P54) TMRB1 TB1IN0 (shared with P20) TB1IN1 (shared with P21) TB1OUT (shared with P55) TMRB2 TB2IN0 (shared with P22) TB2IN1 (shared with P23) TB2OUT (shared with P56) TMRB3 TB3IN0 (shared with P24) TB3IN1 (shared with P25) TB3OUT (shared with P57) TMRB4 TB4OUT (shared with P63) TMRB5 TB5IN0 (shared with P26) TB5IN1 (shared with P27) TB5OUT (shared with P67) TMRB6 TB6IN0 (shared with PA4) TB6IN1 (shared with PA5) TB6OUT(shared with PB2) TMRB7 TB7OUT (shared with PB3) TMRB8 TB8OUT (shared with PB7) TMRB9 TB9IN0 (shared with PH0) TB9IN1 (shared with PH1) TB9OUT (shared with P93) TMRBA TBAIN0 (shared with PH2) TBAIN1 (shared with PH3) TBAOUT (shared with P97) TMRBB TBBIN0 (shared with PH4) TBBIN1 (shared with PH5) TBBOUT (shared with PD3) TMRBC TBCOUT (shared with PD4) TMRBD TBDIN0 (shared with PH6) TBDIN1 (shared with PH7) TBDOUT (shared with PD5) TMRB0 TB0OUT TMRB4 TMRB8 TB8OUT TMRBE TBEOUT (shared with P34) TMRBF TBFOUT (shared with P47) TMRB10 TBFOUT (shared with PI5) TBFOUT (shared with PI6) TB10OUT TMRB10 TMRB11 TB11IN0 (shared with PJ0) TB11IN1 (shared with PJ1) TMRBC 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-2 2010-04-01 TBOUT0 TB1IN0 TB1IN1 Prescaler clock: T0 T4 4 T16 Count clock TB1RUN <TB1RDE> 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-3 Internal data bus Register buffer 1 16-bit timer register TB1RG1 16-bit comparator (CP1) TB1FF0 16-bit timer status register TB1ST Overflow interrupt output Internal data bus Match detection Match detection Timer flip-flop control Timer flip-flop Register 0 interrupt output Register buffer 0 16-bit timer register TB1RG0 16-bit comparator (CP0) 16-bit up-counter (UC0) TB1RUN<TB1RUN> TB1MOD<TB1CLE> Capture register 1 TB1CP1 Register 1 interrupt output TB1RUN <TB1RDE> Selector TB1MOD<TB1CLK1 : 0> TB1MOD T1 <TB1CPM1:0> T4 T16 Internal data bus Timer upcpimter register TB1UC Capture register 0 TB1CP0 TB1RUN <TB1PRUN> TB1MOD Capture control <TB1CP0> T1 2 run/ clear 8 16 32 Internal data bus TMRB1 interrupt INTTB1 TB1OUT Timer flip-flop output TMP19A44 11.1 Block Diagram of Each Channel (Note) Channels 0, 8 and 10 do not have input pin. TB0OUT is input to channels 1 and 4. TB8OUT is input to channels 9 through F. TB9OUT is input to channels 11. Fig. 11.1 TMRB1 Block Diagram (Same for Other Channels) 2010-04-01 TMP19A44 11.2 Register Description 11.2.1 TMRB registers Table 11.2 shows the register names and addresses of each channel. Table 11.2 TMRB registers Channel Specification TMRB0 Timer enable register TB0EN (0xFF00_4500) Timer RUN register TB0RUN (0xFF00_4504) Timer control register TB0CR (0xFF00_4508) Timer mode register TB0MOD (0xFF00_450C) Timer flip-flop control TB0FFCR register (0xFF00_4510) Register TB0ST Timer status register names (0xFF00_4514) (addresse TB0IM Interrupt mask register s) (0xFF00_4518) Timer up counter TB0UC register (0xFF00_451C) TB0RG0 (0xFF00_4520) Timer register TB0RG1 (0xFF00_4524) TB0CP0 (0xFF00_4528) Capture register TB0CP1 (0xFF00_452C) Channel Specification Timer enable register TMRB4 TB4EN (0xFF00_4600) Timer RUN register TB4RUN (0xFF00_4604) Timer control register TB4CR (0xFF00_4608) Timer mode register TB4MOD (0xFF00_460C) Timer flip-flop control TB4FFCR register (0xFF00_4610) Register TB4ST Timer status register names (0xFF00_4614) (addresse TB4IM Interrupt mask register s) (0xFF00_4618) Timer up counter TB4UC register (0xFF00_461C) TB4RG0 (0xFF00_4620) Timer register TB4RG1 (0xFF00_4624) TB4CP0 (0xFF00_4628) Capture register TB4CP1 (0xFF00_462C) TMRB1 TB1EN (0xFF00_4540) TB1RUN (0xFF00_4544) TB1CR (0xFF00_4548) TB1MOD (0xFF00_454C) TB1FFCR (0xFF00_4550) TB1ST (0xFF00_4554) TB1IM (0xFF00_4558) TB1UC (0xFF00_455C) TB1RG0 (0xFF00_4560) TB1RG1 (0xFF00_4564) TB1CP0 (0xFF00_4568) TB1CP1 (0xFF00_456C) TMRB5 TB5EN (0xFF00_4640) TB5RUN (0xFF00_4644) TB5CR (0xFF00_4648) TB5MOD (0xFF00_464C) TB5FFCR (0xFF00_4650) TB5ST (0xFF00_4654) TB5IM (0xFF00_4658) TB5UC (0xFF00_465C) TB5RG0 (0xFF00_4660) TB5RG1 (0xFF00_4664) TB5CP0 (0xFF00_4668) TB5CP1 (0xFF00_466C) 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-4 TMRB2 TB2EN (0xFF00_4580) TB2RUN (0xFF00_4584) TB2CR (0xFF00_4588) TB2MOD (0xFF00_458C) TB2FFCR (0xFF00_4590) TB2ST (0xFF00_4594) TB2IM (0xFF00_4598) TB2UC (0xFF00_459C) TB2RG0 (0xFF00_45A0) TB2RG1 (0xFF00_45A4) TB2CP0 (0xFF00_45A8) TB2CP1 (0xFF00_45AC) TMRB6 TB6EN (0xFF00_4680) TB6RUN (0xFF00_4684) TB6CR (0xFF00_4688) TB6MOD (0xFF00_468C) TB6FFCR (0xFF00_4690) TB6ST (0xFF00_4694) TB6IM (0xFF00_4698) TB6UC (0xFF00_469C) TB6RG0 (0xFF00_46A0) TB6RG1 (0xFF00_46A4) TB6CP0 (0xFF00_46A8) TB6CP1 (0xFF00_46AC) TMRB3 TB3EN (0xFF00_45C0) TB3RUN (0xFF00_45C4) TB3CR (0xFF00_45C8) TB3MOD (0xFF00_45CC) TB3FFCR (0xFF00_45D0) TB3ST (0xFF00_45D4) TB3IM (0xFF00_45D8) TB3UC (0xFF00_45DC) TB3RG0 (0xFF00_45E0) TB3RG1 (0xFF00_45E4) TB3CP0 (0xFF00_45E8) TB3CP1 (0xFF00_45EC) TMRB7 TB7EN (0xFF00_46C0) TB7RUN (0xFF00_46C4) TB7CR (0xFF00_46C8) TB7MOD (0xFF00_46CC) TB7FFCR (0xFF00_46D0) TB7ST (0xFF00_46D4) TB7IM (0xFF00_46D8) TB7UC (0xFF00_46DC) TB7RG0 (0xFF00_46E0) TB7RG1 (0xFF00_46E4) TB7CP0 (0xFF00_46E8) TB7CP1 (0xFF00_46EC) 2010-04-01 TMP19A44 Channel Specification TMRB8 Timer enable register TB8EN (0xFF00_4700) Timer RUN register TB8RUN (0xFF00_4704) Timer control register TB8CR (0xFF00_4708) Timer mode register TB8MOD (0xFF00_470C) Timer flip-flop control TB8FFCR register (0xFF00_4710) Register TB8ST Timer status register names (0xFF00_4714) (addresse TB8IM Interrupt mask register s) (0xFF00_4718) Timer up counter TB8UC register (0xFF00_471C) TB8RG0 (0xFF00_4720) Timer register TB8RG1 (0xFF00_4724) TB8CP0 (0xFF00_4728) Capture register TB8CP1 (0xFF00_472C) Channel Specification Timer enable register TMRBC TBCEN (0xFF00_4800) Timer RUN register TBCRUN (0xFF00_4804) Timer control register TBCCR (0xFF00_4808) Timer mode register TBCMOD (0xFF00_480C) Timer flip-flop control TBCFFCR register (0xFF00_4810) Register TBCST Timer status register names (0xFF00_4814) (addresse TBCIM Interrupt mask register s) (0xFF00_4818) Timer up counter TBCUC register (0xFF00_481C) TBCRG0 (0xFF00_4820) Timer register TBCRG1 (0xFF00_4824) TBCCP0 (0xFF00_4828) Capture register TBCCP1 (0xFF00_482C) TMRB9 TMRBA TB9EN (0xFF00_4740) TB9RUN (0xFF00_4744) TB9CR (0xFF00_4748) TB9MOD (0xFF00_474C) TB9FFCR (0xFF00_4750) TB9ST (0xFF00_4754) TB9IM (0xFF00_4758) TB9UC (0xFF00_475C) TB9RG0 (0xFF00_4760) TB9RG1 (0xFF00_4764) TB9CP0 (0xFF00_4768) TB9CP1 (0xFF00_476C) TBAEN (0xFF00_4780) TBARUN (0xFF00_4784) TBACR (0xFF00_4788) TBAMOD (0xFF00_478C) TBAFFCR (0xFF00_4790) TBAST (0xFF00_4794) TBAIM (0xFF00_4798) TBAUC (0xFF00_479C) TBARG0 (0xFF00_47A0) TBARG1 (0xFF00_47A4) TBACP0 (0xFF00_47A8) TBACP1 (0xFF00_47AC) TMRBD TBDEN (0xFF00_4840) TBDRUN (0xFF00_4844) TBDCR (0xFF00_4848) TBDMOD (0xFF00_484C) TBDFFCR (0xFF00_4850) TBDST (0xFF00_4854) TBDIM (0xFF00_4858) TBDUC (0xFF00_485C) TBDRG0 (0xFF00_4860) TBDRG1 (0xFF00_4864) TBDCP0 (0xFF00_4868) TBDCP1 (0xFF00_486C) 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-5 TMRBE TBAEN (0xFF00_4880) TBERUN (0xFF00_4884) TBECR (0xFF00_4888) TBEMOD (0xFF00_488C) TBEFFCR (0xFF00_4890) TBEST (0xFF00_4894) TBEIM (0xFF00_4898) TBEUC (0xFF00_489C) TBERG0 (0xFF00_48A0) TBERG1 (0xFF00_48A4) TBECP0 (0xFF00_48A8) TBECP1 (0xFF00_48AC) TMRBB TBBEN (0xFF00_47C0) TBBRUN (0xFF00_47C4) TBBCR (0xFF00_47C8) TBBMOD (0xFF00_47CC) TBBFFCR (0xFF00_47D0) TBBST (0xFF00_47D4) TBBIM (0xFF00_47D8) TBBUC (0xFF00_47DC) TBBRG0 (0xFF00_47E0) TBBRG1 (0xFF00_47E4) TBBCP0 (0xFF00_47E8) TBBCP1 (0xFF00_47EC) TMRBF TBFEN (0xFF00_48C0) TBFRUN (0xFF00_48C4) TBFCR (0xFF00_48C8) TBFMOD (0xFF00_48CC) TBFFFCR (0xFF00_48D0) TBFST (0xFF00_48D4) TBFIM (0xFF00_48D8) TBFUC (0xFF00_48DC) TBFRG0 (0xFF00_48E0) TBFBRG1 (0xFF00_48E4) TBFCP0 (0xFF00_48E8) TBFCP1 (0xFF00_48EC) 2010-04-01 TMP19A44 Channel TMRB10 TMRB11 TB10EN (0xFF00_4900) Timer RUN register TB10RUN (0xFF00_4904) Timer control register TB10CR (0xFF00_4908) Timer mode register TB10MOD (0xFF00_490C) Timer flip-flop control TB10FFCR register (0xFF00_4910) Register TB10ST Timer status register names (0xFF00_4914) (addresse TB10IM Interrupt mask register s) (0xFF00_4918) Timer up counter TB10UC register (0xFF00_491C) TB10RG0 (0xFF00_4920) Timer register TB10RG1 (0xFF00_4924) TB10CP0 (0xFF00_4928) Capture register TB10CP1 (0xFF00_492C) TB11EN (0xFF00_4940) TB11RUN (0xFF00_4944) TB11CR (0xFF00_4948) TB11MOD (0xFF00_494C) TB11FFCR (0xFF00_4950) TB11ST (0xFF00_4954) TB11IM (0xFF00_4958) TB11UC (0xFF00_495C) TB11RG0 (0xFF00_4960) TB11RG1 (0xFF00_4964) TB11CP0 (0xFF00_4968) TB11CP1 (0xFF00_496C) Specification Timer enable register 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-6 2010-04-01 TMP19A44 11.3 Description of Operations for Each Circuit 11.3.1 Prescaler There is a 4-bit prescaler for acquiring the TMRB0 source clock. The prescaler input clock T0 is fperiph/2, fperiph/4, fperiph/8 or fperiph/16 selected by SYSCR0<PRCK2:0> in the CG. The peripheral clock, fperiph, is either fgear, a clock selected by SYSCR1<FPSEL> in the CG, or fc, which is a clock before it is divided by the clock gear. The operation or the stoppage of a prescaler is set with TB0RUN<TB0PRUN> where writing "1" starts counting and writing "0" clears and stops counting. Table 11.3shows prescaler output clock resolutions. Table 11.3 Prescaler Output Clock Resolutions (fsys = 80MHz) Release peripheral clock <FPSEL> Clock gear value Select prescaler clock <GEAR2:0> (fsys) <PRCK2:0> 000(fperiph/2) 001(fperiph/4) 000 (fc) 100(fc/2) 0 (fgear) 101(fc/4) 110(fc/8) 111(fc/16) Prescaler output clock resolutions T1 T4 T16 fc/22(0.05s) fc/23(0.1s) 4 fc/24(0.2s) fc/25(0.4s) 7 fc/2 (1.6s) 010(fperiph/8) fc/2 (0.2s) fc/2 (0.8s) fc/28(3.2s) 011(fperiph/16) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) 6 6 fc/26(0.8s) 100(fperiph/32) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 000(fperiph/2) fc/23(0.1s) fc/25(0.4s) 7 fc/2 (1.6s) 4 8 6 001(fperiph/4) fc/2 (0.2s) fc/2 (0.8s) 8 fc/2 (3.2s) 010(fperiph/8) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) 6 011(fperiph/16) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 100(fperiph/32) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 4 8 6 000(fperiph/2) fc/2 (0.2s) fc/2 (0.8s) 8 fc/2 (3.2s) 001(fperiph/4) fc/25(0.4s) 7 fc/2 (1.6s) fc/29(6.4s) 6 010(fperiph/8) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 011(fperiph/16) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 8 8 100(fperiph/32) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 000(fperiph/2) fc/25(0.4s) 7 fc/2 (1.6s) fc/29(6.4s) 6 10 001(fperiph/4) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 010(fperiph/8) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 8 8 011(fperiph/16) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 100(fperiph/32) fc/29(6.4s) fc/211(25.6s) fc/213(102.4s) 6 10 000(fperiph/2) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 001(fperiph/4) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 8 8 010(fperiph/8) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 011(fperiph/16) fc/29(6.4s) fc/211(25.6s) fc/213(102.4s) 10 10 100(fperiph/32) fc/2 (12.8s) fc/2 (51.2s) fc/214(204.8s) 100(fperiph/32) fc/26(0.8s) 8 fc/2 (3.2s) fc/210(12.8s) 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-7 12 2010-04-01 TMP19A44 Release peripheral clock <FPSEL> Clock gear value Select prescaler clock <GEAR2:0> (fsys) <PRCK2:0> 000 (fc) 100(fc/2) 000(fperiph/2) 001(fperiph/4) 2 fc/2 (0.05s) fc/2 (0.1s) fc/2 (0.4s) fc/27(1.6s) 010(fperiph/8) fc/24(0.2s) fc/26(0.8s) fc/28(3.2s) 111(fc/16) 5 7 fc/26(0.8s) fc/2 (1.6s) fc/29(6.4s) 100(fperiph/32) fc/26(0.8s) 8 fc/2 (3.2s) fc/210(12.8s) 4 000(fperiph/2) 001(fperiph/4) fc/23(0.1s) 4 fc/2 (0.2s) fc/26(0.8s) fc/25(0.4s) fc/27(1.6s) 010(fperiph/8) fc/2 (0.2s) fc/2 (0.8s) fc/28(3.2s) 011(fperiph/16) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) 001(fperiph/4) 110(fc/8) 5 fc/24(0.2s) fc/2 (0.4s) 000(fperiph/2) 101(fc/4) 3 011(fperiph/16) 100(fperiph/32) 1 (fc) Prescaler output clock resolutions T1 T4 T16 6 fc/2 (0.8s) 4 6 8 fc/2 (3.2s) fc/210(12.8s) fc/24(0.2s) fc/26(0.8s) 5 7 fc/2 (1.6s) 6 fc/2 (0.4s) 010(fperiph/8) fc/2 (0.2s) fc/2 (0.8s) fc/28(3.2s) 011(fperiph/16) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) 6 100(fperiph/32) fc/2 (0.8s) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8) 8 fc/2 (3.2s) 5 fc/26(0.8s) fc/2 (0.4s) fc/27(1.6s) fc/26(0.8s) 8 fc/2 (3.2s) 011(fperiph/16) fc/2 (0.4s) fc/2 (1.6s) fc/29(6.4s) 100(fperiph/32) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) 000(fperiph/2) 001(fperiph/4) fc/26(0.8s) fc/27(1.6s) 010(fperiph/8) fc/26(0.8s) 8 fc/2 (3.2s) 011(fperiph/16) fc/27(1.6s) fc/29(6.4s) 100(fperiph/32) 5 fc/210(12.8s) 6 fc/2 (0.8s) 7 8 fc/2 (3.2s) fc/210(12.8s) (Note 1) The prescaler output clock Tn must be selected so that Tn<fsys/2 is satisfied (so that Tn is slower than fsys/2). (Note 2) Do not change the clock gear while the timer is operating. (Note 3) "" denotes a setting prohibited. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-8 2010-04-01 TMP19A44 11.3.2 Up-counter (UC0) and Time Up-counter Registers (TB0UC) This is the 16-bit binary counter that counts up in response to the input clock specified by TB0MOD<TB0CLK1:0>. UC0 input clock can be selected from either three types - T1, T4 and T16 - of prescaler output clock or the external clock of the TB0IN0 pin. For UC0, start, stop and clear are specified by TB0RUN<TB0RUN> and if UC0 matches the TB0RG1 timer register, it is cleared to "0" if the setting is "clear enable." Clear enable/disable is specified by TB0MOD<TB0CLE>. If the setting is "clear disable," the counter operates as a free-running counter. The current count value of the UC0 can be captured by reading the TB0UC registers. If UC0 overflow occurs, the INTTB0 overflow interrupt is generated. 11.3.3 Timer Registers (TB0RG0, TB0RG1) These are 16-bit registers for specifying counter values and two registers are built into each channel. If a value set on this timer register matches that on a UC0 up-counter, the match detection signal of the comparator becomes active. To write data to the TB0RG0H/L and TB0RG1H/L timer registers, either a 2-byte data transfer instruction or a 1-byte data transfer instruction written twice in the order of low-order 8 bits followed by high-order 8 bits can be used. TB0RG0 of this timer register is paired with register buffer 0 - a double-buffered configuration. TB0RG0/1 uses TB0CR<TB0WBF> to control the enabling/disabling of double buffering so that if < TB0WBF> = "0," double buffering is disabled and if < TB0WBF> = "1," it is enabled. If double buffering is enabled, data is transferred from register buffer 0 to the TB0RG0/1 timer register when there is a match between UC0 and TB0RG0/1. A reset initializes TB0CR <TB0WBF> to "0" and sets double buffering to "disable." To use double buffering, write data to the timer register, set <TB0WBF> to "1" and then write the following data to the register buffers. TB0RG0/1 and the register buffers are assigned to the same address: 0xFF00_4520/0xFF00_4524. If <TB0WBF> = "0," the same value is written to TB0RG0/1 and each register buffer; if <TB0WBF> = "1," the value is only written to each register buffer. To write an initial value to the timer register, therefore, the register buffers must be set to "disable." 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-9 2010-04-01 TMP19A44 11.3.4 Capture Registers (TB0CP0, TB0CP1) These are 16-bit registers for latching values from the UC0 up-counter. 11.3.5 Capture This is a circuit that controls the timing of latching values from the UC0 up-counter into the TB0CP0 and TB0CP1 capture registers. The timing with which to latch data is specified by TB0MOD <TB0CPM1:0>. Software can also be used to import values from the UC0 up-counter into the capture register; specifically, UC0 values are taken into the TB0CP0 capture register each time "0" is written to TB0MOD<TB0CP0>. To use this capability, the prescaler must be running (TB0RUN<TB0PRUN> = "1"). 11.3.6 Comparators (CP0, CP1) These are 16-bit comparators for detecting a match by comparing set values of the UC0 up-counter with set values of the TB0RG0 and TB0RG1 timer registers. If a match is detected, INTTB0 is generated. 11.3.7 Timer Flip-flop (TB0FF0) The timer flip-flop (TB0FF0) is reversed by a match signal from the comparator and a latch signal to the capture registers. It can be enabled or disabled to reverse by setting the TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1, TB0E0T1>. The value of TB0FF0 becomes undefined after a reset. The flip-flop can be reversed by writing "00" to TB0FFCR<TB0FF0C1:0>. It can be set to "1" by writing "01," and can be cleared to "0" by writing "10." The value of TB0FF0 can be output to the timer output pin, TB0OUT (shared with P54). To enable timer output, the port 5 related registers P5CR and P5FC must be programmed beforehand. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-10 2010-04-01 TMP19A44 11.4 Registers TBnEN (0xFF00_4xx0) bit Symbol Read/Write After reset Function 7 TBnEN R/W 0 TMRBn operation 0: Disable 1: Enable 6 15 14 TMRBn Enable Registern=0~11 5 4 3 2 1 0 R 0 This can be read as "0". 13 12 bit Symbol Read/Write After reset 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset R 0 TBnEN: Specifies the TMRB operation. When the operation is disabled, no clock is supplied to the other registers in the TMRB module. This can reduce power consumption. (This disables reading from and writing to the other registers.) To use the TMRB, enable the TMRB operation (set to "1") before programming each register in the TMRB module. If the TMRB operation is executed and then disabled, settings will be maintained in each register. TMRBn RUN Registern=0~11 7 TBnRUN (0xFF00_4xx4) 6 5 4 3 12 11 10 9 8 19 18 17 16 27 26 25 24 bit Symbol Read/Write After reset R 0 This can be read as "0". Function 15 14 13 bit Symbol Read/Write After reset 2 1 0 TBnRUN TBnPRU N R/W R R/W 0 0 0 Timer Run/Stop Control 0: Stop & clear 1: Count * The first bit can be read as "0." R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset R 0 TBnRUN : Controls the TMRB0 count operation. TBnPRUN: Controls the TMRB0 prescaler operation. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-11 2010-04-01 TMP19A44 TMRBn Control Register (n=0~11) TBnCR (0xFF00_4xx8) bit Symbol Read/Write After reset Function 7 TBnWBF 6 R/W R/W 0 0 Write "0". Double Buffering 0:Disable 1:Enable 15 14 5 TBnSYN C R/W 0 Synchronizati on mode switch-over 0: Individual operation 1: Synchronous operation 4 3 I2TBn R 0 This can be read as "0". R/W 0 IDLE 0:Stop 1:Operat e 12 11 10 9 8 19 18 17 16 27 26 25 24 13 bit Symbol Read/Write After reset 2 1 0 R 0 This can be read as "0". R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset R 0 I2TBm:Controls the operation in the IDLE mode. TBnSYNC:Controls operation mode of timers. "0": timers operate individually. "1": timers operate synchronously. TBmWBF:Controls enabling/disabling of double buffering. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-12 2010-04-01 TMP19A44 TMRBn Mode Register (n=0~11) 7 TBnMOD (0xFF00_4xx4) 6 bit Symbol Read/Write After reset R 0 This can be read as "0". 5 TBnCP0 R/W W 0 1 Write "0". Capture Function 4 3 TBnCPM TBnCPM 1 0 0 0 Capture timing 14 R/W 0 control by 00: Disable software Upcounter control 0: Capture by software 0: Clear/disabl e 01: TBnIN0 TBnIN1 10: TBnIN0 TBnIN0 11: CAPTRG CAPTRG 1: Don't care 15 2 TBnCLE 13 1: 1 TBnCLK 1 0 TBnCLK 0 0 0 Selects source clock 00: TBnIN0 pin input 01: T1 10: T4 11: T16 Clear/enabl e 12 bit Symbol Read/Write After reset 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset R 0 TBnCLK1:0Clears and controls the TMRBn up-counter. TBnCLE:Disables clearing of the up-counter. "0": Disables clearing of the up-counter. "1": Clears up-counter if there is a match with timer register 1 (TBnRG1). TBnCPM1:0:Specifies TMRBn capture timing. "00": Capture disable "01": Takes count values into capture register 0 (TBnCP0) upon the rising of TBnIN0 pin input. Takes count values into capture register 1 (TBnCP1) upon the rising of TBnIN1 pin input. "10": Takes count values into capture register 0 (TBnCP0) upon the rising of TBnIN0 pin input. Takes count values into capture register 1 (TBnCP1) upon the falling of TBnIN0 pin input. "11":Takes count values into capture register 0 (TBnCP0) upon the rising of 16-bit timer match output (TB3OUT) and into capture register 1 (TBnCP1) upon the falling of TBxOUT (TMRB1 through TMRB7TB0OUT, TMRB9 through F:TB8OUT and TMRB11TB10OUT). TBnCP0:Captures count values by software and takes them into capture register 0 (TBnCP0). (Note) The value read from bit 5 of TBnMOD is "1." 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-13 2010-04-01 TMP19A44 TMRBn Flip-flop Control Register (n=0~11) 7 TBnFFCR (0xFF00_4xx8) 6 bit Symbol Read/Write After reset R 1 1 This is always read as "11." Function 5 4 3 2 1 0 TBnC1T1 TBnC0T1 TBnE1T1 TBnE0T1 TBnFF0C TBnFF0C 1 0 R/W R/W 0 0 0 0 1 1 TBnFF0 reverse trigger TBnFF0 control 0: Disable trigger 00: Invert 1: Enable trigger 01: Set When the When the When the When the 10: Clear up-counter up-counter up-counter up-counter 11: Don't care value is taken into TBnCP1 15 14 13 value is taken into TBnCP0 matches TBnRG1 matches TBnRG0 11 10 9 8 19 18 17 16 27 26 25 24 12 bit Symbol Read/Write After reset *This is always read as "11." R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 30 29 bit Symbol Read/Write After reset 28 R 0 <TBnFF0C1:0>: Controls the timer flip-flop. "00": Reverses the value of TBnFF0 (reverse by using software). "01": Sets TBnFF0 to "1." "10": Clears TBnFF0 to "0." "11": Don't care <TBnE1:0>: Reverses the timer flip-flop when the up-counter matches the timer register 0, 1 (TBnRG0, 1). <TBnC1:0>: Reverses the timer flip-flop when the up-counter value is taken into the capture register 0, 1 (TBnCP0, 1). 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-14 2010-04-01 TMP19A44 TMRBn Status Register (n=0~11) 7 6 5 4 3 2 INTTBOFn bit Symbol TBnST (0xFF00_4xxC) Read/Write After reset R 0 This can be read as "0". 0 0: Interrupt not generated 1: Interrupt Function generated 15 14 13 12 bit Symbol Read/Write After reset 1 0 INTTBn1 INTTBn0 R 0 0 0: Interrupt not generated 1: Interrupt generated 0: Interrupt not generated 1: Interrupt generated 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset R 0 <INTTBn0>: Interrupt generated if there is a match with timer register 0 (TBnRG0) <INTTBn1>: Interrupt generated if there is a match with timer register 1 (TBnRG1) <INTTB0Fn>: Interrupt generated if an up-counter overflow occurs (Note) If any interrupt is generated, the flag that corresponds to the interrupt is set to TBnST and the generation of interrupt is notified to INTC. The flag is cleared by reading the TBnST register. TMRBn Interrupt Mask Register (n=0~11) 7 TBnIM (0xFF00_4xx0) 6 5 4 3 R 0 This can be read as "0". 0 1 TBIMn1 R/W 0 1: 1: 0 TBIMn0 0 1: Interrupt Interrupt Interrupt is is is masked masked masked Function 15 14 13 12 bit Symbol Read/Write After reset 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 bit Symbol Read/Write After reset 2 TBIMOFn bit Symbol Read/Write After reset 30 29 28 R 0 TBIMn0:Interrupt is masked if there is a match with timer register 0 (TBnRG0). TBIMn1:Interrupt is masked if there is a match with timer register 1 (TBnRG1). TBIMOFn:Interrupt is masked if an up-and-down counter overflow occurs. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-15 2010-04-01 TMP19A44 TBnUC Time Up-counter Registers (n=0~11) TBnUC (0xFF00_4xx4) bit Symbol 7 6 5 4 3 2 1 0 UCn7 UCn6 UCn5 UCn4 UCn3 UCn2 UCn1 UCn0 9 8 UCn9 UCn8 Read/Write After reset Function bit Symbol 15 14 UCn15 UCn14 Read/Write After reset Function R/W 0 Data obtained by read capture: 7-0 bit data 13 12 11 10 UCn13 UCn12 23 22 21 20 bit Symbol Read/Write After reset UCn10 19 18 17 16 27 26 25 24 R 0 31 bit Symbol Read/Write After reset UCn11 R/W 0 Data obtained by read capture: 15-8 bit data 30 29 28 R 0 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-16 2010-04-01 TMP19A44 TBnRG0 Timer Register (n=0~11) TBnRG0 (0xFF00_4xx8) bit Symbol 7 TBnRG0 7 6 TBnRG0 6 Read/Writ e After reset Function bit Symbol 15 TBnRG0 15 14 TBnRG0 14 Read/Writ e After reset Function 5 TBnRG0 5 4 3 TBnRG0 TBnRG0 4 3 R/W 2 TBnRG0 2 0 Timer count value: 7-0 bit data 13 12 11 10 TBnRG0 TBnRG0 TBnRG0 TBnRG0 13 12 11 10 R/W 1 TBnRG0 1 0 TBnRG0 0 9 TBnRG0 9 8 TBnRG0 8 0 Timer count value: 15-8 bit data 23 22 21 20 bit Symbol Read/Writ e After reset 19 18 17 16 27 26 25 24 1 TBnRG1 1 0 TBnRG1 0 9 TBnRG1 9 8 TBnRG1 8 R 0 31 30 29 28 bit Symbol Read/Writ e After reset R 0 TBnRG1 Timer Register (n=0~11) bit Symbol TBnRG1 (0xFF00_4xxC) 7 TBnRG1 7 6 TBnRG1 6 15 TBnRG1 15 14 TBnRG1 14 23 22 Read/Write After reset Function bit Symbol Read/Write After reset Function 5 TBnRG1 5 4 3 2 TBnRG1 TBnRG1 TBnRG1 4 3 2 R/W 0 Timer count value: 7-0 bit data 13 12 11 10 TBnRG1 TBnRG1 TBnRG1 TBnRG1 13 12 11 10 R/W 0 Timer count value: 15-8 bit data 21 20 bit Symbol Read/Write After reset 18 17 16 27 26 25 24 R 0 31 bit Symbol Read/Write After reset 19 30 29 28 R 0 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-17 2010-04-01 TMP19A44 TBnCP0 Capture Register (n=0~11) TBnCP0 (0xFF00_4xx0) bit Symbol 7 TBnCP0 7 6 TBnCP0 6 5 TBnCP0 5 2 TBnCP0 2 1 TBnCP0 1 0 TBnCP0 0 15 TBnCP0 15 14 TBnCP0 14 R Undefined. Timer capture value: 7-0 bit data 13 12 11 10 TBnCP0 TBnCP0 TBnCP0 TBnCP0 13 12 11 10 R Undefined. Timer capture value: 15-8 bit data 9 TBnCP0 9 8 TBnCP0 8 23 22 Read/Write After reset Function bit Symbol Read/Write After reset Function 21 4 TBnCP0 4 3 TBnCP0 3 20 bit Symbol Read/Write After reset 19 18 17 16 27 26 25 24 R 0 31 30 29 28 bit Symbol Read/Write After reset R 0 TBnCP1 Capture Register (n=0~11) TBnCP1 (0xFF00_4xx4) bit Symbol 7 TBnCP1 7 6 TBnCP1 6 5 TBnCP1 5 2 TBnCP1 2 1 TBnCP1 1 0 TBnCP1 0 15 TBnCP1 15 14 TBnCP1 14 R Undefined. Timer capture value: 7-0 bit data 13 12 11 10 TBnCP1 TBnCP1 TBnCP1 TBnCP1 13 12 11 10 R Undefined. Timer capture value: 15-8 bit data 9 TBnCP1 9 8 TBnCP1 8 23 22 Read/Write After reset Function bit Symbol Read/Write After reset Function 21 4 TBnCP1 4 20 bit Symbol Read/Write After reset 19 18 17 16 27 26 25 24 R 0 31 bit Symbol Read/Write After reset 3 TBnCP1 3 30 29 28 R 0 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-18 2010-04-01 TMP19A44 11.5 Description of Operations for Each Mode 11.5.1 16-bit Interval Timer Mode Generating interrupts at periodic cycles To generate the INTTB0 interrupt, specify a time interval in the TB0RG1 timer register. 7 6 5 4 3 2 1 0 TB0EN TB0RUN IMC0D 1 X X X X X X X X X X X X 0 X 0 0 1 1 0 0 1 0 0 TB0FFCR TB0MOD TB0RG1 1 0 * * * TB0RUN 1 0 * * * 0 1 * * * 0 0 * * * 0 0 * * * 0 1 * * 1 1 * * * X 1 * * * 1 Starts the TMRB0 module. Stops TMRB0. Enables INTTB0, and sets it to level 4. (Setting of INTTB0 only is shown here. This is a 32-bit register and requires settings of other interrupts as well.) Disables the trigger. Designates the prescaler input clock as the output clock, and specifies the time interval. (16 bits * This is a 32-bit register.) Starts TMRB0. X; Don't care -; no change 11.5.2 16-bit Event Counter Mode By using an input clock as an external clock (TB1IN0 pin input), it is possible to make it the event counter. The up-counter counts up on the rising edge of TB1IN0 pin input. By capturing a value using software and reading the captured value, it is possible to read the count value. 7 TB1EN TB1RUN P2CR P2FC3 P2IE IMC0D 6 1 0 1 X X X X X X X X X X X 0 X X 0 - - - 0 0 0 - - - 1 1 1 5 - - - 1 1 1 4 3 2 Starts the TMRB0 module. Stops TMRB1. - - - 0 0 0 - - - 0 0 0 - - - 1 0 1 - - - 0 0 0 0 1 1 0 0 0 TB1FFCR TB1MOD TB1RUN 1 1 0 0 0 0 1 0 X X X X 0 0 X 0 1 1 1 0 X 1 0 1 Enables INTTB0, and sets it to level 4. (Setting of INTTB0 only is shown here. This is a 32-bit register and requires settings of other interrupts as well.) Disables the trigger. Designates the TB1IN0 pin input as the input clock. Starts TMRB1. TB1MOD TB1RG1 X X * * * * 0 * * 1 * * 0 * * 0 * * Captures a value using software. Specifies the time interval. (16 bits * This is a 32-bit register.) 0 * * 0 * * Sets P20 to the input mode. X; Don't care -; no change To be used as the event counter, put the prescaler in a "RUN" state (TB1RUN<TB1PRUN> = "1"). 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-19 2010-04-01 TMP19A44 11.5.3 16-bit PPG (Programmable Square Wave) Output Mode Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active. Programmable square waves can be output from the TB1OUT pin by triggering the timer flip-flop (TB1FF) to reverse when the set value of the up-counter (UC1) matches the set values of the timer registers (TB1RG0 and TB1RG1). Note that the set values of TB1RG0 and TB1RG1 must satisfy the following requirement: (Set value of TB1RG0) < (Set value of TB1RG1) Match with TB1RG0 (INTTB0 interrupt) Match with TB1RG1 (INTTB1 interrupt) TB1OUT pin Fig. 11.2 Example of Output of Programmable Square Wave (PPG) In this mode, by enabling the double buffering of TB1RG0, the value of register buffer 0 is shifted into TB1RG0 when the set value of the up-counter matches the set value of TB1RG1. This facilitates handling of small duties. Match with TB1RG0 Up-counter = Q1 Up-counter = Q2 Match with TB1RG1 TB1RG0 (compare value) Register buffer Trigger to shift to TB1RG1 Q1 Q2 Q2 Q3 Write TB1RG0 Fig. 11.3 Register Buffer Operation 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-20 2010-04-01 TMP19A44 TB1 IN0 T1 T4 T16 TB1RUN<TB0RUN> TB1OUT (PPG output) Selector 16-bit up-counter UC1 16-bit comparator Selector Match Clear F/F (TB1FF0) 16-bit comparator TB1RG0 TB1RG1 TB1RG0-W R TB1RUN<TB1RDE> Register buffer 1 Register buffer 0 Internal data bus Fig. 11.4 Block Diagram of 16-bit PPG Mode Each register in the 16-bit PPG output mode must be programmed as listed below. 1 0 TB1EN TB1RUN 1 X X X X X X X X X X X 0 X 7 6 5 4 3 2 X 0 TB1RG0 TB1CR * * * * 0 * * * * X * * * * 0 * * * * 0 * * * * 0 * * * * 0 * * * * 0 TB1FFCR X X 0 0 1 1 1 0 TB1MOD 0 1 0 0 1 * * - - - 0 (** = 01, 10, 11) 1 - - - - 1 - - - - 0 - - - - 0 - 1 X 1 TB1RG1 P5CR P5FC2 TB1RUN * * * * 1 - - - 1 0 - - - 0 Starts the TMRB1 module. Disables the TB1RG0 double buffering and stops TMRB1. Specifies a duty. (16 bits *This is a 32-bit register) Specifies a cycle. (16 bits *This is a 32-bit register) Enables the TB1RG0 double buffering. (Changes the duty/cycle when the INTTB1 interrupt is generated) Specifies to trigger TB1FF0 to reverse when a match with TB1RG0 or TB1RG1 is detected, and sets the initial value of TB1FF0 to "0." Designates the prescaler input clock as the output clock, and disables the capture function. Assigns P55 to TB1OUT. Starts TMRB1. X; Don't care -; no change 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-21 2010-04-01 TMP19A44 11.5.4 Timer Synchronization Mode The timers can be started synchronously by using the timer synchronization mode. The synchronization mode can be used for PPG output, for example, for application to driving a motor. TBnCR<TBnSYC> is used to turn the synchronization mode on/off. <TBnSYC> ="0": Operates the timers at the timing specified for each channel. <TBnSYC> ="1": Enables the synchronous output. There are five blocks, TMRB0 through TMRB3, TMRB4 through TMRB7, TMRB8 through TMRBB, TMRBC through TMRBF and TMRB10 through TMRB11. If <TBnSYC> is set to "1," the timers will not start at the timing specified for each channel by setting TBmRUN<TBmPRUN,TBmRUN> to "1,1", but the timers in each block will start in synchronization with TMRB0, TMRB4, TMRB8, TMRBC or TMRB10. (Note 1) For the channels to be output synchronously, set TBmRUN<TBmPRUN,TBmRUN> to "1,1" to enable simultaneous start before starting TMRB0, TMRB4, TMRB8, TMRBC or TMRB10. (Note 2) Set TBnCR<TBnSYC> to "0" unless the synchronous output mode is selected. When the synchronous output mode is selected, other channels will not start until TMRB0, 4 , 8, C and 10 start. Note) Master: TMRB0, TMRB4, TMRB8, TMRBC and TMRB10 write TBnSYC"0" TBnCR (0xFF00_4xx8) Bit symbol Read/Write After reset Function 7 TBnWBF 6 R/W 0 R/W 0 Double buffering 0: Disable 1: Enable Write "0." 5 TBnSYN C R/W 0 Synchroniza tion mode 0: Individual operation 4 3 2 1 0 R 0 R 0 I2TBn R 0 This can be read as "0." R/W R 0 0 This can IDLE be read 0:Stop as "0." 1:Operate This can be read as "0." This can be read as "0." 2 1 0 R 0 R 0 R 0 Slave: Write TBnSYC "1" 7 TBnCR (0xFFFF_4xx8) 6 5 R/W R/W TBnSYN C R/W R 0 0 0 0 Double buffering 0: Disable 1: Enable Write "0." Synchroniza tion mode 0: Individual operation Bit symbol TBnWEN Read/Write After reset Function 4 3 I2TBn This can be read as "0." R/W 0 IDLE 0:Stop 1:Operate 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-22 This can be read as "0." This can be read as "0." This can be read as "0." 2010-04-01 TMP19A44 11.6 Applications using the Capture Function The capture function can be used to develop many applications, including those described below: c One-shot pulse output triggered by an external pulse d Frequency measurement e Pulse width measurement f Time difference measurement c One-shot pulse output triggered by an external pulse One-shot pulse output triggered by an external pulse is carried out as follows: The 16-bit up-counter (UC6) is made to count up by putting it in a free-running state using the prescaler output clock. An external pulse is input through the TB6IN0 pin. A trigger is generated at the rising of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (TB6CP0). The INTC must be programmed so that an interrupt INT4 is generated at the rising of an external trigger pulse. This interrupt is used to set the timer registers (TB6RG0) to the sum of the TB6CP0 value (c) and the delay time (d), (c + d), and set the timer registers (TB6RG1) to the sum of the TB6RG0 values and the pulse width (p) of one-shot pulse, (c + d + p). In addition, the timer flip-flop control registers (TB6FFCR<TB6E1T1, TB6E0T1>) must be set to "11." This enables triggering the timer flip-flop (TB6FF0) to reverse when UC6 matches TB6RG0 and TB6RG1. This trigger is disabled by the INTTB6 interrupt after a one-shot pulse is output. Symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in Fig. 11.3. Put the counter in a free-running state Count clock (Internal clock) TB6IN0 pin input (External trigger pulse) c+d+p c+d c Taking data into the capture register (CAP6) INT4 generation INTTB6 generation Match with TB6RG0 INTTB6 generation Enable reverse Match with TB6RG1 Disable reverse when data is taken into CAP6 Enable reverse Timer output TB6OUT pin Delay time Pulse width (d) (p) Fig. 11.5 One-shot Pulse Output (With Delay) 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-23 2010-04-01 TMP19A44 Programming example: Output a 2-ms one-shot pulse triggered by an external pulse from the TB6IN0 pin with a 3-ms delay * Clock condition System clock : High speed (fc) High-speed clock gear : 1X (fc) Prescaler clock : fperiph/8 (fperiph fsys) Main programming 7 6 5 X X X X X X X X X X X X PACR PAFC3 PAPE PAIE 4 0 1 1 1 3 X X X X 2 X X X X 1 X X X X 0 X X X X 0 1 0 0 1 Puts to a free-running state Sets TB6IN0. Uses T1 for counting. TB6MOD X X 1 Takes data into TB6CP0 at the rising of TB6IN0 input TB6FFCR X X 0 0 0 0 1 0 Clears TB6FF0 to zero Disables TB6FF0 to reverse PBCR PBFC1 IMC01 IMC0F TB6RUN - - - - - - - - - - X 1 1 0 X X 1 1 0 X X X X X X 1 0 1 - - 0 0 X - - 0 0 1 TB0CP0 + 3 ms/T1 TB0RG0 + 2 ms/T1 X X - - 1 1 - - 1 1 Assigns PB2 pin to TB6OUT Enables INT0 and disables INTTB6 Starts TMRB6 INT4 programming TB6RG0 TB6RG1 TB6FFCR X X IMC0D 1 1 0 1 0 0 - - 0 0 - - Enables TB2FF0 to reverse when there is a match with TB6RG0, 1 Enables INTTB6 INTTB6 programming TB6FFCR IMC0D X X X X 1 1 0 0 0 0 Disables TB6FF0 to reverse when there is a match with TB6RG0, 1 Disables INTTB6 X; Don't care ;no change 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-24 2010-04-01 TMP19A44 If a delay is not required, TB6FF0 is reversed when data is taken into TB6CP0, and TB6RG1 is set to the sum of the TB6CPO value (c) and the one-shot pulse width (p), (c + p), by generating the INT4 interrupt. TB6FF0 is enabled to reverse when UC6 matches with TB6RG1, and is disabled by generating the INTTB6 interrupt. Count clock (Prescaler output clock) c+p c TB6IN0 input (External trigger pulse) Taking data into the capture register TB6CP0 INT4 generation INTTB6 generation Taking data into the capture register TB6CP1 Match with TB6RG1 Enable reverse Timer output TB6OUT pin Pulse width Enable reverse when data is taken into TB6CP0 (p) Disable reverse when data is taken into TB6CP1 Fig. 11.6 One-shot Pulse Output Triggered by an External Pulse (Without Delay) d Frequency measurement By using the capture function, the frequency of an external clock can be measured. To measure frequency, another 16-bit timer (TMRB0) is used in combination with the 16-bit event counter mode (TMRB0 reverses TB0FFCR to specify the measurement time). The TB3IN0 pin input is selected as the TMRB3 count clock to perform the count operation using an external input clock. TB3MOD<TB3CPM1:0> is set to "11." This setting allows a count value of the 16-bit UC0 up-counter to be taken into the capture register (TB3CP0) upon the rising of a timer flipflop (TB0FFCR) of the 16-bit timer (TMRB0), and an UC0 counter value to be taken into the capture register (TB3CP1) upon the falling of TB3FF of the 16-bit timer (TMRB0). A frequency is then obtained from the difference between TB0CP0 and TB0CP1 based on the measurement, by generating the INTTB3 16-bit timer interrupt. Count clock (TB3IN0 pin input) C1 C2 TB0OUT Taking data into TB3CP0 Taking data into TB3CP1 C1 C1 C2 C2 INTTB0 Fig. 11.7 Frequency Measurement For example, if the set width of TB3FF level "1" of the 16-bit timer is 0.5 s and if the difference between TB0CP0 and TB0CP1 is 100, the frequency is 100 / 0.5 s = 200 Hz. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-25 2010-04-01 TMP19A44 e Pulse width measurement By using the capture function, the "H" level width of an external pulse can be measured. Specifically, an external pulse is input through the TB0IN0 pin, and the up-counter (UC6) is made to count up by putting it in a free-running state using the prescaler output clock. A trigger is generated at each rising and falling edge of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (TB6CP0, TB6CP1). The INTC must be programmed so that INT4 is generated at the falling edge of an external pulse input through the TB6IN0 pin. The "H" level pulse width can be calculated by multiplying the difference between TB6CP0 and TB6CP1 by the clock cycle of an internal clock. For example, if the difference between TB6CP0 and TB6CP1 is 100 and the cycle of the prescaler output clock is 0.5 s, the "H" level pulse width is 100 x 0.5 s = 50 s. Caution must be exercised when measuring pulse widths exceeding the UC6 maximum count time which is dependant upon the source clock used. The measurement of such pulse widths must be made using software. Prescaler output clock C2 C1 TB6IN0 pin input (External pulse) Taking data into TB6CP0 C1 C1 C2 C2 Taking data into TB6CP1 INT4 Fig. 11.8 Pulse Width Measurement The "L" level width of an external pulse can also be measured. In such cases, the difference between C2 generated the first time and C1 generated the second time is initially obtained by performing the second stage of INT4 interrupt processing as shown in Fig. 11.78 and this difference is multiplied by the cycle of the prescaler output clock to obtain the "L" level width. 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-26 2010-04-01 TMP19A44 f Time Difference Measurement By using the capture function, the time difference between two events can be measured. Specifically, the up-counter (UC6) is made to count up by putting it in a free-running state using the prescaler output clock. The value of UC6 is taken into the capture register (TB6CP0) at the rising edge of the TB6IN0 pin input pulse. The INTC must be programmed to generate INT4 interrupt at this time. The value of UC6 is taken into the capture register TB6CP1 at the rising edge of the TB6IN1 pin input pulse. The INTC must be programmed to generate INT5 interrupt at this time. The time difference can be calculated by multiplying the difference between TB6CP1 and TB6CP0 by the clock cycle of an internal clock. Prescaler output clock C2 C1 TB6IN0 pin input TB6IN1 pin input Taking data into TB6CP0 Taking data into TB6CP1 INT4 INT5 Time difference Fig. 11.9 Time Difference Measurement 16-bit Timer/Event Counters (TMRBs) TMP19A44(rev1.3) 11-27 2010-04-01 TMP19A44 12. 32-bit Input Capture (TMRC) TMRC consists of one channel with a 32-bit time base timer (TBT), four channels (TCCAP0 through TCCAP3) each with a 32-bit input capture register, and eight channels (TCCMP0 through TCCMP7) each with a 32-bit compare register. Fig. 12.1 shows the TMRC block diagram. 12.1 TMRC Block Diagram Prescaler input clock (T0) 4 8 16 32 64 T2 T4 T8 T16 T32 128 256 512 T64 RUN & Clear T128 T256 Clear & count control circuit TBTIN (PC0) Noise removal circuit 32-bit time base timer (TBT) Prescaler output T2 through T256 Overflow interrupt (INTTBT) Capture registers 0 through 3 (TCCAP0 through TCCAP3) TC0IN (P32) Noise removal circuit Edge detection 32-bit input capture (TCCAP0) Capture 0 interrupt (INTCAP0) Compare registers 0 through 7 (TCCMP0 through TCCMP7) 32-bit register buffer 0 32-bit comparator Compare match interrupt 0 (INTCMP0) (INTCAPA) 32-bit compare register 0 (TCCMP0) Compare match trigger (CMP0TRG) Compare match output (TCOUT0) Fig. 12.1 Timer C Block Diagram 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-1 2010-04-01 TMP19A44 12.2 Description for Operations of Each Circuit 12.2.1 Prescaler The prescaler is provided to acquire the TMRC source clock. The prescaler input clock T0 is fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selected by SYSCR1<PRCK2:0> in the CG. T2 through T256 generated by dividing T0 are available as TMRC prescaler input clocks and can be selected with TBTCR<TBTCLK3:0>. Fperiph is either "fgear" which is a clock selected by SYSCR1<FPSEL> in the CG, or "fc" which is a clock before it is divided by the clock gear. The operation or stoppage of the prescaler is set with TBTRUN<TBTPRUN> where writing "1" starts counting and writing "0" clears and stops counting. Table 12-1 shows the prescaler output clock resolutions. 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-2 2010-04-01 TMP19A44 Select Clock gear peripheral clock value <FPSEL> <GEAR2:0> 0(fgear) 000(fc) Table 12-1 Prescaler Output Clock Resolutions Select prescaler Prescaler output clock resolution clock <PRCK2:0> 2 8 000(fperiph/2) 001(fperiph/4) 4 5 16 6 fc/2 (0.10s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/2 (0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/2 (0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/2 (0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/27(1.60s) fc/28(3.20s) fc/29(6.32s) fc/210(12.6s) fc/211(25.6s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.32s) fc/210(12.6s) fc/211(25.6s) fc/212(51.2s) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.32s) fc/210(12.6s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) 111(fc/16) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) fc/27(1.60s) fc/28(3.20s) 9 fc/2 (6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.6s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/23(0.10s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/23(0.10s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/24(0.20s) fc/25(0.40s) fc/26(0.80s) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 100(fc/2) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 101(fc/4) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 110(fc/8) 000(fperiph/2) 001(fperiph/4) 1(fc) 3 @fc = 80.0MHz 000(fc) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 100(fc/2) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 101(fc/4) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 110(fc/8) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 111(fc/16) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 32-bit Input Capture (TMRC) 4 5 fc/2 (0.20s) fc/25(0.40s) fc/26(0.80s) fc/27(1.60s) fc/2 (0.40s) fc/26(0.80s) fc/27(1.60s) fc/28(3.20s) fc/2 (0.80s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/25(0.40s) fc/26(0.80s) fc/26(0.80s) fc/27(1.60s) fc/25(0.40s) 5 6 6 fc/2 (0.40s) fc/26(0.80s) fc/27(1.60s) fc/2 (0.80s) fc/27(1.60s) fc/28(3.20s) fc/2 (1.60s) fc/28(3.20s) fc/29(6.40s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/26(0.80s) fc/26(0.80s) fc/27(1.60s) fc/27(1.60s) fc/28(3.20s) fc/26(0.80s) 6 fc/2 (0.80s) fc/27(1.60s) 7 fc/2 (1.60s) fc/28(3.20s) TMP19A44 (rev1.3) 12-3 7 8 fc/2 (3.20s) fc/29(6.40s) fc/29(6.40s) fc/210(12.8s) 2010-04-01 TMP19A44 Select peripheral clock <FPSEL> 0(fgear) Clock gear Select prescaler clock value <PRCK2:0> <GEAR2:0> 000(fc) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 100(fc/2) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 101(fc/4) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 110(fc/8) 000(fperiph/2) 001(fperiph/4) 1(fc) Prescaler output clock resolution 32 64 128 256 fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/215(409.6s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) 12 fc/2 (51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) 13 fc/2 (102.4s) fc/214(204.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) 14 fc/2 (204.8s) fc/215(409.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) 15 fc/2 (409.6s) fc/216(819.2s) 10 11 12 13 010(fperiph/8 011(fperiph/16) 100(fperiph/32) fc/2 (12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/2 (25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/215(409.6s) fc/2 (51.2s) fc/213(102.4s) fc/214(204.8s) fc/215(409.6s) fc/216(819.2s) fc/2 (102.4s) fc/214(204.8s) fc/215(409.6s) fc/216(819.2s) fc/217(1638.4s) 111(fc/16) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) fc/211(25.6s) fc/212(51.2s) 13 fc/2 (102.4s) fc/214(204.8s) fc/215(409.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/215(409.6s) fc/216(819.2s) fc/213(102.4s) fc/214(204.8s) fc/215(409.6s) fc/216(819.2s) fc/217(1638.4s) fc/214(204.8s) fc/215(409.6s) fc/216(819.2s) fc/217(1638.4s) fc/218(3276.8s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) 101(fc/4) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) 110(fc/8) 000(fperiph/2) 001(fperiph/4) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) fc/27(1.60s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/28(3.20s) fc/29(6.40s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/29(6.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/210(12.8s) fc/211(25.6s) fc/212(51.2s) fc/213(102.4s) fc/214(204.8s) 000(fc) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 100(fc/2) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 111(fc/16) 000(fperiph/2) 001(fperiph/4) 010(fperiph/8 011(fperiph/16) 100(fperiph/32) 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-4 2010-04-01 TMP19A44 (Note 1) Do not change the clock gear while the timer is operating. (Note 2) "-" denotes "setting prohibited." 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-5 2010-04-01 TMP19A44 12.2.2 Noise Removal Circuit The noise removal circuit removes noises from an external clock source input (TBTIN) and a capture trigger input (TcnIN) of the time base timer (TBT). It can also output input signals without removing noises from them. 12.2.3 32-bit Time Base Timer (TBT) This is a 32-bit binary counter that counts up upon the rising of an input clock specified by the TBT control register TBTCR of the time base timer. Based on the TBTCR<TBTCLK3:0> setting, an input clock is selected from external clocks supplied through the TBTIN pin and eight prescaler output clocks T2, T4, T8, T16, T32, T64, T128, and T256. "Count," "stop" or "clear" of the up-counter can be selected with TBTRUN<TBTRUN>. When a reset is performed, the up-counter is in a cleared state and the timer is in an idle state. As counting starts, the up-counter operates in a free-running condition. As it reaches an overflow state, the overflow interrupt INTTBT is generated; subsequently, the count value is cleared to 0 and the up-counter restarts a countup operation. This counter can perform a read capture operation. 12.2.4 Edge Detection Circuit By performing sampling, this circuit detects the input edge of an external capture input (TcnIN). It can be set to "rising edge," "falling edge," "both edges" or "not capture" by provisioning the capture control register CAPnCR<CPnEG1:0>. Fig. 12.2 shows capture inputs, outputs (capture factor outputs) produced by the edge detection circuit, and specific detection circuit settings. TCnIN input Capture factor (Rising edge setting) (Falling edge setting) (Both-edge setting) (Not capture setting) Fig. 12.2 Capture Inputs and Capture Factor Outputs (Outputs Produced by the Edge Detection Circuit) 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-6 2010-04-01 TMP19A44 12.2.5 32-bit Capture Register This is a 32-bit register for capturing count values of the time base timer by using capture factors as triggers. If a capture operation is performed, the capture interrupt INTCAPn is generated. Four interrupt requests INTCAP0 through INTCAP3 are then notified to the interrupt controller. 12.2.6 32-bit Compare Register This is a 32-bit register for specifying a compare value. TMRC has eight built-in compare registers, TCCMP0 through TCCMP7. If values set in these compare registers match the value of the time base timer TBT, the match detection signal of a comparator becomes active. "Compare enable" or "compare disable" can be specified with the compare control register CMPCTL<CMPENn>. Each compare register has a double-buffer structure, that is, TCCMPn forms a pair with a register buffer "n." "Enable" or "disable" of the double buffers is controlled by the compare control register CMPCTL <CMPRDEn>. If <CMPRDEn> is set to "0," the double buffers are disabled. If <CMPRDEn> is set to "1," they are enabled. If the double buffers are enabled, data transfer from the register buffer "n" to the compare register TCCMPn takes place when the value of TBT matches that of TCCMPn. Because TCCMPn is indeterminate when a reset is performed, it is necessary to prepare and write data in advance. A reset initializes CMPCTL <CMPRDEn> to "0" and disables the double buffers. To use the double buffers, data must be written to the compare register, <CMPRDEn> must be set to "1," and then the following data must be written to the register buffer. TCCMPn and the register buffer are assigned to the same address. If <CMPRDEn> is "0," the same value is written to TCCMPn and each register buffer. If <CMPRDEn> is "1," data is written to each register buffer only. Therefore, to write an initial value to the compare register, it is necessary to set the double buffers to "disable." 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-7 2010-04-01 TMP19A44 12.3 Register Description TMRC Enable Register TCEN (0xFF00_4A00) bit Symbol Read/Writ e After reset 7 TCEN 5 4 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 R/W R 0 0 TMRC operation Function 6 0: Disable 1: Enable 15 "0" is read. 14 13 12 bit Symbol Read/Writ e After reset R 0 23 22 21 20 bit Symbol Read/Writ e After reset R 0 31 bit Symbol Read/Writ e After reset 30 29 28 R 0 <TCEN>: Specifies enabling/disabling of the TMRC operation. If set to "disable," a clock is not supplied to other registers of the TMRC module and, therefore, a reduction in power consumption is possible (a read of or a write to other registers cannot be executed). To use TMRC, the TMRC operation must be set to "enable" ("1") before making individual register settings of TMRC modules. If TMRC is operated and then set to "disable," individual register settings are retained. 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-8 2010-04-01 TMP19A44 TMRC RUN Register 7 TBTRUN (0xFF00_4A04) bit Symbol Read/Writ e After reset 6 I2TBT 5 4 R R/W R 0 0 0 "0" is read. Function 15 13 2 TBTCAP 1 TBTPRUN 0 TBTRUN R/W 0 IDLE "0" is read. 0:Stop 1:Operati on 14 3 0 Ensure TBT this is set counter to "0". software capture 0: D'ont Care 1: Software capture 12 bit Symbol Read/Writ e After reset 0 0 TimerRun/Stop Control 0: Stop & clear 1: Count 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Writ e After reset R 0 31 30 29 28 bit Symbol Read/Writ e After reset R 0 <TBTRUN> : Controls the TBT count operation. <TBTPRUN> : Controls the TBT prescaler operation. <TBTCAP>: If this is set to "1," the count value of the time base timer (TBT) is taken into the capture register TBTCAPn. <I2TBT> : Controls the TMRC operation in IDLE mode. Fig. 12.3 TMRC-related Registers 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-9 2010-04-01 TMP19A44 TMRC Control Register TBTCR (0xFF00_4A08) bit Symbol Read/Writ e After reset 7 TBTNF 6 5 4 0 0 0 0 TBTIN input noise removal Function 3 TBTCLK 3 R/W 13 0 TBTCLK0 0 0 0 TBT source clock Ensure to write "0". 14 1 TBTCLK 1 0 0000: T2 0001: T4 0010: T8 0011: T16 0100: T32 0101: T64 0110: T128 0111: T256 1111: TBTIN pin input 11 10 9 8 0:2/fsys or more 1:6/fsys or more 15 2 TBTCLK 2 12 bit Symbol Read/Writ e After reset 0 R 23 22 21 20 bit Symbol Read/Writ e After reset 19 18 17 16 27 26 25 24 R 0 31 bit Symbol Read/Writ e After reset 30 29 28 R 0 <TBTCLK3:0>: This is an input clock for TBT. Clocks from "0000" to "0111" are available as prescaler output clocks. A clock "1111" is input through the TBTIN pin. <TBTNF>: Controls the noise removal for the TBTIN pin input. If this is set to "0" (removal disabled), any input of more than 2/fsys (25ns@fperiph=fc=80MHz) is accepted as a source clock for TBT, at whichever level the TBTIN pin is, "H" or "L." If this is set to "1" (removal enabled), any input of less than 6/fsys (75ns@fperiph=fc=80MHz) is regarded as noise and removed, at whichever level the TBTIN pin is, "H" or "L." The range of removal changes depending on the selected clock gear and a system clock used. 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-10 2010-04-01 TMP19A44 TBT Capture Register TBTCAP (0xFF00_4A0C) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 7 CAP07 6 CAP06 5 CAP05 4 CAP04 3 CAP03 2 CAP02 1 CAP01 0 CAP00 0 0 0 0 0 0 0 0 14 CAP14 13 CAP13 12 CAP12 11 CAP11 10 CAP10 9 CAP09 8 CAP08 R Capture data 15 CAP15 R 0 0 0 0 0 0 0 0 23 CAP23 22 CAP22 21 CAP21 20 CAP20 19 CAP19 18 CAP18 17 CAP17 16 CAP16 0 0 0 0 0 0 0 0 30 CAP30 29 CAP29 28 CAP28 27 CAP27 26 CAP26 25 CAP25 24 CAP24 0 0 0 0 Capture data R Capture data 31 CAP31 R 0 0 0 0 Capture data Fig. 12.4 TMRC-related Registers TBTRead Capture RegisterTBTRDCAP TBTRDCAP (0xFF00_4A10) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 0 RDCAP0 RDCAP0 RDCAP0 RDCAP0 RDCAP0 RDCAP0 RDCAP0 RDCAP0 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 Capture data 15 14 13 12 11 10 9 8 RDCAP1 RDCAP1 RDCAP1 RDCAP1 RDCAP1 RDCAP1 RDCAP0 RDCAP0 5 4 3 2 1 0 9 8 R 0 0 0 0 0 0 0 0 Capture data 23 22 21 20 19 18 17 16 RDCAP2 RDCAP2 RDCAP2 RDCAP2 RDCAP1 RDCAP1 RDCAP1 RDCAP1 3 2 1 0 9 8 7 6 R 0 0 0 0 0 0 0 0 Capture data 31 30 29 28 27 26 25 24 RDCAP3 RDCAP3 RDCAP2 RDCAP2 RDCAP2 RDCAP2 RDCAP2 RDCAP2 1 0 9 8 7 6 5 4 R 0 0 0 0 0 0 0 0 Capture data Fig. 12.5 TMRC-related Registers 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-11 2010-04-01 TMP19A44 TMRC Capture Control Register CAP0CR (0xFF00_4Ax0) bit Symbol Read/Write After reset Function 7 TC0NF R/W 0 6 TC0IN input noise removal "0" is read. 5 4 3 2 R 0 Select effective edge of TC0IN input 00: Not captured 01: Rising edge 10: Falling edge 11: Both edges 0:2/fsys or more 1:6/fsys or more 15 14 1 0 CP0EG1 CP0EG0 R/W 0 0 13 12 bit Symbol Read/Write After reset 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 bit Symbol Read/Write After reset 30 29 28 R 0 <CP1EG1:0>: Selects the effective edge of an input to the trigger input pin TC1IN of the capture 1 register (TCCAP1). If this is set to "00," the capture operation is disabled. <TC1NF>: Controls the noise removal for the TC1NF pin input. If this is set to "0" (removal disabled), any input of more than 2/fsys (25ns@fperiph=fc=80MHz) is accepted as a trigger input for TCCAP1, at whichever level TC1IN pin is, "H" or "L." If this is set to "1" (removal enabled), any input of less than 6/fsys (75ns@fperiph=fc=80MHz) is regarded as noise and removed, at whichever level the TC1IN pin is, "H" or "L." The range of removal changes depending on the selected clock gear and a system clock used. Fig. 12.6 TMRC-related Registers 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-12 2010-04-01 TMP19A44 TMRC Capture 0 Register (TCCAP0) TCCAP0 (0xFF00_4Ax4) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 7 6 5 4 3 2 1 CAP007 CAP006 CAP005 CAP004 CAP003 CAP002 CAP001 CAP000 R 0 0 0 0 0 0 0 0 15 CAP015 14 CAP014 13 CAP013 12 CAP012 11 CAP011 10 CAP010 9 CAP009 8 CAP008 0 0 0 0 0 0 0 0 22 CAP022 21 CAP021 20 CAP020 19 CAP019 18 CAP018 17 CAP017 16 CAP016 Capture 0 data R Capture 0 data 23 CAP023 R 0 0 0 0 0 0 0 0 31 CAP031 30 CAP030 29 CAP029 28 CAP028 27 CAP027 26 CAP026 25 CAP025 24 CAP024 0 0 0 0 0 0 0 0 Capture 0 data R Capture 0 data 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-13 2010-04-01 TMP19A44 TMRC Compare Control Register (CMPCTL) 7 CMPCTL0 bit Symbol (0xFF00_4Ax0) Read/Write After reset R 0 "0" is read. Function 15 6 5 4 TCFFEN TCFFC01 TCFFC0 0 0 R/W R/W 0 1 1 TCFF0 reversal 0:Disable 1:Enable 14 TCFF0 control 00:Reversal 01:Set 10:Clear 11:D'ont care 13 2 1 CMPRDE0 R 0 "0" is read. 12 bit Symbol Read/Write After reset 0 CMPEN0 R/W 0 Double buffer 0 0:Disable 1:Enable 0 Compare 0 enable 0:Disable 1:Enable 11 10 9 8 19 18 17 16 27 26 25 24 R 0 23 22 21 20 bit Symbol Read/Write After reset R 0 31 bit Symbol Read/Write After reset <CMPENn>: 3 30 29 28 R 0 Controls enabling/disabling of the compare match detection. <CMPRDEn>: Controls enabling/disabling of double buffers of the compare register. <TCFFCn1:0>: Controls F/F of the compare match output. <TCFFENn>: Controls enabling/disabling of F/F reversal of the compare match output. Fig. 12.7 TMRC-related Registers 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-14 2010-04-01 TMP19A44 TMRC Compare Register (TCCMP0) TCCMP0 (0xFF00_4Ax4) bit Symbol Read/Writ e After reset Function bit Symbol Read/Writ e After reset Function bit Symbol Read/Writ e After reset Function bit Symbol Read/Writ e After reset Function 7 CMP007 6 CMP006 5 CMP005 4 CMP004 3 CMP003 2 CMP002 1 CMP001 0 CMP000 R/W 0 0 0 0 0 0 0 0 13 CMP013 12 CMP012 11 CMP011 10 CMP010 9 CMP009 8 CMP008 Compare register 0 data 15 CMP015 14 CMP014 R/W 0 0 0 0 0 0 0 0 21 CMP021 20 CMP020 19 CMP019 18 CMP018 17 CMP017 16 CMP016 Compare register 0 data 23 CMP023 22 CMP022 R/W 0 0 0 0 0 0 0 0 29 CMP029 28 CMP028 27 CMP027 26 CMP026 25 CMP025 24 CMP024 0 0 0 Compare register 0 data 31 CMP031 30 CMP030 R/W 0 0 0 0 0 Compare register 0 data 32-bit Input Capture (TMRC) TMP19A44 (rev1.3) 12-15 2010-04-01 TMP19A44 13 Two-phase Pulse Input Counter (PHCNT) Each of the six channels (PHCNT0 through PHCNT5) has a two-phase input counter. (The six channels operate in the same way. This section describes PHCNT0 only.) In this mode, the counter is incremented or decremented by one depending on the state transition of the two-phase clock that is input through PHC0IN0 and PHC0IN1 and has phase difference. An interrupt is output when a counter overflow or underflow occurs in the up-and-down counter mode, and when the counting operation is executed. Interrupt is output in the ups and downs counter mode by the count operation. There are two counting operation modes, which are switched by the register setting. 1) Normal operation mode (up/down at the fourth count) 2) Quadruple mode (up/down at each count) 13.1 Overview 1) PHCNT incorporates 16-bit up-and-down counter of which default value is 0x7fff. 2) PHCNT counts up or down according to the combination of asynchronous two-phase pulse inputs. 3) Two-phase pulse input pins incorporate a noise filter that can be enabled or disabled. 4) Counting mode is selectable from normal mode or quadruple mode. 5) PHCNT can control generation of two kinds of compare interrupts and an interrupt that occurs by each count. 6) The control register can control an interrupt output. 7) The status register can distinguish an overflow interrupt, an underflow interrupt and a compare interrupt. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-1 2010-05-10 TMP19A44 Table 13.1 PHCNT Registers Channel Two-phase pulse input pin PHC0IN0 External pin PHCNT1 PHCNT0 Specification (shared with PHC1IN0 PA0) PHC0IN1 (shared PHCNT2 with PHC2IN0 PA2) (shared with PHC1IN1 PA1) (shared with (shared with PA6) (shared with PHC2IN1 PA3) PA7) Timer RUN register PHC0RUN (0xFF00_1600) PHC1RUN (0xFF00_1640) PHC2RUN (0xFF00_1680) Timer control register PHC0CR (0xFF00_1604) PHC1CR (0xFF00_1644) PHC2CR (0xFF00_1684) PHC0EN (0xFF00_1608) PHC1EN (0xFF00_1648) PHC2EN (0xFF00_1688) Register Timer mode register Timer flip-flop control names PHC0FLG (0xFF00_160C) PHC1FLG (0xFF00_164C) PHC2FLG (0xFF00_168C) (addresses register Timer register PHC0CMP0 (0xFF00_1610) PHC1CMP0 (0xFF00_1650) PHC2CMP0 (0xFF00_1690) ) Capture register PHC0CMP1 (0xFF00_1614) PHC1CMP1 (0xFF00_1654) PHC2MP1 (0xFF00_1694) Count read register PHC0CNT (0xFF00_1618) PHC1CNT (0xFF00_1658) PHC2CNT (0xFF00_1698) PHCNT3 PHCNT4 PHCNT5 PHC3IN0 (shared with PHC4IN0 (shared with PI0) PHC5IN0 (shared with PI1) Channel Specification External clock/ External capture trigger pins pin input PB0) PHC4IN1 (shared with PI1) PHC5IN1 (shared with PI2) PHC3IN1 (shared with PB1) Timer RUN register PHC3RUN (0xFF00_16C0) PHC4RUN (0xFF00_1700) PHC5RUN (0xFF00_1740) Timer control register PHC3CR (0xFF00_16C4) PHC4CR (0xFF00_1704) PHC5CR (0xFF00_1744) PHC3EN (0xFF00_16C8) PHC4EN (0xFF00_1708) PHC5EN (0xFF00_1748) Register Timer mode register Timer flip-flop control names PHC3FLG (0xFF00_16CC) PHC4FLG (0xFF00_170C) PHC5FLG (0xFF00_174C) (addresses register Timer register PHC3CMP0 (0xFF00_16D0) PHC4CMP0(0xFF00_1710) PHC5CMP0 (0xFF00_1750) ) Capture register PHC3CMP1 (0xFF00_16D4) PHC4CMP1(0xFF00_1714) PHC5CMP1 (0xFF00_1754) Count read register PHC3CNT (0xFF00_16D8) PHC4CNT (0xFF00_1718) Two-phase Pulse Input Counter (PHCNT) PHC5CNT (0xFF00_1758) TMP19A44(rev1.3)13-2 2010-05-10 TMP19A44 13.2 Block Diagram (PHCNT0) phcintout interrupt output PHCNTIN0 PHCNTIN1 PHINT External input buffer PHCCMP0 comparator phcntin0 phcntin1 CMP0 CMP1 PHCCMP0 PHCCMP1 udevryint srcntin PHCFLG PHCCNT counter Counter control Status OVF UDF register PHCRUN EVRYINT CMP1EN CMP0EN NFOFF PHCMD PHCRUN register PHCCR PHCEN Control register PHCEN Timer enable register Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-3 2010-05-10 TMP19A44 13.3 Operation Mode Counting mode is selected from normal mode or quadruple mode according to PHCMD of the control register (PHCCR). The counter is incremented or decremented by one depending on the state transition of the asynchronous two-phase pulse that is input through PHCNTIN0 and PHCNTIN1. An interrupt can be generated by each count or when counter value matches with a value set in the compare register 0 or 1. The timing to generate an interrupt is selectable with the control register. 1) Normal mode Count up (a) Count value is incremented by one when "2" is input at the previous clock and the current state is "3". (b) Count value is cleared when "3" is input at the previous clock and the current state is "2". (c) Count value is set when "3" is input at the previous clock and the current state is "1". PHCN0IN1 PHCN0IN0 3 1 0 2 3 After (b) is executed, (a) is not executed unless (c) is executed. UP1 set clr Count down (a) Count value is decremented by one when "1" is input at the previous clock and the current state is "3". (b) Count value is cleared when "3" is input at the previous clock and the current state is "1". (c) Count value is set when "3" is input at the previous clock and the current state is "2". PHCN0IN1 PHCN0IN0 3 2 0 3 1 DOWN1 set Two-phase Pulse Input Counter (PHCNT) clr After (b) is executed, (a) is not executed unless (c) is executed. TMP19A44(rev1.3)13-4 2010-05-10 TMP19A44 2) Quadruple mode Count up Count value is incremented by one when: "3" is input at the previous clock and the current state is "1". "1" is input at the previous clock and the current state is "0". "0" is input at the previous clock and the current state is "2". "2" is input at the previous clock and the current state is "3". PHCNTIN1 PHCNTIN0 3 1 0 3 2 Count value incremented by one at each edge Count down Count value is decremented by one when: "3" is input at the previous clock and the current state is "2". "2" is input at the previous clock and the current state is "0". "0" is input at the previous clock and the current state is "1". "1" is input at the previous clock and the current state is "3". PHCNTIN1 PHCNTIN0 3 2 0 1 3 Count value decremented by one at each edge Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-5 2010-05-10 TMP19A44 13.4 Registers 13.4.1 RUN register (PHCnRUN) PHCnRUN (0xFF00_1xx0) 7 6 5 bit Symbol 4 3 2 1 0 PHCnRU N Read/Write R R/W After reset 0 Function 0 "0" can be read. 15 14 13 12 11 Read/Write R After reset 0 Function Timer control 0:Stop 1:Run 10 9 8 18 17 16 26 25 24 "0" can be read. 23 22 21 20 Read/Write 19 R After reset 0 Function "0" can be read. 31 30 29 Read/Write After reset Function 28 27 R 0 "0" can be read. <PHCnRUN>: Controls PHCNTn count operation. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-6 2010-05-10 TMP19A44 13.4.2 Control register (PHCnCR) PHCnCR (0xFF00_1xx4) 7 6 5 4 3 2 1 0 CMP1EN n CMP0EN n NFOFFn PHCMDn R/W bit Symbol EVRYINT n Read/Write R R/W R/W R/W R/W After reset 0 0 0 0 0 0 Noise filter 0: No use Mode switch-ov er 0: Normal Function "0" can be read. Interrupt Compare Compare by interrupt 1 interrupt 0 count 0:Disabled 0:Disabled 0:Disabled 1:Enabled 1:Enabled 11 10 9 8 18 17 16 26 25 24 each 1: Use 1: 1:Enabled 15 14 13 Quadruple 12 Read/Write R After reset 0 Function "0" can be read. 23 22 21 20 Read/Write 19 R After reset 0 Function "0" can be read. 31 30 Read/Write After reset Function 29 28 27 R 0 "0" can be read. <PHCMD>: Controls mode switching. 0: normal mode...an interrupt is generated when count-up or count-down is selected. :quadruple mode... an interrupt is generated by each count. <NFOFF>: Controls noise cancellation. <CMP0EN>: Generates an interrupt if counter value matches with a value set in the compare register 0. <CMP1EN>: Generates an interrupt if counter value matches with a value set in the compare register 1. <EVRYINT>: Controls interrupt generation. Enables to prohibit generating an interrupt by each count when using a compare interrupt. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-7 2010-05-10 TMP19A44 13.4.3 Timer Enable Register (PHCnEN) PHCnEN (0xFF00_1xx8) 7 6 5 4 3 2 1 0 bit Symbol - PHCnEN Read/Write R R/W After reset 0 Function 0 "0" can be read. Timer operation 0:Disable d 1:Enabled 15 14 13 12 Read/Write 11 10 9 8 18 17 16 26 25 24 R After reset 0 Function "0" can be read. 23 22 21 20 Read/Write 19 R After reset 0 Function "0" can be read. 31 30 Read/Write After reset Function 29 28 27 R 0 "0" can be read. <PHCEN>: Enables or disables PHCEN operation. Disabling PHCEN operation stops providing register clock to other registers of PHCNT module, and it can reduce power consumption. (Neither reading nor writing is enabled with other registers). To use PHCNT, enable PHCNT by setting this bit to "1" before setting other PHCNT registers. When disabling PHCNT after temporary operation, setting in each register is kept. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-8 2010-05-10 TMP19A44 13.4.4 Status register (PHCnFLG) PHCnFLG (0xFF00_1xxC) 3 2 1 0 bit Symbol 7 6 UDFn OVFn CMPn1 CMPn0 Read/Write R R/W R/W R/W R/W After reset Function 5 4 0 0 "0" can be read. 0 0 Underflow Overflow An interrupt An interrupt interrupt interrupt generated if generated if there is a there 0: 0 Not 0: Not 14 13 12 Read/Write a generated match with match 1: 1: compare compare Generated Generated register 1 register 0 0: 0: Not 11 with Not generated generated 1: 1: Generated 15 is generated Generated 10 9 8 18 17 16 26 25 24 R After reset 0 Function "0" can be read. 23 22 21 20 19 Read/Write R After reset 0 Function "0" can be read. 31 30 Read/Write After reset Function 29 28 27 R 0 "0" can be read. * These bits are not automatically cleared. Initialize them before use. Writing "1" to each bit clears its flag. <CMP0>: Flag for an interrupt generated if there is a match with compare register 0 (PHCCMP0) <CMP1>: Flag for an interrupt generated if there is a match with compare register 1 (PHCCMP1) <OVF> : Flag for an overflow interrupt of an up-and-down counter. <UDF> : Flag for an underflow interrupt of an up-and-down counter. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-9 2010-05-10 TMP19A44 13.4.5 Compare register 0 (PHCnCMP0) PHCnCMP0 (0xFF00_1xx0) 7 6 5 4 bit Symbol 3 2 1 0 10 9 8 18 17 16 26 25 24 2 1 0 10 9 8 18 17 16 26 25 24 PHCCMP0 Read/Write R/W After reset 0x00 Function Set compare value. 15 14 13 12 11 bit Symbol PHCCMP0 Read/Write R/W After reset 0x00 Function Set compare value. 23 22 21 20 Read/Write 19 R After reset 0 Function "0" can be read. 31 30 29 28 27 Read/Write R After reset 0 Function "0" can be read. 13.4.6 Compare register 1 (PHCnCMP1) PHCnCMP1 (0xFF00_1xx4) 7 6 5 bit Symbol 4 3 PHCCMP1 Read/Write R/W After reset 0x00 Function Set compare value. 15 14 13 bit Symbol 12 11 PHCCMP1 Read/Write R/W After reset 0x00 Function Set compare value. 23 22 21 20 Read/Write 19 R After reset 0 Function "0" can be read. 31 30 29 28 27 Read/Write R After reset 0 Function "0" can be read. * By using both PHCnCMP0 and PHCnCMP1, up to two compare values can be set. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-10 2010-05-10 TMP19A44 13.4.7 Counter Read Register (PHCnCNT) PHCnCNT (0xFF00_1xx8) 7 6 5 4 bit Symbol 3 2 1 0 10 9 8 18 17 16 26 25 24 PHCCNT Read/Write R After reset 0x00 Function Data read from counter 15 14 13 12 11 bit Symbol PHCCNT Read/Write R After reset 0x00 Function Data read from counter 23 22 21 20 Read/Write 19 R After reset 0 Function "0" can be read. 31 30 29 28 27 Read/Write R After reset 0 Function "0" can be read. * Reading twice is recommended. This register is initialized when the RUN register is cleared to "0". Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-11 2010-05-10 TMP19A44 13.5 Up-and-down counter When starting the two-phase input count (PHCRUN<PHCRUN> = "1"), the up-counter is initialized to 0x7FFF and becomes ready for receiving counts. If a counter overflow occurs, the counter returns to 0x0000. If a counter underflow occurs, the counter returns to 0xFFFF. After that, the counter continues the counting operation. Therefore, the state can be checked by reading the counter value and the status flag PHCFLG after an interrupt is generated. Up-count input Up-and-down counter value 0x3FFF 0x4000 0x4001 Up-and-down interrupt (Note 1) The up (down) count input must be set to the "H" level for the states before and after an input. (Note 2) Reading of counter value must be executed during PHCNT0 interrupt handling. 13.6 Interrupt * In the NORMAL or SLOW mode The PHCNT0 interrupt is enabled using the interrupt controller (INTC). The PHCNT0 interrupt is generated by counting up or down. Reading the status register PHCFLG during interrupt handling allows simultaneous check for occurrences of an overflow and an underflow. If PHCnFLG<OVFn> is "1," it indicates that an overflow has occurred. If <UDFn> is "1," it indicates that an underflow has occurred. This register is cleared after "1" is written. The counter becomes 0x0000 when an overflow occurs, and it becomes 0xFFFF when an underflow occurs. After that, the counter continues the counting operation. * In the SLEEP/ backup SLEEP mode The two-phase input pulse input counter operates. The PHCNT0 interrupt is generated by the count-up or count-down input, and the system recovers from the SLEEP mode. Reading the status register PHCFLG during interrupt handling allows simultaneous check for occurrences of an overflow, an underflow and a compare interrupt. This register is cleared after "1" is written. The counter becomes 0x0000 when an overflow occurs, it and becomes 0xFFFF when an underflow occurs. After that, the counter continues the counting operation. Two-phase Pulse Input Counter (PHCNT) TMP19A44(rev1.3)13-12 2010-05-10 TMP19A44 14. Serial Channel (SIO) 14.1 Features This device has three serial I/O channels: SIO0 to SIO2. 14.1.1 Operation Modes Four operation modes (mode 0 through mode 3) are provided to SIO. Table 14.1 shows data format of each mode. Table 14.1 Data Format Mode Mode 0 Mode 1 Mode 2 Mode 3 Type Synchronous mode (I/O interface mode) Asynchronous mode (UART mode) Data length Transfer Add parity Stop bit length (transfer) 8 bit LSB first or MSB first x 7 bit 8 bit 9 bit LSB first x 1 or 2 Mode 0 is to send and receive I/O data and associated synchronization signals (SCLK) to extend I/O. SCLK can be used for input and output. You can select either of LSB or MSB to send first. Neither adding parity nor stop bit is available. Modes 1 through 3 execute asynchronous communication and are designed to send LSB first. In the modes 1 and 2, parity bits can be added. The mode 3 has a wakeup function in which the master controller can start up slave controllers via the serial link (multi-controller system). Stop bit length at transmission can be selected from 1 bit or 2 bits. At reception, stop bit is 1 bit. Hereinafter synchronous mode is referred to as I/O interface mode, asynchronous mode is referred to as UART mode or 7 bit/ 8 bit/ 9 bit UART mode, which includes TX/RX data length. Serial Channel (SIO) TMP19A44(rev1.3) 14-1 2010-04-01 TMP19A44 14.1.2 Data Format Table 14.1 shows data format of each mode. z Mode 0 (I/O interface mode)/LSB first bit 0 1 2 3 4 5 6 7 3 2 1 0 Transmission direction z Mode 0 (I/O interface mode)/MSB first bit 7 6 5 4 Transmission direction z Mode 1 (7-bit UART mode) Without parity start bit 0 1 2 3 4 5 6 stop start bit 0 1 2 3 4 5 6 parity stop With parity z Mode 2 (8-bit UART mode) Without parity start bit 0 1 2 3 4 5 6 7 stop start bit 0 1 2 3 4 5 6 7 parity stop With parity z Mode 3 (9-bit UART mode) start bit 0 1 2 3 4 5 6 7 8 start bit 0 1 2 3 4 5 6 7 bit 8 stop Stop (wake-up) If bit 8 =1, represents address (select code). If bit 8 =0, represents data. Fig. 14.1 Data Format Serial Channel (SIO) TMP19A44(rev1.3) 14-2 2010-04-01 TMP19A44 14.2 Block Diagram (Channel 0) Fig. 14.2 shows the block diagram of SIO0. Each channel consists of a prescaler, a serial clock generation circuit, a receive buffer and its control circuit, and a send buffer and its control circuit. Each channel functions independently. T0 2 4 T1 Prescaler 8 16 32 64 128 T4 T64 T16 Serial clock generation circuit TB0OUT (from TMRB0) BR0CR <BR0CK1, 0> BR0CR <BR0ADDE> Baud rate generator SC0MOD0 <SC1, 0> Selector fSYS/2 /2 SCLK0 input (shares P62) SCLK0 output (shares P62) SIOCLK SC0MOD0 <SM1, 0> I/O interface mode SC0CR <IOC> I/O interface mode Receive counter (16 only with UART) UART Mode Selector Divider Selector T1 T4 T16 T64 BR0ADD <BR0K3:0> Selector BR0CR <BR0S3:0> Interrupt request (INTRX0) SC0MOD0 <WU> Serial channel interrupt control RXDCLK SC0MOD0 <RXE> Receive control Interrupt request (INTTX0) Transmit counter (16 only with UART) TXDCLK Transmit control SC0CR <PE> <EVEN> CTS0 (shares P62) SC0MOD0 <CTSE> Parity control RXD0 (shares P61) Receive buffer 1 (shift register) RB8 Receive buffer 2 (SC0BUF) FIFO control Internal data bus Send buffer 1 (shift register) Error flag TB8 SC0CR <OERR><PERR><FERR> Internal data bus TXD0 (shares P60) Send buffer 2 (SC0BUF) FIFO control Internal data bus Fig. 14.2 SIO0 Block Diagram Serial Channel (SIO) TMP19A44(rev1.3) 14-3 2010-04-01 TMP19A44 14.2.1 Baud Rate Generator The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate. The baud rate generator uses either the T1, T4, T16 or T64 clock supplied from the 7-bit prescaler. This input clock selection is made by setting the baud rate setting register, BR0CR <BR0CK1:0>. The baud rate generator contains built-in dividers for divide by 1, (N + m/16), and 16 where N is a number from 2 to 15 and m is a number from 0 to 15. The division is performed according to the settings of the baud rate control registers BR0CR <BR0ADDE> <BR0S3:0> and BR0ADD <BR0K3:0> to determine the resulting transfer rate. * UART Mode: 1) If BR0CR <BR0ADDE> = 0, The setting of BR0ADD <BR0K3:0> is ignored and the counter is divided by N where N is the value set to BR0CR <BR0S3:0>. (N = 1 to 16). 2) If BR0CR <BR0ADDE> = 1, The N + (16 - K)/16 division function is enabled and the division is made by using the values N (set in BR0CR <BR0S3:0>) and K (set in BR0ADD<BR0K3:0>). (N = 2 to 15, K = 1 to 15) Note * For the N values of 1 and 16, the above N+(16-K)/16 division function is inhibited. So, be sure to set BR0CR<BR0ADDE> to "0." I/O interface mode: The N + (16 - K)/16 division function cannot be used in the I/O interface mode. Be sure to divide by N, by setting BR0CR <BR0ADDE> to "0." * Baud rate calculation to use the baud rate generator: 1) UART mode Baud rate = Baud rated generator input clock /16 Frequency divided by the divide ratio The highest baud rate out of the baud rate generator is 625 kbps when T1 is 20 MHz. The fsys/2 frequency, which is independent of the baud rate generator, can be used as the serial clock. In this case, the highest baud rate will be 2.5 Mbps when fsys is 80 MHz. 2) I/O interface mode Baud rate = Baud rated generator input clock /2 Frequency divided by the divide ratio The highest baud rate will be generated when T1 is 20 MHz. If double buffering is used, the divide ratio can be set to "1" and the resulting output baud rate will be 10 Mbps. (If double Serial Channel (SIO) TMP19A44(rev1.3) 14-4 2010-04-01 TMP19A44 buffering is not used, the highest baud rate will be 5 Mbps applying the divide ratio of "2.") * Example baud rate setting: 1) Division by an integer (divide by N): Selecting fc = 39.321 MHz for fperiph, setting T0 to fperiph/8, using the baud rate generator input clock T1, setting the divide ratio N (BR0CR<BR0S3:0>) = 4, and setting BR0CR<BR0ADDE> = "0," the resulting baud rate in the UART mode is calculated as follows: * Clocking conditions System clock : High speed clock gear : Prescaler clock : Baud rate = fc/32 High-speed (fc) 1/2 (fc) fperiph/8 (fperiph = fsys) /16 4 = 39.321 (bps) x 106 / 32 / 4 / 16 19200 (bps) (Note) 2) The divide by (N + (16-K)/16) function is inhibited and thus BR0ADD <BR0K3:0> is ignored. For divide by N + (16-K)/16 (only for UART mode): Selecting fc = 19.2 MHz for fperiph, setting T0 to fperiph/8, using the baud rate generator input clock T2, setting the divide ratio N (BR0CR<BR0S3:0>) = 7, setting K (BR0ADD<BR0K3:0>) = 3, and selecting BR0CR<BR0ADDE> = 1, the resulting baud rate is calculated as follows: * Clocking conditions System clock : High-speed clock gear : Prescaler clock : Baud rate = 7+ High-speed (fgear) 1/4 (fgear) fperiph/4 (fperiph = fsys) fc/32 /16 (16 - 3) 16 = 19.2 x 106 / 32 / (7 + 13 ) / 16 = 4800 (bps) 16 Serial Channel (SIO) TMP19A44(rev1.3) 14-5 2010-04-01 TMP19A44 Also, an external clock input may be used as the serial clock. The resulting baud rate calculation is shown below: * Baud rate calculation for an external clock input: 1) UART mode Baud Rate = external clock input / 16 In this, the period of the external clock input must be equal to or greater than 4/fsys. If fsys = 80 MHz, the highest baud rate will be 80 / 4 / 16 = 1.25 (kbps). 2) I/O interface mode Baud Rate = external clock input When double buffering is used, it is necessary to satisfy the following relationship: External clock input period > 12/fsys Therefore, when fsys = 80 MHz, the baud rate must be set to a rate lower than 80 / 12 = 6.67 (Mbps). When double buffering is not used, it is necessary to satisfy the following relationship: External clock input period > 16/fsys Therefore, when fsys = 80 MHz, the baud rate must be set to a rate lower than 80 / 16 = 5 (Mbps). Example baud rates for the UART mode are shown in Table 14-2 andTable 14- 3. Serial Channel (SIO) TMP19A44(rev1.3) 14-6 2010-04-01 TMP19A44 Table 14-2 Selection of UART Baud Rate (Use the baud rate generator with BR0CR <BR0ADDE> = 0) Input clock fc [MHz] Divide ratio N (Set to BR0CR <BR0S3:0>) Unit (kbps) T1 T4 T16 T64 (fc/4) (fc/16) (fc/64) (fc/256) 19.6608 1 307.200 76.800 19.200 4.800 2 153.600 38.400 9.600 2.400 4 76.800 19.200 4.800 1.200 8 38.400 9.600 2.400 0.600 0 19.200 4.800 1.200 0.300 24.576 5 76.800 19.200 4.800 1.200 29.4912 A 38.400 9.600 2.400 0.600 1 460.800 115.200 28.800 7.200 2 230.400 57.600 14.400 3.600 3 153.600 38.400 9.600 2.400 4 115.200 28.800 7.200 1.800 6 76.800 19.200 4.800 1.200 C 38.400 9.600 2.400 0.600 (Note) This table shows the case where the system clock is set to fc, the clock gear is set to fc/1, and the prescaler clock is set to fperiph/2. Table 14-1 Selection of UART Baud Rate (The TMRB2 timer output (internal TB2OUT) is used with the timer input clock set to T1.) Unit (kbps) Fperiph/4 TB0REG 19.6608 MHz 16 MHz 2H 153.6 125 3H 76.8 62.5 4H 51.2 41.67 5H 38.4 31.25 Baud rate calculation to use the TMRB2 timer: Transfer rate = Clock frequency selected by SYSCR0 < PRCK2 : 0 > TB2REG x 2 x 2 x 16 (When input clock to the timer TMRB2 is T1) (Note 1) In the I/O interface mode, the TMRB0 timer output signal cannot be used internally as the transfer clock. (Note 2) This table shows the case where the system clock is set to fc, the clock gear is set to fc/1, and the prescaler clock is set to fperiph/4. Serial Channel (SIO) TMP19A44(rev1.3) 14-7 2010-04-01 TMP19A44 14.2.2 Serial Clock Generation Circuit This circuit generates basic transmit and receive clocks. * I/O interface mode: In the SCLK output mode with the SC0CR <IOC> serial control register set to "0," the output of the previously mentioned baud rate generator is divided by 2 to generate the basic clock. In the SCLK input mode with SC0CR <IOC> set to "1," rising and falling edges are detected according to the SC0CR <SCLKS> setting to generate the basic clock. * Asynchronous (UART) mode: According to the settings of the serial control mode register SC0MOD0 <SC1:0>, either the clock from the baud rate register, the system clock (fSYS/2), the internal output signal of the TMRB2 timer, or the external clock (SCLKO pin) is selected to generate the basic clock, SIOCLK. 14.2.3 Receive Counter The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is up-counted by SIOCLK. Sixteen SIOCLK clock pulses are used in receiving a single data bit while the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three samples, majority logic is applied to decide the received data. 14.2.4 Receive Control Unit * I/O interface mode: In the SCLK output mode with SC0CR <IOC> set to "0," the RXD0 pin is sampled on the rising edge of the shift clock output to the SCLK0 pin. In the SCLK input mode with SC0CR <IOC> set to "1," the serial receive data RXD0 pin is sampled on the rising or falling edge of SCLK input depending on the SC0CR <SCLKS> setting. * Asynchronous (UART) mode: The receive control unit has a start bit detection circuit, which is used to initiate receive operation when a normal start bit is detected. 14.2.5 Receive Buffer The receive buffer is of a dual structure to prevent overrun errors. The first receive buffer (a shift register) stores the received data bit-by-bit. When a complete set of bits have been stored, they are moved to the second receive buffer (SC0BUF). At the same time, the receive buffer full flag (SC0MOD2 "RBFLL") is set to "1" to indicate that valid data is stored in the second receive buffer. However, if the receive FIFO is set enabled, the receive data is moved to the receive FIFO and this flag is immediately cleared. If the receive FIFO has been disabled (SCOFCNF <CNFG> = 0 and <FDPX1:0> =01), the INTRX0 interrupt is generated at the same time. If the receive FIFO has been enabled (SCNFCNF <CNFG> = 1 and <FDPX1:0> = 01/11), an interrupt will be generated according to the SC0RFC <RIL1:0> setting. Serial Channel (SIO) TMP19A44(rev1.3) 14-8 2010-04-01 TMP19A44 The CPU will read the data from either the second receive buffer (SC0BUF) or from the receive FIFO (the address is the same as that of the receive buffer). If the receive FIFO has not been enabled, the receive buffer full flag <RBFLL> is cleared to "0" by the read operation. The next data received can be stored in the first receive buffer even if the CPU has not read the previous data from the second receive buffer (SC0BUF) or the receive FIFO. If SCLK is set to generate clock output in the I/O interface mode, the double buffer control bit SC0MOD2 <WBUF> can be programmed to enable or disable the operation of the second receive buffer (SCOBUF). By disabling the second receive buffer (i.e., the double buffer function) and also disabling the receive FIFO (SCOFCNF <CNFG> = 0 and <FDPX1:0> = 01), handshaking with the other side of communication can be enabled and the SCLK output stops each time one frame of data is transferred. In this setting, the CPU reads data from the first receive buffer. By the read operation of CPU, the SCLK output resumes. If the second receive buffer (i.e., double buffering) is enabled but the receive FIFO is not enabled, the SCLK output is stopped when the first receive data is moved from the first receive buffer to the second receive buffer and the next data is stored in the first buffer filling both buffers with valid data. When the second receive buffer is read, the data of the first receive buffer is moved to the second receive buffer and the SCLK output is resumed upon generation of the receive interrupt INTRX. Therefore, no buffer overrun error will be caused in the I/O interface SCLK output mode regardless of the setting of the double buffer control bit SC0MOD2 <WBUF>. If the second receive buffer (double buffering) is enabled and the receive FIFO is also enabled (SCNFCNF <CNFG> = 1 and <FDPX1:0> = 01/11), the SCLK output will be stopped when the receive FIFO is full (according to the setting of SCOFNCF <RFST>) and both the first and second receive buffers contain valid data. Also in this case, if SCOFCNF <RXTXCNT> has been set to "1," the receive control bit RXE will be automatically cleared upon suspension of the SCLK output. If it is set to "0," automatic clearing will not be performed. (Note) In this mode, the SC0CR <OEER> flag is insignificant and the operation is undefined. Therefore, before switching from the SCLK output mode to another mode, the SC0CR register must be read to initialize this flag. In other operating modes, the operation of the second receive buffer is always valid, thus improving the performance of continuous data transfer. If the receive FIFO is not enabled, an overrun error occurs when the data in the second receive buffer (SC0BUF) has not been read before the first receive buffer is full with the next receive data. If an overrun error occurs, data in the first receive buffer will be lost while data in the second receive buffer and the contents of SC0CR <RB8> remain intact. If the receive FIFO is enabled, the FIFO must be read before the FIFO is full and the second receive buffer is written by the next data through the first buffer. Otherwise, an overrun error will be generated and the receive FIFO overrun error flag will be set. Even in this case, the data already in the receive FIFO remains intact. The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit UART mode will be stored in SC0CR <RB8>. Serial Channel (SIO) TMP19A44(rev1.3) 14-9 2010-04-01 TMP19A44 In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wakeup function SC0MOD0 <WU> to "1." In this case, the interrupt INTRX0 will be generated only when SC0CR <RB8> is set to "1." 14.2.6 Receive FIFO Buffer In addition to the double buffer function already described, data may be stored using the receive FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the SC0MOD1 register, the 4byte receive buffer can be enabled. Also, in the UART mode or I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO buffer is to be used, be sure to enable the double buffer function. If data with parity bit is to be received in the UART mode, parity check must be performed each time a data frame is received. 14.2.7 Receive FIFO Operation c I/O interface mode with SCLK output: The following example describes the case a 4-byte data stream is received in the half duplex mode: SC0FCNF <4:0>=10111: Automatically inhibits continued reception after reaching the fill level. The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill level. SC0RFC<1:0>=00: Sets the interrupt to be generated at fill level 4.I SC0RFC<7:6>=01: Clears receive FIFO and sets the condition of interrupt generation. n this condition, 4-byte data reception may be initiated by setting the half duplex transmission mode and writing "1" to the RXE bit. After receiving 4 bytes, the RXE bit is automatically cleared and the receive operation is stopped (SCLK is stopped). Receive buffer 1 1 byte 2 byte 3 byte 4 byte 1 byte 2 byte 3 byte Receive buffer 2 RX FIFO 1 byte 2 byte 1 byte 3 byte 2 byte 1 byte 4 byte 4 byte 3 byte 2 byte 1 byte RBFLL Receive interrupt RXE Fig. 14-3 Receive FIFO Operation Serial Channel (SIO) TMP19A44(rev1.3) 14-10 2010-04-01 TMP19A44 d I/O interface mode with SCLK input: The following example describes the case a 4-byte data stream is received: SC0FCNF <4:0> = 10101: Automatically allows continued reception after reaching the fill level. The number of bytes to be used in the receive FIFO is the maximum allowable number. SC0RFC <1:0> = 00: Sets the interrupt to be generated at fill level 4. SC0RFC <7:6> = 10: Clears receive FIFO and sets the condition of interrupt generation In this condition, 4-byte data reception can be initiated along with the input clock by setting the half duplex transmission mode and writing "1" to the RXE bit. When the 4-byte data reception is completed, the receive FIFO interrupt will be generated. Note that preparation for the next data reception can be managed in this setting, i.e., the next 4-byte data can be received before data is fully read from the FIFO. Receive buffer 1 1 byte 2 byte 3 byte 4 byte 1 byte 2 byte 3 byte Receive buffer 2 RX FIFO 1 byte 2 byte 1 byte 3 byte 2 byte 1 byte 4 byte 4 byte 3 byte 2 byte 1 byte RBFLL Receive interrupt RXE Fig. 14-4 Receive FIFO Operation Serial Channel (SIO) TMP19A44(rev1.3) 14-11 2010-04-01 TMP19A44 14.2.8 Transmit Counter The transmit counter is a 4-bit binary counter used in the asynchronous communication (UART) mode. It is counted by SIOCLK as in the case of the receive counter and generates a transmit clock (TXDCLK) on every 16th clock pulse. SIOCLK 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK Fig. 14-5 Transmit Clock Generation 14.2.9 Transmit Control Unit * I/O interface mode: In the SCLK output mode with SC0CR <IOC> set to "0," each bit of data in the send buffer is output to the TXD0 pin on the rising edge of the shift clock output from the SCLK0 pin. In the SCLK input mode with SC0CR <IOC> set to "1," each bit of data in the send buffer is output to the TXD0 pin on the rising or falling edge of the input SCLK signal according to the SC0CR <SCLKS> setting. * Asynchronous (UART) mode: When the CPU writes data to the send buffer, data transmission is initiated on the rising edge of the next TXDCLK and the transmit shift clock (TXDSFT) is also generated. Serial Channel (SIO) TMP19A44(rev1.3) 14-12 2010-04-01 TMP19A44 * Handshake function The CTS pin enables frame by frame data transmission so that overrun errors can be prevented. This function can be enabled or disabled by SC0MOD0 <CTSE>. When the CTS0 pin is set to the "H" level, the current data transmission can be completed but the next data transmission is suspended until the CTS0 pin returns to the "L" level. However in this case, the INTTX0 interrupt is generated, the next transmit data is requested to the CPU, data is written to the send buffer, and it waits until it is ready to transmit data. Although no RTS pin is provided, a handshake control function can be easily implemented by assigning a port for the RTS function. By setting the port to "H" level upon completion of data reception (in the receive interrupt routine), the transmit side can be requested to suspend data transmission. TXD RXD CTS RTS (Any port) Transmit side Receive side Fig. 14-6 Handshake Function Data write timing to send buffer or shift register Transmission is suspended during d this period CTS c 13 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TXDCLK TXD (Note) start bit bit 0 c If the CTS signal is set to "H" during transmission, the next data transmission is suspended after the current transmission is completed. d Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to "L." Fig. 14-7 CTS (Clear to Send) Signal Timing Serial Channel (SIO) TMP19A44(rev1.3) 14-13 2010-04-01 TMP19A44 14.2.10 Transmit Buffer The send buffer (SC0BUF) is in a dual structure. The double buffering function may be enabled or disabled by setting the double buffer control bit <WBUF> in serial mode control register 2 (SC0MOD2). If double buffering is enabled, data written to send buffer 2 (SCOBUF) is moved to send buffer 1 (shift register). If the transmit FIFO has been disabled (SCOFCNF <CNFG> = 0 or 1 and <FDPX1:0> = 01/11), the INTTX interrupt is generated at the same time and the send buffer empty flag <TBEMP> of SC0MOD2 is set to "1." This flag indicates that send buffer 2 is now empty and that the next transmit data can be written. When the next data is written to send buffer 2, the <TBEMP> flag is cleared to "0." If the transmit FIFO has been enabled (SCNFCNF <CNFG> = 1 and <FDPX1:0> = 10/11), any data in the transmit FIFO is moved to the send buffer 2 and <TBEMP> flag is immediately cleared to "0." The CPU writes data to send buffer 2 or to the transmit FIFO. If the transmit FIFO is disabled in the I/O interface SCLK input mode and if no data is set in send buffer 2 before the next frame clock input, which occurs upon completion of data transmission from send buffer 1, an under-run error occurs and a serial control register (SC0CR) <PERR> parity/under-run flag is set. If the transmit FIFO is enabled in the I/O interface SCLK input mode, when data transmission from send buffer 1 is completed, the send buffer 2 data is moved to send buffer 1 and any data in transmit FIFO is moved to send buffer 2 at the same time. If the transmit FIFO is disabled in the I/O interface SCLK output mode, when data in send buffer 2 is moved to send buffer 1 and the data transmission is completed, the SCLK output stops. So, no underrun errors can be generated. If the transmit FIFO is enabled in the I/O interface SCLK output mode, the SCLK output stops upon completion of data transmission from send buffer 1 if there is no valid data in the transmit FIFO. Note) In the I/O interface SCLK output mode, the SC0CR <PEER> flag is insignificant. In this case, the operation is undefined. Therefore, to switch from the SCLK output mode to another mode, SC0CR must be read in advance to initialize the flag. If double buffering is disabled, the CPU writes data only to send buffer 1 and the transmit interrupt INTTX is generated upon completion of data transmission. If handshaking with the other side is necessary, set the double buffer control bit <WBUF> to "0" (disable) to disable send buffer 2; any setting for the transmit FIFO should not be performed. Serial Channel (SIO) TMP19A44(rev1.3) 14-14 2010-04-01 TMP19A44 14.2.11 Transmit FIFO Buffer In addition to the double buffer function already described, data may be stored using the transmit FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the SC0MOD1 register, the 4byte send buffer can be enabled. In the UART mode or I/O interface mode, up to 4 bytes of data may be stored. If data is to be transmitted with a parity bit in the UART mode, parity check must be performed on the receive side each time a data frame is received. note. Please execute clear the transmit FIFO after the forwarding mode setting and the permission of FIFO of SIO when you use the transmit FIFO buffer. 14.2.12 Transmit FIFO Operation c I/O interface mode with SCLK output (normal mode): The following example describes the case a 4-byte data stream is transmitted: SC0FCNF <4:0> = 01011: Inhibits continued transmission after reaching the fill level. SC0TFC <1:0> = 00: Sets the interrupt to be generated at fill level 0. SC0TFC <7:6> = 11: Clears transmit FIFO and sets the condition of interrupt generation In this condition, data transmission can be initiated by setting the transfer mode to half duplex, writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1." When the last transmit data is moved to the send buffer, the transmit FIFO interrupt is generated. When transmission of the last data is completed, the clock is stopped and the transmission sequence is terminated. TX FIFO Send buffer 2 Data 6 Data 5 Data 4 Data 6 Data 3 Data 6 Data 5 Data 4 Data 5 Data 6 Data 6 Data 2 Data 3 Data 4 Data 5 Data 5 Send buffer 1 Data 1 Data 2 Data 3 Data 4 TBEMP INTTX0 TXE Fig. 14-8 Transmit FIFO Operation Serial Channel (SIO) TMP19A44(rev1.3) 14-15 2010-04-01 TMP19A44 d I/O interface mode with SCLK input (normal mode): The following example describes the case a 4-byte data stream is transmitted: SC0FCNF <4:0> = 01001: Allows continued transmission after reaching the fill level. SC0TFC <1:0> = 00: Clears the transmit FIFO and sets the condition of interrupt generation. SC0TFC <7:6> = 11: Sets the interrupt to be generated at fill level 0. In this condition, data transmission can be initiated along with the input clock by setting the transfer mode to half duplex, writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1." When the last transmit data is moved to the send buffer, the transmit FIFO interrupt is generated. TX FIFO Send buffer 2 Data 6 Data 5 Data 4 Data 6 Data 3 Data 6 Data 5 Data 4 Data 5 Data 6 Data 6 Data 2 Data 3 Data 4 Data 5 Data 5 Send buffer 1 Data 1 Data 2 Data 3 Data 4 TBEMP INTTX0 TXE Fig. 14-9 Transmit FIFO Operation Serial Channel (SIO) TMP19A44(rev1.3) 14-16 2010-04-01 TMP19A44 14.2.13 Parity Control Circuit If the parity addition bit <PE> of the serial control register SC0CR is set to "1," data is sent with the parity bit. Note that the parity bit may be used only in the 7- or 8-bit UART mode. The <EVEN> bit of SC0CR selects either even or odd parity. Upon data transmission, the parity control circuit automatically generates the parity with the data written to the send buffer (SC0BUF). After data transmission is complete, the parity bit will be stored in SC0BUF bit 7 <TB7> in the 7-bit UART mode and in bit 7 <TB8> in the serial mode control register SC0MOD in the 8-bit UART mode. The <PE> and <EVEN> settings must be completed before data is written to the send buffer. Upon data reception, the parity bit for the received data is automatically generated while the data is shifted to receive buffer 1 and moved to receive buffer 2 (SC0BUF). In the 7-bit UART mode, the parity generated is compared with the parity stored in SC0BUF <RB7>, while in the 8-bit UART mode, it is compared with the bit 7 <RB8> of the SC0CR register. If there is any difference, a parity error occurs and the <PERR> flag of the SC0CR register is set. In the I/O interface mode, the SC0CR <PERR> flag functions as an under-run error flag, not as a parity flag. 14.2.14 Error Flag Three error flags are provided to increase the reliability of received data. 1. Overrun error <OERR>: Bit 4 of the serial control register SC0CR In both UART and I/O interface modes, this bit is set to "1" when an error is generated by completing the reception of the next frame receive data before the receive buffer has been read. If the receive FIFO is enabled, the received data is automatically moved to the receive FIFO and no overrun error will be generated until the receive FIFO is full (or until the usable bytes are fully occupied). This flag is set to "0" when it is read. In the I/O interface SCLK output mode, no overrun error is generated and therefore, this flag is inoperative and the operation is undefined. 2. Parity error/under-run error <PERR>: Bit 3 of the SC0CR register In the UART mode, this bit is set to "1" when a parity error is generated. A parity error is generated when the parity generated from the received data is different from the parity received. This flag is set to "0" when it is read. In the I/O interface mode, this bit indicates an under-run error. When the double buffer control bit <WBUF> of the serial mode control register SC0MOD2 is set to "1" in the SCLK input mode, if no data is set to the transmit double buffer before the next data transfer clock after completing the transmission from the transmit shift register, this error flag is set to "1" indicating an under-run error. If the transmit FIFO is enabled, any data content in the transmit FIFO will be moved to the buffer. When the transmit FIFO and the double buffer are both empty, an under-run error will be generated. Because no under-run errors can be generated in the SCLK output mode, this flag is inoperative and the operation is undefined. If send buffer 2 is disabled, the under-run flag <PERR> will not be set. This flag is set to "0" when it is read. Serial Channel (SIO) TMP19A44(rev1.3) 14-17 2010-04-01 TMP19A44 3. Framing error <FERR>: Bit 2 of the SC0CR register In the UART mode, this bit is set to "1" when a framing error is generated. This flag is set to "0" when it is read. A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at around the center. Regardless of the <SBLEN> (stop bit length) setting of the serial mode control register 2, SC0MOD2, the stop bit status is determined by only 1 bit on the receive side. Operation mode UART I/O interface (SCLK input) I/O interface (SCLK output) Error flag OERR PERR FERR OERR PERR FERR OERR PERR FERR Function Overrun error flag Parity error flag Framing error flag Overrun error flag Underrun error flag (WBUF = 1) Fixed to 0 (WBUF = 0) Fixed to 0 Operation undefined Operation undefined Fixed to 0 14.2.15 Direction of Data Transfer In the I/O interface mode, the direction of data transfer can be switched between "MSB first" and "LSB first" by the data transfer direction setting bit <DRCHG> of the SC0MOD2 serial mode control register 2. Don't switch the direction when data is being transferred. 14.2.16 Stop Bit Length In the UART mode transmission, the stop bit length can be set to either 1 or 2 bits by bit 4 <SBLEN> of the SC0MOD2 register. 14.2.17 Status Flag If the double buffer function is enabled (SC0MOD2 <WBUF> = "1"), the bit 6 flag <RBFLL> of the SC0MOD2 register indicates the condition of receive buffer full. When one frame of data has been received and transferred from buffer 1 to buffer 2, this bit is set to "1" to show that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read by CPU/DMAC, it is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not be used as a status flag. When double buffering is enabled (SC0MOD2 <WBUF> = "1"), the bit 7 flag <TBEMP> of the SC0MOD2 register indicates that send buffer 2 is empty. When data is moved from send buffer 2 to send buffer 1 (shift register), this bit is set to "1" indicating that send buffer 2 is now empty. When data is set to the send buffer by CPU/DMAC, the bit is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not be used as a status flag. 14.2.18 Configurations of Send/Receive Buffers UART I/O interface (SCLK input) I/O interface (SCLK output) Serial Channel (SIO) Transmit buffer Receive buffer Transmit buffer Receive buffer Transmit buffer Receive buffer <WBUF> = 0 <WBUF> = 1 Single Double Single Double Single Single Double Double Double Double Double Double TMP19A44(rev1.3) 14-18 2010-04-01 TMP19A44 14.2.19 software reset Software reset is HSC0MOD2 <SWRST1:0>"10" "01" SC0MOD0RXESC0MOD1<TXE>SC0MOD2TBEMP,RBFLL,TXRUN SC0CROERRPERRFERRand internal circuit is initialized. Other states are maintained. 14.2.20 Signal Generation Timing c UART Mode: Receive Side Mode Interrupt generation timing Framing error timing 9-bit Around the center of the 1st stop bit Around the center of the stop bit Parity error generation timing Overrun error generation Around the center timing of the stop bit 8-bit with parity Around the center of the 1st stop bit Around the center of the stop bit Around the center of the last (parity) bit Around the center of the stop bit 8-bit, 7-bit, and 7-bit with parity Around the center of the 1st stop bit Around the center of the stop bit Around the center of the last (parity) bit Around the center of the stop bit Transmit Side Mode Interrupt generation timing (<WBUF> = 0) Interrupt generation timing (<WBUF> = 1) d 9-bit 8-bit with parity 8-bit, 7-bit, and 7-bit with parity Just before the stop Just before the stop bit is Just before the stop bit is sent bit is sent sent Immediately after data is moved to send buffer 1 (just before start bit transmission) Immediately after data is Immediately after data is moved to moved to send buffer 1 send buffer 1 (just before start bit (just before start bit transmission) transmission) I/O interface mode: Receive Side Immediately after the rising edge of the last SCLK Interrupt generation SCLK output timing mode (WBUF = 0) SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or falling edge mode, respectively) Interrupt generation SCLK output Immediately after the rising edge of the last SCLK (just after data timing mode transfer to receive buffer 2) or just after receive buffer 2 is read (WBUF = 1) SCLK input mode Immediately after the rising edge or falling edge of the last SCLK depending on the rising or falling edge triggering mode, respectively (right after data is moved to receive buffer 2) SCLK input mode Immediately after the rising or falling edge of the last SCLK (for Overrun error generation timing rising or falling edge mode, respectively) Transmit Side Immediately after the rising edge of the last SCLK Interrupt generation SCLK output timing mode (WBUF = 0) SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or falling edge mode, respectively) Interrupt generation SCLK output Immediately after the rising edge of the last SCLK or just after timing mode data is moved to send buffer 1 (WBUF = 1) SCLK input mode Immediately after the rising or falling edge of the last SCLK (for the rising or falling edge mode, respectively) or just after data is moved to send buffer 1 Serial Channel (SIO) TMP19A44(rev1.3) 14-19 2010-04-01 TMP19A44 Under-run error generation timing SCLK input mode Immediately after the falling or rising edge of the next SCLK (for the rising or falling edge triggering mode, respectively) Note 1) Do not modify any control register when data is being sent or received (in a state ready to send or receive). Note 2) Do not stop the receive operation (by setting SC0MOD0 <RXE> = "0") when data is being received. Note 3) Do not stop the transmit operation (by setting SC0MOD1 <TXE> = "0") when data is being transmitted. 14.3 Register Description 14.3.1 Operation of Each Channel Registers and addresses of each channel are shown below. Table 14.4 Register List SIO0 SIO1 SIO2 Enable Register SC0EN 0xFF00_4C00 SC1EN 0xFF00_4C40 SC2EN 0xFF00_4C80 TX/ RX Buffer Register SC0BUF 0xFF00_4C04 SC1BUF 0xFF00_4C44 SC2BUF 0xFF00_4C84 Control Register SC0CR 0xFF00_4C08 SC1CR 0xFF00_4C48 SC2CR 0xFF00_4C88 Mode control Register 0 SC0MOD0 0xFF00_4C0C SC1MOD0 0xFF00_4C4C SC2MOD0 0xFF00_4C8C Baud Rate Generator Control Register BR0CR 0xFF00_4C10 BR1CR 0xFF00_4C50 BR2CR 0xFF00_4C90 Baud Rate Generator Control Register 2 BR0ADD 0xFF00_4C14 BR1ADD 0xFF00_4C54 BR2ADD 0xFF00_4C94 Register Mode Control Register 1 name Mode Control Register 2 (address) Receive FIFO Configuration Register SC0MOD1 0xFF00_4C18 SC1MOD1 0xFF00_4C58 SC2MOD1 0xFF00_4C98 SC0MOD2 0xFF00_4C1C SC1MOD2 0xFF00_4C5C SC2MOD2 0xFF00_4C9C SC0RFC 0xFF00_4C20 SC1RFC 0xFF00_4C60 SC2RFC 0xFF00_4CA0 Transmit FIFO Configuration Register SC0TFC 0xFF00_4C24 SC1TFC 0xFF00_4C64 SC2TFC 0xFF00_4CA4 Receive FIFO Status Register SC0RST 0xFF00_4C28 SC1RST 0xFF00_4C68 SC2RST 0xFF00_4CA8 Transmit FIFO Status Register SC0TST 0xFF00_4C2C SC1TST 0xFF00_4C6C SC2TST 0xFF00_4CAC FIFO Configuration Register SC0FCNF 0xFF00_4C30 SC1FCNF 0xFF00_4C70 Serial Channel (SIO) TMP19A44(rev1.3) 14-20 SC2FCNF 0xFF00_4CB0 2010-04-01 TMP19A44 14.3.2 Detailed Description of Registers As channels 0 to 3 have same register set, only channel 0 is described here. 14.3.2.1 Enable Register 7 SC0EN 6 5 bit Symbol Read/Write After reset 4 3 2 1 0 SIOE R/W 0 SIO operation 0: Disable 1: Enable R 0 Always reads "0." Function <SIOE>: It specifies SIO operation. When SIO is to be used, be sure to enable SIO by setting "1" to this register before setting any other registers of the SIO module. When SIO operation is disabled, the clock will not be supplied to the SIO module except for the register part and thus power consumption can be reduced. If SIO is enabled once and then disabled, any register setting is maintained. 14.3.2.2 TX/ RX Buffer Register 7 6 5 4 3 2 1 0 bit Symbol TB7/RB7 TB6/RB6 TB5/RB5 TB4/RB4 TB3/RB3 TB2/RB2 TB1/RB1 TB0/RB0 SC0BUF R/W Read/Writ e After reset 0 0 0 0 0 0 0 0 TB7~0 : TX buffer/ FIFO RB7~0 : RX buffer/ FIFO Function The buffer register (SC0BUF) functions as TX buffer at writing and RX buffer at reading. <TB7:0> TX buffer (only for writing) <RB7:0> RX buffer (only for reading) Serial Channel (SIO) TMP19A44(rev1.3) 14-21 2010-04-01 TMP19A44 14.3.2.3 Control Register bit Symbol SC0CR Read/Writ e After reset 7 RB8 R 0 Receive data Function 6 EVEN Bit 8 (for UART) 5 PE R/W 0 4 OERR (for UART) 0: Odd 1: Even 2 FERR 1 SCLKS R (cleared to "0" when read) 0 Parity 3 PERR Add parity (for UART) 0: Disable 0 0 0 0: Normal operation 1: Error Overrun 1: Enable Parity/ underrun 0 IOC R/W 0 0 0: SCLK0 (for I/O interfac e) Framing 1: SCLK0 0: Baud rate generator 1: SCLK0 pin input <RB8>: Indicates 9th received bit in 9 bit UART mode. <EVEN>: Specifies parity condition. "0": Odd parity "1": Even parity Parity is available for 7 bit/ 8 bit UART mode. <PE>: Enables or disables parity. Parity is available for 7 bit/ 8 bit UART mode. <OERR>: <PERR>: <FERR>: Indicates error flags (overrun error flag, parity error/ underrun error flag and framing error flag). (Note) <SCLKS>: Clock edge selection for data transmission/ reception "0": Data send/receive at rising edges of SCLK0 "1": Data send/receive at falling edges of SCLK0 <IOC>: I/O interface input clock selection. "0": Baud rate generator "1": SCLK0 pin input (Note) Every error flag is cleared when read. Serial Channel (SIO) TMP19A44(rev1.3) 14-22 2010-04-01 TMP19A44 14.3.2.4 Mode Control Register 0 bit Symbol 7 6 5 4 TB8 CTSE RXE WU Read/Write SC0MOD0 After reset Function 3 2 1 0 SM1 SM0 SC1 SC0 R/W 0 Send data Bit 8 0 Handshak e function control 0: Disables CTS 1: Enables CTS 0 Receive control 0: Disables 0 Wake-up function 0: Disable 1: Enable reception 1: Enables reception 0 0 Serial transfer mode 00: I/O interface mode 01: 7-bit length UART mode 10: 8-bit length UART mode 11: 9-bit length UART mode <TB8>: Sets 9th transmit bit in 9 bit UART mode. <CTSE>: Controls handshake function. Setting this bit to "1" enables handshake function using CTS 0 0 Serial transfer clock (for UART) 00: Timer TB2OUT 01: Baud rate generator 10: Internal fSYS/2 clock 11: External clock (SCLK0 input) pin. <RXE>: Executes receive control. (Note) Enable this bit after setting each mode register (SC0MOD0, SC0MOD1 and SC0MOD2). <WU>: Controls wake-up function. This function is available only for 9 bit UART mode. Setting this bit is ignored in other modes. 0 1 9 bit UART mode An interrupt is generated whenever data is received An interrupt is generated when 9th received bit is "1". Others don't care <SM1:0>: Specifies transfer mode. <SC1:0>: Specifies transfer clock in UART mode. In the I/O interface mode, the serial control register (SC0CR) is used for clock. (Note) With <RXE> set to "0," set each mode register (SC0MOD0, SC0MOD1 and SC0MOD2). Then set <RXE> to "1." Serial Channel (SIO) TMP19A44(rev1.3) 14-23 2010-04-01 TMP19A44 14.3.2.5 Mode Control Register 1 bit Symbol SC0MOD1 Read/Write After reset Function 7 6 5 4 3 2 1 I2S0 FDPX1 FDPX0 TXE SINT2 SINT1 SINT0 R/W 0 IDLE 0: Stop 1: Start R/W R/W R/W 0 0 0 Transfer mode setting Transmit 00: Transfer prohibited control 0: Disable 01: Half duplex (RX) 1: Enable 10: Half duplex (TX) 11: Full duplex R/W R/W R/W 0 0 0 Interval time of continuous transmission (for I/O interface) 000: None 100: 8SCLK 001: 1SCLK 101:16SCLK 010: 2SCLK 110: 32SCLK 011: 4SCLK 111: 64SCLK 0 R/W 0 Write "0." <I2S0>: Specifies the IDLE mode operation. <FDPX1:0>: Configures the transfer mode in the I/O interface mode. Also configures the FIFO if it is enabled. In the UART mode, it is used only to specify the FIFO configuration. <TXE>: This bit enables transmission and is valid for all the transfer modes. (Note) If disabled while transmission is in progress, transmission is inhibited only after the current frame of data is completed for transmission. <SINT2:0>: This parameter is valid for I/O interface mode when a clock is not input from SCLK0 pin (invalid for other modes). Specifies the interval time of continuous transmission when double buffering or FIFO is enabled in the I/O interface mode. (Note) Enable <TXE> bit after setting other bits. Serial Channel (SIO) TMP19A44(rev1.3) 14-24 2010-04-01 TMP19A44 14.3.2.6 Mode Control Register 2 bit Symbol SC0MOD2 7 6 5 4 3 2 1 0 TBEMP RBFLL TXRUN SBLEN DRCHG WBUF SWRST1 SWRST0 0 Soft reset 0 Read/Write After reset Function R 1 Send buffer empty flag 0: full 0 Receive buffer full flag 0: Empty 1: Empty 1: full R/W 0 0 In Stop bit transmissi (for UART) on flag 0: 1-bit 0: Stop 1: 2-bit 1: Start 0 Setting transfer direction 0 W-buffer 0: Disable 1: Enable Overwrite "01" on "10" to reset 0: LSB first 1: MSB first <TBEMP>: If double buffering is disabled, this flag is insignificant. This flag shows that the send double buffers are empty. When data in the send double buffers is moved to the send shift register and the double buffers are empty, this bit is set to "1." Writing data again to the double buffers sets this bit to "0." <RBFLL>: If double buffering is disabled, this flag is insignificant. This is a flag to show that the receive double buffers are full. When a receive operation is completed and received data is moved from the receive shift register to the receive double buffers, this bit changes to "1" while reading this bit changes it to "0." <TXRUN>: This is a status flag to show that data transmission is in progress. <TXRUN> and <TBEMP> show the following status. <TXRUN> 1 0 <TBEMP> 1 0 Status Transmission in progress Transmission completed Wait state for transmission with next data in a send buffer. <SBLEN>: This specifies the length of stop bit transmission in the UART mode. On the receive side, the decision is made using only a single bit regardless of the <SBLEN> setting. <DRCHG>: Specifies the direction of data transfer in the I/O interface mode. In the UART mode, you need to fix it to LSB first. <WBUF>: This parameter enables or disables the send/receive buffers to send (in both SCLK output/input modes) and receive (in SCLK output mode) data in the I/O interface mode and to transmit data in the UART. In all other modes, double buffering is enabled when receiving data in I/O interface mode (SCLK input) and UART mode regardless of the <WBUF> setting. <SWRST1:0>: Overwriting "01" in place of "10" generates a software reset. When this software reset is executed, the following bits and their internal circuits are initialized. (Note 1, 2 and 3) Register name SC0MOD0 SC0MOD1 SECMOD2 SC0CR Serial Channel (SIO) Bit RXE TXE TBEMP,RBFLL,TXRUN, OERR,PERR,FERR TMP19A44(rev1.3) 14-25 2010-04-01 TMP19A44 (Note 1) While data transmission is in progress, any software reset operation must be executed twice in succession. (Note 2) To complete software reset, it takes 2 clocks after executing an instruction. Executing SYNC and NOP instructions after software reset is recommended. (Note 3) When software reset is executed, the bits listed in the <SWRST1:0> description are initialized. It requires resetting of the mode registers and control register. Serial Channel (SIO) TMP19A44(rev1.3) 14-26 2010-04-01 TMP19A44 14.3.2.7 Baud Rate Generator Control Register (BR0CR) Baud Rate Generator Control Register 2 (BR0ADD) bit Symbol BR0CR Read/Write After reset 7 6 5 4 3 2 1 0 BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 0 0 R/W 0 "Write "0." Function 7 BR0ADD 0 N+(16K)/16 divider function 0: Disable 1: Enable 0 0 Specify baud rate generator input clock 00: T1 01: T4 10: T16 11: T64 6 bit Symbol Read/Write After reset 5 0 0 Divide ratio "N" 0000: 16 0001: 1 0010: 2 : 1111: 15 4 R 0 Always reads "0." Function 3 2 1 0 BR0K3 BR0K2 BR0K1 BR0K0 R/W 0 0 0 0 Specify K for the "N + (16 - K)/16" division 0000: Setting prohibited 0001: K=1 0010: K=2 : 1111: K=15 <RB0ADDE>: Enables or disables N+(16-K)/16 division function. This function is available only for UART mode. <RB0CK1:0>: Selects input clock to the baud rate generator. <RB0S3:0>: Sets divide ratio "N" of the baud rate generator. <RB0K3:0>: Specifies K for the "N + (16 - K)/16" division. Divide ratio of baud rate generator is set in the above two registers. Table 14. shows the divide ratio configuration. Table 14.5 Divide ratio setting BR0ADDE=0 BR0S BR0K Divide ratio Serial Channel (SIO) BR0ADDE=1 (Note 1) (available for UART mode) Set divide ratio "N" (Note 2, 3) No setting required Set "K" (Note 4) N + (16 - K) N 16 TMP19A44(rev1.3) 14-27 2010-04-01 TMP19A44 (Note 1) To use the "N + (16 - K)/16" division function, be sure to set BR0ADDE <BR0ADDE> to "1" after setting the K value (K = 1 to 15) to BR0ADD <BR0K3:0>. (Note 2) The division ratio "1" ("0001") of the baud rate generator can be specified only when the "N + (16 - K)/16" division function is not used In the UART mode. double buffering is used in the I/O interface mode. (Note 3) To use the "N + (16 - K)/16" division function, neither the division ratio "1" ("0001") nor "16" ("0000") can be set. (Note 4) "0" cannot be set as K value. Serial Channel (SIO) TMP19A44(rev1.3) 14-28 2010-04-01 TMP19A44 14.3.2.8 FIFO Configuration Register bit Symbol SC0FCNF 7 6 5 4 Reserved Reserved Reserved RFST Read/Write After reset 3 2 1 0 TFIE RFIE RXTXCNT CNFG 0 TX interrupt for TX FIFO 0: Disable 0 RX interrupt for RX FIFO 0: Disable 0 Automatic disable of RXE/TXE 0: None 0 FIFO Enable 0: Disable R/W 0 0 Be sure to write "000." Function 0 0 Bytes used in RX FIFO 0: Maximum 1: Same as 1: Enable Fill level of RX FIFO 1: Enable 1: Enable 1: Auto Disa ble <RFST>: Specifies bytes used in RX FIFO. (Note) 0: The maximum number of bytes of the FIFO configured is available. (See description of <CNFG> bit.) 1: Same as the fill level for receive interrupt generation specified by SC0RFC <RIL1:0>. <TFIE>: When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter. <RFIE>: When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter. <RXTXCNT>: The function to automatically disable RXE/TXE bits is disabled. If "1" is set, it functions as shown below according to the communication method configured (the communication method can be set in the mode control register 1 SC0MOD1<FDPX1:0>). Half duplex RX Half duplex TX Full duplex <CNFG>: This parameter is to enable FIFO. Setting "1" enables FIFO. If enabled, the SCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows: (the communication method can be set in the mode control register 1 SC0MOD1<FDPX1:0>). Half duplex RX Half duplex TX Full duplex (Note) When the RX FIFO is filled up to the specified number of valid bytes, SC0MOD0<RXE> is automatically set to "0" to inhibit further reception. When the TX FIFO is empty, SC0MOD1<TXE> is automatically set to "0" to inhibit further transmission. When either of the above two conditions is satisfied, TXE/RXE are automatically set to "0" to inhibit further transmission and reception. RX FIFO 4byte TX FIFO 4byte RX FIFO 2byteTX FIFO 2byte Regarding TX FIFO, the maximum number of bytes being configured is always available. The available number of bytes is the bytes already written to the TX FIFO. Serial Channel (SIO) TMP19A44(rev1.3) 14-29 2010-04-01 TMP19A44 14.3.2.9 SC0RFC Receive FIFO Configuration Register 7 6 bit Symbol RFCS RFIS Read/Write W R/W After reset 0 Clear RX FIFO 1: Clear Function 5 4 3 2 1 0 RIL1 0 Select interrupt generatio n condition RIL0 R R/W 0 0 0 FIFO fill level to generate RX interrupts Always reads "0." Always reads "0." 00: 4 bytes (2 bytes if full duplex) 01:1byte 10:2byte 11:3byte 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <RFCS>: Clears RX FIFO. Writing "1" clears FIFO. If not, "0" is read. <RFIS>: Selects interrupt generation condition. 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <RIL1:0>: Specifies FIFO fill level. (Note) 00 01 10 11 (Note) Full duplex 2byte 1byte 2byte 1byte Others 4byte 1byte 2byte 3byte RIL1 is ignored if FDPX1:0=11 (full duplex). Serial Channel (SIO) TMP19A44(rev1.3) 14-30 2010-04-01 TMP19A44 14.3.2.10 SC0TFC Transmit FIFO Configuration Register 7 6 bit Symbol TFCS TFIS Read/Write W R/W After reset 0 Clear TX FIFO 1: Clear Function 5 4 3 2 1 0 TIL1 R 0 0 Select interrupt generatio n condition Always reads "0." Always reads "0." TIL0 R/W 0 0 FIFO fill level to generate TX interrupts 00:Empty 01:1byte 10:2byte 11:3byte Note: TIL1 is ignored if FDPX1:0=11 (full duplex). 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <TFCS>: Clears TX FIFO. Writing "1" clears FIFO. If not, "0" is read. <TFIS>: Selects interrupt generation condition. 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <TIL1:0>: Specifies FIFO fill level. (Note) 00 01 10 11 (Note) Full duplex Empty 1byte Empty 1byte Others Empty 1byte 2byte 3byte TIL1 is ignored if FDPX1:0=11 (full duplex). Serial Channel (SIO) TMP19A44(rev1.3) 14-31 2010-04-01 TMP19A44 14.3.2.11 Receive FIFO Status Register 7 SC0RST bit Symbol ROR Read/Write R After reset Function 0 RX FIFO Overrun 6 5 4 3 2 1 0 RLVL2 RLVL1 RLVL0 R 0 Always reads "0." R 0 0 0 Status of RX FIFO fill level 000:Empty 001:1Byte 1: Generate d 010:2Byte 011:3Byte 100:4Byte <ROR>: Flag for RX FIFO overrun. This parameter is set to "1" if overrun occurs (note). <RLVL2:0>: Indicates status of RX FIFO fill level. (Note) The <ROR> bit is cleared to "0" when receive data is read from the SC0BUF register. Serial Channel (SIO) TMP19A44(rev1.3) 14-32 2010-04-01 TMP19A44 14.3.2.12 Transmit FIFO Status Register 7 SC0TST bit Symbol TUR Read/Write R After reset 1 TX FIFO Underrun 6 5 4 3 2 0 TLVL2 TLVL1 TLVL0 R 0 Always reads "0." R 0 0 0 Status of TX FIFO fill level 000:Empty 001:1Byte 1: Generated Function 010:2Byte . Cleared to "0" when FIFO is written by received data. 011:3Byte 100:4Byte <TUR>: Flag for TX FIFO underrun. This parameter is set to "1" if underrun occurs (note). <TLVL2:0>: Indicates status of TX FIFO fill level. (Note) The <TUR> bit is cleared to "0" when receive data is read from the SC0BUF register. Serial Channel (SIO) TMP19A44(rev1.3) 14-33 2010-04-01 TMP19A44 14.4 Operation of Each Circuit (Channel 0) As channels 0 to 3 operate identically, only channel 0 is described here. 14.4.1 Prescaler The device includes a 7-bit prescaler to generate necessary clocks to drive SIO0. The input clock T0 to the prescaler is selected by SYSCR of CG <PRCK2:0> to provide the frequency of either fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32. The clock frequency fperiph is either the clock "fgear," to be selected by SYSCR1<FPSEL> of CG, or the clock "fc" before it is divided by the clock gear. The prescaler becomes active only when the baud rate generator is selected for generating the serial transfer clock in the mode control register 0 (SC0MOD0<SC1:0>). Table 14. shows Clock Resolution to the Baud Rate Generator. The serial interface baud rate generator uses four different clocks, i.e., T1, T4, T16 and T64, supplied from the prescaler output clock. Serial Channel (SIO) TMP19A44(rev1.3) 14-34 2010-04-01 TMP19A44 Table 14.6 Clock Resolution to the Baud Rate Generator (fsys=80MHz) Clear peripheral clock <FPSEL> Clock gear value <GEAR2:0> 000 (fc) Prescaler clock selection <PRCK2:0> 0 (fgear) 101(fc/4) 110(fc/8) 111(fc/16) 000 (fc) 100(fc/2) 1 (fc) 111(fc/16) Serial Channel (SIO) T16 T64 fc/24(0.2s) fc/26(0.8s) fc/28(3.2s) 001(fperiph/4) fc/23(0.1s) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) 010(fperiph/8) fc/24(0.2s) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) 5 fc/2 (0.4s) 6 7 fc/2 (1.6s) fc/211(25.6s) 10 fc/2 (6.4s) fc/2 (0.8s) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 000(fperiph/2) fc/23(0.1s) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) 001(fperiph/4) fc/24(0.2s) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) 5 8 9 100(fperiph/32) 010(fperiph/8) fc/2 (0.4s) fc/2 (1.6s) fc/2 (6.4s) fc/211(25.6s) 011(fperiph/16) fc/26(0.8s) 8 fc/2 (3.2s) fc/210(12.8s) fc/212(51.2s) 7 7 fc/2 (1.6s) fc/2 (6.4s) fc/2 (25.6s) fc/213(102.4s) 000(fperiph/2) fc/24(0.2s) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) 5 9 9 100(fperiph/32) fc/2 (0.4s) fc/2 (1.6s) fc/2 (6.4s) fc/211(25.6s) 010(fperiph/8) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) fc/212(51.2s) 7 7 11 001(fperiph/4) fc/2 (1.6s) fc/2 (6.4s) fc/2 (25.6s) fc/213(102.4s) 100(fperiph/32) 8 fc/2 (3.2s) fc/210(12.8s) fc/212(51.2s) fc/214(204.8s) 5 9 9 011(fperiph/16) fc/2 (0.4s) fc/2 (1.6s) fc/2 (6.4s) fc/211(25.6s) 001(fperiph/4) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) fc/212(51.2s) 7 7 11 000(fperiph/2) fc/2 (1.6s) fc/2 (6.4s) fc/2 (25.6s) fc/213(102.4s) 011(fperiph/16) fc/28(3.2s) fc/210(12.8s) fc/212(51.2s) fc/214(204.8s) 9 9 9 010(fperiph/8) fc/2 (6.4s) fc/2 (25.6s) fc/2 (102.4s) fc/215(409.6s) 000(fperiph/2) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) fc/212(51.2s) 7 11 11 100(fperiph/32) fc/2 (1.6s) fc/2 (6.4s) fc/2 (25.6s) fc/213(102.4s) 010(fperiph/8) fc/28(3.2s) fc/210(12.8s) fc/212(51.2s) fc/214(204.8s) 9 9 13 001(fperiph/4) 11 11 011(fperiph/16) fc/2 (6.4s) fc/2 (25.6s) fc/2 (102.4s) fc/215(409.6s) 100(fperiph/32) 10 fc/2 (12.8s) fc/212(51.2s) fc/214(204.8s) fc/216(819.2s) 000(fperiph/2) 001(fperiph/4) 3 fc/2 (0.1s) 4 4 13 fc/2 (0.2s) fc/2 (0.8s) fc/28(3.2s) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) fc/2 (0.2s) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 011(fperiph/16) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 6 6 6 010(fperiph/8) fc/2 (0.8s) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 000(fperiph/2) fc/24(0.2s) 6 fc/2 (0.8s) fc/28(3.2s) 3 8 8 100(fperiph/32) fc/2 (0.1s) fc/2 (0.4s) fc/2 (1.6s) fc/29(6.4s) 010(fperiph/8) fc/24(0.2s) fc/26(0.8s) fc/28(3.2s) fc/210(12.8s) 5 5 10 001(fperiph/4) 7 7 011(fperiph/16) fc/2 (0.4s) fc/2 (1.6s) fc/2 (6.4s) fc/211(25.6s) 100(fperiph/32) fc/26(0.8s) 8 fc/2 (3.2s) fc/210(12.8s) fc/212(51.2s) 000(fperiph/2) 4 4 9 fc/2 (0.2s) fc/2 (0.8s) fc/28(3.2s) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) fc/2 (0.2s) fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) 011(fperiph/16) fc/25(0.4s) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 6 6 6 010(fperiph/8) 8 8 100(fperiph/32) fc/2 (0.8s) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 000(fperiph/2) fc/26(0.8s) fc/28(3.2s) fc/27(1.6s) fc/29(6.4s) 010(fperiph/8) 011(fperiph/16) fc/25(0.4s) 001(fperiph/4) 110(fc/8) T4 001(fperiph/4) 101(fc/4) T1 000(fperiph/2) 011(fperiph/16) 100(fc/2) Prescaler output clock resolution fc/25(0.4s) 6 6 10 fc/2 (0.8s) fc/2 (3.2s) fc/210(12.8s) fc/27(1.6s) fc/29(6.4s) fc/211(25.6s) 8 8 100(fperiph/32) fc/2 (0.8s) fc/2 (3.2s) fc/2 (12.8s) fc/212(51.2s) 000(fperiph/2) fc/26(0.8s) fc/28(3.2s) TMP19A44(rev1.3) 14-35 10 2010-04-01 TMP19A44 Clear peripheral clock <FPSEL> Clock gear value <GEAR2:0> Prescaler clock selection <PRCK2:0> Prescaler output clock resolution T1 T4 011(fperiph/16) fc/2 (1.6s) 100(fperiph/32) fc/26(0.8s) fc/28(3.2s) 001(fperiph/4) 010(fperiph/8) 6 fc/2 (0.8s) 7 T16 T64 fc/27(1.6s) fc/29(6.4s) 8 fc/210(12.8s) 9 fc/2 (6.4s) fc/211(25.6s) fc/210(12.8s) fc/212(51.2s) fc/2 (3.2s) (Note 1) The prescaler output clock Tn must be selected so that the relationship "Tn < fsys/2" is satisfied (so that Tn is slower than fsys/2). (Note 2) Do not change the clock gear while SIO is operating. (Note 3) The horizontal lines in the above table indicate that the setting is prohibited. Serial Channel (SIO) TMP19A44(rev1.3) 14-36 2010-04-01 TMP19A44 14.4.2 Serial Clock Generation Block This block generates basic transmit and receive clocks. In this block, clock is determined according to baud rate generator and specified mode and register setting. 14.4.2.1 Clock Selection Circuit Serial clock is determined according to mode and register setting specified. Specify mode in the mode control register 0 (SC0MOD0<SM1:0>). To use I/O interface mode, clock is specified in the control register SC0CR. To use UART mode, clock is specified in the mode control register0 (SC0MOD0<SC1:0>). Table 14. and Table 14. show details of clock selection in I/O interface mode and UART mode respectively. Table 14.7 Clock selection in I/O interface mode Mode Input/ output Clock edge selection SC0MOD0<SM1:0> selection SC0CR<SCLKS> SC0CR<IOC> SCLK output (Fixed to rising edge) I/O interface mode Rising edge SCLK input Falling edge Clock selection Baud rate generator output divided by 2 Rising edge of SCLK input Falling edge of SCLK input Table 14.8 Clock selection in UART mode Mode Clock selection SC0MOD0<SM1:0> SC0MOD0<SC1:0> Timer output Baud rate generator UART mode fsys/2 SCLK input Serial Channel (SIO) TMP19A44(rev1.3) 14-37 2010-04-01 TMP19A44 14.4.2.2 Baud Rate Generator The baud rate generator divides clocks input from prescaler, and generates transmit and receive clocks. (1) Input clock The baud rate generator uses one of four clocks (T1, T4, T16 or T64) supplied from the prescaler output clock. This input clock selection is made by setting the baud rate generator control register, BR0CR <BR0CK1:0>. Specify the divide ratio of the output clock with the baud rate generator control register BR0CR<BR0ADDE><BR0S3:0> and the baud rate generator control register 2 BR0ADD<BR0K3:0>. (2) UART mode Table 14.9 UART mode BR0CR<BR0ADDE> BR0ADD<BR0K3:0> "0" Setting invalid N+ "1" division (16 - K) Setting valid Set divide ratio "K" K=1,2,3...15 Setting valid Set divide ratio "N" N=2,3...15 N=1,16: setting prohibited 16 Serial Channel (SIO) BR0CR<BR0S3:0> Setting valid Set divide ratio "N" N=1,2,3...16 TMP19A44(rev1.3) 14-38 2010-04-01 TMP19A44 15. Serial Channel (HSIO) 15.1 Features This device has three serial I/O channels: HSIO0 to HSIO2. 15.1.1 Operation Modes Four operation modes (mode 0 through mode 3) are provided to HSIO. Table 15.1 shows data format of each mode. Table 15.1 Data Format Mode Mode 0 Mode 1 Mode 2 Mode 3 Type Synchronous mode (I/O interface mode) Asynchronous mode (UART mode) Data length Transfer Add parity Stop bit length (transfer) 8 bit LSB first or MSB first x 7 bit 8 bit 9 bit LSB first x 1 or 2 Mode 0 is to send and receive I/O data and associated synchronization signals (HSCLK) to extend I/O. HSCLK can be used for input and output. You can select either of LSB or MSB to send first. Neither adding parity nor stop bit is available. Modes 1 through 3 execute asynchronous communication and are designed to send LSB first. In the modes 1 and 2, parity bits can be added. The mode 3 has a wakeup function in which the master controller can start up slave controllers via the serial link (multi-controller system). Stop bit length at transmission can be selected from 1 bit or 2 bits. At reception, stop bit is 1 bit. Hereinafter synchronous mode is referred to as I/O interface mode, asynchronous mode is referred to as UART mode or 7 bit/ 8 bit/ 9 bit UART mode, which includes TX/RX data length. Serial Channel (HSIO) TMP19A44(rev1.3) 15-1 2010-04-01 TMP19A44 15.1.2 Data Format Table 15.1 shows data format of each mode. z Mode 0 (I/O interface mode)/LSB first bit 0 1 2 3 4 5 6 7 3 2 1 0 Transmission direction z Mode 0 (I/O interface mode)/MSB first bit 7 6 5 4 Transmission direction z Mode 1 (7-bit UART mode) Without parity start bit 0 1 2 3 4 5 6 stop start bit 0 1 2 3 4 5 6 parity stop With parity z Mode 2 (8-bit UART mode) Without parity start bit 0 1 2 3 4 5 6 7 stop start bit 0 1 2 3 4 5 6 7 parity stop With parity z Mode 3 (9-bit UART mode) start bit 0 1 2 3 4 5 6 7 8 start bit 0 1 2 3 4 5 6 7 bit 8 stop Stop (wake-up) If bit 8 =1, represents address (select code). If bit 8 =0, represents data. Fig. 15.1 Data Format Serial Channel (HSIO) TMP19A44(rev1.3) 15-2 2010-04-01 TMP19A44 15.2 Block Diagram (Channel 0) Fig. 15.2 shows the block diagram of HSIO0. Each channel consists of a prescaler, a serial clock generation circuit, a receive buffer and its control circuit, and a send buffer and its control circuit. Each channel functions independently. Serial clock generation circuit TB8OUT (from TMRB3) HBR0ADD <BR0K3 : 0> HBR0CR <BR0ADDE> Baud rate generator Selector HSIOCLK HSC0MOD0 HSC0MOD0 <SM1, 0> <SC1, 0> Selector fSYS UART Mode Selector Divider HBR0CR <BR0S5 : 0> /2 fSYS/2 I/O interface mode HSC0CR <IOC> I/O interface mode Interrupt request HINTRX0 HSCLK0 output (shares P92) Receive counter (16 only with UART) RXDCLK HSC0MOD0 Receive <RXE> control HSC0MOD0 Serial <WU> channel interrupt control HTXDCLK Transmit control HSC0CR <PE> <EVEN> Receive buffer 1 (shift register) RB8 Receive buffer 2 (HSC0BUF) FIFO control Internal data bus HCTS0 (shares P92) HSC0MOD0 <CTSE> Parity control HRXD0 (shares P91) Interrupt request HINTTX0 Transmit counter (16 only with UART) Send buffer 1 (shift register) Error flag TB8 HSC0CR <OERR><PERR><FERR> Internal data bus HTXD0 (shares P90) Send buffer 2 (HSC0BUF) FIFO control Internal data bus Fig. 15.2 HSIO0 Block Diagram Serial Channel (HSIO) TMP19A44(rev1.3) 15-3 2010-04-01 TMP19A44 15.3 Register Description 15.3.1 Operation of Each Channel Registers and addresses of each channel are shown below. Table 15.2 Register List HSIO0 HSIO1 TX/ RX Buffer Register HSC0BUF Baud Rate Generator Control Register 2 HBR0ADD 0xFF00_1804 HBR1ADD 0xFF00_1814 HBR2ADD 0xFF00_1824 Mode control Register 1 HSC0MOD1 0xFF00_1805 HSC1MOD1 0xFF00_1815 HSC2MOD1 0xFF00_1825 Mode control Register 2 HC0MOD2 0xFF00_1806 HSC1MOD2 0xFF00_1816 HSC2MOD2 0xFF00_1826 Enable Register HSC0EN Receive FIFO Configuration Register HSC0RFC 0xFF00_1808 HSC1RFC 0xFF00_1818 HSC2RFC 0xFF00_1828 Register Transmit FIFO name Configuration Register (address) 0xFF00_1800 HSC1BUF HSIO2 0xFF00_1807 HSC1EN 0xFF00_1810 HSC2BUF 0xFF00_1817 HSC2EN 0xFF00_1820 0xFF00_1827 HSC0TFC 0xFF00_1809 HSC1TFC 0xFF00_1819 HSC2TFC 0xFF00_1829 Receive FIFO Status Register HSC0RST 0xFF00_180A HSC1RST 0xFF00_181A HSC2RST 0xFF00_182A Transmit FIFO Status Register HSC0TST 0xFF00_180B HSC1TST 0xFF00_181B HSC2TST 0xFF00_182B FIFO Configuration Register HSC0FCNF 0xFF00_180C HSC1FCNF 0xFF00_181C HSC2FCNF 0xFF00_182C Control Register HC0CR Mode control Register 0 HSC0MOD0 0xFF00_180E HSC1MOD0 0xFF00_181E HSC2MOD0 0xFF00_182E Baud Rate Generator Control Register HBR0CR Serial Channel (HSIO) 0xFF00_180D HSC1CR 0xFF00_180F HBR1CR TMP19A44(rev1.3) 15-4 0xFF00_181D HSC2CR 0xFF00_181F HBR2CR 0xFF00_182D 0xFF00_182F 2010-04-01 TMP19A44 Baud Rate Generator The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate. The baud rate generator uses the sys/2 clock. The baud rate generator contains built-in dividers for divide by 1, (N + m/16), and 64 where N is a number from 2 to 63 and m is a number from 0 to 15. The division is performed according to the settings of the baud rate control registers HBR0CR <BR0ADDE> <BR3S3:0> and HBR0ADD <BR0K3:0> to determine the resulting transfer rate. * UART Mode: 1) If HBR0CR <BR0ADDE> = 0, The setting of HBR0ADD <BR0K3:0> is ignored and the counter is divided by N where N is the value set to HBR0CR <BR0S5:0>. (N = 1 to 64). 2) If HBR0CR <BR0ADDE> = 1, The N + (16 - K)/16 division function is enabled and the division is made by using the values N (set in HBR0CR <BR0S3:0>) and K (set in HBR0ADD<BR0K3:0>). (N = 2 to 63, K = 1 to 15) Note * For the N values of 1 and 16, the above N+(16-K)/16 division function is inhibited. So, be sure to set HBR0CR<BR0ADDE> to "0." I/O interface mode: The N + (16 - K)/16 division function cannot be used in the I/O interface mode. Be sure to divide by N, by setting HBR0CR <BR0ADDE> to "0." * Baud rate calculation to use the baud rate generator: 1) UART mode Baud rate = fsys /16 Frequency divided by the divide ratio The highest baud rate out of the baud rate generator is 5 Mbps when fsys is 80 MHz. Serial Channel (HSIO) TMP19A44(rev1.3) 15-5 2010-04-01 TMP19A44 2) I/O interface mode fsys Baud rate = /2 Frequency divided by the divide ratio The highest baud rate will be generated when fsys is 80 MHz. If double buffering is used, the divide ratio can be set to "2" and the resulting output baud rate will be 10 Mbps. (If double buffering is not used, the highest baud rate will be 5 Mbps applying the divide ratio of "2.") * Example baud rate setting: 1) Division by an integer (divide by N): Using the baud rate generator input clock sys, setting the divide ratio N (HBR0CR<BR0S5:0>) = 4, and setting HBR0CR<BR0ADDE> = "0," the resulting baud rate in the UART mode is calculated as follows: * Clocking conditions System clock : High speed clock gear : Baud rate = fsys High-speed (fc) x 1 (fc) /16 4 = 80 x 106 / 4 / 16 =1250 k (bps) (Note) 2) The divide by (N + (16-K)/16) function is inhibited and thus HBR0ADD <BR0K3:0> is ignored. For divide by N + (16-K)/16 (only for UART mode): Using the baud rate generator fsys, setting the divide ratio N (HBR0CR<BR3S5:0>) = 4, setting K (HBR0ADD<BR3K3:0>) = 14, and selecting HBR0CR<BR3ADDE> = 1, the resulting baud rate is calculated as follows: * Clocking conditions System clock : High-speed clock gear : Fsys Baud rate = 4+ (16 - 14) High-speed (fc) x 1 (fc) /16 16 = 80x 106 / (4 + 2 ) / 16 = 121.2 k (bps) 16 Serial Channel (HSIO) TMP19A44(rev1.3) 15-6 2010-04-01 TMP19A44 High-speed Serial Clock Generation Circuit This circuit generates basic transmit and receive clocks. * I/O interface mode: In the HSCLK output mode with the HC0CR <IOC> serial control register set to "0," the output of the previously mentioned baud rate generator is divided by 2 to generate the basic clock. In the HSCLK input mode with HC0CR <IOC> set to "1," rising and falling edges are detected according to the HC0CR <HSCLKS> setting to generate the basic clock. * Asynchronous (UART) mode: According to the settings of the serial control mode register HSC0MOD0 <SC1:0>, either the clock from the baud rate register, the system clock (fSYS), the internal output signal of the TMRB3 timer, or the external clock (HSCLKO pin) is selected to generate the basic clock, HSIOCLK. Receive Counter The receive counter is a 4-bit binary counter used in the asynchronous (UART) mode and is up-counted by HSIOCLK. Sixteen HSIOCLK clock pulses are used in receiving a single data bit while the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three samples, majority logic is applied to decide the received data. Receive Control Unit * I/O interface mode: In the HSCLK output mode with HC0CR <IOC> set to "0," the HRXD0 pin is sampled on the rising edge of the shift clock output to the HSCLK0 pin. In the HSCLK input mode with HC0CR <IOC> set to "1," the serial receive data HRXD0 pin is sampled on the rising or falling edge of HSCLK input depending on the HC0CR <HSCLKS> setting. * Asynchronous (UART) mode: The receive control unit has a start bit detection circuit, which is used to initiate receive operation when a normal start bit is detected. Receive Buffer The receive buffer is of a dual structure to prevent overrun errors. The first receive buffer (a shift register) stores the received data bit-by-bit. When a complete set of bits have been stored, they are moved to the second receive buffer (HSC0BUF). At the same time, the receive buffer full flag (HC0MOD2 "RBFLL") is set to "1" to indicate that valid data is stored in the second receive buffer. However, if the receive FIFO is set enabled, the receive data is moved to the receive FIFO and this flag is immediately cleared. If the receive FIFO has been disabled (HSCOFCNF <CNFG> = 0 and <FDPX1:0> = 01/11), the HINTRX0 interrupt is generated at the same time. If the receive FIFO has been enabled (HSCNFCNF <CNFG> = 1 and SCOMOD1<FDPX1:0> = 01/11), an interrupt will be generated according to the HSC0RFC <RIL1:0> setting. Serial Channel (HSIO) TMP19A44(rev1.3) 15-7 2010-04-01 TMP19A44 The CPU will read the data from either the second receive buffer (HSC0BUF) or from the receive FIFO (the address is the same as that of the receive buffer). If the receive FIFO has not been enabled, the receive buffer full flag <RBFLL> is cleared to "0" by the read operation. The next data received can be stored in the first receive buffer even if the CPU has not read the previous data from the second receive buffer (HSC0BUF) or the receive FIFO. If HSCLK is set to generate clock output in the I/O interface mode, the double buffer control bit HC0MOD2 <WBUF> can be programmed to enable or disable the operation of the second receive buffer (HSCOBUF). By disabling the second receive buffer (i.e., the double buffer function) and also disabling the receive FIFO (HSCOFCNF <CNFG> = 0 or 1 and <FDPX1:0> = 10), handshaking with the other side of communication can be enabled and the HSCLK output stops each time one frame of data is transferred. In this setting, the CPU reads data from the first receive buffer. By the read operation of CPU, the HSCLK output resumes. If the second receive buffer (i.e., double buffering) is enabled but the receive FIFO is not enabled, the HSCLK output is stopped when the first receive data is moved from the first receive buffer to the second receive buffer and the next data is stored in the first buffer filling both buffers with valid data. When the second receive buffer is read, the data of the first receive buffer is moved to the second receive buffer and the HSCLK output is resumed upon generation of the receive interrupt HINTRX. Therefore, no buffer overrun error will be caused in the I/O interface HSCLK output mode regardless of the setting of the double buffer control bit HC0MOD2 <WBUF>. If the second receive buffer (double buffering) is enabled and the receive FIFO is also enabled (HSCNFCNF <CNFG> = 1 and <FDPX1:0> = 01/11), the HSCLK output will be stopped when the receive FIFO is full (according to the setting of HSCOFNCF <RFST>) and both the first and second receive buffers contain valid data. Also in this case, if HSCOFCNF <RXTXCNT> has been set to "1," the receive control bit RXE will be automatically cleared upon suspension of the HSCLK output. If it is set to "0," automatic clearing will not be performed. (Note) In this mode, the HC0CR <OERR> flag is insignificant and the operation is undefined. Therefore, before switching from the HSCLK output mode to another mode, the HC0CR register must be read to initialize this flag. In other operating modes, the operation of the second receive buffer is always valid, thus improving the performance of continuous data transfer. If the receive FIFO is not enabled, an overrun error occurs when the data in the second receive buffer (HSC0BUF) has not been read before the first receive buffer is full with the next receive data. If an overrun error occurs, data in the first receive buffer will be lost while data in the second receive buffer and the contents of HC0CR <RB8> remain intact. If the receive FIFO is enabled, the FIFO must be read before the FIFO is full and the second receive buffer is written by the next data through the first buffer. Otherwise, an overrun error will be generated and the receive FIFO overrun error flag will be set. Even in this case, the data already in the receive FIFO remains intact. The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit UART mode will be stored in HC0CR <RB8>. In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wakeup function HSC0MOD0 <WU> to "1." In this case, the interrupt HINTRX0 will be generated only when HC0CR <RB8> is set to "1." Serial Channel (HSIO) TMP19A44(rev1.3) 15-8 2010-04-01 TMP19A44 Receive FIFO Buffer In addition to the double buffer function already described, data may be stored using the receive FIFO buffer. By setting <CNFG> of the HSC0FCNF register and <FDPX1:0> of the HSC0MOD1 register, the 32-byte receive buffer can be enabled. Also, in the UART mode or I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO buffer is to be used, be sure to enable the double buffer function. Receive FIFO Buffer In addition to the double buffer function already described, data may be stored using the receive FIFO buffer. By setting <CNFG> of the HSC0FCNF register and <FDPX1:0> of the HSC0MOD1 register, the 4-byte receive buffer can be enabled. Also, in the UART mode or I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO buffer is to be used, be sure to enable the double buffer function. If data with parity bit is to be received in the UART mode, parity check must be performed each time a data frame is received. Receive FIFO Operation c I/O interface mode with HSCLK output: The following example describes the case a 32-byte data stream is received in the half duplex mode: HSC0FCNF <4:0>=10111: Automatically inhibits continued reception after reaching the fill level.The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill level. HSC0RFC<4:0>=11111: Sets the interrupt to be generated at fill level 32. HSC0RFC<7:6>=01: Clears receive FIFO and sets the condition of interrupt generation. n this condition, 32-byte data reception may be initiated by setting the half duplex transmission mode and writing "1" to the RXE bit. After receiving 4 bytes, the RXE bit is automatically cleared and the receive operation is stopped (HSCLK is stopped). Receive buffer 1 1 byte 2 byte 3 byte 4 byte 1 byte 2 byte 3 byte 32byte Receive buffer 2 RX FIFO 1 byte 2 byte 1 byte 3 byte 2 byte 1 byte 4 byte 4 byte 3 byte 2 byte 1 byte RBFLL Receive interrupt RXE Fig. 15-3 Receive FIFO Operation Serial Channel (HSIO) TMP19A44(rev1.3) 15-9 2010-04-01 TMP19A44 d I/O interface mode with HSCLK input: The following example describes the case a 32-byte data stream is received: HSC0FCNF <4:0> = 10101:Automatically allows continued reception after reaching the fill level. The number of bytes to be used in the receive FIFO is the maximum allowable number. SC0RFC <4:0> = 11111: Sets the interrupt to be generated at fill level 32. SC0RFC <7:6> = 10: Clears receive FIFO and sets the condition of interrupt generation In this condition, 32-byte data reception can be initiated along with the input clock by setting the half duplex transmission mode and writing "1" to the RXE bit. When the 4-byte data reception is completed, the receive FIFO interrupt will be generated. Note that preparation for the next data reception can be managed in this setting, i.e., the next 32byte data can be received before data is fully read from the FIFO. Receive buffer 1 1 byte 2 byte 3 byte 4 byte 1 byte 2 byte 3 byte 32byte Receive buffer 2 RX FIFO 1 byte 2 byte 1 byte 3 byte 2 byte 1 byte 4 byte 4 byte 3 byte 2 byte 1 byte RBFLL Receive interrupt RXE Fig. 15-4 Receive FIFO Operation Serial Channel (HSIO) TMP19A44(rev1.3) 15-10 2010-04-01 TMP19A44 Transmit Counter The transmit counter is a 4-bit binary counter used in the asynchronous communication (UART) mode. It is counted by SIOCLK as in the case of the receive counter and generates a transmit clock (TXDCLK) on every 16th clock pulse. SIOCLK 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK Fig. 15-5 Transmit Clock Generation Transmit Control Unit * I/O interface mode: In the HSCLK output mode with HC0CR <IOC> set to "0," each bit of data in the send buffer is output to the HTXD0 pin on the rising edge of the shift clock output from the HSCLK0 pin. In the HSCLK input mode with HC0CR <IOC> set to "1," each bit of data in the send buffer is output to the HTXD0 pin on the rising or falling edge of the input HSCLK signal according to the HC0CR <HSCLKS> setting. * Asynchronous (UART) mode: When the CPU writes data to the send buffer, data transmission is initiated on the rising edge of the next HTXDCLK and the transmit shift clock (HTXDSFT) is also generated. Serial Channel (HSIO) TMP19A44(rev1.3) 15-11 2010-04-01 TMP19A44 * Handshake function The H CTS pin enables frame by frame data transmission so that overrun errors can be prevented. This function can be enabled or disabled by HSC0MOD0 <CTSE>. When the H CTS0 pin is set to the "H" level, the current data transmission can be completed but the next data transmission is suspended until the H CTS0 pin returns to the "L" level. However in this case, the HINTTX0 interrupt is generated, the next transmit data is requested to the CPU, data is written to the send buffer, and it waits until it is ready to transmit data. Although no H RTS pin is provided, a handshake control function can be easily implemented by assigning a port for the H RTS function. By setting the port to "H" level upon completion of data reception (in the receive interrupt routine), the transmit side can be requested to suspend data transmission. HTXD HRXD H CTS H RTS (Any port) Transmit side Receive side Fig. 15-6 Handshake Function Data write timing to send buffer or shift register Transmission is suspended during d this period CTS c 13 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TXDCLK TXD (Note) start bit bit 0 c If the CTS signal is set to "H" during transmission, the next data transmission is suspended after the current transmission is completed. d Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to "L." Fig. 15-7 CTS (Clear to Send) Signal Timing Serial Channel (HSIO) TMP19A44(rev1.3) 15-12 2010-04-01 TMP19A44 Transmit Buffer The send buffer (HSC0BUF) is in a dual structure. The double buffering function may be enabled or disabled by setting the double buffer control bit <WBUF> in serial mode control register 2 (HC0MOD2). If double buffering is enabled, data written to send buffer 2 (SCOBUF) is moved to send buffer 1 (shift register). If the transmit FIFO has been disabled (HSCOFCNF <CNFG> = 0 or 1 and <FDPX1:0> = 01/11), the HINTTX interrupt is generated at the same time and the send buffer empty flag <TBEMP> of HC0MOD2 is set to "1." This flag indicates that send buffer 2 is now empty and that the next transmit data can be written. When the next data is written to send buffer 2, the <TBEMP> flag is cleared to "0." If the transmit FIFO has been enabled (HSCNFCNF <CNFG> = 1 and <FDPX1:0> = 10/11), any data in the transmit FIFO is moved to the send buffer 2 and <TBEMP> flag is immediately cleared to "0." The CPU writes data to send buffer 2 or to the transmit FIFO. If the transmit FIFO is disabled in the I/O interface HSCLK input mode and if no data is set in send buffer 2 before the next frame clock input, which occurs upon completion of data transmission from send buffer 1, an under-run error occurs and a serial control register (HC0CR) <PERR> parity/underrun flag is set. If the transmit FIFO is enabled in the I/O interface HSCLK input mode, when data transmission from send buffer 1 is completed, the send buffer 2 data is moved to send buffer 1 and any data in transmit FIFO is moved to send buffer 2 at the same time. If the transmit FIFO is disabled in the I/O interface HSCLK output mode, when data in send buffer 2 is moved to send buffer 1 and the data transmission is completed, the HSCLK output stops. So, no underrun errors can be generated. If the transmit FIFO is enabled in the I/O interface HSCLK output mode, the HSCLK output stops upon completion of data transmission from send buffer 1 if there is no valid data in the transmit FIFO. Note) In the I/O interface HSCLK output mode, the HC0CR <PEER> flag is insignificant. In this case, the operation is undefined. Therefore, to switch from the HSCLK output mode to another mode, HC0CR must be read in advance to initialize the flag. If double buffering is disabled, the CPU writes data only to send buffer 1 and the transmit interrupt HINTTX is generated upon completion of data transmission. If handshaking with the other side is necessary, set the double buffer control bit <WBUF> to "0" (disable) to disable send buffer 2; any setting for the transmit FIFO should not be performed. Serial Channel (HSIO) TMP19A44(rev1.3) 15-13 2010-04-01 TMP19A44 Transmit FIFO Buffer In addition to the double buffer function already described, data may be stored using the transmit FIFO buffer. By setting <CNFG> of the HSC0FCNF register and <FDPX1:0> of the HSC0MOD1 register, the 32-byte send buffer can be enabled. In the UART mode or I/O interface mode, up to 32bytes of data may be stored. If data is to be transmitted with a parity bit in the UART mode, parity check must be performed on the receive side each time a data frame is received. note. Please execute clear the transmit FIFO after the forwarding mode setting and the permission of FIFO of SIO when you use the transmit FIFO buffer. Transmit FIFO Operation c I/O interface mode with HSCLK output (normal mode): The following example describes the case a 4-byte data stream is transmitted: HSC0FCNF <4:0> = 01011: Inhibits continued transmission after reaching the fill level. HSC0TFC <5:0> = 00000: Sets the interrupt to be generated at fill level 0. HSC0TFC <7:6> = 01: Clears transmit FIFO and sets the condition of interrupt generation In this condition, data transmission can be initiated by setting the transfer mode to half duplex, writing 4 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1." When the last transmit data is moved to the send buffer, the transmit FIFO interrupt is generated. When transmission of the last data is completed, the clock is stopped and the transmission sequence is terminated. TX FIFO Send buffer 2 Data 6 Data 5 Data 4 Data 6 Data 3 Data 6 Data 5 Data 4 Data 5 Data 6 Data 6 Data 2 Data 3 Data 4 Data 5 Data 5 Send buffer 1 Data 1 Data 2 Data 3 Data 4 TBEMP INTTX0 TXE Fig. 15-8 Transmit FIFO Operation Serial Channel (HSIO) TMP19A44(rev1.3) 15-14 2010-04-01 TMP19A44 d I/O interface mode with HSCLK input (normal mode): The following example describes the case a 32-byte data stream is transmitted: HSC0FCNF <4:0> = 01001: Allows continued transmission after reaching the fill level. HSC0TFC <5:0> = 000000: Clears the transmit FIFO and sets the condition of interrupt generation. HSC0TFC <7:6> = 11: Sets the interrupt to be generated at fill level 0. In this condition, data transmission can be initiated along with the input clock by setting the transfer mode to half duplex, writing 32 bytes of data to the transmit FIFO, and setting the <TXE> bit to "1." When the last transmit data is moved to the send buffer, the transmit FIFO interrupt is generated. TX FIFO Send buffer 2 Data 6 Data 5 Data 4 Data 6 Data 3 Data 6 Data 5 Data 4 Data 5 Data 6 Data 6 Data 2 Data 3 Data 4 Data 5 Data 5 Send buffer 1 Data 1 Data 2 Data 3 Data 4 TBEMP INTTX0 TXE Fig. 15-9 Transmit FIFO Operation Serial Channel (HSIO) TMP19A44(rev1.3) 15-15 2010-04-01 TMP19A44 Parity Control Circuit If the parity addition bit <PE> of the serial control register HC0CR is set to "1," data is sent with the parity bit. Note that the parity bit may be used only in the 7- or 8-bit UART mode. The <EVEN> bit of HC0CR selects either even or odd parity. Upon data transmission, the parity control circuit automatically generates the parity with the data written to the send buffer (HSC0BUF). After data transmission is complete, the parity bit will be stored in HSC0BUF bit 7 <TB7> in the 7-bit UART mode and in bit 7 <TB8> in the serial mode control register SC0MOD in the 8-bit UART mode. The <PE> and <EVEN> settings must be completed before data is written to the send buffer. Upon data reception, the parity bit for the received data is automatically generated while the data is shifted to receive buffer 1 and moved to receive buffer 2 (HSC0BUF). In the 7-bit UART mode, the parity generated is compared with the parity stored in HSC0BUF <RB7>, while in the 8-bit UART mode, it is compared with the bit 7 <RB8> of the HC0CR register. If there is any difference, a parity error occurs and the <PERR> flag of the HC0CR register is set. In the I/O interface mode, the HC0CR <PERR> flag functions as an under-run error flag, not as a parity flag. Error Flag Three error flags are provided to increase the reliability of received data. 1. Overrun error <OERR>: Bit 4 of the serial control register HC0CR In both UART and I/O interface modes, this bit is set to "1" when an error is generated by completing the reception of the next frame receive data before the receive buffer has been read. If the receive FIFO is enabled, the received data is automatically moved to the receive FIFO and no overrun error will be generated until the receive FIFO is full (or until the usable bytes are fully occupied). This flag is set to "0" when it is read. In the I/O interface HSCLK output mode, no overrun error is generated and therefore, this flag is inoperative and the operation is undefined. 2. Parity error/under-run error <PERR>: Bit 3 of the HC0CR register In the UART mode, this bit is set to "1" when a parity error is generated. A parity error is generated when the parity generated from the received data is different from the parity received. This flag is set to "0" when it is read. In the I/O interface mode, this bit indicates an under-run error. When the double buffer control bit <WBUF> of the serial mode control register HC0MOD2 is set to "1" in the HSCLK input mode, if no data is set to the transmit double buffer before the next data transfer clock after completing the transmission from the transmit shift register, this error flag is set to "1" indicating an under-run error. If the transmit FIFO is enabled, any data content in the transmit FIFO will be moved to the buffer. When the transmit FIFO and the double buffer are both empty, an under-run error will be generated. Because no under-run errors can be generated in the HSCLK output mode, this flag is inoperative and the operation is undefined. If send buffer 2 is disabled, the under-run flag <PERR> will not be set. This flag is set to "0" when it is read. Serial Channel (HSIO) TMP19A44(rev1.3) 15-16 2010-04-01 TMP19A44 3. Framing error <FERR>: Bit 2 of the HC0CR register In the UART mode, this bit is set to "1" when a framing error is generated. This flag is set to "0" when it is read. A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at around the center. Regardless of the <SBLEN> (stop bit length) setting of the serial mode control register 2, HC0MOD2, the stop bit status is determined by only 1 bit on the receive side. Operation mode UART I/O interface (HSCLK input) I/O interface (HSCLK output) Error flag OERR PERR FERR OERR PERR FERR OERR PERR FERR Function Overrun error flag Parity error flag Framing error flag Overrun error flag Underrun error flag (WBUF = 1) Fixed to 0 (WBUF = 0) Fixed to 0 Operation undefined Operation undefined Fixed to 0 Direction of Data Transfer In the I/O interface mode, the direction of data transfer can be switched between "MSB first" and "LSB first" by the data transfer direction setting bit <DRCHG> of the HC0MOD2 serial mode control register 2. Don't switch the direction when data is being transferred. Stop Bit Length In the UART mode transmission, the stop bit length can be set to either 1 or 2 bits by bit 4 <SBLEN> of the HC0MOD2 register. Status Flag If the double buffer function is enabled (HC0MOD2 <WBUF> = "1"), the bit 6 flag <RBFLL> of the HC0MOD2 register indicates the condition of receive buffer full. When one frame of data has been received and transferred from buffer 1 to buffer 2, this bit is set to "1" to show that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read by CPU/DMAC, it is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not be used as a status flag. When double buffering is enabled (HC0MOD2 <WBUF> = "1"), the bit 7 flag <TBEMP> of the HC0MOD2 register indicates that send buffer 2 is empty. When data is moved from send buffer 2 to send buffer 1 (shift register), this bit is set to "1" indicating that send buffer 2 is now empty. When data is set to the send buffer by CPU/DMAC, the bit is cleared to "0." If <WBUF> is set to "0," this bit is insignificant and must not be used as a status flag. Configurations of Send/Receive Buffers UART I/O interface (HSCLK input) I/O interface (HSCLK output) Transmit buffer Receive buffer Transmit buffer Receive buffer Transmit buffer Receive buffer <WBUF> = 0 <WBUF> = 1 Single Double Single Double Single Single Double Double Double Double Double Double software reset Serial Channel (HSIO) TMP19A44(rev1.3) 15-17 2010-04-01 TMP19A44 Software reset is HC0MOD2 <SWRST1:0>"10" "01" SC0MOD0RXEHSC0MOD1<TXE>HC0MOD2TBEMP,RBFLL,TXRUN HC0CROERRPERRFERRand internal circuit is initialized. Other states are maintained. Signal Generation Timing c UART Mode: Receive Side Mode Interrupt generation timing Framing error timing 9-bit 8-bit with parity Around the center of the 1st stop bit Around the center of the stop bit Parity error generation timing Overrun error generation Around the center timing of the stop bit Around the center of the 1st stop bit Around the center of the stop bit Around the center of the last (parity) bit Around the center of the stop bit 8-bit, 7-bit, and 7-bit with parity Around the center of the 1st stop bit Around the center of the stop bit Around the center of the last (parity) bit Around the center of the stop bit Transmit Side Mode Interrupt generation timing (<WBUF> = 0) Interrupt generation timing (<WBUF> = 1) d 9-bit 8-bit with parity 8-bit, 7-bit, and 7-bit with parity Just before the stop Just before the stop bit is Just before the stop bit is sent bit is sent sent Immediately after data is moved to send buffer 1 (just before start bit transmission) Immediately after data is Immediately after data is moved to moved to send buffer 1 send buffer 1 (just before start bit (just before start bit transmission) transmission) I/O interface mode: Receive Side Interrupt generation HSCLK output timing mode (WBUF = 0) HSCLK input mode Interrupt generation HSCLK output timing mode (WBUF = 1) HSCLK input mode Overrun error generation timing HSCLK input mode Immediately after the rising edge of the last HSCLK Immediately after the rising or falling edge of the last HSCLK (for rising or falling edge mode, respectively) Immediately after the rising edge of the last HSCLK (just after data transfer to receive buffer 2) or just after receive buffer 2 is read Immediately after the rising edge or falling edge of the last HSCLK depending on the rising or falling edge triggering mode, respectively (right after data is moved to receive buffer 2) Immediately after the rising or falling edge of the last HSCLK (for rising or falling edge mode, respectively) Transmit Side Interrupt generation HSCLK output timing mode (WBUF = 0) HSCLK input mode Interrupt generation HSCLK output timing mode (WBUF = 1) HSCLK input mode Serial Channel (HSIO) Immediately after the rising edge of the last HSCLK Immediately after the rising or falling edge of the last HSCLK (for rising or falling edge mode, respectively) Immediately after the rising edge of the last HSCLK or just after data is moved to send buffer 1 Immediately after the rising or falling edge of the last HSCLK (for the rising or falling edge mode, respectively) or just after data is moved to send buffer 1 TMP19A44(rev1.3) 15-18 2010-04-01 TMP19A44 Under-run error generation timing HSCLK input mode Immediately after the falling or rising edge of the next HSCLK (for the rising or falling edge triggering mode, respectively) Note 1) Do not modify any control register when data is being sent or received (in a state ready to send or receive). Note 2) Do not stop the receive operation (by setting SC0MOD0 <RXE> = "0") when data is being received. Note 3) Do not stop the transmit operation (by setting HSC0MOD1 <TXE> = "0") when data is being transmitted. Serial Channel (HSIO) TMP19A44(rev1.3) 15-19 2010-04-01 TMP19A44 Detailed Description of Registers As channels 0 to 3 have same register set, only channel 0 is described here. 15.3.1.1 Enable Register 7 HSC0EN 6 5 bit Symbol Read/Write After reset 4 3 2 1 0 SIOE R/W 0 HSIO operation 0: Disable 1: Enable R 0 Always reads "0." Function <SIOE>: It specifies HSIO operation. When HSIO is to be used, be sure to enable HSIO by setting "1" to this register before setting any other registers of the HSIO module. When HSIO operation is disabled, the clock will not be supplied to the HSIO module except for the register part and thus power consumption can be reduced. If HSIO is enabled once and then disabled, any register setting is maintained. 15.3.1.2 TX/ RX Buffer Register 7 6 5 4 3 2 1 0 bit Symbol TB7/RB7 TB6/RB6 TB5/RB5 TB4/RB4 TB3/RB3 TB2/RB2 TB1/RB1 TB0/RB0 HSC0BUF R/W Read/Writ e After reset 0 0 0 0 0 0 0 0 TB7~0 : TX buffer/ FIFO RB7~0 : RX buffer/ FIFO Function The buffer register (HSC0BUF) functions as TX buffer at writing and RX buffer at reading. <TB7:0> TX buffer (only for writing) <RB7:0> RX buffer (only for reading) Serial Channel (HSIO) TMP19A44(rev1.3) 15-20 2010-04-01 TMP19A44 15.3.1.3 Control Register 7 RB8 bit Symbol HSC0CR R Read/Writ e After reset 0 Receive data Function 6 EVEN Bit 8 (for UART) 5 PE R/W 0 4 OERR (for UART) 0: Odd 1: Even 2 FERR 1 HSCLKS R (cleared to "0" when read) 0 Parity 3 PERR Add parity (for UART) 0: Disable 0 0 0 0: Normal operation 1: Error Overrun 1: Enable Parity/ underrun Framing 0 IOC R/W 0 0 0: HSCLK0 (for I/O interfa ce) 1: HSCLK0 0: Baud rate generator 1: HSCLK0 pin input <RB8>: Indicates 9th received bit in 9 bit UART mode. <EVEN>: Specifies parity condition. "0": Odd parity "1": Even parity Parity is available for 7 bit/ 8 bit UART mode. <PE>: Enables or disables parity. Parity is available for 7 bit/ 8 bit UART mode. <OERR>: <PERR>: <FERR>: Indicates error flags (overrun error flag, parity error/ underrun error flag and framing error flag). (Note) <HSCLKS>: <IOC>: (Note) Clock edge selection for data transmission/ reception "0": Data send/receive at rising edges of HSCLK0 "1": Data send/receive at falling edges of HSCLK0 I/O interface input clock selection. "0": Baud rate generator "1": HSCLK0 pin input Every error flag is cleared when read. Serial Channel (HSIO) TMP19A44(rev1.3) 15-21 2010-04-01 TMP19A44 15.3.1.4 Mode Control Register 0 7 TB8 bit Symbol HSC0MOD0 6 CTSE 5 RXE 4 WU 2 SM0 1 SC1 0 SC0 0 0 0 0 R/W Read/Writ e 0 After reset Send data Bit 8 Function 3 SM1 0 Handshake function control 0: Disables CTS 1: Enables CTS 0 Receive control 0 Wake-up function 0: Disable Serial transfer mode 00: I/O interface mode 0: Disables 01: 7-bit length reception UART mode 1: Enable 1: Enables 10: 8-bit length reception UART mode 11: 9-bit length UART mode Serial transfer clock (for UART) 00: Timer TB3OUT 01: Baud rate generator 10: Internal fSYS/2 clock 11: External clock (HSCLK0 input) <TB8>: Sets 9th transmit bit in 9 bit UART mode. <CTSE>: Controls handshake function. Setting this bit to "1" enables handshake function using H CTS pin. <RXE>: Executes receive control. (Note) Enable this bit after setting each mode register (HSC0MOD0, HSC0MOD1 and HC0MOD2). <WU>: Controls wake-up function. This function is available only for 9 bit UART mode. Setting this bit is ignored in other modes. 0 1 9 bit UART mode An interrupt is generated whenever data is received An interrupt is generated when 9th received bit is "1". Others don't care <SM1:0>: Specifies transfer mode. <SC1:0>: Specifies transfer clock in UART mode. In the I/O interface mode, the serial control register (HC0CR) is used for clock. (Note) With <RXE> set to "0," set each mode register (HSC0MOD0, HSC0MOD1 and HC0MOD2). Then set <RXE> to "1." Serial Channel (HSIO) TMP19A44(rev1.3) 15-22 2010-04-01 TMP19A44 15.3.1.5 Mode Control Register 1 bit Symbol HSC0MOD1 Read/Write After reset Function 7 6 5 4 3 2 1 I2S0 FDPX1 FDPX0 TXE SINT2 SINT1 SINT0 R/W 0 IDLE 0: Stop 1: Start R/W R/W R/W 0 0 0 Transfer mode setting Transmit 00: Transfer prohibited control 0: Disable 01: Half duplex (RX) 1: Enable 10: Half duplex (TX) 11: Full duplex R/W R/W R/W 0 0 0 Interval time of continuous transmission (for I/O interface) 000: None 100: 8SCLK 001: 1SCLK 101:16SCLK 010: 2SCLK 110: 32SCLK 011: 4SCLK 111: 64SCLK 0 R/W 0 Write "0." <I2S0>: Specifies the IDLE mode operation. <FDPX1:0>: Configures the transfer mode in the I/O interface mode. Also configures the FIFO if it is enabled. In the UART mode, it is used only to specify the FIFO configuration. <TXE>: This bit enables transmission and is valid for all the transfer modes. (Note) If disabled while transmission is in progress, transmission is inhibited only after the current frame of data is completed for transmission. <SINT2:0>: This parameter is valid for I/O interface mode when a clock is not input from HSCLK0 pin (invalid for other modes). Specifies the interval time of continuous transmission when double buffering or FIFO is enabled in the I/O interface mode. (Note) Enable <TXE> bit after setting other bits. Serial Channel (HSIO) TMP19A44(rev1.3) 15-23 2010-04-01 TMP19A44 15.3.1.6 Mode Control Register 2 bit Symbol HSC0MOD2 7 6 5 4 3 2 1 0 TBEMP RBFLL TXRUN SBLEN DRCHG WBUF SWRST1 SWRST0 0 Soft reset 0 Read/Write After reset Function R 1 Send buffer empty flag 0: full 0 Receive buffer full flag 0: Empty 1: Empty 1: full R/W 0 0 In Stop bit transmissi (for UART) on flag 0: 1-bit 0: Stop 1: 2-bit 1: Start 0 Setting transfer direction 0 W-buffer 0: Disable 1: Enable Overwrite "01" on "10" to reset 0: LSB first 1: MSB first <TBEMP>: If double buffering is disabled, this flag is insignificant. This flag shows that the send double buffers are empty. When data in the send double buffers is moved to the send shift register and the double buffers are empty, this bit is set to "1." Writing data again to the double buffers sets this bit to "0." <RBFLL>: If double buffering is disabled, this flag is insignificant. This is a flag to show that the receive double buffers are full. When a receive operation is completed and received data is moved from the receive shift register to the receive double buffers, this bit changes to "1" while reading this bit changes it to "0." <TXRUN>: This is a status flag to show that data transmission is in progress. <TXRUN> and <TBEMP> show the following status. <TXRUN> 1 0 <TBEMP> 1 0 Status Transmission in progress Transmission completed Wait state for transmission with next data in a send buffer. <SBLEN>: This specifies the length of stop bit transmission in the UART mode. On the receive side, the decision is made using only a single bit regardless of the <SBLEN> setting. <DRCHG>: Specifies the direction of data transfer in the I/O interface mode. In the UART mode, you need to fix it to LSB first. <WBUF>: This parameter enables or disables the send/receive buffers to send (in both HSCLK output/input modes) and receive (in HSCLK output mode) data in the I/O interface mode and to transmit data in the UART. In all other modes, double buffering is enabled when receiving data in I/O interface mode (HSCLK input) and UART mode regardless of the <WBUF> setting. <SWRST1:0>: Overwriting "01" in place of "10" generates a software reset. When this software reset is executed, the following bits and their internal circuits are initialized. (Note 1, 2 and 3) Register name HSC0MOD0 HSC0MOD1 HSECMOD2 HC0CR Serial Channel (HSIO) Bit RXE TXE TBEMP,RBFLL,TXRUN, OERR,PERR,FERR TMP19A44(rev1.3) 15-24 2010-04-01 TMP19A44 (Note 1) While data transmission is in progress, any software reset operation must be executed twice in succession. (Note 2) To complete software reset, it takes 2 clocks after executing an instruction. Executing SYNC and NOP instructions after software reset is recommended. (Note 3) When software reset is executed, the bits listed in the <SWRST1:0> description are initialized. It requires resetting of the mode registers and control register. Serial Channel (HSIO) TMP19A44(rev1.3) 15-25 2010-04-01 TMP19A44 15.3.1.7 Baud Rate Generator Control Register (HBR0CR) Baud Rate Generator Control Register 2 (HBR0ADD) 7 bit Symbol HBR0CR Read/Writ e After reset 4 HBR0S4 0 "Write "0." 0 0 0 Divide ratio "N" 000000: 64 000001: 1 000010: 2 : 111111: 63 N+(16-K)/16 divider function 0: Disable 1: Enable 7 6 5 bit Symbol Read/Writ e After reset 4 0 3 HBR0K3 R 0 Always reads "0." Function <HRB0ADDE>: 3 HBR0S3 2 HBR0S2 1 HBR0S1 0 HBR0S0 0 0 0 R/W Function BR0ADD 6 5 HBR0AD HBR0S5 DE 2 1 HBR0K2 HBR0K1 R/W 0 HBR0K0 0 0 0 0 Specify K for the "N + (16 - K)/16" division 0000: Setting prohibited 0001: K=1 0010: K=2 : 1111: K=15 Enables or disables N+(16-K)/16 division function. This function is available only for UART mode. <HRB0S5:0>: Sets divide ratio "N" of the baud rate generator. <HRB0K3:0>: Specifies K for the "N + (16 - K)/16" division. Divide ratio of baud rate generator is set in the above two registers. Table 15.3 shows the divide ratio configuration. Table 15.3 Divide ratio setting HBR0ADDE=0 HBR0S HBR0K Divide ratio Serial Channel (HSIO) HBR0ADDE=1 (Note 1) (available for UART mode) Set divide ratio "N" (Note 2, 3) No setting required Set "K" (Note 4) N + (16 - K) N 16 TMP19A44(rev1.3) 15-26 2010-04-01 TMP19A44 (Note 1) To use the "N + (16 - K)/16" division function, be sure to set HBR0ADDE <HBR0ADDE> to "1" after setting the K value (K = 1 to 15) to HBR0ADD <HBR0K3:0>. (Note 2) The division ratio "1" ("000001") of the baud rate generator can be specified only when the "N + (16 - K)/16" division function is not used In the UART mode. double buffering is used in the I/O interface mode. (Note 3) To use the "N + (16 - K)/16" division function, neither the division ratio "1" ("0001") nor "16" ("0000") can be set. (Note 4) "0" cannot be set as K value. Serial Channel (HSIO) TMP19A44(rev1.3) 15-27 2010-04-01 TMP19A44 15.3.1.8 FIFO Configuration Register bit Symbol HSC0FCNF 7 6 5 4 Reserved Reserved Reserved RFST Read/Write After reset 3 2 1 0 TFIE RFIE RXTXCNT CNFG 0 TX interrupt for TX FIFO 0: Disable 0 RX interrupt for RX FIFO 0: Disable 0 Automatic disable of RXE/TXE 0: None 0 FIFO Enable 0: Disable R/W 0 0 0 Be sure to write "000." Function 0 Bytes used in RX FIFO 0: Maximum 1: Same as 1: Enable Fill level of RX FIFO 1: Enable 1: Enable 1: Auto disable <RFST>: Specifies bytes used in RX FIFO. (Note) 0: The maximum number of bytes of the FIFO configured is available. (See description of <CNFG> bit.) 1: Same as the fill level for receive interrupt generation specified by HSC0RFC <RIL1:0>. <TFIE>: When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter. <RFIE>: When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter. <RXTXCNT>: The function to automatically disable RXE/TXE bits is disabled. If "1" is set, it functions as shown below according to the communication method configured (the communication method can be set in the mode control register 1 HSC0MOD1<FDPX1:0>). Half duplex RX Half duplex TX Full duplex <CNFG>: This parameter is to enable FIFO. Setting "1" enables FIFO. If enabled, the HSCOMOD1 <FDPX1:0> setting automatically configures FIFO as follows: (the communication method can be set in the mode control register 1 HSC0MOD1<FDPX1:0>). Half duplex RX Half duplex TX Full duplex (Note) When the RX FIFO is filled up to the specified number of valid bytes, HSC0MOD0<RXE> is automatically set to "0" to inhibit further reception. When the TX FIFO is empty, HSC0MOD1<TXE> is automatically set to "0" to inhibit further transmission. When either of the above two conditions is satisfied, TXE/RXE are automatically set to "0" to inhibit further transmission and reception. RX FIFO 32byte TX FIFO 32byte RX FIFO 16byteTX FIFO 16byte Regarding TX FIFO, the maximum number of bytes being configured is always available. The available number of bytes is the bytes already written to the TX FIFO. Serial Channel (HSIO) TMP19A44(rev1.3) 15-28 2010-04-01 TMP19A44 15.3.1.9 Receive FIFO Configuration Register bit Symbol HSC0RFC Read/Writ e After reset 7 RFCS 6 RFIS 5 W R/W R 0 0 0 Clear RX FIFO Function 1: Clear Select interrupt generati on condition Always reads "0." Always reads "0." 4 RIL4 3 RIL3 2 RIL2 1 RIL1 0 RIL0 0 0 R/W 0 0 0 FIFO fill level to generate RX interrupts (0_0000::32byte) 0_0001:1byte 0_0010:2byte To 0_1110:30byte 1_1111:31byte 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <RFCS>: Clears RX FIFO. Writing "1" clears FIFO. If not, "0" is read. <RFIS>: Selects interrupt generation condition. 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <RIL1:0>: Specifies FIFO fill level. Serial Channel (HSIO) TMP19A44(rev1.3) 15-29 2010-04-01 TMP19A44 15.3.1.10 Transmit FIFO Configuration Register bit Symbol HSC0TFC Read/Writ e After reset 7 TFCS 6 TFIS W R/W 0 Clear TX FIFO Function 1: Clear Always reads "0." 0 5 TIL5 4 TIL4 3 TIL3 2 TIL2 1 TIL1 0 TIL0 0 0 0 R R/W 0 0 0 FIFO fill level to generate TX interrupts Select interrupt (00_0000:Empty) generati on 00_0001:1byte 00_0010:2byte condition To 01_1111:31byte 10_0000:32byte 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <TFCS>: Clears TX FIFO. Writing "1" clears FIFO. If not, "0" is read. <TFIS>: Selects interrupt generation condition. 0: An interrupt is generated when the specified fill level is reached. 1: An interrupt is generated when the specified fill level is reached or if the specified fill level has been exceeded at the time data is read. <TIL1:0>: Specifies FIFO fill level. Serial Channel (HSIO) TMP19A44(rev1.3) 15-30 2010-04-01 TMP19A44 15.3.1.11 Receive FIFO Status Register 7 ROR bit Symbol HSC0RST 5 RLVL5 4 RLVL4 After reset 1: Generated 2 RLVL2 1 RLVL1 0 RLVL0 0 0 0 R 0 RX FIFO Overrun 0 Always reads "0." 0 0 Status of RX FIFO fill level (00_0000:32byte) 00_0000:32byte 00_0001:1byte 00_0010:2byte To 01_1110:30byte 01_1111:31byte <ROR>: Flag for RX FIFO overrun. This parameter is set to "1" if overrun occurs (note). <RLVL2:0>: Indicates status of RX FIFO fill level. (Note) 3 RLVL3 R Read/Writ e Function 6 The <ROR> bit is cleared to "0" when receive data is read from the HSC0BUF register. Serial Channel (HSIO) TMP19A44(rev1.3) 15-31 2010-04-01 TMP19A44 15.3.1.12 Transmit FIFO Status Register 7 HSC0TST bit Symbol TUR Read/Writ e R After reset 1: Generated . Cleared to "0" when FIFO is written by received data. 5 4 0 Always reads "0." 0 2 0 TLVL2 TLVL1 TLVL0 0 0 0 0 Status of TX FIFO fill level (00_0000:Empty) 00_0001:1byte 00_0010:2byte To 01_1111:31byte 10_0000:32byte <TUR>: Flag for TX FIFO underrun. This parameter is set to "1" if underrun occurs (note). <TLVL2:0>: Indicates status of TX FIFO fill level. (Note) 3 R 1 TX FIFO Underrun Function 6 The <TUR> bit is cleared to "0" when receive data is read from the HSC0BUF register. Serial Channel (HSIO) TMP19A44(rev1.3) 15-32 2010-04-01 TMP19A44 15.4 Operation of Each Circuit (Channel 0) As channels 0 to 3 operate identically, only channel 0 is described here. 15.4.1 Serial Clock Generation Block This block generates basic transmit and receive clocks. In this block, clock is determined according to baud rate generator and specified mode and register setting. 15.4.1.1 Clock Selection Circuit Serial clock is determined according to mode and register setting specified. Specify mode in the mode control register 0 (HSC0MOD0<SM1:0>). To use I/O interface mode, clock is specified in the control register HC0CR. To use UART mode, clock is specified in the mode control register0 (HSC0MOD0<SC1:0>). Table 15.4 and Table 15.5 show details of clock selection in I/O interface mode and UART mode respectively. Table 15.4 Clock selection in I/O interface mode Mode Input/ output Clock edge selection HSC0MOD0<SM1:0> selection HC0CR<HSCLKS> HC0CR<IOC> HSCLK output (Fixed to rising edge) I/O interface mode Rising edge HSCLK input Falling edge Clock selection Baud rate generator output divided by 2 Rising edge of HSCLK input Falling edge of HSCLK input Table 15.5 Clock selection in UART mode Mode Clock selection HSC0MOD0<SM1:0> HSC0MOD0<SC1:0> Timer output fsys UART mode fsys/2 HSCLK input Serial Channel (HSIO) TMP19A44(rev1.3) 15-33 2010-04-01 TMP19A44 15.4.1.2 Baud Rate Generator The baud rate generator generates transmit and receive clocks. (1) Input clock The input clock selection is made by setting the baud rate generator control register, HBR0CR <BR0CK5:0>. Specify the divide ratio of the output clock with the baud rate generator control register HBR0CR<BR0ADDE><BR0S3:0> and the baud rate generator control register 2 HBR0ADD<BR0K3:0>. (2) UART mode Table 15.6 UART mode HBR0CR<BR0ADDE> HBR0ADD<BR0K3:0> "0" Setting invalid "1" N+ (16 - K) division Setting valid Set divide ratio "K" K=1,2,3...15 HBR0CR<BR0S3:0> Setting valid Set divide ratio "N" N=1,2,3...64 Setting valid Set divide ratio "N" N=2,3...63 16 Serial Channel (HSIO) TMP19A44(rev1.3) 15-34 N=1,64: setting prohibited 2010-04-01 TMP19A44 16. Serial Bus Interface (SBI) The TMP19A44 contains a Serial Bus Interface (SBI) channel, which has the following two operating modes: * * 2 I C bus mode (with multi-master capability) Clock-synchronous 8-bit SIO mode 2 In the I C bus mode, the SBI is connected to external devices via PC4 (SDA) and PC5 (SCL). In the clocksynchronous 8-bit SIO mode, the SBI is connected to external devices via PC6 (SCK), PC4 (SO) and PC5 (SI). The following table shows the programming required to put the SBI in each operating mode. Port open drain output PCODE <6:4> = 11 I2C bus mode Clocksynchronous 8-bit SIO mode 16.1 PCODE <6:4> = x0x Port control register Port function register PCCR<6:4> = x11 PCFC1<6:4> = 011 PCCR<6:4> = 101 (clock output) PCCR<6:4> = 001(clock input) PCFC1<6:4> = 111 Configuration The configuration is shown in Fig. 16.1. INTS0 interrupt request SCL SCK SIO clock control fsys/2 PC6 (SCK) Input/ output control Frequency divider Transfer control circuit 2 Noise canceller I C bus clock synchronization + control (SO/SDA) SI PC5 2 SBICR2/ SBISR SBI status register SO data control Shift register SBI control register 2/ PC4 SIO I2CAR 2 SBIDBR I C bus address register SBI data buffer register I C bus data control SBICR0,1 (SI/SCL) Noise canceller SDA SBIBR0 SBI control registers SBI baud rate register 0 0 and 1 Fig. 16.1 SBI Block Diagram Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-1 2010-04-01 TMP19A44 16.2 Control The following registers control the serial bus interface and provide its status information for monitoring. * Serial bus interface control register 0 (SBICR0) * Serial bus interface control register 1 (SBICR1) * Serial bus interface control register 2 (SBICR2) * Serial bus interface buffer register (SBIDBR) * I2C bus address register (I2CAR) * Serial bus interface status register (SBISR) * Serial bus interface baud rate register 0 (SBIBR0) The functions of these registers vary, depending on the mode in which the SBI is operating. For a detailed 2 description of the registers, refer to "16.4 Control in the I C Bus Mode" and "16.7 Control in the Clocksynchronous 8-bit SIO Mode." I2C Bus Mode Data Formats 16.3 Fig. 16.2 shows the data formats used in the I2C bus mode. (a) Addressing format 8 bits S Slave address 1 R A / C W K Data Once (b) S Data 1 A C P K Repeated Slave address 1 R A / C W K Once 1 to 8 bits 1 A C S K Data 8 bits Slave address Repeated 1 R A / C W K Once 1 to 8 bits Data 1 A C P K Repeated Free data format (master-transmitter to slave-receiver) 8 bits Data S Once Note: 1 to 8 bits Addressing format (with repeated start condition) 8 bits (c) 1 A C K 1 to 8 bits S: R/W : ACK: P: 1 A C K 1 to 8 bits Data 1 A C K 1 to 8 bits Data 1 A C P K Repeated Start condition Direction bit Acknowledge bit Stop condition Fig. 16.2 I2C Bus Mode Data Formats Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-2 2010-04-01 TMP19A44 16.4 Control Registers in the I2C Bus Mode The following registers control the serial bus interface (SBI) in the I2C bus mode and provide its status information for monitoring. Serial bus interface control register 0 Bit symbol SBICR0 Read/Write (0xFF00_4B00) After reset Function 7 SBIEN R/W 0 SBI operation 0: Disable 1: Enable 15 6 5 4 1 0 11 10 9 8 19 18 17 16 27 26 25 24 This can be read as "0." 14 13 12 R 0 After reset This can be read as "0." 23 22 21 20 Bit symbol Read/Write R 0 After reset Function 2 R 0 Bit symbol Read/Write Function 3 This can be read as "0." 31 30 29 28 Bit symbol Read/Write R 0 After reset Function This can be read as "0." <SBIEN>: To use the SBI, enable the SBI operation ("1") before setting each register in the SBI module. Fig. 16.3 I2C Bus Mode Register Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-3 2010-04-01 TMP19A44 Serial bus interface control register 1 SBICR1 Bit symbol (0xFF00_4B04) Read/Write After reset Function 7 BC2 6 BC1 5 BC0 4 ACK R/W 0 0 0 Select the number of bits per transfer (Note 1) R/W 0 3 2 SCK2 R 1 Acknowled This can gment be read clock as "1." 1 SCK1 0 SCK0/ SWRMON R/W R/W 0 0 1 Select internal SCL output clock frequency (Note 2) and reset monitor 0: Not generate 1: Generate 15 14 13 12 Bit symbol Read/Write This can be read as "0." 23 22 21 20 Bit symbol Read/Write This can be read as "0." 31 30 29 28 Bit symbol Read/Write 8 19 18 17 16 27 26 25 24 R 0 After reset Function 9 R 0 After reset Function 10 R 0 After reset Function 11 This can be read as "0." <Bit 2:0><SCK2:0> : Selects internal SCL output clock frequency. On writing <SCK2:0>: Select internal SCL output clock frequency 000 n=5 384 kHz 001 n=6 294 kHz System clock: fsys 010 n=7 200 kHz (=80 MHz) 011 n=8 121 kHz Clock gear: fc/1 100 n=9 68 kHz 101 n=10 36 kHz Frequency = [ Hz ] 110 n=11 18 kHz reserved 111 <Bit 0>< SWRMON:0> : Software reset status monitor On reading <SWRMON>: Software reset status monitor 0 Software reset operation is in progress. 1 Software reset operation is not in progress. <Bit 7:5><BC2:0>Select the number of bits per transfer <BC2:0> 000 001 010 011 100 101 110 111 Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-4 <ACK> = 0 # of clock Data cycles length 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 <ACK> = 1 # of clock Data cycles length 9 8 2 1 3 2 4 3 5 4 6 5 7 6 8 7 2010-04-01 TMP19A44 (Note 1) Clear <BC2:0> to "000" before switching the operation mode to the clock-synchronous 8-bit SIO mode. (Note 2) For details on the SCL line clock frequency, refer to "3.12.5 (3) Serial Clock." (Note 3) After a reset, the <SCK0/SWRMON> bit is read as "1." However, if the SIO mode is selected at the SBICR2 register, the initial value of the <SCK0> bit is "0." Fig. 16.4 I2C Bus Mode Register Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-5 2010-04-01 TMP19A44 Serial bus interface control register 2 Bit symbol SBICR2 Read/Write (0xFF00_4B10) After reset Function 7 MST 6 TRX 5 BB 4 PIN 3 2 SBIM1 SBIM0 W (Note 2) 0 0 W 0 0 0 Select master/slav e 0: Slave Select transmit/ receive 0: Receive 1: Master 1: Transmit Start/stop condition generation 0: Stop condition generated 1: Start condition 1 Clear INTS0 Select serial bus interface operating mode interrupt (Note 2) request 0: - 00: Port mode 1: Clear interrupt 01: SIO mode 10: I2C bus mode request 11: (Reserved) 1 0 SWRST1 SWRST0 W (Note 1) 0 0 Software reset generation Write "10" followed by "01" to generate a reset. generated 15 14 13 12 Bit symbol Read/Write This can be read as "0." 23 22 21 20 Bit symbol Read/Write This can be read as "0." 31 30 29 28 Bit symbol Read/Write 8 19 18 17 16 27 26 25 24 R 0 After reset Function 9 R 0 After reset Function 10 R 0 After reset Function 11 This can be read as "0." <Bit 1:0><SCK2:0>: Write "10" followed by "01" to generate a reset. <Bit 3:2><SBIM1:0>: Select serial bus interface operating mode Select serial bus interface operating mode (Note 2) 00 Port mode (Serial bus interface output disabled) 01 Clock-synchronous 8-bit SIO mode 10 I2C bus mode 11 <Bit 4><PIN> <Bit 5><BB> <Bit 6><TRX> <Bit 7><MST> (Reserved) : Clear INTS0 interrupt request : Start/stop condition generation : Select transmit/ receive : Select master/slave (Note 1) Reading this register causes it to function as the SBISR register. (Note 2) Ensure that the bus is free before switching the operating mode to the port mode. Ensure that the port is at the "H" level before switching the operating mode from the port mode to the I2C bus or clock-synchronous 8-bit SIO mode. (Note 3) Ensure that serial transfer is completed before switching the mode. Fig. 16.5 I2C Bus Mode Register Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-6 2010-04-01 TMP19A44 Table 16.1 Base Clock Resolution @fsys = 80 MHz Serial Bus Interface (SBI) Clock gear value <GEAR2:0> Base clock resolution 000 (fc) fsys/22 (0.05 s) 100 (fc/2) fsys/23 (0.1 s) 101 (fc/4) fsys/24 (0.2 s) 110 (fc/8) fsys/25 (0.4 s) 111 (fc/16) fsys/25 (0.8 s) TMP19A44 (rev1.3) 16-7 2010-04-01 TMP19A44 Serial bus interface status register 7 bit Symbol MST SBISR (0xFF00_4B10) Read/Write After reset 0 Master/ Function slave selection monitor 0: Slave 6 TRX 5 BB 0 Transmit/ receive selection monitor 0: Receive 0 14 1 0 0 0 0 Arbitration lost detection 0: - 1: Busy 0: Interrupt request generated 1: Interrupt request cleared 1: "1" 1: 1: Detected 1: Detected Detected (When the General call is detected, it is set.) 13 12 11 Slave address match detection 0: - General call detection 0: - 10 9 Last received bit monitor 0: "0" 8 R 0 This can be read as "0". 23 22 21 20 19 18 17 16 27 26 25 24 R 0 After reset This can be read as "0". 31 30 29 Bit symbol Read/Write 28 R 0 After reset (Note) 0 LRB INTS0 interrupt request monitor Bit symbol Read/Write Function 1 AD0 2 After reset Function 2 AAS I C bus state monitor 0: Free Bit symbol Read/Write Function 3 AL R 1: Master 1: Transmit 15 4 PIN This can be read as "0". Writing to this register causes it to function as SBICR2. Fig. 16.6 I2C Bus Mode Register Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-8 2010-04-01 TMP19A44 Serial bus interface baud rate register 0 SBIBR (0xFF00_4B14) 7 6 bit Symbol I2SBI0 Read/Write R R/W After reset 1 0 This can IDLE Function be read as 0: Stop "0". 1: Operate 15 14 5 3 2 1 R 1 13 12 11 0 R/W 0 Make sure that you write "0." (Note) This can be read as "0". bit Symbol Read/Write After reset Function This can be read as "0". 23 22 21 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 29 bit Symbol Read/Write After reset Function This can be read as "0". (Note) 4 10 9 8 R 0 20 19 18 17 16 27 26 25 24 1 DB1 0 DB0 R 0 28 R 0 This is read as "1" in the SIO mode. Serial bus interface data buffer register SBIDBR (0xFF00_4B08) 7 DB7 bit Symbol Read/Write After reset 15 6 DB6 14 5 DB5 13 bit Symbol Read/Write After reset Function This can be read as "0". 23 22 21 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 29 bit Symbol Read/Write After reset (Note) 4 3 2 DB4 DB3 DB2 R (Receive)/W (Transmit) 0 12 11 10 9 8 R 0 20 19 18 17 16 27 26 25 24 R 0 28 R 0 Transmit data must be written to this register, with bit 7 being the most-significant bit (MSB). Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-9 2010-04-01 TMP19A44 I2C bus address register I2CAR (0xFF00_4B0C) 7 6 5 4 3 2 bit Symbol SA6 SA5 SA4 SA3 SA2 SA1 Read/Write R/W After reset 0 0 0 0 0 0 Function Set the slave address when the SBI acts as a slave device. 15 14 13 bit Symbol Read/Write After reset Function This can be read as "0". 23 22 21 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 29 bit Symbol Read/Write After reset <Bit 0><ALS> 12 11 10 1 SA0 0 9 0 ALS 0 Specify address recognition mode 8 R 0 20 19 18 17 16 27 26 25 24 R 0 28 R 0 : Specify address recognition mode 0 1 Recognizes the slave address. Does not recognize slave address. (Note) Please set the bit of I2C bus address register I2CAR to "0" about 0< ALS >, except when you use the free data format. It operates as a free data format when setting it to "1", it fixes to the transmission at the master, and the direction of forwarding is fixed to the reception at the slave. Fig. 16.7 I2C Bus Mode Register Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-10 2010-04-01 TMP19A44 Control Registers in the I2C Bus Mode 16.5 16.5.1 Setting the Acknowledgement Mode Setting SBICR1<ACK> to "1" selects the acknowledge mode. When operating as a master, the SBI adds one clock for acknowledgment signals. As a transmitter, the SBI releases the SDA pin during this clock cycle to receive acknowledgment signals from the receiver. As a receiver, the SBI pulls the SDA pin to the "L" level during this clock cycle and generates acknowledgment signals. Setting <ACK> to "0" selects the non-acknowledgment mode. When operating as a master, the SBI does not generate clock for acknowledgement signals. 16.5.2 Setting the Number of Bits per Transfer SBICR1 <BC2:0> specifies the number of bits of the next data to be transmitted or received. Under the start condition, <BC2:0> is set to "000," causing a slave address and the direction bit to be transferred in a packet of eight bits. At other times, <BC2:0> keeps a previously programmed value. 16.5.3 c Serial Clock Clock source SBICR1 <SCK2:0> specifies the maximum frequency of the serial clock to be output from the SCL pin in the master mode. tHIGH tLOW n-1 tLOW = 2 /(fsys/2) + 58/(fsys/2) n-1 tHIGH = 2 /(fsys/2) + 12/(fsys/2) fscl = 1/(tLow + tHIGH) = fsys/2 1/fscl SBI0CR1 <SCK2:0> 000 001 010 011 100 101 110 n 5 6 7 8 9 10 11 n 2 + 70 Fig. 16.3 Clock Source The highest speeds in the standard and high-speed modes are specified to 100KHz and 400KHz respectively in the communications standards. Note that the internal SCL clock frequency is determined by the fsys used and the calculation formula shown above. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-11 2010-04-01 TMP19A44 d Clock Synchronization The I2C bus is driven by using the wired-AND connection due to its pin structure. The first master that pulls its clock line to the "L" level overrides other masters producing the "H" level on their clock lines. This must be detected and responded by the masters producing the "H" level. Clock synchronization assures correct data transfer on a bus that has two or more masters. For example, the clock synchronization procedure for a bus with two masters is shown below. Wait for high-level period counting Start high-level period counting Internal SCL output (Master A) Internal SCL output (Master B) Reset high-level period counting SCL line a b c Fig. 16.4 Example of Clock Synchronization At point a, Master A pulls its internal SCL output to the "L" level, bringing the SCL bus line to the "L" level. Master B detects this transition, resets its "H" level period counter, and pulls its internal SCL output level to the "L" level. Master A completes counting of its "L" level period at point b, and brings its internal SCL output to the "H" level. However, Master B still keeps the SCL bus line at the "L" level, and Master A stops counting of its "H" level period counting. After Master A detects that Master B brings its internal SCL output to the "H" level and brings the SCL bus line to the "H" level at point c, it starts counting of its "H" level period. This way, the clock on the bus is determined by the master with the shortest "H" level period and the master with the longest "L" level period among those connected to the bus. 16.5.4 Slave Addressing and Address Recognition Mode When the SBI is configured to operate as a slave device, the slave address <SA6:0> and <ALS> must be set at I2CAR. Setting <ALS> to "0" selects the address recognition mode. 16.5.5 Configuring the SBI as a Master or a Slave Setting SBICR2<MST> to "1" configures the SBI to operate as a master device. Setting <MST> to "0" configures the SBI as a slave device. <MST> is cleared to "0" by the hardware when the stop condition has been detected on the bus or when arbitration has been lost. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-12 2010-04-01 TMP19A44 16.5.6 Configuring the SBI as a Transmitter or a Receiver Setting SBICR2 <TRX> to "1" configures the SBI as a transmitter. Setting <TRX> to "0" configures the SBI as a receiver. In the slave mode, the SBI receives the direction bit ( R/ W ) from the master device on the following occasions: * when data is transmitted in the addressing format * when the received slave address matches the value specified at I2CCR * when a general-call address is received; i.e., the eight bits following the start condition are all zeros If the value of the direction bit ( R/ W ) is "1," <TRX> is set to "1" by the hardware. If the bit is "0," <TRX> is set to "0." As a master device, the SBI receives acknowledgement from a slave device. If the direction bit of "1" is transmitted, <TRX> is set to "0" by the hardware. If the direction bit is "0," <TRX> changes to "1." If the SBI does not receive acknowledgement, <TRX> retains the previous value. <TRX> is cleared to "0" by the hardware when the stop condition has been detected on the bus or when arbitration has been lost. 16.5.7 Generating Start and Stop Conditions When SBISR<BB> is "0," writing "1" to SBICR2 <MST, TRX, BB, PIN> causes the SBI to generate the start condition on the bus and output 8-bit data. <ACK> must be set to "1" in advance. SCL line SDA line 1 2 3 4 5 6 7 A6 A5 A4 A3 A2 A1 A0 Slave address and direction bit Start condition 8 9 R/W Acknowledgment signal Fig. 16.5 Generating the Start Condition and a Slave Address When <BB> is "1," writing "1" to <MST, TRX, PIN> and "0" to <BB> causes the SBI to start a sequence for generating the stop condition on the bus. The contents of <MST, TRX, BB, and PIN> should not be altered until the stop condition appears on the bus. SCL line SDA line Stop condition Fig. 16.6 Generating the Stop Condition SBISR<BB> can be read to check the bus state. <BB> is set to "1" when the start condition is detected on the bus (the bus is busy), and set to "0" when the stop condition is detected (the bus is free). Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-13 2010-04-01 TMP19A44 16.5.8 Interrupt Service Request and Release When a serial bus interface interrupt request (INTS0) is generated, SBICR2 <PIN> is cleared to "0." While <PIN> is "0," the SBI pulls the SCL line to the "L" level. After transmission or reception of one data word, <PIN> is cleared to "0." It is set to "1" when data is written to or read from SBIDBR. It takes a period of tLOW for the SCL line to be released after <PIN> is set to "1." In the address recognition mode (<ALS> = "0"), <PIN> is cleared to "0" when the received slave address matches the value specified at I2CAR or when a general-call address is received; i.e., the eight bits following the start condition are all zeros. When the program writes "1" to SBICR2<PIN>, it is set to "1." However, writing "0" does clear this bit to "0." 16.5.9 Serial Bus Interface Operating Modes SBICR2 <SBIM1:0> selects an operating mode of the serial bus interface. <SBIM1:0> must be set to "10" to configure the SBI for the I2C bus mode. Make sure that the bus is free before switching the operating mode to the port mode. 16.5.10 Lost-arbitration Detection Monitor The I2C bus has the multi-master capability (there are two or more masters on a bus), and requires the bus arbitration procedure to ensure correct data transfer. A master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no start condition occurring on the SDA and SCL lines. The I2C-bus arbitration takes place on the SDA line. The arbitration procedure for two masters on a bus is shown below. Up until point a, Master A and Master B output the same data. At point a, Master A outputs the "L" level and Master B outputs the "H" level. Then Master A pulls the SDA bus line to the "L" level because the line has the wired-AND connection. When the SCL line goes high at point b, the slave device reads the SDA line data, i.e., data transmitted by Master A. At this time, data transmitted by Master B becomes invalid. In other words, Master B loses arbitration. Master B releases its SDA pin, so that it does not affect the data transfer initiated by another master. If two or more masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. SCL line Internal SDA output (Master A) Loses arbitration and sets the internal SDA output to "1." Internal SDA output (Master B) SDA line a b Fig. 16.7 Lost Arbitration Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-14 2010-04-01 TMP19A44 A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line. If there is a difference between these two values, the master loses arbitration and sets SBI0SR <AL> to "1." When <AL> is set to "1," SBISR <MST, TRX> are cleared to "0," causing the SBI to operate as a slave receiver. <AL> is cleared to "0" when data is written to or read from SBIDBR or data is written to SBICR2. Internal SCLoutput Master A Internal SDA output 1 D7A 2 3 4 5 6 7 8 D6A D5A D4A D3A D2A D1A D0A 2 3 4 9 1 2 3 4 D7A' D6A' D5A' D4A' Clock output stops here Internal SCL output Master B Internal SDA output 1 D7B D6B Internal SDA output is held high because Master B has lost arbitraiton. <AL> <MST> <TRX> Access to SBIDBR or SBICR2 Fig. 16.8 Example of Master B Losing Arbitration (D7A = D7B, D6A = D6B) 16.5.11 Slave Address Match Detection Monitor When the SBI operates as a slave device in the address recognition mode (I2CCR <ALS> = "0"), SBISR <AAS> is set to "1" on receiving the general-call address or the slave address that matches the value specified at I2CCR. When <ALS> is "1," <AAS> is set to "1" when the first data word has been received. <AAS> is cleared to "0" when data is written to or read from SBIDBR. 16.5.12 General-call Detection Monitor When the SBI operates as a slave device, SBISR <AD0> is set to "1" when it receives the general-call address; i.e., the eight bits following the start condition are all zeros. <AD0> is cleared to "0" when the start or stop condition is detected on the bus. 16.5.13 Last Received Bit Monitor SBISR <LRB> is set to the SDA line value that was read at the rising of the SCL line. In the acknowledgment mode, reading SBISR <LRB> immediately after generation of the INTS0 interrupt request causes ACK signal to be read. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-15 2010-04-01 TMP19A44 16.5.14 Software Reset If the serial bus interface circuit locks up due to external noise, it can be initialized by using a software reset. Writing "10" followed by "01" to SBICR2 <SWRST1:0> generates a reset signal that initializes the serial bus interface circuit. After a reset, all control registers and status flags are initialized to their reset values. When the serial bus interface is initialized, <SWRST> is automatically cleared to "0." (Note) A software reset causes the SBI operating mode to switch from the I2C mode to the port mode. 16.5.15 Serial Bus Interface Data Buffer Register (SBIDBR) Reading or writing SBIDBR initiates reading received data or writing transmitted data. When the SBI is acting as a master, setting a slave address and a direction bit to this register generates the start condition. 16.5.16 I2C Bus Address Register (I2CAR) When the SBI is configured as a slave device, the I2CAR<SA6:0> bit is used to specify a slave address. If I2C0AR <ALS> is set to "0," the SBI recognizes a slave address transmitted by the master device and receives data in the addressing format. If <ALS> is set to "1," the SBI does not recognize a slave address and receives data in the free data format. 16.5.17 IDLE Setting Register (SBIBR0) The SBIBR0<I2SBI> register determines if the SBI operates or not when it enters the IDLE mode. This register must be programmed before executing an instruction to switch to the standby mode. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-16 2010-04-01 TMP19A44 Data Transfer Procedure in the I2C Bus Mode 16.6 16.6.1 Device Initialization First, program SBICR1<ACK, SCK2:0> by writing "0" to bits 7 to 5 and bit 3 in SBICR1. Next, program I2CAR by specifying a slave address at <SA6:0> and an address recognition mode at <ALS>. (<ALS> must be set to"0" when using the addressing format.) Next, program SBICR2 to initially configure the SBI in the slave receiver mode by writing "0" to <MST, TRX, BB> , "1" to <PIN> , "10" to <SBIM1:0> and "0" to bits 1 and 0. 7 6 5 SBICR1 0 0 0 I2CAR X X X SBICR2 0 0 0 (Note) X: Don't care 16.6.2 c 4 X X 1 3 0 X 1 2 X X 0 1 X X 0 0 X X 0 Specifies ACK and SCL clock. Specifies a slave address and an address recognition mode. Configures the SBI as a slave receiver. Generating the Start Condition and a Slave Address Master mode In the master mode, the following steps are required to generate the start condition and a slave address. First, ensure that the bus is free (<BB> = "0"). Then, write "1" to SBICR1 <ACK> to select the acknowledgment mode. Write to SBIDBR a slave address and a direction bit to be transmitted. When <BB> = "0," writing "1111" to SBICR2 <MST, TRX, BB, PIN> generates the start condition on the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The SBI outputs the slave address and the direction bit specified at SBIDBR with the first eight clocks, and releases the SDA line in the ninth clock to receive an acknowledgment signal from the slave device. The INTS0 interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to "0." In the master mode, the SBI holds the SCL line at the "L" level while <PIN> is "0." <TRX> changes its value according to the transmitted direction bit at generation of the INTS0 interrupt request, provided that an acknowledgment signal has been returned from the slave device. Settings in main routine Reg. Reg. if Reg. Then SBICR1 SBIDR1 SBICR2 7 6 5 4 3 2 1 0 SBISR Reg. e 0x20 0x00 Ensures that the bus is free. X X X 1 0 X X X X X X X X X X X 1 1 1 1 1 0 0 0 Selects the acknowledgement mode. Specifies the desired slave address and direction. Generates the start condition. Example of INTS0 interrupt routine INTCLR 0xbc Processing End of interrupt Serial Bus Interface (SBI) Clears the interrupt request. TMP19A44 (rev1.3) 16-17 2010-04-01 TMP19A44 d Slave mode In the slave mode, the SBI receives the start condition and a slave address. After receiving the start condition from the master device, the SBI receives a slave address and a direction bit from the master device during the first eight clocks on the SCL line. If the received address matches its slave address specified at I2CAR or is equal to the general-call address, the SBI pulls the SDA line to the "L" level during the ninth clock and outputs an acknowledgment signal. The INTS0 interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to "0." In the slave mode, the SBI holds the SCL line at the "L" level while <PIN> is "0." (Note) The user can only use a DMA transfer: * when there is only one master and only one slave and * continuous transmission or reception is possible. SCL 1 2 3 4 5 6 7 8 SDA A6 A5 A4 A3 A2 A1 A0 R/ W 9 ACK Acknowledgement from slave Start condition Slave address + Direction bit <PIN> INTS0 interrupt request Master to slave Slave to master Fig. 16.9 Generation of the Start Condition and a Slave Address 16.6.3 Transferring a Data Word At the end of a data word transfer, the INTS0 interrupt is generated to test <MST> to determine whether the SBI is in the master or slave mode. c Master mode (<MST> = "1") Test <TRX> to determine whether the SBI is configured as a transmitter or a receiver. Transmitter mode (<TRX> = "1") Test <LRB>. If <LRB> is "1," that means the receiver requires no further data. The master then generates the stop condition as described later to stop transmission. If <LRB> is "0," that means the receiver requires further data. If the next data to be transmitted has eight bits, the data is written into SBIDBR. If the data has different length, <BC2:0> and <ACK> are programmed and the transmit data is written into SBIDBR. Writing the data makes <PIN> to"1," causing the SCL pin to generate a serial clock for transfer of a next data word, and the SDA pin to transfer the data word. After the transfer is completed, the INTS0 interrupt request is generated, <PIN> is set to "0," and the SCL pin is pulled to the "L" level. To transmit more data words, test <LRB> again and repeat the above procedure. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-18 2010-04-01 TMP19A44 INTS0 interrupt if MST = 0 Then go to the slave-mode processing if TRX = 0 Then go to the receiver-mode processing if LRB = 0 Then go to processing for generating the stop condition X X X X 0 X X X SBICR1 Specifies the number of bits to be transmitted and specify whether ACK is required. Writes the transmit data. SBIDBR X X X X X X X X End of interrupt processing (Note) X: Don't care 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 SCL pin 9 Write to SBI0DBR SDA pin ACK Acknowledgment signal from receiver <PIN> INTS0 interrupt request Master to slave Slave to master Fig. 16.10 <BC2:0> = "000" and <ACK> = "1" (Transmitter Mode) Receiver mode (<TRX> = "0") If the next data to be transmitted has eight bits, the transmit data is written into SBIDBR. If the data has different length, <BC2:0> and <ACK> are programmed and the received data is read from SBIDBR to release the SCL line. (The data read immediately after transmission of a slave address is undefined.) On reading the data, <PIN> is set to "1," and the serial clock is output to the SCL pin to transfer the next data word. In the last bit, when the acknowledgment signal becomes the "L" level, "0" is output to the SDA pin. After that, the INTS0 interrupt request is generated, and <PIN> is cleared to "0," pulling the SCL pin to the "L" level. Each time the received data is read from SBIDBR, one-word transfer clock and an acknowledgement signal are output. Read the received data SCL 1 2 3 4 5 6 7 8 SDA D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Next D7 Acknowledgment signal to transmitter <PIN> INTS interrupt request Master to slave Slave to master Fig. 16.11<BC2:0> = "000" and <ACK> = "1" (Receiver Mode) Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-19 2010-04-01 TMP19A44 To terminate the data transmission from the transmitter, <ACK> must be set to "0" immediately before reading the second to last data word. This disables generation of an acknowledgment clock for the last data word. When the transfer is completed, an interrupt request is generated. After the interrupt processing, <BC2:0> must be set to "001" and the data must be read so that a clock is generated for 1-bit transfer. At this time, the master receiver holds the SDA bus line at the "H" level, which signals the end of transfer to the transmitter as an acknowledgment signal. In the interrupt processing for terminating the reception of 1-bit data, the stop condition is generated to terminate the data transfer. 9 SCL SDA 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 1 Acknowledgment signal to transmitter <PIN> INTS0 interrupt request Read out the received data after clearing <ACK> to "0." Read out the received data after setting <BC2:0> to "001." Master to slave Slave to master Fig. 16.12 Terminating Data Transmission in the Master Receiver Mode Example: When receiving N data words INTS0 interrupt (after data transmission) SBICR1 7 6 5 4 3 2 1 0 X X X X 0 X X X Reg. SBI0CBR End of interrupt Sets the number of bits of data to be received and specify whether ACK is required. Reads dummy data. INTS0 interrupt (first to (N-2)th data reception) 7 6 5 4 3 2 1 0 Reg. SBIDBR End of interrupt Reads the first to (N-2)th data words. INTS0 interrupt ( (N-1)th data reception) 7 6 5 4 3 2 1 0 SBI0CR1 X X X 0 0 X X X Reg. SBIDBR End of interrupt Disables generation of acknowledgement clock. Reads the (N-1)th data word. INTS0 interrupt (Nth data reception) 7 6 5 4 3 2 1 0 SBI0CR1 0 0 1 0 0 X X X Reg. SBIDBR End of interrupt Generates a clock for 1-bit transfer. Reads the Nth data word. INTS0 interrupt (after completing data reception) Processing to generate the stop condition End of interrupt Terminates the data transmission. (Note) X: Don't care Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-20 2010-04-01 TMP19A44 d Slave mode (<MST> = "0") In the slave mode, the SBI generates the INTS0 interrupt request on four occasions: 1) when the SBI has received any slave address from the master, 2) when the SBI has received a general-call address, 3) when the received slave address matches its own address, and 4) when a data transfer has been completed in response to a general-call. Also, if the SBI loses arbitration in the master mode, it switches to the slave mode. Upon the completion of data word transfer in which arbitration is lost, the INTS0 interrupt request is generated, <PIN> is cleared to "0," and the SCL pin is pulled to the "L" level. When data is written to or read from SBIDBR or when <PIN> is set to "1," the SCL pin is released after a period of tLOW. In the slave mode, the normal slave mode processing or the processing as a result of lost arbitration is carried out. SBISR <AL>, <TRX>, <AAS> and <AD0> are tested to determine the processing required. Table 16.2 shows the slave mode states and required processing. Example: When the received slave address matches the SBI's own address and the direction bit is "1" in the slave receiver mode INTS0 interrupt if TRX = 0 Then go to other processing if AL = 1 Then go to other processing if AAS = 0 Then go to other processing SBICR1 X X X 1 0 X X X SBIDBR X X X X 0 X X X Sets the number of bits to be transmitted. Sets the transmit data. (Note) X: Don't care Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-21 2010-04-01 TMP19A44 Table 16.2 Processing in Slave Mode <TRX> <AL> <AAS> <AD0> State Processing 1 1 1 0 Set the number of bits in a data word to <BC2:0> and write the transmit data into SBIDBR. 0 1 0 0 0 Arbitration was lost while the slave address was being transmitted, and the SBI received a slave address with the direction bit "1" transmitted by another master. In the slave receiver mode, the SBI received a slave address with the direction bit "1" transmitted by the master. In the slave transmitter mode, the SBI has completed a transmission of one data word. 1 1/0 0 0 1 1/0 0 1/0 0 1 0 Serial Bus Interface (SBI) Arbitration was lost while a slave address was being transmitted, and the SBI received either a slave address with the direction bit "0" or a general-call address transmitted by another master. Arbitration was lost while a slave address or a data word was being transmitted, and the transfer terminated. In the slave receiver mode, the SBI received either a slave address with the direction bit "0" or a general-call address transmitted by the master. In the slave receiver mode, the SBI has completed a reception of a data word. TMP19A44 (rev1.3) 16-22 Test LRB. If it has been set to "1," that means the receiver does not require further data. Set <PIN> to 1 and reset <TRX> to 0 to release the bus. If <LRB> has been reset to "0," that means the receiver requires further data. Set the number of bits in the data word to <BC2:0> and write the transmit data to the SBIDBR. Read the SBIDBR (a dummy read) to set <PIN> to 1, or write "1" to <PIN>. Set the number of bits in the data word to <BC2:0> and read the received data from SBIDBR. 2010-04-01 TMP19A44 16.6.4 Generating the Stop Condition When SBISR <BB> is "1," writing "1" to SBICR2 <MST, TRX, PIN> and "0" to <BB> causes the SBI to start a sequence for generating the stop condition on the bus. Do not alter the contents of <MST, TRX, BB, PIN> until the stop condition appears on the bus. If another device is holding down the SCL bus line, the SBI waits until the SCL line is released. After that, the SDA pin goes high, causing the stop condition to be generated. SBICR2 7 6 5 4 3 2 1 0 1 1 0 1 1 0 0 0 "1" <MST> "1" <TRX> "0" <BB> "1" <PIN> Generates the stop condition. Stop condition SCL pin SDA pin <PIN> <BB> (read) Fig. 16.13 Generating the Stop Condition Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-23 2010-04-01 TMP19A44 16.6.5 Repeated Start Procedure Repeated start is used when a master device changes the data transfer direction without terminating the transfer to a slave device. The procedure of generating a repeated start in the master mode is described below. First, set SBICR2 <MST, TRX, BB> to "0" and write "1" to <PIN> to release the bus. At this time, the SDA pin is held at the "H" level and the SCL pin is released. Because no stop condition is generated on the bus, other devices think that the bus is busy. Then, test SBISR <BB> and wait until it becomes "0" to ensure that the SCL pin is released. Next, test <LRB> and wait until it becomes "1" to ensure that no other device is pulling the SCL bus line to the "L" level. Once the bus is determined to be free this way, use the steps described above in (16.6.2 Generating the Start Condition and a Slave Address) to generate the start condition. To satisfy the setup time of repeated start, at least 4.7-s wait period (in the standard mode) must be created by the software after the bus is determined to be free. 7 6 5 4 3 2 1 0 SBICR2 0 0 0 1 1 0 0 0 if SBISR<BB> 0 Then if SBISR<LRB> 1 Then 4.7 s Wait SBICR1 X X X 1 0 X X X SBIDBR X X X X X X X X SBICR2 1 1 1 1 1 0 0 0 Releases the bus. Checks that the SCL pin is released. Checks that no other device is pulling the SCL pin to the "L" level. Selects the acknowledgment mode. Sets the desired slave address and direction. Generates the start condition. (Note) X: Don't care "0" <MST> "0" <TRX> "0" <BB> "1" <PIN> "1" <MST> "1" <TRX> "1" <BB> "1" <PIN> 4.7 s (min.) Start condition SCL (bus) SCL pin 9 SDA pin <LRB> <BB> <PIN> (Note) Do not write <MST> to "0" when it is "0." (Repeated start cannot be done.) Fig. 16.14 Timing Chart of Generating a Repeated Start Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-24 2010-04-01 TMP19A44 16.7 Control in the Clock-synchronous 8-bit SIO Mode The following registers control the serial bus interface in the clock-synchronous 8-bit SIO mode and provide its status information for monitoring. Serial bus interface control register 0 SBICR0 (0xFF00_4B00) 7 SBIEN R/W 0 bit Symbol Read/Write After reset SBI Function 6 5 4 3 2 1 0 R 0 This can be read as "0". operation 0: Disable 1: Enable 15 14 13 bit Symbol Read/Write After reset Function This can be read as "0". 23 22 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 bit Symbol Read/Write After reset <SBIEN>: 12 11 10 9 8 R 0 21 20 19 18 17 16 27 26 25 24 R 0 29 28 R 0 To use the SBI, enable the SBI operation ("1") before setting each register of SBI module. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-25 2010-04-01 TMP19A44 Serial bus interface control register 1 bit Symbol SBICR1 (0xFF00_4B04) Read/Write After reset Function 7 6 5 4 SIOS SIOINH SIOM1 SIOM0 0 0 0 0 W Start transfer Abort transfer 0: Stop 0: Continue 1: Start 1: Abort Select transfer mode 00: Transmit mode 01: (Reserved) 10: Transmit/receive mode 11: Receive mode 15 13 14 bit Symbol Read/Write After reset Function This can be read as "0". 23 22 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 bit Symbol Read/Write After reset 12 3 2 1 0 SCK2 SCK1 SCK0 R/W 1 R 1 This can be read as "1." W Select serial clock frequency 11 10 0 0 9 8 R 0 21 20 19 18 17 16 27 26 25 24 R 0 29 28 R 0 On writing <SCK2:0>: Select serial clock frequency 000 n = 3 2.5 MHz 001 n = 4 1.25 kHz System clock : fsys 010 n = 5 625 kHz (=80 MHz) kHz 011 n = 6 313 Clock gear : fc/1 kHz 100 n = 7 156 fsys/4 Frequency = [ Hz ] n 78 kHz 101 n = 8 2 kHz 40 110 n = 9 111 External clock (Note) Set <SIOS> to "0" and <SIOINH> to "1" before programming the transfer mode and the serial clock. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-26 2010-04-01 TMP19A44 Serial bus interface data buffer register SBIDBR (0xFFFF_F251) 7 DB7 bit Symbol Read/Writ e After reset 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (Receive)/W (Transmit) Undefined 15 14 13 bit Symbol Read/Writ e After reset Function This can be read as "0". 23 22 bit Symbol Read/Writ e After reset Function This can be read as "0". 31 30 bit Symbol Read/Writ e After reset 12 11 10 9 8 R 0 21 20 19 18 17 16 27 26 25 24 2 SBIM0 1 0 R 0 29 28 R 0 Fig. 16.8 SIO Mode Registers Serial bus interface control register 2 7 bit Symbol SBICR2 (0xFFFF_F253) Read/Write After reset Function 6 5 4 3 SBIM1 R 1 W 0 Select serial bus interface operating mode 00: Port mode 01: Clock-synchronous 8-bit SIO mode 10: I2C bus mode 11: (Reserved) This can be read as "1". 15 14 bit Symbol Read/Write After reset Function This can be read as "0". 23 22 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 bit Symbol Read/Write After reset Serial Bus Interface (SBI) 13 12 R 1 0 This can be read as "1". 11 10 9 8 19 18 17 16 27 26 25 24 R 0 21 20 R 0 29 28 R 0 TMP19A44 (rev1.3) 16-27 2010-04-01 TMP19A44 Serial bus interface register 7 bit Symbol SBISR (0xFFFF_F253) Read/Write After reset Function 6 5 4 3 SIOF R 1 Serial transfer status monitor 0: Terminated 1: In progress 15 14 1 R 0 This can be read as "1". 13 bit Symbol Read/Write After reset Function This can be read as "0". 23 22 bit Symbol Read/Write After reset Function This can be read as "0". 31 30 bit Symbol Read/Write After reset 2 SEF 12 11 0 R 1 0 Shift This can be read as "1". operation status monitor 0: Terminated 1: In progress 10 9 8 R 0 21 20 19 18 17 16 27 26 25 24 2 1 0 R 0 29 28 R 0 Serial bus interface baud rate register 0 7 bit Symbol SBIBR0 (0xFFFF_F254) Read/Write After reset Function R 1 6 I2SBI R/W 0 This can be IDLE read as "1." 5 4 3 R 1 W 0 Make sure that you write "0." This can be read as "1." 0: Stop 1: Operate 15 14 13 bit Symbol Read/Write After reset Function This can be read as "0." 23 22 bit Symbol Read/Write After reset Function This can be read as "0." 31 30 bit Symbol Read/Write After reset Serial Bus Interface (SBI) 12 11 10 9 8 R 0 21 20 19 18 17 16 27 26 25 24 R 0 29 28 R 0 TMP19A44 (rev1.3) 16-28 2010-04-01 TMP19A44 16.7.1 c Serial Clock Clock source Internal or external clocks can be selected by programming SBICR1 <SCK2:0>. Internal clocks In the internal clock mode, one of the seven frequencies can be selected as a serial clock, which is output to the outside through the SCK pin. At the beginning of a transfer, the SCK pin output becomes the "H" level. If the program cannot keep up with this serial clock rate in writing the transmit data or reading the received data, the SBI automatically enters a wait period. During this period, the serial clock is stopped automatically and the next shift operation is suspended until the processing is completed. Automatic wait SCK pin output SO pin output Write the transmit data 1 2 3 7 8 1 a0 a1 a2 a5 a6 a7 b0 a b 2 b1 b4 6 7 8 1 2 3 b5 b6 b7 c0 c1 c2 c Fig. 16.15 Automatic Wait External clock (<SCK2:0> = "111") The SBI uses an external clock supplied from the outside to the SCK pin as a serial clock. For proper shift operations, the serial clock at the "H" and "L" levels must have the pulse widths as shown below. SCK pin tSCKL tSCKH tSCKL, tSCKH > 8/fsys Fig. 16.16 9 Maximum Transfer Frequency of External Clock Input Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-29 2010-04-01 TMP19A44 d Shift Edge Leading-edge shift is used in transmission. Trailing-edge shift is used in reception. Leading-edge shift Data is shifted at the leading edge of the serial clock (or the falling edge of the SCK pin input/output). Trailing-edge shift Data is shifted at the trailing edge of the serial clock (or the rising edge of the SCK pin input/output). SCK pin SO pin Shift register bit 0 bit 1 bit 2 76543210 *7654321 **765432 bit 3 bit 4 bit 5 bit 6 bit 7 ***76543 ****7654 *****765 ******76 ******7 bit 4 bit 5 bit 6 bit 7 (a) Leading-edge shift SCK pin SI pin Shift register bit 0 ******** bit 1 0******* bit 2 10****** bit 3 210***** 3210**** 43210*** (b) Trailing-edge shift 543210** 6543210* 76543210 (Note) *: Don't care Fig. 16.17 Shift Edge Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-30 2010-04-01 TMP19A44 16.7.2 Transfer Modes The transmit mode, the receive mode or the transmit/receive mode can be selected by programming SBICR1 <SIOM1:0>. c 8-bit transmit mode Set the control register to the transmit mode and write the transmit data to SBIDBR. After writing the transmit data, writing "1" to SBICR1 <SIOS> starts the transmission. The transmit data is moved from SBIDBR to a shift register and output to the SO pin, with the leastsignificant bit (LSB) first, in synchronization with the serial clock. Once the transmit data is transferred to the shift register, SBIDBR becomes empty, and the INTS0 (buffer-empty) interrupt is generated, requesting the next transmit data. In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if next data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared when SBIDBR is loaded with the next transmit data. In the external clock mode, SBIDBR must be loaded with data before the next data shift operation is started. Therefore, the data transfer rate varies depending on the maximum latency between when the interrupt request is generated and when SBIDBR is loaded with data in the interrupt service program. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting SBISR <SIOF> to "1" to the falling edge of SCK. Transmission can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the INTS0 interrupt service program. If <SIOS> is cleared, remaining data is output before transmission ends. The program checks SBI0SR <SIOF> to determine whether transmission has come to an end. <SIOF> is cleared to "0" at the end of transmission. If <SIOINH> is set to "1," the transmission is aborted immediately and <SIOF> is cleared to "0." In the external clock mode, <SIOS> must be set to "0" before the next transmit data shift operation is started. Otherwise, operation will stop after dummy data is transmitted. SBICR1 7 6 5 4 3 2 1 0 0 1 0 0 0 X X X Selects the transmit mode. SBIDBR SBICR1 X X X X X X X X 1 0 0 0 0 X X X Writes the transmit data. Starts transmission. INTS0 interrupt SBIDBR Serial Bus Interface (SBI) X X X X X X X X Writes the transmit data. TMP19A44 (rev1.3) 16-31 2010-04-01 TMP19A44 <SIOS> is cleared <SIOS> <SIOF> <SEF> SCK pin (output) a0 * SO pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTS0 interrupt request b a SBIDBR (a) Internal clock Write the transmit data <SIOS> is cleared <SIOS> <SIOF> <SEF> SCK pin (input) a0 * SO pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTS0 interrupt request a SBIDBR b (b) External clock Write the transmit data Fig. 16.18 Transmit Mode Example: Example of programming (MIPS16) to terminate transmission by <SIO> (external clock) ADDIU STEST1 STEST2 : : Serial Bus Interface (SBI) r3, r0, 0x04 LB r2, (SBISR) AND r2, r3 BNEZ r2, STEST1 ADDIU r3, r0, ; If SBISR<SEF> = 1 then loop 0x40 ; If SCK = 0 then loop LB r2, (PC) AND r2, r3 BEQZ r2, STEST2 ADDIU r3, r0, SB r3, (SBICR1) 0y00000111 ; <SIOS> 0 TMP19A44 (rev1.3) 16-32 2010-04-01 TMP19A44 SCK pin SIOF SO pin bit 6 bit 7 tSODH = Min. 4/fsys/2 [s] Fig. 16.19 Transmit Data Retention Time at the End of Transmission d 8-bit receive mode Set the control register to the receive mode. Then writing "1" to SBICR1 <SIOS> enables reception. Data is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the shift register is loaded with the 8-bit data, it transfers the received data to SBIDBR and the INTS0 (buffer-full) interrupt request is generated to request reading the received data. The interrupt service program then reads the received data from SBIDBR. In the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the received data is read from SBIDBR. In the external clock mode, shift operations are executed in synchronization with the external clock. The maximum data transfer rate varies, depending on the maximum latency between generating the interrupt request and reading the received data. Reception can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the INTS0 interrupt service program. If <SIOS> is cleared, reception continues until all the bits of received data are written to SBIDBR. The program checks SBISR <SIOF> to determine whether reception has come to an end. <SIOF> is cleared to "0" at the end of reception. After confirming the completion of the reception, last received data is read. If <SIOINH> is set to "1," the reception is aborted immediately and <SIOF> is cleared to "0." (The received data becomes invalid, and there is no need to read it out.) (Note) The contents of SBIDBR will not be retained after the transfer mode is changed. The ongoing reception must be completed by clearing <SIOS> to "0" and the last received data must be read before the transfer mode is changed. SBICR1 7 6 5 4 3 2 1 0 0 1 1 1 0 X X X Selects the receive mode. SBICR1 1 0 1 1 0 0 0 0 Starts reception. SBIDBR Reads the received data. INTS0 interrupt Reg. Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-33 2010-04-01 TMP19A44 <SIOS> is cleared <SIOS> <SIOF> <SEF> SCK pin (output) a0 SI pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTS0 interrupt request a SBIDBR Read the received data b Read the received data Fig. 16.20 Receive Mode (Example: Internal Clock) e 8-bit transmit/receive mode Set the control register to the transfer/receive mode. Then writing the transmit data to SBIDBR and setting SBICR1 <SIOS> to "1" enables transmission and reception. The transmit data is output through the SO pin at the falling of the serial clock, and the received data is taken in through the SI pin at the rising of the serial clock, with the least-significant bit (LSB) first. Once the shift register is loaded with the 8-bit data, it transfers the received data to SBIDBR and the INTS0 interrupt request is generated. The interrupt service program reads the received data from the data buffer register and writes the next transmit data. Because SBIDBR is shared between transmit and receive operations, the received data must be read before the next transmit data is written. In the internal clock operation, the serial clock will be automatically in the wait state until the received data is read and the next transmit data is written. In the external clock mode, shift operations are executed in synchronization with the external serial clock. Therefore, the received data must be read and the next transmit data must be written before the next shift operation is started. The maximum data transfer rate for the external clock operation varies depending on the maximum latency between generating the interrupt request and reading the received data and writing the transmit data. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting <SIOF> to "1" to the falling edge of SCK. Transmission and reception can be terminated by clearing <SIOS> to "0" or setting SBICR1 <SIOINH> to "1" in the INTS0 interrupt service program. If <SIOS> is cleared, transmission and reception continue until the received data is fully transferred to SBIDBR. The program checks SBISR <SIOF> to determine whether transmission and reception have come to an end. <SIOF> is cleared to "0" at the end of transmission and reception. If <SIOINH> is set, the transmission and reception are aborted immediately and <SIOF> is cleared to "0." (Note) Serial Bus Interface (SBI) The contents of SBIDBR will not be retained after the transfer mode is changed. The ongoing transmission and reception must be completed by clearing <SIOS> to "0" and the last received data must be read before the transfer mode is changed. TMP19A44 (rev1.3) 16-34 2010-04-01 TMP19A44 <SIOS> is cleared <SIOS> <SIOF> <SEF> SCK pin (output) SO pin * a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 SI pin INTS0 interrupt request SBIDBR a c b Write the transmit data (a) Read the received data (c) Write the transmit data (b) d Read the received data (d) Fig. 16.21 Transmit/Receive Mode (Example: Internal Clock) SCK pin SIOF SO pin bit 6 bit 7 of the last word transmitted tSODH = Min. 4/fsys/2 [s] Fig. 16.22 Transmit Data Retention Time at the End of Transmission/Reception (In the Transmit/Receive Mode) SBICR1 7 6 5 4 3 2 1 0 0 1 1 0 0 X X X Selects the transmit mode. SBIDBR SBICR1 X X X X X X X X 1 0 1 0 0 X X X Writes the transmit data. Starts reception/transmission. SBIODBR X X X X X X X X Reads the received data. Writes the transmit data. INTS0 interrupt Reg. SBIDBR Serial Bus Interface (SBI) TMP19A44 (rev1.3) 16-35 2010-04-01 TMP19A44 17. Analog/Digital Converter A 10-bit, sequential-conversion analog/digital converter (A/D converter) is built into the TMP19A44. This A/D converter is equipped with 16 analog input channels, which are divided into three units (4 channels, 4 channels and 8 channels). Fig. 17.1 shows the block diagram of this A/D converter. These 16 analog input channels (pins ANA0 through AINA3, ANB0 through AINB3 and ANC0 through AINC8) are also used as input ports. (Note) If it is necessary to reduce a power current by operating the TMP19A44 in IDLE, SLEEP, SLOW, STOP or BACKUP mode and if either case shown below is applicable, you must first stop the A/D converter and then execute the instruction to put the TMP19A44 into standby mode: 1) 2) The TMP19A44 must be put into IDLE mode when ADMOD1<I2AD> is "0." The TMP19A44 must be put into SLEEP,SLOW,STOP,BACKUP SLEEP, BACKUP STOP mode. Internal data bus Internal data bus Internal data bus ADS ADAMOD1 ADAMOD3 ADAMOD2 ADAMOD0 ADAMOD4 ADAMOD5 HPADCE ADSCNAend busy End scan Channel select AD monitor function AD monitor function interrupt repeat control circuit interrupt Interval start AD start control Busy TB0/CTRG Normal A/D conversion control circuit High-priority AD conversion control Top-priority AD conversion completion interrupt Interrupt request INTAD ADTRGA(PD6) result register + ADAREG0~3 - ADAREG0~3 AINA0 (P70) Comparator AD conversion result register Comparison register AINA1(P71) AD conversion Sample hold Comparator AINA2(P72) Multiplexer AINA3(P73) ADREGSPA VREFH VREFL VREF D/A converter Fig. 17.1 Block Diagram of A/D Converter Unit A (the same applies to Unit B and C) Analog/Digital Converter TMP19A44(rev1.3) 17-1 2010-04-01 TMP19A44 17.1 Control Register 17.1.1 Unit A, Unit B The A/D converter is controlled by A/D mode control registers (ADnMOD0, ADnMOD1, ADnMOD2, ADnMOD3 and ADnMOD4: n=A, B). Results of A/D conversion are stored in A/D conversion result registers ADAREG0 through ADAREG3 and ADBREG0 through ADBREG3. Results of top-priority conversion are stored in ADAREGSP and ADBREGSP. Fig. 17.2 through Fig. 17.4 show the registers related to the A/D converter. A/D Mode Control Register 0 7 ADMOD0 bit Symbol (0x FF00_4D04) Read/Write EOCFNA 0 Normal A/D conversion completion flag 5 ADBFNA R After reset Function 6 4 3 2 1 0 ITMA1 ITMA0 REPEATA SCANA ADSA R 0 Normal A/D conversion BUSY flag 0: Conversion 0: Before or stop during 1: During conversion conversion 1: Completion 0 "0" is read. R/W 0 0 0 0 0 Specify interrupt in fixed channel repeat conversion mode Specify interrupt in fixed channel repeat conversion mode Specify repeat mode 0: Single conversion mode 1: Repeat conversion mode Specify scan mode 0: Fixed channel mode 1: Channel scan mode Start A/D conversion 0: Don't care 1: Start conversion "0" is always read. Specify A/D conversion interrupt in fixed channel repeat conversion mode Fixed channel repeat conversion mode <SCAN> = "0," <REPEAT> = "1" 00 Generate interrupt once every single conversion 01 Generate interrupt once every 4 conversions 10 Setting prohibited 11 Setting prohibited Fig. 17.2 Registers related to the A/D Converter Analog/Digital Converter TMP19A44(rev1.3) 17-2 2010-04-01 TMP19A44 A/D Mode Control Register 1 bit Symbol ADMOD1 (0xFF00_ 4D08) Read/Write 7 6 5 4 VREFONA I2ADA ADSCNA - 2 1 0 ADCHA3 ADCHA2 ADCHA1 ADCHA0 0 0 0 R/W After reset Function 3 0 0 VREF application control 0: OFF 1: ON IDLE 0: Stop 1: Activate 0 0 0 Write "0." Specify operation mode for channel scanning 0: 4ch scan 1: Setting prohibited Select analog input channel Select analog input channel <SCAN> 0 Fixed channel <ADCHA3.2, 1, 0> 1 Channel scan (ADSCN=0) 1 Channel scan (ADSCN=1) 0000 ANn0 AN0 ANn0 0001 ANn1 AN0 to AN1 ANn0 to ANn1 0010 ANn2 AN0 to AN2 ANn0 to ANn2 0011 ANn3 AN0 to AN3 ANn0 to ANn3 0100~1111 Setting prohibited (Note 1) Before starting AD conversion, write "1" to the <VREFON> bit, wait for 3 s during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0<ADS> bit. (Note 2) To go into standby mode upon completion of AD conversion, set <VREFON> to "0." Fig. 17.3 Registers related to the A/D Converter A/D Mode Control Register 2 ADMOD2 (0xFF00_ 4D0C) bit Symbol 7 6 5 4 3 2 1 0 EOCFHPA ADBFHPA HPADCEA - HPADC HPADCH HPADCH HPADCH HA3 A2 A1 A0 0 0 0 Read/Write R After reset Function R 0 0 Top-priority AD conversion completion flag 0: Before or during conversion 1: Upon completion Top-priority AD conversion BUSY flag 0: During conversion halts 1: During conversion <HPADCHA4,3.2, 1, 0> Analog/Digital Converter R/W 0 Activate top-priority conversion 0: Don't care 1: Start conversion. "0" is always read. 0 Write "0." 0 Select analog input channel when activating top-priority conversion Analog input channel when executing top-priority conversion 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100~1111 Setting prohibited TMP19A44(rev1.3) 17-3 2010-04-01 TMP19A44 bit Symbol ADMOD3 (0xFF00 _4D10) Read/Write 7 6 R/W R A/D Mode Control Register 3 5 4 3 ADOBICA After reset 0 0 "0" is read. Make AD monitor function interrupt setting 0: Smaller than comparison register 1: Larger than comparison register Function bit Symbol ADMOD5 (0xFF00 _4D18) Read/Write 7 6 R/W R 0 function interrupt setting 0: Smaller than comparison register 1: Larger than comparison register Function bit Symbol REGSA3 REGSA2 0 0 0001 ADAREG1 0010 ADAREG2 0011 ADAREG3 1XXX ADAREGSP A/D Mode Control Register 4 6 5 4 3 ADHSA HADHTGA 0 HW source for activating top-priority A/D conversion 0: External TRG 1: TB9RG0 0 0 0 AD monitor function 0: Disable 1: Enable 2 1 0 REGSA1 REGSA0 ADOBSVA 0 0 0 HW for activating top-priority A/D conversion 0: Disable 1: Enable 0 HW source for activating normal A/D conversion 0: External TRG 1: TB1RG0 2 ADHTGA 0 AD monitor function 0: Disable 1: Enable 0 HW for activating normal A/D conversion 0: Disable 1: Enable 1 0 ADRSTA1 ADRSTA0 R/W After reset ADOBSVA BIT for selecting the AD conversion result storage register that is to be compared with the comparison register if the AD monitor function is enabled ADAREG0 Read/Write Function 0 0000 HADHSA REGSA0 AD conversion result storage register to be compared <REGSA2, 1, 0> ADAMOD4 (0xFF00_4D14) 0 0 "0" is read. Make AD monitor 7 REGSA1 R/W 0 Write "0." 0 BIT for selecting the AD conversion result storage register that is to be compared with the comparison register if the AD monitor function is enabled A/D Mode Control Register 5 5 4 3 ADOBICA After reset REGSA2 1 R/W 0 Write "0." REGSA3 2 R W W 0 - - "0" is read. Overwriting 10 with 01 allows ADC to be software reset. (Note 1) If AD conversion is executed with the match triggers <ADHTG> and <HADHTG> of a 16-bit timer set to "1" by using a source for triggering H/W, A/D conversion can be activated at specified intervals by performing three steps shown below when the timer is idle: c Select a source for triggering HW: <ADHS>, <HADHS> d Enable H/W activation of AD conversion: <ADHTG>, <HADHTG> e Start the timer. (Note 2) Do not make a top-priority AD conversion setting and a normal AD conversion setting simultaneously. (Note 3) The external trigger cannot be used for H/W activation of AD conversion when it is used for H/W activation of top priority AD conversion. Fig. 17.4 Registers related to the A/D Converter Analog/Digital Converter TMP19A44(rev1.3) 17-4 2010-04-01 TMP19A44 17.1.2 Unit C The A/D converter is controlled by A/D mode control registers (ADCMODC0, ADCMODC1, ADCMODC2, ADCMODC3 and ADCMODC4). Results of A/D conversion are stored in A/D conversion result registers ADCREG0 through ADCREG7. Results of top-priority conversion are stored in ADnREGSP. A/D Mode Control Register 0 ADCMOD0 (0x FF00_4E04) bit Symbol 7 6 EOCFN ADBFN Read/Write R After reset 0 Normal A/D conversion completion flag Function 5 4 3 2 1 0 ITM1 ITM0 REPEAT SCAN ADS R 0 Normal A/D conversion BUSY flag 0: Conversion 0: Before or stop during 1: During conversion conversion 1: Completion 0 "0" is read. R/W 0 0 0 0 0 Specify interrupt in fixed channel repeat conversion mode Specify interrupt in fixed channel repeat conversion mode Specify repeat mode 0: Single conversion mode 1: Repeat conversion mode Specify scan mode 0: Fixed channel mode 1: Channel scan mode Start A/D conversion 0: Don't care 1: Start conversion "0" is always read. Specify A/D conversion interrupt in fixed channel repeat conversion mode Fixed channel repeat conversion mode <SCAN> = "0," <REPEAT> = "1" 00 Generate interrupt once every single conversion 01 Generate interrupt once every 4 conversions 10 Generate interrupt once every 8 conversions 11 Setting prohibited Analog/Digital Converter TMP19A44(rev1.3) 17-5 2010-04-01 TMP19A44 A/D Mode Control Register 1 bit Symbol ADCMOD1 (0xFF00_ 4E08) Read/Write 7 6 5 4 VREFON I2AD ADSCN - 2 1 0 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 R/W After reset Function 3 0 0 VREF application control 0: OFF 1: ON IDLE 0: Stop 1: Activate <ADCH3.2, 1, 0> 0 Specify operation mode for channel scanning 0: 4ch scan 1: Setting prohibited 0 0 Write "0." Select analog input channel Select analog input channel <SCAN> 0 Fixed channel 1 Channel scan (ADSCN=0) 1 Channel scan (ADSCN=1) 0000 AINC0 AIN0 AINC0 0001 AINC1 AIN 0 to AIN 1 AINC 0 to AINC 1 0010 AINC2 AIN 0 to AIN 2 AINC 0 to AINC 2 0011 AINC3 AIN 0 to AIN 3 AINC 0 to AINC 3 0100 AINC4 AINC4 AINC 0 to AINC 4 0101 AINC5 AINC4 to AINC5 AINC 0 to AINC 5 0110 AINC6 AINC4 to AINC6 AINC 0 to AINC 6 0111 AINC7 AINC4 to AINC7 AINC 0 to AINC 3 1000~1111 Setting prohibited (Note 1) Before starting AD conversion, write "1" to the <VREFON> bit, wait for 3 s during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0<ADS> bit. (Note 2) To go into standby mode upon completion of AD conversion, set <VREFON> to "0." Analog/Digital Converter TMP19A44(rev1.3) 17-6 2010-04-01 TMP19A44 A/D Mode Control Register 2 ADCMOD2 (0xFF00_ 4E0C) 7 6 5 4 3 bit Symbol EOCFHP ADBFHP HPADCE - HPADCH3 Read/Write R R After reset Function 0 Top-priority AD conversion completion flag 0: Before or during conversion 1: Upon completion 0 0 Activate top-priority conversion 0: Don't care 1: Start conversion. "0" is always read. AIN0 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000~1111 Setting prohibited R 0 0 W rite " 0." 0 HPADCH1 HPADCH0 0 0 0 ADOBIC REGS3 REGS2 0 0 0 2 1 0 REGS1 REGS0 ADOBSV 0 0 R/W "0" is read. Make AD monitor function interrupt setting 0: Sm aller than comparison register Function HPADCH2 Select analog input channel when activating top-priority conversion A/D Mode Control Register 3 6 5 4 3 R/W After reset 0 Analog input channel when executing top-priority conversion 0001 7 ADCMOD3 (0xFF00 _4E40) Read/Write 0 Write "0." 0000 bit Symbol 1 R/W Top-priority AD conversion BUSY flag 0: During conversion halts 1: During conversion <HPADCH4,3.2, 1, 0> 2 BIT for selecting the AD conversion result storage register that is to be compared with the comparison register if the AD m onitor function is enabled 0 AD monitor function 0: D isable 1: Enabl e 1: Larger than comparison register 7 6 R/W R bit Symbol ADCMOD5 (0xFF00 _4E48) Read/Write After reset 0 W rite " 0." Function 0 5 4 3 ADOBIC REGS3 REGS2 2 1 0 REGS1 REGS0 ADOBSV 0 0 R/W 0 "0" is read. Make AD monitor function interrupt setting 0: Sm aller than comparison register 1: Larger than comparison register 0 0 BIT for selecting the AD conversion result storage register that is to be compared with the comparison register if the AD m onitor function is enabled 0 AD monitor function 0: D isable 1: Enabl e Fig. 17.5 Registers related to the A/D Converter Analog/Digital Converter TMP19A44(rev1.3) 17-7 2010-04-01 TMP19A44 A/D Mode Control Register 3 AD conversion result storage register to be compared <REGS2, 1, 0> 0000 ADCREG0 0001 ADCREG1 0010 ADCREG2 0011 ADCREG3 0100 ADCREG4 0101 ADCREG5 0110 ADCREG6 0111 ADCREG7 1XXX ADAREGSP A/D Mode Control Register 4 ADCMOD4 (0xFF00_4E44) bit Symbol 7 6 HADHS HADHTG Read/Write 4 ADHS ADHTG 3 R/W After reset Function 5 0 HW source for activating top-priority A/D conversion 0: External TRG 1: TB9RG0 0 HW for activating top-priority A/D conversion 0: Disable 1: Enable 2 R 0 HW source for activating normal A/D conversion 0: External TRG 1: TB1RG0 0 HW for activating normal A/D conversion 0: Disable 1: Enable 0 "0" is read. 1 0 ADRST1 ADRST0 W W - - Overwriting 10 with 01 allows ADC to be software reset. Overwriting 10 with 01 allows ADC registers excluding the ADCLK<ADCLK2:0>bit to be reset by software. (Note 1) If AD conversion is executed with the match triggers <ADHTG> and <HADHTG> of a 16-bit timer set to "1" by using a source for triggering H/W, A/D conversion can be activated at specified intervals by performing three steps shown below when the timer is idle: c Select a source for triggering HW: <ADHS>, <HADHS> d Enable H/W activation of AD conversion: <ADHTG>, <HADHTG> e Start the timer. (Note 2) Do not make a top-priority AD conversion setting and a normal AD conversion setting simultaneously. (Note 3) The external trigger cannot be used for H/W activation of AD conversion when it is used for H/W activation of top priority AD conversion. Analog/Digital Converter TMP19A44(rev1.3) 17-8 2010-04-01 TMP19A44 A/D Conversion Result Register 0 (Unit A, B and C) ADAREG0 (0xFF00_4D34) bit Symbol 7 6 ADR01 ADR00 5 4 3 2 1 0 OVR0 ADR0RF Read/Write R R R R After reset 0 0 0 0 Function Store lower 2 bits of "0" is read. Over RUN A/D flag 0: Not conversion generate result storage 1: Generate flag A/D conversion result 1: Presence of conversion result bit Symbol 15 14 13 12 11 10 9 8 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 Read/Write R After reset 0 Function Store upper 8 bits of A/D conversion result 23 22 21 20 19 18 17 16 27 26 25 24 1 0 OVR1 ADR1RF bit Symbol Read/Write R After reset 0 31 30 29 28 bit Symbol Read/Write R After reset 0 A/D Conversion Result Register 1 (Unit A, B and C) ADAREG1 (0xFF00_4D38) bit Symbol 7 6 ADR11 ADR10 5 4 3 2 Read/Write R R R R After reset 0 0 0 0 Function Store lower 2 bits of "0" is read. Over RUNflag 1: Presence 0: Not generate of A/D conversion result 1: Generate conversion result bit Symbol 15 14 13 12 11 10 9 8 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read/Write R After reset 0 Function Store upper 8 bits of A/D conversion result 23 22 21 20 19 18 17 16 27 26 25 24 bit Symbol Read/Write R After reset 0 31 30 29 28 bit Symbol Read/Write R After reset 0 Analog/Digital Converter TMP19A44(rev1.3) 17-9 2010-04-01 TMP19A44 A/D Conversion Result Register 2 (Unit A, B and C) 7 6 5 4 3 2 ADAREG2 (0xFF00_4D3C) bit Symbol ADR21 Read/Write After reset 1 0 OVR2 ADR2RF R R R 0 0 0 Over RUN flag 0: Not generate 1: Generate A/D conversion result storage flag 1: Presence of conversion result ADR20 R 0 Store lower 2 bits of A/D conversion result "0" is read. Function bit Symbol 15 14 13 12 ADR29 ADR28 ADR27 ADR26 Read/Write 11 10 9 8 ADR25 ADR24 ADR23 ADR22 R After reset 0 Function Store upper 8 bits of A/D conversion result 23 22 21 20 19 18 17 16 27 26 25 24 bit Symbol Read/Write R After reset 0 31 30 29 28 bit Symbol Read/Write R After reset 0 A/D Conversion Result Register 3 (Unit A, B and C) 7 6 5 4 3 2 ADAREG3 (0xFF00_4D40) bit Symbol ADR31 Read/Write After reset 1 0 OVR3 ADR3RF R R R 0 0 ADR30 R 0 Store lower 2 bits of A/D conversion result Over RUN flag 0: Not generate 1: Generate "0" is read. Function bit Symbol 0 A/D conversion result storage flag 1: Presence of conversion result 15 14 13 12 11 10 9 8 ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read/Write R After reset 0 Function Store upper 8 bits of A/D conversion result 23 22 21 20 19 18 17 16 27 26 25 24 bit Symbol Read/Write R After reset 0 31 30 29 28 bit Symbol Read/Write R After reset 0 Analog/Digital Converter TMP19A44(rev1.3) 17-10 2010-04-01 TMP19A44 A/D Conversion Result Register 4 (Unit C) bit Symbol ADCREG4 (0xFF00_4E40) Read/Write After reset 7 ADR41 6 ADR40 5 4 R 0 3 2 R 0 Store lower 2 bits of A/D conversion result. "0" is read. Function bit Symbol Read/Write After reset Function 15 ADR49 23 14 ADR48 22 13 ADR47 12 ADR46 11 ADR45 10 ADR44 0 ADR4RF R 0 Over RUN flag 0Not generate 1Generate A/D conversion result storage flag 1: Presence of conversion result 9 ADR43 8 ADR42 17 16 26 25 24 2 1 OVR5 R 0 0 ADR5RF R 0 Over RUN flag 0Not generate 1Generate A/D conversion result storage flag 1: Presence of conversion result R 0 Store upper 8 bits of A/D conversion result. 21 20 19 18 bit Symbol Read/Write After reset 1 OVR4 R 0 R 0 31 30 29 28 bit Symbol Read/Write After reset 27 R 0 A/D Conversion Result Register 5 (Unit C) bit Symbol ADCREG5 (0xFF00_4E44) Read/Write After reset 7 ADR51 6 ADR50 R 0 Store lower 2 bits of A/D conversion result. 5 4 3 R 0 "0" is read. Function bit Symbol Read/Write After reset Function 15 ADR59 23 14 ADR58 22 13 ADR57 12 ADR56 9 ADR53 8 ADR52 17 16 25 24 R 0 31 Analog/Digital Converter 10 ADR54 R 0 Store upper 8 bits of A/D conversion result. 21 20 19 18 bit Symbol Read/Write After reset bit Symbol Read/Write After reset 11 ADR55 30 29 28 27 26 R 0 TMP19A44(rev1.3) 17-11 2010-04-01 TMP19A44 A/D Conversion Result Register 6 (Unit C) bit Symbol ADCREG6 (0xFF00_4E48) Read/Write After reset Function bit Symbol Read/Write After reset Function 7 ADR61 6 ADR60 5 4 R 0 3 2 1 OVR6 R 0 0 ADR6RF R 0 Over RUN flag 0Not generate 1 Generat e A/D conversion result storage flag 1: Presence of conversion result 9 ADR63 8 ADR62 17 16 26 25 24 2 1 OVR7 R 0 0 ADR7RF R 0 Over RUN flag 0Not generate 1 Generat e A/D conversion result storage flag 1: Presence of conversion result 9 ADR73 8 ADR72 17 16 25 24 R 0 Store lower 2 bits "0" is read. of A/D conversion result. 15 ADR69 14 ADR68 23 22 13 ADR67 12 ADR66 11 ADR65 10 ADR64 R 0 Store upper 8 bits of A/D conversion result. 21 20 19 18 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset 27 R 0 A/D Conversion Result Register 7 (Unit C) bit Symbol ADCREG7 (0xFF00_4E4C) Read/Write After reset Function bit Symbol Read/Write After reset Function 7 ADR71 6 ADR70 5 4 R 3 R 0 Store lower 2 bits "0" is read. of A/D conversion result. 15 ADR79 23 14 ADR78 22 13 ADR77 12 ADR76 R 0 31 Analog/Digital Converter 10 ADR74 R 0 Store upper 8 bits of A/D conversion result. 21 20 19 18 bit Symbol Read/Write After reset bit Symbol Read/Write After reset 11 ADR75 30 29 28 27 26 R 0 TMP19A44(rev1.3) 17-12 2010-04-01 TMP19A44 A/D Conversion Result Register SP (Unit A, B and C) 7 ADAREGSP (0xFF00_4D50) bit Symbol Read/Writ e After reset Function 6 5 4 3 2 ADRSPA1 ADRSPA0 1 OVRSPA ADRSPRFA 0 R R R R 0 0 0 0 Store lower 2 bits "0" is read. of A/D conversion result. Over RUN flag 0Not generate 1Generate A/D conversion result storage flag 1: Presence of conversion result bit Symbol Read/Writ e After reset Function 15 14 13 12 11 10 ADRSP9 ADRSP8 ADRSP7 ADRSP6 ADRSP5 ADRSP4 17 16 25 24 0 23 22 Store upper 8 bits of A/D conversion result. 21 20 19 18 R 0 31 Analog/Digital Converter 8 ADRSP2 R bit Symbol Read/Writ e After reset bit Symbol Read/Writ e After reset 9 ADRSP3 30 29 28 27 26 R 0 TMP19A44(rev1.3) 17-13 2010-04-01 TMP19A44 A/D Conversion Result Comparison Register 0 (Unit A, B and C) ADACOMREG0 (0xFF00_4D54) bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function 7 6 ADR21 ADR20 R/W 0 5 4 3 2 1 0 9 ADR23 8 ADR22 17 16 25 24 1 0 9 ADR23 8 ADR22 17 16 25 24 R 0 Store lower 2 bits "0" is read. of A/D conversion result. 15 ADR29 14 ADR28 23 22 13 ADR27 12 11 10 ADR26 ADR25 ADR24 R/W 0 Store upper 8 bits of A/D conversion result. 21 20 19 18 bit Symbol Read/Write After reset R 0 31 30 29 28 bit Symbol Read/Write After reset 27 26 R 0 A/D Conversion Result Comparison Register 1 (Unit A, B and C) ADACOMREG1 bit Symbol (0xFF00_4D58) Read/Write After reset Function bit Symbol Read/Write After reset Function 7 6 ADR21 ADR20 R/W 0 5 4 2 R 0 Store lower 2 bits "0" is read. of A/D conversion result. 15 ADR29 14 ADR28 23 22 13 ADR27 12 11 10 ADR26 ADR25 ADR24 R/W 0 Store upper 8 bits of A/D conversion result. 21 20 19 18 bit Symbol Read/Write After reset R 0 31 bit Symbol Read/Write After reset (Note) 3 30 29 28 27 26 R 0 To set or change a value in this register, the AD monitor function must be disabled (ADnMOD3<ADOBSV>="0"). Analog/Digital Converter TMP19A44(rev1.3) 17-14 2010-04-01 TMP19A44 17.2 Conversion Clock z The conversion time is calculated by the 46 conversion clock. A/D Conversion Clock Setting Register ADACLK (0xFF00_4D00) bit Symbol Read/Writ e After reset Function 7 TSH3 6 tSH2 5 tSH1 4 tSH0 3 2 ADCLK2 1 ADCLK1 0 ADCLK0 R/W R/W R/W R/W R R/W R/W R/W 1 0 0 0 0 0 0 0 Select the A/D sample hold time 1000: 8 conversion clock 1001:16 conversion clock 1010: 24 conversion clock 1011: 32 conversion clock 0011: 64 conversion clock 1100: 128 conversion clock 1101: 512 conversion clock "0" is read. Select the A/D prescaler output 000: fc (note1) 001: fc/2 010: fc/4 011: fc/8 Other than above: reserved 100: fc/16 111:reserved note1.Please change the setting from an initial value when 80MHz operates. note2 ADCLK<2:0 > is not initialized in software reset. ADDCLK2:0 fc /1 /2 /4 /8 /16 ADCLK Example: If fsys = fc = 80 MHz Prescaler [ADDCLK2:0] 1 1/2 1/4 tconv. (conversion time) 40MHz 1.15s 2.3s 4.6s Variable S/H time fc=fsys Conversion clock fc=40MHz ADCLK=40MHz (Prescalar 1/1) fc=80MHz ADCLK=40MHz (Prescalar 1/2) tconv. (conversion 80MHz Setting prohibited 1.15s 2.3s S/H time Conversion clk*8 (0.2us) Conversion clk*16 (0.4us) Conversion clk*24 (0.6us) Conversion clk*32 (0.8us) Conversion clk*64 (1.6us) Conversion clk*128 (3.2us) Conversion clk*512 (12.8us) time) tconv. (conversion time) 1.15s 1.35s 1.55s 1.75s 2.55s 4.15s 13.75s (Note) "Please do not change the analog to digital conversion clock setting in the analog to digital translation. " Analog/Digital Converter TMP19A44(rev1.3) 17-15 2010-04-01 TMP19A44 17.3 Description of Operations 17.3.1 Analog Reference Voltage The "H" level of the analog reference voltage shall be applied to the VREFH pin, and the "L" level shall be applied to the VREFL pin. By writing "0" to the ADMOD1<VREFON> bit, a switched-on state of VREFH-VREFL can be turned into a switched-off state. To start AD conversion, make sure that you first write "1" to the <VREFON> bit, wait for 3 s during which time the internal reference voltage should stabilize, and then write "1" to the ADnMOD0<ADS> bit. 17.3.2 Selecting the Analog Input Channel How the analog input channel is selected is different depending on A/D converter operation mode used. (1) Normal AD conversion mode If the analog input channel is used in a fixed state (ADnMOD0<SCAN>="0"): One channel is selected from analog input pins AINn0 through AINn3 and AINC0 through AINC7 by setting ADnMOD1<ADCH3 to 0> to an appropriate setting. If the analog input channel is used in a scan state (ADnMOD0<SCAN>="1"): One scan mode is selected from 16 scan modes by setting ADnMOD1<ADCH3 to 0> and ADSCN to appropriate settings. (2) Top-priority AD conversion mode One channel is selected from analog input pins AINn0 through AINn3 and AINC0 through AINC7 by setting ADnMOD2<HPADCH3 to 0> to an appropriate setting. After a reset, ADnMOD0<SCAN> is initialized to "0" and ADnMOD1<ADCH3:0> is initialized to "0000." This initialization works as a trigger to select a fixed channel input through the ANn0 pin. The pins that are not used as analog input channels can be used as ordinary input ports. If top-priority AD conversion is activated during normal AD conversion, normal AD conversion is discontinued, top-priority AD conversion is executed and completed, and then normal AD conversion is resumed. Example: A case in which repeat-scan conversion is ongoing at channels AINC0 through AINC3 with ADCMOD0 <REPEAT:SCAN> set to "11" and ADCMOD1<ADCH3:0> set to 0011, and top-priority AD conversion has been activated at AINC7 with ADCMOD2<HPADCH3:0>=0111: Top-priority AD has been activated Conversion Ch Ch0 Analog/Digital Converter Ch1 Ch2 Ch15 TMP19A44(rev1.3) 17-16 Ch2 Ch3 Ch0 2010-04-01 TMP19A44 17.3.3 Starting A/D Conversion Two types of A/D conversion are supported: normal AD conversion and top-priority AD conversion. Normal AD conversion is software activated by setting ADnMOD0<ADS> to "1." Top-priority AD conversion is software activated by setting ADnMOD2<HPADCE> to "1." 4 operation modes are made available to normal AD conversion. In performing normal AD conversion, one of these operation modes must be selected by setting ADnMOD0<2:1> to an appropriate setting. For top-priority AD conversion, only one operation mode can be used: fixed channel single conversion mode. Normal AD conversion can be activated using the HW activation source selected by ADnMOD4<ADHS>, and top-priority AD conversion can be activated using the HW activation source selected by ADnMOD4<HADHS>. If this bit is "0," normal and top-priority AD conversions are activated in response to the input of a falling edge through the ADTRGn pin. If this bit is "1," normal AD conversion is activated in response to TB1TRG generated by the 16bit timer 1, and top-priority AD conversion is activated in response to TB9TRG generated by the 16-bit timer 9. Software activation is still valid even after H/W activation has been authorized. (Note) When an external trigger is used for the HW start source of a top priority analog to digital translation, an external trigger cannot usually be set as analog to digital translation HW start. Each unit has a pin (unit A: ADTRGA, unit B: ADTRGB, unit C: ADTRGC) that is used exclusively for an external trigger. Inputting an external trigger from ADTRGSNC pin allows unit A and unit B to start simultaneously. When normal A/D conversion starts, the A/D conversion Busy flag (ADnMOD0<ADBF>) showing that A/D conversion is under way is set to "1." When top-priority A/D conversion starts, the A/D conversion Busy flag (ADnMOD2<ADBFHP>) showing that A/D conversion is under way is set to "1." If normal A/D conversion is interrupted by top-priority A/D conversion, the value of the Busy flag for normal A/D conversion before the start of top-priority A/D conversion is retained. The value of the conversion completion flag EOCFN for normal A/D conversion before the start of top-priority A/D conversion can also be retained. (Note) Normal A/D conversion must not be activated when top-priority A/D conversion is under way. If activated when top-priority A/D conversion is under way, the top-priority A/D conversion completion flag cannot be set, and the flag for previous normal A/D conversion cannot be cleared. To reactivate normal A/D conversion, a software reset (ADnMOD4<ADRST1:0>) must be performed before starting A/D conversion. The HW activation method must not be used to reactivate normal A/D conversion. If ADnMOD2<HPADCE> is set to "1" during normal A/D conversion, ongoing A/D conversion is discontinued and top-priority A/D conversion starts; specifically, A/D conversion (fixed channel single conversion) is executed for a channel designated by ADnMOD2<3:0>. After the result of this toppriority A/D conversion is stored in the storage register ADnREGSP, normal A/D conversion is resumed. If HW activation of top-priority A/D conversion is authorized during normal A/D conversion, ongoing A/D conversion is discontinued when requirements for activation using a resource are met, and toppriority A/D conversion (fixed channel single conversion) starts for a channel designated by ADnMOD2<3:0>. After the result of this top-priority A/D conversion is stored in the storage register ADnREGSP, normal A/D conversion is resumed. Analog/Digital Converter TMP19A44(rev1.3) 17-17 2010-04-01 TMP19A44 17.3.4 A/D Conversion Modes and A/D Conversion Completion Interrupts For A/D conversion, the following four operation modes are supported. For normal A/D conversion, an operation mode can be selected by setting ADnMOD0<2:1> to an appropriate setting. For top-priority A/D conversion, the fixed channel single conversion mode is automatically selected, irrespective of the ADnMOD0<2:1> setting. Fixed channel single conversion mode Channel scan single conversion mode Fixed channel repeat conversion mode Channel scan repeat conversion mode (1) Normal A/D conversion An operation mode is selected with ADnMOD0<REPEAT, SCAN>. As A/D conversion starts, ADnMOD0<ADBFN> is set to "1." When specified A/D conversion is completed, the A/D conversion completion interrupt (INTADn) is generated, and ADnMOD0<EOCF> showing the completion of A/D conversion is set to "1." If <REPEAT>="0," <ADBFN> returns to "0" concurrently with the setting of EOCF. If <REPEAT> is set to "1," <ADBFN> remains at "1" and A/D conversion continues. c Fixed channel single conversion mode If ADnMOD0 <REPEAT, SCAN> is set to "00," A/D conversion is performed in the fixed channel single conversion mode. In this mode, A/D conversion is performed once for one channel selected. After A/D conversion is completed, ADnMOD0<EOCF> is set to "1," ADnMOD0<ADBF> is cleared to "0," and the interrupt request INTAD is generated. <EOCF> is cleared to "0" upon read. d Channel scan single conversion mode If ADnMOD0 <REPET,SCAN> is set to "01," A/D conversion is performed in the channel scan single conversion mode. In this mode, A/D conversion is performed once for each scan channel selected. After A/D scan conversion is completed, ADnMOD0<EOCF> is set to "1," ADnMOD0<ADBF> is cleared to "0," and the interrupt request INTADn is generated. <EOCF> is cleared to "0" upon read. e Fixed channel repeat conversion mode If ADnMOD0<REPEAT,SCAN> is set to "10," A/D conversion is performed in fixed channel repeat conversion mode. In this mode, A/D conversion is performed repeatedly for one channel selected. After A/D conversion is completed, ADnMOD <EOCF> is set to "1." ADnMOD0 <ADBF> is not cleared to "0." It remains at "1." The timing with which the interrupt request INTADn is generated can be selected by setting ADMOD0 <ITM1:0> to an appropriate setting. <EOCF> is set with the same timing as this interrupt INTAD is generated. <EOCF> is cleared to "0" upon read. With <ITM1:0> set to "00," an interrupt request is generated each time one A/D conversion is completed. In this case, the conversion results are always stored in the storage register ADnREG0. After the conversion result is stored, EOCF changes to "1." With <ITM1:0> set to "01," an interrupt request is generated each time four A/D conversion are completed. In this case, the conversion results are sequentially stored in storage registers ADREG0 through ADREG3. After the conversion results are stored in ADREG3, <EOCF> is set to "1," and the storage of subsequent conversion results starts from ADnREG0. <EOCF> is cleared to "0" Analog/Digital Converter TMP19A44(rev1.3) 17-18 2010-04-01 TMP19A44 upon read. With <ITM1:0> set to "10" (applicable only to unit C), an interrupt request is generated each time eight A/D conversions are completed. In this case, the conversion results are sequentially stored in storage registers ADCREG0 through ADCREG7. After the conversion results are stored in ADCREG7, <EOCF> is set to "1," and the storage of subsequent conversion results starts from ADCREG0. <EOCF> is cleared to "0" upon read. f Channel scan repeat conversion mode If ADnMOD0 <REPEAT, SCAN> is set to "11," A/D conversion is performed in the channel scan repeat conversion mode. In this mode, A/D conversion is performed repeatedly for a scan channel selected. Each time one A/D scan conversion is completed, ADnMOD0 <EOCF> is set to "1," and the interrupt request INTADn is generated. ADnMOD0 <ADBF> is not cleared to "0." It remains at "1." <EOCF> is cleared to "0" upon read. To stop the A/D conversion operation in the repeat conversion mode (modes described in e and f above), write "0" to ADnMOD0 <REPEAT>. When ongoing A/D conversion is completed, the repeat conversion mode terminates, and ADnMOD0 <ADBF> is set to "0." Before switching from one mode to standby mode (such standby modes as IDLE, STOP and BUCKUP etc.), check that A/D conversion is not being executed. If A/D conversion is under way, you must stop it or wait until it is completed. (2) Top-priority A/D conversion Top-priority A/D conversion is performed only in fixed channel single conversion mode. The ADnMOD0<REPEAT, SCAN> setting has no relevance to the top-priority A/D conversion operations or preparations. As activation requirements are met, A/D conversion is performed only once for a channel designated by ADnMOD2<HPADCH3:0>. After the A/D conversion is completed, the top-priority A/D conversion completion interrupt is generated, ADnMOD2<EOCFHP> is set to "1," and <ADBFHP> returns to "0." The EOCFHP Flag is cleared upon read. Analog/Digital Converter TMP19A44(rev1.3) 17-19 2010-04-01 TMP19A44 Relationships between A/D Conversion Modes, Interrupt Generation Timings and Flag Operations Conversion mode Interrupt generation timing Fixed channel single conversion Fixed channel repeat conversion EOCF setting timing (see Note) After conversion is completed Each time one conversion is completed Each time four conversions are completed Each time eight conversions are completed (unit C only) Channel scan single After scan conversion conversion is completed Channel scan Each time one scan repeat conversion conversion is completed (Note) ADBF ADnMOD0 (after the interrupt ITM1:0 REPEAT SCAN is generated) After conversion is completed After one conversion is completed 0 0 0 1 00 1 0 After four conversions are completed 1 01 After eight conversions are completed 1 10 After scan conversion is completed After one scan conversion is completed 0 0 1 1 1 1 EOCF is cleared upon read. Analog/Digital Converter TMP19A44(rev1.3) 17-20 2010-04-01 TMP19A44 17.3.5 High-priority Conversion Mode By interrupting ongoing normal A/D conversion, top-priority A/D conversion can be performed. Toppriority A/D conversion can be software activated by setting ADnMOD2<HPADCE> to "1" or it can be activated using the HW resource by setting ADnMOD4<7:6> to an appropriate setting. If top-priority A/D conversion has been activated during normal A/D conversion, ongoing normal A/D conversion is interrupted, and single conversion is performed for a channel designated by ADnMOD2<3:0>. The result of single conversion is stored in ADnREGSP, and the top-priority A/D conversion interrupt is generated. After top-priority A/D conversion is completed, normal A/D conversion is resumed; the status of normal A/D conversion immediately before being interrupted is maintained. Top-priority A/D conversion activated while top-priority A/D conversion is under way is ignored. For example, if channel repeat conversion is activated for channels ANC0 through ANC7 and if <HPADCE> is set to "1" during ANC3 conversion, AN3 conversion is suspended, and conversion is performed for a channel designated by <HPADC3:0>. After the result of conversion is stored in ADCREGSP, channel repeat conversion is resumed, starting from ANC3. 17.3.6 A/D Monitor Function If ADnMOD3<ADOBSV> is set to "1," the A/D monitor function is enabled. If the value of the conversion result storage register specified by REGS<3:0> becomes larger or smaller ("larger" or "smaller" to be designated by ADOBIC) than the value of a comparison register, the A/D monitor function interrupt is generated. This comparison operation is performed each time a result is stored in a corresponding conversion result storage register, and the interrupt is generated if the conditions are met. Because storage registers assigned to perform the A/D monitor function are usually not read by software, overrun flag <OVRn> is always set and the conversion result storage flag <ADnRRF> is also set. To use the A/D monitor function, therefore, a flag of a corresponding conversion result storage register must not be used. Two values can be specified in each unit at a time for the comparison. 17.3.7 Storing and Reading A/D Conversion Results A/D conversion results are stored in upper and lower A/D conversion result registers for normal A/D conversion (ADAREG0 through ADARG3, ADBREG0 through ADBRG3, ADCREG0 through ADCRG7). In fixed channel repeat conversion mode, A/D conversion results are sequentially stored in ADnREG0 through ADnREG3 and ADnREG7. If <ITM1:0> is so set as to generate the interrupt each time one A/D conversion is completed, conversion results are stored only in ADnREG0. If <ITM1:0> is so set as to generate the interrupt each time four A/D conversions are completed, conversion results are sequentially stored in ADnREG0 through ADnREG3. Table 17.1 shows analog input channels and related A/D conversion result registers. Analog/Digital Converter TMP19A44(rev1.3) 17-21 2010-04-01 TMP19A44 Table 17.1 Analog Input Channels and Related A/D Conversion Result Registers A/D conversion result register Analog input channel Conversion Fixed channel repeat Fixed channel repeat modes other conversion mode conversion mode (port 7) than shown (every one (every four to the right conversion) conversions) AINA0/AINB0 AINA1/AINB1 AINA2/AINB2 AINA3/AINB3 ADAREG0/ ADBREG0 ADAREG1/ ADBREG1 ADRAEG2/ ADBREG2 ADAREG3/ ADBREG3 Fixed channel repeat conversion mode (every eight conversions) ADnREG0 ADAREG0 fixed/ ADBREG0 fixed ADnREG3 A/D conversion result register Analog input channel Conversion Fixed channel repeat Fixed channel repeat modes other conversion mode conversion mode (port 8) than shown (every one (every four to the right conversion) conversions) AINC0 ADCREG0 AINC1 ADCREG1 AINC2 ADCREG2 Fixed channel repeat conversion mode (every eight conversions) ADCREG0 ADCREG0 AINC3 ADCREG3 AINC4 ADCREG4 AINC5 ADCREG5 AINC6 ADCREG6 AINC7 ADCREG7 ADCREG0 fixed ADCREG3 17.3.8 ADCREG7 Data Polling To process A/D conversion results without using interrupts, ADnMOD0<EOCF> must be polled. If this flag is set, conversion results are stored in a specified A/D conversion result register. After confirming that this flag is set, read that conversion result storage register. In reading the register, make sure that you first read upper bits and then lower bits to detect an overrun. If OVRn is "0" and ADRnRF is "1" in lower bits, a correct conversion result has been obtained. Analog/Digital Converter TMP19A44(rev1.3) 17-22 2010-04-01 TMP19A44 18. Watchdog Timer (Runaway Detection Timer) The TMP19A44 has a built-in watchdog timer for detecting runaways. The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or other disturbances and remedying them to return the CPU to normal operation. If the timer detects a runaway, it generates a non-maskable interrupt to notify the CPU. By connecting the output of the watchdog timer to a reset pin (inside the chip), it is possible to force the watchdog timer to reset itself. 18.1 Configuration Fig. 18.1 shows the block diagram of the watchdog timer. WDMOD <RESCR> Reset control RESET pin Internal reset Interrupt request INTWDT WDMOD <WDTP1 : 0> Selector 2 fSYS/2 16 2 18 2 20 2 22 Q Binary counter (22 stages) R S Reset Internal reset Write 4EH Write B1H WDMOD <WDTE> Watchdog timer control register WDCR Internal data bus Fig. 18.1 Block Diagram of the Watchdog Timer Watchdog Timer (Runaway Detection Timer)TMP19A44(rev0.3) 18-1 2010-04-01 TMP19A44 18.2 Watchdog Timer Interrupt The watchdog timer consists of the binary counters that are arranged in 22 stages and work using the fSYS/2 system clock as an input clock. The outputs produced by these binary counters are 216, 218, 220, 222, 224 and 226. By selecting one of these outputs with WDMOD <WDTP1:0>, a watchdog timer interrupt can be generated when an overflow occurs, as shown in Fig. 18.2. Because the watchdog timer interrupt is a non-maskable interrupt factor, NMIFLG <WDT> at the INTC performs a task of identifying it. WDT counter Overflow n 0 WDT interrupt Write of a clear code WDT clear Fig. 18.2 Normal Mode When an overflow occurs, resetting the chip itself is an option to choose. If the chip is reset, a reset is affected for a 32-state time, as shown in Fig. 18.3. If this reset is affected, the clock fSYS that the clock gear generates by dividing the clock fC of the high-speed oscillator by 16 is used as an input clock fSYS/2. Overflow WDT counter n WDT interrupt Internal reset 32-state (12.8 s @ fC = 40 MHz, fsys = 5 MHz, fsys/2 = 2.5 MHz) Fig. 18.3 Reset Mode Watchdog Timer (Runaway Detection Timer)TMP19A44(rev0.3) 18-2 2010-04-01 TMP19A44 18.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. 18.3.1 c Watchdog Timer Mode Register (WDMOD) Specifying the detection time of the watchdog timer <WDTP1: 0> This is a 2-bit register for specifying the watchdog timer interrupt time for runaway detection. When a reset is effected, this register is initialized to WDMOD <WDTP1, 0> = "00." Fig. 18.4 shows the detection time of the watchdog timer. d Enabling/disabling the watchdog timer <WDTE> When reset, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled. To disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code (B1H) must be written to the WDCR register. This dual setting is intended to minimize the probability that the watchdog timer may inadvertently be disabled if a runaway occurs. To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to "1." e Watchdog timer out reset connection <RESCR> This is a register for specifying whether or not to reset the watchdog timer itself after a runaway is detected. As a reset initializes this setting to WDMOD <RESCR>="0," a reset initiated the output of the watchdog timer is not performed. 18.3.2 Watchdog Timer Control Register (WDCR) This is a register for disabling the watchdog timer function and controlling the clearing function of the binary counter. * Disabling control By writing the disable code (B1H) to this WDCR register after setting WDMOD <WDTE> to "0," the watchdog timer can be disabled. * - - - - - - - WDMOD 0 WDCR 1 0 1 1 0 0 0 1 Clears WDTE to "0." Writes the disable code (B1H). Enabling control Set WDMOD <WDTE> to "1." * Watchdog timer clearing control Writing the clear code (4EH) to the WDCR register clears the binary counter and allows it to resume counting. WDCR (Note) 0 1 0 0 1 1 1 0 Writes the clear code (4EH) Writing the disable code (BIH) clears the binary counter. Watchdog Timer (Runaway Detection Timer)TMP19A44(rev0.3) 18-3 2010-04-01 TMP19A44 WDMOD 0xFF00_4F00 7 bit Symbol WDTE Read/Write R/W After reset 1 WDT Function 6 WDTP2 0 5 WDTP1 R/W 0 4 WDTP0 3 2 1 I2WDT RESCR R/W 0 1 IDLE 0: 0: Stop Generate NMI 1: Start interrupt R 0 Selects WDT detection time "0" is read. control 16 1: Enable 000: 2 /fSYS 18 001: 2 /fSYS 0 R/W 0 Write "0." 20 010: 2 /fSYS 1: Internally connect WDT output to reset pin 22 011: 2 /fSYS 24 100: 2 /fSYS 26 101: 2 /fSYS 110: Setting prohibited 111: Setting prohibited Watchdog timer out control 0 Generates NMI interrupt 1 Connects WDTOUT to reset @ fc = 80 MHz Detection time of watchdog timer SYSCR1 Detection Time of Watchdog Timer clock gear value WDMOD<WDTP2:0> 000 001 010 011 100 101 000 fc 0.82 ms 3.28 ms 13.11 ms 52.43 ms 209.72 ms 0.84 s 100 (fc/2) 1.64 ms 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s 101 (fc/4) 3.28 ms 13.11 ms 52.43 ms 209.72 ms 838.86 ms 3.36 s 110 (fc/8) 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s 6.71 s 111 (fc/16) 13.11 ms 52.43 ms 209.72 ms 838.86 ms 3.36 s 13.42 s <GEAR2:0> Enable/disable control of the watchdog timer 0 1 Disable Enable Fig. 18.4 Watchdog Timer Mode Register 7 6 WDCR (0xFF00_4F04) Read/Write 4 3 2 1 0 After reset Function 5 W bit Symbol B1H : WDT disable code 4EH : WDT clear code Disable & clear of WDT B1H 4EH Others Disable code Clear code Fig. 18.5 Watchdog Timer Control Register Watchdog Timer (Runaway Detection Timer)TMP19A44(rev0.3) 18-4 2010-04-01 TMP19A44 18.4 Operation Description The watchdog timer generates the INTWDT interrupt after a lapse of the detection time specified by the WDMOD <WDTP2, 0> register. Before generating the INTWD interrupt, the binary counter for the watchdog timer must be cleared to "0" using software (instruction). If the CPU malfunctions (runs away) due to noise or other disturbances and cannot execute the instruction to clear the binary counter, the binary counter overflows and the INTWD interrupt is generated. The CPU is able to recognize the occurrence of a malfunction (runaway) by identifying the INTWD interrupt and to restore the faulty condition to normal by using a malfunction (runaway) countermeasure program. Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices. The watchdog timer begins operation immediately after a reset is cleared. In STOP mode, the watchdog timer is reset and in an idle state. When the bus is open ( BUSAK = "L"), it continues counting. In IDLE mode, its operation depends on the WDMOD <I2WDT> setting. Before putting it in IDLE mode, WDMOD <I2WDT> must be set to an appropriate setting, as required. Examples: c To clear the binary counter WDCR d 7 6 5 4 3 2 1 0 1 0 1 - - - - - To disable the watchdog timer WDMOD WDCR Note: Writes the clear code (4EH) To set the detection time of the watchdog timer to 218/fSYS WDMOD e 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 7 6 5 4 3 2 1 0 0 - - - - - - - 1 0 1 1 0 0 0 1 Clears WDTE to "0" Writes the disable code (B1H) If the watchdog timer is operated when the high-frequency oscillator is idle, the system reset operation initiated by the watchdog timer becomes erratic due to the unstable oscillation of the high-frequency oscillator. Therefore, do not operate the watchdog timer when the high-frequency oscillator is idle. Watchdog Timer (Runaway Detection Timer)TMP19A44(rev0.3) 18-5 2010-04-01 TMP19A44 19. 19.1 Real Time Clock (RTC) Functions 1) 2) 3) 4) 5) 19.2 Clock (hour, minute and second) Calendar (month, week, date and leap year) Selectable 12 (am/ pm) and 24 hour display Time adjustment or 30 seconds (by software) Alarm interrupt (selectable from 1sec/ 500msec/ 250msec/ 125msec/ 62.5msec or calendar) Block Diagram 32 KHz clock 1, 2, 4, 8 and 16 Hz l k Divider Alarm register Alarm selector 1s Carry hold Comparator INTRTC Clock Address bus Adjust RD WR Internal data bus R/W control D0~D16 Address Fig. 19.1 Block Diagram (Note 1) Western calendar year column: This product uses only the final two digits of the year. The year following 99 is 00 years. Please take into account the first two digits when handling years in the western calendar. (Note 2) Leap year: A leap year is divisible by 4 excluding a year divisible by 100; the year divisible by 100 is not considered to be a leap year. Any year divisible by 400 is a leap year. This product is considered the year divisible by 4 to be a leap year and does not take into account the above exceptions. It needs adjustments for the exceptions. Real Time Clock (RTC) TMP19A44 (rev1.3) 19-1 2010-04-01 TMP19A44 19.3 Registers 19.3.1 Control Register Table 19.1 PAGE0 (clock function) register Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 SECR 0xFF00_1500 40 sec 20 sec 10 sec 8 sec 4 sec MINR 0xFF00_1501 40 min 20 min 10 min 8 min 4 min HOURR 0xFF00_1502 20 hours 10 hours 8 hours 4 hours Bit1 Bit0 Function Read/Write 2 sec 1 sec Second column R/W 2 min 1 min Minute column R/W 2 hours 1 hours Hour column R/W W2 W1 W0 Day of the week column R/W /PM/AM DAYR 0xFF00_1504 DATER 0xFF00_1505 MONTHR 0xFF00_1506 Day 20 YEARR 0xFF00_1507 PAGER 0xFF00_1508 Interrupt enable RESTR 0xFF00_150C Year 80 Day 10 Day 8 Day 4 Day 2 Day 1 Day column R/W Oct. Aug. Apr. Feb. Jan. Month column R/W Year 10 Year 8 Year 4 Year 2 Year 1 Year column (lower two columns) R/W Adjustment Clock function enable Alarm enable PAGE setting PAGE register W, R/W Reset register W only Year 40 Year 20 1Hz enable 16Hz enable Clock reset Alarm reset Always write "0". (Note) Reading SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE0 captures the current state. Table 19.2 PAGE1 (alarm function) registers Symbol Address SECR 0xFF00_1500 MINR 0xFF00_1501 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read/Write 40 min 20 min 10 min 8 min 4 min 2 min 1 min Minute column R/W 10 hours 8 hours 4 hours 2 hours 1 hours Hour column R/W W2 W1 W0 Day of the week column R/W Day 4 Day 2 Day 1 Day column R/W 24/12 24-hour clock mode R/W 0xFF00_1502 20 HOURR hours /PM/AM DAYR 0xFF00_1504 DATER 0xFF00_1505 MONTH R 0xFF00_1506 YEARR 0xFF00_1507 0xFF00_1508 PAGER RESTR 0xFF00_150C Day 20 Day 10 Day 8 Leap-year setting Leap-year mode Adjustme Clock nt enable function Interrupt enable 1Hz enable 16Hz enable Clock reset Alarm reset Alarm enable Always write "0". PAGE setting R/W PAGE register W,R/W Reset register W only (Note 1) Reading SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE1 captures the current state. (Note 2) SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE0 and YEARR of PAGE1 (for leap year) must be read twice and compare the data captured. Real Time Clock (RTC) TMP19A44 (rev1.3) 19-2 2010-04-01 TMP19A44 19.3.2 Detailed Description of Control Register The RTC is not initialized by system reset. All registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 SECR Bit symbol 6 5 4 SE6 SE5 SE4 Read/Write 2 1 0 SE3 SE2 SE1 SE0 4 sec. column 2 sec. column 1 sec. column R/W After reset Function 3 Undefined "0" is read. 40 sec. column 20 sec. column 10 sec. column 8 sec. column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 0 1 1 3 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec : : 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 sec : 0 1 1 1 0 0 1 39 sec 1 0 0 0 0 0 0 40 sec : 1 0 0 1 0 0 1 49 sec 1 0 1 0 0 0 0 50 sec 0 0 1 59 sec : 1 0 Note) Real Time Clock (RTC) 1 1 Do not set data other than as shown above. TMP19A44 (rev1.3) 19-3 2010-04-01 TMP19A44 (2) Minute column register (for PAGE0/1) 7 MINR Bit symbol 6 5 4 MI6 MI5 MI4 Read/Write 2 1 0 MI3 MI2 MI1 MI0 4 min. column 2 min. column 1 min. column R/W Undefined After reset Function 3 "0" is read 40 min. column 20 min. column 10 min. column 8 min. column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min : : 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min : 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min : 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0 0 50 min 0 0 1 59 min 1 don't care : 1 0 Note) 1 Real Time Clock (RTC) 1 1 Do not set data other than as shown above. 1 1 1 1 1 TMP19A44 (rev1.3) 19-4 2010-04-01 TMP19A44 (3) Hour column register (for PAGE0/1) 1. 24-hour clock mode (MONTHR<MO0>="1") 7 HOURR 6 Bit symbol 5 4 3 HO5 HO4 HO3 Read/Write 2 1 0 HO2 HO1 HO0 R/W After reset Undefined Function "0"is read. 20 hour 10 hour 8 hour 4 hour 2 hour 1 hour column column column column column column 0 0 0 0 0 0 0 o' clock 0 0 0 0 0 1 1 o' clock 0 0 0 0 1 0 2 o' clock 8 o' clock : 0 0 1 0 0 0 0 0 1 0 0 1 9 o' clock 0 1 0 0 0 0 10 o' clock 0 1 1 0 0 1 19 o' clock 1 0 0 0 0 0 20 o' clock 0 1 1 23 o' clock 1 don't care : : 1 Note) 1 2. 0 Do not set data other than as shown above. 1 1 1 1 12-hour clock mode (MONTHR<MO0>="0") 7 HOURR 0 6 Bit symbol 5 4 3 HO5 HO4 HO3 Read/Write 1 0 HO2 HO1 HO0 4 hour column 2 hour column 1 hour column R/W Undefined After reset Function 2 "0"is read. PM/AM 10 hour column 8 hour column 0 0 0 0 0 0 0 o' clock (AM) 0 0 0 0 0 1 1 o' clock 0 0 0 0 1 0 2 o' clock : 0 0 1 0 0 1 9 o' clock 0 1 0 0 0 0 10 o' clock 0 1 0 0 0 1 11 o' clock 1 0 0 0 0 0 0 o' clock (PM) 1 0 0 0 0 1 1 o' clock 1 don't care Note) Do not set data other than as shown above. 1 Real Time Clock (RTC) 1 1 TMP19A44 (rev1.3) 19-5 1 1 2010-04-01 TMP19A44 (4) Day of the week column register (for PAGE0/1) 7 DAYR 6 5 4 3 2 Bit symbol WE2 Read/Write 1 0 WE1 WE0 R/W Undefined After reset Function W2 "0" is read. W1 W0 0 0 0 Sunday 0 0 1 Monday 0 1 0 Tuesday 0 1 1 Wednesday 1 0 0 Thursday 1 0 1 Friday 1 0 Saturday 1 Note) Do not set data other than as shown above. 1 1 1 don't care (5) Day column register (PAGE0/1) 7 DATER 6 Bit symbol 5 4 3 DA5 DA4 DA3 Read/Write 1 0 DA2 DA1 DA0 Day 2 Day 1 R/W After reset Function 2 Undefined "0" is read. Day 20 Day 10 Day 8 Day 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day : 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day : 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day : 1 0 1 0 0 1 29th day 1 1 0 0 0 0 30th day 1 1 0 0 0 1 31st day 1 don't care Note 1) Do not set data other than as shown above. Note 2) Do not set for non-existent days (e.g.: 30th Feb) 1 Real Time Clock (RTC) 1 1 TMP19A44 (rev1.3) 19-6 1 1 2010-04-01 TMP19A44 (6) Month column register (for PAGE0 only) 7 MONTHR 6 5 Bit symbol 4 3 2 1 0 MO4 MO4 MO2 MO1 MO0 2 months 1 month Read/Write R/W After reset Undefined Function "0" is read. 10 months Note) 8 months 4 months 0 0 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December Do not set data other than as shown above. (7) Selection of 24-hour clock or 12-hour clock (for PAGE1 only) 7 MONTHR 6 5 4 3 2 Bit symbol 1 0 MO0 Read/Write R/W After reset Undefined Function "0" is read. 1: 24-hour 0: 12-hour (Note) Do not change the MONTHR<MO0> bit while the RTC is in operation (PAGER<RNATMR>="1"). Real Time Clock (RTC) TMP19A44 (rev1.3) 19-7 2010-04-01 TMP19A44 (8) Year column register (for PAGE0 only) YEARR Bit symbol 7 6 5 4 YE7 YE6 YE5 YE4 Read/Write 2 1 0 YE3 YE2 YE1 YE0 4 years 2 years 1 years R/W After reset Function 3 Undefined 80 years 40 years 20 years 10 years 8 years 0 0 0 0 0 0 0 0 00 years 0 0 0 0 0 0 0 1 01 years 0 0 0 0 0 0 1 0 02 years 0 0 0 0 0 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 1 0 0 1 99 years : 1 Note) 0 0 1 Do not set data other than as shown above. (9) Leap year register (for PAGE1 only) 7 YEARR 6 5 4 3 2 Bit symbol 0 LEAP1 Read/Write LEAP0 R/W After reset Undefined Function 00: leap year 01: one year after leap year 10: two years after leap year 11: three years after leap year "0" is read. Real Time Clock (RTC) 1 TMP19A44 (rev1.3) 19-8 0 0 Current year is a leap-year. 0 1 Current year is the following a leap-year. 1 0 Current year is two years after a leap year. 1 1 Current year is three years after a leap year year 2010-04-01 TMP19A44 (10) PAGE register (for PAGE0/1) 7 PAGER 6 5 4 3 ENATMR Bit symbol INTENA ADJUST Read/Write R/W W After reset a read-modify- Function write operation cannot be performed. 0 Undefined INTRTC 0: Disabled "0" is read. 1: Enabled 2 1 0 ENAALM PAGE R/W R/W Undefined Undefined 0: Don't care Clock ALARM 1: Adjust 0: Disabled 0: Disabled 1: Enabled 1: Enabled "0" is read. PAGE selection (Note) Keep the setting order of <ENATMR>, <ENAAML> and <INTENA> as shown in the example below. Ensure an interval of time between Clock/Alarm and interrupt. PAGE 0 Selects Page0 1 Selects Page1 0 Don't care 1 Adjusts sec. counter by setting this bit to "1". If it is set when the time elapsed is within 0 and 29, the sec. counter is cleared to "0". If the time elapsed is within 30 and 59, the min. counter is carried and sec. counter is cleared to "0". The ADJUST signal is output during 1 cycle of fSYS. After being adjusted once, the ADJUST state is released automatically (PAGE0 only). ADJUST (11) Reset register (for PAGE0/1) RESTR (0xFF00_150C) 7 6 5 4 3 2 1 0 DIS1HZ DIS16HZ RSTTMR RSTALM DIS4HZ DIS8HZ Read/Write R/W R/W - R DIS2HZ After reset 1 0 0 1 Bit symbol A read-modify- Function write operation cannot be performed. 1 Hz 0: Enabled 1: Disabled RSTALM RSTTMR <DIS1HZ> <DIS2HZ> <DIS4HZ> <DIS8HZ> <DIS16HZ> Real Time Clock (RTC) 16 Hz 0: Enabled 1: Clock 1: Alarm reset reset 1: Disabled Always write "0". 0 Unused 1 Reset alarm register. 0 Unused 1 Reset clock register. 0 Enabled 1 Disabled TMP19A44 (rev1.3) 19-9 R/W 1 Hz 1 1 Hz 1 1 Hz 0: Enabled 0: Enabled 0: Enabled 1: Disabled 1: Disabled 1: Disabled 2010-04-01 TMP19A44 19.4 Operational description The RTC incorporates a sec. counter that generates an 1Hz signal from a 32.768 KHz signal. The sec. counter operation must be taken into account when using the RTC. 19.4.1 Clock Operation (1) Reading clock data 1. Using 1Hz interrupt The count-up of the internal data synchronizes with 1Hz interrupt. Data can be read correctly if reading data after 1Hz interrupt occurred. 2. Using pair reading There is a possibility that the clock data may be read incorrectly if the internal counter operates carry during reading. To ensure correct data reading, read the clock data twice as shown below. A pair of data read successively needs to match. Start PAGER<PAGE> = "0", then select PAGE0 Clock data reading (1st) Clock data reading (2nd) NO 1st data = 2nd data YES End Fig. 19.2 Flowchart of the clock data reading Real Time Clock (RTC) TMP19A44 (rev1.3) 19-10 2010-04-01 TMP19A44 (2) Writing clock data A carry during writing ruins correct data writing. The following procedure ensures the correct data writing. 1. Using 1Hz interrupt The count-up of the internal data synchronizes with 1Hz interrupt. Data can be written correctly if writing data after 1Hz interrupt occurred. 2. Resetting counter The RTC incorporates 15-stage counter that generates a 1Hz clock from 32,768 KHz. After resetting the counter, the data is written. If clearing the counter, an interrupt is output only first writing at half of the setting time. To ensure the correct clock counting, enable the 1Hz-interrupt after clearing the counter. And then set the time after the first interrupt (occurs at 0.5Hz) occurs. Start PAGER<PAGE>="0" then select PAGE0 RESTR<RSTTMR>="1" then reset counter RESTR<DIS1HZ>="0" then enable 1Hz interrupt First interrupt (After 0.5S) NO YES Time setting End Fig. 19.3 Flowchart of the clock data writing Real Time Clock (RTC) TMP19A44 (rev1.3) 19-11 2010-04-01 TMP19A44 3. Disabling the clock Writing "0" to PAGER<ENATMR> disables clock operation including a carry. In the meantime, the 1 second carry hold circuit executes time adjustment instead. While the clock is disabled, the carry hold circuit holds a 1 second carry signal from a divider. When the clock becomes enabled, the carry signal is output to the clock, the time is revised and operation continues. The disabled duration for one second and more causes slowing of clocks. Start Disabling clock Writing the clock data Enabling the clock End Fig. 19.4 Flowchart of the disabling clock Real Time Clock (RTC) TMP19A44 (rev1.3) 19-12 2010-04-01 TMP19A44 19.4.2 Alarm function By writing "1" to PAGER<PAGE>, the alarm function of the PAGE1 registers is enabled. The INTRTC outputs a 1-shot pulse by detecting the falling edge. The RTC is not initialized by reset. Clear the interrupt request flag in the interrupt controller when the clock or alarm function is used. (1) INTRTC interrupt is generated when the alarm register corresponds with the clock (2) 1Hz ,2Hz,4Hz,8Hz, 16Hz clock (1) How to use alarm To initialize the alarm, write "1" to RESTR<RSTALM>. It makes all alarm settings "don't care". In this case, the alarm always corresponds with the value of the clock. The INTRTC interrupt request is generated if PAGER <INENA> <ENAALM>="1". Setting alarm for min., hour, date and day is done by writing data to the relevant PAGE1 register. Each writing releases the "don't care" state respectively. When all setting contents correspond with the setting of PAGER<INTENA> <ENAALM>=1", the RTC generates an INTRTC interrupt. However, contents which have not been set up ("don't care" state) are always considered to be corresponding. Contents which have already been set up cannot be returned independently but all together to the "don't care" state by initializing the alarm. The following is an example program for outputting an alarm from the ALARM pin at noon (PM12:00) every day. LD LD LD LD LD LD LD LD (PAGER), 09H (RESTR), D7H (DAYR), FFH (DATAR),FFH (HOURR), FFH (MINR), FFH (HOURR), 12H (MINR), 00H LD LD (PAGER), 0CH (PAGER), 8CH ; ; ; Disables alarm, sets PAGE1 Initializes alarm ; ; ; ; Sets 12 o'clock Sets 00 min. Set up time 31 s (Note) ; ; Enables alarm Enables interrupt When the CPU is operating at high frequency oscillation, it may take a maximum of one clock at 32 kHz (about 30us) for the time register setting to become valid. In the above example, it is necessary to set 31s of set up time between setting the time register and enabling the alarm register. (Note) This set up time is unnecessary when you use only internal interruption. Real Time Clock (RTC) TMP19A44 (rev1.3) 19-13 2010-04-01 TMP19A44 (2) 1Hz clock (2,4,8,16Hz clock) Setting PAGER<ENAALM>= "0", RESTR<DIS1HZ>= "0" and <DIS16HZ>= "1" generates an INTRC interrupt per second. Real Time Clock (RTC) TMP19A44 (rev1.3) 19-14 2010-04-01 TMP19A44 20. Key-on Wakeup Circuit 20.1 Outline * The TMP19A44 has 32 key inputs, KEY00 to KEY31, which can be used for releasing the Standby mode or for external interrupts. Note that interrupt processing is executed with one interrupt factor for the 32 inputs. (This is programmed in the CG block.) Each key input can be configured to be used or not, by programming (KWUPSTn)<KEYnEN>. * The active state of each input can be configured to the rising edge, the falling edge, both edges, the high level or the low level, by programming (KWUPSTn)<KEYn>. * An interrupt request is cleared by programming the key interrupt request clear register KWUPCLR in the interrupt processing. * The key input pins have pull-up functions, which can be switched between static pull-up and dynamic pull-up by programming the (KWUPSTn)<DPEn> bit. This programming is needed for each of 32 inputs. KEYEN INT Static Pull-up Dynamic Pull-up RD Clr 1 KUPIN KWUPINT 1 IPH 1 IPH Level/Edge fs DPUP fs <DPE> PKEY 1 RD Clr IPH 1 <DPE> IPH High/Low Level 20.2 Key-on Wakeup Operation The TMP19A44 has 32 key input pins, KEY00 to KEY31. Program the IMCGD<KWUPEN> register in the CG to determine whether to use the key inputs for releasing the Standby mode or for normal interrupts. Setting <KWUPEN> to "1" causes all the key inputs, KEY00 to KEY31, to be used for interrupts for releasing the STOP mode. Program KWUPSTn<KEYnEN> to enable or disable interrupt inputs for each key input pin. Also, program KWUPSTn<KEYn2: KEYn0> to define the active state of each key input pin to be used. Detection of key inputs is carried out in the KWUP block, and the detection results are notified to the IMCGD register in the CG as the active high level. Therefore, program IMCGD<EMCGD2:0> to "001" to determine the detection level to the high level. The results of detection in the CG are also notified to the interrupt controller INTC as the active high level. Therefore, program the INTC to "01" to define the corresponding interrupt as the high level. Setting IMCGD<KWUPEN> to 0 (default) configures all the input pins, KEY00 to KEY31 to the normal interrupts. In this case, you don't have to make settings at the CG, but just specify the INTC detection level to the high level. Program KWUPSTn in the same way to enable or disable each key input and define their active states. Writing "1010" to KWUPCLR during interrupt processing clears all the key interrupt requests. (Note) If two or more key inputs are generated, all the key input requests will be cleared by clearing interrupt requests. Key-on Wakeup Circuit TMP19A44(rev1.3)20-1 2010-04-01 TMP19A44 20.3 Pull-up Function Each key input has the pull-up function and can be programmed by setting the register in the port. When a static pull-up is set, the pull-up function can be used regardless of what is set in KWUPSTn<KEYnEN > (it is controlled by the PxPUP<PExx> bit of each port). Key-on Wakeup Control 7 KWUPCNT Bit Symbol (0xFF00_1A84) Read/Write After reset Function 6 5 T2S1 R/W R 0 0 This can be Make sure that read as "0." you write "0." 15 14 4 T2S0 3 T1S1 0 0 Dynamic pull-up duration 00: 256/fs 10: 1024/fs 01: 512/fs 11: 2048/fs 13 12 0 0 Dynamic pull-up duration 00: 2/fs 10: 8/fs 01: 4/fs 11: 16/fs R After reset 0 23 22 21 20 R 0 This can be read as "0." 11 10 9 8 19 18 17 16 27 26 25 24 R After reset 0 This can be read as "0." 31 30 Bit Symbol Read/Writ e 29 28 R After reset Function 0 This can be read as "0." Bit Symbol Read/Writ e Function 1 R/W Bit Symbol Read/Writ e Function 2 T1S0 0 This can be read as "0." Key-on Wakeup Circuit TMP19A44(rev1.3)20-2 2010-04-01 TMP19A44 Dynamic pull-up operation is executed as shown below. T1 T2 Pull-up is executed only in the T1 period determined by <T1S1:0>. Pull-up is not executed in the remaining period. 00: 2/fs (62.5 s @fs = 32 kHz) 01: 4/fs (125 s @fs = 32 kHz) 10: 8/fs (250 s @fs = 32 kHz) 11: 16/fs (500 s @fs = 32 kHz) Dynamic pull-up operation is repeated in the T2 cycle determined by <T2S1:0>. 00: 256/fs (8 ms @fs = 32 kHz) 01: 512/fs (16 ms @fs = 32 kHz) 10: 1024/fs (32 ms @fs = 32 kHz) 11: 2048/fs (64 ms @fs = 32 kHz) fs must be operated while dynamic pull-up is used. Key input must be started during the second T1 period after enabling dynamic pull-up. Key-on Wakeup Circuit TMP19A44(rev1.3)20-3 2010-04-01 TMP19A44 20.4 Key Input Detection Timing 1) When the static pull-up is selected by setting PnPE<PEn> to 1 and KWUPSTn<DPEn> to 0: The active state of each key input can be defined to the high or low level or to the rising and/or falling edges by setting KWUPSTn<KEYn2:0>. The active states of key inputs are continuously detected. 2) When the dynamic pull-up is selected by setting PnPE<PEn> to 1 and KWUPSTn<DPEn> to 1: Detection of the active state of each key input (interrupt detection) is carried out only at the edge one-clock before fs at the end of the T1 period. Therefore, a key input not shorter than the T2 period is needed. In this case, do not define the active state to the high or low level. There is a delay up to the T2 period before key input detection. The figure below shows an example of defining the active state to the falling edge. Pull-up(T1) (T2) T2 period or longer is required (L period) Key input H or High-Z H or High-Z or L Interrupt detection timing Key input detection Internal sampling results Key-on Wakeup Circuit TMP19A44(rev1.3)20-4 2010-04-01 TMP19A44 The external state of port value can be monitored during dynamic pull-up operation by referring to the PKEYn <PKEYn> register. Sampling is executed in the dynamic pull-up cycle. 7 PKEY0 (0xFF00_1A80) Bit Symbol Read/Write After reset Function Bit Symbol Read/Write After reset Function Bit Symbol Read/Write After reset Function Bit Symbol Read/Write After reset Function Key-on Wakeup Circuit PKEY07 6 5 4 3 2 1 0 PKEY06 PKEY05 PKEY04 PKEY03 PKEY02 PKEY01 PKEY00 R 0 0 0 0 0 0 0 0 PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 15 14 13 12 11 10 9 8 PKEY15 PKEY14 PKEY13 PKEY12 PKEY11 PKEY10 PKEY09 PKEY08 R 0 0 0 0 0 0 0 0 PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 23 22 21 20 19 18 17 16 PKEY23 PKEY22 PKEY21 PKEY20 PKEY19 PKEY18 PKEY17 PKEY16 R 0 0 0 0 0 0 0 0 PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 31 30 29 28 27 26 25 24 PKEY31 PKEY30 PKEY29 PKEY28 PKEY27 PKEY26 PKEY25 PKEY24 R 0 0 0 0 0 0 0 0 PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE PORT STATE 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" 0:"Lo" 1:"Hi" TMP19A44(rev1.3)20-5 2010-04-01 TMP19A44 KWUPST00 (0xFF00_1A00) bit Symbol 7 DPE00 6 KEY002 Read/Write After reset Function 0 0 5 KEY001 R/W 1 4 KEY000 3 1 0 KEY00EN R 0 This can be read as "0." 0 Pull-up Define the KEY00 active state 0:Static 000: "L" level 1:Dynamic 001: "H" level 010: Falling edge 011: Rising edge 15 2 R/W 0 KEY00 interrupt input 0: Disable 1: Enable 100: Both edges 14 13 12 11 10 9 8 19 18 17 16 27 26 25 24 3 2 1 Bit Symbol Read/Write R 0 After reset Function This can be read as "0." 23 22 21 20 Bit Symbol Read/Write R 0 After reset Function This can be read as "0." 31 30 29 28 Bit Symbol Read/Write R 0 After reset Function KWUPST31 (0xFF00_1A7C) bit Symbol Read/Write This can be read as "0." 7 DPE31 After reset Function 0 6 KEY312 0 5 KEY311 R/W 1 4 KEY310 15 12 11 10 9 8 19 18 17 16 27 26 25 24 R 0 This can be read as "0." 23 22 21 20 Bit Symbol Read/Write R 0 After reset This can be read as "0." 31 30 Bit Symbol Read/Write 29 28 R 0 After reset Function KEY31 interrupt input 1: Enable After reset Function R/W 0 0: Disable Bit Symbol Read/Write Function R 0 This can be read as "0." 0 Pull-up Define the KEY31 active state 0:Static 000: "L" level 1:Dynamic 001: "H" level 010: Falling edge 011: Rising edge 100: Both edges 14 13 0 KEY31EN This can be read as "0." Key-on Wakeup Circuit TMP19A44(rev1.3)20-6 2010-04-01 TMP19A44 20.5 Detection of Key Input Interrupts and Clearance of Requests When KEYnEN is set to 1 and an active signal is input to KEYn, the KEYINTn channel that corresponds to KWUPINTn is set to "1," indicating that an interrupt is generated. The KWUPINTn is the read-only register. Reading this register clears the corresponding bit that has been set to "1" and the interrupt request. (A clear by KWUPCLR is also possible. If the active state is set to the high or low level, the corresponding bit of the KWUPINTn register remains "1" after it is read, unless the external input is withdrawn. 7 KWUPINT (0xFF00_1A8C) 6 5 4 3 2 1 0 bit Symbol KEYINT7 KEYINT6 KEYINT5 KEYINT4 KEYINT3 KEYINT2 KEYINT1 KEYINT0 Read/Write R After reset 0 0 0 0 0 0 0 0 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Function 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 15 14 13 12 0:Not generated 1:Generated 11 0:Not generated 1:Generated 10 0:Not generated 1:Generated 9 bit Symbol KEYINT15 KEYINT14 KEYINT13 KEYINT12 KEYINT11 KEYINT10 KEYINT9 Read/Write R After reset 0 0 0 0 0 0 0 Function Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 8 KEYINT8 0 Interrupt 0:Not generated 1:Generated 23 22 21 20 19 18 17 16 bit Symbol KEYINT23 KEYINT22 KEYINT21 KEYINT20 KEYINT19 KEYINT18 KEYINT17 KEYINT16 Read/Write R After reset 0 0 0 0 0 0 0 0 Function Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 31 30 29 28 27 26 25 24 bit Symbol KEYINT31 KEYINT30 KEYINT29 KEYINT28 KEYINT27 KEYINT26 KEYINT25 KEYINT24 Read/Write R After reset 0 0 0 0 0 0 0 0 Function Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt 0:Not generated 1:Generated Key-on Wakeup Circuit 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated TMP19A44(rev1.3)20-7 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 0:Not generated 1:Generated 2010-04-01 TMP19A44 7 KWUPCLR bit Symbol (0xFF00_1A88) Read/Write After reset Function 6 5 4 3 KEYCLR3 2 KEYCLR2 R 1 0 KEYCLR1 KEYCLR0 W 0 Writing "1010" clears all the key factors. This can be read as "0." 15 14 13 This can be read as "0." 11 10 12 9 8 Bit Symbol Read/Write After reset This can be read as "0." Function 23 22 Bit Symbol R 0 21 20 Read/Write After reset This can be read as "0." Function 31 30 Bit Symbol Read/Write After reset This can be read as "0." Function Key-on Wakeup Circuit 19 18 17 16 27 26 25 24 R 0 29 28 R 0 TMP19A44(rev1.3)20-8 2010-04-01 TMP19A44 20.6 Setting example Cautions on Use of Key Inputs with Pull-up Enabled A) When you make the first setting after turning the power ON (Example: port E0 with interrupts at both edges) 1) Make a setting of the port. PECR<PE0C> = "0" The setting for input pin. PEFC1<PE0F> = "1" The function is set to the key. PEPUP<PEE0> = "1" Pull-up ON control PEIE<PIEE0> = "1" Input enabled 2) Set KWUPST08<KEY08EN> to "0" for the key input to be used. 3) Set KWUPST08<KEY082:KEY080> to "100" to define the active state of the key input to be used. 4) Set KWUPST08<KEY08EN> to "1" for the key input to be used. 5) Wait until the pull-up operation is completed. 6) Set KWUPCLR to "1010" to clear interrupt requests. 7) Program the CG and the INTC by setting IMCGD3<EMCGC2:0> to "001" and IMCGD3<KWUPEN> to "1." (Refer to Chapter 6, "Interrupt Settings" for the details of setting methods.) B) To change the active state of a key input during operation 1) Disable key interrupts by setting IMC04<IL122:120> to "000" at the INTC. 2) Set KWUPST08<KEY08EN> to "0" for the key input to be used. 3) Change the active state by setting KWUPST08<KEY082:KEY080> to "000" for the key input to be changed. (Example: Lo level interrupt) 4) Set KWUPST08<KEY08EN> to "1" for the key input to be used. 5) Clear interrupt requests by setting KWUPCLR to "1010." 6) Enable the key interrupt at the INTC. Set IMC04<IL122:120> to a desired level "xxx." C) To enable a key input during operation 1) Disable key interrupts by setting IMC04<IL122:120> to "000" at the INTC. 2) Set KWUPST08KEY08EN to "0" for the key input to be used. 3) Define the active state of the key input to be used at the corresponding KWUPST08. 4) Set KWUPST08KEY08EN to "1" for the key input to be used. 5) Wait until the pull-up operation is completed. 6) Clear interrupt requests by setting KWUPCLR. 7) Enable key interrupts at the INTC. (Set IMC04<IL122:120> to a desired level.) Key-on Wakeup Circuit TMP19A44(rev1.3)20-9 2010-04-01 TMP19A44 Cautions on Use of Key Inputs with Pull-up Disabled A) When you make the first setting after turning the power ON 1) PECR<PE0C> = "0" The setting for input pin. PEFC1<PE0F> = "1" The function is set to the key. PEPUP<PEE0> = "0" Pull-up OFFcontrol PEIE<PIEE0> = "1" Input enabled 2) Set KWUPST08KEY08EN to "0" for the key input to be used. 3) Set KWUPST08<KEY082:KEY080> to "000" to define the active state of the key input to be used. 4) Set KWUPST08KEY08EN to "1" for the key input to be used. 5) Set KWUPCLR to "1010" to clear interrupt requests. 6) Set KWUPST08KEY08EN to "1" for the key input to be used. 7) Program the CG and the INTC. (Refer to Chapter 6, "Interrupt Settings" for the details of setting methods.) B) To change the active state of a key input during operation 1) Disable key interrupts by setting IMC04<IL122:120> to "000" at the INTC. 2) Set KWUPST08KEY08EN to "0" for the key input to be used. 3) Change the active state by setting KWUPSTn for the key input to be changed. 4) Set KWUPST08KEY08EN to "1" for the key input to be used. 5) Clear interrupt requests by setting KWUPCLR. 6) Enable key interrupts at the INTC. (Set IMC04<IL122:120> to a desired level.) C) To enable a key input during operation 1) Disable key interrupts by setting IMC04<IL122:120> to "000" at the INTC. 2) Set KWUPST08KEY08EN to "0" for the key input to be used. 3) Define the active state by setting KWUPSTn for the key input to be used. 4) Set KWUPST08KEY08EN to "1" for the key input to be used. 5) Clear interrupt requests by setting KWUPCLR. 6) Set KWUPSTnKEYnEN to "1" for the key input to be used. 7) Enable key interrupts at the INTC. (Set IMC04<IL122:120> to a desired level.) Key-on Wakeup Circuit TMP19A44(rev1.3)20-10 2010-04-01 TMP19A44 21. ROM Correction Function This chapter describes the ROM correction function built into the TMP19A44. 21.1 Features * Using this function, twelve pieces of eight-word data can be replaced. * If an address (lower 5 bits are "don't care" bits) written to the address register matches an address generated by the PC or DMAC, ROM data is replaced by data generated by the ROM correction data register which is established in a RAM area assigned to the above address register. * ROM correction is automatically authorized by writing an address to each address register. * If ROM correction cannot be executed using eight-word data due to a program modification or for other reasons, it is possible to place a "jump-to-RAM" instruction in a data register in a RAM area and to correct ROM data in that RAM area. 21.2 Description of Operations By setting in the address register ADDREGn a physical address (including a projection area) of the ROM area to be corrected, ROM data can be replaced by data generated by a data register in a RAM area assigned to ADDREGn. The ROM correction function is automatically enabled when an address is set in ADDREGn, and it cannot be disabled. After a reset, the ROM correction function is disabled. Therefore, to execute ROM correction with the initialization after a reset is cleared, it is necessary to set an address in ADDREG. As an address is set in ADDREG, the ROM correction function is enabled for this register. If the CPU has the bus authority, ROM data is replaced when the value generated by the PC matches that of the address register. If the DMAC has the bus authority, ROM data is replaced when a source or destination address generated by the DMAC matches the value of the address register. For example, if an address is set in ADDREG0 and ADDREG3, the ROM correction function is enabled for this area; match detection is performed on these registers, and data replacement is executed if there is a match. Data replacement is not executed for ADDREG1, ADDREG2, and ADDREG4 through ADDREG7. Although the bit <31:5> exists in address registers, match detection is performed on A<19:5> for reasons of circuitry simplification. Internal processing is that data replacement is executed when the calculation of a logical product is completed by multiplying the ROMCS signal showing a ROM area by the result of a match detection operation performed by ROM correction circuitry. If eight-word data is replaced, an address for ROM correction can be established only on an eight-word boundary, and data is replaced in units of 32 bytes. If only part of 32-byte data must be replaced with different data, the addresses that do not need to be replaced must be overwritten with the same data as the one existing prior to data replacement. ROM Correction Function TMP19A44(rev1.3)21-1 2010-04-01 TMP19A44 ADDREGn registers and RAM areas assigned to them are as follows: Register Address RAM area Number of words ADDREG0 0xff00_0000 0xFFFF_FE80 - 0xFFFF_FE9F 8 ADDREG1 0xff00_0004 0xFFFF_FEA0 - 0xFFFF_FEBF 8 ADDREG2 0xff00_0008 0xFFFF_FEC0 - 0xFFFF_FEDF 8 ADDREG3 0xff00_000C 0xFFFF_FEE0 - 0xFFFF_FEFF 8 ADDREG4 0xff00_0010 0xFFFF_FF00 - 0xFFFF_FF1F 8 ADDREG5 0xff00_0014 0xFFFF_FF20 - 0xFFFF_FF3F 8 ADDREG6 0xff00_0018 0xFFFF_FF40 - 0xFFFF_FF5F 8 ADDREG7 0xff00_001C 0xFFFF_FF60 - 0xFFFF_FF7F 8 ADDREG8 0xff00_0020 0xFFFF_FF80 - 0xFFFF_FF9F 8 ADDREG9 0xff00_0024 0xFFFF_FFA0 - 0xFFFF_FFBF 8 ADDREGA 0xff00_0028 0xFFFF_FFC0 - 0xFFFF_FFDF 8 ADDREGB 0xff00_002C 0xFFFF_FFE0 - 0xFFFF_FFFF 8 (Note 1) To use the ROM correction function, the ROM must be unprotected. An instruction to be corrected under ROM protection is replaced by an instruction in RAM. Neither ROM read nor DMAC setting can be executed by the instruction that the ROM correction is applied. (Note 2) When executing ROM correction to the ROM area, upper address specified in the address register is ignored and the address [19:5] is decoded. ROM Correction Function TMP19A44(rev1.3)21-2 2010-04-01 TMP19A44 Internal bus Address register Write detection & hold circuit of ADDREGn ADDREGn Authorize comparison Conversion circuit ROM RAM Comparison circuit Selector Operand Address Instruction Address TX19A/H1 processor Selector Operand Data Instruction Data Bus interface circuit Fig. 21.1 ROM Correction System Diagram ROM Correction Function TMP19A44(rev1.3)21-3 2010-04-01 TMP19A44 21.3 Registers (1) Address registers ADDREG0 bit Symbol 7 ADD07 6 ADD06 (0xFF00_0000) Read/Write bit Symbol 4 3 0 0 Set the physical address of the ROM area to correct. This can be read as "0". 0Disable 15 ADD015 14 ADD014 13 ADD013 1Enable 12 ADD012 11 ADD011 10 ADD010 9 ADD09 8 ADD08 18 ADD018 17 ADD017 16 ADD016 R/W 0 Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD019 Read/Write R After reset Function 0 ADD00 0 After reset bit Symbol 1 R Read/Write Function 2 R/W After reset Function 5 ADD05 R/W 1 0 This can be read as This can be read as "1". "0". 31 30 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function ADDREG1 bit Symbol 0 This can be read as "0". 7 ADD17 6 ADD16 (0xFF00_0004) Read/Write After reset Function bit Symbol 1 This can be read as "1". 5 ADD15 4 3 1 R R 0 0 0 Set the physical address of the This can be read as "0". ROM area to correct. 15 ADD115 0 ADD10 R/W 14 ADD114 13 ADD113 12 ADD112 Read/Write 11 ADD111 0Disable 1Enable 10 ADD110 9 ADD19 8 ADD18 R/W After reset 0 Function Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD119 bit Symbol Read/Write 18 ADD118 R After reset Function 2 17 ADD117 16 ADD116 R/W 1 0 This can be read as "1". 31 30 This can be read as "0". 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 This can be read as "0". 1 This can be read as "1". Fig. 21.2 ROM correction registers ROM Correction Function TMP19A44(rev1.3)21-4 2010-04-01 TMP19A44 ADDREG2 bit Symbol 7 ADD27 6 ADD26 (0xFF00_0008) Read/Write bit Symbol 4 3 0 0 0 This can be read as "0". 0Disable 15 ADD215 14 ADD214 13 ADD213 1Enable 12 ADD212 11 ADD211 R/W 0 Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD219 Read/Write 10 ADD210 9 ADD29 8 ADD28 18 ADD218 17 ADD217 16 ADD216 R After reset Function 0 ADD20 Set the physical address of the ROM area to correct. After reset bit Symbol 1 R Read/Write Function 2 R/W After reset Function 5 ADD25 R/W 1 0 This can be read as This can be read as "1". "0". 31 30 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 1 This can be read as "0". 7 ADD37 6 ADD36 This can be read as "1". 5 ADD35 4 3 2 1 0 ADD30 ADDREG3 bit Symbol (0xFF00_000C) Read/Write R/W R R After reset 0 0 0 Function bit Symbol Set the physical address of the This can be read as "0". ROM area to correct. 15 ADD315 14 ADD314 13 ADD313 12 ADD312 Read/Write 11 ADD311 10 ADD310 9 ADD39 8 ADD38 R/W After reset 0 Function Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD319 bit Symbol Read/Write 18 ADD318 R After reset Function 0Disable 1Enable 17 ADD317 16 ADD316 R/W 1 0 This can be read as "1". 31 30 This can be read as "0". 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 This can be read as "0". 1 This can be read as "1". Fig. 21.3 ROM correction registers ROM Correction Function TMP19A44(rev1.3)21-5 2010-04-01 TMP19A44 ADDREG4 bit Symbol 7 ADD47 6 ADD46 (0xFF00_0010) Read/Write bit Symbol 4 3 0 0 0 This can be read as "0". 0Disable 15 ADD415 14 ADD414 13 ADD413 1Enable 12 ADD412 11 ADD411 R/W 0 Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD419 Read/Write 10 ADD410 9 ADD49 8 ADD48 18 ADD418 17 ADD417 16 ADD416 R After reset Function 0 ADD40 Set the physical address of the ROM area to correct. After reset bit Symbol 1 R Read/Write Function 2 R/W After reset Function 5 ADD45 R/W 1 0 This can be read as This can be read as "1". "0". 31 30 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function ADDREG5 bit Symbol 0 This can be read as "0". 7 ADD57 6 ADD56 (0xFF00_0014) Read/Write After reset Function bit Symbol 1 This can be read as "1". 5 ADD55 4 3 1 R R 0 0 0 Set the physical address of the This can be read as "0". ROM area to correct. 15 ADD515 0 ADD50 R/W 14 ADD514 13 ADD513 12 ADD512 Read/Write 11 ADD511 0Disable 1Enable 10 ADD510 9 ADD59 8 ADD58 R/W After reset 0 Function Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD519 bit Symbol Read/Write 18 ADD518 R After reset Function 2 17 ADD517 16 ADD516 R/W 1 0 This can be read as "1". 31 30 This can be read as "0". 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 This can be read as "0". 1 This can be read as "1". Fig. 21.4 ROM correction registers ROM Correction Function TMP19A44(rev1.3)21-6 2010-04-01 TMP19A44 ADDREG6 bit Symbol 7 ADD67 6 ADD66 (0xFF00_0018) Read/Write bit Symbol 4 3 0 0 0 This can be read as "0". 0Disable 15 ADD615 14 ADD614 13 ADD613 1Enable 12 ADD612 11 ADD611 R/W 0 Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD619 Read/Write 10 ADD610 9 ADD69 8 ADD68 18 ADD618 17 ADD617 16 ADD616 R After reset Function 0 ADD60 Set the physical address of the ROM area to correct. After reset bit Symbol 1 R Read/Write Function 2 R/W After reset Function 5 ADD65 R/W 1 0 This can be read as This can be read as "1". "0". 31 30 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 1 This can be read as "0". 7 ADD77 6 ADD76 This can be read as "1". 5 ADD75 4 3 2 1 0 ADD70 ADDREG7 bit Symbol (0xFF00_001C) Read/Write R/W R R After reset 0 0 0 Function bit Symbol Set the physical address of the This can be read as "0". ROM area to correct. 15 ADD715 14 ADD714 13 ADD713 12 ADD712 Read/Write 11 ADD711 10 ADD710 9 ADD79 8 ADD78 R/W After reset 0 Function Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD719 bit Symbol Read/Write 18 ADD718 R After reset Function 0Disable 1Enable 17 ADD717 16 ADD716 R/W 1 0 This can be read as "1". 31 30 This can be read as "0". 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 This can be read as "0". 1 This can be read as "1". Fig. 21.5 ROM correction registers ROM Correction Function TMP19A44(rev1.3)21-7 2010-04-01 TMP19A44 ADDREG8 bit Symbol 7 ADD87 6 ADD86 (0xFF00_0020) Read/Write bit Symbol 4 3 0 0 0 This can be read as "0". 0Disable 15 ADD815 14 ADD814 13 ADD813 1Enable 12 ADD812 11 ADD811 R/W 0 Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD819 Read/Write 10 ADD810 9 ADD89 8 ADD88 18 ADD818 17 ADD817 16 ADD816 R After reset Function 0 ADD80 Set the physical address of the ROM area to correct. After reset bit Symbol 1 R Read/Write Function 2 R/W After reset Function 5 ADD85 R/W 1 0 This can be read as This can be read as "1". "0". 31 30 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function ADDREG9 bit Symbol 0 This can be read as "0". 7 ADD97 6 ADD96 (0xFF00_0024) Read/Write After reset Function bit Symbol 1 This can be read as "1". 5 ADD95 4 3 1 R R 0 0 0 Set the physical address of the This can be read as "0". ROM area to correct. 15 ADD915 0 ADD90 R/W 14 ADD914 13 ADD913 12 ADD912 Read/Write 11 ADD911 0Disable 1Enable 10 ADD910 9 ADD99 8 ADD98 R/W After reset 0 Function Set the physical address of the ROM area to correct. 23 22 21 20 19 ADD919 bit Symbol Read/Write 18 ADD918 R After reset Function 2 17 ADD917 16 ADD916 R/W 1 0 This can be read as "1". 31 30 This can be read as "0". 29 28 Set the physical address of the ROM area to correct. 27 26 25 24 bit Symbol Read/Write R After reset Function 0 This can be read as "0". 1 This can be read as "1". Fig. 21.6 ROM correction registers ROM Correction Function TMP19A44(rev1.3)21-8 2010-04-01 TMP19A44 ADDREGA bit Symbol 7 ADDA7 6 ADDA6 (0xFF00_0028) Read/Write bit Symbol 4 3 0 0 0 This can be read as "0". 0Disable 15 ADDA15 14 ADDA14 13 ADDA13 1Enable 12 ADDA12 11 ADDA11 R/W 0 Set the physical address of the ROM area to correct. 23 22 21 20 19 ADDA19 Read/Write 10 ADDA10 9 ADDA9 8 ADDA8 18 ADDA18 17 ADDA17 16 ADDA16 R After reset Function 0 ADDA0 Set the physical address of the ROM area to correct. After reset bit Symbol 1 R Read/Write Function 2 R/W After reset Function 5 ADDA5 R/W 1 0 This can be read as "1". 31 This can be read as "0". 30 29 Set the physical address of the ROM area to correct. 28 27 26 25 24 1 0 ADDB0 bit Symbol Read/Write R After reset Function 0 1 This can be read as "0". 7 ADDB7 6 ADDB6 This can be read as "1". 5 ADDB5 4 3 2 ADDREGB bit Symbol (0xFF00_002C) Read/Write R/W R R After reset 0 0 0 Function bit Symbol Set the physical address of the This can be read as "0". ROM area to correct. 15 ADDB15 14 ADDB14 13 ADDB13 12 ADDB12 Read/Write 11 ADDB11 10 ADDB10 9 ADDB9 8 ADDB8 R/W After reset 0 Function Set the physical address of the ROM area to correct. 23 22 21 20 19 ADDB19 bit Symbol Read/Write 18 ADDB18 R After reset Function 0Disable 1Enable 17 ADDB17 16 ADDB16 R/W 1 0 This can be read as "1". This can be read as "0". Set the physical address of the ROM area to correct. 31 30 29 28 27 26 25 24 bit Symbol Read/Write R After reset Function 0 This can be read as "0". 1 This can be read as "1". (Note 1) Data cannot be transferred by DMA to the address register. However, data can be transferred by DMA to the RAM area where data for replacement is placed. The ROM correction function supports data replacement for both CPU and DMA access. (Note 2) Writing back the initial value "0x00" allows data at the reset address to be replaced. Fig. 21.7 ROM correction registers ROM Correction Function TMP19A44(rev1.3)21-9 2010-04-01 TMP19A44 22. Table of Special Function Registers [1] ROM correction [2] FLASH control [3] Protect control [4] Interrupt controller [5] DMA controller [6] Chip select/wait controller [7] Real time clock [8] Two-phase pulse input counter [9] High speed serial channel [10] Clock generator [11] Key-on wake-up [12] Port registers [13] 16-bit timer [14] 32-bit timer [15] I2CBUS/serial channel [16] UART/serial channel [17] 10-bit A/D converter [18] Watchdog timer Table of Special Function Registers TMP19A44(rev1.3)22-1 2010-04-01 TMP19A44 Little [1] ROM correction ADR Register name ADR Register name ADR Register name ADR Register name FF000000H 1H 2H 3H ADDREG0 " " " FF000010H 1H 2H 3H ADDREG4 " " " FF000020H 1H 2H 3H ADDREG8 " " " FF000030H 1H 2H 3H 4H 5H 6H 7H ADDREG1 " " " 4H 5H 6H 7H ADDREG5 " " " 4H 5H 6H 7H ADDREG9 " " " 4H 5H 6H 7H 8H 9H AH BH ADDREG2 " " " 8H 9H AH BH ADDREG6 " " " 8H 9H AH BH ADDREGA " " " 8H 9H AH BH CH DH EH FH ADDREG3 " " " CH DH EH FH ADDREG7 " " " CH DH EH FH ADDREGB " " " CH DH EH FH [2] FLASH control [3] Protect control ADR Register name ADR Register name ADR Register name ADR Register name FF000100H 1H 2H 3H FLCS " " " FF000200H 1H 2H 3H SECBIT " " " FF000210H 1H 2H 3H FF000220H 1H 2H 3H 4H 5H 6H 7H Reserved " " " 4H 5H 6H 7H DSUSECBIT " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH Reserved " " " 8H 9H AH BH SECCODE " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH Reserved " " " CH DH EH FH DSUSECCODE CH DH EH FH CH DH EH FH " " " [4] Interrupt controller ADR Register name ADR Register name ADR Register name ADR Register name FF001000H 1H 2H 3H IMC0 " " " FF001010H 1H 2H 3H IMC4 " " " FF001020H 1H 2H 3H IMC8 " " " FF001030H 1H 2H 3H IMCC " " " 4H 5H 6H 7H IMC1 " " " 4H 5H 6H 7H IMC5 " " " 4H 5H 6H 7H IMC9 " " " 4H 5H 6H 7H IMCD " " " 8H 9H AH BH IMC2 " " " 8H 9H AH BH IMC6 " " " 8H 9H AH BH IMCA " " " 8H 9H AH BH IMCE " " " CH DH EH FH IMC3 " " " CH DH EH FH IMC7 " " " CH DH EH FH IMCB " " " CH DH EH FH IMCF " " " Table of Special Function Registers TMP19A44(rev1.3)22-2 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF001040H 1H 2H 3H IMC10 " " " FF001050H 1H 2H 3H IMC14 " " " FF001060H 1H 2H 3H IMC18 " " " FF001070H 1H 2H 3H Reservd " " " 4H 5H 6H 7H IMC11 " " " 4H 5H 6H 7H IMC15 " " " 4H 5H 6H 7H IMC19 " " " 4H 5H 6H 7H Reservd " " " 8H 9H AH BH IMC12 " " " 8H 9H AH BH IMC16 " " " 8H 9H AH BH Reservd " " " 8H 9H AH BH Reservd " " " CH DH EH FH IMC13 " " " CH DH EH FH IMC17 " " " CH DH EH FH Reservd " " " CH DH EH FH Reservd " " " ADR Register name ADR FF001080H 1H 2H 3H IVR " " " FF001090H 1H 2H 3H FF0010A0H 1H 2H 3H FF0010B0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ADR Register name FF0010C0H 1H 2H 3H ADR Register name ADR Register name ADR Register name ADR Register name ADR Register name FF0010D0H 1H 2H 3H FF0010E0H 1H 2H 3H FF0010F0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH 4H 5H 6H 7H INTCLR " " " Register name DREQFLG " " " Table of Special Function Registers TMP19A44(rev1.3)22-3 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF001100H 1H 2H 3H FF001110H 1H 2H 3H FF001120H 1H 2H 3H FF001130H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ILEV " " " [5] DMA controller ADR Register name ADR Register name ADR Register name ADR Register name FF001200H 1H 2H 3H CCR0 " " " FF001210H 1H 2H 3H BCR0 " " " FF001220H 1H 2H 3H CCR1 " " " FF001230H 1H 2H 3H BCR1 " " " 4H 5H 6H 7H CSR0 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR1 " " " 4H 5H 6H 7H 8H 9H AH BH SAR0 " " " 8H 9H AH BH 8H 9H AH BH SAR1 " " " 8H 9H AH BH CH DH EH FH DAR0 " " " CH DH EH FH CH DH EH FH DAR1 " " " CH DH EH FH DTCR0 " " " DTCR1 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF001240H 1H 2H 3H CCR2 " " " FF001250H 1H 2H 3H BCR2 " " " FF001260H 1H 2H 3H CCR3 " " " FF001270H 1H 2H 3H BCR3 " " " 4H 5H 6H 7H CSR2 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR3 " " " 4H 5H 6H 7H 8H 9H AH BH SAR2 " " " 8H 9H AH BH 8H 9H AH BH SAR3 " " " 8H 9H AH BH CH DH EH FH DAR2 " " " CH DH EH FH CH DH EH FH DAR3 " " " CH DH EH FH Table of Special Function Registers DTCR2 " " " TMP19A44(rev1.3)22-4 DTCR3 " " " 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF001280H 1H 2H 3H CCR4 " " " FF001290H 1H 2H 3H BCR4 " " " FF0012A0H 1H 2H 3H CCR5 " " " FF0012B0H 1H 2H 3H BCR5 " " " 4H 5H 6H 7H CSR4 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR5 " " " 4H 5H 6H 7H 8H 9H AH BH SAR4 " " " 8H 9H AH BH 8H 9H AH BH SAR5 " " " 8H 9H AH BH CH DH EH FH DAR4 " " " CH DH EH FH CH DH EH FH DAR5 " " " CH DH EH FH DTCR4 " " " DTCR5 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF0012C0H 1H 2H 3H CCR6 " " " FF0012D0H 1H 2H 3H BCR6 " " " FF0012E0H 1H 2H 3H CCR7 " " " FF0012F0H 1H 2H 3H BCR7 " " " 4H 5H 6H 7H CSR6 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR7 " " " 4H 5H 6H 7H 8H 9H AH BH SAR6 " " " 8H 9H AH BH 8H 9H AH BH SAR7 " " " 8H 9H AH BH CH DH EH FH DAR6 " " " CH DH EH FH CH DH EH FH DAR7 " " " CH DH EH FH DTCR6 " " " DTCR7 " " " [6] Chip select/wait controller ADR Register name ADR Register name ADR FF001300H 1H 2H 3H DCR " " " FF001400H 1H 2H 3H BMA0 " " " FF001410H 1H 2H 3H FF001420H 1H 2H 3H 4H 5H 6H 7H RSR " " " 4H 5H 6H 7H BMA1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH BMA2 " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH BMA3 " " " CH DH EH FH CH DH EH FH 8H 9H AH BH CH DH EH FH DHR " " " Table of Special Function Registers Register name TMP19A44(rev1.3)22-5 ADR Register name 2010-04-01 TMP19A44 [7] Real time clock ADR Register name ADR Register name ADR FF001480H 1H 2H 3H B01CS " " " FF001500H 1H 2H 3H SECR MINR HOURR " FF001510H 1H 2H 3H FF001520H 1H 2H 3H 4H 5H 6H 7H B23CS " " " 4H 5H 6H 7H DAYR DATER MONTHR YEARR 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PAGER " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH RESTR " " " CH DH EH FH CH DH EH FH 8H 9H AH BH CH DH EH FH BUSCR " " " Register name ADR Register name [8] Two-phase pulse input counter ADR Register name ADR Register name ADR Register name ADR Register name FF001600H 1H 2H 3H PHC0RUN " " " FF001610H 1H 2H 3H PHC0CMP0 " " " FF001620H 1H 2H 3H Reserved FF001630H 1H 2H 3H 4H 5H 6H 7H PHC0CR " " " 4H 5H 6H 7H PHC0CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC0EN " " " 8H 9H AH BH PHC0CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC0FLG " " " CH DH EH FH Reservd " " " CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF001640H 1H 2H 3H PHC1RUN " " " FF001650H 1H 2H 3H PHC1CMP0 " " " FF001660H 1H 2H 3H Reservd " " " FF001670H 1H 2H 3H 4H 5H 6H 7H PHC1CR " " " 4H 5H 6H 7H PHC1CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC1EN " " " 8H 9H AH BH PHC1CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC1FLG " " " CH DH EH FH Reservd " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-6 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF001680H 1H 2H 3H PHC2RUN " " " FF001690H 1H 2H 3H PHC2CMP0 " " " FF0016A0H 1H 2H 3H Reservd " " " FF0016B0H 1H 2H 3H 4H 5H 6H 7H PHC2CR " " " 4H 5H 6H 7H PHC2CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC2EN " " " 8H 9H AH BH PHC2CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC2FLG " " " CH DH EH FH Reservd " " " CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0016C0H 1H 2H 3H PHC3RUN " " " FF0016D0H 1H 2H 3H PHC3CMP0 " " " FF0016E0H 1H 2H 3H Reservd " " " FF0016F0H 1H 2H 3H 4H 5H 6H 7H PHC3CR " " " 4H 5H 6H 7H PHC3CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC3EN " " " 8H 9H AH BH PHC3CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC3FLG " " " CH DH EH FH Reservd " " " CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF001700H 1H 2H 3H PHC4RUN " " " FF001710H 1H 2H 3H PHC4CMP0 " " " FF001720H 1H 2H 3H Reservd " " " FF001730H 1H 2H 3H 4H 5H 6H 7H PHC4CR " " " 4H 5H 6H 7H PHC4CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC4EN " " " 8H 9H AH BH PHC4CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC4FLG " " " CH DH EH FH Reservd " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-7 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF001740H 1H 2H 3H PHC5RUN " " " FF001750H 1H 2H 3H PHC5CMP0 " " " FF001760H 1H 2H 3H Reservd " " " FF001770H 1H 2H 3H 4H 5H 6H 7H PHC5CR " " " 4H 5H 6H 7H PHC5CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC5EN " " " 8H 9H AH BH PHC5CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC5FLG " " " CH DH EH FH Reservd " " " CH DH EH FH CH DH EH FH [9] High speed serial channel ADR Register name FF001800H 1H 2H 3H HSC0BUF ADR Register name FF001810H 1H 2H 3H HSC1BUF ADR Register name FF001820H 1H 2H 3H HSC2BUF ADR Register name FF001830H 1H 2H 3H 4H 5H 6H 7H HBR0ADD HSC0MOD1 HSC0MOD2 HSC0EN 4H 5H 6H 7H HBR1ADD HSC1MOD1 HSC1MOD2 HSC1EN 4H 5H 6H 7H HBR2ADD HSC2MOD1 HSC2MOD2 HSC2EN 4H 5H 6H 7H 8H 9H AH BH HSC0RFC HSC0TFC HSC0RST HSC0TST 8H 9H AH BH HSC1RFC HSC1TFC HSC1RST HSC1TST 8H 9H AH BH HSC2RFC HSC2TFC HSC2RST HSC2TST 8H 9H AH BH CH DH EH FH HSC0FCNF HSC0CR HSC0MOD0 HBR0CR CH DH EH FH HSC1FCNF HSC1CR HSC1MOD0 HBR1CR CH DH EH FH HSC2FCNF HSC2CR HSC2MOD0 HBR2CR CH DH EH FH [10] Clock generator ADR Register name ADR Register name ADR FF001900H 1H 2H 3H SYSCR " " " FF001910H 1H 2H 3H SCKSEL " " " FF001920H 1H 2H 3H IMCGA " " " FF001930H 1H 2H 3H IMCGE " " " 4H 5H 6H 7H OSCCR " " " 4H 5H 6H 7H ICRCG " " " 4H 5H 6H 7H IMCGB " " " 4H 5H 6H 7H IMCGF " " " 8H 9H AH BH STBYCR " " " 8H 9H AH BH NMIFLG " " " 8H 9H AH BH IMCGC " " " 8H 9H AH BH IMCG10 " " " CH DH EH FH PLLSEL " " " CH DH EH FH RSTFLG " " " CH DH EH FH IMCGD " " " CH DH EH FH IMCG11 " " " Table of Special Function Registers Register name TMP19A44(rev1.3)22-8 ADR Register name 2010-04-01 TMP19A44 [11] Key-on wake-up ADR Register name ADR Register name ADR Register name ADR Register name FF001A00H 1H 2H 3H KWUPST00 " " " FF001A10H 1H 2H 3H KWUPST04 " " " FF001A20H 1H 2H 3H KWUPST08 " " " FF001A30H 1H 2H 3H KWUPST12 " " " 4H 5H 6H 7H KWUPST01 " " " 4H 5H 6H 7H KWUPST05 " " " 4H 5H 6H 7H KWUPST09 " " " 4H 5H 6H 7H KWUPST13 " " " 8H 9H AH BH KWUPST02 " " " 8H 9H AH BH KWUPST06 " " " 8H 9H AH BH KWUPST10 " " " 8H 9H AH BH KWUPST14 " " " CH DH EH FH KWUPST03 " " " CH DH EH FH KWUPST07 " " " CH DH EH FH KWUPST11 " " " CH DH EH FH KWUPST15 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF001A40H 1H 2H 3H KWUPST 16 " " " FF001A50H 1H 2H 3H KWUPST 20 " " " FF001A60H 1H 2H 3H KWUPST 24 " " " FF001A70H 1H 2H 3H KWUPST 28 " " " 4H 5H 6H 7H KWUPST 17 " " " 4H 5H 6H 7H KWUPST 21 " " " 4H 5H 6H 7H KWUPST 25 " " " 4H 5H 6H 7H KWUPST 29 " " " 8H 9H AH BH KWUPST 18 " " " 8H 9H AH BH KWUPST 22 " " " 8H 9H AH BH KWUPST 26 " " " 8H 9H AH BH KWUPST 30 " " " CH DH EH FH KWUPST 19 " " " CH DH EH FH KWUPST 23 " " " CH DH EH FH KWUPST 27 " " " CH DH EH FH KWUPST 31 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF001A80H 1H 2H 3H PKEY " " " FF001A90H 1H 2H 3H FF001AA0H 1H 2H 3H FF001AB0H 1H 2H 3H 4H 5H 6H 7H KWUPCNT " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH KWUPCLR " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH KWUPINT " " " CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-9 2010-04-01 TMP19A44 [12] Port registers ADR Register name ADR Register name ADR Register name ADR Register name FF004000H 1H 2H 3H P0 " " " FF004010H 1H 2H 3H FF004020H 1H 2H 3H FF004030H 1H 2H 3H 4H 5H 6H 7H P0CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P0FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH Register name ADR P0PUP " " " Register name CH DH EH FH ADR Register name ADR ADR Register name FF004040H 1H 2H 3H P1 " " " FF004050H 1H 2H 3H FF004060H 1H 2H 3H FF004070H 1H 2H 3H 4H 5H 6H 7H P1CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P1FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P1FC2 " " " CH DH EH FH CH DH EH FH P1PUP " " " Register name CH DH EH FH ADR Register name ADR Register name ADR ADR Register name FF004080H 1H 2H 3H P2 " " " FF004090H 1H 2H 3H P2FC3 " " " FF0040A0H 1H 2H 3H FF0040B0H 1H 2H 3H 4H 5H 6H 7H P2CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P2FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P2FC2 " " " CH DH EH FH CH DH EH FH Table of Special Function Registers P2PUP " " " TMP19A44(rev1.3)22-10 P2IE " " " CH DH EH FH 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF0040C0H 1H 2H 3H P3 " " " FF0040D0H 1H 2H 3H FF0040E0H 1H 2H 3H FF0040F0H 1H 2H 3H 4H 5H 6H 7H P3CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P3FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P3FC2 " " " CH DH EH FH CH DH EH FH Register name ADR P3PUP " " " Register name CH DH EH FH ADR Register name ADR FF004100H 1H 2H 3H P4 " " " FF004110H 1H 2H 3H FF004120H 1H 2H 3H FF004130H 1H 2H 3H ADR Register name 4H 5H 6H 7H P4CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P4FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P4FC2 " " " CH DH EH FH CH DH EH FH P4PUP " " " Register name Register name ADR Register name ADR FF004140H 1H 2H 3H P5 " " " FF004150H 1H 2H 3H P5FC3 " " " FF004160H 1H 2H 3H FF004170H 1H 2H 3H ADR Register name 4H 5H 6H 7H P5CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P5FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P5FC2 " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-11 P4IE " " " CH DH EH FH ADR P5PUP " " " P3IE " " " P5IE " " " CH DH EH FH 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004180H 1H 2H 3H P6 " " " FF004190H 1H 2H 3H P6FC3 " " " FF0041A0H 1H 2H 3H FF0041B0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H P6CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P6FC1 " " " 8H 9H AH BH 8H 9H AH BH P6ODE " " " 8H 9H AH BH CH DH EH FH P6FC2 " " " CH DH EH FH CH DH EH FH P6PUP " " " CH DH EH FH ADR Register name ADR FF0041C0H 1H 2H 3H P7 " " " FF0041D0H 1H 2H 3H FF0041E0H 1H 2H 3H FF0041F0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH P7FC2 " " " Register name Register name P7PUP " " " FF004200H 1H 2H 3H P8 " " " FF004210H 1H 2H 3H FF004220H 1H 2H 3H FF004230H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH P8PUP " " " TMP19A44(rev1.3)22-12 P7IE " " " CH DH EH FH ADR Table of Special Function Registers Register name Register name Register name P8FC2 " " " ADR ADR ADR CH DH EH FH Register name ADR P6IE " " " ADR Register name P8IE " " " CH DH EH FH 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004240H 1H 2H 3H P9 " " " FF004250H 1H 2H 3H FF004260H 1H 2H 3H FF004270H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H P9CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P9FC1 " " " 8H 9H AH BH 8H 9H AH BH P9ODE " " " 8H 9H AH BH CH DH EH FH P9FC2 " " " CH DH EH FH CH DH EH FH P9PUP " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR FF004280H 1H 2H 3H PA " " " FF004290H 1H 2H 3H Reserved " " " FF0042A0H 1H 2H 3H FF0042B0H 1H 2H 3H Register name 4H 5H 6H 7H PACR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PAFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH PAFC2 " " " CH DH EH FH CH DH EH FH PAPUP " " " Register name Register name ADR Register name ADR FF0042C0H 1H 2H 3H PB " " " FF0042D0H 1H 2H 3H Reserved " " " FF0042E0H 1H 2H 3H FF0042F0H 1H 2H 3H ADR Register name 4H 5H 6H 7H 4H 5H 6H 7H PBCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PBFC1 " " " 8H 9H AH BH 8H 9H AH BH PBODE " " " 8H 9H AH BH CH DH EH FH PBFC2 " " " CH DH EH FH CH DH EH FH PBPUP " " " CH DH EH FH TMP19A44(rev1.3)22-13 PAIE " " " CH DH EH FH ADR Table of Special Function Registers P9IE " " " PBIE " " " 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004300H 1H 2H 3H PC " " " FF004310H 1H 2H 3H Reserved " " " FF004320H 1H 2H 3H FF004330H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H PCCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PCFC1 " " " 8H 9H AH BH 8H 9H AH BH PCODE " " " 8H 9H AH BH CH DH EH FH PCFC2 " " " CH DH EH FH CH DH EH FH PCPUP " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR FF004340H 1H 2H 3H PD " " " FF004350H 1H 2H 3H Reserved " " " FF004360H 1H 2H 3H FF004370H 1H 2H 3H 4H 5H 6H 7H Register name 4H 5H 6H 7H PDCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PDFC1 " " " 8H 9H AH BH 8H 9H AH BH PDODE " " " 8H 9H AH BH CH DH EH FH PDFC2 " " " CH DH EH FH CH DH EH FH PDPUP " " " CH DH EH FH Register name ADR Register name ADR Register name ADR FF004380H 1H 2H 3H PE " " " FF004390H 1H 2H 3H Reserved " " " FF0043A0H 1H 2H 3H FF0043B0H 1H 2H 3H ADR PECR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PEFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH Table of Special Function Registers PEPUP " " " TMP19A44(rev1.3)22-14 PDIE " " " Register name 4H 5H 6H 7H CH DH EH FH PCIE " " " PEIE " " " CH DH EH FH 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF0043C0H 1H 2H 3H PF " " " FF0043D0H 1H 2H 3H Reserved " " " FF0043E0H 1H 2H 3H FF0043F0H 1H 2H 3H 4H 5H 6H 7H PFCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PFFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH PFFC2 " " " CH DH EH FH CH DH EH FH PFPUP " " " Register name CH DH EH FH ADR Register name ADR Register name ADR FF004400H 1H 2H 3H PG " " " FF004410H 1H 2H 3H Reserved " " " FF004420H 1H 2H 3H FF004430H 1H 2H 3H ADR Register name 4H 5H 6H 7H PGCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PGFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH PGPUP " " " Register name Register name ADR Register name ADR FF004440H 1H 2H 3H PH " " " FF004450H 1H 2H 3H Reserved " " " FF004460H 1H 2H 3H FF004470H 1H 2H 3H ADR Register name 4H 5H 6H 7H PHCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHFC2 " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-15 PGIE " " " CH DH EH FH ADR PHPUP " " " PFIE " " " PHIE " " " CH DH EH FH 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004480H 1H 2H 3H PI " " " FF004490H 1H 2H 3H Reserved " " " FF0044A0H 1H 2H 3H FF0044B0H 1H 2H 3H 4H 5H 6H 7H PICR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PIFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH Register name ADR PIPUP " " " Register name CH DH EH FH ADR Register name ADR FF0044C0H 1H 2H 3H PJ " " " FF0044D0H 1H 2H 3H FF0044E0H 1H 2H 3H FF0044F0H 1H 2H 3H ADR Register name 4H 5H 6H 7H PJCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PJFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH PIIE " " " PJPUP " " " PJIE " " " CH DH EH FH [13] 16-bit timer ADR Register name ADR Register name ADR Register name ADR Register name FF004500H 1H 2H 3H TB0EN " " " FF004510H 1H 2H 3H TB0FFCR " " " FF004520H 1H 2H 3H TB0RG0 " " " FF004530H 1H 2H 3H 4H 5H 6H 7H TB0RUN " " " 4H 5H 6H 7H TB0ST " " " 4H 5H 6H 7H TB0RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB0CR " " " 8H 9H AH BH TB0IM " " " 8H 9H AH BH TB0CP0 " " " 8H 9H AH BH CH DH EH FH TB0MOD " " " CH DH EH FH TM0UC " " " CH DH EH FH TB0CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-16 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004540H 1H 2H 3H TB1EN " " " FF004550H 1H 2H 3H TB1FFCR " " " FF004560H 1H 2H 3H TB1RG0 " " " FF004570H 1H 2H 3H 4H 5H 6H 7H TB1RUN " " " 4H 5H 6H 7H TB1ST " " " 4H 5H 6H 7H TB1RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB1CR " " " 8H 9H AH BH TB1IM " " " 8H 9H AH BH TB1CP0 " " " 8H 9H AH BH CH DH EH FH TB1MOD " " " CH DH EH FH TM1UC " " " CH DH EH FH TB1CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004580H 1H 2H 3H TB2EN " " " FF004590H 1H 2H 3H TB2FFCR " " " FF0045A0H 1H 2H 3H TB2RG0 " " " FF0045B0H 1H 2H 3H 4H 5H 6H 7H TB2RUN " " " 4H 5H 6H 7H TB2ST " " " 4H 5H 6H 7H TB2RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB2CR " " " 8H 9H AH BH TB2IM " " " 8H 9H AH BH TB2CP0 " " " 8H 9H AH BH CH DH EH FH TB2MOD " " " CH DH EH FH TM2UC " " " CH DH EH FH TB2CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0045C0H 1H 2H 3H TB3EN " " " FF0045D0H 1H 2H 3H TB3FFCR " " " FF0045E0H 1H 2H 3H TB3RG0 " " " FF0045F0H 1H 2H 3H 4H 5H 6H 7H TB3RUN " " " 4H 5H 6H 7H TB3ST " " " 4H 5H 6H 7H TB3RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB3CR " " " 8H 9H AH BH TB3IM " " " 8H 9H AH BH TB3CP0 " " " 8H 9H AH BH CH DH EH FH TB3MOD " " " CH DH EH FH TM3UC " " " CH DH EH FH TB3CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-17 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004600H 1H 2H 3H TB4EN " " " FF004610H 1H 2H 3H TB4FFCR " " " FF004620H 1H 2H 3H TB4RG0 " " " FF004630H 1H 2H 3H 4H 5H 6H 7H TB4RUN " " " 4H 5H 6H 7H TB4ST " " " 4H 5H 6H 7H TB4RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB4CR " " " 8H 9H AH BH TB4IM " " " 8H 9H AH BH TB4CP0 " " " 8H 9H AH BH CH DH EH FH TB4MOD " " " CH DH EH FH TM4UC " " " CH DH EH FH TB4CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004640H 1H 2H 3H TB5EN " " " FF004650H 1H 2H 3H TB5FFCR " " " FF004660H 1H 2H 3H TB5RG0 " " " FF004670H 1H 2H 3H 4H 5H 6H 7H TB5RUN " " " 4H 5H 6H 7H TB5ST " " " 4H 5H 6H 7H TB5RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB5CR " " " 8H 9H AH BH TB5IM " " " 8H 9H AH BH TB5CP0 " " " 8H 9H AH BH CH DH EH FH TB5MOD " " " CH DH EH FH TM5UC " " " CH DH EH FH TB5CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004680H 1H 2H 3H TB6EN " " " FF004690H 1H 2H 3H TB6FFCR " " " FF0046A0H 1H 2H 3H TB6RG0 " " " FF0046B0H 1H 2H 3H 4H 5H 6H 7H TB6RUN " " " 4H 5H 6H 7H TB6ST " " " 4H 5H 6H 7H TB6RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB6CR " " " 8H 9H AH BH TB6IM " " " 8H 9H AH BH TB6CP0 " " " 8H 9H AH BH CH DH EH FH TB6MOD " " " CH DH EH FH TM6UC " " " CH DH EH FH TB6CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-18 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF0046C0H 1H 2H 3H TB7EN " " " FF0046D0H 1H 2H 3H TB7FFCR " " " FF0046E0H 1H 2H 3H TB7RG0 " " " FF0046F0H 1H 2H 3H 4H 5H 6H 7H TB7RUN " " " 4H 5H 6H 7H TB7ST " " " 4H 5H 6H 7H TB7RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB7CR " " " 8H 9H AH BH TB7IM " " " 8H 9H AH BH TB7CP0 " " " 8H 9H AH BH CH DH EH FH TB7MOD " " " CH DH EH FH TM7UC " " " CH DH EH FH TB7CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004700H 1H 2H 3H TB8EN " " " FF004710H 1H 2H 3H TB8FFCR " " " FF004720H 1H 2H 3H TB8RG0 " " " FF004730H 1H 2H 3H 4H 5H 6H 7H TB8RUN " " " 4H 5H 6H 7H TB8ST " " " 4H 5H 6H 7H TB8RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB8CR " " " 8H 9H AH BH TB8IM " " " 8H 9H AH BH TB8CP0 " " " 8H 9H AH BH CH DH EH FH TB8MOD " " " CH DH EH FH TM8UC " " " CH DH EH FH TB8CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004740H 1H 2H 3H TB9EN " " " FF004785H 1H 2H 3H TB9FFCR " " " FF004760H 1H 2H 3H TB9RG0 " " " FF004770H 1H 2H 3H 4H 5H 6H 7H TB9RUN " " " 4H 5H 6H 7H TB9ST " " " 4H 5H 6H 7H TB9RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB9CR " " " 8H 9H AH BH TB9IM " " " 8H 9H AH BH TB9CP0 " " " 8H 9H AH BH CH DH EH FH TB9MOD " " " CH DH EH FH TM9UC " " " CH DH EH FH TB9CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-19 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004780H 1H 2H 3H TBAEN " " " FF004790H 1H 2H 3H TBAFFCR " " " FF0047A0H 1H 2H 3H TBARG0 " " " FF0047B0H 1H 2H 3H 4H 5H 6H 7H TBARUN " " " 4H 5H 6H 7H TBAST " " " 4H 5H 6H 7H TBARG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBACR " " " 8H 9H AH BH TBAIM " " " 8H 9H AH BH TBACP0 " " " 8H 9H AH BH CH DH EH FH TBAMOD " " " CH DH EH FH TMAUC " " " CH DH EH FH TBACP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0047C0H 1H 2H 3H TBBEN " " " FF0047D0H 1H 2H 3H TBBFFCR " " " FF0047E0H 1H 2H 3H TBBRG0 " " " FF0047F0H 1H 2H 3H 4H 5H 6H 7H TBBRUN " " " 4H 5H 6H 7H TBBST " " " 4H 5H 6H 7H TBBRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBBCR " " " 8H 9H AH BH TBBIM " " " 8H 9H AH BH TBBCP0 " " " 8H 9H AH BH CH DH EH FH TBBMOD " " " CH DH EH FH TMBUC " " " CH DH EH FH TBBCP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004800H 1H 2H 3H TBCEN " " " FF004810H 1H 2H 3H TBCFFCR " " " FF004820H 1H 2H 3H TBCRG0 " " " FF004830H 1H 2H 3H 4H 5H 6H 7H TBCRUN " " " 4H 5H 6H 7H TBCST " " " 4H 5H 6H 7H TBCRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBCCR " " " 8H 9H AH BH TBCIM " " " 8H 9H AH BH TBCCP0 " " " 8H 9H AH BH CH DH EH FH TBCMOD " " " CH DH EH FH TMCUC " " " CH DH EH FH TBCCP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-20 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004840H 1H 2H 3H TBDEN " " " FF004850H 1H 2H 3H TBDFFCR " " " FF004860H 1H 2H 3H TBDRG0 " " " FF004870H 1H 2H 3H 4H 5H 6H 7H TBDRUN " " " 4H 5H 6H 7H TBDST " " " 4H 5H 6H 7H TBDRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBDCR " " " 8H 9H AH BH TBDIM " " " 8H 9H AH BH TBDCP0 " " " 8H 9H AH BH CH DH EH FH TBDMOD " " " CH DH EH FH TMDUC " " " CH DH EH FH TBDCP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004880H 1H 2H 3H TBEEN " " " FF004890H 1H 2H 3H TBEFFCR " " " FF0048A0H 1H 2H 3H TBERG0 " " " FF0048B0H 1H 2H 3H 4H 5H 6H 7H TBERUN " " " 4H 5H 6H 7H TBEST " " " 4H 5H 6H 7H TBERG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBECR " " " 8H 9H AH BH TBEIM " " " 8H 9H AH BH TBECP0 " " " 8H 9H AH BH CH DH EH FH TBEMOD " " " CH DH EH FH TMEUC " " " CH DH EH FH TBECP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0048C0H 1H 2H 3H TBFEN " " " FF0048D0H 1H 2H 3H TBFFFCR " " " FF0048E0H 1H 2H 3H TBFRG0 " " " FF0048F0H 1H 2H 3H 4H 5H 6H 7H TBFRUN " " " 4H 5H 6H 7H TBFST " " " 4H 5H 6H 7H TBFRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBFCR " " " 8H 9H AH BH TBFIM " " " 8H 9H AH BH TBFCP0 " " " 8H 9H AH BH CH DH EH FH TBFMOD " " " CH DH EH FH TMFUC " " " CH DH EH FH TBFCP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-21 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004900H 1H 2H 3H TB10EN " " " FF004910H 1H 2H 3H TB10FFCR " " " FF004920H 1H 2H 3H TB10RG0 " " " FF004930H 1H 2H 3H 4H 5H 6H 7H TB10RUN " " " 4H 5H 6H 7H TB10ST " " " 4H 5H 6H 7H TB10RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB10CR " " " 8H 9H AH BH TB10IM " " " 8H 9H AH BH TB10CP0 " " " 8H 9H AH BH CH DH EH FH TB10MOD " " " CH DH EH FH TM10UC " " " CH DH EH FH TB10CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004940H 1H 2H 3H TB11EN " " " FF004950H 1H 2H 3H TB11FFCR " " " FF004960H 1H 2H 3H TB11RG0 " " " FF004970H 1H 2H 3H 4H 5H 6H 7H TB11RUN " " " 4H 5H 6H 7H TB11ST " " " 4H 5H 6H 7H TB11RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB11CR " " " 8H 9H AH BH TB11IM " " " 8H 9H AH BH TB11CP0 " " " 8H 9H AH BH CH DH EH FH TB11MOD " " " CH DH EH FH TM11UC " " " CH DH EH FH TB11CP1 " " " CH DH EH FH [14] 32-bit timer ADR Register name ADR Register name ADR Register name ADR Register name FF004A00H 1H 2H 3H TCEN " " " FF004A10H 1H 2H 3H TBTRDCAP " " " FF004A20H 1H 2H 3H CMPCTL0 " " " FF004A30H 1H 2H 3H CMPCTL1 " " " TCCMP0 " " " 4H 5H 6H 7H TCCMP1 " " " 4H 5H 6H 7H TBTRUN " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH TBTCR " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH TBTCAP " " " CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-22 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004A40H 1H 2H 3H CMPCTL2 " " " FF004A50H 1H 2H 3H CMPCTL3 " " " FF004A60H 1H 2H 3H CMPCTL4 " " " FF004A70H 1H 2H 3H CMPCTL5 " " " 4H 5H 6H 7H TCCMP2 " " " 4H 5H 6H 7H TCCMP3 " " " 4H 5H 6H 7H TCCMP4 " " " 4H 5H 6H 7H TCCMP5 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004A80H 1H 2H 3H CMPCTL6 " " " FF004A90H 1H 2H 3H CMPCTL7 " " " FF004AA0H 1H 2H 3H CAPCR0 " " " FF004AB0H 1H 2H 3H CAPCR1 " " " 4H 5H 6H 7H TCCMP6 " " " 4H 5H 6H 7H TCCMP7 " " " 4H 5H 6H 7H TCCAP0 " " " 4H 5H 6H 7H TCCAP1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004AC0H 1H 2H 3H CAPCR2 " " " FF004AD0H 1H 2H 3H CAPCR3 " " " FF004AE0H 1H 2H 3H FF004AF0H 1H 2H 3H 4H 5H 6H 7H TCCAP2 " " " 4H 5H 6H 7H TCCAP3 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-23 2010-04-01 TMP19A44 [15] I2CBUS/serial channel ADR Register name ADR Register name ADR FF004B00H 1H 2H 3H SBICR0 " " " FF004B10H 1H 2H 3H SBICR2/SBISR FF004B20H 1H 2H 3H FF004B30H 1H 2H 3H 4H 5H 6H 7H SBICR1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH SBIDBR " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH I2CAR " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " SBIBR " " " Register name ADR Register name [16] UART/serial channel ADR Register name ADR Register name ADR Register name ADR Register name FF004C00H 1H 2H 3H SC0EN " " " FF004C10H 1H 2H 3H BR0CR " " " FF004C20H 1H 2H 3H SC0RFC " " " FF004C30H 1H 2H 3H SC0FCNF " " " 4H 5H 6H 7H SC0BUF " " " 4H 5H 6H 7H BR0ADD " " " 4H 5H 6H 7H SC0TFC " " " 4H 5H 6H 7H 8H 9H AH BH SC0CR " " " 8H 9H AH BH SC0MOD1 " " " 8H 9H AH BH SC0RST " " " 8H 9H AH BH CH DH EH FH SC0MOD0 " " " CH DH EH FH SC0MOD2 " " " CH DH EH FH SC0TST " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004C40H 1H 2H 3H SC1EN " " " FF004C50H 1H 2H 3H BR1CR " " " FF004C60H 1H 2H 3H SC1RFC " " " FF004C70H 1H 2H 3H SC1FCNF " " " 4H 5H 6H 7H SC1BUF " " " 4H 5H 6H 7H BR1ADD " " " 4H 5H 6H 7H SC1TFC " " " 4H 5H 6H 7H 8H 9H AH BH SC1CR " " " 8H 9H AH BH SC1MOD1 " " " 8H 9H AH BH SC1RST " " " 8H 9H AH BH CH DH EH FH SC1MOD0 " " " CH DH EH FH SC1MOD2 " " " CH DH EH FH SC1TST " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-24 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004C80H 1H 2H 3H SC2EN " " " FF004C90H 1H 2H 3H BR2CR " " " FF004CA0H 1H 2H 3H SC2RFC " " " FF004CB0H 1H 2H 3H SC2FCNF " " " 4H 5H 6H 7H SC2BUF " " " 4H 5H 6H 7H BR2ADD " " " 4H 5H 6H 7H SC2TFC " " " 4H 5H 6H 7H 8H 9H AH BH SC2CR " " " 8H 9H AH BH SC2MOD1 " " " 8H 9H AH BH SC2RST " " " 8H 9H AH BH CH DH EH FH SC2MOD0 " " " CH DH EH FH SC2MOD2 " " " CH DH EH FH SC2TST " " " CH DH EH FH [17] 10-bit A/D converter ADR Register name ADR Register name ADR Register name ADR Register name FF004D00H 1H 2H 3H ADACLK " " " FF004D10H 1H 2H 3H ADAMOD3 " " " FF004D20H 1H 2H 3H reserved " " " FF004D30H 1H 2H 3H ADAREG0 " " " 4H 5H 6H 7H ADAMOD0 " " " 4H 5H 6H 7H ADAMOD4 " " " 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADAREG1 " " " 8H 9H AH BH ADAMOD1 " " " 8H 9H AH BH ADAMOD5 " " " 8H 9H AH BH reserved " " " 8H 9H AH BH ADAREG2 " " " CH DH EH FH ADAMOD2 " " " CH DH EH FH CH DH EH FH ADAREG3 " " " CH DH EH FH ADR Register name ADR Register name ADR FF004D40H 1H 2H 3H reserved " " " FF004D50H 1H 2H 3H ADAREGSP " " " FF004D60H 1H 2H 3H FF004D70H 1H 2H 3H 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADACOMREG0 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH reserved " " " 8H 9H AH BH ADACOMREG1 8H 9H AH BH 8H 9H AH BH CH DH EH FH reserved " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " Table of Special Function Registers " " " Register name TMP19A44(rev1.3)22-25 ADR Register name 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR Register name ADR Register name FF004D80H 1H 2H 3H ADBCLK " " " FF004D90H 1H 2H 3H ADBMOD3 " " " FF004DA0H 1H 2H 3H reserved " " " FF004DB0H 1H 2H 3H ADBREG0 " " " 4H 5H 6H 7H ADBMOD0 " " " 4H 5H 6H 7H ADBMOD4 " " " 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADBREG1 " " " 8H 9H AH BH ADBMOD1 " " " 8H 9H AH BH ADBMOD5 " " " 8H 9H AH BH reserved " " " 8H 9H AH BH ADBREG2 " " " CH DH EH FH ADBMOD2 " " " CH DH EH FH CH DH EH FH ADBREG3 " " " CH DH EH FH ADR Register name ADR Register name ADR FF004DC0H 1H 2H 3H reserved " " " FF004DD0H 1H 2H 3H ADBREGSP " " " FF004DE0H 1H 2H 3H FF004DF0H 1H 2H 3H 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADBCOMREG0 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH reserved " " " 8H 9H AH BH ADBCOMREG1 8H 9H AH BH 8H 9H AH BH CH DH EH FH reserved " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " " " " Register name ADR Register name ADR Register name ADR Register name ADR Register name ADR Register name FF004E00H 1H 2H 3H ADCCLK " " " FF004E10H 1H 2H 3H ADCMOD3 " " " FF004E20H 1H 2H 3H reserved " " " FF004E30H 1H 2H 3H ADCREG0 " " " 4H 5H 6H 7H ADCMOD0 " " " 4H 5H 6H 7H ADCMOD4 " " " 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADCREG1 " " " 8H 9H AH BH ADCMOD1 " " " 8H 9H AH BH ADCMOD5 " " " 8H 9H AH BH reserved " " " 8H 9H AH BH ADCREG2 " " " CH DH EH FH ADCMOD2 " " " CH DH EH FH CH DH EH FH ADCREG3 " " " Table of Special Function Registers CH DH EH FH TMP19A44(rev1.3)22-26 2010-04-01 TMP19A44 ADR Register name ADR Register name ADR FF004E40H 1H 2H 3H ADCREG4 " " " FF004E50H 1H 2H 3H ADREGSP " " " FF004E60H 1H 2H 3H FF004E70H 1H 2H 3H 4H 5H 6H 7H ADCREG5 " " " 4H 5H 6H 7H ADCOMREG0 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH ADCREG6 " " " 8H 9H AH BH ADCOMREG1 8H 9H AH BH 8H 9H AH BH CH DH EH FH ADCREG7 " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " " " " Register name ADR Register name [18] Watchdog timer ADR Register name ADR Register name ADR Register name ADR Register name FF004F00H 1H 2H 3H WDMOD " " " FF004F10H 1H 2H 3H FF004F20H 1H 2H 3H FF004F30H 1H 2H 3H 4H 5H 6H 7H WDCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH reserved " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH reserved " " " CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-27 2010-04-01 TMP19A44 Big [1] ROM correction ADR Register name ADR Register name ADR Register name ADR FF000000H 1H 2H 3H ADDREG0 " " " FF000010H 1H 2H 3H ADDREG4 " " " FF000020H 1H 2H 3H ADDREG8 " " " FF000030H 1H 2H 3H 4H 5H 6H 7H ADDREG1 " " " 4H 5H 6H 7H ADDREG5 " " " 4H 5H 6H 7H ADDREG9 " " " 4H 5H 6H 7H 8H 9H AH BH ADDREG2 " " " 8H 9H AH BH ADDREG6 " " " 8H 9H AH BH ADDREGA " " " 8H 9H AH BH CH DH EH FH ADDREG3 " " " CH DH EH FH ADDREG7 " " " CH DH EH FH ADDREGB " " " CH DH EH FH [2] FLASH control Register name [3] Protect control ADR Register name ADR Register name ADR Register name ADR Register name FF000100H 1H 2H 3H FLCS " " " FF000200H 1H 2H 3H SECBIT " " " FF000210H 1H 2H 3H FF000220H 1H 2H 3H 4H 5H 6H 7H Reserved " " " 4H 5H 6H 7H DSUSECBIT " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH Reserved " " " 8H 9H AH BH SECCODE " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH Reserved " " " CH DH EH FH DSUSECCODE CH DH EH FH CH DH EH FH " " " [4] Interrupt controller ADR Register name ADR Register name ADR Register name ADR Register name FF001000H 1H 2H 3H IMC0 " " " FF001010H 1H 2H 3H IMC4 " " " FF001020H 1H 2H 3H IMC8 " " " FF001030H 1H 2H 3H IMCC " " " 4H 5H 6H 7H IMC1 " " " 4H 5H 6H 7H IMC5 " " " 4H 5H 6H 7H IMC9 " " " 4H 5H 6H 7H IMCD " " " 8H 9H AH BH IMC2 " " " 8H 9H AH BH IMC6 " " " 8H 9H AH BH IMCA " " " 8H 9H AH BH IMCE " " " CH DH EH FH IMC3 " " " CH DH EH FH IMC7 " " " CH DH EH FH IMCB " " " CH DH EH FH IMCF " " " Table of Special Function Registers TMP19A44(rev1.3)22-28 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF001040H 1H 2H 3H IMC10 " " " FF001050H 1H 2H 3H IMC14 " " " FF001060H 1H 2H 3H IMC18 " " " FF001070H 1H 2H 3H Reserved " " " 4H 5H 6H 7H IMC11 " " " 4H 5H 6H 7H IMC15 " " " 4H 5H 6H 7H IMC19 " " " 4H 5H 6H 7H Reserved " " " 8H 9H AH BH IMC12 " " " 8H 9H AH BH IMC16 " " " 8H 9H AH BH Reserved " " " 8H 9H AH BH Reserved " " " CH DH EH FH IMC13 " " " CH DH EH FH IMC17 " " " CH DH EH FH Reserved " " " CH DH EH FH Reserved " " " ADR Register name ADR Register name FF001080H 1H 2H 3H IVR " " " FF001090H 1H 2H 3H FF0010A0H 1H 2H 3H FF0010B0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH Register name ADR FF0010C0H 1H 2H 3H INTCLR " " " FF0010D0H 1H 2H 3H FF0010E0H 1H 2H 3H FF0010F0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers Register name Register name Register name DREQFLG " " " ADR ADR ADR 4H 5H 6H 7H Register name ADR TMP19A44(rev1.3)22-29 ADR Register name 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF001100H 1H 2H 3H FF001110H 1H 2H 3H FF001120H 1H 2H 3H FF001130H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ILEV " " " [5] DMA controller ADR Register name ADR Register name ADR Register name ADR Register name FF001200H 1H 2H 3H CCR0 " " " FF001210H 1H 2H 3H BCR0 " " " FF001220H 1H 2H 3H CCR1 " " " FF001230H 1H 2H 3H BCR1 " " " 4H 5H 6H 7H CSR0 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR1 " " " 4H 5H 6H 7H 8H 9H AH BH SAR0 " " " 8H 9H AH BH 8H 9H AH BH SAR1 " " " 8H 9H AH BH CH DH EH FH DAR0 " " " CH DH EH FH CH DH EH FH DAR1 " " " CH DH EH FH DTCR0 " " " DTCR1 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF001240H 1H 2H 3H CCR2 " " " FF001250H 1H 2H 3H BCR2 " " " FF001260H 1H 2H 3H CCR3 " " " FF001270H 1H 2H 3H BCR3 " " " 4H 5H 6H 7H CSR2 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR3 " " " 4H 5H 6H 7H 8H 9H AH BH SAR2 " " " 8H 9H AH BH 8H 9H AH BH SAR3 " " " 8H 9H AH BH CH DH EH FH DAR2 " " " CH DH EH FH CH DH EH FH DAR3 " " " CH DH EH FH Table of Special Function Registers DTCR2 " " " TMP19A44(rev1.3)22-30 DTCR3 " " " 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF001280H 1H 2H 3H CCR4 " " " FF001290H 1H 2H 3H BCR4 " " " FF0012A0H 1H 2H 3H CCR5 " " " FF0012B0H 1H 2H 3H BCR5 " " " 4H 5H 6H 7H CSR4 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR5 " " " 4H 5H 6H 7H 8H 9H AH BH SAR4 " " " 8H 9H AH BH 8H 9H AH BH SAR5 " " " 8H 9H AH BH CH DH EH FH DAR4 " " " CH DH EH FH CH DH EH FH DAR5 " " " CH DH EH FH DTCR4 " " " DTCR5 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF0012C0H 1H 2H 3H CCR6 " " " FF0012D0H 1H 2H 3H BCR6 " " " FF0012E0H 1H 2H 3H CCR7 " " " FF0012F0H 1H 2H 3H BCR7 " " " 4H 5H 6H 7H CSR6 " " " 4H 5H 6H 7H 4H 5H 6H 7H CSR7 " " " 4H 5H 6H 7H 8H 9H AH BH SAR6 " " " 8H 9H AH BH 8H 9H AH BH SAR7 " " " 8H 9H AH BH CH DH EH FH DAR6 " " " CH DH EH FH CH DH EH FH DAR7 " " " CH DH EH FH DTCR6 " " " DTCR7 " " " [6] Chip select/wait controller ADR Register name ADR Register name ADR FF001300H 1H 2H 3H DCR " " " FF001400H 1H 2H 3H BMA0 " " " FF001410H 1H 2H 3H FF001420H 1H 2H 3H 4H 5H 6H 7H RSR " " " 4H 5H 6H 7H BMA1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH BMA2 " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH BMA3 " " " CH DH EH FH CH DH EH FH 8H 9H AH BH CH DH EH FH DHR " " " Table of Special Function Registers Register name TMP19A44(rev1.3)22-31 ADR Register name 2010-04-01 TMP19A44 Big [7] Real time clock ADR Register name ADR Register name ADR Register name ADR Register name FF001480H 1H 2H 3H B01CS " " " FF001500H 1H 2H 3H HOURR " MINR SECR FF001510H 1H 2H 3H FF001520H 1H 2H 3H 4H 5H 6H 7H B23CS " " " 4H 5H 6H 7H YEARR MONTHR DATER DAYR 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH BEXCS " " " 8H 9H AH BH PAGER " " " 8H 9H AH BH 8H 9H AH BH F0014C0H 1H 2H 3H BUSCR CH DH EH FH RESTR " " " CH DH EH FH CH DH EH FH [8] Two-phase pulse input counter ADR Register name ADR Register name ADR Register name ADR Register name FF001600H 1H 2H 3H PHC0RUN " " " FF001610H 1H 2H 3H PHC0CMP0 " " " FF001620H 1H 2H 3H Reserved " " " FF001630H 1H 2H 3H 4H 5H 6H 7H PHC0CR " " " 4H 5H 6H 7H PHC0CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC0EN " " " 8H 9H AH BH PHC0CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC0FLG " " " CH DH EH FH Reserved " " " CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF001640H 1H 2H 3H PHC1RUN " " " FF001650H 1H 2H 3H PHC1CMP0 " " " FF001660H 1H 2H 3H Reserved " " " FF001670H 1H 2H 3H 4H 5H 6H 7H PHC1CR " " " 4H 5H 6H 7H PHC1CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC1EN " " " 8H 9H AH BH PHC1CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC1FLG " " " CH DH EH FH Reserved " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-32 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF001680H 1H 2H 3H PHC2RUN " " " FF001690H 1H 2H 3H PHC2CMP0 " " " FF0016A0H 1H 2H 3H Reserved " " " FF0016B0H 1H 2H 3H 4H 5H 6H 7H PHC2CR " " " 4H 5H 6H 7H PHC2CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC2EN " " " 8H 9H AH BH PHC2CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC2FLG " " " CH DH EH FH Reserved " " " CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0016C0H 1H 2H 3H PHC3RUN " " " FF0016D0H 1H 2H 3H PHC3CMP0 " " " FF0016E0H 1H 2H 3H Reserved " " " FF0016F0H 1H 2H 3H 4H 5H 6H 7H PHC3CR " " " 4H 5H 6H 7H PHC3CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC3EN " " " 8H 9H AH BH PHC3CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC3FLG " " " CH DH EH FH Reserved " " " CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF001700H 1H 2H 3H PHC4RUN " " " FF001710H 1H 2H 3H PHC4CMP0 " " " FF001720H 1H 2H 3H Reserved " " " FF001730H 1H 2H 3H 4H 5H 6H 7H PHC4CR " " " 4H 5H 6H 7H PHC4CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC4EN " " " 8H 9H AH BH PHC4CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC4FLG " " " CH DH EH FH Reserved " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-33 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF001740H 1H 2H 3H PHC5RUN " " " FF001750H 1H 2H 3H PHC5CMP0 " " " FF001760H 1H 2H 3H Reserved " " " FF001770H 1H 2H 3H 4H 5H 6H 7H PHC5CR " " " 4H 5H 6H 7H PHC5CMP1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHC5EN " " " 8H 9H AH BH PHC5CNT " " " 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHC5FLG " " " CH DH EH FH Reserved " " " CH DH EH FH CH DH EH FH [9] High speed serial channel ADR Register name FF001800H 1H 2H 3H HSC0BUF ADR Register name FF001810H 1H 2H 3H HSC1BUF ADR Register name FF001820H 1H 2H 3H HSC2BUF ADR Register name FF001830H 1H 2H 3H 4H 5H 6H 7H HSC0EN HSC0MOD2 HSC0MOD1 HBR0ADD 4H 5H 6H 7H HSC1EN HSC1MOD2 HSC1MOD1 HBR1ADD 4H 5H 6H 7H HSC3EN HSC3MOD2 HSC3MOD1 HBR3ADD 4H 5H 6H 7H 8H 9H AH BH HSC0TST HSC0RST HSC0TFC HSC0RFC 8H 9H AH BH HSC1TST HSC1RST HSC1TFC HSC1RFC 8H 9H AH BH HSC3TST HSC3RST HSC3TFC HSC3RFC 8H 9H AH BH CH DH EH FH HBR0CR HSC0MOD0 HSC0CR HSC0FCNF CH DH EH FH HBR1CR HSC1MOD0 HSC1CR HSC1FCNF CH DH EH FH HBR3CR HSC3MOD0 HSC3CR HSC3FCNF CH DH EH FH [10] Clock generator ADR Register name ADR Register name ADR Register name ADR Register name FF001900H 1H 2H 3H SYSCR " " " FF001910H 1H 2H 3H SCKSEL " " " FF001920H 1H 2H 3H IMCGA " " " FF001930H 1H 2H 3H IMCGE " " " 4H 5H 6H 7H OSCCR " " " 4H 5H 6H 7H ICRCG " " " 4H 5H 6H 7H IMCGB " " " 4H 5H 6H 7H IMCGF " " " 8H 9H AH BH STBYCR " " " 8H 9H AH BH NMIFLG " " " 8H 9H AH BH IMCGC " " " 8H 9H AH BH IMCG10 " " " CH DH EH FH PLLSEL " " " CH DH EH FH RSTFLG " " " CH DH EH FH IMCGD " " " CH DH EH FH IMCG11 " " " Table of Special Function Registers TMP19A44(rev1.3)22-34 2010-04-01 TMP19A44 Big [11] Key-on wake-up ADR Register name ADR Register name ADR Register name ADR Register name FF001A00H 1H 2H 3H KWUPST00 " " " FF001A10H 1H 2H 3H KWUPST04 " " " FF001A20H 1H 2H 3H KWUPST08 " " " FF001A30H 1H 2H 3H KWUPST12 " " " 4H 5H 6H 7H KWUPST01 " " " 4H 5H 6H 7H KWUPST05 " " " 4H 5H 6H 7H KWUPST09 " " " 4H 5H 6H 7H KWUPST13 " " " 8H 9H AH BH KWUPST02 " " " 8H 9H AH BH KWUPST06 " " " 8H 9H AH BH KWUPST10 " " " 8H 9H AH BH KWUPST14 " " " CH DH EH FH KWUPST03 " " " CH DH EH FH KWUPST07 " " " CH DH EH FH KWUPST11 " " " CH DH EH FH KWUPST15 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF001A40H 1H 2H 3H KWUPST 16 " " " FF001A50H 1H 2H 3H KWUPST 20 " " " FF001A60H 1H 2H 3H KWUPST 24 " " " FF001A70H 1H 2H 3H KWUPST 28 " " " 4H 5H 6H 7H KWUPST 17 " " " 4H 5H 6H 7H KWUPST 21 " " " 4H 5H 6H 7H KWUPST 25 " " " 4H 5H 6H 7H KWUPST 29 " " " 8H 9H AH BH KWUPST 18 " " " 8H 9H AH BH KWUPST 22 " " " 8H 9H AH BH KWUPST 26 " " " 8H 9H AH BH KWUPST 30 " " " CH DH EH FH KWUPST 19 " " " CH DH EH FH KWUPST 23 " " " CH DH EH FH KWUPST 27 " " " CH DH EH FH KWUPST 31 " " " ADR Register name ADR Register name ADR Register name ADR Register name FF001A80H 1H 2H 3H PKEY " " " FF001A90H 1H 2H 3H FF001AA0H 1H 2H 3H FF001AB0H 1H 2H 3H 4H 5H 6H 7H KWUPCNT " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH KWUPCLR " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH KWUPINT " " " CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-35 2010-04-01 TMP19A44 Big [12] Port registers ADR Register name ADR Register name ADR Register name ADR Register name FF004000H 1H 2H 3H P0 " " " FF004010H 1H 2H 3H FF004020H 1H 2H 3H FF004030H 1H 2H 3H 4H 5H 6H 7H P0CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P0FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH Register name ADR P0PUP " " " Register name CH DH EH FH ADR Register name ADR ADR Register name FF004040H 1H 2H 3H P1 " " " FF004050H 1H 2H 3H FF004060H 1H 2H 3H FF004070H 1H 2H 3H 4H 5H 6H 7H P1CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P1FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P1FC2 " " " CH DH EH FH CH DH EH FH P1PUP " " " Register name CH DH EH FH ADR Register name ADR Register name ADR ADR Register name FF004080H 1H 2H 3H P2 " " " FF004090H 1H 2H 3H P2FC3 " " " FF0040A0H 1H 2H 3H FF0040B0H 1H 2H 3H 4H 5H 6H 7H P2CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P2FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P2FC2 " " " CH DH EH FH CH DH EH FH Table of Special Function Registers P2PUP " " " TMP19A44(rev1.3)22-36 P2IE " " " CH DH EH FH 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF0040C0H 1H 2H 3H P3 " " " FF0040D0H 1H 2H 3H FF0040E0H 1H 2H 3H FF0040F0H 1H 2H 3H 4H 5H 6H 7H P3CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P3FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P3FC2 " " " CH DH EH FH CH DH EH FH Register name ADR P3PUP " " " Register name CH DH EH FH ADR Register name ADR FF004100H 1H 2H 3H P4 " " " FF004110H 1H 2H 3H FF004120H 1H 2H 3H FF004130H 1H 2H 3H ADR Register name 4H 5H 6H 7H P4CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P4FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P4FC2 " " " CH DH EH FH CH DH EH FH P4PUP " " " Register name Register name ADR Register name ADR FF004140H 1H 2H 3H P5 " " " FF004150H 1H 2H 3H P5FC3 " " " FF004160H 1H 2H 3H FF004170H 1H 2H 3H ADR Register name 4H 5H 6H 7H P5CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P5FC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH P5FC2 " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-37 P4IE " " " CH DH EH FH ADR P5PUP " " " P3IE " " " P5IE " " " CH DH EH FH 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004180H 1H 2H 3H P6 " " " FF004190H 1H 2H 3H P6FC3 " " " FF0041A0H 1H 2H 3H FF0041B0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H P6CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P6FC1 " " " 8H 9H AH BH 8H 9H AH BH P6ODE " " " 8H 9H AH BH CH DH EH FH P6FC2 " " " CH DH EH FH CH DH EH FH P6PUP " " " CH DH EH FH ADR Register name ADR FF0041C0H 1H 2H 3H P7 " " " FF0041D0H 1H 2H 3H FF0041E0H 1H 2H 3H FF0041F0H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH P7FC2 " " " Register name Register name P7PUP " " " FF004200H 1H 2H 3H P8 " " " FF004210H 1H 2H 3H FF004220H 1H 2H 3H FF004230H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH P8PUP " " " TMP19A44(rev1.3)22-38 P7IE " " " CH DH EH FH ADR Table of Special Function Registers Register name Register name Register name P8FC2 " " " ADR ADR ADR CH DH EH FH Register name ADR P6IE " " " ADR Register name P8IE " " " CH DH EH FH 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004240H 1H 2H 3H P9 " " " FF004250H 1H 2H 3H FF004260H 1H 2H 3H FF004270H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H P9CR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH P9FC1 " " " 8H 9H AH BH 8H 9H AH BH P9ODE " " " 8H 9H AH BH CH DH EH FH P9FC2 " " " CH DH EH FH CH DH EH FH P9PUP " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR FF004280H 1H 2H 3H PA " " " FF004290H 1H 2H 3H Reserved " " " FF0042A0H 1H 2H 3H FF0042B0H 1H 2H 3H Register name 4H 5H 6H 7H PACR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PAFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH PAFC2 " " " CH DH EH FH CH DH EH FH PAPUP " " " Register name Register name ADR Register name ADR FF0042C0H 1H 2H 3H PB " " " FF0042D0H 1H 2H 3H Reserved " " " FF0042E0H 1H 2H 3H FF0042F0H 1H 2H 3H ADR Register name 4H 5H 6H 7H 4H 5H 6H 7H PBCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PBFC1 " " " 8H 9H AH BH 8H 9H AH BH PBODE " " " 8H 9H AH BH CH DH EH FH PBFC2 " " " CH DH EH FH CH DH EH FH PBPUP " " " CH DH EH FH TMP19A44(rev1.3)22-39 PAIE " " " CH DH EH FH ADR Table of Special Function Registers P9IE " " " PBIE " " " 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004300H 1H 2H 3H PC " " " FF004310H 1H 2H 3H Reserved " " " FF004320H 1H 2H 3H FF004330H 1H 2H 3H 4H 5H 6H 7H 4H 5H 6H 7H PCCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PCFC1 " " " 8H 9H AH BH 8H 9H AH BH PCODE " " " 8H 9H AH BH CH DH EH FH PCFC2 " " " CH DH EH FH CH DH EH FH PCPUP " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR FF004340H 1H 2H 3H PD " " " FF004350H 1H 2H 3H Reserved " " " FF004360H 1H 2H 3H FF004370H 1H 2H 3H 4H 5H 6H 7H Register name 4H 5H 6H 7H PDCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PDFC1 " " " 8H 9H AH BH 8H 9H AH BH PDODE " " " 8H 9H AH BH CH DH EH FH PDFC2 " " " CH DH EH FH CH DH EH FH PDPUP " " " CH DH EH FH Register name ADR Register name ADR Register name ADR FF004380H 1H 2H 3H PE " " " FF004390H 1H 2H 3H Reserved " " " FF0043A0H 1H 2H 3H FF0043B0H 1H 2H 3H ADR PECR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PEFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH Table of Special Function Registers PEPUP " " " TMP19A44(rev1.3)22-40 PDIE " " " Register name 4H 5H 6H 7H CH DH EH FH PCIE " " " PEIE " " " CH DH EH FH 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF0043C0H 1H 2H 3H PF " " " FF0043D0H 1H 2H 3H Reserved " " " FF0043E0H 1H 2H 3H FF0043F0H 1H 2H 3H 4H 5H 6H 7H PFCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PFFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH PFFC2 " " " CH DH EH FH CH DH EH FH PFPUP " " " Register name CH DH EH FH ADR Register name ADR Register name ADR FF004400H 1H 2H 3H PG " " " FF004410H 1H 2H 3H Reserved " " " FF004420H 1H 2H 3H FF004430H 1H 2H 3H ADR Register name 4H 5H 6H 7H PGCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PGFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH PGPUP " " " Register name Register name ADR Register name ADR FF004440H 1H 2H 3H PH " " " FF004450H 1H 2H 3H Reserved " " " FF004460H 1H 2H 3H FF004470H 1H 2H 3H ADR Register name 4H 5H 6H 7H PHCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PHFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH PHFC2 " " " CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-41 PGIE " " " CH DH EH FH ADR PHPUP " " " PFIE " " " PHIE " " " CH DH EH FH 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004480H 1H 2H 3H PI " " " FF004490H 1H 2H 3H Reserved " " " FF0044A0H 1H 2H 3H FF0044B0H 1H 2H 3H 4H 5H 6H 7H PICR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PIFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH Register name ADR PIPUP " " " Register name CH DH EH FH ADR Register name ADR FF0044C0H 1H 2H 3H PJ " " " FF0044D0H 1H 2H 3H FF0044E0H 1H 2H 3H FF0044F0H 1H 2H 3H ADR Register name 4H 5H 6H 7H PJCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH PJFC1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH PIIE " " " PJPUP " " " PJIE " " " CH DH EH FH [13] 16-bit timer ADR Register name ADR Register name ADR Register name ADR Register name FF004500H 1H 2H 3H TB0EN " " " FF004510H 1H 2H 3H TB0FFCR " " " FF004520H 1H 2H 3H TB0RG0 " " " FF004530H 1H 2H 3H 4H 5H 6H 7H TB0RUN " " " 4H 5H 6H 7H TB0ST " " " 4H 5H 6H 7H TB0RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB0CR " " " 8H 9H AH BH TB0IM " " " 8H 9H AH BH TB0CP0 " " " 8H 9H AH BH CH DH EH FH TB0MOD " " " CH DH EH FH TM0UC " " " CH DH EH FH TB0CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-42 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004540H 1H 2H 3H TB1EN " " " FF004550H 1H 2H 3H TB1FFCR " " " FF004560H 1H 2H 3H TB1RG0 " " " FF004570H 1H 2H 3H 4H 5H 6H 7H TB1RUN " " " 4H 5H 6H 7H TB1ST " " " 4H 5H 6H 7H TB1RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB1CR " " " 8H 9H AH BH TB1IM " " " 8H 9H AH BH TB1CP0 " " " 8H 9H AH BH CH DH EH FH TB1MOD " " " CH DH EH FH TM1UC " " " CH DH EH FH TB1CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004580H 1H 2H 3H TB2EN " " " FF004590H 1H 2H 3H TB2FFCR " " " FF0045A0H 1H 2H 3H TB2RG0 " " " FF0045B0H 1H 2H 3H 4H 5H 6H 7H TB2RUN " " " 4H 5H 6H 7H TB2ST " " " 4H 5H 6H 7H TB2RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB2CR " " " 8H 9H AH BH TB2IM " " " 8H 9H AH BH TB2CP0 " " " 8H 9H AH BH CH DH EH FH TB2MOD " " " CH DH EH FH TM2UC " " " CH DH EH FH TB2CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0045C0H 1H 2H 3H TB3EN " " " FF0045D0H 1H 2H 3H TB3FFCR " " " FF0045E0H 1H 2H 3H TB3RG0 " " " FF0045F0H 1H 2H 3H 4H 5H 6H 7H TB3RUN " " " 4H 5H 6H 7H TB3ST " " " 4H 5H 6H 7H TB3RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB3CR " " " 8H 9H AH BH TB3IM " " " 8H 9H AH BH TB3CP0 " " " 8H 9H AH BH CH DH EH FH TB3MOD " " " CH DH EH FH TM3UC " " " CH DH EH FH TB3CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-43 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004600H 1H 2H 3H TB4EN " " " FF004610H 1H 2H 3H TB4FFCR " " " FF004620H 1H 2H 3H TB4RG0 " " " FF004630H 1H 2H 3H 4H 5H 6H 7H TB4RUN " " " 4H 5H 6H 7H TB4ST " " " 4H 5H 6H 7H TB4RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB4CR " " " 8H 9H AH BH TB4IM " " " 8H 9H AH BH TB4CP0 " " " 8H 9H AH BH CH DH EH FH TB4MOD " " " CH DH EH FH TM4UC " " " CH DH EH FH TB4CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004640H 1H 2H 3H TB5EN " " " FF004650H 1H 2H 3H TB5FFCR " " " FF004660H 1H 2H 3H TB5RG0 " " " FF004670H 1H 2H 3H 4H 5H 6H 7H TB5RUN " " " 4H 5H 6H 7H TB5ST " " " 4H 5H 6H 7H TB5RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB5CR " " " 8H 9H AH BH TB5IM " " " 8H 9H AH BH TB5CP0 " " " 8H 9H AH BH CH DH EH FH TB5MOD " " " CH DH EH FH TM5UC " " " CH DH EH FH TB5CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004680H 1H 2H 3H TB6EN " " " FF004690H 1H 2H 3H TB6FFCR " " " FF0046A0H 1H 2H 3H TB6RG0 " " " FF0046B0H 1H 2H 3H 4H 5H 6H 7H TB6RUN " " " 4H 5H 6H 7H TB6ST " " " 4H 5H 6H 7H TB6RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB6CR " " " 8H 9H AH BH TB6IM " " " 8H 9H AH BH TB6CP0 " " " 8H 9H AH BH CH DH EH FH TB6MOD " " " CH DH EH FH TM6UC " " " CH DH EH FH TB6CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-44 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF0046C0H 1H 2H 3H TB7EN " " " FF0046D0H 1H 2H 3H TB7FFCR " " " FF0046E0H 1H 2H 3H TB7RG0 " " " FF0046F0H 1H 2H 3H 4H 5H 6H 7H TB7RUN " " " 4H 5H 6H 7H TB7ST " " " 4H 5H 6H 7H TB7RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB7CR " " " 8H 9H AH BH TB7IM " " " 8H 9H AH BH TB7CP0 " " " 8H 9H AH BH CH DH EH FH TB7MOD " " " CH DH EH FH TM7UC " " " CH DH EH FH TB7CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004700H 1H 2H 3H TB8EN " " " FF004710H 1H 2H 3H TB8FFCR " " " FF004720H 1H 2H 3H TB8RG0 " " " FF004730H 1H 2H 3H 4H 5H 6H 7H TB8RUN " " " 4H 5H 6H 7H TB8ST " " " 4H 5H 6H 7H TB8RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB8CR " " " 8H 9H AH BH TB8IM " " " 8H 9H AH BH TB8CP0 " " " 8H 9H AH BH CH DH EH FH TB8MOD " " " CH DH EH FH TM8UC " " " CH DH EH FH TB8CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004740H 1H 2H 3H TB9EN " " " FF004785H 1H 2H 3H TB9FFCR " " " FF004760H 1H 2H 3H TB9RG0 " " " FF004770H 1H 2H 3H 4H 5H 6H 7H TB9RUN " " " 4H 5H 6H 7H TB9ST " " " 4H 5H 6H 7H TB9RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB9CR " " " 8H 9H AH BH TB9IM " " " 8H 9H AH BH TB9CP0 " " " 8H 9H AH BH CH DH EH FH TB9MOD " " " CH DH EH FH TM9UC " " " CH DH EH FH TB9CP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-45 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004780H 1H 2H 3H TBAEN " " " FF004790H 1H 2H 3H TBAFFCR " " " FF0047A0H 1H 2H 3H TBARG0 " " " FF0047B0H 1H 2H 3H 4H 5H 6H 7H TBARUN " " " 4H 5H 6H 7H TBAST " " " 4H 5H 6H 7H TBARG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBACR " " " 8H 9H AH BH TBAIM " " " 8H 9H AH BH TBACP0 " " " 8H 9H AH BH CH DH EH FH TBAMOD " " " CH DH EH FH TMAUC " " " CH DH EH FH TBACP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0047C0H 1H 2H 3H TBBEN " " " FF0047D0H 1H 2H 3H TBBFFCR " " " FF0047E0H 1H 2H 3H TBBRG0 " " " FF0047F0H 1H 2H 3H 4H 5H 6H 7H TBBRUN " " " 4H 5H 6H 7H TBBST " " " 4H 5H 6H 7H TBBRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBBCR " " " 8H 9H AH BH TBBIM " " " 8H 9H AH BH TBBCP0 " " " 8H 9H AH BH CH DH EH FH TBBMOD " " " CH DH EH FH TMBUC " " " CH DH EH FH TBBCP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004800H 1H 2H 3H TBCEN " " " FF004810H 1H 2H 3H TBCFFCR " " " FF004820H 1H 2H 3H TBCRG0 " " " FF004830H 1H 2H 3H 4H 5H 6H 7H TBCRUN " " " 4H 5H 6H 7H TBCST " " " 4H 5H 6H 7H TBCRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBCCR " " " 8H 9H AH BH TBCIM " " " 8H 9H AH BH TBCCP0 " " " 8H 9H AH BH CH DH EH FH TBCMOD " " " CH DH EH FH TMCUC " " " CH DH EH FH TBCCP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-46 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004840H 1H 2H 3H TBDEN " " " FF004850H 1H 2H 3H TBDFFCR " " " FF004860H 1H 2H 3H TBDRG0 " " " FF004870H 1H 2H 3H 4H 5H 6H 7H TBDRUN " " " 4H 5H 6H 7H TBDST " " " 4H 5H 6H 7H TBDRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBDCR " " " 8H 9H AH BH TBDIM " " " 8H 9H AH BH TBDCP0 " " " 8H 9H AH BH CH DH EH FH TBDMOD " " " CH DH EH FH TMDUC " " " CH DH EH FH TBDCP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004880H 1H 2H 3H TBEEN " " " FF004890H 1H 2H 3H TBEFFCR " " " FF0048A0H 1H 2H 3H TBERG0 " " " FF0048B0H 1H 2H 3H 4H 5H 6H 7H TBERUN " " " 4H 5H 6H 7H TBEST " " " 4H 5H 6H 7H TBERG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBECR " " " 8H 9H AH BH TBEIM " " " 8H 9H AH BH TBECP0 " " " 8H 9H AH BH CH DH EH FH TBEMOD " " " CH DH EH FH TMEUC " " " CH DH EH FH TBECP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF0048C0H 1H 2H 3H TBFEN " " " FF0048D0H 1H 2H 3H TBFFFCR " " " FF0048E0H 1H 2H 3H TBFRG0 " " " FF0048F0H 1H 2H 3H 4H 5H 6H 7H TBFRUN " " " 4H 5H 6H 7H TBFST " " " 4H 5H 6H 7H TBFRG1 " " " 4H 5H 6H 7H 8H 9H AH BH TBFCR " " " 8H 9H AH BH TBFIM " " " 8H 9H AH BH TBFCP0 " " " 8H 9H AH BH CH DH EH FH TBFMOD " " " CH DH EH FH TMFUC " " " CH DH EH FH TBFCP1 " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-47 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004900H 1H 2H 3H TB10EN " " " FF004910H 1H 2H 3H TB10FFCR " " " FF004920H 1H 2H 3H TB10RG0 " " " FF004930H 1H 2H 3H 4H 5H 6H 7H TB10RUN " " " 4H 5H 6H 7H TB10ST " " " 4H 5H 6H 7H TB10RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB10CR " " " 8H 9H AH BH TB10IM " " " 8H 9H AH BH TB10CP0 " " " 8H 9H AH BH CH DH EH FH TB10MOD " " " CH DH EH FH TM10UC " " " CH DH EH FH TB10CP1 " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004940H 1H 2H 3H TB11EN " " " FF004950H 1H 2H 3H TB11FFCR " " " FF004960H 1H 2H 3H TB11RG0 " " " FF004970H 1H 2H 3H 4H 5H 6H 7H TB11RUN " " " 4H 5H 6H 7H TB11ST " " " 4H 5H 6H 7H TB11RG1 " " " 4H 5H 6H 7H 8H 9H AH BH TB11CR " " " 8H 9H AH BH TB11IM " " " 8H 9H AH BH TB11CP0 " " " 8H 9H AH BH CH DH EH FH TB11MOD " " " CH DH EH FH TM11UC " " " CH DH EH FH TB11CP1 " " " CH DH EH FH [14] 32-bit timer ADR Register name ADR Register name ADR Register name ADR Register name FF004A00H 1H 2H 3H TCEN " " " FF004A10H 1H 2H 3H TBTRDCAP " " " FF004A20H 1H 2H 3H CMPCTL0 " " " FF004A30H 1H 2H 3H CMPCTL1 " " " TCCMP0 " " " 4H 5H 6H 7H TCCMP1 " " " 4H 5H 6H 7H TBTRUN " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH TBTCR " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH TBTCAP " " " CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-48 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004A40H 1H 2H 3H CMPCTL2 " " " FF004A50H 1H 2H 3H CMPCTL3 " " " FF004A60H 1H 2H 3H CMPCTL4 " " " FF004A70H 1H 2H 3H CMPCTL5 " " " 4H 5H 6H 7H TCCMP2 " " " 4H 5H 6H 7H TCCMP3 " " " 4H 5H 6H 7H TCCMP4 " " " 4H 5H 6H 7H TCCMP5 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004A80H 1H 2H 3H CMPCTL6 " " " FF004A90H 1H 2H 3H CMPCTL7 " " " FF004AA0H 1H 2H 3H CAPCR0 " " " FF004AB0H 1H 2H 3H CAPCR1 " " " 4H 5H 6H 7H TCCMP6 " " " 4H 5H 6H 7H TCCMP7 " " " 4H 5H 6H 7H TCCAP0 " " " 4H 5H 6H 7H TCCAP1 " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004AC0H 1H 2H 3H CAPCR2 " " " FF004AD0H 1H 2H 3H CAPCR3 " " " FF004AE0H 1H 2H 3H FF004AF0H 1H 2H 3H 4H 5H 6H 7H TCCAP2 " " " 4H 5H 6H 7H TCCAP3 " " " 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-49 2010-04-01 TMP19A44 Big [15] I2CBUS/serial channel ADR Register name ADR Register name ADR FF004B00H 1H 2H 3H SBICR0 " " " FF004B10H 1H 2H 3H SBICR2/SBISR FF004B20H 1H 2H 3H FF004B30H 1H 2H 3H 4H 5H 6H 7H SBICR1 " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH SBIDBR " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH I2CAR " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " SBIBR " " " Register name ADR Register name [16] UART/serial channel ADR Register name ADR Register name ADR Register name ADR Register name FF004C00H 1H 2H 3H SC0EN " " " FF004C10H 1H 2H 3H BR0CR " " " FF004C20H 1H 2H 3H SC0RFC " " " FF004C30H 1H 2H 3H SC0FCNF " " " 4H 5H 6H 7H SC0BUF " " " 4H 5H 6H 7H BR0ADD " " " 4H 5H 6H 7H SC0TFC " " " 4H 5H 6H 7H 8H 9H AH BH SC0CR " " " 8H 9H AH BH SC0MOD1 " " " 8H 9H AH BH SC0RST " " " 8H 9H AH BH CH DH EH FH SC0MOD0 " " " CH DH EH FH SC0MOD2 " " " CH DH EH FH SC0TST " " " CH DH EH FH ADR Register name ADR Register name ADR Register name ADR Register name FF004C40H 1H 2H 3H SC1EN " " " FF004C50H 1H 2H 3H BR1CR " " " FF004C60H 1H 2H 3H SC1RFC " " " FF004C70H 1H 2H 3H SC1FCNF " " " 4H 5H 6H 7H SC1BUF " " " 4H 5H 6H 7H BR1ADD " " " 4H 5H 6H 7H SC1TFC " " " 4H 5H 6H 7H 8H 9H AH BH SC1CR " " " 8H 9H AH BH SC1MOD1 " " " 8H 9H AH BH SC1RST " " " 8H 9H AH BH CH DH EH FH SC1MOD0 " " " CH DH EH FH SC1MOD2 " " " CH DH EH FH SC1TST " " " CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-50 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004C80H 1H 2H 3H SC2EN " " " FF004C90H 1H 2H 3H BR2CR " " " FF004CA0H 1H 2H 3H SC2RFC " " " FF004CB0H 1H 2H 3H SC2FCNF " " " 4H 5H 6H 7H SC2BUF " " " 4H 5H 6H 7H BR2ADD " " " 4H 5H 6H 7H SC2TFC " " " 4H 5H 6H 7H 8H 9H AH BH SC2CR " " " 8H 9H AH BH SC2MOD1 " " " 8H 9H AH BH SC2RST " " " 8H 9H AH BH CH DH EH FH SC2MOD0 " " " CH DH EH FH SC2MOD2 " " " CH DH EH FH SC2TST " " " CH DH EH FH [17] 10-bit A/D converter ADR Register name ADR Register name ADR Register name ADR Register name FF004D00H 1H 2H 3H ADACLK " " " FF004D10H 1H 2H 3H ADAMOD3 " " " FF004D20H 1H 2H 3H reserved " " " FF004D30H 1H 2H 3H ADAREG0 " " " 4H 5H 6H 7H ADAMOD0 " " " 4H 5H 6H 7H ADAMOD4 " " " 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADAREG1 " " " 8H 9H AH BH ADAMOD1 " " " 8H 9H AH BH ADAMOD5 " " " 8H 9H AH BH reserved " " " 8H 9H AH BH ADAREG2 " " " CH DH EH FH ADAMOD2 " " " CH DH EH FH CH DH EH FH ADAREG3 " " " CH DH EH FH ADR Register name ADR Register name ADR FF004D40H 1H 2H 3H reserved " " " FF004D50H 1H 2H 3H ADAREGSP " " " FF004D60H 1H 2H 3H FF004D70H 1H 2H 3H 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADACOMREG0 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH reserved " " " 8H 9H AH BH ADACOMREG1 8H 9H AH BH 8H 9H AH BH CH DH EH FH reserved " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " Table of Special Function Registers " " " Register name TMP19A44(rev1.3)22-51 ADR Register name 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR Register name ADR Register name FF004D80H 1H 2H 3H ADBCLK " " " FF004D90H 1H 2H 3H ADBMOD3 " " " FF004DA0H 1H 2H 3H reserved " " " FF004DB0H 1H 2H 3H ADBREG0 " " " 4H 5H 6H 7H ADBMOD0 " " " 4H 5H 6H 7H ADBMOD4 " " " 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADBREG1 " " " 8H 9H AH BH ADBMOD1 " " " 8H 9H AH BH ADBMOD5 " " " 8H 9H AH BH reserved " " " 8H 9H AH BH ADBREG2 " " " CH DH EH FH ADBMOD2 " " " CH DH EH FH CH DH EH FH ADBREG3 " " " CH DH EH FH ADR Register name ADR Register name ADR FF004DC0H 1H 2H 3H reserved " " " FF004DD0H 1H 2H 3H ADBREGSP " " " FF004DE0H 1H 2H 3H FF004DF0H 1H 2H 3H 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADBCOMREG0 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH reserved " " " 8H 9H AH BH ADBCOMREG1 8H 9H AH BH 8H 9H AH BH CH DH EH FH reserved " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " " " " Register name ADR Register name ADR Register name ADR Register name ADR Register name ADR Register name FF004E00H 1H 2H 3H ADCCLK " " " FF004E10H 1H 2H 3H ADCMOD3 " " " FF004E20H 1H 2H 3H reserved " " " FF004E30H 1H 2H 3H ADCREG0 " " " 4H 5H 6H 7H ADCMOD0 " " " 4H 5H 6H 7H ADCMOD4 " " " 4H 5H 6H 7H reserved " " " 4H 5H 6H 7H ADCREG1 " " " 8H 9H AH BH ADCMOD1 " " " 8H 9H AH BH ADCMOD5 " " " 8H 9H AH BH reserved " " " 8H 9H AH BH ADCREG2 " " " CH DH EH FH ADCMOD2 " " " CH DH EH FH CH DH EH FH ADCREG3 " " " Table of Special Function Registers CH DH EH FH TMP19A44(rev1.3)22-52 2010-04-01 TMP19A44 Big ADR Register name ADR Register name ADR FF004E40H 1H 2H 3H ADCREG4 " " " FF004E50H 1H 2H 3H ADREGSP " " " FF004E60H 1H 2H 3H FF004E70H 1H 2H 3H 4H 5H 6H 7H ADCREG5 " " " 4H 5H 6H 7H ADCOMREG0 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH ADCREG6 " " " 8H 9H AH BH ADCOMREG1 8H 9H AH BH 8H 9H AH BH CH DH EH FH ADCREG7 " " " CH DH EH FH CH DH EH FH CH DH EH FH " " " " " " Register name ADR Register name [18] Watchdog timer ADR Register name ADR Register name ADR Register name ADR Register name FF004F00H 1H 2H 3H WDMOD " " " FF004F10H 1H 2H 3H FF004F20H 1H 2H 3H FF004F30H 1H 2H 3H 4H 5H 6H 7H WDCR " " " 4H 5H 6H 7H 4H 5H 6H 7H 4H 5H 6H 7H 8H 9H AH BH reserved " " " 8H 9H AH BH 8H 9H AH BH 8H 9H AH BH CH DH EH FH reserved " " " CH DH EH FH CH DH EH FH CH DH EH FH Table of Special Function Registers TMP19A44(rev1.3)22-53 2010-04-01 TMP19A44 23. JTAG Interface The TMP19A44 is equipped with the boundary scan interface that conforms to the Joint Test Action Group (JTAG) standard. This interface uses the industry-standard JTAG protocol (IEEE Standard 1149.1/D6). This chapter describes this JTAG interface with a mention of boundary scan, interface pins, interface signals, and test access ports (TAP). 23.1 Boundary Scan Overview IC (Integrated Circuit) density is ever increasing, SMDs (Surface Mount Devices) continue to decrease in size, components are now mounted on both sides of printed circuit boards (PCBs), and there are considerable technical developments related to embedding holes. Conventional internal circuit testing techniques are dependent on the physical contact between internal circuitry and chips and, therefore, their limitations with respect to efficiency and accuracy are manifest. With the ever-increasing IC complexity, tests conducted to perform inspections on all chips integrated into an IC are becoming larger in scale, and it is becoming more difficult to design an efficient, reliable IC testing program. To overcome this difficulty in performing IC tests, the "boundary scan" circuit was developed. It is a group of shift registers called "boundary scan cells" established between pins and internal circuitry (see Fig. 23-1). These boundary scan cells are bypassed under normal conditions. When an IC goes into test mode, data is sent from the boundary scan cells through the shift register bus in response to the instruction given by a test program, and various diagnostic tests are executed. In IC tests, five signals TDI, TDO, TMS, TCK and TRST are used. These signals are explained in the next section. Integrated circuit Pins on IC package Boundary scan cells Fig. 23-1 JTAG Boundary Scan Cells Note) The optional instructions IDCODE, USERCODE, INTEST and RUNBIST are not implemented in the TMP19A44. JTAG Interface TMP19A44(rev1.3) 23-1 2010-04-01 TMP19A44 23.2 JTAG Interface Signals JTAG interface signals are as follows (see Fig. 23-2): * TDI : To input JTAG serial data * TDO : To output JTAG serial data * TMS : To select JTAG test mode * TCK : To input JTAG serial clock * TRST : To input JTAG test reset 3 0 Instruction register JTDI pin 0 JTDO pin TAP controller Bypass register JTMS pin 482 0 Boundary scan register JTCK pin TRST pin Fig. 23-2 JTAG Interface Signals and Registers The JTAG boundary scan mechanism (hereafter called "JTAG mechanism") enables testing of the processor, printed circuit boards connected to the processor, and connections between other components on printed circuit boards. The JTAG mechanism does not have a function of testing the processor itself. JTAG Interface TMP19A44(rev1.3) 23-2 2010-04-01 TMP19A44 23.3 JTAG Controller and Registers The following JTAG controller and registers are built into the processor: * Instruction register * Boundary scan register * Bypass register * Device identification register * Test Access Port (TAP) controller In the JTAG basic mechanism, the TAP controller state machine monitors the signals input through the JTMS pin. As the JTAG mechanism starts operation, the TAP controller determines a test function to be executed by loading data into the JTAG instruction register (IR) and performing a serial data scan via the data register (DR), as shown in Table 23-1. When data is scanned, the state of the JTMS pin represents new specific data words and the end of data flow. The data register is selected according to data loaded into the instruction register. 23.3.1 Instruction Register The JTAG instruction register consists of four cells, including shift registers. It is used to select either a test to be executed or a test data register to be accessed or to select both. Either the boundary scan register or the bypass register is selected according to combinations shown in Table 23-1. Table 23-1 Bit Configurations of the JTAG Instruction Register Instruction code Most significant to least significant bit Instruction Data register to be selected 0000 0001 0010 to 1110 1111 EXTEST SAMPLE/PRELOAD Reserved BYPASS Boundary scan register Boundary scan register Reserved Bypass register Fig. 23-3 shows the format of the instruction register. 3 2 MSB 1 0 LSB Fig. 23-3 Instruction Register JTAG Interface TMP19A44(rev1.3) 23-3 2010-04-01 TMP19A44 The instruction code is shifted from the least significant bit to the instruction register. Most significant Least significant TDI TDO Fig. 23-4 Direction of a Shift of the Instruction Code to the Instruction Register 23.3.2 Bypass Register The bypass register has a one-bit width. If the TAP controller is in the Shift-DR state (bypass state), data at the TDI pin is shifted into the bypass register, and the output from the bypass register is shifted out to the TDO output pin. Simply put, the bypass register is a circuit for bypassing the devices in a serial boundary scan chain connected to the substrates that are not required for a test to be conducted. Fig. 23-5 shows the logical position of the bypass register in a boundary scan chain. If the bypass register is used, the speed of access to boundary scan registers in an active IC in a data path used for substrate level testing can be increased. JTDI Bypass register Input to substrate JTDO JTDO Input from substrate JTDI JTDO JTDI JTDI JTDO JTDI JTDO Pad cell of boundary scan register IC package Substrate Fig. 23-5 Function of the Bypass Register JTAG Interface TMP19A44(rev1.3) 23-4 2010-04-01 TMP19A44 23.3.3 Boundary Scan Register The boundary scan register has inputs and outputs for some analog output signals, as well as all signals from the TMP19A44 except control signals. Pins of the TMP19A44 can drive any test patterns by scanning data into the boundary scan register in the Shift-DR state. After the boundary scan register goes into the Capture-DR state, data enters the processor, is shifted, and inspected. The boundary scan register forms a data path. It basically functions as a single shift register of 483-bit width. Cells in this data path are connected to all input and output pads of the TMP19A44. The TDI input is introduced to the least significant bit (LSB) in the boundary scan register. The most significant bit in the boundary scan register is taken out of the TDO output. 23.3.4 Test Access Port (TAP) The test access port (TAP) consists of five signal pins: TRST, TDI, TDO, TMS, and TCK. Serial test data, instructions and test control signals are sent and received through these signal pins. Data is serially scanned into one of three registers (instruction register, bypass register and boundary scan register) via the TDI pin or it is scanned out from one of these three registers into the TDO pin, as shown in Fig. 23-6. The TMS input is used to control the state transitions of the main TAP controller state machine. The TCK input is a test clock exclusively for shifting serial JTAG data synchronously; it works independently of a chip core clock or a system clock. TCK TMS and TDI are sampled on the rising edge of TCK. TDO is sampled on the falling edge of TCK. Data is serially scanned in. 3 Data is serially scanned out. 0 Instruction register 0 Instruction register 0 0 Bypass register 482 0 Boundary scan register Bypass register TDI pin TMS pin 482 TDO pin 0 Boundary scan register Fig. 23-6 JTAG Test Access Port Data through the TDI and TMS pins are sampled on the rising edge of the input clock signal TCK. Data through the TDO pin changes on the falling edge of the clock signal TCK. JTAG Interface TMP19A44(rev1.3) 23-5 2010-04-01 TMP19A44 23.3.5 TAP Controller In the processor, a 16-state TAP controller specified in the IEEE JTAG standard is implemented. 23.3.6 Controller Reset To reset the state machine of the TAP controller, * assert the TRST signal input (Low) to reset the TAP controller or * continue to assert the input signal TMS by using the rising edge of the TCK input five times successively after clearing the reset state of the processor. The reset state can be maintained by keeping TMS in an asserted state. JTAG Interface TMP19A44(rev1.3) 23-6 2010-04-01 TMP19A44 23.3.7 State Transitions of the TAP Controller Fig. 23-7 shows the state transitions of the TAP controller. The state of the TAP controller changes depending on which value TMS will select on the rising edge of TCK, 0 or 1. In this figure, the arrow shows a state transition and the value that TMS selects to execute each state transition is shown alongside of the arrow. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 0 0 Capture-DR 1 Capture-IR 1 0 0 Shift-DR Shift-IR 0 1 1 Exit 1-IR 0 1 0 Pause-DR Pause-IR 0 1 0 1 Exit 2-DR 0 Exit 2-IR 1 1 Update-DR 1 0 1 Exit 1-DR 0 1 0 Update-IR 1 0 Fig. 23-7 State Transition Diagram of the TAP Controller JTAG Interface TMP19A44(rev1.3) 23-7 2010-04-01 TMP19A44 The TAP controller operates in each state described below. In Fig. 23-7, a column to the left is the data column and a column to the right is the instruction column. The data column represents the data register (DR), and the instruction column represents the instruction register (IR). * Test-Logic-Reset If the TAP controller is in a reset state, the device identification register is selected by default. The most significant bit in the boundary scan register is cleared to "0," and the output is disabled. The TAP controller remains in the Test-Logic-Reset state if TMS is "1." If "0" is input into TMS in the Test-Logic-Reset state, the TAP controller goes into the Run-Test/Idle state. * Run-Test/Idle In the Run-Test/Idle state, the IC goes into test mode only if a specific instruction, such as the built-in self test (BIST) instruction, is issued. If an instruction that cannot be executed in the RunTest/Idle state has been issued, the test data register selected by the last instruction maintains the existing state. The TAP controller remains in the Run-Test/Idle state if TMS is "0." If "1" is input into TMS, the TAP controller goes into the Select-DR-Scan state. * Select-DR-Scan The Select-DR-Scan state of the TAP controller is a transient state. In this state, the IC performs no operations. If "0" is input into TMS when the TAP controller is in the Select-DR-Scan state, the TAP controller goes into the Capture-DR state. If "1" is input into TMS, the instruction column goes into the Select-IR-Scan state. * Select-IR-Scan The Select-IR-Scan state of the TAP controller is a transient state. In this state, the IC performs no operations. If "0" is input into TMS when the TAP controller is in the Select-IR-Scan state, the TAP controller goes into the Capture-IR state. If "1" is input into TMS, the TAP controller returns to the TestLogic-Reset state. * Capture-DR If the data register selected by the instruction register has parallel inputs when the TAP controller is in the Capture-DR state, data is loaded into the data register in a parallel fashion. If the data register does not have parallel inputs or if data does not need to be loaded into the selected test data register, the data register maintains the existing state. If "0" is input into TMS when the TAP controller is in the Capture-DR state, the TAP controller goes into the Shift-DR state. If "1" is input into TMS, the TAP controller goes into the Exit 1-DR state. JTAG Interface TMP19A44(rev1.3) 23-8 2010-04-01 TMP19A44 * Shift-DR If the TAP controller is in the Shift-DR state, data is serially shifted out by the data register connected between TDI and TDO. If the TAP controller is in the Shift-DR state, the Shift-DR state is maintained while TMS is "0." If "1" is input into TMS, the TAP controller goes into the Exit 1-DR state. * Exit 1-DR The Exit 1-DR state of the TAP controller is a transient state. If "0" is input into TMS when the TAP controller is in the Exit 1-DR state, the TAP controller goes into the Pause-DR state. If "1" is input into TMS, it goes into the Update-DR state. * Pause-DR In the Pause-DR state, the shift operation performed by the data register selected by the instruction register is temporarily suspended. The instruction register and the data register maintain their existing state. The TAP controller remains in the Pause-DR state while TMS is "0." If "1" is input into TMS, it goes into the Exit 2-DR state. * Exit 2-DR The Exit 2-DR state of the TAP controller is a transient state. If "0" is input into TMS when the TAP controller is in the Exit 2-DR state, the TAP controller returns to the Shift-DR state. If "1" is input into TMS, it goes into the Update-DR state. * Update-DR In the Update-DR state, data is output in a parallel fashion from the data register having a parallel output synchronously to the rising edge of TCK. The data register with a parallel output latch does not output data during the shift operation; it outputs data only in the Update-DR state. If "0" is input into TMS when the TAP controller is in the Update-DR state, the TAP controller goes into the Run-Test/Idle state. If "1" is input into TMS, it goes into the Select-DR-Scan state. * Capture-IR In the Capture-IR state, data is loaded into the instruction register in a parallel fashion. Data loaded is 0001. The Capture-IR state is used to test the instruction register. A malfunction of the instruction register can be detected by shifting out the data loaded. If "0" is input into TMS when the TAP controller is in the Capture-IR state, the TAP controller goes into the Shift-IR state. If "1" is input into TMS, it goes into the Exit 1-IR state. * Shift-IR In the Shift-IR state, the instruction register is connected between TDI and TDO, and data loaded synchronously to the rising edge of TCK is serially shifted out. The TAP controller remains in the Shift-IR state while TMS is "0." If "1" is input into TMS, the TAP controller goes into the Exit 1-IR state. * Exit 1-IR The Exit 1-IR state of the TAP controller is a transient state. If "0" is input into TMS when the TAP controller is in the Exit 1-IR state, the TAP controller goes into the Pause-IR state. If "1" is input into TMS, it goes into the Update-IR state. JTAG Interface TMP19A44(rev1.3) 23-9 2010-04-01 TMP19A44 * Pause-IR In the Pause-IR state, the shift operation performed by the instruction register is temporarily suspended. The existing state of the instruction register and that of the data register are maintained. The TAP controller remains in the Pause-IR state while TMS is "0." If "1" is input into TMS, it goes into the Exit 2-IR state. * Exit 2-IR The Exit 2-IR state of the TAP controller is a transient state. If "0" is input into TMS when the TAP controller is in the Exit 2-IR state, the TAP controller goes into the Shift-IR state. If "1" is input into TMS, it goes into the Update-IR state. * Update-IR In the Update-IR state, instructions shifted into the instruction register are updated by outputting them in a parallel fashion synchronously to the rising edge of TCK. If "0" is input into TMS when the TAP controller is in the Update-IR state, the TAP controller goes into the Run-Test/Idle state. If "1" is input into TMS, it goes into the Select-DR-Scan state. Table 23-2 shows the boundary scan sequence relative to processor signals. Table 23-2 JTAG Scan Sequence Relative to the TMP19A44 Processor Pins 1: P86 8: P75 15: P96 22: PB4 29: PC0 36: P32 43: P37 50: P07 57: P21 64: P23 71: P43 78: P52 85: P61 92: PJ3 99: PJ5 106:PG7 113:PI2 120:BW0 127:PA3 134:PA4 141:PD5 148:PF0 155:PF6 162:P84 2: P87 9: P76 16: P94 23:PB6 30: PC3 37: P33 44: P01 51:P11 58: P17 65: P27 72: P44 79: P54 86: P64 93: PJ4 100: PG0 107:PG5 114:PI6 121:PH5 128:PA2 135:PD7 142:PE0 149:PE1 156:PF7 163:P85 3: P70 10: P77 17: P95 24: PB5 31: PC4 38: PC7 45: P05 52:P06 59: P20 66: P40 73: P45 80: P56 87: P60 94: P65 101: PG2 108: PI1 115:PI7 122:PH4 129:PA1 136:PD0 143:PE3 150:PF2 157:PF3 4: P71 11: P92 18:P97 25: PB7 32: PC5 39: P34 46: P00 53:P13 60: P16 67: P26 74: P46 81: P53 88: P63 95: PJ1 102: PG1 109: PI0 116:PI5 123:PH3 130:PA7 137:PD1 144:PE4 151:PF5 158:P80 5: P72 12: P90 19: PB3 26: PB0 33: P31 40:P35 47: P04 54:P12 61: P22 68: P42 75: P47 82: P55 89: P62 96: PJ2 103: PG4 110: PI4 117:PH2 124:PH6 131:PA5 138:PD2 145:PE5 152:PE6 159:P81 6: P73 13: P91 20: PB1 27: PC1 34: PC6 41: P36 48: P03 55: P14 62: P24 69: BOOT 76: P50 83: PJ0 90: P67 97: PJ6 104: PG3 111: PI3 118:PH0 125:PA0 132:PD3 139:PD6 146:PE2 153:PE7 160:P82 7: P74 14: P93 21: PB2 28: PC2 35: P30 42: P02 49: P10 56: P15 63: P25 70: P41 77: P51 84: P57 91: P66 98: PJ7 105:PG6 112:DINT 119:PH1 126:PH7 133:PA6 140:PD4 147:PF1 154:PF4 161:P83 Note: Terminal list to which JTAG can be scanned. JTAG Interface TMP19A44(rev1.3) 23-10 2010-04-01 TMP19A44 23.4 Instructions Supported by the JTAG Controller Cells This section describes the instructions supported by the JTAG controller cells of the TMP19A44. 23.4.1 EXTEST Instruction The EXTEST instruction is used for external interconnect test. If this instruction is issued, the BSR cells at output pins output test patterns in the Update-DR state, and the BSR cells at input pins capture test results in the Capture-DR state. Before the EXTEST instruction is selected, the boundary scan register is usually initialized using the SAMPLE/PRELOAD instruction. If the boundary scan register has not been initialized, there is the possibility that indeterminate data will be transmitted in the Update-DR state and bus conflicts may occur between ICs. Fig. 23-8 shows the flow of data while the EXTEST instruction is selected. Boundary scan path Input Internal logic TDI Output TDO Fig. 23-8 Flow of Data While the EXTEST Instruction Is Selected The basic external interconnect test procedure is as follows: 1. Initialize the TAP controller to put it in the Test-Logic-Reset state. 2. Load the SAMPLE/PRELOAD instruction into the instruction register. This allows the boundary scan register to be connected between TDI and TDO. 3. Initialize the boundary scan register by shifting in determinate data. 4. Load the initial test data into the boundary scan register. 5. Load the EXTEST instruction into the instruction register. 6. Capture the data applied to the input pin and input it into the boundary scan register. 7. Shift out the captured data while simultaneously shifting in the next test pattern. 8. Output to the output pin the test pattern that was shifted into the boundary scan register for output. Repeat steps 6 through 8 for each test pattern. EXTEST Instruction CPU is working and note the terminal input, please when using it. EXTEST InstructionPlease test after releasing system reset when using it. JTAG Interface TMP19A44(rev1.3) 23-11 2010-04-01 TMP19A44 23.4.2 SAMPLE and PRELOAD Instructions The SAMPLE and PRELOAD instructions are used to connect TDI and TDO by way of the boundary scan register. Each instruction performs the function described below: * The SAMPLE instruction is used to monitor the I/O pad of an IC. While SAMPLE is monitoring the I/O pads, the internal logic is not disconnected from the I/O pins of an IC. This instruction is executed in the Capture-DR state. A main function of SAMPLE is to read values of the I/O pins of an IC at the rising edge of TCK during normal functional operation. Fig. 23-9 shows the flow of data while the SAMPLE instruction is selected. Boundary scan path Input Internal logic TDI Output TDO Fig. 23-9 Flow of Data While SAMPLE Is Selected * The PRELOAD instruction is used to initialize the boundary scan register before selecting other instructions. For example, the boundary scan register is initialized using PRELOAD before selecting the EXTEST instruction, as previously explained. PRELOAD shifts data into the boundary scan register without affecting the normal operation of the system logic. Fig. 23-10 shows the flow of data while the PRELOAD instruction is selected. Boundary scan path Input Internal logic TDI Output TDO Fig. 23-10 Flow of Test Data While PRELOAD Is Selected JTAG Interface TMP19A44(rev1.3) 23-12 2010-04-01 TMP19A44 23.4.3 BYPASS Instruction When conducting the type of test in which an IC does not need to be controlled or monitored, the BYPASS instruction is used to form the shortest serial path bypassing an IC by connecting the bypass register between JTDI and JTDO. The BYPASS instruction does not affect the normal operation of the system logic implemented on a chip. Data passes through the bypass register while the BYPASS instruction is selected, as shown in Fig. 23-11. Bypass register TDI TDO 1 bit Fig. 23-11 Flow of Data While the Bypass Register Is Selected 23.5 Points to Note This section describes the points to note regarding JTAG boundary scan operations implemented in this processor. * The X2 and X1 signal pads do not comply with JTAG. * To reset the JTAG circuit, execute either of the following: c Initialize the JTAG circuit by asserting TRST, and then deassert TRST. d Set the TMS pin to "1," and supply TCK with more than 5 clocks. JTAG Interface TMP19A44(rev1.3) 23-13 2010-04-01 TMP19A44 24. Flash Memory Operation This section describes the hardware configuration and operation of the flash memory. 24.1 Flash Memory 24.1.1 Features 1) Memory capacity The TMP19A44F10XBG device contains 8M bits (1024 kB) of flash memory capacity. The memory area consists of 10 independent memory blocks (128 kB x 7, 64 kB x 1 and 32 kB x 2) to enable independent write access to each block. When the CPU is to access the internal flash memory, 32-bit data bus width is used. The TMP19A44FEXBG device contains 6M bits (768 kB) of flash memory capacity. The memory area consists of 8 independent memory blocks (128 kB x 5, 64 kB x 1 and 32 kB x 2). The TMP19A44FDAXBG device contains 4M bits (512 kB) of flash memory capacity. The memory area consists of 6 independent memory blocks (128 kB x 3, 64 kB x 1 and 32 kB x 2). Flash memory access: Interleave access is used in this device. 2) Write/erase time Write time: 0.5 sec/128 Kbyte (Typ.) TMP19A44F10XBG: 4sec (Typ)/ TMP19A44FDAXBG: 2 sec (Typ) Erase: 100 msec/1 block (Typ.) TMP19A44F10XBG: 1sec (Typ)/ TMP19A44FDAXBG: 0.6 sec (Typ) (Note) The above values are theoretical values not including data transfer time. The write time per chip depends on the write method to be used by the user. 3) Programming method The onboard programming mode is available for the user to program (rewrite) the device while it is mounted on the user's board. 4-1) User boot mode The user's original rewriting method can be supported. 4-2) Single boot mode The rewriting method to use serial data transfer (Toshiba's unique method) can be supported. Rewriting method The flash memory included in this device is generally compliant with the applicable JEDEC standards except for some specific functions. Therefore, if the user is currently using an external flash memory device, it is easy to implement the functions into this device. Furthermore, the user is not required to build his/her own programs to realize complicated write and erase functions because such functions are automatically performed using the circuits already built-in the flash memory chip. This device is also implemented with a read-protect function to inhibit reading flash memory data from any external writer device. On the other hand, rewrite protection is available only through commandbased software programming; any hardware setting method to apply +12VDC is not supported. The above described protection function is enabled for each area respectively. When the user removes protection, the internal data is automatically erased before the protection is actually removed. Flash Memory Operation TMP19A44 (rev1.3)24-1 2010-04-01 TMP19A44 JEDEC compliant functions * Automatic programming * Automatic chip erase * Automatic block erase * Data polling/toggle bit 24.1.2 Modified, added, or deleted functions <Modified> Block protect (only software protection is supported) <Deleted> Erase resume - suspend function Automatic multiple block erase (supported to the chip level) Block Diagram of the Flash Memory Section Internal address bus Internal data bus Internal control bus ROM controller/interleave control Control Address Data Flash Memory Command register Address latch Data latch Column decoder/sense amplifier Row decoder Control circuit (includes automatic sequence control) Flash memory cell 1024 KB/ 768KB/ 512 KB Erase block decoder Fig. 24.1 Block Diagram of the Flash Memory Section Flash Memory Operation TMP19A44 (rev1.3)24-2 2010-04-01 TMP19A44 24.2 Operation Mode This device has three operation modes including the mode not to use the internal flash memory. Table 24.1 Operation Modes Operation mode Single chip mode Operation details After reset is cleared, it starts up from the internal flash memory. Normal mode In this operation mode, two different modes, i.e., the mode to execute user application programs and the mode to rewrite the flash memory onboard the user's card, are defined. The former is referred to as "normal mode" and the latter "user boot mode." User boot mode The user can uniquely configure the system to switch between these two modes. For example, the user can freely design the system such that the normal mode is selected when the port "00" is set to "1" and the user boot mode is selected when it is set to "0." The user should prepare a routine as part of the application program to make the decision on the selection of the modes. After reset is cleared, it starts up from the internal Boot ROM (Mask ROM). In the Boot ROM, an algorithm to enable flash memory rewriting on the user's set through the serial port of this device is programmed. By connecting to an external host computer through the serial port, the internal flash memory can be programmed by transferring data in accordance with predefined protocols. Single boot mode Among the flash memory operation modes listed in the above table, the User Boot mode and the Single Boot mode are the programmable modes. These two modes, the User Boot mode and the Single Boot mode, are referred to as "Onboard Programming" modes where onboard rewriting of internal flash memory can be made on the user's card. Flash Memory Operation TMP19A44 (rev1.3)24-3 2010-04-01 TMP19A44 Either the Single Chip or Single Boot operation mode can be selected by externally setting the level of the BOOT input pin while the device is in reset status. After the level is set, the CPU starts operation in the selected operation mode when the reset condition is removed. Regarding the TEST0, TEST1, and BOOT pins, be sure not to change the levels during operation once the mode is selected. The mode setting method and the mode transition diagram are shown below: Table 24.2 Operation Mode Setting Input pin Operation mode Single chip mode Single boot mode RESET BOOT 0 to 1 0 to 1 1 0 Fig. 24.2 Mode Transition Diagram Reset state Single chip mode Normal mode User to set the switch method 24.2.1 User Boot mode Single Boot mode Onboard Programming mode Reset Operation To reset the device, ensure that the power supply voltage is within the operating voltage range, that the internal oscillator has been stabilized, and that the RESET input is held at "0" for a minimum duration of 12 system clocks (1.2 s with 10MHz oscillator operation; the "1/8" clock gear mode is applied after reset). (Note 1) Regarding power-on reset of devices with internal flash memory; For devices with internal flash memory, it is necessary to apply "0" to the RESET inputs upon power on for a minimum duration of 500 microseconds regardless of the operating frequency. (Note 2) While flash programming or deletion is in progress, at least 0.5 microseconds of reset period is required regardless of the system clock frequency. Flash Memory Operation TMP19A44 (rev1.3)24-4 2010-04-01 TMP19A44 24.2.2 User Boot mode(Single chip mode) User Boot mode is to use flash memory programming routine defined by users. It is used when the data transfer buses for flash memory program code on the old application and for serial I/O are different. It operates at the single chip mode; therefore, a switch from normal mode in which user application is activated at the single chip mode to User Boot Mode for programming flash is required. Specifically, add a mode judgment routine to a reset program in the old application. The condition to switch the modes needs to be set by using the I/O of 19A44 in conformity with the user's system setup condition. Also, flash memory programming routine that the user uniquely makes up needs to be set in the new application. This routine is used for programming after being switched to User Boot Mode. The execution of the programming routine must take place while it is stored in the area other than the flash memory since the data in the internal flash memory cannot be read out during delete/ writing mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental writing/ erasing during subsequent Single-Chip (Normal mode) operations. All the interruption including a non-maskable are inhibited at User Boot Mode. (1-A) and (1-B) are the examples of programming with routines in the internal flash memory and in the external memory. For a detailed description of the erase and program sequence, refer to "On-board Programming of Flash Memory (Rewrite/Erase)". Flash Memory Operation TMP19A44 (rev1.3)24-5 2010-04-01 TMP19A44 User Boot Mode (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1) Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMP19A44F on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. * Mode judgment routine: Code to determine whether or not to switch to User Boot mode * Programming routine: Code to download new program code from a host controller and reprogram the flash memory * Copy routine: Code to copy the flash programming routine from the TMP19A44F flash memory to either the TMP19A44F on-chip RAM or external memory device. Host Controller New Application Program Code I/O TMP19A44F Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy Routine (2) After RESET is released, the reset procedure determines whether to put the TMP19A44F flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be globally disabled while in User Boot mode.) Host Controller TMP19A44F New Application Program Code I/O 0 1 RESET Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine (c) Copy Routine Flash Memory Operation RAM TMP19A44 (rev1.3)24-6 Conditions for entering User Boot mode (defined by the user) 2010-04-01 TMP19A44 (3) Once User Boot mode is entered, execute the copy routine to copy the flash programming routine to either the TMP19A44F on-chip RAM. Host Controller New Application Program Code I/O TMP19A44F Flash Memory Old Application Program Code [Reset Procedure] (b) Programming Routine (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy Routine (4) Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block after releasing the protection for accidental writing/ erasing of the old application program code. Host Controller New Application Program Code I/O TMP19A44F Flash Memory Erased [Reset Procedure] (b) Programming Routine (a) Mode Judgment Routine (b) Programming Routine (c) Copy Routine Flash Memory Operation RAM TMP19A44 (rev1.3)24-7 2010-04-01 TMP19A44 (5) Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. Once programming is complete, turn on the protection for writing/ erasing of that flash block. Host Controller New Application Program Code I/O TMP19A44F Flash Memory New Application Program Code [Reset Procedure] (b) Programming Routine (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy Routine (6) Drive RESET low to reset the TMP19A44F. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. Host Controller (I/O) TMP19A44F Flash Memory 0 1 RESET New Application Program Code e [Reset Procedure] Set to Normal mode (a) Mode Judgment Routine (b) Programming Routine (c) Copy Routine Flash Memory Operation RAM TMP19A44 (rev1.3)24-8 2010-04-01 TMP19A44 (1-B) Method 2: Transferring a Programming Routine from an External Host (1) Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMP19A44F on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. Mode judgment routine: Code to determine whether or not to switch to User Boot mode Transfer routine: Code to download new program code from a host controller Also, prepare a programming routine on the host controller: Programming routine: flash memory Code to download new program code from an external host controller and re-program the Host Controller New Application Program Code I/O (c) Programming Routine TMP19A44F Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine (2) After RESET is released, the reset procedure determines whether to put the TMP19A44F flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be globally disabled while in User Boot mode.) Host Controller I/O New Application Program Code (c) Programming Routine TMP19A44F 0 1 RESET Flash Memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine RAM Conditions for entering User Boot mode (defined by the user) (b) Transfer Routine Flash Memory Operation TMP19A44 (rev1.3)24-9 2010-04-01 TMP19A44 (3) Once User Boot mode is entered, execute the transfer routine to download the flash programming routine from the host controller to the TMP19A44F on-chip RAM. Host Controller New Application Program Code I/O (c) Programming Routine TMP19A44F Flash Memory Old Application Program Code (c) Programming routine [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine (4) Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block after releasing the protection for accidental writing/ erasing of the old application program code. Host Controller New Application Program Code I/O (c) Programming Routine TMP19A44F Flash Memory Erased (c) Programming Routine [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine Flash Memory Operation TMP19A44 (rev1.3)24-10 2010-04-01 TMP19A44 (5) Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. Once programming is complete, turn on the protection for writing/ erasing of that flash block. Host Controller New Application Program Code I/O (c) Programming Routine TMP19A44F Flash Memory New Application Program Code (c) Programming Routine [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine Drive RESET low to reset the TMP19A44F. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. Host Controller I/O TMP19A44F 0 1 RESET Flash Memory New Application Program Code Set to Normal mode [Reset Procedure] (a) Mode Judgment Routine RAM (b) Transfer Routine Flash Memory Operation TMP19A44 (rev1.3)24-11 2010-04-01 TMP19A44 24.2.3 Single Boot Mode In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMP19A44F on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it. Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the TMP19A44F is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMP19A44F on-chip RAM. Then, the flash memory is reprogrammed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO0 and the host must follow the protocol described later. To secure the contents of the flash memory, the validity of the application's password is checked before a programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the non-maskable (NMI) interrupt must be globally disabled in Single Boot mode while the flash memory is being erased or programmed. In Single Boot mode, the boot-ROM programs are executed in Normal mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental writing/ erasing during subsequent Single-Chip (Normal mode) operations. For a detailed description of the erase and program sequence, refer to On-Board Programming and Erasure. Flash Memory Operation TMP19A44 (rev1.3)24-12 2010-04-01 TMP19A44 Boot Mode (2-A) General Procedure: Using the Program in the On-Chip Boot ROM (1) The flash block containing the older version of the program code need not be erased before executing the programming routine. Since a programming routine and programming data are transferred via the SIO0, the SIO0 must be connected to a host controller. Prepare a programming routine on the host controller. Host Controller New Application Program Code I/O (a) Programming Routine TMP19A44F Boot ROM SIO0 Flash Memory Old Application Program Code (or Erased State) RAM (2) Reset the TMP19A44F with the mode setting pins held at appropriate logic values, so that the CPU re-boots from the on-chip boot ROM. The 12-byte password transferred from the host controller is first compared to the contents of special flash memory locations. (If the flash block has already been erased, the password is 0xFFFF.) Host Controller I/O New Application Program Code (a) Programming Routine TMP19A44F 0 1 RESET Boot ROM SIO0 Flash Memory 0 BOOT Old Application Program Code (or Erased State) RAM Flash Memory Operation TMP19A44 (rev1.3)24-13 2010-04-01 TMP19A44 (3) If the password was correct, the boot program downloads, via the SIO0, the programming routine from the host controller into the on-chip RAM of the TMP19A44F. The programming routine must be stored in the address range 0xFFFD_A400 - 0xFFFD_FFFF. Host Controller New Application Program Code I/O (a) Programming routine TMP19A44F Boot ROM SIO0 Flash Memory (a) Programming Routine Old Application Program Code (or Erased State) RAM (4) The CPU jumps to the programming routine in the on-chip RAM to erase the flash block containing the old application program code. The Block Erase or Chip Erase command may be used. Host Controller New Application Program Code I/O (a) Programming routine TMP19A44F Boot ROM SIO0 Flash Memory (a) Programming Routine Erased RAM Flash Memory Operation TMP19A44 (rev1.3)24-14 2010-04-01 TMP19A44 (5) Next, the programming routine downloads new application program code from the host controller and programs it into the erased flash block. Once programming is complete, protection for writing/ erasing of that flash block is turned on. It is not allowed to move program control from the programming routine back to the boot ROM. In the example below, new program code comes from the same host controller via the same SIO channel as for the programming routine. However, once the programming routine has begun to execute, it is free to change the transfer path and the source of the transfer. Create board hardware and a programming routine to suit your particular needs. Host Controller New Application Program Code I/O (a) Programming Routine TMP19A44F Boot ROM SIO0 Flash Memory (a) Programming Routine New Application Program Code RAM (6) When programming of the flash memory is complete, power off the board and disconnect the cable leading from the host to the target board. Turn on the power again so that the TMP19A44F re-boots in Single-Chip (Normal) mode to execute the new program. Host Controller TMP19A44F 0 1 RESET Boot ROM SIO0 Flash Memory Set to Single-Chip mode ( BOOT =1). New Application Program Code RAM Flash Memory Operation TMP19A44 (rev1.3)24-15 2010-04-01 TMP19A44 (1) Mode Setting For on-board programming, boot the TMP19A44F in Single Boot mode, as follows: BOOT = 0 RESET = 0 1 Set the RESET input at logic 0, and the BOOT input at the logic values shown above, and then release RESET (high). (2) Memory Map Fig. 24.3 shows a comparison of the memory maps in Normal and Single Boot modes. In single Boot mode, the on-chip flash memory is mapped to physical addresses (0x000_0000 through 0x4007_FFFF), virtual addresses (0x0000_0000 through 0x0007_FFFF), and the on-chip boot ROM is mapped to physical addresses 0x1FC0_0000 through 0x1FC0_0FFF. Normal Mode On-Chip RAM (24 KB) Single Boot Mode 0xFFFF_FFFF On-Chip RAM (24 KB) (Reserved) (Reserved) On-Chip RAM (8 KB) On-Chip RAM (8 KB) (Reserved) (Reserved) On-Chip ROM Shadow 0xFFFF_FFFF 0xBFC7_FFFF 0x4007_FFFF On-Chip Flash 0x4000_0000 ROM (Reserved) 0xBFC0_0000 0x1FC7_FFFF 0x1FC0_0FFF User Program Area 0x1FC0_0500 Maskable Interrupt Area Exception Vector Area (Reserved) Boot ROM (8KB) 0x1FC0_0000 0x0007_FFFF 0x1FC0_0000 On-Chip Flash ROM 0x0000_0000 0x0000_0000 Fig. 24.3 Memory Maps for Normal and Single Boot Modes (Physical Addresses) Flash Memory Operation TMP19A44 (rev1.3)24-16 2010-04-01 TMP19A44 (3) Interface Specification In Single Boot mode, an SIO channel is used for communications with a programming controller. Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. The communication formats are shown below. In the subsections that follow, virtual addresses are indicated, unless otherwise noted. * UART mode Communication channel: Transfer mode: Data length: Parity bits: STOP bits: Baud rate: * SIO Channel 0 (SIO0) UART (asynchronous) mode, half-duplex, LSB first 8 bits None 1 Arbitrary baud rate I/O Interface mode Communication channel: SIO Channel 0 (SIO0) Transfer mode: I/O Interface mode, full-duplex, LSB first Synchronization clock (SCLK0): Input mode Handshaking signal: P63 output mode Baud rate: Arbitrary baud rate Table 24.3 Required Pin Connections Interface Pin UART Mode I/O Interface Mode DVCC3 Required Required DVSS Required Required Mode-Setting Pin BOOT Required Required Reset Pin RESET Required Required Communication Pins TXD0 (P60) Required Required RXD0 (P61) Required Required SCLK0 (P62) Not Required Required (Input Mode) P63 Not Required Required (OUTPUT Mode) Power Supply Pins (4) Data Transfer Format The host controller is to issue one of the commands listed in Table 24.4 to the target board. Table 24.6 illustrate the sequence of two-way communications that should occur in response to each command. Table 24.4 Single Boot Mode Commands Code 10H Flash Memory Operation Command RAM Transfer TMP19A44 (rev1.3)24-17 2010-04-01 TMP19A44 (5) Restrictions on internal memories Single Boot Mode places restrictions on the internal RAM and ROM as shown in Table 24.5 Restrictions in Single Boot Mode. Table 24.5 Restrictions in Single Boot Mode Memory Details Internal RAM BOOT ROM is mapped to 0xFFFF_A000 to 0xFFFF_A3FF. Store the RAM transfer program in 0xFFFF_A4000xFFFF_FFFF. Internal ROM 0x0000_0470 to 0x0000_047F are assigned for storing software ID information and passwords. Storing program in these addresses is not recommendable. Flash Memory Operation TMP19A44 (rev1.3)24-18 2010-04-01 TMP19A44 Table 24.6 Transfer Format for the RAM Transfer Command Byte Boot ROM 1st byte Data Transferred from the Controller to the TMP19A44 Serial operation mode and baud rate For UART mode 86H For I/O Interface mode 30H Baud Rate Desired baud rate (Note 1) 2nd byte Data Transferred from the TMP19A44 to the Controller ACK for the serial operation mode byte For UART mode Normal acknowledge 86H (The boot program aborts if the baud rate is can not be set correctly.) For I/O Interface mode Normal acknowledge 3rd byte Command code 4th byte 5th byte 30H (10H) ACK for the command code byte (Note 2) Normal acknowledge 10H Negative acknowledge x1H Communication error x8H Password sequence (12 bytes) thru 16th byte 17th byte (0x3F8F_FFF4 thru 0x3F8F_FFFF) Checksum value for bytes 5-16 18th byte ACK for the checksum byte (Note 2) Normal acknowledge 10H Negative acknowledge x1H Communication error x8H 19th byte RAM storage start address (bits 31-24) 20th byte RAM storage start address (bits 23-16) 21st byte RAM storage start address (bits 15-8) 22nd byte RAM storage start address (bits 7-0) 23rd byte RAM storage byte count (bits 15-8) 24th byte RAM storage byte count (bits 7-0) 25th byte Checksum value for bytes 19-24 26th byte 27th byte ACK for the checksum byte (Note 2) Normal acknowledge 10H Negative acknowledge x1H Communication error x8H RAM storage data thru mth byte (m + 1)th byte RAM Checksum value for bytes 27-m (m + 2)th byte (m + 3)th byte ACK for the checksum byte (Note 2) Normal acknowledge 10H Non-acknowledge x1H Communications error x8H Jump to RAM storage start address Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Note 3: The 19th to 25th bytes must be within the RAM address range 0xFFFF_A400-0xFFFF_FFFF . Flash Memory Operation TMP19A44 (rev1.3)24-19 2010-04-01 TMP19A44 (6) Overview of the Boot Program Commands When Single Boot mode is selected, the boot program is automatically executed on startup. The boot program offers these four commands, the details of which are provided on the subsections 1) through 4). 1. RAM Transfer command The RAM Transfer command stores program code transferred from a host controller to the onchip RAM and executes the program once the transfer is successfully completed. The maximum program size is 24 Kbytes. The RAM storage start address must be within the range. The RAM Transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. The programming routine must utilize the flash memory command sequences described in Section 24.3. Before initiating a transfer, the RAM Transfer command checks a password sequence coming from the controller against that stored in the flash memory. If they do not match, the RAM Transfer command aborts. Once the RAM Transfer command is complete, the whole on-chip RAM is accessible. 1) RAM Transfer Command (see Table 24.6) 1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed description of how the serial operation mode is determined, see Section 0. If it is determined as UART mode, the boot program then checks if the SIO0 is programmable to the baud rate at which the 1st byte was transferred. During the first-byte interval, the RXE bit in the SC0MOD0 register is cleared. * To communicate in UART mode Send, from the controller to the target board, 86H in UART data format at the desired baud rate. If the serial operation mode is determined as UART, then the boot program checks if the SIO0 can be programmed to the baud rate at which the first byte was transferred. If that baud rate is not possible, the boot program aborts, disabling any subsequent communications. * To communicate in I/O Interface mode Send, from the controller to the target board, 30H in I/O Interface data format at 1/16 of the desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent bytes at a rate equal to the desired baud rate. In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port in monitoring its logic transitions. If the baud rate of the incoming data is high or the chip's operating frequency is high, the CPU may not be able to keep up with the speed of logic transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the boot program does not check the receive error flag; thus there is no such thing as error acknowledge (x8H). Flash Memory Operation TMP19A44 (rev1.3)24-20 2010-04-01 TMP19A44 2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. The boot program echoes back the first byte: 86H for UART mode and 30H for I/O Interface mode. * UART mode If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the boot program programs the SC0BRCR and sends back 86H to the controller as an acknowledge. If the SIO0 is not programmable at that baud rate, the boot program simply aborts with no error indication. Following the 1st byte, the controller should allow for a time-out period of five seconds. If it does not receive 86H within the allowed time-out period, the controller should give up the communication. The boot program sets the RXE bit in the SC0MOD0 register to enable reception before loading the SIO transmit buffer with 86H. * I/O Interface mode The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O Interface mode (clocked by the rising edge of SCLK0), writes 30H to the SC0BUF. Then, the SIO0 waits for the SCLK0 signal to come from the controller. Following the transmission of the 1st byte, the controller should send the SCLK clock to the target board after a certain idle time (several microseconds). This must be done at 1/16 the desire baud rate. If the 2nd byte, which is from the target board to the controller, is 30H, then the controller should take it as a go-ahead. The controller must then deliver the 3rd byte to the target board at a rate equal to the desired baud rate. The boot program sets the RXE bit in the SC0MOD0 register to enable reception before loading the SIO transmit buffer with 30H. 3. The 3rd byte, which the target board receives from the controller, is a command. The code for the RAM Transfer command is 10H. 4. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits x8H and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined -- they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 24.4, the boot program echoes it back to the controller. When the RAM Transfer command was received, the boot program echoes back a value of 10H and then branches to the RAM Transfer routine. Once this branch is taken, a password check is done. Password checking is detailed in Section "Password". If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined -- they hold the same values as the upper four bits of the previously issued command. 5. The 5th to 16th bytes, which the target board receives from the controller, are a 12-byte password. The 5th byte is compared to the contents of address 0x0000_0474 in the flash memory; the 6th byte is compared to the contents of address 0x0000_0475 in the flash memory; likewise, the 16th byte is compared to the contents of address 0x0000_047F in the flash memory. If the password checking fails, the RAM Transfer routine sets the password error flag. Flash Memory Operation TMP19A44 (rev1.3)24-21 2010-04-01 TMP19A44 6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the two's complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in Section "Checksum Calculation". 7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th bytes. If there was a receive error, the boot program sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 5th to 16th bytes must result in zero (with the carry dropped). If it is not zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. Finally, the RAM Transfer routine examines the result of the password check. The following two cases are treated as a password error. In these cases, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. * Irrespective of the result of the password comparison, all of the 12 bytes of a password in the flash memory are the same value other than FFH. * Not the entire password bytes transmitted from the controller matched those contained in the flash memory. When all the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. 8. The 19th to 22nd bytes, which the target board receives from the controller, indicate the start address of the RAM region where subsequent data (e.g., a flash programming routine) should be stored. The 19th byte corresponds to bits 31-24 of the address, and the 22nd byte corresponds to bits 7-0 of the address. 9. The 23rd and 24th bytes, which the target board receives from the controller, indicate the number of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte corresponds to bits 15-8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7-0 of the number of bytes. 10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add all these bytes together, drop the carries and take the two's complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in Section. 11. The 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the Flash Memory Operation TMP19A44 (rev1.3)24-22 2010-04-01 TMP19A44 series of the 19th to 24th bytes must result in zero (with the carry dropped). If it is not zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. The RAM storage start address must be within the range 0xFFFF_A400-0xFFFF_FFFF. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. 12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMP19A44. Storage begins at the address specified by the 19th-22nd bytes and continues for the number of bytes specified by the 23rd-24th bytes. 13. The (m+1)th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes together, drop the carries and take the two's complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in Section "Checksum Calculation ". 14. The (m+2)th byte is a acknowledge response to the 27th to (m+1)th bytes. First, the RAM Transfer routine checks for a receive error in the 27th to (m+1)th bytes. If there was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 27th to (m)th bytes must result in zero (with the carry dropped). If it is not zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. 15. If the (m+2)th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes in 32-bit ISA mode. Flash Memory Operation TMP19A44 (rev1.3)24-23 2010-04-01 TMP19A44 7) Acknowledge Responses The boot program represents processing states with specific codes. Table 24.7 to Table 24.14 show the values of possible acknowledge responses to the received data. The upper four bits of the acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1 and bit 2 are always 0. Receive error checking is not done in I/O Interface mode. Table 24.7 ACK Response to the Serial Operation Mode Byte Return Value Meaning 0x86 The SIO can be configured to operate in UART mode. (See Note) 0x30 The SIO can be configured to operate in I/O Interface mode. Note: If the serial operation mode is determined as UART, the boot program checks if the SIO can be programmed to the baud rate at which the operation mode byte was transferred. If that baud rate is not possible, the boot program aborts, without sending back any response. Table 24.8 ACK Response to the Command Byte Return Value 0x?8 (See Note) Meaning A receive error occurred while getting a command code. 0x?1 (See Note) An undefined command code was received. (Reception was completed normally.) 0x10 The RAM Transfer command was received. Note: The upper four bits of the ACK response are the same as those of the previous command code. Flash Memory Operation TMP19A44 (rev1.3)24-24 2010-04-01 TMP19A44 8) Determination of a Serial Operation Mode The first byte from the controller determines the serial operation mode. To use UART mode for communications between the controller and the target board, the controller must first send a value of 86H at a desired baud rate to the target board. To use I/O Interface mode, the controller must send a value of 30H at 1/16 the desired baud rate. Fig. 24.4 shows the waveforms for the first byte. Start Point A bit 0 bit 1 Point B bit 2 bit 3 Point C bit 4 bit 5 bit 6 bit 7 Point D Stop UART (86H) tAB bit 0 Point A bit 1 tCD bit 2 bit 3 bit 4 Point B bit 5 bit 6 Point C bit 7 Point D I/O Interface (30H) tAB tCD Fig. 24.4 Serial Operation Mode Byte After RESET is released, the boot program monitors the first serial byte from the controller, with the SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Fig. 24.5 shows a flowchart describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot program captures timer counts each time a logic transition occurs in the first serial byte. Consequently, the calculated tAB, tAC and tAD intervals are bound to have slight errors. If the transfer goes at a high baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive pin. In particular, I/O Interface mode is more prone to this problem since its baud rate is generally much higher than that for UART mode. To avoid such a situation, the controller should send the first serial byte at 1/16 the desired baud rate. The flowchart in Fig. 24.6 shows how the boot program distinguishes between UART and I/O Interface modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is determined as UART mode. If the length of tAB is greater than the length of tCD, the serial operation mode is determined as I/O Interface mode. Bear in mind that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. This becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. To prevent this problem, reset UART mode within the programming routine. For example, the serial operation mode may be determined to be I/O Interface mode when the intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should allow for a time-out period within which it expects to receive an echo-back (86H) from the target board. The controller should give up the communication if it fails to get that echo-back within the allowed time. When I/O Interface mode is utilized, once the first serial byte has been transmitted, the controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowledge response is not 30H, the controller should give up further communications. When the intended mode is I/O interface mode, the first byte does not have to be 0x30 as long as tAB is greater than tCD as shown above. 0x91, 0xA1 or 0xB1 can be sent as the first byte code to determine the falling edges of Point A and Point C and the rising edges of Point B and Point D. If tAB is greater than tCD and SIO is selected by the resolution of the operation mode determination, the second byte code is 0x30 even though the transmitted code on the first byte is not 0x30 (The first byte code to determine I/O interface mode is described as 0x30). Flash Memory Operation TMP19A44 (rev1.3)24-25 2010-04-01 TMP19A44 Start Initialize 16-bit Timer 0 (T1 = 16/fc, counter cleared) Set TB0RG1 to 0xFFFF Prescaler is on. High-to-low transition on serial receive pin? Point A Yes 16-bit Timer 0 starts counting up Low-to-high transition on serial receive pin? Point B Yes Software-capture and save timer value (tAB) High-to-low transition on serial receive pin? Point C Yes Software-capture and save timer value (tAC) Low-to-high transition on serial receive pin? Point D Yes Software-capture and save timer value (tAD) 16-bit Timer 0 stops counting tAC tAD? Yes Make backup copy of tAD value Done Stop operation (infinite loop) Fig. 24.5 Serial Operation Mode Byte Reception Flow Flash Memory Operation TMP19A44 (rev1.3)24-26 2010-04-01 TMP19A44 Start tCD tAD - tAC tAB > tCD? Yes UART Mode I/O Interface Mode Fig. 24.6 Serial Operation Mode Determination Flow 9) Password The RAM Transfer command (10H) causes the boot program to perform a password check. Following an echo-back of the command code, the boot program checks the contents of the 12-byte password area (0x0000_0474 to 0x0000_047F) within the flash memory. If all these address locations contain the same bytes of data other than FFH, a password area error occurs. In this case, the boot program returns an error acknowledge (11H) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all FFHs. The password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. All of the 12 bytes must match to pass the password check. Otherwise, a password error occurs, which causes the boot program to return an error acknowledge in response to the checksum byte (the 17th byte). The password check is performed even if the security function is enabled. Start Are all bytes the same? No Yes Are all bytes equal to FFH? Yes No Password area error Password area is normal. Fig. 24.7 Password Area Check Flow Flash Memory Operation TMP19A44 (rev1.3)24-27 2010-04-01 TMP19A44 10) General Boot Program Flowchart Fig. 24.8 shows an overall flowchart of the boot program. Single Boot program starts Initialize Get SIO operation mode SIO operation mode? UART I/O interface Baud rate setting ? Cannot be set Can be set Set I/O interface mode Program UART mode and baud rate ACK data received data (30H) ACK data received data (86H@UART) (Send 30H) Normal response (Send 86H) Normal response Stop operation Prepare to get a command ACK data ACK data & 0xF0 Receive routine Get a command Receive error ? Yes ACK data ACK data 0x08 Transmission routine (Sendx8H:receive error) No normally RAM transfer? YES (10H) ACK data Received data (10H) Transmission routine (Send 10H: normal response) RAM transfer processing Processed normally? Yes normally Jump to RAM Fig. 24.8 Overall Boot Program Flow Flash Memory Operation TMP19A44 (rev1.3)24-28 2010-04-01 TMP19A44 24.3 On-board Programming of Flash Memory (Rewrite/Erase) In on-board programming, the CPU is to execute software commands for rewriting or erasing the flash memory. The rewrite/erase control program should be prepared by the user beforehand. Because the flash memory content cannot be read while it is being written or erased, it is necessary to run the rewrite/erase program from the internal RAM or from an external memory device after shifting to the user boot mode. In this section, flash memory addresses are represented in virtual addresses unless otherwise noted. 24.3.1 Flash Memory Except for some functions, writing and erasing flash memory data are in accordance with the standard JEDEC commands. In writing or erasing, use the SW command of the CPU to enter commands to the flash memory. Once the command is entered, the actual write or erase operation is automatically performed internally. Table 24.9 Flash Memory Functions Major functions Description Automatic page program Automatic chip erase Automatic block erase Write protect Writes data automatically. Erases the entire area of the flash memory automatically. Erases a selected block automatically. The write or erase function can be individually inhibited for each block. When all blocks are set for protection, the entire protection function is automatically enabled. By writing a 4-bit protection code, the write or erase function can be individually inhibited for each area. Protect function Note that addressing of operation commands is different from the case of standard commands due to the specific interface arrangements with the CPU. Also note that the flash memory is written in 32-bit blocks. So, 32-bit (word) data transfer commands must be used in writing the flash memory. (1) Block configuration 32 K 0xBFC0_0000 32 K 64 K 128 K 19A44FDA 128 K 19A44FE 19A44F10 128 K 0xBFC7_FFFF 0xBFCB_FFFF 128 K 128 K 128 K 128 K 0xBFCF_FFFF 128 words | x 256 128 words Fig. 24.9 Block Configuration of Flash Memory Flash Memory Operation TMP19A44 (rev1.3)24-29 2010-04-01 TMP19A44 (2) Basic operation Generally speaking, this flash memory device has the following two operation modes: The mode to read memory data (Read mode) The mode to automatically erase or rewrite memory data (Automatic operation) Transition to the automatic mode is made by executing a command sequence while it is in the memory read mode. In the automatic operation mode, flash memory data cannot be read and any commands stored in the flash memory cannot be executed. In the automatic operation mode, any interrupt or exception generation cannot set the device to the read mode except when a hardware reset is generated. During automatic operation, be sure not to cause any exceptions other than debug exceptions and reset while a DSU probe is connected. Any interrupt or exception generation cannot set the device to the read mode except when a hardware reset is generated. 1) Read When data is to be read, the flash memory must be set to the read mode. The flash memory will be set to the read mode immediately after power is applied, when CPU reset is removed, or when an automatic operation is normally terminated. In order to return to the read mode from other modes or after an automatic operation has been abnormally terminated, either the Read/reset command (a software command to be described later) or a hardware reset is used. The device must also be in the read mode when any command written on the flash memory is to be executed. Read/reset command and Read command (software reset) When an automatic operation is abnormally terminated, the flash memory cannot return to the read mode by itself (When FLCS<FlashBusy> = 0, data read from the flash memory is undefined.) In this case, the Read/reset command can be used to return the flash memory to the read mode. Also, when a command that has not been completely written has to be canceled, the Read/reset command must be used to return to the read mode. The Read command is used to return to the read mode after executing the SW command to write the data "0x0000_00F0" to an arbitrary address of the flash memory. With the Read/reset command, the device is returned to the read mode after completing the third bus write cycle. 2) Command write This flash memory uses the command control method. Commands are executed by executing a command sequence to the flash memory. The flash memory executes automatic operation commands according to the address and data combinations applied (refer to Command Sequence). If it is desired to cancel a command write operation already in progress or when any incorrect command sequence has been entered, the Read/reset command is to be executed. Then, the flash memory will terminate the command execution and return to the read mode. While commands are generally comprised of several bus cycles, the operation to apply the SW command to the flash memory is called "bus write cycle." The bus write cycles are to be in a specific sequential order and the flash memory will perform an automatic operation when the sequence of the bus write cycle data and address of a command write operation is in accordance with a predefined specific sequence. If any bus write cycle does not follow a predefined command write sequence, the flash memory will terminate the command execution and return to the read mode. The address [31:20] in each bus write cycle should be the virtual address [31:20] of command execution. It will be explained later for the address bits [19:8]. Flash Memory Operation TMP19A44 (rev1.3)24-30 2010-04-01 TMP19A44 (Note 1) Command sequences are executed from outside the flash memory area. (Note 2) The interval between bus write cycles for this device must be 15 system clock cycles or longer. The command sequencer in the flash memory device requires a certain time period to recognize a bus write cycle. If more than one bus write cycles are executed within this time period, normal operation cannot be expected. For adjusting the applicable bus write cycle interval using a software timer to be operated at the operating frequency, use the section 10) "ID-Read" to check for the appropriateness. (Note 3) Between the bus write cycles, never use any load command (such as LW, LH, or LB) to the flash memory or perform a DMA transmission by specifying the flash area as the source address. Also, don't execute a Jump command to the flash memory. While a command sequence is being executed, don't generate any interrupt such as maskable interrupts (except debug exceptions when a DSU probe is connected). If such an operation is made, it can result in an unexpected read access to the flash memory and the command sequencer may not be able to correctly recognize the command. While it could cause an abnormal termination of the command sequence, it is also possible that the written command is incorrectly recognized. (Note 4) The SYNC command must be executed immediately after the SW command for each bus write cycle. (Note 5) For the command sequencer to recognize a command, the device must be in the read mode prior to executing the command. Be sure to check before the first bus write cycle that the FLCS[0]R <FlashBusy> bit is set to "1." It is recommended to subsequently execute a Read command. (Note 6) Upon issuing a command, if any address or data is incorrectly written, be sure to perform a system reset operation or issue a reset command to return to the read mode again. 3) Reset Hardware reset The flash memory has a reset input as the memory block and it is connected to the CPU reset signal. Therefore, when the RESET input pin of this device is set to VIL or when the CPU is reset due to any overflow of the watch dog timer, the flash memory will return to the read mode terminating any automatic operation that may be in progress. The CPU reset is also used in returning to the read mode when an automatic operation is abnormally terminated or when any mode set by a command is to be canceled. It should also be noted that applying a hardware reset during an automatic operation can result in incorrect rewriting of data. In such a case, be sure to perform the rewriting again. Refer to Section 24.2.1 "Reset Operation" for CPU reset operations. After a given reset input, the CPU will read the reset vector data from the flash memory and starts operation after the reset is removed. 4) Automatic Page Programming Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is necessary to perform an erase operation. The automatic page programming function of this device writes data in 128 word blocks. A 128 word block is defined by a same [31:9] address and it starts from the address [8:0] = 0 and ends at the address [8:0] = 0x1FF. This programming unit is hereafter referred to as a "page." Flash Memory Operation TMP19A44 (rev1.3)24-31 2010-04-01 TMP19A44 Writing to data cells is automatically performed by an internal sequencer and no external control by the CPU is required. The state of automatic page programming (whether it is in writing operation or not) can be checked by the FLCS [0] <FlashBusy> register. Also, any new command sequence is not accepted while it is in the automatic page programming mode. If it is desired to interrupt the automatic page programming, use the hardware reset function. If the operation is stopped by a hardware reset operation, it is necessary to once erase the page and then perform the automatic page programming again because writing to the page has not been normally terminated. The automatic page programming operation is allowed only once for a page already erased. No programming can be performed twice or more times irrespective of the data cell value whether it is "1" or "0." Note that rewriting to a page that has been once written requires execution of the automatic block erase or automatic chip erase command before executing the automatic page programming command again. Note that an attempt to rewrite a page two or more times without erasing the content can cause damages to the device. No automatic verify operation is performed internally to the device. So, be sure to read the data programmed to confirm that it has been correctly written. The automatic page programming operation starts when the fourth bus write cycle of the command cycle is completed. On and after the fifth bus write cycle, data will be written sequentially starting from the next address of the address specified in the fourth bus write cycle (in the fourth bus write cycle, the page top address will be command written) (32 bits of data is input at a time). Be sure to use the SW command in writing commands on and after the fourth bus cycle. In this, any SW command shall not be placed across word boundary. On and after the fifth bus write cycle, data is command written to the same page area. Even if it is desired to write the page only partially, it is required to perform the automatic page programming for the entire page. In this case, the address input for the fourth bus write cycle shall be set to the top address of the page. Be sure to perform command write operation with the input data set to "1" for the data cells not to be set to "0." For example, if the top address of a page is not to be written, set the input data of the fourth bus write cycle to 0xFFFFFFFF to command write the data. Once the fourth bus cycle is executed, it is in the automatic programming operation. This condition can be checked by monitoring the register bit FLCS [0] <FlashBusy> (SeeTable 24.10). Any new command sequence is not accepted while it is in automatic page programming mode. If it is desired to stop operation, use the hardware reset function. Be careful in doing so because data cannot be written normally if the operation is interrupted. When a single page has been command written normally terminating the automatic page writing process, the FLCS [0] <FlashBusy> bit is set to "1" and it returns to the read mode. When multiple pages are to be written, it is necessary to execute the page programming command for each page because the number of pages to be written by a single execution of the automatic page program command is limited to only one page. It is not allowed for automatic page programming to process input data across pages. Data cannot be written to a protected block. When automatic programming is finished, it automatically returns to the read mode. This condition can be checked by monitoring FLCS [0] <FlashBusy> (See Table 24.10). If automatic programming has failed, the flash memory is locked in the mode and will not return to the read mode. For returning to the read mode, it is necessary to use the reset command or hardware reset to reset the flash memory or the device. In this case, while writing to the address has failed, it is recommended not to use the device or not to use the block that includes the failed address. Flash Memory Operation TMP19A44 (rev1.3)24-32 2010-04-01 TMP19A44 Note: Software reset becomes ineffective in bus write cycles on and after the fourth bus write cycle of the automatic page programming command. 5) Automatic chip erase The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is completed. This condition can be checked by monitoring FLCS [0] <FlashBusy> (See Table 24.10). While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. Any new command sequence is not accepted while it is in an automatic chip erase operation. If it is desired to stop operation, use the hardware reset function. If the operation is forced to stop, it is necessary to perform the automatic chip erase operation again because the data erasing operation has not been normally terminated. Also, any protected blocks cannot be erased. If all the protected blocks are protected, the automatic chip erase operation will not be performed and it returns to the read mode after completing the sixth bus read cycle of the command sequence. When an automatic chip erase operation is normally terminated, it automatically returns to the read mode. If an automatic chip erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. For returning to the read mode, it is necessary to use the reset command or hardware reset to reset the flash memory or the device. In this case, the failed block cannot be detected. It is recommended not to use the device anymore or to identify the failed block by using the block erase function for not to use the identified block anymore. 6) Automatic block erase (one block at a time) The automatic block erase operation starts when the sixth bus write cycle of the command cycle is completed. This status of the automatic block erase operation can be checked by monitoring FLCS [0] <FlashBusy> (See Table 24.10). While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. Any new command sequence is not accepted while it is in an automatic block erase operation. If it is desired to stop operation, use the hardware reset function. In this case, it is necessary to perform the automatic block erase operation again because the data erasing operation has not been normally terminated. Also, any protected blocks cannot be erased. If an automatic block erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. In this case, use the reset command or hardware reset to reset the flash memory or the device. 7) Automatic programming of protection bits This device is implemented with four protection bits. The protection bits can be individually set in the automatic programming. The applicable protection bit is specified in the seventh bus write cycle. By automatically programming the protection bits, write and/or erase functions can be inhibited (for protection) individually for each area. The protection status of each area can be checked by the FLCS <PROTECT 3:0> register to be described later. This status of the automatic programming operation to set protection bits can be checked by monitoring FLCS <FlashBusy> (See Table 24.10). Any new command sequence is not accepted while automatic programming is in progress to program the protection bits. If it is desired to stop the programming operation, use the hardware reset function. In this case, it is necessary to perform the programming operation again Flash Memory Operation TMP19A44 (rev1.3)24-33 2010-04-01 TMP19A44 because the protection bits may not have been correctly programmed. If all the protection bits have been programmed, the flash memory cannot be read from any area outside the flash memory such as the internal RAM. Note: Software reset is ineffective in the seventh bus write cycle of the automatic protection bit programming command. The FLCS <FlashBusy> bit turns to "0" after entering the seventh bus write cycle. 8) Automatic erasing of protection bits The protection condition can be canceled by the automatic protection bit erase operation. The target bits are specified in the seventh bus write cycle and when the command is completed, the device is in a condition all the blocks are erased. This operation can be checked by monitoring FLCS <FlashBusy>. Also, you can check the protection condition by monitoring FLCS <PROTECT 3:0>. When the automatic protection bit erase command is command written, the flash memory is automatically initialized within the device. When the seventh bus write cycle is completed, the entire area of the flash memory data cells is erased and then the protection bits are erased. While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that it has been correctly erased. For returning to the read mode while the automatic operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to reset the device. If this is done, it is necessary to check the status of protection bits by FLCS <PROTECT 3:0> after retuning to the read mode and perform either the automatic protection bit erase, automatic chip erase, or automatic block erase operation, as appropriate. In any case, any new command sequence is not accepted while it is in an automatic operation to erase protection bits. If it is desired to stop the operation, use the hardware reset function. When the automatic operation to erase protection bits is normally terminated, it returns to the read mode. The FLCS <FlashBusy> bit is "0" while in automatic operation and it turns to "1" when the automatic operation is terminated. Flash Memory Operation TMP19A44 (rev1.3)24-34 2010-04-01 TMP19A44 9) Flash control/ status register This resister is used to monitor the status of the flash memory and to indicate the area protection status. Table 24.10 Flash Control Register FLCS (0xFF00_0100) bit Symbol Read/Writ e After reset 7 6 5 4 3 2 1 0 FlashBusy 0 0 0 1 R 0 0 0 15 bit Symbol Read/Writ e After reset Function 14 13 12 11 10 9 8 0 0 0 0 R 0 23 bit Symbol Read/Writ e After reset Function 0BUSY 1READY "0" can be read. Function bit Symbol Read/Writ e After reset Function 0 0 22 0 21 0 "0" can be read. 20 19 PROTECT3 18 17 16 PROTECT2 PROTECT1 PROTECT0 0 0 0 R 0 0 0 0 0 31 30 29 28 27 Indicates protection condition. 26 25 24 R 0 0 0 0 0 0 0 0 "0" can be read. Bit 0: FlashBusy flag bit The FlashBusy output is provided as a means to monitor the status of automatic operation. This bit is a function bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and outputs "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0" output. By applying a hardware reset, it returns to "1." (note)Please issue it after confirming the command issue is always a ready state. A normal command not only is sent when the command is issued to a busy inside but also there is a possibility that the command after that cannot be input. In that case, please return by system reset or the reset command. Bits [19:16]: Protection status bits ( Each of the protection bits (4 bits) represents the protection status of the corresponding area. When a bit is set to "1," it indicates that the block corresponding to the bit is protected. When the block is protected, data cannot be written to it. Flash Memory Operation TMP19A44 (rev1.3)24-35 2010-04-01 TMP19A44 10) ID-Read Using the ID-Read command, you can obtain the type and other information on the flash memory contained in the device. The data to be loaded will be different depending on the address [15:14] of the fourth and subsequent bus write cycles (any input data other than 0xF can be used). On and after the fourth bus write cycle, when an LW command (to read an arbitrary flash memory area) is executed after an SW command, the ID value will be loaded (execute a SYNC command immediately after the LW command). Once the fourth bus write cycle of an ID-Read command has passed, the device will not automatically return to the read mode. In this condition, the set of the fourth bus write cycle and LW/SYNC commands can be repetitively executed. For returning to the read mode, reset the system or use the Read or Read/reset command. (Important) The "interval between bus write cycles" between successive command sequences must be 15 system clock cycles or longer irrespective of the operating frequency used. This device doesn't have any function to automatically adjust the interval between bus write cycles regarding execution of multiple SW commands to the flash memory. Therefore, if an inadequate interval is used between two sets of bus write cycles, the flash memory cannot be written as expected. Prior to setting the device to work in the onboard programming mode, adjust the bus write cycle interval using a software timer, etc., to verify that the ID-Read command can be successfully executed at the operating frequency of the application program. In the onboard programming mode, use the bus write cycle interval at which the ID-Read command can be operated normally to execute command sequences to rewrite the flash memory. Flash Memory Operation TMP19A44 (rev1.3)24-36 2010-04-01 TMP19A44 (3) List of Command Sequences Table 24.11 Flash Memory Access from the Internal CPU Command sequence Read First bus cycle Second bus cycle Third bus cycle Fourth bus cycle Fifth bus cycle Sixth bus cycle Seventh bus cycle Addr. Addr. Addr. Addr. Addr. Addr. Addr. Data Data Data Data Data Data Data 0xXX 0xF0 RA RD Read/reset 0x55XX 0xAA 0xAAXX 0x55 0x55XX 0xF0 ID-Read 0x55XX 0xAAXX 0x55XX IA 0xXX - 0xAA 0x55 0x90 0x00 ID - Automatic page programming (note) 0x55XX 0xAAXX 0x55XX PA 0x55 0xA0 PA PD1 PA 0xAA PA PD0 PD2 PD3 Automatic chip erase 0x55XX 0xAAXX 0x55XX 0x55XX 0xAAXX 0x55XX - 0xAA 0x55 0x80 0xAA 0x55 0x10 - Auto Block erase (note) 0x55XX 0xAAXX 0x55XX 0x55XX 0xAAXX BA - 0xAA 0x55XX 0xAA 0x55XX 0xAA 0x55 0xAAXX 0x55 0xAAXX 0x55 0x80 0x55XX 0x9A 0x55XX 0x6A 0xAA 0x55 0x55XX 0xAA 0x55XX 0xAA 0xAAXX 0x55 0xAAXX 0x55 0x30 0x55XX 0x9A 0x55XX 0x6A - PBA 0x9A PBA 0x6A Protection bit programming Protection bit erase RA RD (4) Supplementary explanation RA: Read address RD: Read data IA: ID address ID:ID data PA: Program page address PD: Program data (32-bit data) After the fourth bus cycle, enter data in the order of the address for a page. BA: Block address PBA: Protection bit address (Note 1) (Note 2) (Note 3) (Note 4) (Note 5) Always set "0" to the address bits [1:0] in the entire bus cycle. (Setting values to bits [7:2] are undefined.) Bus cycles are "bus write cycles" except for the second bus cycle of the Read command, the fourth bus cycle of the Read/reset command, and the fifth bus cycle of the ID-Read command. Bus write cycles are executed by SW commands. Use "Data" in the table for the rt register [7:0] of SW commands. The address [31:16] in each bus write cycle should be the target flash memory address [31:16] of the command sequence. Use "Addr." in the table for the address [15:0]. In executing the bus write cycles, the interval between each bus write cycle shall be 15 system clocks or more. The "Sync command" must be executed immediately after completing each bus write cycle. Execute the "Sync command" immediately following the "LW command" after the fourth bus write cycle of the IDRead command. Flash Memory Operation TMP19A44 (rev1.3)24-37 2010-04-01 TMP19A44 (5) Address bit configuration for bus write cycles Table 24.12 Address Bit Configuration for Bus Write Cycles Address Addr Addr Addr Addr Addr Addr Addr Addr Addr Addr [31:20] [19] [18:17] [16] [15] [14] [13] [12:9] [8] [7:0] Normal bus write cycle address configuration Normal comman ds Flash area "0" is recommended Addr [1:0]=0 (fixed), Others: 0 (recommended) Command [15:8] 0xbfc0 0x00 BA: Block address (Set the sixth bus write cycle address for block erase operation) Flash area Block selection Addr[19:15] Addr[1:0]=0 (fixed), Others: 0 (recommended) Block erase Block 0:0xbfc00000 Block 2:0xbfc10000 Block 4:0xbfc40000 Block 6:0xbfc80000 Block 8:0xbfcc0000 Block 1:0xbfc08000 Block 3:0xbfc20000 Block 5:0xbfc60000 Block 7:0xbfca0000 Block 9:0xbfce0000 Auto page programming PA: Program page address (Set the fourth bus write cycle address for page programming operation) IDREAD Flash area Flash area Block selection [19:15] Page selection [14:9] Addr[1:0]=0 (fixed), Others: 0 (recommended) IA: ID address (Set the fourth bus write cycle address for ID-Read operation) "0" is recommended 0xbfc0 ID address [15:14] Addr[1:0]=0 (fixed), Others: 0 (recommended) PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming) Protection bit write [18:9] Protectio n bit programming Flash area "0" [18:11]=00100000 [10:9] Area 0:00 Area 1:01 Area 2:10 Area 0:0xbfc10000 Area 2:0xbfc10400 Area 3:11 Addr[1:0]=0 (fixed), Others: 0 (recommended) Area 1:0xbfc10200 Area 3:0xbfc10600 PBA: Protection bit address (Set the seventh bus write cycle address for protection bit erasure) Protectio n bit erase Flash area "0" is recom mend ed Erase protection [1817]00 0xbfc00000 Addr[1:0]=0 (fixed), Others: 0 (recommended) As for the Protection bit, the batch deletion is done. (Note) Table 24.11 "Flash Memory Access from the Internal CPU" can also be used. (Note) Address setting can be performed according to the "Normal bus write cycle address configuration" from the first bus cycle. (Note) "0" is recommended" can be changed as necessary. Flash Memory Operation TMP19A44 (rev1.3)24-38 2010-04-01 TMP19A44 Table 24.13 Block Erase Address Table BA TMP19A44FDAXB G TMP19A44FEXBG Product TMP19A44F10XBG Address Range Flash Memory Address When applied to the projected area Size Block 0 BFC0_0000 - BFC0_7FFF 0x0000_00000x0000_7FFF 32 KB Block 1 BFC0_8000 - BFC0_FFFF 0x0000_80000x0000_FFFF 32 KB Block 2 BFC1_0000 - BFC1_FFFF 0x0001_00000x0001_FFFF 64 KB Block 3 BFC2_0000 - BFC3_FFFF 0x0002_00000x0003_FFFF 128 KB Block 4 BFC4_0000 - BFC5_FFFF 0x0004_00000x0005_FFFF 128 KB Block 5 BFC6_0000 - BFC7_FFFF 0x0006_00000x0007_FFFF 128 KB Block 6 BFC8_0000 - BFC9_FFFF 0x0008_00000x0009_FFFF 128 KB Block 7 BFCA_0000 - BFCB_FFFF 0x000A_00000x000B_FFFF 128 KB Block 8 BFCC_0000 - BFCD_FFFF 0x000C_00000x000D_FFFF 128 KB Block 9 BFCE_0000 - BFCF_FFFF 0x000E_00000x000F_FFFF 128 KB Example: When BA0 is to be selected, any single address in the range 0xBFC0_0000 to 0xBFC0_7FFF may be entered. (Note) As for the addresses from the first to the sixth bus cycles, specify the upper 4 bit with the corresponding flash memory addresses of the blocks to be erased. Table 24.14 Protection Bit Programming/ Erasing Address Table Programming (address) Protect bit 18 17 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 bit0 bit1 bit2 bit3 Erasing (address) 18 17 0 0 Table 24.15 The ID-Read command's fourth bus write cycle ID address (IA) and the data to be read by the following LW command (ID) IA [15:14] ID [7: 0] 00b 0x98 01b 10b 0x5A Reserved 11b Flash Memory Operation 0x10:FE/F10 Code Manufacturer code Device code --Macro code 0x12:FD TMP19A44 (rev1.3)24-39 2010-04-01 TMP19A44 25. Various protecting functions 25.1 Overview The ROM protect function for designating the internal ROM (flash) area as a read-protected area and the DSU protect function for prohibiting the use of DSU (DSU-Probe) are built into the TMP19A44. The read protect functions specifically include the following: * Flash protection * ROM data protection * DSU protection 25.2 Features - Flash Protection It protects data in FLASH memory by prohibiting accidental rewriting and deletion. This function covers the area where protecting bit is set. - ROM data Protection It prevents operand of FLASH data from being read incorrectly. Area attribution is specified with protecting bit and the ROMSEC register. * Deleting protection bit and clearing the ROMSEC register and the DSUSEC register are under protection as well. - DSU Protection It prevents incorrect program analysis using DSU. 25.3 Protecting Functions 25.3.1 Flash Protection An internal FLASH can prohibit the operation of writing and the deletion per protected area. This function is called the flash protection. To make the protection effective, set "1" to the protecting bit corresponding to the area to protect. By clearing this bit to "0", the protection can be released (see "Chapter 24 Flash Memory Operation" for how to program.) The protecting bit can be monitored with FLCS register. a) Operation mode: Valid in single or single boot mode. b) ROM division: The entire ROM area is divided into 4 areas. Protection can be set for each area. d) Area attribution: Defines area as protected or normal (area without protection). FLASH protection/ ROM data protection/ DSU protection Use of protecting bit Item Use of ROMSEC register Use of DSUSEC register Function FLASH protection Yes - - - Prohibits Flash operation (Chip/Block deletion, page writing) ROM protection Yes (with restriction at deletion) Yes (with restriction at clearing) (with restriction at clearing) - Prohibits ROM reading - Controls data deletion at protecting bit deletion - Prohibits clearing register used for ROM data protection - Prohibits clearing register used for DSU protection - Prohibits clearing error flag Yes - - Yes - - Prohibits break. - Prohibits trace (including memory store) data DSU protection Various protecting functions TMP19A44 (rev1.3) 25-1 2010-04-01 TMP19A44 TMP19A44F10XBG1024KB (Physical address) (Flash address) Unit: Word BFC0_0000 BFC0_7FFF 32Kbyte (BLK0) 0000007FFF Area 0 BFC0_8000 32Kbyte (BLK1) 080000FFFF Area 1 64Kbyte (BLK2) 100001FFFF Area 2 128Kbyte (BLK3) 200003FFFF 128Kbyte (BLK4) 400005FFFF 128Kbyte (BLK5) 600007FFFF 128Kbyte (BLK6) 800009FFFF 128Kbyte (BLK7) A0000BFFFF 128Kbyte (BLK8) C0000DFFFF 128Kbyte (BLK9) E0000FFFFF The protection can be set for each area. Overall protection Protected area = 0~3 Area 3 BFCF_FFFF Various protecting functions TMP19A44 (rev1.3) 25-2 2010-04-01 TMP19A44 TMP19A44FEXBG768KB (Physical address) (Flash address) Unit: Word BFC0_0000 Area 0 BFC0_7FFF 32Kbyte (BLK0) 0000007FFF BFC0_8000 32Kbyte (BLK1) 080000FFFF Area 1 64Kbyte (BLK2) 100001FFFF Area 2 128Kbyte (BLK3) 200003FFFF 128Kbyte (BLK4) 400005FFFF 128Kbyte (BLK5) 600007FFFF 128Kbyte (BLK6) 800009FFFF 128Kbyte (BLK7) A0000BFFFF The protection can be set for each area. Overall protection Protected area = 0~3 Area 3 BFCB_FFFF TMP19A44FDAXBG512KB (Physical address) (Flash address) Unit: Word BFC0_0000 BFC0_7FFF 32Kbyte (BLK0) BFC0_8000 32Kbyte (BLK1) 0000007FFF 080000FFFF 64Kbyte (BLK2) 100001FFFF 128Kbyte (BLK3) 200003FFFF 128Kbyte (BLK4) 400005FFFF 128Kbyte (BLK5) Area 0 Area 1 Area 2 Area 3 600007FFFF BFC7_FFFF Various protecting functions TMP19A44 (rev1.3) 25-3 2010-04-01 TMP19A44 ROM Data Protection TMP19A44F10XBG (evaluation sample) The ROM data protection restricts data reading from internal FLASH. This function does not cover: - access to unprotected area - access to protected area by ROM correction (the area is considered to be accessed by an internal RAM) - access to an internal RAM, internal Boot-ROM, external memory and DSU (debug area) - access to operand by an internal DMAC - access by FLASH writer How to make the protection valid Set SECBIT, which corresponds to area to protect, of the SECBIT register to "1" (enabled). (All bits are set to "1"and enabled after power-on.) Procedure of detecting protection 1) Issuing a protecting bit erase command from normal area. 2) Detecting protection. 3) Deleting the entire data in FLASH. 4) Deleting a protecting bit. Procedure of SECBIT protection 1) Writing corresponding SECBIT from normal area. 2) Detecting protection (no value updated). Procedure of ROM data protection 1) Reading protected area from normal area. 2) Detecting protection. (Flash writer is used) Initial data in an internal ROM can be read. (Others) "0x0098" can be read. Procedure of DSU protection 1) Either of the following takes place: - Executing an instruction in protected area (for inhibiting break, event/ PC trace). - Executing operand bus cycle caused by an instruction in protected area (for inhibiting data trace). 2) Detecting protection. 3) Inhibiting break (executes EJTAGBOOT and step) and trace (including store to trace memory). Various protecting functions TMP19A44 (rev1.3) 25-4 2010-04-01 TMP19A44 25.4 Definition of operations/ terms - Protected area valid: Corresponding SECBIT bit is set to "1" (enabled). - Detecting ROM data protection : Control by ROSMEC (operand mask etc.) is in operation. - Detecting DSU protection : Control by DSUSEC (inhibiting break/ trace etc.) is in operation Example of detecting protection Protecting bit 1 1 Under protection Access from Internal ROM SECBIT OK OK Protected area NG NG 1 0 0 0 Normal area 0 1 Normal area OK Normal area OK Internal RAM (including when ROM correction is executed) Internal BROM External MEM DMAC DSU Flash-WR : operand access OK: correct access NG: incorrect access Various protecting functions TMP19A44 (rev1.3) 25-5 2010-04-01 TMP19A44 25.5 Registers Flash Control Register (FLCS) 7 FLCS (0xFF00_0100) bit Symbol 6 5 4 Read/Write After reset 0 1 0 0 0 0 0 0 "0" can be read. 15 bit Symbol 14 13 12 0 0 0 0 Read/Write After reset 23 bit Symbol 22 21 0 0 0 31 30 0 0 0 11 10 9 8 0 0 0 0 18 17 16 PROTECT2 PROTECT1 PROTECT0 0 0 0 25 24 0 0 0 Indicates protection condition. 29 28 27 26 Read/Write After reset 1 R Function bit Symbol FlashBusy 0:BUSY 1:READY "0" can be read. 20 19 PROTECT3 Read/Write After reset 0 R Function R 0 0 0 0 "0" can be read. Function PROTECT3:0 2 R Function FlashBusy 3 : FLASH READY/BUSY signal 0: BUSY 1: READY : Under protection. Various protecting functions TMP19A44 (rev1.3) 25-6 2010-04-01 TMP19A44 7 SECBIT (0xFF00_0200) bit Symbol ROM Data Protection Enable Bit Register (SECBIT) 6 5 4 3 2 SECBIT3 SECBIT2 Read/Write After reset R 0 0 0 14 13 Read/Write 1 12 11 0 Function "0" can be read. 20 19 23 22 21 Read/Write 1 10 9 8 18 17 16 26 25 24 R After reset 0 Function "0" can be read. 28 27 31 bit Symbol 1 R After reset bit Symbol 1 xxx1 :Enabling area 0 protection xx1x :Enabling area 1 protection x1xx :Enabling area 2 protection 1xxx :Enabling area 3 protection Function 15 0 SECBIT0 R/W 0 "0" can be read. bit Symbol 1 SECBIT1 Read/Write 30 29 R After reset 0 Function "0" can be read. Various protecting functions TMP19A44 (rev1.3) 25-7 2010-04-01 TMP19A44 ROM Protection Lock Register 7 6 5 4 3 2 1 0 11 10 9 8 18 17 16 26 25 24 SECCODE Bit Symbol (0xFF00_0208) Read/Write W After reset Undefined Function See note. 15 14 13 12 Bit Symbol Read/Write W After reset Undefined Function See note. 23 22 21 20 19 Bit Symbol Read/Write W After reset Undefined Function See note. 31 30 29 28 27 Bit Symbol Read/Write W After reset Undefined Function See note. (Note) Setting 0x0000_003d to the SECCODE register enables writing to the SECBIT register. Various protecting functions TMP19A44 (rev1.3) 25-8 2010-04-01 TMP19A44 DSU Protection Enable Bit Register 7 DSUSECBIT (0xFF00_0204) 6 5 4 Bit Symbol 3 2 1 0 DSUSECBIT3 DSUSECBIT2 DSUSECBIT1 DSUSECBIT0 Read/Write R After reset 0 Function R/W 1 xxx1 :Enabling area 0 protection xx1x :Enabling area 1 protection x1xx :Enabling area 2 protection 1xxx :Enabling area 3 protection "0" can be read. 15 14 13 12 11 10 9 8 18 17 16 26 25 24 Bit Symbol Read/Write R After reset 0 Function "0" can be read. 23 22 21 20 19 Bit Symbol Read/Write R After reset 0 Function "0" can be read. 31 30 29 28 27 Bit Symbol Read/Write After reset Function R 0 "0" can be read. DSU protection enable bit register setting: 1: Protection enabled 0: Protection disabled Protection for each area can be set. xxx1: Enabling area 0 protection xx1x: Enabling area 1 protection x1xx: Enabling area 2 protection 1xxx: Enabling area 3 protection Power-on reset sets the entire bits to "1". Various protecting functions TMP19A44 (rev1.3) 25-9 2010-04-01 TMP19A44 DSU Protection Control Register DSUSECCODE (0xFF00_020C) Bit Symbol 7 6 5 4 3 2 1 0 DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE 07 06 05 04 03 02 01 00 Read/Write W After reset 0 Function Bit Symbol Write "0x0000_00C5". 15 14 13 12 11 10 9 8 DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE 15 14 13 12 11 10 09 08 Read/Write W After reset 0 Function Bit Symbol Write "0x0000_00C5". 23 22 21 20 19 18 17 16 DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE 23 22 21 20 19 18 17 16 Read/Write W After reset 0 Function Bit Symbol Write "0x0000_00C5". 31 30 29 28 27 26 25 24 DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE DSECODE 31 30 29 28 27 26 25 24 Read/Write After reset Function W 0 Write "0x0000_00C5". (Note 1) To access this register, 32-bit access is required. (Note 2) This is read-only register. Undefined values are read. Setting 0x0000_00c5 to the SUSECCODE register enables writing to the DSUSECBIT register. Example) If area 0 is protected: The instruction from area 0 can write both "0" and "1" to the SECBIT and DSUSECBIT registers. The instruction from area 1, 2 and 3 can write "1" to the SECBIT and DSUSECBIT registers. Various protecting functions TMP19A44 (rev1.3) 25-10 2010-04-01 TMP19A44 26. Backup module 26.1 Features The backup mode, one of the system operation modes, enables the 19A44 to operate in the low power consumption. By cutting electricity to the entire block, such as CPU or other peripheral I/Ps, other than the backup module, this mode significantly reduces power consumption. 26.2 Overview The backup mode operates in lower power consumption than STOP/SLEEP modes. Backup mode Condition for releasing standby mode Backup STOP Two-phase counter (counting enabled, INT, Key-on wake-up (static), STOP release ,reset Backup SLEEP Two-phase counter (asynchronous input) ,INT, Key-on wake-up (dynamic/static), real time clock,reset 26.3 Operation in Backup Mode DSU Transition to the backup mode is available while DSU is connected. When the transition takes place, the power supply to DSU is not cut and DSU retains data but stops operating. Two-phase counter High-speed counting is available in both Backup STOP and Backup SLEEP modes. PORT Output/Pull-up: retains the condition set in the PORTKEEP register. Input: disabled (two-phase counter, key-on wake-up and INT input are enabled.) Key-on wake-up operates by dynamic pull-up (input enabled). Backup module TMP19A44 (rev1.3)26-1 2010-04-01 TMP19A44 26.4 Block Diagram Fig. 26.1 shows the block diagram of the backup module. Backup module ADC (3V only) Key-on wake-up RTC RAM16/8 Two-phase counter CG RESET INT RSTGEN Standby release Reset control Retains interrupt Generates reset Standby signal Wake-up PLL PORT Retains PORT condition 1.5V Regulator 3V Always ON Regulator main 1.5V In backup mode: OFF Fig. 26.1 Block Diagram of Backup Module Backup module TMP19A44 (rev1.3)26-2 2010-04-01 TMP19A44 26.5 Registers 26.5.1 Standby Control Register 7 CR0 LITTLE (0xFF00_1908) BIG (0xFF00_190B) Bit symbol Read/Write After reset Function 6 CR1 LITTLE (0xFF00_1909) (0xFF00_190A) BIG CR2 LITTLE BIG (0xFF00_190A) (0xFF00_1909) 14 <Bit 2:0><STBY2:0> 13 12 11 2 1 STBY2 STBY1 R/W R/W 0 1 Standby mode selection 000: Reserved 001: STOP 010: SLEEP 011: IDLE 100: Reserved 101: Backup STOP 110: Backup SLEEP 111: Reserved 10 R 0 "0" is read. 22 21 20 19 18 28 27 26 R 0 "0" is read. 31 Bit symbol Read/Write After reset 3 "0" is read. 23 Bit symbol Read/Write After reset Function 4 R 0 15 Bit symbol Read/Write After reset Function 5 30 29 9 RXTEN R/W 0 Low-speed oscillator operation after releasing STOP mode 8 RXEN R/W 1 High-speed oscillator operation after releasing STOP mode 0: Stop 1: Oscillating 17 PTKEEP R/W 0 0:PORT control 1: retains condition shifted from 0 to 1. 0: Stop 1: Oscillating 16 DRVE R/W 0 0: Not to drive the pin even in the STOP mode. 1: Drive the pin even in the STOP mode. 24 25 R "0" is read. : Selects standby mode. <Bit 8><RXEN> : Selects high-speed oscillator operation after releasing STOP mode <Bit 9><RXTEN> : Selects low-speed oscillator operation after releasing STOP mode <Bit 16><DRVE> : Selects pin drive condition in STOP mode. This setting is invalid in the backup mode. <Bit 17><PTKEEP> : Retains port condition in the backup mode. Reset initializes the port, therefore reconfiguration is required. Backup module 0 STBY0 R/W 1 TMP19A44 (rev1.3)26-3 2010-04-01 TMP19A44 26.5.2 Reset Flag Register 7 6 0 0 5 4 0 0 Bit symbol RSTFLG (0xFF00_191C) Read/Write After reset Function R "0" is read. 3 BUPRST F R/W 0 Backup reset flag 0: "0" is written. 1:Resetti ng backup mode Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function 15 14 13 12 0 0 0 0 23 22 21 0 "0" is read. 20 19 0 0 0 0 31 30 29 0 "0" is read. 28 27 0 0 0 0 2 WDTRST F R/W 0 Watchdo g timer reset flag 0: "0" is written. 11 1:Reset by watchd og timer 10 1 PINRSTF R/W 0 RESET pin flag 0 PONRST F R/W 1 Power-on Reset flag 0: "0" is written. 0: "0" is written. 1:Reset from RESET pin 1:Power On Reset 9 8 0 0 0 18 17 16 0 0 0 26 25 24 0 0 0 R R R 0 "0" is read. <Bit 0><PONRSTF> : Power-on reset sets this bit to "1". <Bit 1><PINRSTF> : Reset from RESET pin sets this bit to "1". <Bit 2><WDTRSTF> : Reset by a watch dog timer sets this bit to "1". <Bit 3><BUPRSTF> : Returning from backup mode sets this bit to "1". Writing "0" resets a flag. Backup module TMP19A44 (rev1.3)26-4 2010-04-01 TMP19A44 26.6 Return Circuit KEYx NF CG INTx PHCNT NF KWUP PHCNT RTC In the backup mode, a return signal of an external factor or the real time clock is transferred to the internal clock generator. The interrupt factor is retained in the clock generator, and the main regulator is powered on. The instruction is executed from the initial address in the same manner as reset operation. The flags in the Reset Flag Register indicate which interrupt factor is used. Backup module TMP19A44 (rev1.3)26-5 2010-04-01 TMP19A44 26.7 Transition flowchart Preparing for standby Setting CG register STB=STOP/SLEEP Retaining port condition PTKEEP=1, Processed by software Backup for mode setting Transition to HALT mode Transition to STOP/SLEEP mode During standby Supplying electricity only to backup module Main regulator stops Transition to reset mode Waiting for an interrupt Power supply to main regulator: ON Power supply stability time (Warm-Up) Oscillation stability time (Warm-Up) Reset Normal operation Checking reset flag. Checking if it can return to backup mode Setting for interrupt Jump to a handler. Checking a factor to activate backup mode Processed by software Default setting of port PTKEEP=0/BUP=0 Backup module TMP19A44 (rev1.3)26-6 2010-04-01 TMP19A44 27. Electrical Characteristics The letter x in equations presented in this chapter represents the cycle period of the fsys clock selected through the programming of the SCKSEL.SYSCK bit. The fsys clock may be derived from either the highspeed or low-speed crystal oscillator. The programming of the clock gear function also affects the fsys frequency. All relevant values in this chapter are calculated with the high-speed (fc) system clock (SCKSEL.SYSCK = 0) and a clock gear factor of 1/fc (SYSCR1.GEAR[2:0] = 000). 27.1 Absolute Maximum Ratings Parameter Symbol Supply voltage Low-level Per pin output Total current High-level Per pin output Total current Power consumption (Ta = 85C) Soldering temperature (10 s) Storage temperature Operating Temperature - 0.3 to 3.9 AVCC3A/D - 0.3 to 3.9 DVCC3 - 0.3 to 3.9 During Flash W/E - 0.3toVCC + 0.3 Unit V V IOL 5 IOL 50 IOH -5 IOH -50 PD 600 mW TSOLDER 260 C -40to125 C TSTG Exceptduring Flash W/E Write/erase cycles Note: VCC3 (I/O) VIN Supply voltage Rating TOPR NEW -20 to 85 0 to 70 100 mA C cycle Absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no Absolute maximum rating value is exceeded with respect to current, voltage, power consumption, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. Electrical Characteristics TMP19A44 (rev1.3) 27-1 2010-04-01 TMP19A44 27.2 DC ELECTRICAL CHARACTERISTICS (1/3) Ta=20 to 85C Parameter Supply voltage Symbol Rating Min. Typ. Max. Unit 3.6 V (Note 1) AVCC3 n= DVCC3=3.3V DVCC3 CVSS=DVSS= AVSS= 0V fosc = 8 to 10MHz fs = 30kHz to 34kHz fsys = 30KHz to 34KHz 4MHz to 80MHz 2.7 Low-level input voltage P7 to P8 VIL1 2.7VAVCC3n3.6V 0.3 AVCC3n Normal port VIL2 2.7VDVCC33.6V 0.3 DVCC3 - 0.3 Schmitt-Triggered port XT1 V VIL3 2.7VDVCC33.6V 0.2 DVCC3 VIL5 2.7VDVCC33.6V 0.1DVCC3 Note 1: Ta = 25C, DVCC3= AVCC3n=3.3V, unless otherwise noted. Ta=20 to 85C Parameter Symbol Rating Min. High-level input voltage VIH1 2.7VAVCC33.6V 0.7 AVCC3 Normal port VIH2 2.7VDVCC33.6V 0.7 DVCC3 XT1 Low-level output voltage High-level output voltage Max. Unit DVCC3 + 0.3 V (Note 1) P7 to P8 Schmitt-Triggered port Typ. VIH3 2.7VDVCC33.6V 0.8 DVCC3 VIH5 2.7VDVCC33.6V 0.9 CVCCL VOL IOL = 2mA VOH IOH = - 2mA DVCC32.7V DVCC32.7V 0.4 2.4 (DVCC3=0.3) V Note 1: Ta = 25C, DVCC3= AVCC3n=3.3V, unless otherwise noted Electrical Characteristics TMP19A44 (rev1.3) 27-2 2010-04-01 TMP19A44 27.3 DC ELECTRICAL CHARACTERISTICS (2/3) Ta=20 to 85C Parameter Symbol Rating Min. Typ. Max. Unit (Note 1) Input leakage current Output leakage current ILI 0.0 VIN DVCC3 0.02 0.0 VIN AVCC3n ILO A 0.2 VIN DVCC3 - 0.2 0.2 VIN AVCC3n- 0.2 0.05 10 150 Pull-up resister at Reset RRST DVCC3= 2.7Vto3.6V 20 50 Schmitt-Triggered port VTH 2.7VDVCC33.6V 0.3 0.6 Programmable pull-up/ pull-down resistor PKH DVCC3 = 2.7V to3.6V 20 50 CIO fc = 1MHz Pin capacitance (Except power supply pins) 5 k V 150 k 10 pF Note 1: Ta = 25C, DVCC3= AVCC3n=3.3V, unless otherwise noted. 27.4 DC ELECTRICAL CHARACTERISTICS (3/3) Ta=20 to 85C DVCC3=AVCC3n=2.7V to 3.6V TMP19A44FDAXBG Parameter Symbol Rating Min. Typ. Max. Unit (Note 1) NORMAL(Note 2): Gear = 1/1 fsys =-80 MHz IDLE(Doze) (Note 3) (f IDLE(Halt) (Note 3) SLOW (Note 4) OSC = -10 MHz) ICC SLEEP (Note 4) fs = 32.768kHz 45 55 30 40 25 40 23 35 mA 3 10 A 250 3000 A A Backup SLEEP 25 145 STOP 200 2800 Backup STOP 22 140 A (Note 1) Ta = 25C, DVCC3= AVCC3=3.3V, unless otherwise noted (Note 2) ICC NORMAL: Measured with the CPU dhrystone operating ( DSU is excluded.), RAM, FLASH. All functions operating. A/D excluded. (Note 3) ICC IDLE : Measured with all functions stoping. (Note 4) ICC SLOW, SLEEP and Backup SLEEP: Measured with RTC on low-speed (Note 5) EJE=1 Electrical Characteristics TMP19A44 (rev1.3) 27-3 2010-04-01 TMP19A44 DVCC3=AVCC3n=2.7V to 3.6V Ta=20 to 85C TMP19A44FEXBG/F10XBG Parameter Symbol Rating Min. Typ. Max. Unit (Note 1) NORMAL(Note 2): Gear = 1/1 fsys =-80 MHz IDLE(Doze) (Note 3) (f IDLE(Halt) (Note 3) SLOW (Note 4) OSC = -10 MHz) ICC 50 60 30 40 27 45 24 40 mA A 5 16 340 6200 A Backup SLEEP 33 710 A STOP 290 6000 Backup STOP 30 700 SLEEP (Note 4) fs = 32.768kHz A (Note 6) Ta = 25C, DVCC3= AVCC3n=3.3V, unless otherwise noted (Note 7) ICC NORMAL: Measured with the CPU dhrystone operating ( DSU is excluded.), RAM, FLASH. All functions operating. A/D excluded. (Note 8) ICC IDLE : Measured with all functions stoping. (Note 9) ICC SLOW, SLEEP and Backup SLEEP: Measured with RTC on low-speed (Note 10) EJE=1 Electrical Characteristics TMP19A44 (rev1.3) 27-4 2010-04-01 TMP19A44 27.5 10-bit ADC Electrical Characteristics DVCC3=AVCC3n=VREFH=2.7V to 3.6V, AVSS = DVSS ,Ta=20 to 85C AVCC3 load capacitance= 3.3F, VREFH load capacitance= 3.3F Parameter Symbol Rating Min Typ Max Unit Analog reference voltage ( + ) VREFH 2.7 3.3 3.6 V Analog reference voltage ( - ) VREFL AVSSn AVSSn AVSSn V VAIN VREFLn VREFHn V 2 5 mA 0.02 5 A 7 10 mA Analog input voltage Analog supply current consumption current A/D conversion Non-A/D conversion A/D conversion IREF 1.3k Conversion time1.15s AIN resistance INL error AIN load capacitance 0.1F DNL error 3 2 Offset error 4 Fullscale error 4 (Note 1) 1LSB = (VREFH - VREFL) / 1024[V] (Note 2) No guarantee about Relative accuracy in the multiple-channel operation Electrical Characteristics TMP19A44 (rev1.3) 27-5 LSB 2010-04-01 TMP19A44 27.6 AC Electrical Characteristic 27.6.1 Separate Bus mode (1) DVCC3AVCC3n=2.7Vto3.6V, Ta = 20 to 85C BUSCR<ALESEL> = "01" BxxCS<BxW> = "0_1010" BxxCS<BxCSCV> =" 001" BxxCS<BxRCV> = "01" BxxCS<BxWCV> ="01" Equation No. Parameter 40 MHz (fsys)(Note) Symbol Min 1 System clock period (x) x tSYS 2 A0-A23 valid to RD , WR asserted or HWR 3 A0-A23 hold after RD , WR or HWR negated Max tAC tCAR Min 12.5 x (1 + ALE) - 19 6 x (1 + CSR) - 19 6 Unit Max ns ns ns 4 A0-A23 valid to D0-D15 Data in tAD x (2 + ALE + W) - 46 116.5 ns 5 RD asserted to D0-D15 data in tRD x (1 + W) - 46 91.5 ns 6 RD tRR x (1 + W) - 13 7 D0-D15 hold after RD negated tHR 0 8 tRAE x (1+ CSR RWR) - 19 tWW x (1 + W) - 13 width low RD negated to next A0-A23 output 9 WR /HWR width low 10 WR or HWR asserted to D0-D15 valid tDO 11 D0-D15 hold negated after HWR tDW 12 D0-D15 negated after or HWR tWD hold WR or WR 14 WAIT hold after RD , WR or HWR asserted ns 0 ns 19 ns 6 x (1 + ALE + W - 2) 46 x (W - 2 + N) - 46 90 ns ns 118.5 x (1 + CSR) - 19 x (W - 2) - 10 ns 124.5 x (1 + W) - 19 tCW ns 18.5 19 tAW 13 A0-A23 valid to WAIT input + 124.5 79 ns 104 ns Note : ALE: Number of ALE insertion W: Number of Auto wait insertion , N : Number of external wait insertion AC measurement conditions: Output levels: High = 0.8DVCC3 V/Low 0.2DVCC3 V, CL = 30 pF Input levels: High = 0.7DVCC3 V/Low 0.3DVCC3 V Electrical Characteristics TMP19A44 (rev1.3) 27-6 2010-04-01 TMP19A44 (1) Read cycle timing (BUSCR <ALESEL>= 0, 1 programmed wait state) 4CLK/1BUS Cycle InternalCLK S1 Sw S2 S0 S1 CS0~3 tAD A0~23 tAC tHR D0~15 D015 tRR RD tCAR tRAE tRD R/W Electrical Characteristics TMP19A44 (rev1.3) 27-7 2010-04-01 TMP19A44 (2) Read cycle timing (BUSCR <ALESEL> = 1, 1 programmed wait state) 5CLK/1BUS Cycle InternalCLK S1i S1 Sw S2 S0 S1i CS0~3 tAD A16~23 tAC tHR tAD D0~15 D015 tRR RD tCAR tRAE tRD R/W Electrical Characteristics TMP19A44 (rev1.3) 27-8 2010-04-01 TMP19A44 (3)Read cycle timing BUSCR <ALESEL> = 1, 4 externally generated wait states with N = 1) 8CLK/1BUS Cycle InternalCLK S1 Sw Sw SwE Sw S0 S2 CS0~3 A0~23 D0~15 D015 RD tCW R/W tAW WAIT Electrical Characteristics TMP19A44 (rev1.3) 27-9 2010-04-01 S1i TMP19A44 (4) Write cycle timing (BUSCR <ALESEL> = 1, zero wait sate) 4CLK/1BUS Cycle InternalCLK CS0~3 A0~23 tAC tDW D0~15 tWD D015 tDO tWW tCAR WR, HWR R/W Electrical Characteristics TMP19A44 (rev1.3) 27-10 2010-04-01 TMP19A44 (5) Write cycle timing (BUSCR <ALESEL> =1, auto 2 wait state+2N(N=1)) 4CLK/1BUS Cycle InternalCLK CS0~3 tAC A0~23 tDW D0~15 tWD D015 tDO tWW tCAR WR, HWR R/W WAIT Electrical Characteristics TMP19A44 (rev1.3) 27-11 2010-04-01 TMP19A44 (6) Write cycle timing (BUSCR <ALESEL>= 1, auto 3 wait state+2N(N=1)) 4CLK/1BUS Cycle InternalCLK CS0~3 tAC A0~23 tDW D0~15 tWD D015 tDO tWW tCAR WR, HWR R/W WAIT Electrical Characteristics TMP19A44 (rev1.3) 27-12 2010-04-01 TMP19A44 27.6.2 Multiplex Bus mode (1) DVCC3AVCC3n= 2.7Vto3.6V,Ta =20to85C BUSCR<ALESEL> ="01" BxxCS<BxW> ="0_1010" BxxCS<BxCSCV> ="001" BxxCS<BxRCV> ="01" BxxCS<BxWCV> ="01" Equation No. Parameter 40 MHz (fsys)(Note) Symbol Min Max Min Unit Max 1 System clock period (x) tSYS x 12.5 ns 2 A0-A15 VALID TO ALE LOW tAL x (1 + ALE) - 19 18.5 ns 3 A0-A15 HOLD AFTER ALE LOW tLA x - 12 0.5 ns 4 ALE pulse width high tLL x (1 + ALE) - 6 31.5 5 ALE low to RD , WR or HWR asserted tLC 6 RD , WR or HWR negated to ALE high tCL x(1+CSR+RWR) - 19 18.5 ns 7 A0-A15 valid to RD , WR or HWR asserted tACL x (1 + ALE) - 19 18.5 ns 8 A16-A23 valid to RD , WR or HWR asserted tACH x (1 + ALE) - 19 18.5 9 A16-A23 hold after tCAR x (1CSR) - 19 6 RD , WR HWR or x - 12 ns ns 0.5 ns ns negated 10 A0-A15 valid to D0-D15 Data in tADL x (2 + ALE + W) - 46 129 ns 11 A16-A23 valid to D0-D15 Data in tADH x (2 + ALE + W) - 46 129 ns 12 RD 91.5 ns 13 RD 14 asserted to D0-D15 data in x (1 + W) - 46 tRD tRR x (1 + W) - 13 D0-D15 hold after RD negated tHR 0 15 RD negated to next A0-A15 output tRAE x(1+CSR+ RWR) -19 16 WR / HWR tWW x (1 + W) - 13 17 D0-D15 valid to WR or HWR negated width low width low 18 D0-D15 hold negated after WR or tDW HWR ns 0 ns 18.5 ns 124.5 x (1 + W) - 19 tWD 124.5 ns ns 118.5 x (1 + CSR) - 19 ns 6 19 A16-A23 valid to WAIT input tAWH x (1 + ALE + W - 2) - 46 91.5 ns 20 A0-A15 valid to WAIT input tAWL x (1 + ALE + W - 2) - 46 91.5 ns 21 WAIT 104 ns hold after RD , WR or HWR asserted tCW x (W - 2) - 10 x (W - 2 + N) - 46 90 Note : ALE: Number of ALE insertion W: Number of Auto wait insertion , N : Number of external wait insertion AC measurement conditions: Output levels: High = 0.8DVCC3 V/Low 0.2DVCC3 V, CL = 30 pF Input levels: High = 0.7DVCC3 V/Low 0.3DVCC3 V Electrical Characteristics TMP19A44 (rev1.3) 27-13 2010-04-01 TMP19A44 (1) Read cycle timing, ALE width = 1 clock cycle, 1 programmed wait state 5CLK/1BUS Cycle InternalCLK S1i W1 S1 S2 Sw S3 S2 S1i S1 S0 tLL ALE tCL tAL tLA AD0~15 D015 A015 tADL tADH A16~23 tHR tACH tACL tLC tRR tCAR tRAE RD tRD CS0~3 R/W Electrical Characteristics TMP19A44 (rev1.3) 27-14 2010-04-01 TMP19A44 (2) Read cycle timing, ALE width = 1 clock cycle, 2 programmed wait state 6CLK/1BUS Cycle InternalCLK tLL ALE tCL tAL tLA AD0~15 D015 A015 tADL tADH A16~23 tHR tACH tACL tLC tRR tCAR tRAE tRD RD CS0~3 R/W Electrical Characteristics TMP19A44 (rev1.3) 27-15 2010-04-01 TMP19A44 (3) Read cycle timing, ALE width = 1 clock cycle, 4 programmed wait state 8CLK/1BUS Cycle InternalCLK ALE AD0~15 A015 D015 AD16~23 RD tCW CS0~3 R/W tAWL/H WAIT Electrical Characteristics TMP19A44 (rev1.3) 27-16 2010-04-01 TMP19A44 (4) Read cycle timing, ALE width = 2 clock cycle, 1 programmed wait state 6CLK/1BUS Cycle InternalCLK S1i S1x S1 Sw S2 S0 S1i tLL ALE tAL tCL tLA AD0~15 A015 D015 tADL tHR tADH A16~23 tACH tACL tLC tRR tRAE tRD RD CS0~3 R/W Electrical Characteristics TMP19A44 (rev1.3) 27-17 2010-04-01 TMP19A44 (5) Read cycle timing, ALE width = 2 clock cycle, 4 programmed wait state 9CLK/1BUS Cycle InternalCLK S1x S1 Sw Sw SwEx Sw S2 S0 S1x ALE AD0~15 A015 D015 AD16~23 RD tCW CS0~3 R/W tAWL/H WAIT Electrical Characteristics TMP19A44 (rev1.3) 27-18 2010-04-01 TMP19A44 (6) Write cycle timing, ALE width = 2 clock cycles, zero wait state 5CLK/1BUS Cycle InternalCLK tLL ALE tAL tCL tLA AD0~15 D015 A015 tDW AD16~23 tWD tACH tACL tLC tWW tCAR WR, HWR CS0~3 R/W Electrical Characteristics TMP19A44 (rev1.3) 27-19 2010-04-01 TMP19A44 (7) Write cycle timing, ALE width = 1 clock cycles, 2 wait state 6CLK/1BUS Cycle InternalCLK tLL ALE tAL tCL tLA AD0~15 D015 A015 tDW AD16~23 tWD tACH tACL tLC tWW tCAR WR, HWR CS0~3 R/W Electrical Characteristics TMP19A44 (rev1.3) 27-20 2010-04-01 TMP19A44 (8) Write cycle timing, ALE width = 2 clock cycles, 4 wait state 9CLK/1BUS Cycle InternalCLK tLL ALE tAL tCL tLA AD0~15 AD16~23 D015 A015 tDW tWD tWW tCAR tACH tACL tLC WR, HWR tCW CS0~3 R/W tAWL/H WAIT Electrical Characteristics TMP19A44 (rev1.3) 27-21 2010-04-01 TMP19A44 27.7 Transfer with DMA Request The following shows an example of a transfer between the on-chip RAM and an external device in multiplex bus mode. * 16-bit data bus width, non-recovery time * Level data transfer mode * Transfer size of 16 bits, device port size (DPS) of 16 bits * Source/destination: on-chip RAM/external device The following shows transfer operation timing of the on-chip RAM to an external bus during write operation (memory-to-memory transfer). GCLKIN Internal Clock (1) tDREQ_w (2) tDREQ_w DREQn (2) tDREQ_r (1) tDREQ_r AD[15:0] Add Data Add (N-1)transfer Data Add N transfer Data (N+1)transfer ALE HWR LWR CS R/W GBSTART (1) Indicates the condition under which Nth transfer is performed successfully. (2) Indicates the condition under which (N + 1)th transfer is not performed. GACK 2Clk 2Clk DVCC3=AVCC3n=2.7V to 3.6V, Ta = 20 to 85C Equation Parameter 80 MHz (fsys) Symbol (1) Min (2) Max Min Max Unit RD asserted to DREQn negated (external device to on-chip RAM transfer) tDREQ_r W+1x 2WALE8x51 25 86.5 ns WR / HWR rising to DREQn negated tDREQ_w -(W+2)x 5+WAITx51.8 -37.5 23.2 ns (on-chip RAM to external device transfer) Electrical Characteristics TMP19A44 (rev1.3) 27-22 2010-04-01 TMP19A44 27.8 Serial Channel Timing (1) I/O Interface modeDVCC3=2.7V to 3.6V In the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. 1) SCLK input modeSIO0 to SIO2 Sym bol Parameter Equation Min 40/ 80 MHz Max Min Max Unit SCLK period tSCY 6x 150 ns SCLK Clock High width(input) TscH tSCY /2 75 ns SCLK Clock Low width (input) TscL tSCY /2 75 ns TxD data to SCLK rise or fall* tOSS tSCY /2 - 2x - 45 tOHS RxD data valid to SCLK rise or fall* tSRD RxD data hold after SCLK rise or fall* tHSR tSCY /2 30 x + 30 -20 75 30 55 ns TxD data hold after SCLK rise or fall* * ns ns ns SCLK rise or fall: Measured relative to the programmed active edge of SCLK. 2) SCLK output mode SIO0 to SIO2 Sym bol Parameter Equation Min 40/ 80 MHz Max Min Unit Max SCLK period tSCY 4x 100 ns TxD data to SCLK rise or fall* tOSS tSCY /2 - 20 45 ns TxD data hold after SCLK rise or fall* tOHS tSCY /2 - 20 45 ns RxD data valid to SCLK rise or fall* tSRD 45 45 ns RxD data hold after SCLK rise or fall* tHSR 0 0 ns tSCY SCLK SCK Output Mode/ Active-High SCL Input Mode SCLK Active-Low SCK Input Mode OUTPUT DATA TxD tOSS 0 tOHS 1 2 tSRD INPUT DATA RxD Electrical Characteristics 3 tHSR 0 1 2 3 VALID VALID VALID VALID TMP19A44 (rev1.3) 27-23 2010-04-01 TMP19A44 27.9 High Speed Serial Channel Timing (1) I/O Interface modeDVCC3=2.7V to 3.6V In the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. 1) HSCLK input modeHSIO0 to HSIO2 Equation Sym bol Parameter Min 40/ 80 MHz Max Min Unit Max HSCLK period tSCY 8x 100 ns HSCLK Clock High width(input) TscH tSCY /2 50 ns HSCLK Clock Low width (input) TscL tSCY /2 50 ns TxD data to HSCLK rise or fall* tOSS tSCY /2 - 3x - 45 -32.5 tSCY /2 - 3x - 36 -23.5 ns TxD data hold after HSCLK rise or fall* tOHS tSCY /2 50 ns RxD data valid to HSCLK rise or fall* tSRD 30 30 ns RxD data hold after HSCLK rise or fall* tHSR x/2 + 30 36.25 ns * HSCLK rise or fall: Measured relative to the programmed active edge of HSCLK. 2) HSCLK output mode HSIO0 to HSIO2 Equation Sym bol Parameter Min 40 MHz Max Min Max Unit HSCLK period tSCY 4 100 ns TxD data to HSCLK rise or fall* tOSS (tSCY /2) -10 40 ns TxD data hold after HSCLK rise or fall* tOHS (tSCY /2) -10 40 ns RxD data valid to HSCLK rise or fall* tSRD 45 45 ns RxD data hold after HSCLK rise or fall* tHSR 0 0 ns tSCY SCLK SCK Output Mode/ Active-High SCL Input Mod SCLK Active-Low SCK Input Mode OUTPUT DATA TxD tOHS tOSS 0 1 2 tSRD INPUT DATA RxD Electrical Characteristics 3 tHSR 0 1 2 3 VALID VALID VALID VALID TMP19A44 (rev1.3) 27-24 2010-04-01 TMP19A44 27.10 SBI Timing (1) I2C mode In the table below, the letters x represent the fsys periods, respectively. n denotes the value of n programmed into the SCK (SCL output frequency select) field in the SBI0CR. Equation Standard mode Fast mode Min Max Min Max 0 100 0 400 Parameter Symbol SCL clock frequency tSC Hold time for START condition tHD:STA 4.0 0.6 s SCL clock low width (Input) (Note 1) Min Max 0 Unit kHz tLOW 4.7 1.3 s SCL clock high width (Output) (Note 2) tHIGH 4.0 0.6 s Setup time for a repeated START tSU;STA (Note 5) condition 4.7 0.6 s Data hold time (Input) (Note 3, 4) tHD;DAT 0.0 0.0 s Data setup time tSU;DAT 250 100 ns Setup time for STOP condition tSU;STO 4.0 0.6 s 4.7 1.3 s Bus free time between STOP and tBUF START conditions (Note 5) Note 1: SCL clock low width (output) is calculated with: (2n-1 +58)/(fsys/2) Note 2: SCL clock high width (output) is calculated with (2n-1 +12)/(fsys/2) Notice: On I2C-bus specification, Maximum Speed of Standard Mode is 100KHz ,Fast mode is 400Khz. Internal SCL clock Frequency setting should be shown above Note1 & Note2. Note 3: The output data hold time is equal to 12x Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the fall edge of SCL. However, this SBI does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the SCL and SDA lines. Note 5: Software-dependent tSCL tf tLOW tr tHIGH SCL tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF SDA S Sr P S: START condition Sr: Repeated START condition P: STOP condition Electrical Characteristics TMP19A44 (rev1.3) 27-25 2010-04-01 TMP19A44 (2) Clock-Synchronous 8-Bit SIO mode In the tables below, the letters x represent the fsys cycle periods, respectively. The letter n denotes the value of n programmed into the SCK (SCL output frequency select) field in the SBI0CR1. The electrical specifications below are for an SCK signal with a 50% duty cycle. 3) SCK Input mode Equation Symb ol Parameter 40/ 80 MHz Min Max Min Max Unit SCK period tSCY 16x 400 ns SCK Clock High width(input) TscH tSCY /2 200 ns SCKClock Low width(input) TscH tSCY /2 SO data to SCK rise tOSS (tSCY/2) - (6x + SO data hold after SCK rise tOHS SI data valid to SCK rise tSRD SI data hold after SCK rise tHSR 4x + 10 200 ns 30 ns (tSCY/2) + 4x 300 ns 0 0 ns 110 ns 20) 4) SCK Output mode Equation 40/ 80 MHz Symb ol Min SCK period (programmable) tSCY 2 T 800 ns SO data to SCK rise tOSS (tSCY/2) - 20 380 ns SO data hold after SCK rise tOHS (tSCY/2) - 20 380 ns SI data valid to SCK rise tSRD 2x + 30 55 ns SI data hold after SCK rise tHSR 0 0 ns Parameter n tSCY Unit 0 tOHS 1 2 tSRD Electrical Characteristics Max tSCL tOSS INPUT DATA TxD Min tSCH SCLK OUTPUT DATA TxD Max 3 tHSR 0 1 2 3 VALID VALID VALID VALID TMP19A44 (rev1.3) 27-26 2010-04-01 TMP19A44 27.11 Event Counter In the table below, the letter x represents the fsys cycle period. Parameter Symbol Equation Min Max 80 MHz Min Max Unit Clock low pulse width tVCKL 2X + 100 125 ns Clock high pulse width tVCKH 2X + 100 125 ns 27.12 Timer Capture In the table below, the letter x represents the fsys cycle period. Parameter Symbol Equation Min Max 80 MHz Min Max Unit Low pulse width tCPL 2X + 100 125 ns High pulse width tCPH 2X + 100 125 ns 27.13 General Interrupts In the table below, the letter x represents the fsys cycle period. Parameter Symbol Equation Min Max 80 MHz Min Max Unit Low pulse width for INT0-INTA tINTAL X + 100 112.5 ns High pulse width for INT0-INTA tINTAH X + 100 112.5 ns 27.14 STOP /SLEEP/SLOW Wake-up Interrupts Parameter Symbol Equation Min Max 80 MHz Min Max Unit Low pulse width for INT0-INTB tINTBL 100 100 ns High pulse width for INT0-INTB tINTBH 100 100 ns 27.15 SCOUT Pin Parameter Symbol Clock high pulse width tSCH Clock low pulse width tSCL Equation Min Max 0.5T - 5 0.5T - 5 80 MHz Min Max Unit 1.25 ns 1.25 ns Note: In the above table, the letter T represents the cycle period of the SCOUT output clock. tSCH SCOUT Electrical Characteristics tSCL TMP19A44 (rev1.3) 27-27 2010-04-01 TMP19A44 27.16 Bus Request and Bus Acknowledge Signals BUSRQ (Note1) BUSAK tBAA tABA (Note2) AD0~AD15 (Note2) A0~A23, RD , WR CS0 ~ CS3 , R / W , HWR ALE Parameter Symbol Equation 80 MHz Min Max Min Max Unit Bus float to BUSAK asserted tABA 0 80 0 80 ns Bus float after BUSAK negated tBAA 0 80 0 80 ns Note 1: If the current bus cycle has not terminated due to wait-state insertion, the TMP19A44 does not respond to BUSRQ until the wait state ends. Note 2: This broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. The pin holds the last logic value present at that pin before the bus is relinquished. This is dynamically accomplished through external load capacitances. The equipment manufacturer may maintain the bus at a predefined state by means of off-chip restores, but he or she should design, considering the time (determined by the CR constant) it takes for a signal to reach a desired state. The on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states. Electrical Characteristics TMP19A44 (rev1.3) 27-28 2010-04-01 TMP19A44 27.17 KWUP Input Parameter Equation Symbol Min 80 MHz Max Min Max Unit Low pulse width for KEY tkyTBL 100 100 ns High pulse width for KEY tkyTBH 100 100 ns 27.18 Dual Pulse Input Parameter Equation Symbol Min 80 MHz Max Min Max Unit Dual input pulse period Tdcyc TBD ns Dual input pulse setup Tabs TBD ns Dual input pulse hold Tabh Y :Sampling clock (fsys/2) TBD ns A Tabs B Tabh Tdcyc 27.19 ADTRG input Parameter Symbol Low pulse width for ADTRG tadL High pulse width for ADTRG Tadh Electrical Characteristics Equation Min fsysy/2 20 fsysy/2 20 Max 80 MHz Min Max Unit 26.25 ns 26.25 ns TMP19A44 (rev1.3) 27-29 2010-04-01 TMP19A44 27.20 EJTAG Parameter Symbol Equation Min 10 MHz(*) Max Min Max Unit TCK valid to TMS/TDI Data in Ttsetup 40 40 ns TMS/TDI hold after TCK negated Tthold 50 50 ns TDO hold after TCK asserted Ttout 10 10 ns * Operating Frequency of TCK is 10MHz only Ttclk TCK tTsetup INPUT DATA TMS,TDI tThold 0 1 2 3 VALID VALID VALID VALID OUTPUT DATA TDO tTOUT Electrical Characteristics TMP19A44 (rev1.3) 27-30 2010-04-01 TMP19A44 28. PKG P-TFBGA241-1212-A5 PKG TMP19A44 (rev1.3)28-1 2010/4/1 TMP19A44 29. RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. 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