AT89C51
3
The AT89C 51 pro vides the follo wing st andar d featur es: 4K
bytes of Flash, 128 byte s of RAM, 32 I/O l ines, two 16-bit
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock cir-
cuitry. In addition, the AT89C51 is designed with static logic
for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The
Power-down Mode saves the RAM contents but freezes
the osci ll ato r d isabl in g al l othe r c hi p fu nc tio ns unt il the n ex t
hardware reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 i s an 8-b it open-dra in bi-dir ectional I/O po rt. As an
output port, eac h pin can s ink eight TT L inputs . When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Por t 0 may al so be co nfigur ed to be t he mul tiplex ed low-
order address/data b us during accesses to external pro-
gram and data memory. In this mode P0 has internal
pullups.
Port 0 also receives the code bytes during Flash program-
ming, and outputs the code bytes during program
verific ation. Extern al pull ups are requi red dur ing pro gram
verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
externa l d ata m em or y that use 16-bi t ad dres se s ( MO VX @
DPTR). In this application, it uses strong internal pullups
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs ,
Port 3 pins that are externally being pulled low will sourc e
current (IIL) because of the pull ups .
Port 3 also serv es the fun ctions of v arious speci al fea tures
of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash
programming.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency, and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)