Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
19-3701; Rev 2; 1/12
Devices are available in a lead(Pb)-free/RoHS-compliant package.
Specify lead-free by adding a plus (+) to the part number when
ordering.
Ordering Information
Pin Configurations
Typical Operating Circuit
General Description
The MAX270/MAX271 are digitally-programmed, dual
second-order continuous-time lowpass filters. Their typi-
cal dynamic range of 96dB surpasses most switched
capacitor filters which require additional filtering to
remove clock noise. The MAX270/MAX271 are ideal for
anti-aliasing and DAC smoothing applications and can
be cascaded for higher-order responses.
The two filter sections are independently programmable
by either microprocessor (FP) control or pin strapping.
Cutoff frequencies in the 1kHz to 25kHz range can be
selected.
The MAX270 has an on-board, uncommitted op amp,
while the MAX271 has an internal track-and-hold (T/H).
Applications
Lowpass Filtering
Anti-Aliasing Filter
Output Smoothing
Low-Noise Applications
Anti-Aliasing and Track-and-Hold (MAX271)
Features
S Continuous-Time Filtering - No Clock Required
S Dual 2nd-Order Lowpass Filters
S Sections Independently Programmable: 1kHz to
25kHz
S 96dB Dynamic Range
S No External Components
S Cascadable for Higher Order
S Low-Power Shutdown Mode
S Track-and-Hold (MAX271)
V+
+5V -5V
FILTER A
ANTI-ALIASING
INA OUTAIN
V-GND
FILTER B
ANTI-ALIASING
AO CSD0-D6
µP OR PIN-STRAP CONTROL
OUTB INB
DSB
DAC
A/D WITH
T/H
OUT
WR
MAX270
OUTA
SHDN D4
1
2
20
19
OP OUT
V+ D6
D5
OP IN
PDIP/SO(W)
TOP VIEW
3
4
18
17
INB
OUTB D0
5
6
16
15
INA
V- D2
D1
D3
7
8
14
13
GND
Pin Configurations
continued at end
of data sheet.
A0
91
2
WR CS
10 11
MAX270
PART TEMP RANGE PIN-PACKAGE
MAX270CPP 0NC to +70NC20 PDIP
MAX270CWP 0NC to +70NC20 Wide SO
MAX270EPP -40NC to +85NC20 PDIP
MAX270EWP -40NC to +85NC20 Wide SO
MAX271CNG 0NC to +70NC20 PDIP
MAX271CWG 0NC to +70NC20 Wide SO
MAX271ENG -40NC to +85NC20 PDIP
MAX271EWG -40NC to +85NC20 Wide SO
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
2 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
V+ to V- .................................................................-0.3V to +17V
V+ to GND ............................................................ -0.3V to +8.5V
V- to GND .............................................................. -0.3V to -8.5V
Input Voltage to GND, Any Input Pin ....(V- - 0.3V) to (V+ + 0.3V)
Duration of Output Short Circuit to GND ...................Continuous
Continuous Power Dissipation (TA = +70NC)
MAX270
PDIP (derate 11.1mW/NC above +70NC) .....................889mW
SO (W) (derate 10mW/NC above +70NC ......................800mW
MAX271
PDIP (derate 13.3mW/NC above +70NC) ...................1067mW
SO (W) (derate 11.7mW/NC above +70NC) .................. 941mw
Operating Temperature Ranges:
MAX27_C_ _ ....................................................... 0NC to +70NC
MAX27_E_ _ .................................................... -40NC to +85NC
Storage Temperature Range ............................ -65NC to +165NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow)
Lead(Pb)-free ...............................................................+260NC
Containing lead(Pb) .....................................................+240NC
ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5V; TA = +25NC, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FILTER CHARACTERISTICS
Operating Frequency Range (Note 1) 2 MHz
Programmed Cutoff Frequency (fC)
Range 1 to 25 kHz
Programmed Cutoff Frequency
Error
fC code = 53 (2.536kHz typ) Q2.9 %
fC code = 127 (25kHz typ) Q9.5
Filter Gain
fC code = 0 (1kHz typ),
TA = TMIN to TMAX
fIN = 1kHz -3.6 -2.4
dB
fIN = 8kHz -33
fC code = 127 (25kHz typ),
TA = TMIN to TMAX
fIN = 25kHz -6 -0.5
fIN = 200kHz -34
Maximum Gain (Peaking) fC code = 0 (1kHz typ) 0.15 dB
fC code = 127 (25kHz typ) 0.15
Wideband Noise 50Hz to 50kHz bandwidth
fC code = 0
(1kHz typ) 12
FVRMS
fC code = 127
(25kHz typ) 38
DC CHARACTERISTICS
DC Output Signal Swing
OUTA, OUTB, OP OUT (MAX270)
OUTA, OUTB, T/H OUT (MAX271)
RLOAD = 5kI, TA = TMIN to TMAX -3 +3 V
Offset Voltage at Outputs
OUTA, OUTB, OP OUT (MAX270)
OUTA, OUTB, T/H OUT (MAX271)
-2 +2 mV
DC Input Leakage Current
INA, INB (MAX270)
INA, INB (MAX271)
TA = TMIN to TMAX -1 +1 FA
3Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V, V- = -5V; TA = +25NC, unless otherwise noted.)
Note 1: All internal amplifiers limited to 2MHz bandwidth.
Note 2: Only filter A tested for these parameters.
Note 3: Spurious-Free Dynamic Range is the ratio of the fundamental to the largest of any harmonic or noise spur in dB.
Note 4: Includes T/H propagation delays. With 5kω, parallel 100pF load.
Note 5: ±2V input step settling 0.1% with 5kω parallel 100pF load.
Note 6: T/H pin toggled at sampling rate, 50% duty cycle.
Note 7: THD and SFDR specifications for T/H include contributions from filter.
Note 8: Digital pins include SHDN, WR, CS, A0, D0–D6 (MAX270) and SHDN, T/H, A/B, WR, T/H EN, CS, A0, A1, D0–D6, T/H
(MAX271).
Note 9: Input of uncommitted op amp disconnected with a 5kω feedback resistor from input to output.
Note 10: WR, CS, A0, D0–D6 held at +5V; VSHDN = 0V (MAX270). WR, CS, A0, A1, D0–D6, T/H, T/H, A/B, T/H, MODE held at
+5V; VSHDN = 0V (MAX271).
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC FILTER CHARACTERISTICS (MAX270)
Total Harmonic Distortion THD fC code = 44 (2.01kHz typ), VIN = 3.5VP-P at
390.625Hz (Notes 2 and 3)
-70
dBSignal Noise Plus Distortion SINAD 73
Spurious-Free Dynamic Range SFDR 70
UNCOMMITTED AMPLIFIER (MAX270)
Slew Rate 1.2 V/Fs
Bandwidth 2 MHz
TRACK AND HOLD (MAX271)
Hold Settling Time To 0.1% (Note 4) 500 ns
Acquisition Time To 0.1% (Note 5) 1.8 Fs
Hold Step 1 mV
Droop Rate TA = TMIN to TMAX 30 FV/Fs
Offset Voltage at T/H OUT Includes filter offset -6 +6 mV
T/H OUT Disabled Output Leakage
Current TA = TMIN to TMAX, VT/H = 0V (Track Mode) -10 +10 FA
Total Harmonic Distortion THD fC code = 44 (2.01kHz typ), VIN = 3.5VP-P at
390.625Hz, sampling rate = 50kHz
(Notes 2, 6, 7)
-70
dB
Spurious-Free Dynamic Range SFDR 70
DIGITAL INPUTS
Digital Input High Voltage TA = TMIN to TMAX (Note 8) 2.4 V
Digital Input Low Voltage 0.8
Digital Input Current TA = TMIN to TMAX, digital input held at Q5V,
includes MODE (MAX271)(Note 8) -1 +1 FA
POWER REQUIREMENTS
Supply Voltage Range Q2.375
to Q8V
Supply Current TA = TMIN to TMAX (Note 9) 6.5 mA
Shutdown Supply Current TA = TMIN to TMAX (Note 10) 15 FA
Power-Supply Rejection Ratio at
1kHz PSRR fC code = 0 (1kHz typ), V+ = 5VDC +
10mVP-P at 1kHz 30 dB
4 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
TIMING CHARACTERISTICS (Figure 2)
(V+ = +5V, V- = -5V; TA = +25NC, unless otherwise noted.)
Note 11: All input control signals specified with tr = tf = 5ns (10% to 90% of +5V) and timed from a +1.6V voltage level.
Typical Operating Characteristics
FILTER GAIN vs. FREQUENCY
MAX270 toc01
fIN (Hz)
GAIN (dB)
100k10k
-60
-40
-20
0
-80
1k 1M
V+ = +5V
V- = -5V
fC CODE = 127 (25kHz TYP)
TA = +25˚C
FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
MAX270 toc02
fIN/fC
GAIN (dB)
101.0
-60
-40
-20
0
-80
0.1 100
V+ = +5V
V- = -5V
fC CODE = 0-127 (1-25kHz TYP)
TA = +25˚C
MAX270 toc03
fIN/fC
GAIN (dB)
10010
-2
-1
0
0.5
-3
11
k
V+ = +5V
V- = -5V
fC CODE = 0 (1kHz TYP)
TA = +125˚C
TA = +25˚C
TA = -55˚C
PASSBAND FILTER GAIN
vs. FREQUENCY
PASSBAND FILTER GAIN
vs. FREQUENCY
MAX270 toc04
fIN (Hz)
GAIN (dB)
1k 10k100
-2
-1
0
0.5
-3
25 25k
V+ = +5V
V- = -5V
fC CODE = 127 (25kHz TYP)
TA = +125˚C
TA = +25˚C
TA = -55˚C
MAX270 toc05
fIN/fC
GAIN (dB)
0.10.01
-2
-1
0
+0.5
-3
0.001 1.0
PASSBAND FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
V+ = +5V
V- = -5V
fC CODE = 0-127 (1-25kHz TYP)
TA = +25˚C
MAX270 toc06
fIN/fC
PHASE SHIFT (DEGREES)
1.00.1
-45
-90
-135
-180
0
0.01 10
FILTER PHASE SHIFT vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
V+ = +5V
V- = -5V
fC CODE = 0-127
(1-25kHz TYP)
TA = +25˚C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CS to WR Setup tWS 0 ns
CS to WR Hold tWH 0 ns
WR Pulse Width tSV 100 ns
Address-Setup Time tAS 30 ns
Address-Hold Time tAH 10 ns
Data-Setup Time tDS 30 ns
Data-Hold time tDH 10 ns
5Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Typical Operating Characteristics (continued)
MAX270 toc07
fIN/fC
GAIN (dB)
0.1
-1.5
-0.5
-3.5
-2.5
-5.5
-4.5
-7.5
-6.5
+0.5
0.01 1.0
CASCADED FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
V+ = +5V
V- = -5V
fC (FILTER A) = fC (FILTER B) =
0-127 (1-25kHz TYP)
FILTERS A AND B CASCADED
FIGURE 5
TA = +25˚C
MAX270 toc08
fIN/fC
GAIN (dB)
1.0
-80
-20
-40
-60
0
0.01 10
CASCADED FILTER GAIN vs. FREQUENCY
(NORMALIZED TO CUTOFF FREQUENCY)
V+ = +5V
V- = -5V
fC (FILTER A) = fC (FILTER B) =
0-127 (1-25kHz TYP)
FILTERS A AND B CASCADED
FIGURE 5
TA = +25˚C
MAX270 toc09
F (Hz)
GAIN (dB)
1k 2k 3k
-120
-20
-40
-100
-80
-60
0
04
k
FILTER HARMONIC DISTORTION
V+ = +5V
V- = -5V
fC CODE = 44 (2.01kHz TYP)
fTEST = 390.625Hz
TA = +25˚C
VIN = 3.5VP-P
MAX270 toc10
V+ = 5V, V- = -5V; VIN = 3.5VP-P; TA = +25˚C
FILTER TOTAL HARMONIC DISTORTION
PLUS NOISE vs.INPUT FREQUENCY
fIN
(Hz)
fC
CODE
fC
(Hz)
(TYP)
THD PLUS
NOISE
(TYP)
190 01k -78
390
1367
4875
44
100
127
2.01k
7.01k
25k
-73
-67
-66
MAX270 toc11
VIN (VP-P)
GAIN (dB)
1.0
-85
-60
-65
-70
-75
-80
0.2 8.0
FILTER TOTAL HARMONIC DISTORTION
PLUS NOISE vs. INPUT AMPLITUDE
V+ = +5V
V- = -5V
fIN = 390.625Hz
fC CODE = 44 (2.01kHz TYP)
TA = +25˚C
MAX270 toc14
MAX271 FILTER PLUS TRACK-AND-HOLD
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING FREQUENCY
fSAMPLE
(Hz)
100k
200k
500k
fIN
(Hz)
781
1562
3906
fC
CODE
72
105
124
SFDR
(dB)
72
72
64
fC
(Hz)
4.01k
8.08k
19.4k
V+ = 5V, V- = -5V; VIN = 3.5VP-P;
T/H SWITCHED AT 50kHz, 50% DUTY CYCLE; TA = +25˚C
MAX270 toc13
VIN (VP-P)
SFDR (dB)
1.0
-85
55
65
75
0.5 8.0
MAX271 FILTER PLUS TRACK-AND-HOLD
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT AMPLITUDE
V+ = +5V
V- = -5V
fIN = 390Hz
fC CODE = 44 (2.01kHz TYP)
TA = +25˚C
MAX270 toc12
MAX271 FILTER PLUS TRACK-AND-HOLD
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT FREQUENCY
fIN
(Hz)
fC
CODE
fC
(Hz)
(TYP)
SFDR
(dB)
195 01k 73.5
781
1562.5
3906
72
105
124
4.01k
8.08k
19.4k
69.5
66
61.5
V+ = 5V, V- = -5V; VIN = 3.5VP-P;
T/H SWITCHED AT 50kHz, 50% DUTY CYCLE; TA = +25˚C
6 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Pin Description Detailed Description
Figures 1a, 1b, and 1c show the MAX270/MAX271 func-
tional diagrams. Both the MAX270 and MAX271 contain
two independent, second-order, Sallen-Key, lowpass
filter sections, A and B to provide a frequency vs. gain
rolloff of approximately 40dB/decade. These are not
switched-capacitor filters, but have a continuous-time
design similar to discrete active filters built around op
amps. The MAX270/MAX271 eliminate clock noise and
aliasing problems which limit low-noise performance of
switched-capacitor filters; resulting dynamic range is
over 96dB.
Each filter section contains two banks of programmable
capacitors, controlled by an internal 7-bit memory, which
set filter cutoff frequencies (fC) from 1kHz to 25kHz. The
filters provide two program modes. In FP mode, cutoff
frequencies are programmed by writing 7-bit data to one
of two memory addresses (one for each filter section).
Alternately, a pin-strap programming mode programs
both filter sections simultaneously. In this mode, both
memory latches are transparent (not addressable), and
data pins D0–D6 may be pin-strapped (hard-wired) to
set a common fC for both filter sections.
The filters are trimmed at the wafer level, setting 0 for
a maximum of 0.15dB passband peaking for fC pro-
grammed to 1kHz. Maximum passband peaking at other
codes is typically less than 0.15dB. Filter Q is not user-
programmable.
The MAX270 includes an uncommitted op amp (nonin-
verting input grounded); the MAX271 has an on-chip T/H
that tracks and holds the output of either filter section
(selectable). The held output is provided at T/H OUT. T/H
functions are controlled by writing control bits to internal
registers (in FP mode) or by control pins directly (in pin-
strap mode).
The MAX270 and MAX271 provide a low quiescent cur-
rent shutdown mode controlled by the SHDN pin, which
turns off internal amplifiers and disconnects all outputs,
reducing quiescent operating current to less than 15FA.
When the MAX271 is in FP mode, shutdown mode is
selected by writing control bits to memory (the SHDN
pin is disabled).
MAX270
Note: All digital input levels are TTL and CMOS compatible,
unless otherwise noted.
PIN NAME FUNCTION
1 OP OUT Uncommitted Op Amp Output
2 V+ Positive Supply Voltage
3 OUTA Filter A Output
4SHDN
Shutdown Control. Low level
disconnects OUTA, OUTB, and OP OUT
and places device into shutdown mode.
5 INA Filter A Input
6 V- Negative Supply Voltage
7 INB Filter B Input
8 OUTB Filter B Output
9 GND Ground
10 WR
Write Control Input. A low level writes
data D0–D6 to program memory
addressed by A0. High level latches
data.
11 CS Chip-Select Input. Must be low for WR
input to be recognized.
12 A0
Three-Level Address Input
Logic High: Addresses filter A
Logic Low: Addresses filter B
Connect to V-: Pin-strap mode
13-
19 D0–D6
7-Bit Data Inputs. Allows programming
of 128 cutoff frequencies in a 1kHz to
25kHz range.
20 OP IN Uncommitted Op Amp Input
7Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Pin Description (continued)
MAX271
X = Pin has no function in this mode.
Note: All digital input levels are TTL and CMOS compatible, unless otherwise noted.
PIN NAME FUNCTION, FP MODE (MODE = GND OR V-) FUNCTION, FP MODE (MODE = GND OR V+)
1 T/H OUT Track-and-Hold Output
2 V+ Positive Supply Voltage
3 OUTA Filler A Signal Output
4SHDN —SHUTDOWN Control. A low level disconnects outputs
and places device into shutdown mode
5 INA Filter A Signal Input
6 V- Negative Supply Voltage
7 INB Filter B Signal Input
8 MODE Selects FP mode when connected to GND or V- and pin-strap mode when connected to V+.
9 OUTB Filter B Signal Output
10 GND Ground
11 T/H A/B—Track-and-Hold Input Control. A high/low level internally
connects OUTNOUTB to input of Track-and-Hold
12 WR
WRITE Control Input. A low level writes data
D0-D6 program memory addressed by A1, A0
(or performs function as described for address
inputs). High level latches data.
—
13 T/H EN X Track-and-Hold Output Control. Low level disconnects
T/H OUT. Connect pin high for normal operation
14 CS Chip Select Input. Must be low for WR input to
be recognized. —
15, 16 A1, A0
Address and FP Control Inputs.
0, 0 Programs fC, filter A
0, 1 Programs fC, filter B
1,0 Controls T/H functions:
D0 performs T/H En pin function
D1 performs T/H A/B pin function.
1,1 Controls device shutdown:
D0 performs SHDN pin function
Note: The WR pin must be strobed low to initiate
a program/function (Figure 2).
—
17-23 D0–D6
7-bit Data Inputs. Allows programming of
128 cutoff frequencies (also performs control
functions as described above).
7-bit Data Inputs. Program memory latches are trans-
parent in this mode. Connect pins high or low to
program filters A and B simultaneously to the same fC.
24 T/H Track-and-Hold Control. Low level causes T/H OUT to track selected filter output. Filter output level held at
T/H OUT synchronous with T/H rising transition.
8 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Figure 1a. MAX270 Block Diagram
Figure 1b. MAX271 Block Diagram—µP Mode
LATCH
CONTROL
fC LATCH A
D0-D6
13-19
5
INA
OUTA
2
1011
WR
6
V+ V-
9
GND
fC LATCH B
EN 3
7
20
INB
OP IN
OUTB
OP OUT
EN 8
1
12 4
A0 SHDN
CS
EN
MAX270
µP MODE
CONTROL
fC LATCH A
D0-D6
17-23
5INA
OUTA
T/H OUT
OUTB
2
1516
A1
6
V+ V-
10
GND
fC LATCH B
LATCH
CONTROL
EN
EN
3
1
9
7
INB
14 12
CS WR SHDN* T/H*
A/B
T/H
A0
*PIN HAS NO FUNCTION IN µP MODE.
D1
D0
MAX271
EN
8 MODE
T/H*
EN
TO V+
µP
MODE
4112413
9Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Figure 1c. MAX271 Block Diagram—Pin-Strap Mode
Filter Programming
Cutoff Frequency
fC is the frequency of 3dB attenuation in the filter
response.
Table 1 shows how data pins D0–D6 allow programming
of 128 cutoff frequencies from 1kHz to 25kHz.
The equations for calculating fC from the programmed
code are as follows:
−
−
−
−
=
=
=
=
C
C
C
C
87.5
f x1kHz forcodes0 63
87.5 CODE )
(f 1kHz to3.57kHz
262.5
f x1kHz for codes 64 127
137.5 CODE (f kHz to kHz)
3.57 25
where CODE is the data on pins D0–D6 (0–127). D6 is
the most significant bit (MSB).
Actual cutoff frequencies are subject to some error for
each programmed code. Highest accuracy occurs at
CODE = 0 where filters are trimmed for a 1kHz cut-
off frequency. At higher codes, CODE vs. fC errors
increase; the frequency error at CODE = 127 {highest
code) remains typically within Q9.5%. This means that
the actual filter cutoff frequency, when programmed to
CODE = 127, falls between 22.63kHz and 27.38kHz.
DIRECT
CONTROL
D0-D6
17-23
5INA
OUTA
T/H OUT
OUTB
2
1516
A1*
6
V+ V-
10
GND
EN
EN
3
1
9
7
INB
14 12 4
CS* WR* SHDN*
11
T/H*
A/B
24
TO GND OR V-
T/H
A0*
*PIN HAS NO FUNCTION IN PIN-STRAP MODE.
EN
13
T/H*
EN
PIN-STRAP
MODE
8
MAX270
MODE
10 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Table 1. Programmed Cutoff Frequency Codes (typ)
Programmed code is the data on pins D0–D6 (0–127). D6 is the MSB.
PROGRAMMED
CODE fC (kHz) PROGRAMMED
CODE fC (kHz) PROGRAMMED
CODE
fC
(kHz)
PROGRAMMED
CODE fC (kHz)
0
1
.
000
32
1
.
576
64
3.571
96
6
.
325
1
1
.
0
11
33
1.605
65
3
.
620
97
6
.
481
2
1
.
0
23
34
1.635
66
3
.
671
98
6
.
645
3
1
.
035
35
1
.
666
67
3
.
723
99
6
.
8
18
4
1
.
047
36
1
.
699
68
3
.
777
100
7
.
008
5
1.060
37
1.732
69
3
.
832
101
7.191
6
1
.
073
38
1.767
70
3
.
888
102
7.394
7
1.087
39
1
.
804
71
3.947
103
7
.
608
8
1
.
100
40
1
.
842
72
4
.007
104
7
.
835
9
1
.
114
41
1.881
73
4
.
0
69
105
8
.
076
10
1
.
129
42
1
.
923
74
4
.
133
106
8
.
333
11
1
.
143
43
1
.
966
75
4.200
107
8.606
12
1
.
158
44
2
.
011
76
4.268
108
8.898
13
1.174
45
2
.
058
77
4.338
109
9.210
14
1
.
190
46
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.
108
78
4.411
110
9
.
5
45
15
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206
47
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160
79
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487
111
9
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905
16
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223
48
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215
80
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.
5
65
112
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294
17
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241
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81
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113
10.714
18 1
1
.
259
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82
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114
11
.
170
19
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.
277
51
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83
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.
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115
11
.
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20
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.
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52
2.464
84
4.906
116
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.
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85
5.000
117
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16.935
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125
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.
000
11Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Table 2. MAX271 µP-Mode Interface
MAX270 Control Interlace
The A0 pin is a three-level input that selects the memory
addresses for updating cutoff frequency data in FP mode:
Figure 2 shows µP-mode interface timing.
Connecting A0 to the negative supply selects pin-strap
mode. Pin-strap mode allows filter programming with
no timing requirements. Internal memory latches are
disabled, permitting filters A and B to be programmed
directly to fC data strapped on D0–D6. This mode dis-
ables CS and WR controls, and filters A and B are pro-
grammed to the same fC.
A low level on the SHDN pin shuts down all amplifiers
and disconnects OUTA, OUTB, and OP OUT. Current
consumption drops to less than 15µA in this mode.
MAX271 Control Interlace
Connecting the MODE pin to GND or V- selects the
µP mode. In this mode, addressable program memory
controls filter cutoff frequency programming and all T/H
functions, except T/H. See the Figure 2 for timing charac-
teristics. Table 2 describes available functions:
In FP mode, SHDN, T/H A/B, and T/H EN pins are dis-
abled. T/H remains enabled and performs the T/H track-
ing/holding function.
Tying MODE to V+ selects pin-strap mode. In this mode,
both memory latches are transparent, and data on D0–D6
controls the fC of filters A and 8 directly (filters A and 8
are programmed to the same fC). Pin strap D0–D6 for
operation without FP. A0, A1, CS, and WR are disabled.
X = Don't care
Figure 2. MAX270/MAX271 Digital Timing Diagram
CS
tWS tWH
tWR
tAS
WR
ADDRESS
(A0, A1)
DATA
(D0-D6)
NOTE : ALL DIGITAL INPUTS ARE LEVEL-SENSITIVE. WHEN WR AND CS ARE BOTH LOW,
THE DATA INPUT LATCHES ARE TRANSPARENT. AND THE FILTERS ARE
PROGRAMMED TO THE DATA ON D0–D6
tAH
tDS tDH
A0 SELECTS
Logic Low Filter B
Logic High Filter A
A1 A0 06 05 04 03 02 01 D0 FUNCTION
0 0 7-bit fC data Selects
f
ilte
r
A
0 1 7-bit fC data Selects
f
il
t
e
r
B
1 0 X X X X X X 0 T/H OUT
disabled
1 0 X X X X X X 1 T/H OUT
e
n
ab
le
d
1 0 X X X X X 0 X Selects OUTB as
input
to
T
/H
1 0 X X X X X 1 X Selects OUTA as input
to
T
/H
1 1 X X X X X X 0 Filter shutdown mode. All outputs floated, 15µA
max supply current
1 1 X X X X X X 1 Removes filter from shutdown mode
12 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Digital Threshold Levels
All digital inputs are TTL and CMOS compatible, unless
otherwise stated. Inputs are CMOS gates with less than
1µA leakage current and 8pF capacitance loading.
Typical logic voltage thresholds are a function of the V+
supply voltage as shown below (voltages are referenced
to GND).
Filter Performance
All MAX270/MAX271 internal amplifier and output stages
for filter sections. uncommitted op amp, and T/H are
identical. The outputs are designed to drive 5kω in paral-
lel with a maximum capacitance of 100pF. At higher load
levels, the output swing becomes asymmetric. All outputs
can be short circuited to GND for an indefinite duration.
The MAX270/MAX271 operating frequency range is
limited to approximately 2MHz by the bandwidth of the
internal amplifiers.
Filter Noise
Wideband filter noise over a 50kHz bandwidth is
12µVRMS and 38µVRMS per section for fC programmed
to 1kHz and 25kHz, respectively. A dynamic range of
over 96dB results.
Filter Input Impedance
At DC, the input impedance at INA and INB is equal to
the DC input impedance of the amplifier, which is about
5Mω. At higher frequencies, internal capacitors contrib-
ute to an effective input impedance that may fall as low
as 100kω at 25kHz.
MAX271 Track-and-Hold
The MAX271 T/H is functionally equivalent to a switched
200pF capacitor buffered by a unity-gain amplifier (Figures
1b and 1c). When the T/H pin is driven low, the output of
filter A or filter B (whichever is selected via control inter-
face) internally connects to the amplifier, and T/H OUT
follows the filter output. The offset at T/H OUT (±6mV max)
is the combined offset of the filter amplifier and the T/H
buffer. When T/H is pulled high, the switch disconnects
the filter signal from the T/H. The T/H capacitor holds the
stored charge, and that voltage is buffered at T/H OUT.
A low level at T/H EN disconnects T/H OUT, enabling mul-
tiplexed operation (Figure 3). T/H A/B selects between
OUTA and OUTB as the T/H input. In FP mode, the T/H
EN and T/H OUT functions are controlled by writing con-
trol bits to program memory, with T/H EN and T/H OUT
pins disabled.
See the Typical Operating Characteristics graphs for T/H
dynamic accuracy.
Note: For +5V single-supply operation, where incoming logic
signals are referenced to V-, typical logic thresholds are +3.5V.
Therefore, a CMOS (rail-to-rail) logic interface is recommended.·
Figure 3. MAX271 Multiplexed Operation
AY0
T/H OUT
T/H EN
CH1
Y1
INA
Y2
Y7
B
C
CHANNEL
SELECT
74HC238
T/H OUT
T/H EN
CH3
INA
T/H OUT
T/H EN
CH2
INA
OUTPUT
V+ (V) LOGIC THRESHOLD
VOLTAGE (V)
8 +2.4
7 +2.3
6 +2.0
5 +1.75
4 +1.5
2.5 +1.0
13Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Applications Information
Power-Supply Configurations
The MAX270/MAX271 power supplies must be properly
bypassed. Best performance is achieved if V+ and V- are
bypassed to GND with 4.7µF electrolytic (tantalum is pre-
ferred) and 0.1µF ceramic capacitors in parallel. These
should be as close as possible to the chip supply pins.
Single supplies in the range of 4.75V to 16V may be
used to power the MAX270/MAX271 as shown in Figure
4. Digital logic may be referenced to V- (system ground),
but will not maintain TTL compatibility. CMOS (rail-to-
rail) logic recommended. For µP-mode operation with a
single supply, the MAX270 A0 pin must be configure with
a voltage divider (Figure 4).
Lowest quiescent current in shutdown mode is achieved
when A0 is either at V+ or V-.
Independent fC Programming Without a µP
Figure 6 shows how filter sections A and B may be pro-
grammed to different cutoff frequencies without the use
of a µP. The MAX690 µP supervisory circuit provides the
proper programming sequence when the circuit is pow-
ered up by controlling the 74HC373 data buffer and the
MAX270 addressing pin to load independent fC data for
filters A and B.
Figure 4. Power-Supply Configurations
V+
A0
(MAX270)
SINGLE-SUPPLY OPERATION
GND
V-
4.7kI
10kI
PIN-STRAP
MODE
µP
MODE 0V
+5V
+5V
10kI
4.7kI4.7µF 0.1µF
0.1µF
4.7µF
+5V
MAX270
V+
BIPOLAR-SUPPLY OPERATION
GND
V-
4.7µF 0.1µF
0.1µF
4.7µF
+5V
-5V
MAX270
MAX271
14 Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Figure 5. Cascading Filter Sections
Figure 6. Independent fC Programming without a µP
OUTBINA
58
OUPUT fC = 1kHz
80dB/dec. ROLLOFF
OUTA
INB
3
7
SHDN 4+5V
-5V
V+ 2
MAX270 A0
D5
D6
D4
D3
D2
D1
D0
12
V- 6
11
10
OP IN 20
GND 9
16
15
17
18
19
14
13
WR
CS
INPUT
SIGNAL
OUTBOP OUT
D6
MAX270
MAX690
WR
GND
FILTER SECTION A
+5V
OUTB
INB
V--5V
INA
SHDNSIGNAL B
SIGNAL A
+5V
OUTA
100kI
6
D6
D5
100kI
100kI
4.7kI
5
D5
D4
100kI
4
D4
D3
100kI
3
D3
D2
100kI
2
D2
D1
100kI
1
D1
D0
A0
CS
100kI
0
D0
PFO
WDI
RESET
VBATTVOUT
VCC
GND
PFI
0.1µF
0.1µF
+5V
0
1
2
34
5
VCC
OC
8D
74HC373
1Q
TO D0
TO D1
TO D2
TO D3 TO D4
TO D5
+5V
+5V
GND
4Q
4D
3D
3Q
2Q
2D
1D
7D
7Q
6Q
6D
5D
5Q
C
V++5V
6
TO D6
8Q
FILTER SECTION B
STRAP PINS HIGH/LOW TO SET FILTER tC DATA.
FILTER DATA RELOADED ON EACH POWER-UP.
15Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Chip Information
PROCESS: BiCMOS
Pin Configurations (continued)
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
OUTA
SHDN D4
1
2
24
23
T/H OUT
V+ D6
D5
T/H
3
4
22
21
INB
MODE D0
5
6
20
19
INA
V- D2
D1
D3
7
8
18
17
OUTB A0
91
6
GND A1
10 15
T/H A/BCS
11 14
PDIP/SO(W)
WR T/H EN12 13
MAX271
TOP VIEW
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 PDIP P20-2 21-0043 —
20 SO (W) W20-3 21-0042 90-0108
24 PDIP N24-3 21-0043 —
24 SO (W) W24-2 21-0042 90-0182
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
16 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/91 Initial release —
1 8/91 Revised Electrical Characteristics 2
2 1/12 Revised Ordering Information and Absolute Maximum Ratings. 1, 2
