_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
General Description
The MAX98400A/MAX98400B Class D amplifiers provide
high-performance, thermally efficient amplifier solutions. The
MAX98400A delivers 2x20W into 8I loads or 1x40W into a
4I load. The MAX98400B delivers 2x12W into 8I loads.
An integrated limiting circuit prevents output clipping
distortion, protects small speakers from transient volt-
ages, and reduces power dissipation.
A thermal-foldback feature can be enabled to automati-
cally reduce the output power at above a junction tem-
perature of +120NC. Traditional thermal protection is also
available in addition to robust overcurrent protection.
The ICs operate from a single 8V to 28V supply and
provide a high 67dB PSRR, eliminating the need for a
regulated power supply. They offer up to 90% efficiency
from a 12V supply.
Filterless modulation allows the ICs to pass EN55022B
EMI limits with 1m cables using only a low-cost ferrite
bead and small-value capacitor on each output.
Both devices feature eight digitally controlled gain settings.
Comprehensive click-and-pop reduction circuitry mini-
mizes noise coming into and out of shutdown.
The MAX98400A/MAX98400B are available in 36-pin
and 24-pin TQFN packages, respectively, and are speci-
fied over the -40NC to +85NC temperature range.
Features
S Wide 8V to 28V Supply Voltage Range
S Single-Supply Operation
S Low EMI: Active Emissions Limiting
S Clipping Limiter
S Low Quiescent Current
S Thermal Foldback
S Thermal and Overcurrent Protection
Applications
LCD/PDP Televisions
LCD Monitors
MP3 Docking Stations
Notebook PCs
Ordering Information
19-5286; Rev 0; 6/10
Simplified Block Diagram
Note: Devices operate over the -40°C to +85°C temperature
range.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART PIN-PACKAGE SPEC
MAX98400AETX+ 36 TQFN-EP* 2x20W
MAX98400BETG+ 24 TQFN-EP* 2x12W
INR-
INR+
OUTR-
OUTR+
PGA
CLIPPING
LIMITER
CLASS D
MODULATOR
AND H-BRIDGE
INL-
INL+
OUTL-
OUTL+
MONO*
PGA
CLIPPING
LIMITER
CLASS D
MODULATOR
AND H-BRIDGE
*MAX98400A ONLY
MAX98400A/B
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
2
Table of ConTenTs
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stereo Configuration for MAX98400A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Mono Configuration for MAX98400A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Efficiency..................................................................................16
Shutdown..................................................................................16
Click-and-Pop Suppression ...................................................................16
Mono Configuration..........................................................................16
Clipping Limiter.............................................................................16
Limiter Threshold Control (LIM_TH)...........................................................17
Release Time Control (RELEASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Preamplifier Gain Setting .....................................................................18
Protection .................................................................................18
Thermal Foldback ........................................................................18
Overtemperature Protection.................................................................18
Overcurrent Protection.....................................................................18
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Filterless Class D Operation ...................................................................18
Inductor-Based Output Filters..................................................................19
Component Selection ........................................................................19
Input Capacitor...........................................................................19
Power Supplies...........................................................................19
Internal Regulator VS ......................................................................19
Supply Bypassing, Layout, and Grounding .......................................................19
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
3
lisT of figures
Figure 1. MAX98400B EMI Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2. MAX98400A Efficiency vs. Class AB Effifciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Limiter Control, Mode3 Configuration (Table 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. Output Filter for PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
lisT of Tables
Table 1. Limiter Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Gain Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. Filter Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
4
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PVDD to PGND ......................................................-0.3V to +30V
VS to GND ...............................................................-0.3V to +6V
SHDN, MONO to GND ............................................-0.3V to +6V
IN_ to GND ..............................................................-0.3V to +6V
G1, G2, RELEASE, TEMPLOCK,
LIM_TH to GND ........................................ -0.3V to (VS + 0.3V)
OUT_ to PGND ......................................-0.3V to (VPVDD + 0.3V)
PGND to GND ......................................................-0.3V to +0.3V
Continuous Current into OUT_ .......................................... +2.4A
Continuous Current into PVDD, PGND ............................. +4.8A
Continuous Current into All Other Pins ........................... +10mA
Duration of OUT_ Short Circuit to PVDD or PGND ...Continuous
Duration of Short Circuit Between
OUT_+ and OUT_- .................................................Continuous
Continuous Power Dissipation (TA = +70NC)
36-Pin TQFN Multilayer Board
(derate 35.7mW/NC above +70NC) .........................2857.1mW
BJA (Note 1) .............................................................28NC/W
BJC (Note 1) ...............................................................1NC/W
24-Pin TQFN Multilayer Board
(derate 27.8mW/NC above +70NC) .............................35.7mW
BJA (Note 1) .............................................................36NC/W
BJC (Note 1) ...............................................................3NC/W
Junction Temperature .....................................................+150NC
Operating Temperature Range .......................... -40NC to +85NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VPVDD = 18V, CIN = 1FF, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CREL
= 1FF, C1 = C2 = 1FF, RL = J, AC measurement bandwidth 20Hz to 20kHz, differential input signal, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Notes 2, 3)
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AMPLIFIER DC CHARACTERISTICS
PVDD Supply Voltage Range VPVDD Inferred from PVDD_PSRR 8 28 V
VS Supply Input Voltage VSInferred from IVS test 4.75 5.5 V
Quiescent Current IPVDD Dual-supply mode:
VS = 4.75V, TA = +25NC
10 15 mA
IVS 6 8.2
Single-Supply
Quiescent Current IPVDD
Single-supply mode:
TA = +25NC16 23 mA
RL = 8I (Note 3) 17
Shutdown Current ISHDN_PVDD VSHDN = 0V, TA = +25NC,
VS = 5.5V
8 20 FA
ISHDN_VS 3 10
PVDD Undervoltage Lockout VUVLO 7 7.9 V
VS Regulator Output Voltage VS4.2 4.47 4.75 V
INPUT STAGE
Differential Input Voltage Range 2 VRMS
Single-Ended Input Voltage
Range 1 VRMS
Common-Mode Rejection Ratio CMRR 60 dB
Input Resistance Differential VLIM_TH = 0V, gain = +35dB 20 32 kI
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
5
ELECTRICAL CHARACTERISTICS (continued)
(VPVDD = 18V, CIN = 1FF, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CREL
= 1FF, C1 = C2 = 1FF, RL = J, AC measurement bandwidth 20Hz to 20kHz, differential input signal, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER STAGE
Shutdown to Full Operation tSON 11 ms
Gain Accuracy Q0.8 Q4%
Left-to-Right Gain Matching All gain settings Q2%
Crosstalk 1kHz -85 dB
10kHz -68
Output Offset Voltage VOS TA = +25NCQ8Q45 mV
Click-and-Pop Level KCP
Peak voltage,
32 samples/s,
A-weighted,
TA = +25NC (Notes 4, 5)
Into
shutdown -47
dBV
Out of
shutdown -56
PVDD Power-Supply Rejection
Ratio PSRRPVDD
VPVDD = 8V to 28V 52 63
dB1kHz, 100mVP-P ripple 67
10kHz, 100mVP-P ripple 57
VS Power-Supply Rejection Ratio PSRRVS
VS = 4.75V to 5.5V 39 55
dB1kHz, 100mVP-P ripple 50
10kHz, 100mVP-P ripple 40
MAX98400A Output Power POUT
Stereo, RL = 8I, 10% THD+N,
fIN = 1kHz (Note 3) 22
W
Mono, RL = 4I, 10% THD+N,
fIN = 1kHz (Note 3) 44
MAX98400B Output Power POUT Stereo, RL = 8I, 10% THD+N,
fIN = 1kHz (Note 3) 15
Total Harmonic Distortion Plus
Noise THD+N
POUT = 0.1W to POUT/2, fIN = 20Hz to
20kHz, RL = 8I 0.3 %
POUT/2, fIN = 1kHz, RL = 8I0.03
Output Noise VNA-weighted 100 FVRMS
Efficiency EPOUT = 2x20W, RL = 8I (MAX98400A)
fIN = 1kHz (Note 3) 90 %
Current Limit ILIM 3.5 5 A
Output FET Resistance RDSON 0.4 I
Switching Frequency fSW 265 330 395 kHz
Peak Output Voltage VPVDD = 28V 20 26 V
LIMITER
Attack Time VLIM_TH = 0V 240 500 Fs
Release Time VLIM_TH = 0V 0.8 s
Maximum Trigger Level VPVDD = 14V (Note 6) 4 dBFS
Minimum Trigger Level (Note 7) -6 dBFS
Trigger Level VLIM_TH = 0V -1 0 +1 dBFS
Compression Range VLIM_TH = 0V -12 dB
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
6
Note 2: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 3: The MAX98400A stereo mode is specified with an 8I resistive load in series with a 68FH inductive load connected across
BTL outputs. The MAX98400A mono mode is specified with a 4I resistive load in series with 33FH inductive load. The
MAX98400B is specified with an 8I resistive load in series with a 68FH inductive load connected across BTL outputs.
Note 4: Amplifier inputs AC-coupled to GND.
Note 5: Mode transitions controlled by SHDN.
Note 6: Relative to equivalent full-scale undistorted output. Full scale (FS) = VPVDD x 0.95.
Note 7: Relative to equivalent full-scale undistorted output. Full scale (FS) = VPVDD.
ELECTRICAL CHARACTERISTICS (continued)
(VPVDD = 18V, CIN = 1FF, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CREL
= 1FF, C1 = C2 = 1FF, RL = J, AC measurement bandwidth 20Hz to 20kHz, differential input signal, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25NC.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VGA Distortion Compression = 0 to -12dB 3.5 %
LIM_TH Input-Voltage Low
(PVDD Tracking) 0.15 V
LIM_TH Input-Voltage High
(Limiter Off)
VS
- 1 V
Channel-to-Channel Attenuation
Tracking Q1dB
THERMAL FOLDBACK
Internal Templock Resistor 120 205 310 kI
Trigger Temperature +130 NC
Hard Thermal Protection +165 NC
LOGIC INPUT (G1, G2)
Sink Current TA = +25NC, VG1, VG2 = 0V +2.5 +5 +8 FA
Source Current TA = +25NC, VG1, VG2 = VS-8 -5 -2.5 FA
Input High Threshold 0.8 x
VSV
Input Low Threshold 0.3 x
VSV
Input Three-State Window 0.45 x
VS
0.5 x
VS
0.55 x
VSV
LOGIC INPUT (SHDN, MONO (MAX98400A Only))
Input Leakage Current IIN TA = +25NCQ10 FA
Input High Threshold VINH 2 V
Input Low Threshold VINL 0.4 V
Input-Voltage Hysteresis 100 mV
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
7
Typical Operating Characteristics
(MAX98400A, VPVDD = 18V, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CIN =
CREL = C1 = C2 = 1FF, typical values are at TA = +25NC, unless otherwise noted.)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98400 toc01
FREQUENCY (kHz)
THD+N (%)
1010.1
0.01
0.1
1
0.001
0.01 100
POUT = 0.5W
VPVDD = 12V
8I LOAD
POUT = 4W
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98400 toc02
FREQUENCY (kHz)
THD+N (%)
1010.1
0.01
0.1
1
0.001
0.01 100
POUT = 1W
VPVDD = 12V
4I LOAD
POUT = 7W
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98400 toc03
FREQUENCY (kHz)
THD+N (%)
1010.1
0.01
0.1
1
0.001
0.01 100
POUT = 1W VPVDD = 18V
8I LOAD
POUT = 10W
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
MAX98400 toc04
OUTPUT POWER (W)
THD+N (%)
108642
0.01
0.1
1
10
0.001
0 12
f = 6kHz
f = 1kHz
VPVDD = 12V
8I LOAD
f = 100Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
MAX98400 toc05
OUTPUT POWER (W)
THD+N (%)
20161284
0.01
0.1
1
10
0.001
0 24
f = 6kHz
f = 1kHz
VPVDD = 18V
8I LOAD
f = 100Hz
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
MAX98400 toc06
OUTPUT POWER (W)
THD+N (%)
403224168
0.01
0.1
1
10
0.001
0 48
f = 6kHz
f = 1kHz
f = 100Hz
VPVDD = 24V
RL = 8I
STOPS BEFORE 10% THD+N
DUE TO THERMAL LIMITING OF
THERMAL FOLDBACK FEATURE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
MAX98400 toc07
OUTPUT POWER (W)
16
14121086420 18
THD+N (%)
0.01
0.1
1
10
0.001
f = 6kHz
f = 1kHz
f = 100Hz VPVDD = 12V
4I LOAD
EFFICIENCY vs. OUTPUT POWER
MAX98400 toc08
TOTAL OUTPUT POWER (W)
EFFICIENCY (%)
181612 144 6 8 102
10
20
30
40
50
60
70
80
90
100
0
0 20
VPVDD = 12V,
8I LOAD,
BOTH CHANNELS DRIVEN
EFFICIENCY vs. OUTPUT POWER
MAX98400 toc09
TOTAL OUTPUT POWER (W)
35
3020 2510 1550 40
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VPVDD = 18V,
8I LOAD,
BOTH CHANNELS DRIVEN
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
8
Typical Operating Characteristics (continued)
(MAX98400A, VPVDD = 18V, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CIN =
CREL = C1 = C2 = 1FF, typical values are at TA = +25NC, unless otherwise noted.)
MAX98400 toc10
TOTAL OUTPUT POWER (W)
50
403020100 60
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VPVDD = 24V,
8I LOAD,
BOTH CHANNELS DRIVEN
MAX98400 toc11
TOTAL OUTPUT POWER (W)
30
20100 40
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VPVDD = 12V,
4I LOAD,
BOTH CHANNELS DRIVEN
MAXIMUM OUTPUT POWER vs. SUPPLY VOLTAGE
(WITH THERMAL SHUTDOWN)
MAX98400 toc12
SUPPLY VOLTAGE (V)
MAXIMUM OUTPUT POWER (W)
24201612
10
20
30
40
50
60
70
80
90
100
0
8 28
8I LOAD, BOTH
CHANNELS ARE DRIVEN
10% THD+N
1% THD+N
MAXIMUM OUTPUT POWER vs. SUPPLY VOLTAGE
(WITH THERMAL SHUTDOWN)
MAX98400 toc13
SUPPLY VOLTAGE (V)
MAXIMUM OUTPUT POWER (W)
141210
10
20
30
40
50
60
0
8 16
10% THD+N
1% THD+N
4I LOAD, BOTH CHANNELS ARE DRIVEN
OUTPUT POWER vs. LOAD
MAX98400 toc14
LOAD (I)
POUT (W)
908010 20 30 50 6040 70
5
10
15
20
25
30
35
40
0
0 100
VPVDD = 12V
10% THD+N
1% THD+N
OUTPUT POWER vs. LOAD
MAX98400 toc15
LOAD (I)
POUT (W)
908060 7020 30 40 5010
5
10
15
20
25
30
35
40
45
50
0
0 100
10% THD+N
1% THD+N
VPVDD = 18V
OUTPUT POWER vs. LOAD
MAX98400 toc16
LOAD (I)
POUT (W)
908010 20 30 50 6040 70
10
20
30
40
50
60
70
80
0
0 100
10% THD+N
1% THD+N
VPVDD = 24V
POWER-SUPPLY REJECTION RATIO
MAX98400 toc17
FREQUENCY (kHz)
PSRR (dB)
1010.1
-70
-60
-50
-40
-30
-20
-10
0
10
-80
0.01 100
100mVP-P RIPPLE
FREQUENCY (kHz)
1100
CROSSTALK (dB)
100.10.01
CROSSTALK vs. FREQUENCY
MAX98400 toc18
-80
-60
-40
-20
0
8I LOAD,
POUT = 1W,
f = 1kHz
20
-100
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
9
Typical Operating Characteristics (continued)
(MAX98400A, VPVDD = 18V, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CIN =
CREL = C1 = C2 = 1FF, typical values are at TA = +25NC, unless otherwise noted.)
INBAND OUTPUT SPECTRUM
MAX98400 toc19
FREQUENCY (kHz)
OUTPUT AMPLITUDE (dBV)
15105
-100
-80
-60
-40
-20
0
-120
0 20
8I LOAD
FREQUENCY (MHz)
OUTPUT AMPLITUDE (dBV)
1010.1 100
WIDEBAND OUTPUT SPECTRUM
MAX98400 toc20
-100
-80
-60
-40
-20
0
-120
RBW = 100Hz
MAX98400 toc21
OUTPUT
2V/div
4ms/div
SHDN ON/OFF RESPONSE
SHDN
2V/div
SUPPLY CURRENT
vs. PVDD SUPPLY VOLTAGE
MAX98400 toc22
PVDD SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2420
IPVDD
VS = 5V
1612
2
4
6
8
10
12
14
0
8 28
IVS
SUPPLY CURRENT
vs. VS SUPPLY VOLTAGE
MAX98400 toc23
VS SUPPLY VOLTAGE (V)
5.25
5.004.75 5.50
SUPPLY CURRENT (mA)
2
4
6
8
10
12
14
0
IPVDD
VPVDD = 18V
IVS
SHUTDOWN CURRENT
vs. PVDD SUPPLY VOLTAGE
MAX98400 toc24
PVDD SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (µA)
24201612
2
4
6
8
10
12
14
0
8 28
IPVDD_SHDN
VS = 5V
IVS_SHDN
SHUTDOWN CURRENT
vs. VS SUPPLY VOLTAGE
MAX98400 toc25
VS SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (µA)
5.255.00
2
4
6
8
10
12
14
0
4.75 5.50
IPVDD_SHDN
IVS_SHDN
VPVDD = 18V
PVDD SUPPLY VOLTAGE (V)
MAXIMUM POUT (W)
2420
8I LOAD
1612
10
20
30
40
50
60
0
8 28
MAXIMUM OUTPUT POWER
vs. PVDD (NO THERMAL SHUTDOWN)
MAX98400 toc26
4I LOAD
THERMAL FOLDBACK DISABLED,
BOTH CHANNELS DRIVEN
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (MONO)
MAX98400 toc27
FREQUENCY (kHz)
THD+N (%)
1010.1
0.01
0.1
1
0.001
0.01 100
POUT = 8W
POUT = 1W
VPVDD = 12V
4I LOAD
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
10
Typical Operating Characteristics (continued)
(MAX98400A, VPVDD = 18V, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CIN =
CREL = C1 = C2 = 1FF, typical values are at TA = +25NC, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (MONO)
MAX98400 toc28
OUTPUT POWER (W)
THD+N (%)
20161284
0.01
0.1
1
10
0.001
0 24
f = 6kHz
f = 100Hz
f = 1kHz
VPVDD = 12V,
4I LOAD
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (MONO)
MAX98400 toc29
OUTPUT POWER (W)
THD+N (%)
403224168
0.01
0.1
1
10
0.001
0 48
f = 6kHz
f = 100Hz
f = 1kHz
VPVDD = 18V,
4I LOAD
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (MONO)
MAX98400 toc30
OUTPUT POWER (W)
THD+N (%)
70605040302010
0.01
0.1
1
10
0.001
0 80
f = 6kHz
f = 100Hz
f = 1kHz
VPVDD = 24V,
4I LOAD
EFFICIENCY vs. OUTPUT POWER (MONO)
MAX98400 toc31
TOTAL OUTPUT POWER (W)
EFFICIENCY (%)
15105
10
20
30
40
50
60
70
80
90
100
0
0 20
VPVDD = 12V,
4I LOAD
MAX98400 toc32
353020 2510 1550 40
EFFICIENCY vs. OUTPUT POWER (MONO)
TOTAL OUTPUT POWER (W)
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VPVDD = 18V,
4I LOAD
MAX98400 toc33
353020 2510 1550 40
EFFICIENCY vs. OUTPUT POWER (MONO)
TOTAL OUTPUT POWER (W)
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VPVDD = 24V,
4I LOAD
MAXIMUM OUTPUT POWER
vs. PVDD (WITH THERMAL SHUTDOWN, MONO)
MAX98400 toc34
PVDD SUPPLY VOLTAGE (V)
MAXIMUM POUT (W)
242016128 28
10
20
30
40
50
60
70
80
90
100
04I LOAD, THERMAL FOLD DISABLED
10% THD+N
1% THD+N
OUTPUT POWER vs. LOAD (MONO)
MAX98400 toc35
LOAD (I)
POUT (W)
908070605040302010
5
10
15
20
25
0
0 100
VPVDD = 12V
10% THD+N
1% THD+N
OUTPUT POWER vs. LOAD (MONO)
MAX98400 toc36
POUT (W)
5
10
15
20
25
30
35
40
45
50
0
LOAD (I)
9080706050403020100 100
VPVDD = 18V
10% THD+N
1% THD+N
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
11
Typical Operating Characteristics (continued)
(MAX98400A, VPVDD = 18V, VSHDN = 5V, LIM_TH = VS, TEMPLOCK = unconnected; G1 = GND, G2 = open (gain = 20.1dB), CIN =
CREL = C1 = C2 = 1FF, typical values are at TA = +25NC, unless otherwise noted.)
OUTPUT POWER vs. LOAD (MONO)
MAX98400 toc37
LOAD (I)
POUT (W)
908010 20 30 50 6040 70
10
20
30
40
50
60
70
80
0
0 100
VPVDD = 24V
10% THD+N
1% THD+N
SUPPLY CURRENT
vs. PVDD SUPPLY VOLTAGE (MONO)
MAX98400 toc38
PVDD SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
24201612
2
4
6
8
10
12
14
0
8 28
VS = 5V
IPVDD
IVS
SUPPLY CURRENT
vs. VS SUPPLY VOLTAGE (MONO)
MAX98400 toc39
VS SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.255.00
2
4
6
8
10
12
14
0
4.75 5.50
VPVDD = 18V
IPVDD
IVS
PVDD SUPPLY VOLTAGE (V)
MAXIMUM POUT (W)
24201612
10
20
30
40
50
60
0
8 28
MAXIMUM OUTPUT POWER
vs. PVDD (NO THERMAL SHUTDOWN, MONO)
MAX98400 toc40
4I LOAD, THERMAL FOLD DISABLED
LIMITER TRANSFER CHARACTERISTIC
MAX98400 toc41
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.52.01.51.00.5
2
4
6
8
10
12
14
16
18
20
22
24
0
0 3.0
RL = 8I + 68µH
LIM_TH = GND
VPVDD = 8V
VPVDD = 18V
VPVDD = 24V
MAX98400 toc42
OUTPUT
4V/div
200ms/div
tRELEASE
LIMITER RELEASE TIME
INPUT
2V/div
LIM_TH = GND
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
12
Pin Descriptions
Pin Configurations
N.C.
INR+
GND
GND
INL+
LIM_TH
MONO
INL-
INR-PGND
PVDD
PVDD
PGND
PGND
N.C.
N.C. 18
17
16
15
14
13
12
11
10
OUTL+
VS
N.C.
G2
OUTL+
N.C.
OUTL-
OUTL-
OUTR-
N.C.
OUTR+
OUTR+
N.C.
SHDN
RELEASE
TEMPLOCK
OUTR-
TQFN
TOP VIEW
PVDD
G1
PGND
1 2 3 4 5 6 7 8
28
29
30
31
32
33
34
35
36
9
27 26 25 24 23 22 21 20 19
+EP
TQFN
19
20
21
22
1 2 3 4 5 6
18 17 16 15 14 13
23
24
12
11
10
9
8
7
PGND
PVDD
PGND
PVDD
PGND
OUTL-
OUTL-
OUTL+
VS
G1
G2
OUTR
-
OUTR
-
SHDN
RELEASE
TEMPLOCK
PGND
INR+
GND
INR-
INL-
LIM_TH
INL+
OUTR+
TOP VIEW
+EP
MAX98400A
MAX98400B
PIN NAME FUNCTION
MAX98400A MAX98400B
1, 2 1, 2 OUTL- Negative Left Speaker Output
3, 7, 18, 22,
25, 28, 36 — N.C. No Connection
4, 5 3 OUTL+ Positive Left Speaker Output
6 4 VS5V Regulator Supply. Bypass VS to GND with a 1μF capacitor. Connect to a
+5V source for dual-supply operation.
8 5 G1 Three-State Input for Gain Selection 1. See the Detailed Description section.
9 6 G2 Three-State Input for Gain Selection 2. See the Detailed Description section.
10 7 LIM_TH
See the Limiter Threshold Control (LIM_TH) section for details.
Connect to:
1) VS to disable limiter.
2) GND to have no clipping.
3) RLIM1 resistor to GND to have a PVDD tracking threshold.
4) RLIM1 and RLIM2 resistor-divider to have an absolute threshold.
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
13
Pin Descriptions (continued)
PIN NAME FUNCTION
MAX98400A MAX98400B
11 8 INL+ Left-Channel Positive Analog Input
12 9 INL- Left-Channel Negative Analog Input
13 — MONO Mono Operation. Connect MONO to GND for stereo operation. Connect MONO
to VS for mono operation.
14, 15 10 GND Analog Ground
16 11 INR- Right-Channel Negative Analog Input
17 12 INR+ Right-Channel Positive Analog Input
19 13 TEMPLOCK
See the Thermal Foldback section for details.
Connect to:
1) GND to disable thermal foldback.
2) Leave open to enable thermal foldback.
20 14 RELEASE Sets the Limiter Time Constant. Connect to GND through 1FF.
21 15 SHDN
Active-Low Shutdown Input
Low = shutdown
High = enable
23, 24 16 OUTR+ Positive Right Speaker Output
26, 27 17, 18 OUTR- Negative Right Speaker Output
29, 30, 34, 35 19, 20,
23, 24 PGND Power Ground
31, 32, 33 21, 22 PVDD Power Supply. Bypass PVDD to PGND with 1FF and 200FF capacitors.
— — EP Exposed Pad. Connect to PGND for optimum thermal performance.
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
14
Stereo Configuration for MAX98400A
INL+
OUTL+
OUTL-
OUTR+
OUTR-
11
4, 5
1, 2
23, 24
26, 27
INL-
TEMPLOCK
12
19
PGA
CLIPPING
LIMITER
REGULATOR
THERMAL
FOLDBACK
INR+ 17
INR- 16
PGA
CLIPPING
LIMITER
LIMITER
CONTROL
GAIN
SELECTION
BIAS AND
OSCILLATOR
LIM_TH
10
6
VS
RELEASE
20
31, 32, 33
PVDD
G1
8
G2
9
SHDN
ENABLE
21
GND
14, 15
PGND
29, 30,
34, 35
POWER
STAGE
WITH THERMAL
AND
OVERCURRENT
PROTECTION
MONO 13
C2
1.0µF
CIN
1.0µF
CIN
1.0µF
CIN
1.0µF
CREL
1.0µF
CIN
1.0µF
C1
1.0µF
MAX98400A
CBULK
200µF
8V TO 28V
LEFT
INPUT
RIGHT
INPUT
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
15
Mono Configuration for MAX98400A
Detailed Description
The MAX98400A/MAX98400B Class D amplifiers pro-
vide high-performance, thermally efficient amplifier solu-
tions. The MAX98400A delivers 2x20W into 8I loads or
1x40W into a 4I load. The MAX98400B delivers 2x12W
into 8I loads.
An integrated limiting circuit prevents output clipping
distortion and protects small speakers from transient
voltages.
A thermal-foldback feature can be enabled to automati-
cally reduce the output power if the supply voltage, input
signal, and/or ambient temperature are too high to oper-
ate within a junction temperature of +130NC. Traditional
thermal protection is also available in addition to robust
overcurrent protection.
Both devices operate from an 8V to 28V supply and pro-
vide a high 67dB PSRR, eliminating the need for a regu-
lated power supply. They offers up to 90% efficiency
from a 12V supply.
Filterless modulation allows the ICs to pass EN55022B
EMI limits with 1m cables using only a low-cost fer-
rite bead and small-value capacitor on each output
(Figure 1).
Comprehensive click-and-pop reduction circuitry mini-
mizes noise coming into and out of shutdown.
MAX98400A
INL+
OUTL+
OUTL-
OUTR+
OUTR-
11
MONO 13
4, 5
1, 2
23, 24
26, 27
INL-
TEMPLOCK
12
19
PGA
CLIPPING
LIMITER
REGULATOR
THERMAL
FOLDBACK
INR+ 17
INR- 16
PGA
CLIPPING
LIMITER
LIMITER
CONTROL
GAIN
SELECTION
BIAS AND
OSCILLATOR
LIM_TH
10
6
VS
VS
RELEASE
20
31, 32, 33
PVDD
G1
8
G2
9
SHDN
ENABLE
21
GND
14, 15
PGND
29, 30,
34, 35
POWER
STAGE
WITH THERMAL
AND
OVERCURRENT
PROTECTION
C2
1.0µF
C1
1.0µF
CBULK
200µF
CREL
1.0µF
CIN
1µF
CIN
1µF
CIN
1µF
CIN
1µF
8V TO 28V
LEFT
INPUT
RIGHT
INPUT
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
16
The MAX98400A/MAX98400B are available in 36-pin
and 24-pin TQFN packages, respectively, and are
specified over the -40NC to +85NC temperature range.
Efficiency
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as switches
and consume negligible power. Power loss associated
with the Class D output stage is due to the I2R loss of the
MOSFET on-resistance, various switching losses, and
quiescent current overhead.
The theoretical best efficiency of a linear amplifier is 78%
at peak output power. Under typical music reproduction
levels, the efficiency falls below 30%, whereas these
ICs exhibit > 85% efficiency under the same conditions
(Figure 2).
Shutdown
The ICs feature a shutdown mode that reduces power
consumption and extends battery life in portable appli-
cations. The shutdown mode reduces supply current to
8FA (typ). Drive SHDN high for normal operation. Drive
SHDN low to place the device in low-power shutdown
mode. In shutdown mode, the outputs are high imped-
ance and the common-mode voltage at the output
decays to zero. The shutdown mode serves as a mute
function.
Click-and-Pop Suppression
The ICs feature comprehensive click-and-pop suppres-
sion that minimizes audible transients on startup and
shutdown. While in shutdown, the H-bridge is in a high-
impedance state.
Mono Configuration
The MAX98400A features a mono mode that allows the
right and left channels to operate in parallel, achieving
up to 40W of output power. Apply a logic-high (VS) to
MONO to enable mono mode. In mono mode, an audio
signal applied to the left channel (INL) is routed to the
H-bridges of both channels. Connect OUTL+ to OUTR+
and OUTL- to OUTR- using heavy PCB traces as close
as possible to the device. Driving MONO low (stereo
mode) while the outputs are wired together in mono
mode can trigger the short-circuit or thermal-overload
protection, or both.
Clipping Limiter
The ICs feature a programmable clipping limiter to pre-
vent output clipping distortion and excessive power dis-
sipation and to protect small speakers. All limiter func-
tionality is controlled by two pins: LIM_TH and RELEASE.
The voltage applied at the LIM_TH pin controls the
threshold when the limiter acts, and the capacitor at the
RELEASE pin controls the release time of the limiter. The
limiter controls both left and right channels together.
Figure 1. MAX98400B EMI Performance Figure 2. MAX98400A Efficiency vs. Class AB Efficiency
FREQUENCY (MHz)
AMPLITUDE (dBµV/m)
0
10
20
30
40
-10
10030 1000
EFFICIENCY vs. OUTPUT POWER
TOTAL OUTPUT POWER (W)
EFFICIENCY (%)
15105
10
20
30
40
50
60
70
80
90
100
0
0 20
MAX98400A
CLASS AB
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
17
Limiter Threshold Control (LIM_TH)
There are three modes for the limiter, defined by VLIM_TH,
the voltage applied to the LIM_TH pin (Table 1).
In Mode1, the limiter is disabled. The output clips when
output peak voltage reaches the voltage on PVDD, VPVDD.
In Mode2, the limiter threshold (VTHRESH) tracks supply
voltage, VPVDD. The peak output voltage is limited to
approximately VTHRESH = VPVDD x 0.95.
In Mode3, the limiter threshold, VTHRESH, is program-
mable. VLIM_TH can be set to a voltage proportional to
the desired output threshold. The limiter threshold can
be set down to 0.5 x VPVDD and up to 1.6 x VPVDD.
VTHRESH cannot exceed 22V.
Threshold settings below VPVDD can be used to protect
speakers; the peak output voltage is limited to a value of
VTHRESH = VLIM_TH x 6.4.
Threshold settings above VPVDD can be used to limit the
output distortion; the peak output voltage is limited to a
value of VTHRESH = VLIM_TH x 6.4 x 0.95. The 0.95 fac-
tor takes into account the voltage drop across the power
FET that occurs when the amplifier is clipped. Choose
RLIM1 and RLIM2 (Figure 3) to set the desired voltage at
the LIM_TH pin. For best accuracy, the parallel combina-
tion RLIM1||RLIM2 should be approximately 100kI.
Example:
If the speaker in the application can handle only
12V peak, but VPVDD is higher, the threshold voltage
(VTHRESH) should be set to 12V:
VTHRESH = 12V
The voltage that needs to be applied to VLIM_TH is then
defined as:
VLIM_TH = VTHRESH/6.4 = 12V/6.4 = 1.88V
For a 5V supply, a resistor-divider of RLIM1 = 165kI/
RLIM2 = 270kI gives both an unloaded voltage of 1.82V
and the desired output resistance of approximately
100kI.
If only distortion limiting is desired, set VTHRESH to be
20% higher than VPVDD. This limits the output clipping
levels to approximately 10% THD.
The attack time for the limiter is fixed, typically < 200Fs.
Release Time Control (RELEASE)
The release time for the limiter is set by an external
capacitor at RELEASE (CREL) to GND. Choose CREL =
Release Time [s] x 1FF. The CREL limit is 2.2FF.
Table 1. Limiter Control Modes
Note: VTHRESH is the output peak limiting voltage (limiter threshold voltage).
Figure 3. Limiter Control, Mode3 Configuration (Table 1)
MODE NAME FUNCTION LIM_TH VOLTAGE
RANGE
Mode1 Disable The limiter is disabled when connecting LIM_TH to VS or a voltage greater
than 3.9V. 3.9V < VLIM_TH P VS
Mode2 PVDD tracking
The output peak voltage is limited to just below the supply voltage,
VPVDD. VTHRESH = VPVDD x 0.95 when LIM_TH is connected to ground or
a voltage below 0.3V.
VGND P VLIM_TH <
0.15V
Mode3 Programmable
The output peak voltage, VTHRESH, is limited to the threshold set by the
voltage applied on the LIM_TH so that VTHRESH = VLIM_TH x 6.4.
When VTHRESH is set 20% higher than VPVDD, the output THD distortion is
limited to 10%.
0.6V P VLIM_TH P 3.8V
MAX98400A
MAX98400B
VS
REGULATOR
LIMITER
CONTROL
RLIM2
RLIM1
LIM_TH RELEASE
VS
PVDD
PVDD 18V
C1
1.0µF
C2
1.0µF
CREL
1.0µF
PVDD
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
18
Preamplifier Gain Setting
The ICs offer eight pin-selectable gain settings, select-
able through the G1 and G2 pins.
Protection
The ICs feature overcurrent protection and two types of
thermal protection: thermal foldback and overtempera-
ture protection.
Thermal Foldback
The ICs feature thermal foldback that helps prevent
unwanted thermal-shutdown events. If activated, ther-
mal foldback attenuates the stereo output signal once
the internal junction temperature exceeds +130NC.
Attenuation is applied proportionally as the junction tem-
perature (TJ) exceeds the fixed +130NC threshold. The
thermal-foldback mode is controlled by the TEMPLOCK
pin.
Overtemperature Protection
The ICs feature an overtemperature protection that dis-
ables the amplifier if the junction temperature exceeds
+165NC. Once the amplifier is disabled and the die tem-
perature has cooled by 20NC, the devices enable again
and resume normal operation.
Overcurrent Protection
When the output current reaches the current limit, 5A
(typ), the ICs disable the outputs and initiate a recovering
sequence. The shutdown and recovering sequence is
repeated until the output fault is removed.
Applications Information
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filters add cost, increase the solution size of the
amplifier, and can decrease efficiency and THD+N
performance. The traditional PWM scheme uses large
differential output swings (2 x VDD peak-to-peak) and
causes large ripple currents. Any parasitic resistance in
the filter components results in a loss of power, lowering
the efficiency.
These ICs do not require an output filter. The devices
rely on the inherent inductance of the speaker coil and
the natural filtering of both the speaker and the human
ear to recover the audio component of the square-wave
output. Eliminating the output filter results in a smaller,
lower cost solution.
Because the frequency of the ICs’ output is well beyond
the bandwidth of most speakers, voice coil movement
due to the square-wave frequency is very small. For
optimum results, use a speaker with a series inductance
> 10FH. Typical 8I speakers exhibit series inductances
in the 20FH to 100FH range.
Table 2. Gain Selection
G1 G2 GAIN SETTING
(dB)
GND GND 9
Unconnected GND 13
VSGND 16.7
GND Unconnected 20.1
Unconnected Unconnected 23.3
VSUnconnected 26.4
GND VS29.8
Unconnected VS32.9
VSVSReserved
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
19
Inductor-Based Output Filters
Some applications use the ICs with a full inductor-/
capacitor-based (L/C) output filter. See Figure 4 for the
correct connections of these components.
The load impedance of the speaker determines the filter
component selection (Table 3).
Inductors L1 and L2 and capacitor C1 form the primary
output filter. Capacitors C2 and C3 provide common-
mode filtering to reduce radiated emissions. Capacitors
C4 and C5, plus resistors R1 and R2, form a Zobel at
the output. A Zobel corrects the output loading to com-
pensate for the rising impedance of the loudspeaker.
Without a Zobel, the filter exhibits a peak response near
the cutoff frequency.
Component Selection
Input Capacitor
The input AC-coupling capacitors allow the amplifier to
automatically bias the signal to an optimum DC level.
1FF is recommended for the input capacitor.
Power Supplies
The ICs are designed to be operated from a single-
supply voltage, VPVDD, which can range from 8V to 28V.
Inside the ICs, this VPVDD supplies power for the output
FETs and other high-power circuitry, while the low-power
circuitry operates from VS, an internally generated 5V
supply (4.6V typ). VS is internally generated from a lin-
ear regulator that is powered from VPVDD. Bypass both
PVDD and VS pins to ground with a 1FF capacitor.
Internal Regulator VS
For highest efficiency operation and best thermal perfor-
mance, especially at higher VPVDD levels, the VS can be
supplied from an external 5V supply. To do this, connect
a 5V source to the VS pin (4.75V to 5.5V). When a 5V
supply is connected to the VS pin, the internal regulator
is automatically disabled and the power dissipation of
the ICs is reduced.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use wide traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Proper grounding improves
audio performance, minimizes crosstalk between chan-
nels, and prevents switching noise from coupling into
the audio signal. Connect PGND and GND together at
a single point on the PCB. Route all traces that carry
switching transients away from GND and the traces/
components in the audio signal path.
Bypass each PVDD pin with a 0.1FF capacitor to PGND.
Place the bypass capacitors as close as possible to the
ICs. Place a 220FF capacitor between PVDD and PGND.
Bypass both PVDD and VS pins with a 1FF capacitor to
GND.
Use wide, low-resistance output traces. Current drawn
from the outputs increases as load impedance decreas-
es. High-output trace resistance decreases the power
delivered to the load. The TQFN package features an
exposed thermal pad on its underside. This pad lowers
the package’s thermal resistance by providing a heat
conduction path from the die to the PCB. Connect the
exposed thermal pad to PGND by using a large pad and
multiple vias to the PGND plane.
For best optimum thermal performance, use 2oz copper
and allow lots of PCB area around the device.
Chip Information
PROCESS: CMOS
Figure 4. Output Filter for PWM Mode
Table 3. Filter Component Selection
MAX98400A/B
C3
L1
L2
C2
C1
C5
R2
C4
R1
RL (I)L1, L2 (µH) C1 (µF) C2, C3 (µF) C4, C5 (µF) R1, R2 (I)
4 10 0.47 0.10 0.22 10
8 15 0.15 0.15 0.15 15
16 33 0.10 0.10 0.10 33
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
20
Functional Diagrams
MAX98400A
INL+
OUTL+
OUTL-
OUTR+
OUTR-
11
MONO 13
4, 5
1, 2
23, 24
26, 27
INL-
TEMPLOCK
12
19
PGA
CLIPPING
LIMITER
REGULATOR
THERMAL
FOLDBACK
INR+ 17
INR- 16
PGA
CLIPPING
LIMITER
LIMITER
CONTROL
GAIN
SELECTION
BIAS AND
OSCILLATOR
LIM_TH
10
6
VS
RELEASE
20
31, 32, 33
PVDD
G1
8
G2
9
SHDN
21
GND
14, 15
PGND
29, 30,
34, 35
POWER
STAGE
WITH THERMAL
AND
OVERCURRENT
PROTECTION
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
21
Functional Diagrams (continued)
MAX98400B
INL+
OUTL+
OUTL-
OUTR+
OUTR-
8
3
1, 2
16
17, 18
INL-
TEMPLOCK
9
13
PGA
CLIPPING
LIMITER
REGULATOR
THERMAL
FOLDBACK
INR+ 12
INR- 11
PGA
CLIPPING
LIMITER
LIMITER
CONTROL
GAIN
SELECTION
BIAS AND
OSCILLATOR
LIM_TH
7
4
VS
RELEASE
14
21, 22
PVDD
G1
5
G2
6
SHDN
15
GND
10
PGND
19, 20,
23, 24
POWER
STAGE
WITH THERMAL
AND
OVERCURRENT
PROTECTION
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
22
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
36 TQFN-EP T3666+2 21-0141 90-0052
24 TQFN-EP T2444+4 21-0139 90-0068
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
23
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
24
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
25
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
Stereo, High-Power, Class D Amplifiers
MAX98400A/MAX98400B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/10 Initial release —
