Supertex inc.
Supertex inc.
www.supertex.com
Doc.# DSFP-VN10K
B031411
VN10K
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiVN
10K
YYWW
Features
►Free from secondary breakdown
►Low power drive requirement
►Ease of paralleling
►Low CISS and fast switching speeds
►Excellent thermal stability
►Integral source-drain diode
►High input impedance and high gain
Applications
►Motor controls
►Converters
►Ampliers
►Switches
►Power supply circuits
►Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
General Description
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefcient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
N-Channel Enhancement-Mode
Vertical DMOS FET
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±30V
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
TO-92
Product Marking
Package may or may not include the following marks: Si or
Pin Conguration
TO-92
GATE
SOURCE
DRAIN
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
IDSS
(min)
60V 5.0Ω750mA
Typical Thermal Resistance
Package θja
TO-92 132OC/W
Ordering Information
Part Number Package Option Packing
VN10KN3-G TO-92 1000/Bag
VN10KN3-G P002
TO-92 2000/Reel
VN10KN3-G P003
VN10KN3-G P005
VN10KN3-G P013
VN10KN3-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
2
Supertex inc.
www.supertex.com
Doc.# DSFP-VN10K
B031411
VN10K
Electrical Characteristics (TA = 25OC unless otherwise specied)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 60 - - V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage 0.8 - 2.5 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature - -3.8 - mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage - - 100 nA VGS = 15V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10
µA
VGS = 0V, VDS = 45V
- - 500 VGS = 0V, VDS = 45V,
TA = 125°C
ID(ON) On-state drain current 0.75 - - A VGS = 10V, VDS = 10V
RDS(ON) Static drain-to-source on-state resistance - - 7.5 ΩVGS = 5.0V, ID = 200mA
- - 5.0 VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature - 0.7 - %/OC VGS = 10V, ID = 500mA
GFS Forward transductance 100 - - mmho VDS = 10V, ID = 500mA
CISS Input capacitance - 48 60
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance - 16 25
CRSS Reverse transfer capacitance - 2.0 5.0
t(ON) Turn-on time - - 10
ns
VDD = 15V,
ID = 600mA,
RGEN = 25Ω
t(OFF) Turn-off time - - 10
VSD Diode forward voltage drop - 0.8 - V VGS = 0V, ISD = 500mA
trr Reverse recovery time - 160 - ns VGS = 0V, ISD = 500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Notes:
† ID (continuous) is limited by max rated Tj . (VN0106N3 can be used if an ID (continuous) of 500mA is needed.)
Switching Waveforms and Test Circuit
90%
10%
90% 90%
10%
10%
Pulse
Generator
VDD
RL
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
r
INPUT
INPUT
OUTPUT
10V
VDD
RGEN
0V
0V
tf
Thermal Characteristics
Package ID
(continuous)†
ID
(pulsed)
Power Dissipation
@TC = 25OCIDR
†IDRM
TO-92 310mA 1.0A 1.0W 310mA 1.0A
3
Supertex inc.
www.supertex.com
Doc.# DSFP-VN10K
B031411
VN10K
Typical Performance Curves
Transconductance vs Gate-Source Voltage
Gfs (m )
ID (amperes)
GFS (mhos)
Output Conductance vs Drain Current
On-Resistance vs. Gate-to-Source Voltage
RDS(ON) (ohms)
BVDSS (normalized)
Tj (OC)
Transfer Characteristics
ID (amperes)
Capacitance vs. Drain-to-Source Voltage
50
40
30
20
10
0
C (picofarads)
VDS (volts)
VGS (volts)
BVDSS Variation with Temperature
0 10 20 30 40 50
0 2.0 4.0 6.0 8.0 10
-50 0 50 100 150
1.1
1.0
0.9
100
10
1.0
1.0 10 100
1.0
0.8
0.6
0.4
0.2
0
250
200
150
100
50
0
Ω
VGS (volts)
1.0
0.1
0.01
0.01 0.1 1.0
VDS = 0.1V
Reduction
Due to
Heating
VDS = 25V
80µs, 1%
Duty Cycle,
Pulse Test
VDS = 10V
3000µs, 2%
Duty Cycle
Pulse Test
CISS
C
OSS
CRSS
VGS (volts)
VDS = 10V
300µs, 2%
Duty Cycle,
Pulse Test
0 2.0 4.0 6.0 8.0 10
4
Supertex inc.
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Doc.# DSFP-VN10K
B031411
VN10K
Typical Performance Curves (cont.)
Output Characteristics
1.0
0.8
0.6
0.4
0.2
0
V
DS
(volts)
I
D
(amperes)
Saturation Characteristics
1.0
0.8
0.6
0.4
0.2
0
Maximum Rated Safe Operating Area
1.0 10 100 1000
10
1.0
0.1
0.01
V
DS
(volts)
Switching Waveform
10
5.0
0
15
10
5.0
0
0 10 20 30 40 50
t – Time (ns)
Transconductance vs. Drain Current
250
200
150
100
50
0
0 200 400 600 800 1000
G
FS
(m )
I
D
(mA)
Power Dissipation vs. Case Temperature
0 25 50 75 100 125 150
2.0
1.0
0
T
C
(
O
C)
P
D
(watts)
TO-92
V
DS
= 10V
300µs, 2%
Duty Cycle,
Pulse Test
TO-92 (DC)
0 10 20 30 40 50
6V
5V
4V
2V
0 2.0 4.0 6.0 8.0 10
6V
4V
2V
3V
Ω
Output Voltage
(volts)
5V
3V
9V
8V
7V
TC = 25OC
V
DS
(volts)
I
D
(amperes)
VGS = 10V
Input Voltage
(volts)
I
D
(amperes)
VGS = 10V
7V8V
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
5
VN10K
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-VN10K
B031411
3-Lead TO-92 Package Outline (N3)
Symbol A b c D E E1 e e1 L
Dimensions
(inches)
MIN .170 .014†.014†.175 .125 .080 .095 .045 .500
NOM - - - - - - - - -
MAX .210 .022†.022†.205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
Seating
Plane
1
2
3
Front View Side View
Bottom View
E1 E
D
e1
L
e
c
1 2 3
b
A