ACPL-330J
1.5 Amp Output Current IGBT Gate Driver Optocoupler
with Integrated (VCE) Desaturation Detection, UVLO,
Fault Feedback, Active Miller Clamp and Auto-Fault Reset
Data Sheet
Description
The ACPL-330J is an advanced 1.5 A output current, easy-
to-use, intelligent gate driver which makes IGBT VCE fault
protection compact, aordable, and easy-to implement.
Features such as integrated VCE detection, under
voltage lockout (UVLO), “soft” IGBT turn-o, isolated
open collector fault feedback and active Miller clamping
provide maximum design exibility and circuit protec-
tion.
The ACPL-330J contains a AlGaAs LED. The LED is
optically coupled to an integrated circuit with a power
output stage. ACPL-330J is ideally suited for driving
power IGBTs and MOSFETs used in motor control inverter
applications. The voltage and current supplied by these
optocouplers make them ideally suited for directly
driving IGBTs with ratings up to 1200 V and 100 A. For
IGBTs with higher ratings, the ACPL-330J can be used to
drive a discrete power stage which drives the IGBT gate.
The ACPL-330J has an insulation voltage of VIORM = 1414
VPEAK.
Block Diagram
Features
• 1.5 A maximum peak output current
• 1.0 A minimum peak output current
• 250 ns maximum propagation delay over
temperature range
• 1.0A Active Miller Clamp. Clamp pin short to VEE if not
in used
• Miller Clamping
• Desaturation Detection
• Under Voltage Lock-Out Protection (UVLO)
with Hysteresis
• Open Collector Isolated fault feedback
• “Soft” IGBT Turn-o
• Automatic Fault Reset after xed Mute Time , typically
26ms
• Available in SO-16 package
• 100 ns maximum pulse width distortion (PWD)
• 50 kV/µs minimum common mode rejection (CMR)
at VCM = 1500 V
• ICC(max) < 5 mA maximum supply current
• Wide VCC operating range: 15 V to 30 V over
temperature range
• Wide operating temperature range: –40°C to 105°C
• Safety Approvals:
UL, 5000 VRMS for 1 minute, CSA Approval,
IEC/EN/DIN-EN 60747-5-5 VIORM = 1414 VPEAK
Applications
• Isolated IGBT/Power MOSFET gate drive
• AC and brushless DC motor drives
• Industrial inverters and Uninterruptible Power Supply
(UPS)
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD. The components
featured in this datasheet are not to be used in military or aerospace applications or environments.
SHIELD
SHIELD
D
R
I
V
E
R
VE
DESAT
VCC2
VOUT
VCLAMP
VEE
VCC1
VS
FAULT
ANODE
CATHODE
VCLAMP
VLED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
2
Pin Description Pin Symbol Description
1 VSInput Ground
2 VCC1 Positive input supply voltage. (3.3 V to 5.5 V)
3FAULT Fault output. FAULT changes from a high impedance state
to a logic low output within 5 µs of the voltage on the
DESAT pin exceeding an internal reference voltage of 6.5 V.
FAULT output is an open collector which allows the FAULT
outputs from all ACPL-330J in a circuit to be connected
together in a “wired OR” forming a single fault bus for inter-
facing directly to the micro-controller.
4 VSInput Ground
5 CATHODE Cathode
6 ANODE Anode
7 ANODE Anode
8 CATHODE Cathode
9 VEE Output supply voltage.
10 VCLAMP Miller clamp
11 VOUT Gate drive voltage output
12 VEE Output supply voltage.
13 VCC2 Positive output supply voltage
14 DESAT Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 6.5 V while the
IGBT is on, FAULT output is changed from a high impedance
state to a logic low state within 5 µs.
15 VLED LED anode. This pin must be left unconnected for guaran-
teed data sheet performance. (For optical coupling testing
only)
16 VECommon (IGBT emitter) output supply voltage.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
Ordering Information
ACPL-330J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Part number
Option
Package
Surface
Mount Tape& Reel
IEC/EN/DIN EN
60747-5-5 QuantityRoHS Compliant
ACPL-330J -000E SO-16 X X 45 per tube
-500E X X X 850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-330J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-330J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
3
Package Outline Drawings
16-Lead Surface Mount
9
7.493 ± 0.254
(0.295 ± 0.010)
10111213141516
87654321
0.457
(0.018)
3.505 ± 0.127
(0.138 ± 0.005)
9°
10.312 ± 0.254
(0.406 ± 0.10)
10.363 ± 0.254
(0.408 ± 0.010)
0.64 (0.025) MIN.
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
8.763 ± 0.254
(0.345 ± 0.010)
0-8°
0.457
(0.018) 1.270
(0.050)
A XXXX
YYWW
TYPE NUMBER
DATE CODE
11.63 (0.458)
2.16 (0.085)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
EEE
LOT ID
AVAGO
LEAD-FREE
Dimensions in Millimeters (Inches)
Floating lead protrusion is 0.25 mm (10 mils) Max.
Note: Initial and continued variation in color of the white mold compound is normal and does not aect performance or reliability of the device
ALL LEADS TO
BE COPLANAR
± 0.05 (0.002)
PIN 1 DOT
4
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description Symbol Characteristic Unit
Installation classication per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000Vrms
I – IV
I – IV
I – IV
I – III
Climatic Classication 40/100/21
Pollution Degree (DIN VDE 0110/39) 2
Maximum Working Insulation Voltage VIORM 1414 Vpeak
Input to Output Test Voltage, Method b**,
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR 2652 Vpeak
Input to Output Test Voltage, Method a**,
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR 2262 Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature TS175 °C
Input Current IS, INPUT 400 mA
Output Power PS, OUTPUT 1200 mW
Insulation Resistance at TS, VIO = 500 V RS>109W
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classication is class A in accordance with CECCOO802.
** Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV02-2041EN for a
detailed description of Method a and Method b partial discharge test proles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)
P
S
- POWER - mW
0
0
TS - CASE TEMPERATURE - °C
200
1200
800
25
1400
50 75 100
400
150 175
PS , OUTPUT
PS , INPUT
125
200
600
1000
Recommended Pb-Free IR Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-330J has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 Approval under: DIN EN 60747-5-5 (VDE 0884-5):2011-11 EN 60747-5-5:2011
UL Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361.
CSA Approval under CSA Component Acceptance Notice #5, File CA 88324.
5
Table 2. Insulation and Safety Related Specications
Parameter Symbol ACPL-330J Units Conditions
Minimum External Air
Gap (Clearance)
L(101) 8.3 mm Measured from input terminals to output terminals,
shortest distance through air.
Minimum External
Tracking (Creepage)
L(102) 8.3 mm Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal
Plastic Gap (Internal
Clearance)
0.5 mm Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
Tracking Resistance
(Comparative Tracking
Index)
CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 105 °C 2
Output IC Junction Temperature TJ125 °C 2
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current
(<1 µs pulse width, 300pps)
IF(TRAN) 1.0 A
Reverse Input Voltage VR5 V
“High” Peak Output Current IOH(PEAK) 1.5 A 3
“Low” Peak Output Current IOL(PEAK) 1.5 A 3
Positive Input Supply Voltage VCC1 -0.5 7.0 V
FAULT Output Current IFAULT 8.0 mA
FAULT Pin Voltage VFAULT -0.5 VCC1 V
Total Output Supply Voltage (VCC2 - VEE) -0.5 33 V
Negative Output Supply Voltage (VE - VEE) -0.5 15 V 6
Positive Output Supply Voltage (VCC2 - VE) -0.5 33 - (VE - VEE) V
Gate Drive Output Voltage VO(PEAK) -0.5 VCC2 V
Peak Clamping Sinking Current IClamp 1.0 A
Miller Clamping Pin Voltage VClamp -0.5 VCC2 V
DESAT Voltage VDESAT VEVE + 10 V
Output IC Power Dissipation PO600 mW 2
Input IC Power Dissipation PI150 mW 2
Solder Reow Temperature Prole See Package Outline Drawings section
Table 4. Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Operating Temperature TA- 40 105 °C 2
Total Output Supply Voltage (VCC2 - VEE) 15 30 V 7
Negative Output Supply Voltage (VE - VEE) 0 15 V 4
Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) V
Input Current (ON) IF(ON) 8 12 mA
Input Voltage (OFF) VF(OFF) - 3.6 0.8 V
6
Table 5. Electrical Specications (DC)
Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
FAULT Logic Low
Output Voltage
VFAULTL 0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 5.5V
0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 3.3V
FAULT Logic High
Output Current
IFAULTH 0.02 0.5 µA VFAULT = 5.5 V, VCC1 = 5.5V
0.002 0.3 µA VFAULT = 3.3 V, VCC1 = 3.3V
High Level
Output Current
IOH -0.3 -0.75 A VO = VCC2 – 4 4, 18 5
-1.0 A VO = VCC2 – 15 3
Low Level
Output Current
IOL 0.3 0.75 A VO = VEE + 2.5 5, 19 5
1.0 A VO = VEE + 15 3
Low Level Output Current
During Fault Condition
IOLF 90 140 230 mA VOUT - VEE = 14 V 6
High Level
Output Voltage
VOH VCC-2.9 VCC-2.0 V IO = -650 µA 2, 4,
20
7, 8,9
23
Low Level
Output Voltage
VOL 0.17 0.5 V IO = 100 mA 3, 5,
21
Clamp Pin Threshold
Voltage
VtClamp 2.0 V
Clamp Low Level
Sinking Current
ICL 0.21 0.7 A VO = VEE + 2.5
High Level Supply Current ICC2H 2.5 5 mA IO = 0 mA 6, 7,
23
9
Low Level Supply Current ICC2L 2.5 5 mA IO = 0 mA
Blanking Capacitor
Charging Current
ICHG 0.13 -0.24 -0.33 mA VDESAT = 2 V 8, 24 9, 10
Blanking Capacitor
Discharge Current
IDSCHG 10 30 mA VDESAT = 7.0 V 25
DESAT Threshold VDESAT 6 6.5 7.5 V VCC2 -VE >VUVLO- 9, 27 9
UVLO Threshold VUVLO+ 10.5 11.6 12.5 V VO > 5 V 7, 9, 11
VUVLO- 9.2 10.3 11.1 V VO < 5 V 7, 9, 12
UVLO Hysteresis (VUVLO+
- VUVLO-)
0.4 1.3 V
Threshold Input Current
Low to High
IFLH 2.0 6 mA IO = 0 mA, VO > 5 V
Threshold Input Voltage
High to Low
VFHL 0.8 V
Input Forward Voltage VF1.2 1.6 1.95 V IF = 10 mA
Temperature Coecient
of Input Forward Voltage
DVF/DTA-1.3 mV/°C
Input Reverse Breakdown
Voltage
BVR5 V IR = 10 µA
Input Capacitance CIN 70 pF f = 1 MHz, VF = 0 V
7
Table 6. Switching Specications (AC)
Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time
to High Output Level
tPLH 100 180 250 ns Rg = 20 W, Cg = 5 nF,
f = 10 kHz,
Duty Cycle = 50%,
IF = 10 mA, VCC2 = 30 V
1, 10,
11, 12,
13, 26
13, 15
Propagation Delay Time
to Low Output Level
tPHL 100 180 250 ns
Pulse Width Distortion PWD -100 20 100 ns 14, 17
Propagation Delay Dierence
Between Any Two Parts or
Channels
(tPHL - tPLH)
PDD
-150 150 ns 17, 16
Rise Time tR50 ns
Fall Time tF50 ns
DESAT Sense to 90% VO Delay tDESAT(90%) 0.15 0.3 µs CDESAT = 100pF, RF=2.1kΩ,
Rg = 20 W, Cg = 5 nF,
VCC2 = 30 V
14, 27,
34
19
DESAT Sense to 10% VO Delay tDESAT(10%) 1.1 1.5 µs CDESAT = 100pF, RF=2.1kΩ ,
Rg = 20 W, Cg = 5 nF,
VCC2 = 30 V
15, 16,
17, 27,
34
DESAT Sense to Low Level
FAULT Signal Delay
tDESAT(FAULT) 0.25 0.5 µs CDESAT = 100 pF, RF = 2.1
kΩ, CF = Open, Rg = 20 Ω,
Cg = 5 nF, VCC2 = 30 V
27, 34 18
0.8 CDESAT = 100 pF, RF = 2.1
kΩ, CF = 1 nF, Rg = 20 Ω,
Cg = 5 nF, VCC2 = 30 V
DESAT Sense to DESAT
Low Propagation Delay
tDESAT(LOW) 0.25 µs CDESAT = 100pF, RF = 2.1
kW,
Rg = 20 W, Cg = 5 nF,
VCC2 = 30 V
27, 34 19
DESAT Input Mute tDESAT(MUTE) 15 26 40 µs CDESAT = 100pF, RF = 2.1
kW,
Rg = 20 W, Cg = 5 nF,
VCC1 = 5.5V, VCC2 = 30 V
34 20
Output High Level Common
Mode Transient Immunity
|CMH| 15 25 kV/µs TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V,
RF = 2.1 kΩ, CF = 15 pF
28, 29,
30, 31
21
50 60 TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V,
RF = 2.1 kΩ, CF = 1 nF
21, 26
Output Low Level Common
Mode Transient Immunity
|CML| 15 25 kV/µs TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V,
RF = 2.1 kΩ, CF = 15 pF
28, 29,
30, 31
22
50 60 TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V,
RF = 2.1 kΩ, CF = 1 nF
8
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specied, pins 4, 9, and 10 require ground plane connections and may require
airow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air ow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A.
Derate linearly from 2.0 A at +25°C to 1.5 A at +105°C. This compensates for increased IOPEAK due to changes in VOL over temperature.
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 µs.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 12.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
8. Maximum pulse width = 1.0 ms.
9. Once VO of the ACPL-330J is allowed to go high (VCC2 - VE > VUVLO+), the DESAT detection feature of the ACPL-330J will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 is increased from 0V to above VUVLO+, DESAT will remain functional
until VCC2 is decreased below VUVLO-. Thus, the DESAT detection and UVLO features of the ACPL-330J work in conjunction to ensure constant
IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE
12. This is the “decreasing” (i.e. turn-o or “negative going” direction) of VCC2 - VE
13. This load condition approximates the gate load of a 1200 V/75A IGBT.
14. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH| for any given unit.
15. As measured from IF to VO.
16. The dierence between tPHL and tPLH between any two ACPL-330J parts under the same test conditions.
17. As measured from ANODE, CATHODE of LED to VOUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply
voltage dependent.
20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation
(Auto Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V).
22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.
25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 31.
Table 7. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage
VISO 5000 Vrms RH < 50%, t = 1 min.,
TA = 25°C
24, 25
Input-Output Resistance RI-O > 109WVI-O = 500 V 25
Input-Output Capacitance CI-O 1.3 pF freq=1 MHz
Output IC-to-Pins 9 &10
Thermal Resistance
q09-10 30 °C/W TA = 25°C
9
(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V
TA- TEMPERATURE -°C
-2.5
-2
-1.5
-1
-0.5
0
-40 -20 0 20 40 60 80 105
____IOUT = -650µA
0
0.05
0.1
0.15
0.2
0.25
-40 -20 0 20 40 60 80 105
VOL - OUTPUT LOW VOLTAGE - V
TA- TEMPERATURE -°C
25
26
27
28
29
30
0.0 0.2 0.4 0.6 0.8 1.0
IOH - OUTPUT HIGH CURRENT - A
VOH - HIGH OUTPUT VOLTAGE DROP - V
_ _ _ _ 105°C
______ 25°C
--------- -40°C
0
1
2
3
4
0 0.5 1 1.5
IOL - OUTPUT LOW CURRENT - A
_ _ _ _ 100°C
25°C
--------- -40°C
VOL - OUTPUT LOW VOLTAGE - V
Figure 1. Timing Curve
Figure 2. VOH vs. temperature Figure 3. VOL vs. temperature
Figure 4. VOH vs. IOH Figure 5. VOL vs. IOL
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
10
2.00
2.25
2.50
2.75
3.00
3.25
3.50
-40 -20 0 20 40 60 80 105
ICC2 - OUTPUT SUPPLY CURRENT - mA
TA- TEMPERATURE -°C
2.25
2.35
2.45
2.55
2.65
15 20 25 30
ICC2 - OUTPUT SUPPLY CURRENT - mA
VCC2 - SUPPLY VOLTAGE - V
-0.35
-0.30
-0.25
-0.20
-40 -20 0 20 40 60 80 105
I
CH
- BLANKING CAPACITOR
CHARGING CURRENT - mA
TA- TEMPERATURE -°C
6.0
6.5
7.0
7.5
-40 -20 0 20 40 60 80 105
VDESAT - DESAT THRESHOLD - V
TA- TEMPERATURE -°C
100
150
200
250
300
-40 -20 0 20 40 60 80 105
TP - PROPAGATION DELAY - ns
TA- TEMPERATURE -°C
100
150
200
250
300
15 20 25 30
VCC - SUPPLY VOLTAGE - V
TP - PROPAGATION DELAY - ns
t
t
PLH
PHL
t
t
PLH
PHL
ICC2H
ICC2L
ICC2H
ICC2L
Figure 7. ICC2 vs. VCC2
Figure 8. ICHG vs. temperature Figure 9. DESAT threshold vs. temperature
Figure 10. Propagation delay vs. temperature Figure 11. Propagation delay vs. supply voltage
Figure 6. ICC2 vs. temperature
11
100
150
200
250
300
0 10 20 30 40 50
LOAD RESISTANCE - ohm
t
PLH
t
PHL
TP - PROPAGATION DELAY - ns
0
100
200
300
0 10 20 30 40 50
LOAD CAPACITANCE - nF
t
PLH
tPHL
TP - PROPAGATION DELAY - ns
100
150
200
250
-40 -20 0 20 40 60 80 105
TDESAT90% - DESAT Sense to 90% Vo Delay - ns
TA- TEMPERATURE -°C
0.0
0.5
1.0
1.5
2.0
-40 -20 0 20 40 60 80 105
V
cc2
=15V
Vcc2 =30V
TDESAT10% - DESAT Sense to 10% Vo Delay - us
TA- TEMPERATURE -°C
0.0
1.0
2.0
3.0
4.0
10 20 30 40 50
LOAD RESISTANCE-ohm
V
cc2
=15V
Vcc2 =30V
TDESAT10% - DESAT Sense to 10% Vo Delay - us
0.000
0.004
0.008
0.012
0 10 20 30 40 50
LOAD CAPACITANCE-nF
TDESAT10% - DESAT Sense to 10% Vo Delay - ms
Vcc2 =15V
Vcc2 =30V
Figure 13. Propagation delay vs. load capacitance
Figure 14. DESAT sense to 90% VOUT delay vs. temperature Figure 15. DESAT sense to 10% VOUT delay vs. temperature
Figure 16. DESAT sense to 10% VOUT delay vs. load resistance Figure 17. DESAT sense to 10% VOUT delay vs. load capacitance
Figure 12. Propagation delay vs. load resistance
12
Figure 18. IOH Pulsed test circuit
Figure 19. IOL Pulsed test circuit
Figure 20. VOH Pulsed test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+
_
10mA
+
_
0.1µF
0.1µF
15V Pulsed
IOUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+
_
10mA
+
_
0.1µF0.1µF
0.1µF0.1µF
15V Pulsed
IOUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
0.1µF
0.1µF
15V Pulsed
I
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
0.1µF0.1µF
0.1µF0.1µF
15V Pulsed
I
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
650µA
V
OUT
30V
10mA
13
Figure 21. VOL Pulsed test circuit
Figure 22. ICC2H test circuit
Figure 23. ICC2L test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
100mA
V
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
100mA
V
OUT
30V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
I
CC2
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
I
CC2
30V
10mA10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF 30V
I
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF 30V
I
CC2
14
Figure 24. ICHG Pulsed test circuit
Figure 25. IDSCHG test circuit
Figure 26. tPLH, tPHL, tf, tr, test circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
I
CHG
30V
10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
I
CHG
30V
10mA10mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
7V
30V
+
_
IDSCHG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
7V
30V
+
_
IDSCHG
5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF
0.1µF
V
OUT
30V
20Ω
10mA, 10kHz,
50% Duty Cycle
5nF5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
0.1µF0.1µF
0.1µF0.1µF
V
OUT
30V
10mA, 10kHz,
50% Duty Cycle
15
Figure 27. tDESAT fault test circuit
Figure 28. CMR Test circuit LED2 o
Figure 29. CMR Test Circuit LED2 on
5nF
+
_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
5V
0.1µF
0.1µF
V
OUT
30V
20Ω
V
IN
V
FAULT
10mA 5nF
+
_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
+
_
5V
0.1µF0.1µF
0.1µF0.1µF
V
OUT
30V
V
IN
V
FAULT
10mA10mA
V
CM
20Ω
5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
30V
360Ω
0.1µF
5V
V
CM
5nF5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
0.1µF0.1µF
SCOPE
30V
VCM
20Ω
5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
0.1µF
30V
360Ω
0.1µF
5V
VCM
5nF5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
VS
0.1µF0.1µF
SCOPE
30V
0.1µF0.1µF
5V5V
R
F
=2.1kΩ
C
F
=15pF
or 1nF
R
F
=2.1kΩ
C
F
=15pF
or 1nF
R
F
=2.1kΩ
C
F
16
Figure 30. CMR Test circuit LED1 o
Figure 31. CMR Test Circuit LED1 on
20Ω
5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
V
CM
360Ω
0.1µF
5V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
µµ
V
CM
V
CM
µ
V
CM
20Ω
5nF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
0.1µF
SCOPE
30V
360Ω
0.1µF
5V
V
CM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
V
S
R
F
=2.1kΩ
C
F
=15pF
or 1nF
R
F
=2.1kΩ
C
F
=15pF
or 1nF
5
6
7
8
CATHODE
ANODE
ANODE
CATHODE
180Ω
5V
180Ω
Split resistors network with a ratio of 1:1
17
Application Information
Product Overview Description
The ACPL-330J is a highly integrated power control
device that incorporates all the necessary components
for a complete, isolated IGBT / MOSFET gate drive circuit
with fault protection and feedback into one SO-16
package. Active Miller clamp function eliminates the
need of negative gate drive in most application and
allows the use of simple bootstrap supply for high side
driver. An optically isolated power output stage drives
IGBTs with power ratings of up to 100 A and 1200 V. A
high speed internal optical link minimizes the propaga-
tion delays between the microcontroller and the IGBT
while allowing the two systems to operate at very large
common mode voltage dierences that are common
in industrial motor drives and other power switching
applications. An output IC provides local protection
for the IGBT to prevent damage during over current,
and a second optical link provides a fully isolated fault
status feedback signal for the microcontroller. A built
in “watchdog” circuit, UVLO monitors the power stage
supply voltage to prevent IGBT caused by insucient
gate drive voltages. This integrated IGBT gate driver is
designed to increase the performance and reliability of
a motor drive without the cost, size, and complexity of a
discrete design.
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two optical
channels. The output Detector IC is designed manufac-
tured on a high voltage BiCMOS/Power DMOS process.
The forward optical signal path, as indicated by LED1,
transmits the gate control signal. The return optical signal
path, as indicated by LED2, transmits the fault status
feedback signal.
Under normal operation, the LED1 directly controls the
IGBT gate through the isolated output detector IC, and
LED2 remains o. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a con-
trolled manner to avoid potential IGBT damage from
inductive over voltages. Simultaneously, this fault status
is transmitted back to the input via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insucient gate
voltage to the IGBT, by forcing the ACPL-330J’s output
low. Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-330J provides IGBT pro-
tection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
Recommended Application Circuit
The ACPL-330J has an LED input gate control, and an
open collector fault output suitable for wired ‘OR’ ap-
plications. The recommended application circuit shown
in Figure 33 illustrates a typical gate drive implementa-
tion using the ACPL-330J. The following describes about
driving IGBT. However, it is also applicable to MOSFET.
Depending upon the MOSFET or IGBT gate threshold
requirements, designers may want to adjust the VCC
supply voltage (Recommended VCC = 17.5V for IGBT and
12.5V for MOSFET).
The two supply bypass capacitors (0.1 µF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the
charging currents, a low current (5mA) power supply
suces. The desaturation diode DDESAT 600V/1200V
fast recovery type, trr below 75ns (e.g. ERA34-10) and
capacitor CBLANK are necessary external components for
the fault detection circuitry. The gate resistor RG serves to
limit gate charge current and controls the IGBT collector
voltage rise and fall times. The open collector fault
output has a passive pull-up resistor RF (2.1 kW) and a
1000 pF ltering capacitor, CF. A 47 kW pull down resistor
RPULL-DOWN on VOUT provides a predictable high level
output voltage (VOH). In this application, the IGBT gate
driver will shut down when a fault is detected and fault
reset by next cycle of IGBT turn on. Application notes are
mentioned at the end of this datasheet.
Figure 32. Block Diagram of ACPL-330J
SHIELD
SHIELD
D
R
I
V
E
R
VE
DESAT
VCC2
VOUT
VCLAMP
VEE
VCC1
VS
FAULT
ANODE
CATHODE
VCLAMP
VLED
6, 7
5, 8
2
3
1, 4
13
11
14
9, 12
10
16
15
DESAT
UVLO
LED1
LED2
18
Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp
Description of Operation
Normal Operation
During normal operation, VOUT of the ACPL-330J is con-
trolled by input LED current IF (pins 5, 6, 7 and 8), with
the IGBT collector-to-emitter voltage being monitored
through DESAT. The FAULT output is high. See Figure 34.
Fault Condition
The DESAT pin monitors the IGBT Vce voltage. When the
voltage on the DESAT pin exceeds 6.5 V while the IGBT
is on, VOUT is slowly brought low in order to “softly”
turn-o the IGBT and prevent large di/dt induced
voltages. Also
Figure 34. Fault Timing diagramactivated is an internal
feedback channel which brings the FAULT output low for
the purpose of notifying the micro-controller of the fault
condition.
Fault Reset
Once fault is detected, the output will be soft-shut down
to low. All input LED signals will be ignored during
the fault period to allow the driver to completely soft
shut-down the IGBT. For ACPL-330J, the driver will auto-
matically reset the FAULT pin after a xed mute time of
25ms (typical). See Figure 34.
+
_
+
_
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
+
_
R
G
100 Ω
C
BLANK
D
DESAT
Q1
Q2
+
V
CE
-
R
F
R
R
PULL-DOWN
+ HVDC
- HVDC
3-PHASE
AC
+
V
CE
-
0.1µF
0.1µF
C
F
7
+
_
-
Figure 34. Fault Timing diagram
IF
VDESAT
VOUT
FAULT
6.5V
tDESAT(LOW)
10%
tDESAT(10%)
90%
tDESAT(90%)
50%
tDESAT(FAULT)
tDESAT(MUTE)
Automatic Reset
after mute time
50%
tBLANK
19
Output Control
The outputs (VOUT and FAULT) of the ACPL-330J are con-
trolled by the combination of IF, UVLO and a detected
IGBT Desat condition. Once UVLO is not active (VCC2 -
VE > VUVLO), VOUT is allowed to go high, and the DESAT
(pin 14) detection feature of the ACPL-330J will be the
primary source of IGBT protection. Once VCC2 is increased
from 0V to above VUVLO+, DESAT will remain functional
until VCC2 is decreased below VUVLO-. Thus, the DESAT
detection and UVLO features of the ACPL-330J work in
conjunction to ensure constant IGBT protection.
Desaturation Detection and High Current Protection
The ACPL-330J satises these criteria by combining a
high speed, high output current driver, high voltage
optical isolation between the input and output, local
IGBT desaturation detection and shut down, and an
optically isolated fault status feedback signal into a single
16-pin surface mount package.
The fault detection method, which is adopted in the
ACPL-330J is to monitor the saturation (collector)
voltage of the IGBT and to trigger a local fault shutdown
sequence if the collector voltage exceeds a predeter-
mined threshold. A small gate discharge device slowly
reduces the high short circuit IGBT current to prevent
damaging voltage spikes. Before the dissipated energy
can reach destructive levels, the IGBT is shut o. During
the o state of the IGBT, the fault detect circuitry is simply
disabled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is eective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the ACPL-330J limits
the power dissipation in the IGBT even with insucient
gate drive voltage. Another more subtle advantage of the
desaturation detection method is that power dissipation
in the IGBT is monitored, while the current sense method
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.
Slow IGBT Gate Discharge during Fault Condition
When a desaturation fault is detected, a weak pull-down
device in the ACPL-330J output drive stage will turn on
to ‘softly’ turn o the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn o, the large
output pull-down device remains o until the output
voltage falls below VEE + 2 Volts, at which time the large
pull down device clamps the IGBT gate to VEE.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
threshold. This time period, called the DESAT blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor.
The nominal blanking time is calculated in terms of
external capacitance (CBLANK), FAULT threshold voltage
(VDESAT), and DESAT charge current (ICHG) as tBLANK =
CBLANK x VDESAT / ICHG. The nominal blanking time with
the recommended 100pF capacitor is 100pF * 6.5 V / 240
µA = 2.7 µsec.
The capacitance value can be scaled slightly to adjust the
blanking time, though a value smaller than 100 pF is not
recommended. This nominal blanking time represents
the longest time it will take for the ACPL-330J to respond
to a DESAT fault condition. If the IGBT is turned on while
the collector and emitter are shorted to the supply rails
(switching into a short), the soft shut-down sequence
will begin after approximately 3 µsec. If the IGBT collector
and emitter are shorted to the supply rails after the IGBT
is already on, the response time will be much quicker due
to the parasitic parallel capacitance of the DESAT diode.
The recommended 100pF capacitor should provide
adequate blanking as well as fault response times for
most applications.
IFUVLO(VCC2-VE) DESAT Function Pin 3 (FAULT) Output VOUT
ON Active Not Active High Low
ON Not Active Active (with DESAT fault) Low (FAULT) Low
ON Not Active Active (no DESAT fault) High (or no fault) High
OFF Active Not Active High Low
OFF Not Active Not Active High Low
20
Figure 35. Output pull-down resistor.
DESAT Pin Protection Resistor
The freewheeling of yback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the driver if protection is not used. To
limit this current to levels that will not damage the driver
IC, a 100 ohm resistor should be inserted in series with
the DESAT diode. The added resistance will not alter the
DESAT threshold or the DESAT blanking time.
Figure 36. DESAT pin protection.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
RG
RPULL-DOWN
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
RG
RPULL-DOWN
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
E
V
LED
DESAT
V
CC2
V
EE
V
OUT
V
CLAMP
V
EE
V
S
V
CC1
FAULT
V
S
CATHODE
ANODE
ANODE
CATHODE
R
G
V
CC
100 Ω
100pF
D
DESAT
V
CC
Under Voltage Lockout
The ACPL-330J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insucient gate
voltage to the IGBT by forcing the ACPL-330J output
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated VCE(ON) voltage.
At gate voltages below 13 V typically, the VCE(ON) voltage
increases dramatically, especially at higher currents.
At very low gate voltages (below 10 V), the IGBT may
operate in the linear region and quickly overheat.
The UVLO function causes the output to be clamped
whenever insucient operating supply (VCC2) is applied.
Once VCC2 exceeds VUVLO+ (the positive-going UVLO
threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
VCC2 is increased from 0 V (at some level below VUVLO+),
rst the DESAT protection circuitry becomes active. As
VCC2 is further increased (above VUVLO+), the UVLO clamp
is released. Before the time the UVLO clamp is released,
the DESAT protection is already active. Therefore, the
UVLO and DESAT Fault detection feature work together
to provide seamless protection regardless of supply
voltage (VCC2).
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation and can eliminate the use
of a negative supply voltage in most of the applications.
During turn-o, the gate voltage is monitored and the
clamp output is activated when gate voltage goes below
2V (relative to VEE). The clamp voltage is VOL+2.5V typ
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
Other Recommended Components
The application circuit in Figure 33 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and
Active Miller Clamp connection.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
the output voltage to VCC2-3(VBE), a pull-down resistor,
RPULL-DOWN between the output and VEE is recommend-
ed to sink a static current of several 650 µA while the
output is high. Pull-down resistor values are dependent
on the amount of positive supply and can be adjusted
according to the formula, Rpull-down = [VCC2-3 * (VBE)] /
650 µA.
21
Pull-up Resistor on FAULT Pin
The FAULT pin is an open collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Also the FAULT output can be wire ‘OR’ed together with
other types of protection (e.g. over-temperature, over-
voltage, over-current ) to alert the microcontroller.
Figure 38. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.
Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is
used as secondary gate discharge path. * indicates component required for negative gate drive topology
Other Possible Application Circuit (Output Stage)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
RG
Q1
Q2
+
VCE
-
RPULL-DOWN
+ HVDC
-HVDC
3-PHASE
AC
+
VCE
-
01F 01F
01F
O R 1
O R 2
RG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED
DESAT
VCC2
VEE
VOUT
VCLAMP
VEE
VS
VCC1
FAULT
VS
CATHODE
ANODE
ANODE
CATHODE
+
_
+
_
RG
Q1
Q2
+
VCE
-
RPULL-DOWN
+ HVDC
-HVDC
3-PHASE
AC
+
VCE
-
01F 01F
01F
O R 1
O R 2
R3
9
RG
R3
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can aect the fault pin
voltage while the fault output is in the high state. A 1000
pF capacitor should be connected between the fault pin
and ground to achieve adequate CMOS noise margins at
the specied CMR value of 50 kV/µs.
Related Application Notes
AN5314 – Active Miller Clamp
AN5315 – “Soft” Turn-o Feature
AN1043 – Common-Mode Noise : Sources and Solutions
AV02-0310EN - Plastic Optocouplers Product ESD and Moisture Sensitivity
Thermal Model
The ACPL-330J is designed to dissipate the majority of
the heat through pins 1, 4, 5 & 8 for the input IC and pins
9 & 12 for the output IC. (There are two VEE pins on the
output side, pins 9 and 12, for this purpose.) Heat ow
through other pins or through the package directly into
ambient are considered negligible and not modeled
here.
In order to achieve the power dissipation specied in
the absolute maximum specication, it is imperative
that pins 5, 9, and 12 have ground planes connected to
them. As long as the maximum power specication is
not exceeded, the only other limitation to the amount
of power one can dissipate is the absolute maximum
junction temperature specication of 125°C. The junction
temperatures can be calculated with the following
equations:
Tji = Pi (θi5 + θ5A) + TA
Tjo = Po (θo9,12 + θ9,12A) + TA
where Pi = power into input IC and Po = power into
output IC. Since θ5A and θ9,12A are dependent on PCB
layout and airow, their exact number may not be
available. Therefore, a more accurate method of calcu-
lating the junction temperature is with the following
equations:
Tji = Pi θi5 + TP5
Tjo = Po θo9,12 + TP9,12
These equations, however, require that the pin 5 and pins
9, 12 temperatures be measured with a thermal couple
on the pin at the ACPL-330J package edge.
If the calculated junction temperatures for the thermal
model in Figure 39 is higher than 125°C, the pin tem-
perature for pins 9 and 12 should be measured (at the
package edge) under worst case operating environment
for a more accurate estimate of the junction tempera-
tures.
Figure 39. ACPL-330J Thermal Model
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
TP5 = pin 5 temperature at package edge
TP9,12 = pin 9 and 12 temperature at package edge
θI5 = input side IC to pin 5 thermal resistance
θo9,12 = output side IC to pin 9 and 12 thermal resistance
θ5A = pin 5 to ambient thermal resistance
θ9,12A = pin 9 and 12 to ambient thermal resistance
*The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air ow.
This value may increase or decrease by a factor of 2 depending on PCB layout and/or airow.
TP1 TP9, 12
θ1A = 50°C/W*
Tji
TA
θI1 = 60°C/W
θ9, 12A = 50°C/W*
θl9, 12 = 30°C/W
Tjo
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Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved.
AV02-1280EN - November 20, 2015