FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams FEATURES Full CMOS, 6T Cell Data Retention with 2.0V Supply (FT6187L Military) High Speed (Equal Access and Cycle Times) - 10/12/15/20/25/35/45 ns (Commercial) - 12/15/20/25/35 /45 ns (Industrial) - 15/20/25/35/45/55/70/85 ns (Military) Separate Data I/O Three-State Output Low Power Operation - 743 mW Active -10 - 660/770 mW Active for -12/15 - 550/660 mW Active for -20/25/35 - 193/220 mW Standby (TTL Input) - 83/110 mW Standby (CMOS Input) P4C187 - 5.5 mW Standby (CMOS Input) FT6187L (Military) Single 5V10% Power Supply TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) - 22-Pin 300 mil DIP - 24-Pin 300 mil SOJ - 22-Pin 290x490 mil LCC - 28-Pin 350x550 mil LCC DESCRIPTION consumption to a low 743mW active, 193/83mW standby for TTL/CMOS inputs and only 5.5 mW standby for the FT6187L. The FT6187/FT6187L are 65, 536-bit ultra high speed static RAMs organised as 64K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 10A. The FT6187/FT6187L are available in 22-pin 300 mil DIP, 24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages providing excellent board level densities. Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. CMOS reduces power FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P3, D3, C3) SOJ (J4) LCC Pin configurations at end of datasheet. REV 1.1 1/13 2008 FT6187/FT6187L MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND -0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC +0.5 V TA Operating Temperature -55 to +125 C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature GND VCC 0V 0V 0V 5.0V 10% 5.0V 10% 5.0V 10% Military -55C to +125C -40C to +85C Industrial 0C to +70C Commercial Symbol Parameter Value Unit TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = 18 mA VOL Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current VOH ILI -0.5(3) -0.5 (3) IOL = +8 mA, VCC = Min. IOH = -4 mA, VCC = Min. VCC = Max. ISB1 -0.5(3) 0.8 V 0.2 V -1.2 -1.2 V 0.4 0.4 V 0.2 2.4 Mil. V -0.5 (3) 2.4 V -10 -5 +10 +5 -5 n/a +5 n/a A -10 -5 +10 +5 -5 n/a +5 n/a A Standby Power Supply CE VIH Mil. Current (TTL Input Levels) VCC = Max ., Ind./Com'l. f = Max., Outputs Open ___ ___ 40 ___ ___ 40 n/a mA CE VHC Mil. VCC = Max., Ind./Com'l. f = 0, Outputs Open VIN VLC or VIN VHC ___ ___ 20 ___ ___ 1.0 n/a mA Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC ISB 0.8 FT6187L Unit Min Max 2.2 VCC +0.5 V VCC -0.2 VCC +0.5 VCC -0.2 VCC +0.5 VIN = GND to VCC ILO FT6187 Min Max 2.2 VCC +0.5 Test Conditions Standby Power Supply Current (CMOS Input Levels) Com'l. Mil. Com'l. 35 15 n/a = Not Applicable Notes: 2. Extended temperature operation guaranteed with 400 linear feet per 1. Stresses greater than those listed under MAXIMUM RATINGS may minute of air flow. cause permanent damage to the device. This is a stress rating only 3. Transient inputs with VIL and IIL not more negative than -3.0V and and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification -100mA, respectively, are permissible for pulse widths up to 20 ns. is not implied. Exposure to MAXIMUM rating conditions for extended 4. This parameter is sampled and not 100% tested. periods may affect reliability. REV 1.1 2/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* Temperature Range Commercial -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Unit 180 170 160 155 150 N/A N/A N/A N/A N/A mA Industrial N/A 180 170 160 155 150 N/A N/A N/A N/A mA Military N/A N/A 170 160 155 150 145 145 145 145 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL. DATA RETENTION CHARACTERISTICS (FT6187L Military Temperature Only) Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Test Conditons Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 10 CE VCC -0.2V, VIN VCC -0.2V or VIN 0.2V 15 600 900 ns tRC ns tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM REV 1.1 3/13 A 0 *TA = +25C Unit 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams AC CHARACTERISTICS--READ CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Symbol Parameter t RC Read Cycle Time -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 15 20 25 35 45 55 70 85 t AA Address Access Time 10 12 15 20 25 35 45 55 70 85 t AC Chip Enable Access Time 10 12 15 20 25 35 45 65 70 85 t OH Output Hold from Address Change 2 2 2 2 2 2 2 2 2 2 t LZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 2 2 2 t HZ Chip Disable to Output in High Z t PU Chip Enable to Power Up Time t PD Chip Disable to Power Down Time 5 0 6 0 10 8 0 12 10 0 15 12 0 20 17 0 25 20 0 35 25 0 45 30 0 55 35 0 70 85 TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2(6) Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. REV 1.1 7. Transition is measured 200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. 4/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Symbol Parameter t WC t CW t AW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 15 20 25 35 45 55 70 85 8 10 12 15 20 25 30 35 40 45 8 10 12 15 20 25 30 35 40 45 tAS Address Set-up Time 0 0 0 0 0 0 0 0 0 0 t WP Write Pulse Width 8 10 12 15 20 25 30 35 40 45 0 0 0 0 0 0 0 0 0 0 6 7 10 13 15 20 25 30 35 40 0 0 0 0 0 0 0 0 0 0 t AH t DW t DH t WZ t OW Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 6 0 7 0 8 0 12 0 15 0 17 0 20 0 25 0 30 0 35 0 WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. REV 1.1 5/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams CE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load See Figures 1 and 2 Figure 2. Thevenin Equivalent Figure 1. Output Load * including scope and test fixture. Note: Due to the ultra-high speed of the FT6187/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, REV 1.1 proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance). 6/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams LCC PIN CONFIGURATIONS 22-PIN LCC (L3) REV 1.1 28-PIN LCC (L5) 7/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams ORDERING INFORMATION FT6187 X XX X X M5004 SELECTION GUIDE The FT6187 is available in the following temperature, speed and package options. The FT6187L is only available over the military temperature range. Temperature Range Commercial Industrial Military Temperature Military Processed* Package Speed (ns) 10 12 15 20 25 35 45 55 70 85 Plastic DIP -10PC -12PC -15PC -20PC -25PC -35PC -45PC N/A N/A N/A Plastic SOJ -10JC -12JC -15JC -20JC -25JC -35JC -45JC N/A N/A N/A Plastic DIP N/A -12PI -15PI -20PI -25PI -35PI -45PI N/A N/A N/A Plastic SOJ N/A -12JI -15JI -20JI -25JI -35JI -45JI N/A N/A N/A Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM -45CM -55CM -70CM -85CM CERDIP N/A N/A -15DM -20DM -25DM -35DM -45DM -55DM -70DM -85DM LCC (28 Pin) N/A N/A -15L28M -20L28M -25L28M -35L28M -45L28M -55L28M -70L28M -85L28M LCC (22 Pin) N/A N/A -15LM -20LM -25LM -35LM -45LM -55LM -70LM -85LM Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB -45CMB -55CMB -70CMB -85CMB CERDIP N/A N/A -15DMB -20DMB -25DMB -35DMB -45DMB -55DMB -70DMB -85DMB LCC (28 Pin) N/A N/A -15L28MB -20L28MB -25L28MB -35L28MB -45L28MB -55L28MB -70L28MB -85L28MB LCC (22 Pin) N/A N/A -15LMB -20LMB -25LMB -35LMB -45LMB -55LMB -70LMB -85LMB * Military temperature range with MIL-STD-883 M5004 N/A = Not Available REV 1.1 8/13 2008 FT6187/FT6187L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 REV 1.1 C3 SIDE BRAZED DUAL IN-LINE PACKAGES Ultra High Speed 64K x 1 Static Cmos Rams 22 (300 mil) Min Max 0.100 0.200 0.014 0.023 0.030 0.060 0.008 0.015 1.050 1.260 0.260 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - D3 CERDIP DUAL IN-LINE PACKAGE 22 (300 mil) Min Max 0.225 0.015 0.020 0.045 0.065 0.009 0.012 1.060 1.110 0.290 0.320 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0 15 9/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L1 ND NE REV 1.1 J4 SOJ SMALL OUTLINE IC PACKAGE 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - L3 RECTANGULAR LEADLESS CHIP CARRIER 22 Min Max 0.060 0.080 0.050 0.068 0.022 0.028 0.284 0.296 0.150 BSC 0.075 BSC 0.296 0.484 0.496 0.300 BSC 0.150 BSC 0.496 0.050 BSC R = .012 R = .012 0.039 0.051 0.039 0.051 0.058 0.072 4 7 10/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L REV 1.1 L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 P3 PLASTIC DUAL IN-LINE PACKAGE 22 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.145 1.165 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0 15 11/13 2008 Ashley Crt, Henley, Marlborough, Wilts, SN8 3RH UK Tel: +44(0)1264 731200 Fax:+44(0)1264 731444 E-mail sales@forcetechnologies.co.uk www.forcetechnologies.co.uk Unless otherwise stated in this SCD/Data sheet , Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified. Life Support Applications Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such improper use or sale. Copyright Force Technologies Ltd 2008 All trademarks acknowledged REV 1.1 12/13 2008 FT6187/FT6187L Ultra High Speed 64K x 1 Static Cmos Rams REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM111 FT6187 / FT6187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS ISSUE DATE ORIG. OF CHANGE 1997 DAB New Data Sheet 1 2007 B.S Revised Sheet 1.1 Jan-08 B.S Added 55, 70, and 85 ns speeds REV. ORIG REV 1.1 DESCRIPTION OF CHANGE 13/13 2008