FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
– 743 mW Active -10
– 660/770 mW Active for -12/15
– 550/660 mW Active for -20/25 /35
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C187
– 5.5 mW Standby (CMOS Input) FT6187L (Military)
Single 5V±10% Power Supply
PIN CONFIGURATIONSFUNCTIONAL BLOCK DIAGRAM
DIP (P3, D3, C3)
LCC Pin configurations at end of datasheet.
Data Retention with 2.0V Supply (FT6187L
Military)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
DESCRIPTION
The FT6187/FT6187L are 65, 536-bit ultra high speed
static RAMs organised as 64K x 1. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. The RAMs operate from a single 5V ± 10%
tolerance power supply. Data integrity is maintained for sup-
ply voltages down to 2.0V, typically drawing 10µA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
FT6187L.
The FT6187/FT6187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
SOJ (J4)
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 1/13 2008
MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Pin with –0.5 to +7 V
Respect to GND
Terminal Voltage with –0.5 to
VTERM Respect to GND VCC +0.5 V
(up to 7.0V)
TAOperating Temperature –55 to +125 °C
Symbol Parameter Value Unit
TBIAS Temperature Under –55 to +125 °C
Bias
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current 50 mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ISB Standby Power Supply
Current (TTL Input Levels)
CE ≥ VIH Mil.
VCC = Max ., Ind./Com’l.
f = Max., Outputs Open
___
___ 40
35
___
___
___
___
20
15
40
n/a
1.0
n/a
mA
mA
___
___
CE ≥ VHC Mil.
VCC = Max., Ind./Com’l.
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
Standby Power Supply
Current
(CMOS Input Levels)
ISB1
Grade(2) Ambient
Temperature GND VCC
0V
0V
5.0V ± 10%
5.0V ± 10%
0V 5.0V ± 10%
–55°C to +125°C
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
5
7
Unit
pF
pF
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
n/a = Not Applicable
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
VIH
VIL
VHC
VLC
VCD
VOL
VOH
ILI
ILO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = Min., IIN = 18 mA
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max. Mil.
VIN = GND to VCC Com’l.
VCC = Max., CE = VIH, Mil.
VOUT = GND to VCC Com’l.
FT6187
Min
2.2
–0.5(3)
VCC –0.2
–0.5(3)
2.4
–10
–5
–10
–5
Max
VCC +0.5
0.8
VCC +0.5
0.2
–1.2
0.4
+10
+5
+10
+5
FT6187L
Min Max
2.2
–0.5(3)
VCC –0.2
–0.5(3)
2.4
–5
n/a
–5
n/a
VCC +0.5
0.8
VCC +0.5
0.2
0.4
–1.2
+5
n/a
+5
n/a
Unit
V
V
V
V
V
V
V
µA
µA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
Military
Industrial –40°C to +85°C
0°C to +70°C
Commercial
FT6187/FT6187L
REV 1.1 2/13 2008
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL.
DATA RETENTION CHARACTERISTICS (FT6187L Military Temperature Only)
Symbol
VDR
ICCDR
tCDR
tR
†
Parameter
VCC for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditons
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V
or VIN ≤ 0.2V
Min
2.0
0
tRC
§
Typ.*
VCC =
2.0V 3.0V
Max
VCC =
2.0V 3.0V
Unit
10 15 600 900
V
µA
ns
ns
*TA = +25°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
ICC
Symbol Parameter Temperature
Range
Dynamic
Operating
Current*
Commercial
Industrial
Military
–10
N/A
–12 –15 –20 –25 –35 –45 Unit
N/A
mA
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A 150155160170180
N/A 170 160 155 150 145
180 170 160 155 150 N/A N/A
–85
N/A
145
N/A
–70
N/A
145
N/A
–55
N/A
145
N/A
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 3/13 2008
Notes:
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
TIMING WAVEFORM OF READ CYCLE NO. 1(5)
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax
tRC Read Cycle Time 10 12 15 20 25 35 45 55 70 85
tAA Address Access Time 10 12 15 20 25 35 45 55 70 85
tAC Chip Enable Access Time 10 12 15 20 25 35 45 65 70 85
tOH Output Hold from Address Change 2222222222
tLZ Chip Enable to Output in Low Z2222222222
tHZ Chip Disable to Output in High Z 5 6 8 10 12 17 20 25 30 35
tPU Chip Enable to Power Up Time0000000000
tPD Chip Disable to Power Down Time 10 12 15 20 25 35 45 55 70 85
ParameterSymbol -10 -12 -45 -55 -70 -85-15 -20 -25 -35
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 4/13 2008
Notes:
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WEWE
WEWE
WE CONTROLLED)(9)
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time 10 12 15 20 25 35 45 55 70 85
tCW
Chip Enable Time to
End of Write 8 101215202530354045
tAW
Address Valid to End
of Write 8 101215202530354045
tAS Address Set-up Time0000000000
tWP Write Pulse Width 8 10 12 15 20 25 30 35 40 45
tAH
Address Hold Time
from End of Write 0000000000
tDW
Data Valid to End of
Write 6 7 10 13 15 20 25 30 35 40
tDH Data Hold Time0000000000
tWZ
Write Enable to
Output in High Z 6 7 8 12 15 17 20 25 30 35
tOW
Output Active from
End of Write 0000000000
-15-20-25-35-45-55-70-85
ParameterSymbol -10 -12
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 5/13 2008
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CECE
CECE
CE CONTROLLED)(9)
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Due to the ultra-high speed of the FT6187/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
AC TEST CONDITIONS TRUTH TABLE
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns
Input Timing Reference Level 1.5V
Output Timing Reference Level 1.5V
Output Load See Figures 1 and 2
Mode CECE
CECE
CE WEWE
WEWE
WE Output Power
Standby H X High Z Standby
Read L H DOUT Active
Write L L High Z Active
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 6/13 2008
28-PIN LCC (L5)
LCC PIN CONFIGURATIONS
22-PIN LCC (L3)
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 7/13 2008
ORDERING INFORMATION
SELECTION GUIDE
The FT6187 is available in the following temperature, speed and package options. The FT6187L is only available over
the military temperature range.
* Military temperature range with MIL-STD-883 M5004
N/A = Not Available
10 12 15 20 25 35 45 55 70 85
Plastic DIP -10PC -12PC -15PC -20PC -25PC -35PC -45PC N/A N/A N/A
Plastic SOJ -10JC -12JC -15JC -20JC -25JC -35JC -45JC N/A N/A N/A
Industrial Plastic DIP N/A -12PI -15PI -20PI -25PI -35PI -45PI N/A N/A N/A
Plastic SOJ N/A -12JI -15JI -20JI -25JI -35JI -45JI N/A N/A N/A
Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM -45CM -55CM -70CM -85CM
CERDIP N/A N/A -15DM -20DM -25DM -35DM -45DM -55DM -70DM -85DM
LCC (28 Pin) N/A N/A -15L28M -20L28M -25L28M -35L28M -45L28M -55L28M -70L28M -85L28M
LCC (22 Pin) N/A N/A -15LM -20LM -25LM -35LM -45LM -55LM -70LM -85LM
Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB -45CMB -55CMB -70CMB -85CMB
CERDIP N/A N/A -15DMB -20DMB -25DMB -35DMB -45DMB -55DMB -70DMB -85DMB
LCC (28 Pin) N/A N/A -15L28MB -20L28MB -25L28MB -35L28MB -45L28MB -55L28MB -70L28MB -85L28MB
LCC (22 Pin) N/A N/A -15LMB -20LMB -25LMB -35LMB -45LMB -55LMB -70LMB -85LMB
Speed (ns)
Military
Temperature
Military
Processed*
Temperature
Range Package
Commercial
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
FT6187 X XX XX
M5004
REV 1.1 8/13 2008
Pkg #
# Pins
Symbol Min Max
A - 0.225
b 0.015 0.020
b2 0.045 0.065
C 0.009 0.012
D 1.060 1.110
E 0.290 0.320
eA
e
L 0.125 0.200
Q 0.015 0.060
S1 0.005 -
0° 15°
D3
22 (300 mil)
0.300 BSC
0.100 BSC
α
CERDIP DUAL IN-LINE PACKAGE
SIDE BRAZED DUAL IN-LINE PACKAGES
Pkg #
# Pins
Symbol Min Max
A 0.100 0.200
b 0.014 0.023
b2 0.030 0.060
C 0.008 0.015
D 1.050 1.260
E 0.260 0.310
eA
e
L 0.125 0.200
Q 0.015 0.070
S1 0.005 -
S2 0.005 -
C3
22 (300 mil)
0.300 BSC
0.100 BSC
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 9/13 2008
Pkg #
# Pins
Symbol Min Max
A 0.060 0.080
A1 0.050 0.068
B1 0.022 0.028
D 0.284 0.296
D1
D2
D3 - 0.296
E 0.484 0.496
E1
E2
E3 - 0.496
e
h
j
L 0.039 0.051
L1 0.039 0.051
L1 0.058 0.072
ND
NE
R = .012
4
7
0.300 BSC
0.150 BSC
0.050 BSC
R = .012
L3
22
0.150 BSC
0.075 BSC
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol Min Max
A 0.128 0.148
A1 0.082 -
b 0.016 0.020
C 0.007 0.010
D 0.620 0.630
e
E
E1 0.292 0.300
E2
Q0.025-
J4
24 (300 mil)
0.050 BSC
0.267 BSC
0.335 BSC
SOJ SMALL OUTLINE IC PACKAGE
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 10/13 2008
Pkg #
# Pins
Symbol Min Max
A 0.060 0.075
A1 0.050 0.065
B1 0.022 0.028
D 0.342 0.358
D1
D2
D3 - 0.358
E 0.540 0.560
E1
E2
E3 - 0.558
e
h
j
L 0.045 0.055
L1 0.045 0.055
L2 0.075 0.095
ND
NE
0.020 REF
5
9
0.400 BSC
0.200 BSC
0.050 BSC
0.040 REF
L5
28
0.200 BSC
0.100 BSC
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol Min Max
A - 0.210
A1 0.015 -
b 0.014 0.022
b2 0.045 0.070
C 0.008 0.014
D 1.145 1.165
E1 0.240 0.280
E 0.300 0.325
e
eB - 0.430
L 0.115 0.150
0° 15°
0.100 BSC
P3
22 (300 Mil)
PLASTIC DUAL IN-LINE PACKAGE
α
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 11/13 2008
Ashley Crt, Henley,
Marlborough, Wilts, SN8 3RH UK
Tel: +44(0)1264 731200
Fax:+44(0)1264 731444
E-mail
sales@forcetechnologies.co.uk
www.forcetechnologies.co.uk
Life Support Applications
Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies
product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products
for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such
improper use or sale.
All trademarks acknowledged Copyright Force Technologies Ltd 2008
Unless otherwise stated in this SCD/Data sheet , Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ
-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no
responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these
products, and makes no representation or warranties that these products are free f rom patent, copyright or mask work infringement, unless
otherwise specified.
REV 1.1 12/13 2008
REVISIONS
DOCUMENT NUMBER: SRAM111
DOCUMENT TITLE: FT6187 / FT6187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
REV. ISSUE
DATE
ORIG. OF
CHANGE DESCRIPTION OF CHANGE
ORIG 1997 DAB New Data Sheet
1 2007 B.S Revised Sheet
1.1 Jan-08 B.S Added 55, 70, and 85 ns speeds
FT6187/FT6187L
Ultra High Speed 64K x 1
Static Cmos Rams
REV 1.1 13/13 2008
