Z16IZF2E-100UCU - STEC

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MT29F8G08ABACAM71M3WC1

Orderable Part Information

Status Contact

Factory

Alternative

Part

N/A

FBGA

Code

N/A SPD Data N/A

MBQual

Data

N/A Shipping

Media

N/A

PLP No Start Date N/A

Specs

Density

8Gb

Status

Contact

Factory

RoHS

Yes

Width

Voltage

3.3V

Package

Wafer

Count

n/a

MT/s

I/O

Common

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SLC NAND FAQs (3)

Do you support small block devices?

How much ECC do I need to support your devices?

I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I

read back from the NAND device.

NAND Flash FAQs (15)

How do I achieve greater PROGRAM /READ throughput for the NAND device?

How is Nvb specified?

I am seeing a lot of READ DISTURB errors. Can you tell me if there is a problem with your part?

I’ve heard that NAND has too many errors to boot from. Is this true?

Should I be marking blocks bad due to READ errors?

When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.

Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?

Where can I find simulation models for NAND Flash devices?

Why am I getting a bit/byte e rror reading back the information I programmed into the NAND device?

Why doesn't the NAND Flash device respond correctly to commands issued to it?

What is a "bank"?

What is the impedance tolerance of the driver in match-impedance mode relative to the expected value base on the perfect

reference resistor connected to ZQ pin?

Does thermal information change for IT parts?

My design was based on a specification stating the JTAG was relative to VDD (1.8V), but now we’ve discovered that JTAG is

actually relative to VDDQ (1.5V). It’s a fairly significant board spin to change this; what do I risk by leaving the design as-is? I

assume that the specification is still for VDDQ + 0.3V = 1.8V, but with CMOS parts there’s no way I can guarantee that it won’t

swing past that on transitions.

Should the ECC memory chip share chip select and CKE signals with the other two main memory chips in our point-to-point

application?

Products and Support FAQs (1)

Who do I contact if I have questions about my buymicron.com order?

Recently Added

Sim Models & Software

Documentation & Support

Date What was added

04/2013 MT29F (1Gb, 2Gb, 4Gb, 8Gb, 16Gb, 32Gb) General Low-Level

Driver

08/2012 Verilog: NAND 8/16Gb SLC M71M

Title & Description Secure ID Updated

IBIS: 8Gb,16Gb: x8, x16 NAND (Rev C) M71M:

Rev. 2.0 M71M 05/2012

Verilog: NAND 8/16Gb SLC M71M: 8/16Gb

Verilog model Rev 7.30 M71M 08/2012

See all Sim Models (2)

FAQs

Do you support small block devices?

How much ECC do I need to support your devices?

I am using the correct amount of error correction code (ECC) for the

NAND device, but I’m still seeing bit/byte errors in data I read back

from the NAND device.

See all FAQs

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