QG41110 S L93U - INTEL

Order Number: 311638-002US

Notice:

The Intel

41110 Serial to Parallel PCI Bridge may contain design defects or errors known as errata

which may cause the product to deviate from published specifications. Current characterized errata are available

on request.

Intel

41110 Serial to Parallel PCI

Bridge

Specification Update

Septembert 2007

Intel

41110 Serial to Parallel PCI Bridge

Specificiation Update Septembert 2007

2Order Number: 311638-002US

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Intel

41110 Serial to Parallel PCI Bridge

Septembert 2007 Specificiation Update

Order Numbe r: 31 16 38 -00 2U S 3

Contents—41110

Contents

Revision History

........................................................................................................4

Introduction

..............................................................................................................5

Summary Tables of Current Product Issue Activity

....................................................7

General Product Information

.....................................................................................9

Errata

...................................................................................................................... 10

Specification Changes

.............................................................................................. 11

Specification Clarifications

...................................................................................... 12

Document-Only Changes

......................................................................................... 13

Intel

41110—Revision History

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

4Order Number: 311638-002US

Revision History

Date Version Description

September 2007 002 Ad d e d S p e c if ica tion Clarif ica t io ns 2 and 3.

Added Document Chan ge 2.

February 20 06 001 Initial release .

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 5

Preface—Intel

41110

Preface

This document is an update to the specifica tions contained in the Affected

Documents/Related Documents table below.

This document is a comp ilatio n of device

and documentation errata, specification clarifications and changes.

It is intended for

hardware system manufacturers and software developers of applications, operating

systems, or tools.

Information types defined in Nomen clatu re are c ons olidated into the sp ecific ation

update and are no longer published in other documents.

This document may also conta in informa tion that was not previously published.

Affected Documents/Related Documents

Nomenclature

Errata

are design defects or errors.

These may cause the Intel

41110 behavior to

deviate from published specifications.

Hardware and software designed to be used with

any given stepping must assume that all errata documented for that stepping are

present on all devices.

Specification Changes

are modifications to the current pu blis hed s pecification s.

These changes will be incorporated in any new release of the specification.

Specification Clarifications

describe a specification in greater detail or further

highlight a specification’s impact to a complex design situ ation.

These clarifications will

be incorporated in any new release of the spec ification.

Documentation Changes

include typos, errors, or omissions from the current

published specifications. These will be inco rporated in any new re lease of the

specification.

Note:

Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances,

errata removed from the specification update are archived a nd available upon request.

Specification changes, spe cifica tion clarification s an d doc umentation changes are

removed from the specification upd ate when the appropriate changes are made to the

appropriate product specification or user documentation (datasheets, manuals, etc.).

Title Orde r

Intel

41110 Seria l to Parallel PC I Bridge Developer’s Manual

310183

Intel

41110 Seria l to Parallel PC I Bridge Design Guide

310335

Intel

41110 Seria l to Parallel PC I Bridge Datash eet

310182

Intel

41110—Summary Table of Changes

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

6Order Number: 311638-002US

Summary Table of Changes

The following table indicates the errata, specific ation cha n ges , spe cifica tion

cl ar if ic atio ns, o r d oc ume ntat i on c ha nge s w hi ch ap p l y t o t he I nt e l

41110 product.

Intel

may fix some of the errata in a future step p ing of the comp onen t, and acc ount for the

other outstanding issues through documentation or specification changes as noted.

This table uses the following notations:

Codes Used in Summary Table

Stepping

X: Errata exists in the stepping indicated.

Specification Change or

Clarification that applies to this stepping.

(No mark)

or (Blank box): This erratum is fixed in listed stepping or specificatio n change

does not apply to listed stepping.

Page

(Page): Page location of item in this documen t.

Status

Doc: Document change or update will be implemented.

Fix: This erratum is intended to be fixed in a future step of the

component.

Fixed: This erratum has been previously fixed.

No Fix: There are no plans to fix this erratum.

Plan Fix: This erratum may be fixed in a future stepping of the product.

Row

Change bar to left of table row indicates th is erratum is either

new or modified from the previous version of the document.

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 7

Summary Table of Changes—Intel

41110

Errata

No.

Steppings

Page Status Errata

C1 # # #

1X10 No Fix Secondary bus PxPCIRST# pulse prior to the rising

edge of PERST#

2X10 No Fix Unable to train in ×1 on Lane 3, 4, or 7 when Lane 0 is

broken

3X10 No Fix IOxAPIC End-Of-Interrupt (EOI) register is read/write

but should be write -only

4X11 No Fix Unreliable PCI Express link operation when L0s active

state power managemen t is enabled

5X11 No Fix Slow edge rates are observed when the Intel® 41110

Serial to Parallel PCI Bridge is driving the PCI-X bus at

specific temperatures

6X11 No Fix SSE bit set for PERR# assertion when error reporting

is ma sked

7X12 No Fix Data Parity Error detected on PCI/X interface fails to

propagate bad parity

8X12 No Fix Bridge Fails to train down in the presence of a

degraded lane

9X13 No Fix PCI Express and PCI-X Header Logs and First Error

Pointers do not remain sticky through reset.

10 X13 No Fix Incorrect Default Value for PCI Express Flow Control

Protocol Error Severity Bit.

11 X13 No Fix Power State Bits in P CI Express Power Man age men t

Control/Status Register mistakenly accept reserved

values.

12 X14 No Fix Performa nce across an Upstream x1 PCI Express Link

is less than expe cte d.

13 X14 No Fix SKP Ordered Set may not be sent within required

interval during link recovery if a packet is pending

14 X15 No Fix PCI Express ESD enhancemen t requires a change to

15 X15 No Fix SERR fatal/non-fatal error message enabled with

incorrect err or messa ge ena bled bit

16 X16 No Fix Byte Enables (BE) not included in P CI delaye d read s

can cau se dat a corru ption

17 X16 No Fix Bridge may become unresponsive when transitioning

into the D3 power state.

18 X17 No Fix Under certain conditi ons, i nbound prefetched PCI read

requests may return wrong data to the requestor

19 X17 No Fix Bridge In co rrectly Reports Itself as a Multi-Function

Device

Intel

41110—Summary Table of Changes

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

8Order Number: 311638-002US

Specification Changes

No.

Steppings Page

Specification Changes

A1 B0 C0 C1

1XXXX18 L0s state is not supported

2XXXX18 Linear Voltage Regulators are Recommended for 1.5 V

supplies

3XXXX18 Updated Power Sequencing Steps for VCC15 and VCC33

Voltages

4XXXX19 Use Microcontroller When Implementing Some Erratum

Workarounds

5XXXX19 BCNF Bit 3 Changed to Reserved bit

6XXXX19 R EFCLK relationship to voltage rails

Specification Clarifications

No.

Steppings Page

Specification Clarifica tions

A1 B0 C0 C1

1XXXX20 SM Bus connection recommendations for PCI Express*

adapter c ards

2XXXX20 Bridge Device ID corrected to 032D

3XXXX21 41x10 interaction with 5V PIC microcontroller may be

intermittent

Documentation Changes

No. Document

Revision Page Documentation Changes

310182

310183

310335

22 L0s state is not supported.

2310183 22 Device REVID 00h (is an error) and needs to be changed to 09h per the C1

revision

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 9

Identification Information—Intel

41110

Identification Information

Markings

Figure 1. Marking Information

Part Number Stepping Q Number MM Number

a. MM = Material Master ID. Reference the MM Number when placing an order.

Notes

NQ41110 Production SL93T 878375 Pb (Leaded)

QG41110 Production SL93U 878377 Pb free (Lead free)

NQ41110

XXXXXXXX

QXXXES

‘03

M C

Part #

FPO #

Q #

Intel Copyright

Intel

41110—Errata

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

10 Order Number: 311638-002US

Errata

1. Second ary bus PxPCIRST # pulse prior to the rising edge of PERS T#

Problem: During system power on and prior to the 41110 Bridge receiving the rising edge of

PERST#, a pulse is observed on the secondary bus PxPCIRST# signals.

Implication: PCI/PCI-X controllers on the secondary bus segments could interpret this PxPCIRST#

pulse as a true rising edge and initialize into an undetermined state.

Workaround: A temporary HW workaround has been identified. The PERST# signal that is received

by the 41110 Bridge co mp o ne nt sh o ul d be u se d to ga te the s eco n da ry bu s P xPCIRS T#

signals.

Status: No Fix. See the “Summary Table of Changes” on page 6.

2. Unable to tr ain in ×1 on L ane 3, 4 , or 7 when Lane 0 is broken

Probl em: The 41110 fails to train as a × 1 wi dth o n eith er La ne 3, 4, or 7 w h en Lan e 0 is bro ken

(in other words, not electrically visible to the M CH/XMB/TMB).

Implication: This problem prevents 41110 Bridge training as a ×1 in Lane 3, 4, or 7 (w hen Lane 0 is

broken or oth erw ise electric al ly disc o nn ec ted).

Workaround: None

Status: No Fix. See the “Summary Table of Changes” on page 6.

3. IOxAPI C End-Of-Interrupt (EOI) register is read/write but sho uld be

write-only

Problem: The IOxAPIC End-Of-Interrupt register (EOI) (Bus 0, Device 0, Functions 1 and 3,

Direct Memory Space Register, Offset 40h) should be write-only. The APIC specification

specifies that this register must be implemented as write-only. In the 41110, this

Implica tion: When im plemen ted as wri te-only, this register return s the value F Fh wh en read . Sin ce

this register is implemented as read -write, the 41110 Brid ge returns the “re al” value of

the register contents when read.

There is no impact to functionality.

Workaround: None.

Status: No Fix. See the “Summary Table of Changes” on page 6.

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 11

Errata—Intel

41110

4. U nreliable PCI Express link operation when L0s active state power

m ana ge m e nt is ena ble d

Problem: PCI Express* link operation is unreliable after the L0s state is enabled in the 41110

Bridge.

Implication: When L0s is enabled, the system may hang or be have in an u nsta ble ma nner.

Workaround: The link control register must be written to prevent the 41110 from entering L0s. A

platform- dependent BIOS workaround has been identified. Please refer to Specification

Changes “L0s state is not supported” on page 18 and to the Intel

41110

Initialization

by the SMB Bus Using The PIC16F876A Microcontroller White Paper (302281)

for

details on how to disable L0s support and implement this workaround.

Note:

The Intel® 41110 Serial to Parallel P CI Bridge Initialization Cus tomer Reference Code

associated to this workaround is available from Intel. Cont act your Intel Representative

for more information.

Status: No Fix. See the “Summary Table of Changes” on page 6.

5. Slow edg e rate s a re ob se rv ed w hen t he In t el

4111 0 Seri al t o P aral l el

PCI Bridge is driving the PCI-X bu s at specific tempe ratures

Problem: Signal-integrity issues may occur at a specific temperature when 41110 Bridge is

driving the PCI/PCI-X bus. This issue is highly sensitive to temperature and occurs

within a narrow range (1–2 °C) within the normal operating temperature range. The

failing temperature varies for each die. The cause of the problem is that a hidden

signals.

Implication: Parity errors and system hangs may occur.

Workaround: Write 1s to the bridge configuration spa ce (addre ss offset 224h , bits[29:17], fu nctio n 0

and 2). This must be done before any PCI-X bus access occurs. Please refer to the

Intel

41110

Initialization by the SMB Bus Using The PIC16F876A Microcontroller

White Paper (302281)

for details on implementing this workaround.

Note:

The Intel® 41110 Serial to Parallel P CI Bridge Initialization Cus tomer Reference Code

associated to this workaround is available from Intel. Cont act your Intel Representative

for more information.

Status: No Fix. The workaround must be in place for all steppings of the 41110 Bridge. See the

“Summary Table of Changes” on page 6.

6. SSE bit set for PERR# assertion when error reporting is masked

Problem: During a downstream memory write to 41110 Bridge, the following erroneous behavior

is seen whe n PE RR# is as serted on the sec o nd ary bu s:

• Signaled System Error (SSE) in the STS_REG register (D:0, F:0&2, offset 06h, bit

14) is set when SERR# Enable (SEE ) (D:0, F:0&2, offset 04h, bit 8) an d Parity

Error Response Enable (PERE) (D:0, F:0&2, offset 04h, bit 6) are set in the CMD

• The PERE bit in the BRDG_C N TL register is set (D:0, F:0&2, offset 3E h, bit 0).

• Error reporting is disabled in the UN C_PXERRMSK register (D:0, F:0&2, offset

130h).

Implication: False indication of an error message escalated as recorded in SSE of the STS_REG

functioning properly.

Workaround: None at this time.

Status: No Fix. See the “Summary Table of Changes” on page 6

Intel

41110—Errata

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

12 Order Number: 311638-002US

7. Data P arity Error detected on P C I/X in terface fails to propag ate bad

parity

Problem: In PCI and PCI-X mode using 32-bit data transfers, when a read request gets

disconnected at an even dword boundary with data parity error, such that the

subsequent request for partial data gets retried, the completion for this request is

issu ed over PCI Expre ss to the MC H (root com plex) with out the po iso ned data EP field

set in the PCI-Express TLP header.

Implication: Corrupted Data forwarded without error indication if error escalation is not enabled.

Workaround: Uncorrectable error escalation must be enabled in the MCH and 41110 Bridge to

contain this data parity escape. Therefore, a complete wo rkarou nd fo r this E rratum w ill

also require MCH/root complex escalate parity errors correctly appropriate platform.

Pleas e refer to the Intel

41110

Initia lization by the SM B Bus U sing The PIC16F876A

Microcontroller White Paper (302281)

for details on implementing this workaround.

Note:

The Intel® 41110 Serial to Parallel PCI Bridge Initialization Custo mer Reference Code

associated to this workaround is available from I ntel. Contact your Intel R epresentat ive

for more information.

Status: No Fix. See the “Summary Table of Changes” on page 6

8. Bridge Fails to train down in the presence of a degraded lane

Problem: Problem:During the PCI Express training sequence, if a broken endpoint has correct

receiver termin ation on a lan e and trans mits trainin g sequ ence s on the la ne wh ich are

invalid, the 41110 Bridge will fail to link train.

Implication: The PCI Express specification intends that, if some lanes are transmitting bogus data

instead of valid training sequences, those lanes should be treated as broken, and the

link s hou ld fa il do wn to an acc eptable width , su ch a s x1. If Lane 0 were failin g in this

manner, the PCI-E specification would anticipate that the link would fail to train. If a

high er-nu mb ered lan e w ere fai lin g in th is m an n er, th e P CI-E spe cif ica tio n re qu ires tha t

the lin k attemp t to train as a x1 on lan e 0. In either case , 41110 Brid ge wil l no t tra in

for the problem scenario.

On production material, failures are an ticipa ted to be either a broken tran smi tter path

or a broken receiver path, or a silent transmitter. 41110 Bridge will train properly for

these failure modes, since either the receiver termination will be mis sing, or th e

transmitted signals will not be seen at the 41110 Bridge. In order to see invalid

transmitted data on lanes at the 41110 Brid ge, e ither a logic bug in the o ther P C I-E

endpoint would be required, or a signal in tegrity issue s o severe as to make o peration

impossible, such as a broken or intermittent connection.

Workaround: None. A non-compliant or broken device could exhibit this erratum.

Status: No Fix. See the “Summary Table of Changes” on page 6

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 13

Errata—Intel

41110

9. PCI Express an d PCI-X Header Logs and First Error Pointers do not

remain sticky through reset.

The PCI Express and PCI-X header logs an d Firs t Error p ointers are n ot ma intain ing

their values after a warm/hot reset. These registers should be unaffected by a

warm/hot reset, but instead, they are reset to d efault valu es. The fo llowing registers

with “sticky” bits are affected: ADVERR_CTL (o ffset 118h), HDR_LOG (offset 11Ch ),

PCIXERRUNC_PTR (offset 138h), PCIXHDR_LOG (offset 13Ch)

Implic ation : Errors detected will be lo gged a nd es cala ted prop erly, but af ter a warm /hot re set, th e

header logs and first error pointers will reset to th eir defa ult valu es.

Note:

Error status registers are unaffected, and properly main tain th eir values thro ugh reset.

Workaround: None at this time.

Status: No Fix. See the “Summary Table of Changes” on page 6

10. Incorrect Default Value for P C I Expre ss Flow Control Protocol Error

Severity Bit.

Problem: The PCI Express Flow Control Error Severity bit, register offset 10C, bit 13, is

programmed to a default value of 0, indicating an uncorrectable flow control error will

be reported as non-fatal. This is in contradiction with the PCI Express Specification,

whic h r e q uir es a d e f aul t val u e of 1, i nd ic atin g a n un co r r ec t ab l e fl ow co nt r ol e r r or w il l be

reported as fatal.

Implic atio n : Impl ic atio ns fo r th is erratum de pen d up on th e e rror resp on s e s trategy im ple me nted in

a speci fic system.

This bit can be reprogrammed to match the specified default value if desired. Refer to

the Intel

41110

Initialization by the SMB Bus U sing The PIC 16F876A Micro con troller

White Paper (302281)

for details on this workaround.

Note:

The Intel® 41110 Serial to Parallel P CI Bridge Initialization Cus tomer Reference Code

associated to this workaround is available from Intel. Cont act your Intel Representative

for more information.

Status: No Fix. See the “Summary Table of Changes” on page 6.

11. Power State Bits in PCI Express Power Management Control/Status

Prob lem: The Pow er State b its, bi t 1:0 o f PM_PM CSR (Off set 70h) wi ll allo w a res erved valu e of

01 or 10 to be written. This is contrary to the specification, whic h o riginally stated th at

if software attempted to write an unsupported reserved state to this field, the data

would be discarded and no state change would occur.

Implic atio n : If a re serve d s tate is wri tten to this fi eld , there w ill be a mi sm atch betw een th e ac tua l

pow er state of the part an d the state repo rted in con figuration s pace. In s ome case s,

writin g a reserve d value to this fiel d cou ld ca use the 41110 Bridge to trans ition to the

D0 power state, regardless of the previo us po wer s tate.

Workaround: Never write a reserved value to this bit field.

Status: No Fix. See the “Summary Table of Changes” on page 6.

Intel

41110—Errata

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

14 Order Number: 311638-002US

12. Performance across an Upstream x1 PCI Express Link is less than

expected.

Problem: When the 41110 Bridge is configured with an upstream x1 PCI Express link, the

realized performance is significantly less than the predicted linear assumption that a x1

link will provide ¼ the performance of a x4 link. This is caused by c ircum stanc e s where

41110 Bridge mu st disca rd a larg e portio n of the data it rece ives ac ross th e upstre am

link. Notab ly; anytime 41110 Bridge services an incorrect prefetch, or anytime 41110

Bridge services interleaved requests from multi-function devices, 41110 Bridge must

discard data.

The problem occurs because, in PCI mode, the target memory has no indication of the

amo unt of dat a t o se nd i n re sp on se t o a r e a d r e q ue st . I t mus t r e l y up on pr e f etch po li cy

and di s con nect s . I f a di s con ne ct oc cu r s, it mus t d is ca r d (p os si b ly s t al e ) da t a . D a t a that

is discarded after consuming bandwid th on the P CIe b us mu st then be re-read and c an

become a significant percentage of the available PCIe ba ndwidth.

Single-function masters on a PCI bus segme n t typically do not ex hibit this beh avior.

Mul t i -f unc t i on de v i ce s and / or mu ltip l e dev i ce s on a PCI bu s se gm e nt ar e mor e li k e ly t o

cause this problem, since they are likely to interleave read requests, which is a primary

cause of data discard.

This problem has not been seen in P CI-X, be cau se byte co un ts of read requ ests a re

known, buffers are preallocated and data do es n ot need to be discarded.

Implica tio n: Devices tha t rel y h eavi ly o n p refetc hi ng , or mu lti-fu n ctio n de vic es tha t requ es t da ta in

an interleaved fashion are the mos t likely to experien ce d egraded performance.

Workaround: System designers should reduce the amount of prefetching allowed to devices behind

41110 Bridge if possible.

Status: No Fix. See the “Summary Table of Changes” on page 6

13. SKP Ordered Set may not be sent within required interval during link

recove ry if a pa cket is pen d ing

Problem: During Link Recovery on the PCI Express port, the device may fail to transmit a SKP

Ordered set within the required time interval as defined in the PCI Express 1.0a

Specification if a TLP or DLLP was pending when the link en tered Recovery.Idle state.

Implica tio n: If the rece ivin g d evic e d epe nd s u po n rece ipt o f a SKP Ord ered se t to pro gre ss thro ug h

Link Recovery, a timeout will occur resulting in Link Down and a u toma tic reinitialization

of the PCI Express Link. A link transitions through Recovery only under exceptional

operational conditions. Following the Link Recovery timeout an d reinitialization, the PCI

Express link should resume normal operation unless the original Link Recovery

condition was entered as a result of a hard failure mechanism.

Workaround: None.

Status: No Fix. See the “Summary Table of Changes” on page 6.

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 15

Errata—Intel

41110

14. PCI Express ESD en ha ncem en t requires a change to register settings

Problem: Validation has shown PCI Express ESD enhancement, with changes to undisclosed

registers in the 41110 Bridge.

Implication: The workaround that follows inc reases the margin fo r the eye and res ults in a healthie r,

improved PCI Express link.

Worka round: S et F0/F2:R260h bit[15] to 1 and clear F0/F2:R270h bit[31] to 0. This workaround is

requi red fo r bo th c ol d an d wa rm res et. Refer to the

Intel® 41110 Se ria l to Pa ral lel PCI

Bridge Initialization by the SMBus using the PIC16F876A Microcontroller White Paper

(302281) for details on implementing th is wo rkarou nd.

Note:

The Intel® 41110 Serial to Parallel P CI Bridge Initialization Customer Reference Code

associated to this workaround is available from Intel. Cont act your Intel Representative

for more information.

Status: No Fix. See the “Summary Table of Changes” on page 6.

15 . SERR fata l/no n-fatal erro r m e ssage ena b led w ith in cor rect error

message enabled bit

Problem: When Secondary bus SERR errors are not being escalated (i.e., when the SERR#

Enable (SEE) bit in the PCI Command Register (offset 0x4) is not set), then the

Advanced Error Reporting scheme concerning SERR configuration is flawed. Specifically,

whe n SE RR is con fi gu red as a fatal error, the gen eratio n o f a SE RR fatal error me ss ag e

is mistakenly gated by the Non-Fatal Error Reporting E nable d bit (bit[1]) instead of the

Fatal Error Reporting enabled bit (bit[2]) of the Device Control Register (offset 4Ch).

Likewise, when SERR is configured as a non-fatal error, the generation of a SERR

non-fatal error message is gated by the Fatal Error Reporting enabled bit.

Implication: The SERR fatal error message can be gener ated only when non-fatal error messaging is

enabled, and the SERR non-fatal error m essa ge can be genera ted onl y when fatal erro r

messaging is enabled.

Workaround: The workaround for this errata is implementation specific. The following are options for

working around this errata:

• ................. Set the SERR# enable bit in PCI command register (offset 0x4 - bit 8)

• ... ........ ........ ...................................................... For Adv anced Error rep orti ng:

Set the Report NonFatal and Fatal Erro r bits (o ffset 0x4C - bits 1 and 2).

• ....... I f using the Advanced Error reporting capabilit y for SERR# escalation as Fatal

(ERR_FATAL):

Set the Report NonFatal Error enable bit (offset 4c, bit 1) and mask other PCI-X

errors that are set to NonFatal, using offset 0x134 and 0x130, if escalation of those

errors is no t desire d.

• If using the Advanced Error reporting capability for SERR# escalation as Non-F atal

(ERR_NonFATAL):

Set the Report Fatal errors en able b it (offset 4c, bit 2).

Status: No Fix. See the “Summary Table of Changes” on page 6.

Intel

41110—Errata

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

16 Order Number: 311638-002US

16. Byte Enab les (BE) not included in PCI delayed reads can caus e data

corruption

Problem: A PCI device on one of the secondary busses that generates a zero length read request

may cause data corruption in platforms utilizing non-Intel MCH components, as the

byte enables (BE) are not included by the 41110 bridge in ma tching comp letion s to PCI

delayed read requests.

Implication: All Intel MCH devices will return data consistent with the address of a zero-length read

reques t. No co rru ptio n ca n o c cu r if a su bs equ en t no n -zero -len gth rea d is in adve rtently

comp leted with da ta returned on beha lf of the zero -length request bu t this behavi or is

not required by specification.

The following is an example ca se:

1. A memory read request with zero BE is issued over PCI, a corresponding zero

length read results on PCI-Express to th e ho st.

2. A PCI device on the same PCI segment issues a MR/MRL /MRM to the same address

with valid BE’s.

3. The 41110 bridge matches the completion for the Memory Read request on line 1

to the request on line 2 (i.e. - BE’s are igno red.)

4. Unspecified data (returned for the zero-length read reques t) is driven to the PCI

card, resulting in data corruption.

Note:

This exclusively affects PCI mode and is n o t an issue when the secondary busses are

operating in PCI-X mode. Whether corruption can occur through this mechanism is

dependent upon behavior of the non-Intel MCH component. If the MCH in use behaves

similarly to Intel MCH designs, there is no expos ure to data co rruptio n, and th e

incomplete completion match will not have an y side-effects.

Workaround: None.

Status: No Fix. See the “Summary Table of Changes” on page 6.

17. Bridge ma y beco me unresponsive when transitioning into the D3

power state.

Probl em: When the 41110 Bridge tran sition s to a p ower state o f D3 o r lo wer, th e 41110 Bri dge

may becom e un res po ns ive.

Implication: There have been no observed failures on systems with currently available software.

Operating systems th at independently manage the power state of the 41110, outside

the scope of system level power state transitions, may result in the loss of link

communications to the MCH.

Workaround: Independent device power state management of the 41110 should be avoided. If the

41110 Bridge beco mes u nresp onsi ve, a fu nda mental device reset mu st be as serted to

return the system to norm al operation.

Status: No Fix. See the “Summary Table of Changes” on page 6.

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 17

Errata—Intel

41110

18. Under certain conditions , inbound prefetched PCI read requests m ay

retu r n wr o ng da ta to the requ e sto r

Prob lem : With so me pre fetc h po li cy se tting s, the 41110 may over-aggre ss ively prefetc h da ta fo r

PCI reads and subsequently return the wrong data to the requestor. This problem only

exists when there is more than one active agent on the PCI bus. It exists for all

supported frequencies and exists on both 41110 PCI segments. It does not effect

PCI-X operation at any supported frequency.

Implic ation: Inb ound re ad reques ts that are en abled fo r prefetchin g may return invalid data w hen

multiple agents exist on the same PCI bus. No error is reported by the 41110.

Worka rou n d: S et D0:F0/F 2 O ffse t 184h (Dwo rd) bit [2] to 1. The w o rkaro u nd c o rrects th e p rob lem

at all supported frequencies and all prefetch p olicy settings.

Status: No Fi x. Not to be fixed. The w orkaro und must b e left in place for al l 41110 s te pping s.

See the “Summary Table of Changes” on page 6.

19. Bridge Incorrectly R eports Itself as a Mu lti-Fun ction Device

Problem: The multi-function bit is set ON in the Header Type configuration register, offset Eh,

identifying that there are multiple functions associated with the device when there is

only one.

Implication: Configuration software assumes that there are multiple devices behind the bridge and

may perform unnecessary operations.

Workaround: None. Software needs to verify that a function is valid before taking action.

Status: No Fix. Not to be fixed. See the “Summary Table of Changes” on page 6.

Intel

41110—Specification Changes

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

18 Order Number: 311638-002US

Specification Changes

1. L0s state is no t suppo rted

Issue: The L0s state has been defeatured in the 41110 Bridge.

Affected Docs:Intel

41110 Serial to Parallel PCI Bridge Datasheet (278885-001)

Intel

41110 Serial to Parallel PCI Bridge Developer’s Manual (278890-001)

Intel

41110 Serial to Parallel PCI Bridge Design Guide (278801-001)

2. Linea r Voltage Regu lato rs are Recommended for 1.5 V supplies

Issue: Linear Voltage regulators are recom mended when using 1.5 Volt power supplies.

Affected Docs:Intel

41110 Serial to Parallel PCI Bridge Design Guide (278801-001)

3. Updated Power Sequencing Steps for VCC15 and VCC33 Voltages

Issue: The following three steps are the power sequencing requirements that must be

followed with the 41110 Bridge:

1. The 41110 Bridge requires that the VCC33 voltage rail be no less than 0.5V below

VCC15 (absolute voltage value) at all times during 41110 o peration , includin g

during system power up and power down. In other words, the following must

always be true:

VCC33 >= (VCC15 – 0.5V)

This can be accomplished by placing a diode (with a voltage drop <0.5V) between

VCC15 and VCC33. A node w ill be connected to VCC15 and cathode will be

con ne cted to VCC33.

If VCC15 (1.5V PCI-X I/O voltage) and VCC (1.5V core voltage) are tied together

on the platform, then both voltages must meet the above rule.

Note:

Linear voltage regulators are recommended when using 1.5 Volt power supplies.

2. If a voltage regulator solution is used which shunts VCC15 to ground while VCC33

is powered, the maximum allowable time that VCC15 can be shunted to ground

while VCC33 is fully powered is 20ms. This includes c onfig uration s wh ere VCC and

VCC15 are powered by the same power source.

3. The maximum allowed time between VCC33 and VCC15 ramping is 525ms.

Note:

There is no minimum sequencing time requirement other than requirements

in Steps 2 and 3.

Affected Docs:Intel

41110 Serial to Parallel PCI Bridge Design Guide (278801-001)

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 19

Specification Changes—Intel

41110

4. U se M icrocon troller When Implementing Some Erratum Workarounds

Issu e: Th e w o rkaro u nd s fo r a n um ber of erratum ob se rved in th e 41110 Seri al to Parall el P CI

Bridg e (Erratum 19, 20, 25, 28, an d 32) require tha t Config uration Space registers b e

loaded with specific values. Intel requires that this be done using the microcontroller

attached to the 41110 Bridge SM Bus prior to releasing the CFGRETRY signal.

Affected Docs:Intel

41110 Serial to Parallel PCI Bridge Developer’s M anu a l (278890-001)

Intel

41110 Serial to Parallel PCI Bridge Des ign Guide (278801-001)

5. BCNF Bit 3 Change d to Reserved bit

Issue: Bit 3 in the Bridge Configuration Register (Offset 40 in both A- and B- bridges) is

currently defined as ‘Downstream Delayed Transaction Resource Partitioning (ODTP)’

with a default setting of ‘0’. Setting this bit to ‘1’ may cause undesired functionality;

therefo re BCNF.3 is changed to ‘reserved’. As a ‘reserved’ bit, the default condition of

‘0’ should be maintained and BIOS firmware should never set this bit to a ‘1’.

Affected Docs:Intel

41110 Serial to Parallel PCI Bridge Developer’s M anu a l (278890-001).

6. R EFCLK r e lationship to voltage rails

Issue: When the 41110 is on an add-in card, only 3.3V and 12V are provided to the slot,

therefo re, a l oc al regu la tor is requ ire d fo r 1.5V an d 2. 5V ge ne ration . Due to the dela y

by the local regulators, REFCLK may already be provided before the power rails are

stable. If this is the case, no device overstress will occur, provided that the REFCLK

input current does not exceed 900mA and the input voltage does not exceed the PCI

Expres s s pe cif ica tio n o f 1. 15V. RE F CLK bu ffers on m any Intel pla tform s s ho w an in pu t

current of 15.6mA, well under the 900mA limit.

The requirement for "all 41110 voltage rails to be stable before the PCI Express

differential clocks REFCLKp and REFCLKn begin run ning" is no lo nger a requiremen t.

Affected Docs:Intel® 41110 Serial to Pa rallel Bridge Des ign Guide (278801-003)

Intel

41110—Specification Clarifications

Intel

41110 Serial to Parallel PCI Bridge

Specification Update September 2007

20 Order Number: 311638-002US

Specification Clarifications

1. SMBus connection recommendations for PCI Express* adapter cards

Issue : PCI Express * cards based on the 41110 Bridge must implement the SMBus signals in

one of the fo llo wi ng ways:

1. The SMDAT and SMCLK signals from the PCI Express* connector must be left as

"no connects". The SMBCLK and SMBDAT signals on the 41110 must have pull-ups

even when they are not used . The pull-ups p revent the inpu ts from oscillating and

potentially causing other problem s.

2. When the SMBus feature is require d, an isolation devic e (for e xample , the

LTC4301) mus t be placed between the SMBus signals on the PCI Express*

connector and the 41110, so that the system has no connection to the 41110 on

these two signals when powe r is off.

For embedded/backplane designs, it is assume d that the SMBus is routed only to

devices that are required and that remain powered

Affected Docs:

Intel

41110 Serial to Parallel PCI Bridge Datashee t

and

Intel

41110 Serial to Parallel PCI Bridge Develo per’s Manual

2. Bridge D evice ID correcte d to 0 32D

Issue : In sec tion 12.2.1, Tab le 35, o f the 41110 Developer's Man ual, bits [31:16] inco rrectly

state the device ID for the 41110. Bits [31:16], in Section 12.2.1, Table 35, now

appears as follows:

Affected Docs:

Intel

41110 Serial to Parallel PCI Bridge Deve lope r’s Manual

Intel

41110 Serial to Parallel PCI Bridge

September 2007 Specification Update

Order Numbe r: 31 16 38 -00 2U S 21

Specification Clarifications—Intel

41110

3. 41 x1 0 interaction with 5V P IC micro con troller m ay b e interm ittent

Issu e: The In tel 41x10 Cus tomer referenc e bo ard co ntain s a n erro r that m ay preven t prop er

operation on the PIC microcontroller. The 41x10, a 3.3V logic device is asserting a

signal to a Schmitt trigger input of a 5V part (PIC Microcontroller - PIC16F876A -

requires 4V for a logic high on the Schmitt trigger input). In certain cases, the PIC

microcontroller may not detect the logic high and thus fail to execute the PIC

initialization code.

Only designs which leveraged the 41x10 reference board with the implemenat ion of the

5V PIC microcontroller are affected. Implementations using a 3.3V microcontroller are

not affected by this issue.

A fix to the PIC initialization reference co de h a s been iden tified to workaround this

issue.

Note:

The Intel 41x10 Serial to Parallel PCI Bridge Initialization Customer Reference Code

associated with this fix is available from Intel. Co ntact yo ur In tel repres entative fo r