PIC12F509T-I/SN - MICROCHIP TECHNOLOGY

PIC12F508/509/16F505

Data Sheet

8/14-Pin, 8-Bit Flash Microcontrollers

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by up dates. I t is you r r es ponsibil it y to

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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC , PI Cmi cro, PIC START,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE, In- Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PIC DEM .net, PICkit,

PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microch ip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

PIC12F508/509/16F505

Devices Included In Thi s Data Sheet:

High-Performance RISC CPU:

• Only 33 Single-Word Instructions to Learn

• All Single-Cycle Instructions Except for Program

Bran ches, which ar e Two-Cycle

• 12-Bi t Wide Instructions

• 2-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

for Data and Instructions

• 8-Bit Wide Data Path

• 8 Special Function Hardware Registers

• Operati ng Sp eed :

- DC – 20 MHz clock input (PIC16F505 only)

- DC – 200 ns instruction cycle (PIC16F505

only)

- DC – 4 MHz clock input

- DC – 1000 ns instruction cycle

S pecial Microcontroller Features:

• 4 MHz Precision Internal Oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) Su pport

• Power-On Reset (POR)

• Device Re se t Timer (DR T)

• Watchdog Timer (WDT) with Dedicated On-Chip

RC Oscillator for Reliable Operation

• Programmable Code Protection

• Multiplexed MCLR Input Pin

• Internal Weak Pull-Ups on I/O Pins

• Power-Saving Sleep mode

• Wake-Wp from Sleep on Pin Change

• Selecta ble Oscillator Options:

- INTRC: 4 MHz precision Internal oscillator

- EXTRC: External lo w-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

(PIC16F5 05 onl y)

- LP: Power-saving, low-frequency crystal

- EC: High-speed external clock input

(PIC16F5 05 onl y)

Low-Power Features/CMOS Technology:

• Operating Current:

- < 175 μA @ 2V, 4 MHz, typical

• Standby Current:

- 100 nA @ 2V, typical

• Low-Power, High-Speed Flash Technology:

- 100,000 Flash endura nce

- > 40 year retention

• Fully Static Design

• Wide Operating Voltage Range: 2.0V to 5.5V

• Wide Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Feat ures (PIC12F508/509):

• 6 I/O Pins:

- 5 I/O pins with individual direction control

- 1 input only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pu ll-ups

• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit

Programmable Prescaler

Peripheral Feat ures (PIC16F505):

• 12 I/O Pins:

- 11 I/O pins with ind iv idu al dire ction control

- 1 input only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pu ll-ups

• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit

Programmable Prescaler

• PIC12F508 • PIC12F509 • PIC16F505

8/14-Pin, 8-Bit Flash Mi croc ontrollers

PIC12F508/509/16F505

Pin Diagrams

PIC16F505 16-Pin Diagram (QFN)

PDIP, SOIC, TSSOP

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

VSS

RB0/ICSPDAT

PIC16F505

RC5/T0CKI

RC4

RC3

RB1/ICSPCLK

RB2

RC0

RC1

RC2

PDIP, SOIC, MSOP

VDD

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

VSS

GP0/ICSPDAT

PIC12F508/509

GP1/ICSPCLK

GP2/T0CKI

DFN

PIC12F508/509

VSS

GP0/ICSPDAT

GP1/ICSPCLK

GP2/T0CKI

VDD

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

PIC16F505

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

RC5/TOCKI

VDD

VSS

RB0/ICSPDAT

RB1/ICSPCLK

RB2

RC0

RC4

RC3

RC2

RC1

PIC12F508/509/16F505

Device Program Memory Data Memory I/O Timers

8-bit

Flash (words) SRAM (bytes)

PIC12F508 512 25 6 1

PIC12F509 1024 41 6 1

PIC16F505 1024 72 12 1

PIC12F508/509/16F505

Table of Contents

1.0 General Description................................ .. .... .. .... ......... .. .... .... .. ......... .... .. .... .. ......... .... .. ................................................................. 7

2.0 PIC12F508/509/16F505 Device Varieties .......................... .... ........... .... .... ......... .... .... .... ........... .... . ............................................. 9

3.0 Architectural Overview ............................................................................................................................................................... 11

4.0 Memory Organization................................................................................................................................................................. 17

5.0 I /O Po rt............... ........................... ............................ ........................... ...................................................................................... 31

6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 35

7.0 Sp e cial Features Of The CPU........................ ..................... ..................... ............................ ...................................................... 41

8.0 Instruction Set Summary............................................................................................................................................................ 57

9.0 Development Support................................................................................................................................................................. 65

10.0 Electrical Characteristics............................................................................................................................................................ 69

11.0 DC and AC Characteristics Graphs and Charts............................................................................. ............................................ 81

12.0 Packagin g In fo rmation....... ............... ..................... ........................... ..................... ........... .......................................................... 91

Index .................................................................................................................................................................................................. 105

The Micro chip Web Site.......... ........................... ........................... ............................ ......................................................................... 107

Customer Change Notification Service .............................................................................................................................................. 107

Customer Support.......................................................................................... ...... .............................................................................. 107

Reader Response.............................................................................................................................................................................. 108

Product Identification System............................................................................................................................................................. 109

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Most Current Data Sheet

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Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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Customer No tific atio n Syst em

PIC12F508/509/16F505

1.0 GENERAL DESCRIP T ION

The PIC12F508/509/16F505 devices from Microchip

Technology are low-cost, high-performance, 8-bit,

fully -stat ic, Fl ash-b ased C MOS mic rocon tro llers. They

employ a RISC architecture with only 33 single-word/

single-cycle instructions. All instructions are single

cycle (200 μs) except for program branches, which

take two cycles. The PIC12F508/509/16F505 devices

delive r perfor manc e an order of magnit ude high er than

their comp etitors i n the sa me price category. Th e 12-bit

wide instructions are highly symmetrical, resulting in a

typical 2:1 code compression over other 8-bit

microcontrollers in its class. The easy to use and easy

to remember instruction set reduces development time

significantly.

The PIC12F508/509/16F505 products are equipped

with special features that reduce system cost and

power requirements. The Power-on Reset (POR) and

Devic e Reset T imer (DR T) eliminate t he need for exter-

nal Reset circuitry. There are four oscillator configura-

tions to cho os e from (six on the PIC 16 F50 5), inc lu din g

INTRC Internal Oscillator mode and the power-saving

LP (Low-Power) Oscillator mode. Power-Saving Sleep

mode, Watchdog Timer and code protection features

improve system cost, power and reliability.

The PIC12F508/509/16F505 devices are available in

the cost-effective Flash programmable version, which

is suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership

in Flash programmable microcontrollers, while

benefiting from the Flash programmable flexibility.

The PIC12F508/509/16F505 products are supported

by a full-featured macro assembler, a software simula-

tor, an in-circuit emulator, a ‘C’ compiler, a low-cost

development programmer and a full featured program-

mer. All the tools are supported on IBM® PC and

compatible machin es.

1.1 Applications

The PIC12F508/509/16F505 devices fit in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The Flash technology makes customizing application

programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient. The smal l footpri nt p ackag es, for t hrough h ole or

surface mounting, make these microcontrollers perfect

for applications with space limitations. Low cost, low

powe r, high perfo rmanc e, eas e-of- use an d I/O f lexib il-

ity mak e the PIC12 F508/5 09/ 16F505 devices very v er-

satile even in areas where no microcontroller use has

been co nsidered befo re (e.g., timer f unctions, lo gic and

PLDs in l arge r s ystem s and coprocessor a ppl ic ati ons ).

TABLE 1-1: PIC12F508/509/16F505 DEVICES

PIC12F508 PIC12F509 PIC16F505

Clock Maximum Frequency of Operation (MHz) 4 4 20

Memory Flash Program Me mory (words) 512 1024 1024

Data Memory (bytes) 25 41 72

Peripherals Timer Module(s) TMR0 TMR0 TMR0

Wake-up from Sleep on Pin Change Yes Yes Yes

Features I/O Pi n s 5 5 11

Input Pins 1 1 1

Internal Pull-ups Yes Yes Yes

In-Circuit Serial Programming Yes Yes Yes

Number of Instructions 33 33 33

Packages 8-pin PDIP, SOIC,

MSOP, DFN 8-pin PDIP, SOIC,

MSOP, DFN 14-pin PDIP, SOIC,

TSSOP

The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current

capability and precision internal oscillator.

The PIC12F508/509/16F505 devices use serial programming with data pin RB0/GP 0 and clock pin RB1/GP1.

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

2.0 PIC12F508/50 9/1 6F5 05 DEVIC E

VARIETIES

A variety of packaging options are available. Depend-

ing on application and production requirements, the

proper device option can be selected using the

information in th is section. Wh en placing orde rs, please

use the PIC12F508/509/16F505 Product Identification

System at the back of this data sheet to specify the

correct part numbe r.

2.1 Quick Turn Programming (QTP)

Devices

Microchip offers a QTP programming service for

factory production orders. This service is made

available for users who choose not to program

medium-to-high quantity units and whose code

patterns have stabilized. The devices are identical to

the Flash devices but with all Flash locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are available. Please

cont act your loc al Microchip Technol ogy sales of fice for

more details.

2.2 Serialized Quick Turn

ProgrammingSM (SQTPSM) Devices

Microchip offers a unique programming service, where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry code,

password or ID number.

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

3.0 ARCHITECTURAL OVERVIEW

The hi gh pe rf or ma nce of t he P IC 12F 508/ 509 /1 6F 505

devices can be attributed to a number of architectural

features commonly found in RISC microprocessors.

To begin with, the PIC12F508/509/16F505 devices

use a H arvard archit ectur e in whi ch progr am and da t a

are accessed on separate buses. This improves

bandwidth over traditional von Neumann architec-

tures where program and data are fetched on the

same bus . Se para ti ng pro gr am an d data mem or y fur-

ther allows instructions to be sized differently than the

8-bit wide data wor d. Instruct ion opcode s are 12 bits

wide, making it possible to have all single-word

instructions. A 12-bit wide program memory access

bus fetches a 12-bit instruction in a single cycle. A

two-stage pipeline overlaps fetch and execution of

instructions. Consequently, all instructions (33)

execute in a single cycle (200 n s @ 20 MHz, 1 μs @

4 MHz) except for program branches.

Table 3-1 bel ow lists program memory (Flash) and da ta

memory (RAM) for the PIC12F508/509/16F505

devices.

TABLE 3-1: PIC12F50 8/5 09/1 6F 505

MEMORY

The PIC12F508/509/16F505 devices can directly or

indirec tly addres s its register f iles and data m emory. All

Special Function Registers (SFR), including the PC,

are mapped in the data memory. The PIC12F508/509/

16F505 devices have a highly orthogonal (symmetri-

cal) instruction set that makes it possible to carry out

any operation, on any register, using any addressing

mode. This symmetrical nature and lack of “special

optimal situations” make programming with the

PIC12F508/509/16F505 devices simple, yet efficient.

In addition, the learning curve is reduced significantly.

The PIC12F508/509/16F505 devices contain an 8-bit

ALU and working register. The ALU is a general

purpose arithmetic unit. It performs arithmetic and

Boolean fu nctions be tween da ta in the w orking reg ister

and any register file.

The ALU is 8 bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two’s comple-

ment in nature. In two-operand instructions, one

operand is ty pi ca lly the W (w ork ing ) re gis ter. The oth er

operand is either a file register or an immediate

const ant. I n sing le ope rand in st ruction s, the ope ran d is

either the W register or a file register.

The W registe r is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bit s in the ST ATUS regi ster . The C and DC bit s

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

Simplified bloc k dia grams are sho w n in Fig ure 3-1 and

Figure 3-2, with the corresponding pin described in

Table 3-2 and Table 3-3.

Device Memory

Program Data

PIC12F508 512 x 12 25 x 8

PIC12F509 1024 x 12 41 x 8

PIC16F505 1024 x 12 72 x 8

PIC12F508/509/16F505

FIGURE 3-1: PIC12F50 8/509 BLOCK DIAGRAM

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Flash

Program

Memory

12 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr 5

RAM Addr 9

Addr MUX

Indirect

Addr

FSR Reg

Status Reg

MUX

ALU

W Reg

Instruction

Decode and

Control

Timing

Generation

OSC1/CLKIN

OSC2

MCLR VDD, VSS

Timer0

GPIO

GP4/OSC2

GP3/MCLR/VPP

GP2/T0CKI

GP1/ISCPCLK

GP0/ISCPDAT

5-7

GP5/OSC1/CLKIN

Stack 1

Stack 2

512 x 12 or

25 x 8 or

1024 x 12

41 x 8

Internal RC

OSC

PIC12F508/509/16F505

TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

GP0/IC SPDAT GP0 TTL CMOS Bidirecti onal I/O pin. Can be soft ware programmed fo r internal

weak pull-up and wake-up from Sleep on pin change.

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

GP1/IC SPCLK GP1 TTL CMOS Bidirecti onal I/O pin . Can be soft ware programmed fo r internal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

GP2/T0CKI GP2 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is

an activ e-low Res et to the dev ice. Voltage on MC LR/VPP mu st

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP HV — Programming voltage input.

GP4/OSC2 GP4 TTL CMOS Bidirectional I/O pin.

OSC2 — XTAL Oscillato r cryst al out put. Conn ections t o cryst al or reso nator in

Cryst al Oscill ator mode (XT and LP mode s only , G PIO in other

modes).

GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O pin.

OSC1 XTAL — Oscillator crystal input.

CLKIN ST — External clock source input.

VDD VDD — P Positive supply for logic and I/O pins.

VSS VSS — P Ground reference for logic and I/O pins.

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, HV = High Voltage

PIC12F508/509/16F505

FIGURE 3-2: PIC16F505 BLOCK DIAGRAM

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Flash

Program

Memory

12 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Addr 5

RAM Addr 9

Addr MUX

Indirect

Addr

FSR Reg

Status Reg

MUX

ALU

W Reg

Instruction

Decode and

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

Timer0

PORTB

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

RB2

RB1/ICSPDAT

RB0/ICSPCLK

5-7

RB5/OSC1/CLKIN

Stack 1

Stack 2

1K x 12

72 bytes

Internal RC

OSC

PORTC

RC4

RC3

RC2

RC1

RC0

RC5/T0CKI

PIC12F508/509/16F505

TABLE 3-3: PIC16F505 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RB0/ICSPDAT RB0 TTL CMOS Bidirecti onal I/O pin . Can be soft ware programmed fo r internal

weak pull-up and wake-up from Sleep on pin change.

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

RB1/ICSPCLK RB1 TTL CMOS Bidirecti onal I/O pin. Can be softwar e programmed fo r internal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

RB2 RB2 TTL CMOS Bidirectional I/O pin.

RB3/MCLR/VPP RB3 TTL — Input port. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is

an activ e-low Res et to the dev ice. Voltage on MC LR/VPP mu st

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP HV — Programming voltage input.

RB4/OSC2 /CLKOUT RB4 TTL CMOS Bidirecti onal I/O pin. Ca n be softwa re programmed fo r internal

weak pull-up and wake-up from Sleep on pin change.

OSC2 — XTAL Oscillato r cryst al out put. Conn ections t o cryst al or reso nator in

Crystal Oscillator mode (XT, HS and LP modes only).

CLKOUT — CMOS In EXTRC and INTRC modes, the pin output can be

configu red for CLKOUT, which has 1/4 the frequency of OS C1

and denotes the instruction cycle rate.

RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin.

OSC1 XTAL — Crystal input.

CLKIN ST — External clock source input.

RC0 RC0 TTL CMOS Bidirectional I/O pin.

RC1 RC1 TTL CMOS Bidirectional I/O pin.

RC2 RC2 TTL CMOS Bidirectional I/O pin.

RC3 RC3 TTL CMOS Bidirectional I/O pin.

RC4 RC4 TTL CMOS Bidirectional I/O pin.

RC5/T0CKI RC5 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

VDD VDD — P Positive supply for logic and I/O pins.

VSS VSS — P Ground reference for logic and I/O pins.

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, HV = High Voltage

PIC12F508/509/16F505

3.1 Clocking Scheme/Instruction

Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC

is incremented every Q1 and the instruction is fetched

from program memory and latched into the instruction

following Q1 through Q4. The clocks and instruction

execution flow is shown in Fi gure 3-3 and Example 3-1.

3.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to cha nge (e.g., GOTO), then tw o c ycle s

are req uired to com plete the ins tructi on (Exampl e 3-1).

A fetch cycle begins with the PC incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q 3 and Q4 c ycles. Dat a mem ory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

PC PC PC + 1 PC + 2

Fetch INST (PC)

Execute INST (PC – 1) Fetch INST (PC + 1)

Execute INST (PC) Fetch INST (PC + 2)

Execute INST (PC + 1)

Internal

phase

clock

All instru ctions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

1. MOVLW 03H Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTB, BIT1 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC12F508/509/16F505

4.0 MEMORY ORGANIZATION

The PIC12F508/509/16F505 memories are organized

into program memory and data memory. For devices

with m ore than 512 bytes of program memo ry , a pa ging

scheme is used. Program memory pages are accessed

using one ST ATUS regist er bit. For the PIC12 F509 and

PIC16F505, with data memory register files of more

than 32 registers, a banking scheme is used. Data

memory banks are accessed using the File Select

4.1 Program Memory Orga nization for

the PIC12F508/509

The PIC12F508 device has a 10-bit Program Counter

(PC) and PIC12F509 has a 11-bit Program Counter

(PC) cap able of add ressing a 2K x 12 p rogram memo ry

space.

Only the first 512 x 12 (0000h-01FFh) for the

PIC12F508, and 1K x 12 (0000h-03FFh) for the

PIC12F509 are physically implemented (see

Figure 4-1). Accessing a location above these

boundaries will cause a wrap-around within the first

512 x 12 space (PIC12F508) or 1K x 12 space

(PIC12F509 ). The effective R eset vector is a 0000h

(see Figure 4-1). Location 01FFh (PIC12F508) and

location 03FFh (PIC12F509) contain the internal

clock oscillator calibration value. This value should

never be overw ritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12F508/509

CALL, RETLW

PC<11:0>

S tack Level 1

S tack Level 2

User Memory

Space

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector(1)

Note 1: Address 0000h becomes the

effective Reset vector. Location

01FFh, 03FFh (PIC12F508,

PIC12F509) contains the MOVLW XX

internal oscillator calibration value.

512 Word

1024 Word 03FFh

0400h

On-chip Program

Memory

PIC12F508/509/16F505

4.2 Program Memory Organization

For The PIC16F505

The PIC16F505 device has a 11-bit Program Counter

(PC) cap able of add ressing a 2K x 12 p rogram memo ry

space.

The 1K x 12 (0000h-03FFh) for the PIC16F505 are

physically implemented. Refer to Figure 4-2.

Accessing a location above this boundary will cause a

wrap-around within the first 1K x 12 space. The

effective Reset vector is at 0000h (see Figure 4-2).

Location 03FFh contains the internal oscillator

calibration value. This value should never be

overwritten.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F505

4.3 Data Memory Organization

Data memory is composed of registers or bytes of

RAM. T herefore, da t a me mory for a d ev ic e is speci fie d

by its register file. The register file is divided into two

functional groups: Special Function Registers (SFR)

and General Purpose Registers (GPR).

The Special Function Registers include the TMR0

are used to control the I/O port configuration and

prescaler options.

The General Purpose Registers are used for data and

control information u nd er c om mand of the ins tru cti ons .

For the PIC12F508/509, the register file is composed of

7 Special Function Registers, 9 General Purpose

Registers and 16 or 32 General Purpose Registers

accessed by banking (see Figure 4-3 and Figure 4-4).

For the PIC16F505, the register file is composed of 8

Special Function Registers, 8 General Purpose

Registers and 64 General Purpose Registers accessed

by banking (Figure 4-5).

4.3.1 GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.9 “Indirect Data Addressing:

INDF and FSR Registers”.

CALL, RETLW

PC<11:0>

S tack Level 1

S tack Level 2

User Memory

Space

0000h

7FFh

01FFh

0200h

Reset Vector(1)

Note 1: Address 0000h becomes the

effective Reset vector. Location

03FFh contains the MOVLW XX

internal oscillator calibration value.

1024 Words 03FFh

0400h

On-chip Program

Memory

PIC12F508/509/16F505

FIGURE 4-3: PIC12F50 8 REGI STE R

FILE MAP FIGURE 4-4: PIC12F509 REGISTER

FILE MAP

FIGURE 4-5: PIC16F505 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and

FSR Registers”.

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

0Fh 10h

Bank 0 Bank 1

3Fh

30h

20h

2Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map

back to

addresses

in Bank 0.

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and F SR

Registers”.

FSR<5> 0 1

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

PORTB

0Fh 10h

Bank 0 Bank 1

3Fh

30h

20h

2Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map back to

addresses in Bank 0.

Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers” .

FSR<6:5> 00 01

Bank 3

7Fh

70h

60h

6Fh

General

Purpose

Registers

Bank 2

5Fh

50h

40h

4Fh

General

Purpose

Registers

08h

PORTC

PIC12F508/509/16F505

4.3.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used b y the CPU and periph eral functio ns to cont rol the

operation of the device (Table 4-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset(2) Page #

00h INDF Uses Contents of FSR to Address Data Memory (not a physical

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35

02h(1) PCL Low-order 8 bits of PC 1111 1111 27

03h STATUS GPWUF —PA0

(5) TO PD ZDCC0-01 1xxx(3) 22

04h FSR Indirect Data Memory Address Pointer 111x xxxx 28

04h(4) FSR Indirect Data Memory Address Pointer 110x xxxx 28

05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —1111 111- 26

06h GPIO —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31

N/A TRISGPIO —— I/O Contro l Regis te r --11 1111 31

N/A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 24

Legend: – = unimplemente d, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter”

for an explanation of how to access these bits.

2: Other (non Power-up ) Reset s inc lude extern al Reset thro ugh M CLR, Watchdog Timer and wake-up on pin

change R eset.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

4: PIC12F509 only.

5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.

PIC12F508/509/16F505

TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset(2) Page #

00h INDF Uses Contents of FSR to Address Data Memory (not a physical

01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 35

02h(1) PCL Low-order 8 bits of PC 1111 1111 27

03h STATUS RBWUF —PA0TO PD ZDCC0-01 1xxx 22

04h FSR Indirect Data Memory Address Pointer 100x xxxx 28

05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —1111 111- 26

06h PORTB —— RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 31

07h PORTC —— RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 31

N/A TRISB —— I/O Control Register --11 1111 31

N/A TRISC —— I/O Control Register --11 1111 31

N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 25

Legend: – = unimplemented, read as ‘0’, x = unknow n, u = unchanged, q = value depends on condition.

Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

2: Other (non Power-up) Resets include external reset through MCLR, Watchd og Timer and w ake- up on p in

change R eset.

PIC12F508/509/16F505

4.4 STATUS Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For exam ple, CLRF STATUS, will clear the upper thre e

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and

MOVWF instructions be used to alter the STATUS regis-

ter. These instruct ion s do not af f ec t the Z, D C or C bits

from the STATUS register. For other instructi ons wh ich

do af fect S t atu s bit s, see Sect ion 8.0 “Inst ruction Set

Summary”.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF —PA0TOPD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GPWUF: GP IO Reset bit

1 = Reset due to wake-up from Sleep on pin change

0 = After power-up or other Reset

bit 6 Reserved: Do not use

bit 5 PA0: Program Page Preselect bits(1)

1 = Page 1 (200h-3FFh)

0 = Page 0 (000h-1FFh)

Each page is 512 bytes.

Using the PA 0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is

not recommended, since this may affect upward compatibility with future products.

bit 4 TO: Time- Out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)

ADDWF:

1 = A carry from the 4th low-order bit of the result occurred

0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur

0 = A borrow from the 4th low-order bit of the result occurred

bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF: SUBWF: RRF or RLF:

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively

0 = A carry did not occur 0 = A borrow occurred

Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.

PIC12F508/509/16F505

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

RBWUF —PA0TOPD ZDCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBWUF: PORTB Reset bit

1 = Reset due to wake-up from Sleep on pin change

0 = After power-up or other Reset

bit 6 Reserved: Do not use

bit 5 PA0: Program Page Preselect bits

1 = Page 1 (200h-3FFh)

0 = Page 0 (000h-1FFh)

Each page is 512 bytes.

Using the PA0 bit as a general purp ose read/write bit in de vi ces whic h do no t use it for program page

preselect is not recommended, since this may affect upward compatibility with future products.

bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)

ADDWF:

1 = A carry from the 4th low-order bit of the result occurred

0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow fro m the 4th low-order bit of the result did not occu r

0 = A borrow from the 4th low-order bit of the result occurred

bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF:SUBWF:RRF or RLF:

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively

0 = A carry did not occu r 0 = A borrow occurred

PIC12F508/509/16F505

4.5 OPTION Register

The OPTION register is a 8-bit wide, write-only register ,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION regis-

ter. A Reset sets the OPTION<7:0> bits.

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin (i.e., note that TRIS overrides

Option control of GPPU/RBPU and

GPWU/RBWU).

Note: If the T0CS bit is set to ‘1’, it will override

the TRIS functi on on the T0CK I pin .

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

bit 6 GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0 = Transition on internal instruction cycle cloc k, FOSC/4

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on the T0CKI pin

0 = Increment on low-to-high transition on the T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

PIC12F508/509/16F505

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)

1 = Disabled

0 = Enabled

bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)

1 = Disabled

0 = Enabled

bit 5 T0CS: Timer0 clock So urce Select bit

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0 = Transition on internal instruction cycle cloc k, FOSC/4

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on the T0CKI pin

0 = Increment on low-to-high transition on the T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

PIC12F508/509/16F505

4.6 OSCCAL Register

The Oscill ator Calibration (OSCCAL) register is used to

calibrate the internal precision 4 MHz oscillator. It

cont ains seven bit s for calibra tio n.

After you move in the calibration constant, do not

change the value. See Section 7.2.5 “Internal 4 MHz

RC Oscillator”.

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 =Maximum frequency

•

0000001

0000000 =Center frequency

1111111

•

1000000 =Minimum frequency

bit 0 Unimplemented: Read as ‘0’

PIC12F508/509/16F505

4.7 Program Counter

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The Program Counter

(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS

(Figure 4-6).

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not co me fro m the in stru ct ion word, but is always

cleared (Figure 4-6).

Instr uctions where the PCL is th e destinatio n, or modif y

PCL instructions, include MOVWF PC, ADDWF PC and

BSF PC,5.

FIGURE 4-6: LOADING OF PC

BRANCH INSTRUCTIONS

4.7.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC

addresses the last location in the last page (i.e., the

oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 00h and

begin executing user code.

The STATUS register page preselect bits are cleared

upon a Reset, which means that pag e 0 is pre-selected.

Therefore, upon a Reset, a GOTO instruction will

automat ically cause t he program to jump to page 0 until

the value of the page bits is altered.

4.8 Stack

The PIC12F508/509/16F505 devices have a 2-deep,

12-bit wide hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of Stack

1 into Stack 2 and then PUSH the current PC value,

incremented by one, into S tack Level 1. If more than two

sequential CALLs are executed , only the most rec ent two

return ad dresses are s tored.

A RETLW instruction will POP the contents of Stack

Level 1 into the PC and then copy Stack Level 2

content s into S ta ck Level 1. If more tha n two seq uential

RETLWs are executed, the stack will be filled with the

address previously stored in Stack Level 2. Note that

the W register will be loaded with the literal value

specif ied in the inst ruction. This i s particu larly useful f or

the implementation of data look-up tables within the

program memory.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program memory page ( 512 words long).

PA0

Status

PC 87 0

PCL

910

Inst ruction Word

GOTO Ins truction

CALL or Modify PCL Instruction

PA0

Status

PC 87 0

PCL

910

Inst ruction Word

Reset to ‘0’

Note 1: There are no Status bits to indicate stack

overflows or stack underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occ ur from th e e xecution of the CALL

and RETLW instructions.

PIC12F508/509/16F505

4.9 Indire ct Data Addressi ng: INDF

and FSR Registers

The INDF register is not a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a pointer). This is indirect addressing.

4.9.1 INDIRECT ADDR ES SING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

The FSR is a 5-bit wide register . It is used in conjunctio n

with the INDF register to indirectly address the data

memory area.

The FSR<4:0> bits are used to select data memory

addresses 00 h to 1Fh.

FIGURE 4-7: DIRECT/INDIRECT ADDRESSING (PIC12F508/509)

PIC12F508 – Does not use banking. FSR <7:5> are

unimplemented and read as ‘1’s.

PIC12F509 – Use s FSR<5>. Selec ts betwee n bank 0

and bank 1. FSR<7:6> are unimplemented, read as

‘1’.

PIC16F505 – Us es FSR<6:5>. S elects fro m bank 0 to

bank 3. FSR<7> is unimplemented, read as ‘1’.

MOVLW 0x10 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF

;register

INCF FSR,F ;inc pointer

BTFSC FSR,4 ;all done?

GOTO NEXT ;NO, clear next

CONTINUE

: ;YES, continue

Note 1: For register map detail, see Section 4. 3 “Data Memory Organization”.

2: PIC12F509.

Bank Location Select

Location Select

Bank Select

Indirect Addressing

Direct Addressing

Data

Memory(1) 0Fh

10h

Bank 0 Bank 1(2)

6(FSR)

00 01

00h

1Fh 3Fh

(opcode) 04

(FSR)

Addresses

map back to

addresses

in Bank 0.

PIC12F508/509/16F505

FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505)

Note 1: For register map detail, see Section 4.3 “Data Memory Organization” .

Direct Addressing

(FSR)

6 5 4 (opcode) 0

Bank Select Location Select

00 01 10 11

00h

0Fh

10h

Data

Memory(1)

1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Indirect Addressing

6 5 4 (FSR) 0

Bank Location Select

Addresses

map back to

addresses

in Bank 0.

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

5.0 I/O PORT

As with any other register, the I/O register(s) can be

written and read und er program contro l. Howeve r , rea d

instructions (e.g., MOVF PORTB,W) always r ead t he I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

5.1 PORTB/GPIO

PORTB/GPIO is an 8-bit I/O register. Only the low-

order 6 bi ts are used (RB/GP<5:0>). Bits 7 and 6 are

unimplemented and read as ‘0’s. Pl ease note th at RB3/

GP3 is an input only pin. The Configuration Word can

set se veral I/O’ s t o a lte rnate functio ns. When actin g a s

alternate functions, the pins will read as ‘0’ during a port

read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4

can be configured with weak pull-ups and also for

wake-up on change. The wake-up on change and weak

pull-up functions are not pin selectable. If RB3/GP3/

MCLR is configured as MCLR, weak pull-up is always

on and wake-up on change for this pin is not enabled.

5.2 PORTC (PIC16F505 Only)

PORT C is an 8-bit I/O register . Only the low-order 6 bit s

are used (RC<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s.

5.3 TRIS Registers

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A ‘1’ from a TRIS regi ster bit pu ts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are RB3/GP3, which is input only and the T0CKI

pin, which may be controlled by the OPTION register.

See R egister 4-3 and Reg ister 4-4.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-2. All port pins, except RB3/GP3 which is

input only, may be use d for both inp ut and outp ut oper-

ations. For input operations, these ports are non-latch-

ing. Any input must be present until read by an input

instruction (e.g., MOVF PORTB, W). The outputs are

latched and remain unchanged until the output latch is

rewritten. To use a port pin as output, the correspond-

ing dir ectio n contro l bit in TR IS must be cleared (= 0).

For use as an input, the corresponding TRIS bit must

be set. Any I/O pin (except RB3/GP3) can be

programmed individually as input or output.

FIGURE 5-1: PIC12F508/509/16F505

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note: On the PIC12 F508/509, I /O POR TB i s ref-

erenced as GPIO. On the PIC16F505, I/O

PORTB is referenced as PORTB.

Note: On power-up, TOCKI functionality is

enabled in the OPTION register and must

be disabled to allow RC5 to be used as

general purpose I/O.

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enab led and driven hig h,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

Reg

Latch

Reset

Note 1: See Table 3-3 for buffer type.

VSS

VDD

(1)

PIC12F508/509/16F505

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

All Other

Resets

N/A TRISGPIO(1) —— I/O Control Register --11 1111 --11 1111

N/A TRISB(2) —— I /O Control Register --11 1111 --11 1111

N/A TRISC(2) —— I/O Control Register --11 1111 --11 1111

N/A OPTION(1) GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A OPTION(2) RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111

03h STATUS(1) GPWUF —PAO TO PD ZDC C0-01 1xxx q00q quuu(3)

03h STATUS(2) RBWUF —PAO TO PD ZDC C0-01 1xxx q00q quuu(3)

06h GPIO(1) —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

06h PORTB(2) —— RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu

07h PORTC(2) —— RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu

Legend: Shaded cells are not used by Port registers, read as ‘0’. – = unimplemented, read as ‘0’, x = unknown, u = unchanged,

q = depends on condition.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

PIC12F508/509/16F505

5.5 I/O Programming Considerations

5.5.1 BIDIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for

exampl e, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pin s are use d as in put/outputs . For

exampl e, a BSF operation on bit 5 of PO RTB/ GPI O will

cause a ll eig ht b it s of PO R TB/GPIO to be rea d in to th e

CPU, bit 5 t o be set a nd th e P ORTB /G P IO val u e to be

written to the output latches. If another bit of PORTB/

GPIO i s used as a bidire ctiona l I /O pin (s ay b it 0) an d it

is define d as an input at this time, the input signa l pres-

ent on the pin itself would be read into the CPU and

rewritte n to the dat a latch o f this p articular pin, o verwrit-

ing the p reviou s content. As long as t he pin st ays in th e

Input mode, no problem occurs. However, if bit 0 is

switched into Output mode later on, the content of the

data l atch may now be unknown.

Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired OR”, “wired

AND”). The res ulting hig h output curre nts may dam age

the chip.

EXAMPLE 5-1: RE AD-MODIFY -WRITE

INSTRUCTIONS ON AN

I/O PORT(e.g., PIC16F505)

5.5.2 SUCCESSIVE OPERATIONS ON

I/O PORTS

The actual write to an I/O port happens at the end of an

instr uction cycl e, wher eas f or read ing , the d ata mu st be

valid at the beginning of the instruction cycle (Figure 5-2).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

caus es that fi le to be read into the CPU. Other wis e, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

access ing thi s I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC16F505 Shown)

;Initial PORTB Settings

;PORTB<5:3> Inputs

;PORTB<2:0> Outputs

;

; PORTB latch PORTB pins

; ---------- ----------

BCF PORTB, 5 ;--01 -ppp --11 pppp

BCF PORTB, 4 ;--10 -ppp --11 pppp

MOVLW 007h;

TRIS PORTB ;--10 -ppp --11 pppp

;

Note 1: The user may have expected the pin values to

be ‘--00 pppp’. The 2nd BCF caused RB5 to

be latched as the pin value (High).

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetched

RB<5:0>

MOVWF PORTB NOP

Port pin

sampled here

NOPMOVF PORTB, W

Instruction

Executed MOVWF PORTB

(Write to PORTB) NOPMOVF PORTB,W

This example shows a write to PORTB

followed by a read from PORTB.

Data s e tu p ti me = (0.2 5 TCY – TPD)

where: TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

(Read PORTB)

Port pi n

written here

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

6.0 TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increm ent ev ery ins tru cti on cycle (wi t ho ut p res ca ler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-2 and Figure 6-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge. Restric-

tions on the external clock input are discussed in detail

in Section6.1 “Using Timer0 with an External

Clock”.

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (OPTION<3>). Clearing the PSA bit

will assign the prescale r to T imer0 . The pres caler is not

readable or writable. Whe n the prescaler is assi gned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 6.2 “Prescaler” detai ls

the operation of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks TM R0 Re g

PSOUT

(2 TCY delay)

PSOUT

Data Bus

PSA(1)

PS2, PS1, PS0(1)

Sync

T0SE

(GP2/RC5)/T0CKI

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetch

Timer0

PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6

T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC + 5

(Program

Counter)

PIC12F508/509/16F505

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

All Other

Resets

01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu

N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A TRISGPIO(1), (3) —— I/O Control Register --11 1111 --11 1111

N/A TRISC(2), (3) —— RC5 RC4 RC3 RC2 RC1 RC0 --11 1111 --11 1111

Legend: Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u = unchanged.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

3: The TRIS of the T0CKI pin is overridden when T0CS = 1.

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetch

Timer0

PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6

T0 T0 + 1 NT0 NT0 + 1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC + 5

(Program

Counter)

PIC12F508/509/16F505

6.1 Using Timer0 with an External

Clock

When an external cl ock input i s used for T ime r0, it must

meet ce r tain r equ ir e me nts. The ex t er na l cl oc k req u ire -

ment is due to internal phase clock (TOSC) synchroni-

zation. Also, there is a del ay in the actu al incre mentin g

of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK

SYNCHRONIZATION

When no pr escal er is used, t he ex ternal clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI with the internal phase clocks is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

pres caler, so t hat the prescal er output is symme trical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, i t is nec essa ry for T0CKI to h ave a perio d of

at least 4 TOSC (and a small RC delay of 4 Tt0H)

divided by the prescaler value. The only requirement

on T0C KI hig h and lo w time is that th ey do no t viol ate

the min imum pu lse width requi rement of Tt0 H. Re fer to

param ete rs 40, 41 a nd 42 in the e lec tric al s pec if ication

of the desired device.

6.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

External Clock/ Pres caler

Output After Sampling (3)

Prescaler Output (2)

(1)

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

PIC12F508/509/16F505

6.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 7.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 regis ter (e.g., CLRF 1, MOVWF 1,

BSF 1, x, etc.) wil l clear the prescaler. When assi gned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writ able. On a Re set, the prescal er contains all ‘0’s.

6.2.1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software control

(i.e., it can be changed “on-the-fly” during program

execution). To avoid an unintended device Reset, the

following instruction sequence (Example 6-1) must be

executed when changing the prescaler assignment

from Timer0 to the WDT.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0 → WDT)

To change the prescaler from the WDT to the Timer0

module , use the se quence sh own in Exa mple 6-2. This

sequenc e mus t be us ed ev en if th e WDT is disab led. A

CLRWDT instruction should be executed before

switching the prescaler.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT → TIMER0)

Note: The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 & Prescaler

MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)

OPTION ;are required only if

;desired

CLRWDT ;PS<2:0> are 000 or 001

MOVLW ‘00xx1xxx’b ;Set Postscaler to

OPTION ;desired WDT rate

CLRWDT ;Clear WDT and

;prescaler

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

OPTION

PIC12F508/509/16F505

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2)

TCY (= FOSC/4)

Sync

Cycles TMR0 Reg

8-bit Prescaler

8-to-1 MUX

MUX

Watchdog

Timer

PSA

WDT

Time-out

PS<2:0>

PSA

WDT Enable bit

Data Bus

PSA

T0CS

T0SE

(GP2/RC5)/T0CKI

Note 1: T0CS, T0SE, PSA, PS <2:0> are bits in the OPTIO N register.

2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509.

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

7.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other

process ors are speci al circui ts th at deal with t he need s

of real-time applications. The PIC12F508/509/16F505

microcontrollers have a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power-

saving operating modes and offer code protection.

These features are:

• Oscillator Selection

• Reset:

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from Sleep on Pin Change

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

•Clock Out

The PIC12F508/509/16F505 devices have a W atchdog

T imer , wh ich can be shut of f only throug h Confi guration

bit WDTE. It runs off of its own RC oscillator for added

reliabil ity . If using HS (PIC16F505), XT or LP selectable

oscillator options, there is always an 18 ms (nominal)

delay provided by the Device Reset Timer (DRT),

intended to keep the chip in Reset until the crystal

oscillator is stable. If using INTRC or EXTRC, there is

an 18 ms delay only on VDD power -up. With th is time r

on-chip, most applications need no external Reset

circuitry.

The Sleep mode is des igned to of fer a ve ry low-c urrent

Power-Down m ode . T he user can wake-up from Slee p

through a change on in put pins or through a Watchdog

Timer time-out. Several oscillator options are also

made available to allow the part to fit the application,

including an internal 4 MHz oscillator. The EXTRC

oscillator option saves system cost while the LP crystal

option saves power. A set of Configuration bits are

used to select various options.

7.1 Configuration Bits

The PIC12F508/509/16F505 Configuration Words

consist of 12 bits. Configuration bits can be

programmed to select various device configurations.

Three bits are for the selection of the oscillator type;

(two bits on the PIC12F508/509), one bit is the

Watchdog Timer enable bit, one bit is the MCLR enable

bit and one bit is for code protection (Register 7-1,

PIC12F508/509/16F505

— — — — — — — MCLRE CP WDTE FOSC1 FOSC0

bit 11 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown

bit 11-5 Unimplemented: Read as ‘0’

bit 4 MCLRE: GP3/MCLR Pin Function Select bit

1 = GP3/MCLR pin function is MCLR

0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD

bit 3 CP: Code Protection bit

1 = Code protection off

0 = Code protection on

bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0 FOSC<1:0>: Oscillator Selection bits

11 = EXTRC = external RC oscillator

10 = INTRC = internal RC oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to

access the Configuration Word. The Configuration Word is not user addressable during device operation.

PIC12F508/509/16F505

— — — — — — MCLRE CP WDTE FOSC2 FOSC1 FOSC0

bit 11 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 11-6 Unimplemented: Re ad as ‘0’

bit 5 MCLRE: RB3/MCLR Pin Function Sele ct bit

1 = RB3/MCLR pin function is MCLR

0 = RB3/MCLR pin function is digital input, MCLR internally tied to VDD

bit 4 CP: Code Protection bit

1 = Code protection off

0 = Code protection on

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0 FOSC<1:0>: Oscillator Selection bits

111 = External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin

110 = External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

101 = Internal RC osci lla tor/CL KOUT functi on on RB4/O SC2/CL KOUT pin

100 = Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

011 = EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

010 = HS oscillator

001 = XT oscillator

000 = LP oscillator

Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to access

the Configuration Word. The Configuration Word is no t user add ressable during de vic e operation.

PIC12F508/509/16F505

7.2 Oscillator Configurations

7.2.1 OSCILLATOR TYPES

The PIC12F508/509/16F505 devices can be operated

in up to six different oscillator modes. The user can

program up to three Configuration bits (FOSC<1:0>

[PIC12F 508/509], FOSC<2 :0> [PIC16F 505]). To select

one of these modes:

• LP: Low-Power Crystal

• XT: Crystal/Resonator

• HS: High-Spe ed Cr ystal/Resona tor

(PIC16F5 05 onl y)

• INTRC: Intern al 4 MHz Oscillator

• EXTRC: Extern al Resi st or/C apacitor

• EC: External High-Speed Clock Input

(PIC16F5 05 onl y)

7.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In HS (PIC16F505), XT or LP modes, a crystal or

ceramic resonator is connected to the (GP5/RB5)/

OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins

to establish oscillation (Figure 7-1). The PIC12F508/

509/16F505 oscillator designs require the use of a

parallel cut crystal. Use of a series cut crystal may give

a frequency out of the crystal manufacturers

specifications. When in HS (PIC16F505), XT or LP

modes, the device can have an external clock source

drive the (GP5/RB5)/OSC1/CLKIN pin (Figure 7-2).

When the part is used in this fashion, the output drive

levels on the OSC2 pin are very weak. This pin should

be lef t open and unload ed. Also, wh en using th is mode,

the external clock should observe the frequency limits

for the clock mode chosen (HS, XT or LP).

FIGURE 7-1: CRYSTAL OPERATION

(OR CERAMIC

RESONATOR)

(HS, XT OR LP OSC

CONFIGURATION)

FIGURE 7-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC

CONFIGURATION)

T ABLE 7-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS –

PIC12F508/509/16F505(1)

Note 1: This device has been designed to per-

form to the parameters of its data sheet.

It has been tested to an electrical

specification designed to determine its

conformance with these parameters.

Due to process differences in the

manufacture of this device, this device

may have different performance charac-

teristics than its earlier version. These

differences may cause this device to

perform differently in your application

than the earlier version of this device.

2: The user should verify that the device

oscillator starts and performs as

expect ed. Adjusting the loading capacitor

values and/or the Oscillator mode may

be required.

Osc

Type Resonator

Freq. Cap. Range

C1 Cap. Range

XT 4.0 MHz 30 pF 30 pF

HS(2) 16 MHz 10-47 pF 10-47 pF

Note 1: These values are for design guidance

only. Since each reso nat or has it s own

characteristics, the user should consult

the resonator manufacturer for

appropriate values of external

components.

2: PIC16F505 only.

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for A T

strip cut crystals.

3: RF approx. value = 10 MΩ.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) Sleep

To internal

logic

RS(2)

PIC12F508/509

PIC16F505

Clock from

ext. system OSC1

OSC2 PIC16F505

Open

PIC12F508/509

PIC12F508/509/16F505

TABLE 7-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR –

PIC12F508/509/16F505(2)

7.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator wi ll provide good perfor-

mance with TTL gates. Two types of crystal oscillator

circuits can be used: one with parallel resonance, or

one with series resonance.

Figure 7-3 shows impl ementati on of a paralle l resonant

oscillator circuit. The circuit is designed to use the fun-

dament al frequen cy of the c rystal. The 74AS04 in verter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ters bias the 74AS04 in the linear region. This circuit

could be used for external oscillator designs.

FIGURE 7-3: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 7-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 7-4: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

7.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additi onal cost savin gs . The RC osc il lat or

frequenc y is a fun ction of the sup ply volta ge, the resis-

tor (REXT) and capacitor (C EXT) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit-to-unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C

components used.

Figure 7-5 shows how the R/C combination is

connected to the PIC12F508/509/16F505 devices. For

REXT values bel ow 3.0 kΩ, the oscilla tor operat ion may

become unstable, or stop completely. For very high

REXT values (e.g., 1 MΩ), the oscillator becomes

sensitive to noise, humidity and leakage. Thus, we

recommend keeping REXT between 5.0 kΩ and

100 kΩ.

Osc

Type Resonator

Freq. Cap. Range

C1 Cap. Range

LP 32 kHz(1) 15 pF 15 pF

XT 200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

HS(3) 20 MHz 15-47 pF 15-47 pF

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

2: These values are for design guidance

only. Rs may be required to av oid over-

driv ing crys tal s with lo w drive leve l spe cifi-

cation. Since each crystal has its own

characteristics, the user should consult

the crystal manufacturer for appropriate

values of external components.

3: PIC16F5 05 onl y.

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04

PIC16F505

CLKIN

To Other

Devices

PIC12F508

PIC12F509

330

74AS04 74AS04

PIC16F505

CLKIN

To Other

Devices

XTAL

330

74AS04

0.1 mF PIC12F508

PIC12F509

PIC12F508/509/16F505

Although the oscillator will operate with no external

capacitor (CEXT = 0pF), we recommend using values

above 2 0 pF for nois e a nd st a bility reas ons . W ith no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

Sect io n 10.0 “E lec tri cal Cha ract eri sti cs” shows RC

frequency variation from part-to-part due to normal

process variation. The variation is larger for larger val-

ues of R (since leakage current varia tion will affect RC

frequenc y more for la rge R) and for sm aller val ues of C

(since variation of input capacitance will affect RC

frequency more).

Also, see the Electrical Specifications section for

variation of oscillator frequency due to VDD for given

REXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and VDD

values.

FIGURE 7-5: EXTERNAL RC

OSCILLATOR MODE

7.2.5 INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator provides a fixed 4 MHz

(nominal) system clock at VDD = 5V and 25°C, (see

Section 10.0 “Electrical Characteristics” for

information on variation over voltage and temperature).

In addit ion , a ca librati on in structi on is progra mmed into

the last address of memory, which contains the

calibration value for the internal RC oscillator. This

location is always uncode protected, regardless of the

code-protect settings. This value is programmed as a

MOVLW XX instruc tion where XX is the calibration value,

and is placed at the Reset vector. This will load the W

PC will then roll over to the users program at address

0x000. The user t hen has th e option of writing the value

to the OSCCAL Register (05h) or ignoring it.

OSCCAL, when writte n to with the calibration va lue, will

“trim” the internal oscillator to remove process variation

from the oscil la tor frequ enc y.

For the PIC12F508/509/16F505 devices, only bits

<7:1> of OSCCAL are implemented. Bits CAL6-CAL0

are used for calibration. Adjusting CAL6-CAL0 from

‘0000000’ to ‘1111111’ changes the cloc k speed. Se e

VDD

REXT

CEXT

VSS

OSC1 Internal

clock

PIC16F505

FOSC/4 OSC2/CLKOUT

PIC12F508

PIC12F509

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

Note: The 0 bit of OSCCAL is unimplemented

and should be written as ‘0’ when

modifying OSCCAL for compatibility with

future devices.

PIC12F508/509/16F505

7.3 Reset

The device differentiates between various kinds of

Reset:

• Power-on Reset (POR)

•MCLR

Reset during normal operation

•MCLR

Reset during Sleep

• WDT time-out Reset during normal operation

• WDT time-out Reset during Sleep

• Wake-up from Sleep on pin change

Some registers are not reset in any way, they are

unknown on POR and unchanged in any other Reset.

Most other registers are reset to “Reset state” on

Power-on Reset (POR), MCLR, WDT or Wake-up on

pin change Reset during normal operation. They are

not affected by a WDT Reset during Sleep or MCLR

Reset during Sleep, since these Resets are viewed as

resumpt ion of n orm al ope ration. The ex ce pti ons to thi s

are TO, PD and RBWUF/GPWUF bits. They are set or

cleared differently in different Reset situations. These

bits are used in software to determine the nature of

Reset. See Table 7-4 for a full description of Reset

state s of all regi ste r s.

TABLE 7-3: RESET CONDITIONS FOR REGISTERS – PIC12F508/509

Wake-up On Pin Change

W—qqqq qqqu(1) qqqq qqqu(1)

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu(2), (3)

FSR(4) 04h 110x xxxx 11uu uuuu

FSR(5) 04h 111x xxxx 111u uuuu

OSCCAL 05h 1111 111- uuuu uuu-

GPIO 06h --xx xxxx --uu uuuu

OPTION — 1111 1111 1111 1111

TRIS — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depen ds on con di tion .

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of

memory.

2: See Table 7-5 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

4: PIC12F5 09 onl y.

5: PIC12F5 08 onl y.

PIC12F508/509/16F505

TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505

TABLE 7-5: RESET CONDITION FOR SPECIAL REGISTERS

Wake-up On Pin Change

W—qqqq qqqu(1) qqqq qqqu(1)

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu(2), (3)

FSR 04h 100x xxxx 1uuu uuuu

OSCCAL 05h 1111 111- uuuu uuu-

PORTB 06h --xx xxxx --uu uuuu

PORTC 07h --xx xxxx --uu uuuu

OPTION — 1111 1111 1111 1111

TRISB — --11 1111 --11 1111

TRISC — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depen ds on con di tion .

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instructi on at t op of

memory.

2: See Table 7-5 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

STATUS Addr: 03h PCL Addr: 02h

Power-on Reset 0001 1xxx 1111 1111

MCLR Reset during normal operation 000u uuuu 1111 1111

MCLR Reset during Sleep 0001 0uuu 1111 1111

WDT Reset during Sleep 0000 0uuu 1111 1111

WDT Reset normal operation 0000 uuuu 1111 1111

Wake-up from Sleep on pin change 1001 0uuu 1111 1111

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.

PIC12F508/509/16F505

7.3.1 MCLR ENABLE

This C onf igu rati on b it, w h en u npro gra mm ed (l ef t in the

‘1’ state), enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD and the pin is assigned to be an input only. See

Figure 7-6.

FIGURE 7-6: MCLR SELECT

7.4 Power-on Reset (POR)

The PIC12F508/509/16F505 devices incorporate an

on-chip Power-on Reset (POR) circuitry, which

provides an internal chip Reset for most power-up

situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the internal POR,

prog ram the (GP3/R B3)/MC LR/VPP pin as MCLR and

tie through a resistor to VDD, or program the pin as

(GP3/RB3). An internal weak pull-up resistor is

implemented using a transistor (refer to Table 10-2 for

the pull -up resistor ran ges). This wil l e lim in ate external

RC components usually needed to create a Power-on

Reset. A maxi mum rise tim e for VDD is specified. See

Section 10.0 “Electrical Characteristics” for details.

When the devices start normal operation (exit the

Reset condition), device operating parameters

(voltage, frequency, temperature,...) must be met to

ensure operation. If these conditions are not met, the

devices must be held in Reset until the operating

parameters are met.

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 7-7.

The Power-on Reset circuit and the Device Reset

Timer (see Section 7.5 “Devic e R e set T im er (DRT)”)

circuit are closely related. On power-up, the Reset latch

is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, whi ch is typic ally 18 ms, it will reset th e

Reset latch and thus end the on-chip Reset signal.

A power-up example where MCLR is held low is shown

in Figu re 7-8. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT msec after MCLR goe s high .

In Figure 7-9, the on-chip Power-on Reset feature is

being use d (MCLR a nd V DD are tied together or the pin

is programmed to be (GP3/RB3). The VDD is stable

before the s tart-up timer ti mes out and there is no prob-

lem in getting a proper Reset. However, Figure 7-10

depict s a pro ble m situ ation whe re VDD rises too slowly .

The time be tw ee n when the DRT sen ses tha t MCLR is

high and when MCLR and VDD actually reach their full

value, is too long. In this situation, when the start-up

timer times out, VDD has not reached the VDD (min)

value a nd the chip ma y not functio n c orre ctly. For such

situations, we recommend that external RC circuits be

used to achieve longer POR delay times (Figure 7-9).

For additional information, refer to Application Notes

AN522 “Power-Up Considerations” (DS00522) and

AN607 “Power-up Trouble Shooting” (DS00607).

(GP3/RB3)/MCLR/VPP

MCLRE Internal MCLR

GPWU/RBWU

Note: When the devices start normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the device must be held in Reset until the

operating conditions are met.

PIC12F508/509/16F505

FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

VDD

(GP3/RB3)/MCLR/VPP

Power-up

Detect POR (Pow e r- on Reset)

WDT Reset CHIP Reset

MCLRE

Wake-up on pin Change Reset

Start-up Timer

(10 μs or 18 ms)

WDT Time-out

Pin Change

Sleep

MCLR Reset

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

TDRT

VDD

MCLR

Inter n al POR

DRT Time-out

Internal Reset

TDRT

PIC12F508/509/16F505

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

TDRT

Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

PIC12F508/509/16F505

7.5 Device Reset Timer (DRT)

On the PIC1 2F5 08 /509 /16 F505 device s, the DR T run s

any time the device is powered up. DRT runs from

Reset and varies based on oscillator selection and

Reset type (see Table 7-6).

The DRT operates on an internal RC oscillator. The

process or is kept in Reset as long as the DR T is active.

The DR T del ay allo w s VDD to rise above VDD min. and

for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resona-

tors require a certain time after power-up to establish a

stable osci llation. The on-chip DRT kee ps the devices in

a Reset condition for approximately 18 ms after MCLR

has reached a logic high (VIH MCLR) level.

Programming (GP3/RB3)/MCLR/VPP as MCLR and

using an external RC network connected to the MCLR

input is not required in most cases. This allows savings

in cost-sensitive and/or sp ace res tricted applications , as

well as allowing the use of the (GP3/RB3)/MCLR/VPP

pin as a general purpose input.

The Device Reset Time delays will vary from chip-to-

chip due to VDD, temperature and process variation.

See AC parameters for details.

The D RT w ill also be tri ggered upon a Watchdog T im er

time-out from Sleep. This is particularly important for

applications using the WDT to wake from Sleep mode

automatically.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 7.9.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

7.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the (GP5/RB5)/OSC1/CLKIN

pin and the internal 4 MHz oscillator. This means that

the WDT will run even if the main processor clock has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation or Sleep, a WDT

Reset or wake-up Reset, generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by

programming the configuration WDTE as a ‘0’ (see

Section 7.1 “Configuration Bits”). Refer to the

PIC12F508/509/16F505 Programming Specifications

to determine how to access the Configuration Word.

TABLE 7-6: DRT (DEVICE RESET TIMER

PERIOD)

7.6.1 WDT PERIOD

The WDT has a nomin al time-out p eriod of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, a time-out period

of a nominal 2.3 seconds can be realized. These

periods vary with temperature, VDD and part-to-part

process va riat ions ( see DC spec s).

Under worst c ase condi tions ( VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time- out occurs.

7.6.2 WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

post scaler , if as signed to the WDT, and prevent s it from

timing out and generating a device Reset.

The SLEEP instruction resets the WDT and the post-

scaler, if assig ned to the WDT. This g ives the ma ximum

Sleep time before a WDT wake-up Reset.

Oscillator

Configuration POR Reset Subsequent

Resets

INTOSC, EXTRC 18 ms (typical) 10 μs (typical)

HS(1), XT, LP 18 ms (typical) 18 ms (typical)

EC(1) 18 ms (typical) 10 μs (typic al)

Note 1: PIC16F505 only.

PIC12F508/509/16F505

FIGURE 7-11 : WATCHDOG TIMER BLOCK DIAGRAM

TABLE 7-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

All Other

Resets

N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

(Figure 6-5)

Postscaler

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

WDT Time-out

Watchdog

Time

From Timer0 Clock Source

WDT Enable

Configuration

Bit

PSA

Postscaler

8-to-1 MUX PS<2:0>

(Figure 6-4)

To Timer0

PSA

MUX

PIC12F508/509/16F505

7.7 Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO, PD, GPWUF/RBWU F)

The TO, PD and (GPWUF/RBWUF) bits in the

STATUS register can be tested to determine if a Reset

condition has been caused by a Power-up condition, a

MCLR or Watchdog Timer (WDT) Reset.

TABLE 7-8: TO/PD/(GPWUF/RBWUF)

STATUS AFTER RESET

7.8 Reset on Brown-out

A brown-out is a condition where device power (VDD)

dips below it s minimum value, but no t to zero, an d then

recovers. The device should be reset in the event of a

brown-out.

To reset PIC12F508/509/16F505 devices when a

brown-out occurs, external brown-out protection

circuits may be built, as shown in Figure 7-12 and

Figure 7-13.

FIGURE 7-12: BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 7-13: BROWN-OUT

PROTECTION CIRCUIT 2

FIGURE 7-14: BROWN-OUT

PROTECTION CIRCUIT 3

GPWUF/

RBWUF TO PD Reset Caused By

000WDT w ake-up from S leep

00uWDT time-out (not from

Sleep)

010MCLR wake-up from Sleep

011Power-up

0uuMCLR not dur ing Slee p

110Wake-up from Sleep on pin

change

Legend: u = unchanged

Note 1: The TO, PD and GPWUF/RBWUF bits

maintain their status (u) until a Reset

occurs. A low-pulse on the MCLR input

does not change the TO, PD and

GPWUF/RBWUF Status bits.

Note 1: This circuit will activate Reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

2: Pin must be confirmed as MCLR.

33k

10k

40k(1)

VDD

MCLR(2)

PIC16F505

VDD

Q1 PIC12F508

PIC12F509

Note 1: This brown-out circuit is less expensive,

although less accurate. Transistor Q1 turns

off when VDD is below a certain level such

that:

2: Pin must be confirmed as MCLR.

VDD • R1

R1 + R2 = 0.7V

R2 40k(1)

VDD

MCLR(2)

PIC16F505

VDD

PIC12F508

PIC12F509

Note: This brown-out protection circuit employs

Microchip Technology’s MCP809 micro-

controller supervisor. There are 7 different

trip point selections to accommodate 5V to

3V systems.

MCLR

PIC16F505

VDD

VSS

RST

MCP809

VDD

Bypass

Capacitor

PIC12F508

PIC12F509

PIC12F508/509/16F505

7.9 Power-down Mode (Sleep)

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

7.9.1 SLEEP

The Power-Down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low or high-impedance).

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

(GP3/RB3)/MCLR/VPP pin must be at a logic high

level if MCLR is enabled.

7.9.2 WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of

the following events:

1. An external Reset input on (GP3/RB3)/MCLR/

VPP pin, when configured as MCLR.

2. A Watchdog Timer time-out Reset (if WDT was

enabled).

3. A change on input pin GP0/RB0, GP1/RB1,

GP3/RB3 or RB4 when wake-up on change is

enabled.

These events cause a device Reset. The TO, PD and

GPWUF/RBWUF bits can be used to determine the

cause of de vi ce Rese t . T he TO bit is cleared if a WDT

time-out occurred (and caused wake-up). The PD bit,

which is set on power-up, is cleared when SLEEP is

invoked. The GPWUF/RBWUF bit indicates a change

in state while in Sleep at pins GP0/RB0, GP1/RB1,

GP3/RB3 or RB4 (since the last file or bit operation on

GP/RB port).

The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.

7.10 Program Verification/Code

Protection

If the cod e protection bit has not been programmed, the

on-chip program memory can be read out for

verification pur poses.

The first 64 locations and the last location (OSCCAL)

can be read, regardless of the code protection bit

setting.

The last m emory locatio n can be read regardl ess of the

code protection bit setting on the PIC12F508/509/

16F505 devices.

7.11 ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writ ab le duri ng Progra m/ Verify.

Use on ly the lower 4 bits of the ID locati ons and al ways

program the upper 8 bits as ‘0’s.

7.12 In-Circuit Serial Programming™

The PIC12F508/509/16F505 microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data,

and three other lines for power, ground and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware, or

a custom firmware, to be progra mmed.

The devices are placed into a Program/Verify mode by

holding the GP1/RB1 and GP0/RB0 pins low while

raising the MCLR (VPP) pin from VIL to VIHH (see

programming specification). GP1/RB1 becomes the

programming clock and GP0/RB0 becomes the

programming data. Both GP1/RB1 and GP0/RB0 are

Schmitt Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the

device. D ependi ng on the co mmand , 14 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read. For complete

details of serial programming, please refer to the

PIC12F508/509/16F505 Programming Specifications.

A typical In-Circuit Serial Programming connection is

shown in Figure 7-15.

Note: A Reset generated by a WDT time-out

does not drive the MCLR pin low.

Note: Caution: Right before entering Sleep,

read the input pins. When in Sleep, wake-

up occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs an d the pins are not rea d before re-

entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

PIC12F508/509/16F505

FIGURE 7-15: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16F505

VDD

VSS

MCLR/VPP

GP1/RB1

GP0/RB0

+5V

VPP

CLK

Data I/O

VDD

PIC12F508

PIC12F509

PIC12F508/509/16F505

8.0 INSTRUCTION SE T SUMMARY

The PIC16 instruction set is highly orthogonal and is

comprised of three basic categories.

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

Each PIC16 instruction is a 12-bit word divided into an

opcode, which specifies the instruction type, and one

or mor e operands which further specify the operation

of the instruction. The formats for each of the catego-

ries is presented in Figure 8-1, while the various

opcode fields are summarized in Table 8-1.

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator whic h sel ec t s the number of the bit af fected

by the op erat ion, while ‘ f’ represe nt s the num be r of th e

file in which the bit is located.

For literal and control operations, ‘k’ represents an

8 or 9-bit constant or literal value.

TABLE 8-1: OPCODE FIELD

DESCRIPTIONS

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

inst ruction ex ecution ti me is 1 μs. If a conditi onal test i s

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 μs.

Figure 8-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

0xhhh

wher e ‘h’ sign ifies a hexadecimal digi t.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

f Register f ile address (0x00 to 0x7F)

W Worki ng register (accu m ulator)

b Bit address within an 8-bit file register

k Literal fie l d, constant data or label

x Don’t care location (= 0 or 1)

The assembler will generate code with x = 0. It is

the rec ommended form of use for comp atibility with

all Microchip so ftware tools.

d Destination select;

d = 0 (store result in W)

d = 1 (store result in file register ‘f’)

Default is d = 1

label Label name

TOS Top-of-Stack

PC Program Counter

WDT Watchdog Timer counter

TO T i me-out bit

PD Power-do w n bit

des t D e s ti n a ti o n, eith er th e W re gi s t er or th e s p ec i f i ed

[ ] Options

( ) Content s

→Assigned to

< > Register bi t field

∈In the se t of

italics User defined term (font is courier)

Byte-oriented file register operations

11 6 5 4 0

d = 0 for destination W

OP C O D E d f (FILE #)

d = 1 for destination f

f = 5-bit file register address

Bit-oriented file register ope rations

11 8 7 5 4 0

OP C O D E b (B IT # ) f (F IL E #)

b = 3-bit bit address

f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations – GOTO instruction

11 9 8 0

OPCODE k (li te r a l )

k = 9-bit immediate value

PIC12F508/509/16F505

TABLE 8-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles 1 2-Bit Opcode Status

Affected Notes

MSb LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

—

f, d

—

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Incr eme nt f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

Exclusive OR W with f

1(2)

0001

0000

0010

0000

0010

0011

0001

0010

0000

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

10df

11df

00df

001f

0000

01df

00df

10df

ffff

0000

ffff

0000

ffff

C, DC, Z

None

C, DC, Z

None

1, 2, 4

2, 4

1, 4

2, 4

1, 2, 4

2, 4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1(2)

0100

0101

0110

0111

bbbf

ffff

None

2, 4

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

XORLW

—

AND literal with W

Call Subro uti ne

Clear Watchdog Timer

Unconditional branch

Inclusive OR literal with W

Move literal to W

Load OPTION register

Return, place literal in W

Go into Standby mode

Load TRIS register

Exclusive OR literal to W

1110

1001

0000

101k

1101

1100

0000

1000

0000

1111

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0100

kkkk

0010

kkkk

0011

0fff

kkkk

None

TO, PD

None

TO, PD

None

Note 1: The 9th bit of the program coun ter wil l be fo rce d to a ‘0’ by any ins truc tio n tha t wr ites to th e PC exc ept for

GOTO. See Section 4.7 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the valu e use d will be that

value pr ese nt on the pins t hemse lves. For e xamp le, if the dat a la tch is ‘1’ for a pin c onfigu red a s input and

is driven low by an external device, the data will be written back with a ‘0’.

3: The instru ction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

PIC12F508/509/16F505

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Description: Add the contents of the W register

and register ‘f’. If ‘d’ is’0’, the result

is stored in the W register. If ‘d’ is

‘1’, the resu lt is sto r ed bac k in

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W).AND. (k) → (W)

Status Affected: Z

Description: The contents of the W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Description: The contents of the W register are

AND’ed with register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W register .

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

St at us Af fe cte d: Non e

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

St at us Af fe cte d: Non e

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

St at us Af fe cte d: Non e

Descr iption : If bit ‘b’ in regis ter ‘f’ is ‘ 0’, then the

next instruction is skipped.

If bit ‘b’ is ‘0’, the n the nex t ins truc -

tion fetched during the current

instruction execution is discarded,

and a NOP is executed instead,

making this a two-cycle instruction.

PIC12F508/509/16F505

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Desc ription : If bit ‘b ’ in reg ister ‘f’ is ‘1’, the n the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instru c-

tion fetched during the current

instruction execution, is discarded

and a NOP is executed instead,

making this a two-cycle instruction.

CALL Subroutine Call

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 255

Operation: (PC) + 1→ Top-of-Stack;

k → PC<7:0>;

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: None

Description: Subroutine call. First, return

address (PC + 1) is PUSHed onto

the stack. The eight-bit immediate

address is loaded into PC

bits <7:0>. The upper bits

PC<10:9> are loaded from

STATUS<6:5>, PC<8> is cleared.

CALL is a two-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 31

Operation: 00h → (f);

1 → Z

Status Affected: Z

Description: The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W);

1 → Z

St at us Af fe cte d: Z

Description: The W register is cleared. Zero bit

(Z) is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

St at us Af fe cte d: TO, PD

Description: The CLRWDT instruction resets the

WDT. It also reset s the prescal er , if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

St at us Af fe cte d: Z

Description: The co ntents of register ‘f’ ar e

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, th e result is stored back in

PIC12F508/509/16F505

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) – 1 → (dest)

Status Affected: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

stored back in register ‘f’.

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) – 1 → d; skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

decr emente d. If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOP is executed

instead making it a two-cycle

instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 511

Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

Description: GOTO is an unconditi onal branch .

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTO is a two-

cycle inst ruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) + 1 → (dest)

St at us Af fe cte d: Z

Description: The co ntents of register ‘f’ ar e

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) + 1 → (dest), skip if result = 0

St at us Af fe cte d: Non e

Description: The co ntents of register ‘f’ ar e

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOP is

executed instead making it a

two-cycle instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. (k) → (W)

St at us Af fe cte d: Z

Descripti on: The content s of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

PIC12F508/509/16F505

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W).OR. (f) → (dest)

Status Affected: Z

Description: Inclusive OR the W regist er with

placed in the W re gister. If ‘d’ is ‘1’,

the result is placed back in registe r

‘f’.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Description: The contents of register ‘f’ are

moved to destina tion ‘d’. If ‘d ’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the destination is file

test of a file register, since status

flag Z is affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Description: The eight-bit literal ‘k’ is loaded

into the W register. The “don’t

cares” wi ll assem bl ed as ‘0’s.

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 31

Operation: (W) → (f)

St at us Af fe cte d: Non e

Description: Move data from the W register to

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operati on: N o ope rati on

St at us Af fe cte d: Non e

Descr ipti on : No operati on.

OPTION Load OPTION Register

Syntax: [ label ] OPTION

Operands: None

Operation: (W) → OPTION

St at us Af fe cte d: Non e

Description: The content of the W register is

loaded into the OPTION register.

PIC12F508/509/16F505

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Description: The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cycle instructi on.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag . If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is stored back in

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag . If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

Cregister ‘f’

SLEEP Enter SLEEP Mode

Syntax: [label ]SLEEP

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler;

1 → TO;

0 → PD

St at us Af fe cte d: TO, PD, RBWUF

Description: Time-out S tat us bit (TO) is set. The

Power-dow n St atu s bit (PD) is

cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into Sleep

mode with the oscillator stopped.

See Section 7.9 “Power-down

Mode (Sleep)” on Sleep for more

details.

SUBWF Subtract W from f

Syntax: [label ] SUBWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) – (W) → (dest)

St at us Af fe cte d: C, DC, Z

Descr iption : Subtract (2’ s comp lemen t method )

the W reg ister fr om regist er ‘f’. If ‘d’

is ‘0’, the result is stored in the W

stored back in regi ster ‘f’.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

St at us Af fe cte d: Non e

Description: The upper and lower nibbles of

‘0’, the result is placed in W

placed in regi ste r ‘f’.

PIC12F508/509/16F505

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operand s: f = 6

Operation: (W) → TRIS register f

Status Affected: None

Description: TRIS register ‘f’ (f = 6 or 7) is

loaded wi th the co nten t s of the W

XORLW Exclusive OR literal with W

Syntax: [label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Description: The contents of the W register are

XOR’ed w ith the eight- bit lite ral ‘k ’.

The result is placed in the W

XORWF Exclu sive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

St at us Af fe cte d: Z

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in regi ster ‘f’.

PIC12F508/509/16F505

9.0 DEVELOPMENT SU PPO R T

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mm ers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

9.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separa tel y)

- In-Circuit Deb ugger (so ld separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e he lp

• Integration of select third party tools, such a s

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your sour ce fil es (either assemb ly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- Source fil es (a ssembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC12F508/509/16F505

9.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly co de

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

9.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 and PIC24 families of microcon-

trollers and the dsPIC30 and dsPIC33 family of digital

signal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compil ers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

9.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and ex traction

9.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linke d with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

9.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by

simulating the PIC MCUs and dsPIC® DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC12F508/509/16F505

9.7 MPLAB ICE 2000

High-Performance

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

9.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated D evelopment Environment (IDE),

included with each kit.

The MPLAB REAL ICE pro be is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or w ith the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB ID E, new devic es w ill be supported,

and new features will be added, suc h as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages ov er competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables .

9.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step -

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

9.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is incl uded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions an d

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

PIC12F508/509/16F505

9.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated D evelopm ent Envir onment software m akes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

9.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families

of Flash memory microcontrollers. The PICkit 2 Starter

Kit includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler , and is desig ned to hel p get up to s peed

quickly using PIC® microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

9.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards includ e prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and

demonstration software for analog filter design,

KEELOQ® security ICs, CAN, IrDA®, PowerSmart

battery management, SEEVAL® evaluation system,

Sigma-Delta ADC, flow rate sensing, plus many more.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

PIC12F508/509/16F505

10.0 ELECTRIC AL CHARACTERISTICS

Absolute Maximum Ratings(†)

Ambient temperature under bias..........................................................................................................-40°C to +125°C

Storage temperature............................................................................................................................-65°C to +150°C

Vo lt a ge on VDD with respect to VSS ...............................................................................................................0 to +6.5V

Vo lt a ge on MCLR with respect to VSS..........................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation(1) ..................................................................................................................................800 mW

Max. current out of VSS pin................................ ....................... ...................... ....................... ...................... ......200 mA

Max. current into VDD pin...................................................................................................................................150 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)...........................................................................................................±20 mA

Max. output current sunk by any I/O pin ..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Power dissip ation is calcula ted as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – V OH) x IOH} + ∑(VOL x IOL)

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

thos e in di c at e d in t he o pe rat i o n l is tin g s o f t his s pec if i ca t io n is not i mp li e d. Ex po su r e to m ax im um r at i ng c ond it i on s

for extended periods may affect device reliability.

PIC12F508/509/16F505

FIGURE 10-1: PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

FIGURE 10-2: MAXIMUM OSCILLATOR FREQUENCY TABLE

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

(PIC16F505 only)

0200 kHz 4 MHz 20 MHz

Frequency (MHz)

HS(1)

EXTRC

Oscillator Mode

EC(1)

INTOSC

Note 1: For PIC16F505 only.

PIC12F508/509/16F505

10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial)

DC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

Param

No. Sym. Characteristic Min. Typ(1) Max. Units Conditions

D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1

D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sl eep mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset — Vss — V See Section 7.4 "Power-on

Reset (POR)" for details

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 7.4 "Power-on

Reset (POR)" for details

D010 IDD Supply Current(3,4) —

—175

0.625 275

1.1 μA

mA FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

—

—500

1.5 650

2.2 μA

mA FOSC = 10 MHz, VDD = 3.0V

FOSC = 20 MHz, VDD = 5.0V

(PIC16F505 only)

—

—11

38 20

54 μA

μAFOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020 IPD Power-down Current (5) —

—0.1

0.35 1.2

2.4 μA

μAVDD = 2.0V

VDD = 5.0V

D022 IWDT WDT Current(5) —

—1.0

7.0 3.0

16.0 μA

μAVDD = 2.0V

VDD = 5.0V

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, osci llator type, bu s rate, internal code exec ution pattern and temperature also have an im pact on

the current consumption.

4: The test conditions for all IDD measurements in active operation mode are:

OSC1 = extern al squar e wave , from rail-t o-rail; al l I/O pins tri-s tat ed, pu lled to VSS, T0CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For st andby curren t meas ureme nts , the c ondit ions a re the s ame as IDD , exc ept tha t the de vice is in Sleep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

PIC12F508/509/16F505

10.2 DC Characteristics: PIC12F508/509/16F505 (Extended)

DC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (extended)

Param

No. Sym. Characteristic Min. Typ(1) Max. Units Conditions

D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1

D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset —Vss— VSee Section 7.4 "Power-on

Reset (POR)" for details

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 7.4 "Power-on

Reset (POR)" for details

D010 IDD Supply Current(3,4) —

—175

0.625 275

1.1 μA

mA FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

—

—500

1.5 650

2.2 μA

mA FOSC = 10 MHz, VDD = 3.0V

FOSC = 20 MHz, VDD = 5.0V

(PIC16F515 only)

—

—11

38 26

110 μA

μAFOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020 IPD Power-down Current (5) —

—0.1

0.35 9.0

15.0 μA

μAVDD = 2.0V

VDD = 5.0V

D022 IWDT WDT Current(5) —

—1.0

7.0 18

22 μA

μAVDD = 2.0V

VDD = 5.0V

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading , oscil lator type, bus rate , inte rnal code execu tio n p at tern and temperatu r e also have an imp ac t on

the current consumption.

4: The test conditions for all IDD measurements in active operation mode are:

OSC1 = exter nal square wav e, from ra il-to-rai l; all I/O pins tri -st ated, pu lled to VSS, T0 CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For st andby curre nt me asurem ent s, th e con dition s are the sa me as ID D, exce pt tha t th e dev ice is in Sle ep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

PIC12F508/509/16F505

TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating temperature -40°C ≤ TA ≤ +85° C (industrial)

-40°C ≤ TA ≤ +125 °C (exte nd ed)

Operating voltage VDD range as described in DC specification

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

VIL Input Low Voltage

I/O ports:

D030 with TTL buffer Vss — 0.8V V For all 4.5 ≤ VDD ≤ 5.5V

D030A Vss — 0.15 VDD V Otherwise

D031 with Schmitt Trigger buffer Vss — 0.15 VDD V

D032 MCLR, T0CKI Vss — 0.15 VDD V

D033 OSC1 (in EXTRC) Vss — 0.15 VDD V(Note1)

D033 OSC1 (in HS) Vss — 0.3 VDD V(Note1)

D033 OSC1 (in XT and LP) Vss — 0.3 V (Note1)

VIH Input High V oltage

I/O ports: —

D040 with TTL buffer 2.0 — VDD V4.5 ≤ VDD ≤ 5.5V

D040A 0.25 VDD

+ 0.8 —V

DD V Otherwise

D041 with Schmitt Trigger buffer 0.85 VDD —VDD V For entire VDD range

D042 MCLR, T0CKI 0.85 VDD —VDD V

D043 OSC1 (in EXTRC) 0.85 VDD —VDD V(Note1)

D043 OSC1 (in HS) 0.7 VDD —VDD V(Note1)

D043 OSC1 (in XT and LP) 1.6 — VDD V

D070 IPUR GPIO/PORTB weak pull-up

current(4) 50 250 400 μAVDD = 5V, VPIN = VSS

IIL Inp u t Leakage Current(2), (3)

D060 I/O ports — — ± 1 μAVss ≤ VPIN ≤ VDD, Pin at high-impedance

D061 GP3/RB3/MCLRI(5) —± 0.7± 5 μAVss ≤ VPIN ≤ VDD

D063 OSC1 — — ± 5 μAVss ≤ VPIN ≤ VDD, XT, HS and LP oscillator

configuration

Output Low Voltage

D080 I/O ports/CLKOUT — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C

D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C

D083 OSC2 — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C

D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C

Output High Voltage

D090 I/O ports/CLKOUT(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C

D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C

D092 OSC2 VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C

D092A VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C

Capacitive Loading Specs on

Output Pins

D100 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is

used to drive OSC1.

D101 All I/O pins and OSC2 — — 50 pF

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/

16F505 be driven with external clock in RC mode.

2: The leak age curr ent on t he M CLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating

conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming ou t of the pin.

4: The specification applies to all weak pull-up devices, including the weak pull-up on GP3/MCLR. The current listed will be the same

whether GP3/MCLR is configured as GP3 with a weak pull-up or enabled as MCLR.

5: This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit

is higher than the standard I/O logic.

PIC12F508/509/16F505

TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505

VDD (Volts) Temperature (°C) Min. Typ. Max.

GP0(RBO)/GP1(RB1)

2.0 –40 73K 105K 186K

25 73K 113K 187K

85 82K 123K 190K

125 86K 132k 190K

5.5 –40 15K 21K 33K

25 15K 22K 34K

85 19K 26k 35K

125 23K 29K 35K

GP3(RB3)

2.0 –40 63K 81K 96K

25 77K 93K 116K

85 82K 96k 116K

125 86K 100K 119K

5.5 –40 16K 20k 22K

25 16K 21K 23K

85 24K 25k 28K

125 26K 27K 29K

* These parameters are characterized but not tested.

PIC12F508/509/16F505

10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505

The timing parameter symbols have been created following one of the following formats:

FIGURE 10-3: LOAD CONDITIONS – PIC12F508/509/16F505

FIGURE 10-4: EXTERNAL CLOCK TIMING – PIC12F508/509/16F505

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase subscripts (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc Oscillator

cy Cycle time os OSC1

drt Device Reset Timer t0 T0CKI

io I/O po rt wdt Watchdog Timer

Uppercase letters and their mean ings:

FFall PPeriod

HHigh RRise

I Invalid (high-impedance) V Valid

L Low Z High-impedance

VSS

Legend:

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock

is used to drive OSC1

OSC1

Q4 Q1 Q2 Q3 Q4 Q1

133

PIC12F508/509/16F505

TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505

AC CHARACTERISTICS

Standard Opera ting Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1 "Power-

on Reset (POR)"

Param

No. Sym. Characteristic Min. Typ(1) Max. Units Conditions

1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT Oscillat or mode

DC — 20 MHz EC, HS Oscillator mode

(PIC16F505 only)

DC — 200 kHz LP Oscillator mode

Oscillator Frequency(2) — — 4 MHz EXTRC Oscillator mode

0.1 — 4 MHz XT Oscillator mode

4 — 20 MHz HS Oscillator mode (PI C16F505

only)

— — 200 kHz LP Oscillator mode

OSC External CLKIN Period(2) 250 — — ns XT Oscillator mode

50 — — ns EC, HS Oscillator mode

(PIC16F505 only)

5——μs LP Oscillator mode

Oscillator Period(2) 250 — — ns EXTRC Oscillator mode

250 — 10,000 ns XT Oscillator mode

50 — 250 ns HS Oscillator mod e (PIC16F5 05

only)

5——μs LP Oscillator mode

CY Instructi on Cy c le Time 200 4/FOSC —ns

3 TosL,

TosH Clock in (OSC1) Low or High

Time 50* — — ns XT Oscillator

2* — — μs LP Oscillator

10* — — ns EC, HS Oscillator

(PIC16F505 only)

4TosR,

TosF Clock in (OSC1) Rise or Fall

Time — — 25* ns XT Oscillator

— — 50* ns LP Oscillator

— — 15* ns EC, HS Oscillator

(PIC16F505 only)

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless ot herwise stated. These parameters are for

design guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. When an external clock

input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC12F508/509/16F505

TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505

FIGURE 10-5: I/O TIMING – PIC12F508/509/16F505

AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

Param

No. Sym. Characteristic Freq

Tolerance Min. Typ† Max. Units Conditions

F10 FOSC Internal Calibrated

INTOSC Frequency(1) ± 1% 3.96 4.00 4.04 MHz VDD = 3.5V, TA = 25°C

± 2% 3.92 4.00 4.08 MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

± 5% 3.80 4.00 4.20 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

* These parameters are characterized but not tested.

† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: To ensure these o scil lat or frequency to lera nc es , VDD a nd V SS must be capacitively decoupled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

OSC1

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

PIC12F508/509/16F505

TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505

FIGURE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –

PIC12F508/509/16F505

CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is des cri be d in Section 10.1 "Power-on Reset (POR)"

Param

No. Sym. Characteristic Min. Typ(1) Max. Units

17 TOSH2IOVOSC1↑ (Q1 cycle) to Port Out Valid(2), (3) ——100*ns

18 TOSH2IOIOSC1↑ (Q 2 cy cl e) to Port Input Inval id (I/O in hol d ti me ) (2) 50 — — ns

19 TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time) 20 — — ns

20 TIOR Port Output Rise Time(3) —1025**ns

21 TIOF Port Output Fall Time(3) —1025**ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested.

Note 1: Data i n the Typical (“Typ”) column i s at 5V, 25°C unless o therwis e st ated. Th ese p aram eters a re for de sign

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 10-3 for loading conditions.

VDD

MCLR

Internal

POR

DRT

Timeout(2)

Internal

Reset

Watchdog

Timer

Reset

I/O pin(1)

32 32

Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.

2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes.

PIC12F508/509/16F505

TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505

AC CHARACTERISTICS Standard Opera ting Cond ition s (unle ss oth erw ise s peci fied)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Param

No. Sym. Characteristic Min. Typ(1) Max. Units Conditions

30 TMCLMCLR Pulse Width (low) 2000* — — ns VDD = 5.0V

31 TWDT W atchdog Timer Time-out Period

(no prescaler) 9*

9* 18*

18* 30*

40* ms

ms VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

32 TDRT Device Reset Timer Period(2) 9*

9* 18*

18* 30*

40* ms

ms VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

34 TIOZ I/O High-impedance from MCLR

low — — 2000* ns

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless ot herwise stated. These parameters are for

design guidance only and are not tested.

PIC12F508/509/16F505

FIGURE 10-7: TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505

TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operati ng Temperatu re -40°C ≤ TA ≤ +85°C (industria l)

-40°C ≤ TA ≤ +125°C (extended)

Operati ng Voltage VDD range is described in

Section 10.1 "Power-on Reset (POR)"

Param

No. Sym. Characteristic Min. Typ(1) Max. Units Conditions

40 Tt0H T0CKI High Pulse

Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse

Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

Note 1: Data in the Ty pica l (“Typ”) co lu mn is at 5V, 25°C unles s otherwis e st ated. Th ese p ara meters ar e for desi gn

guidance only and are not tested.

T0CKI

40 41

PIC12F508/509/16F505

11.0 DC AND AC CHARA CTERISTICS GRAPHS AND CH ARTS

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean -

3σ) respectively, where s is a standard deviation, over each temperature range.

FIGURE 11-1: IDD vs. VDD at FOSC = 4 MHz

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for info rmational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

200

400

600

800

1,000

1,200

1,400

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

4 MHz

Maximum

Typical

PIC12F508/509/16F505

FIGURE 11 -2: IDD VS. FOSC Over VDD (HS MODE, PIC16F505 only)

FIGURE 11-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

3.00

2.50

2.00

1.50

1.00

0.50

0.00 510 15 20 25

Max. 5V

Typical 5V

Max. 3V

Typical 3V

Fosc (MHz )

(mA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -Case T emp) + 3σ

(-40°C to 125°C)

Typical

(Sleep Mode all Peripherals Disabled)

0.0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -Cas e Temp) + 3σ

(-40°C to 125°C)

PIC12F508/509/16F505

FIGURE 11-4: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

FIGURE 11-5 : TYPICAL WDT IPD vs. VDD

Maximum

(Sleep Mode all Peripherals Disabled)

Max. 125°C

Max. 85°C

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

18.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -Case T emp) + 3σ

(-40°C to 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-Cas e Temp) + 3σ

(-40°C to 125°C)

PIC12F508/509/16F505

FIGURE 11-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

FIGURE 11-7: WDT TIME-OUT or DEVICE RESET TIMER vs. VDD OVER TEMPERATURE (NO

WDT PRESCALER)(1)

Maximum

Max. 125°C

Max. 85°C

0.0

5.0

10.0

15.0

20.0

25.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-Ca se Temp ) + 3σ

(-40°C to 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (ms)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -Cas e Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typical. 25°C

Min. -40°C

Note 1: Device Rese t Timer (DRT) values are for case of Reset of power-up. Table 7-6 shows DRT values for

the case of other types of Reset events.

PIC12F508/509/16F505

FIGURE 11-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

FIGURE 11-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

(VDD = 3V, -40×C TO 125×C)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

IOL (mA)

VOL (V)

Max. 85°C

Max. 125°C

Typical 25°C

Min. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

IOL (mA)

VOL (V)

Typical: Statistical Mean @25×C

Maximum: Meas + 3 (-40×C to 125×C)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

Max. 85°C

Typ. 25°C

Min. -40°C

Max. 125°C

PIC12F508/509/16F505

FIGURE 11 -10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

FIGURE 11 -11: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)

VOH (V)

Typ. 25°C

Max. -40°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

(, )

3.0

3.5

4.0

4.5

5.0

5.5

-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)

VOH (V)

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

PIC12F508/509/16F505

FIGURE 11-12: TTL INPUT THRESHOLD VIN vs. VDD

FIGURE 11-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD

(TTL Input, -40×C TO 125×C)

0.5

0.7

0.9

1.1

1.3

1.5

1.7

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN (V)

Typ. 25°C

Max. -40°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-Ca se Temp ) + 3σ

(-40°C to 125°C)

(ST Input, -40×C TO 125×C)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN (V)

VIH Max. 125°C

VIH Min. -40°C

VIL Min. 125°C

VIL Max. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

PIC12F508/509/16F505

FIGURE 11-14: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (25°C)

FIGURE 11-15: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (-40°C)

-5

-4

-3

-2

-1

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

Change from Calibration (%)

22.5 33.544.555.5

-1

-2

-3

-4

-5

-4

-3

-2

-1

2 2.5 3 3.5 4 4.5 5 5.5

Change from Calibration (%)

VDD (V)

22.5 33.544.555.5

-1

-2

-3

-4

-5

PIC12F508/509/16F505

FIGURE 11-16: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (85°C)

FIGURE 11-17: TYPICAL INTOSC FREQUENCY CHANGE vs VDD (125°C

-5

-4

-3

-2

-1

2 2.5 3 3.5 4 4.5 5 5.5

Change fr om Calibration (%)

VDD (V)

-1

-2

-3

-4

-5 22.5 33.544.555.5

-5

-4

-3

-2

-1

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

Change fr om Calibration (%)

22.5 33.544.555.5

-1

-2

-3

-4

-5

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

8-Lead SOIC (3.90 mm)

XXXXXXXX

XXXXYYWW

NNN

Example

12F509-I

/SN 0610

017

8-Lead MSOP

XXXXXX

YWWNNN

Example

12F509

0610017

X X X

Y W W

N N

8-Lead 2x3 DFN*

B E Q

6 1 0

1 7

Example

XXXXXNNN

8-Lead PDIP

XXXXXXXX

YYWW /P 017

Example

12F508-I

0610

Note: In the event the full M icroch ip p art numb er canno t be mark ed on one line, it w ill

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*Standard PIC® dev ice marki ng co nsist s of Mic rochip par t numbe r, yea r code, week code, and traceabi lity

code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

Legend: XX...X Customer-spec ifi c inform atio n

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

PIC12F508/509/16F505

12.1 Package Marking Informat ion (Continued)

XXXXXXXXXXXXXX

YYWWNNN

14-Lead PDIP (300 mil)

14-Lead SOIC (3.90 mm)

XXXXXXXXXXX

YYWWNNN

Example

PIC16F505-E

0610017

XXXXXXXXXXX

14-Lead TSSOP (4.4 mm)

XXXXXXXX

YYWW

Example

16F505-I

0610

NNN 017

/SL0125

Example

PIC16F505

0610017

0215

-I/P

TABLE 12-1: 8-LEAD 2X3 DFN (MC) TOP MARKING

Part Number Marking

PIC12F508 (T) - I/MC BN0

PIC12F508-E/MC BP0

PIC12F509 (T) - I/MC BQ0

PIC12F509-E/MC BR0

XXXXXXX

16-Lead QF N

XXXXXXX

YYWWNNN

16F505

Example

-I/MG

0610017

PIC12F508/509/16F505





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 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

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1,21!'!&$& "!**&"&&!

 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - -

##4>#& .   <

: 9&  -< -? 

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

123

  * ,<1

PIC12F508/509/16F505

 ! ""#$%& !'



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 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = 

##44!!   = =

&#%%+  = 

: >#& . ?1,

##4>#& . -1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = 

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

12 3

  * ,1

PIC12F508/509/16F505

 ! ""#$%& !'

&&255***''54

PIC12F508/509/16F505

(" !)*( ( !



  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  = = 

##44!!   < 

&#%%   = 

: >#& . 1,

##4>#& . -1,

: 9&  -1,

3&9& 9  ? <

3&& 9 .3

3& IB = <B

9#4!!  < = -

9#>#& )  = 

NOTE 1

A2 c

L1 L

  * ,1

PIC12F508/509/16F505

+$)*(',--%&+



  !"#$%&"' ()"&'"!&)&#*&&&#

 4' '$!#&)!&#!

- 4!!*!"&#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  <  

&#%%    

,&&4!! - .3

: 9&  1,

: >#& . -1,

.$!##9&  - = 

.$!##>#& .  = 

,&&>#& )   -

,&&9& 9 -  

,&&&.$!## C  = =

NOTE 1

EXPOSED PAD

NOTE 1

A3 A1

NOTE 2

BOTTOM VIEW

TOP VIEW

  * ,-,

PIC12F508/509/16F505

./



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

 '!#&.0

1,21!'!&$& "!**&"&&!

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - -

##4>#& .   <

: 9&  -  

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

123

A1 b1

  * ,1

PIC12F508/509/16F505

./ ! ""#$%& !'



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  1,

: 8&  = = 

##44!!   = =

&#%%+   = 

: >#& . ?1,

##4>#& . -1,

: 9&  <?1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = 

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

123

hα

  * ,?1

PIC12F508/509/16F505

./01 1") ! 0/%/0 !



  !"#$%&"' ()"&'"!&)&#*&&&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  ?1,

: 8&  = = 

##44!!  <  

&#%%   = 

: >#& . ?1,

##4>#& . -  

##49&    

3&9& 9  ? 

3&& 9 .3

3& B = <B

9#4!!   = 

9#>#& )  = -

NOTE 1

L1 L

  * ,<1

PIC12F508/509/16F505

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC12F508/509/16F505

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC12F508/509/16F505

APPENDIX A: REVISION HISTORY

Revision A (April 2004)

Original data sheet for PIC12F508/509/16F505

devices

Revision B (June 2005)

Update packages

Revision C (03/2007)

Revis ed Ta ble 3-2 Leg end; Revis ed Table 3-3 RB3 an d

Legend; Revised Table 10-4 F10; Replaced Package

Drawings (Rev. AN); Added DFN package; Replaced

Development Support Section; Revised Product ID

System.

Revision D (12/2007)

Revis ed Ti tle; Operating Current; Table 1-1 added DFN

and revised note; Revised Section 3.0, last paragraph;

Revis ed Fig ure 4-4; R evi se d Table 4 -2 (FSR); Revised

Revised Table 7-3, Note 2; Revised Table 7-4 (FSR)

and Note 2; Deleted Section 7.3.1: External Clock In

and Figure 7-6; Revised new Section 7.3.1; Replaced

TBD with new data in Tables 10-4 and 10-5; Revised

Tables 10-1 (Industrial), 10-2 (Extended), and Tables

10-1 (Indust rial, E xtende d) and 10 -2 (Pul l-up Re sistor

Ranges), 10-3, 10-4 and 10-6; Revised Figure 10-1,

Figure 10-2; Section 11.0, Added Char data; Revised

Package Marking Information; Revised Product ID

System.

Revision E (08/2009)

Added PIC 16F505 16 -Pin diag ram (QFN ); Added No te

after subsection 5.2 PORTC; Updated Note 4 and

deleted Note 5, Table 10-1; Deleted Param. No. D061

(Table 10-1) and Param. No. D061A becomes D061;

Added QFN Package Information; Revised Product

Identification System; Added Figures 11-14, 11-15, 11-

16, 11-7 to Char Dat a sectio n; Other min or corrections ;

Removed Preli m inary status.

PIC12F508/509/16F505

NOTES:

PIC12F508/509/16F505

INDEX

ALU.....................................................................................11

Assembler

MPASM Assembler.....................................................66

Block Diagram

On-Chip Rese t Circuit....... ......... .............. ............... ....50

Timer0.........................................................................35

TMR0/WDT Prescaler.................................................39

Watchdog Timer............................... .... .... .. ......... .. .... ..53

Brown-Out Protection Circuit ..............................................54

C Compilers

MPLAB C18..... ..................... ............................ ..........66

MPLAB C30..... ..................... ............................ ..........66

Carry ...................................................................................11

Clocking Scheme................................................................16

Code Protection ............................................................41, 55

Configuration Bits................................................................41

Configuration Word.............................................................43

Customer Change Notification Service.............................107

Custome r Notification Ser vice.............. .............. ...............107

Customer Support.............................................................107

DC and AC Characteristics........................................... .... ..81

Development Support .........................................................65

Digit Carry...........................................................................11

Errata ....................................................................................6

Family of Devices

PIC12F508/509/PIC16F505..........................................7

FSR.....................................................................................28

I/O Int e rfacing ................. .............. ..................... .................31

I/O Ports................................ ........................... ...................31

I/O Prog ramming Conside rations....... ..................... ............33

ID Locations..................................................................41, 55

INDF....................................................................................28

Indirect Data Addressing.....................................................28

Instruction Cycle .................................................................16

Instruction Flow/Pipelining..................................................16

Instruction Set Summary.....................................................58

Inter net Address.................... ........................... .................107

Loading of PC ....................... .. .. .. .. ....... .. .. .. .... .. .. .. ....... .. .. .. ..27

Memory Organization..........................................................17

Data Memor y ...................... ..................... ...................18

Program Memory (PIC12F508/509)............................17

Program Memo ry (P IC16F505)...................................18

Microc h i p In ternet Web Sit e................... ..................... ......107

MPLAB ASM30 Assembler, Linker, Librarian .....................66

MPLAB ICD 2 In-Circuit Debugger ................ .... ......... ...... ..67

MPLAB ICE 2000 High-Perform ance Universal

In-Circuit Emulator......................................................67

MPLAB Integrated Development Environment Software. ... 65

MPL AB PM3 D e v i ce Prog ra mmer .. ...... .. ...... ..... ...... ...... .. ... 6 7

MPLAB REA L IC E In -Circuit Em u l a tor System.................. 67

MPL IN K Ob j e ct Linker/ MPLIB O b j ec t Li b ra ri a n... .. ...... .. ..... 66

Option Register ................................................................... 24

OSC selection..................................................................... 41

OSCCAL Register............................................................... 26

Oscillator Configurat ions. ........... ........ ........ ........... .......... .... 44

Oscillator Types

HS............................................................................... 44

LP............................................................................... 44

RC .............................................................................. 44

XT............................................................................... 44

PIC12F508/509/16F505 Device Varieties ............................ 9

PICSTART Plus Development Programmer....................... 68

PORDevic e R e set Timer ( D R T) . .. ...... .......... ..... ...... ..... 41, 52

PD......................................................................... 54, 41

TO............................................................................... 54

PORTB ............................................................................... 31

Power-down Mode .............................................................. 55

Prescaler ............................................................................ 38

Program Counter................................................................ 27

Q cycles.................... ........................... ..................... .......... 16

RC Oscillator....................................................................... 45

Reader Response............................................................. 108

Read-Modify-Write.............................................................. 33

PIC12F508 ................................................................. 19

PIC12F509 ................................................................. 19

PIC16F505 ................................................................. 19

Registers

Spec i a l Func t io n.......... ..... ...... .......... ..... ...... ...... ...... ... 2 0

Reset .................................................................................. 41

Reset on Brown -Out.......................... ............... .................. 54

Sleep .... .. ...... ...... ..... ...... ...... ..... .. ...... ...... ...... ..... ...... ..... 41, 55

Software Simulator (MPLAB SIM) ...................................... 66

Special Features of the CPU................... ..................... ...... 41

Special Function Registers................................................. 20

Stack................................................................................... 27

Statu s Reg i ster..................... ............... ..................... .... 11, 22

Timer0

Timer0 ........................................................................ 35

Timer0 (TMR0) Module .............................................. 35

TMR0 w i th Extern a l C l o ck .. ...... ...... .. ..... ...... ...... .. ...... . 37

Timing Diagrams and Specifications .................................. 75

Timing Parameter Symbology and Load Conditions .......... 75

TRIS Regis te rs ............... ..................... ............... ................ 31

PIC12F508/509/16F505

Wake-up from Sleep ...........................................................55

Watchdog Timer (WDT)......................................... .. .... .41, 52

Period..........................................................................52

Programming Considerations ..... ............... ............... ..52

WWW Address..................................................................107

WWW, On-Line Support ........................................................6

Zero bit............... ..................... ..................... .......................11

PIC12F508/509/16F505

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Micro chi p con sultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local S ales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical suppo rt is avail able throug h the we b site

at: http://support.microchip.com

PIC12F508/509/16F505

READER RESP ONSE

It is ou r intention to provide you w it h th e b es t documentation possible to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subject matter, and ways in whic h our doc umenta tion

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS41236EPIC12F508/509/16F505

1. What are t he best features of this d ocument?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

PIC12F508/509/16F505

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F505

PIC12F508

PIC12F509

PIC16F505T(1)

PIC12F508T(2)

PIC12F509T(2)

Temperature

Range: I= -40°C to +85°C (Industrial)

E= -40°C to +125°C (Extended)

Package: MC = 8L DFN 2x3 (DUAL Flatpack No-Leads)(3, 4)

MS = Micro-Small Outline Package (MSOP)(3, 4)

P = Plastic (PDIP)(4)

SL = 14L Small Outline, 3.90 mm (SOIC)(4)

SN = 8L Small Outline, 3.90 mm Narrow (SOIC)(4)

ST = Thin Shrink Small Outline (TSSOP)(4)

MG = 16L QFN (3x3x0.9)(5)

Pattern: Sp ecial Requirement s

Examples:

a) PIC12F508-E/P 301 = Extended Temp., PDIP

package, QTP pattern #301

b) PIC12F508-I/SN = Industrial Temp., SOIC

package

c) PIC12F508T-E/P = Extended Temp., PDIP

package, Tape and Reel

Note 1: T = in tape and reel SOIC, TSSOP and

QFN packages only

2: T = in tape and reel SOIC and MSOP

packages only.

3: PIC12F508/PIC12F509 only.

4: Pb-free.

5: PIC16F505 only.

Note: Tape a nd Ree l avai lable for on ly t he follo wing packages: SOIC, MS OP

and TSSOP.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

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Tel: 678-957-9614

Fax: 678-957-1455

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Tel: 774-760-0087

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Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

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Tel: 972-818-7423

Fax: 972-818-2924

Detroit

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Tel: 248-538-2250

Fax: 248-538-2260

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Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

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Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11 - 4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spai n - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921- 5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

03/26/09