PXB4310 - Siemens Semiconductors

ICs for Communications

ATM Switc hing Matrix

PXB 4310 Version 1.1

Preliminary Data Sheet 12.97 DS 2

PXB 4310

Revision History: Current Version : 12.97 Functional Update

Previous Version: Preliminary Data Sheet 08.95 (V 1.1)

Page

(in previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

23 30 VBIAS has no built-in bandgap reference

91 97 Note 17 changed to comment, new note 17 added

52-55 59-62 Register ISR some descriptions changed

57 66 Note to ILA register added

Bit LSE added, description o f LSYN C refined

57 66 Additional bit in LFR register

58-63 67-73 All register addresses changed

58 68 Bit RXof COR inverted

62 72 Register PQLR added

63 74 Bit IVINP added to MR register

47-50 53-56 Section about cell sequenc e simplified

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Edition 12.97

Published by Siemens AG,

HL TS,

Balans traße 73,

81541 München

Attention please!

As far as patents or other rights of third parties ar e concerned, liabil it y is only assumed for components, not for

applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change desi gn reserved.

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Com ponents used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Semiconductor Group of Si emens AG, may only be used in life-support devices or

systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a l ife-support device or system whose fa il ure can reasonably be

expected to cause the fail ure of that life- suppor t devi ce or system, or t o affect it s safety or effect iveness of that

device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or

maintain and sustain human life. If they fail , it is reasonable to assume that the health of the user may be en-

dangered.

PXB 4310
Table of Contents Page
Semiconductor Group 3 12.97
 
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1 Fe a tur e s   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .11
2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Pin Definitions and Functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Functional Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Functional Description   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1 Routing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2 Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4 Interfaces Description  . . . . . . .  . . . . .  . . . . . . . . . . . .  . . . . . . . . . . . . . . .  .30
4.1 High Speed Data Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.2 Multicast RAM Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Device Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 Boundary Scan  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.5 Microprocessor-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.6 Clock and Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5 ATM Cell Format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6 Examples for System Integration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1 Funnel-Type Switching Networks  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 .2 Ba n ya n  S w i t c h i n g  N e tw o rks  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .46
6.3 Multiplexers/Concentrators  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.4 Multicast Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Functional Blocks Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1 Bit Phase Alignment  . . . . . . . . . .  . . . . . . . . . . . . .  . . . .  . . . . . . . . . . . . .  .52
2 Cell Detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3 Deactivation of Input Ports   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4 Check of Header Parity Bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5 Device-internal Cell Parity Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6 Empty Cell Removal/Inse rtion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7 Output Port Bundling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8 ATM Cel l Sequence . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
9 Routing Evaluation   . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
10 Multicast Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
11 Output Queue Fairness Management . . . . . . . . . . . .  . . . . . . . . . . . . . . . .57
12 Cell Insertion via the Processor Interface  . . . . . . .  . . . . . . . . . . . . . . . . . .57
13 Cell Receiving via the Processor Interface  . . . . . . . . . . . . . . . . . . . . . . . .58
14 Procedures for System Failures  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

PXB 4310
Table of Contents Page
Semiconductor Group 4 12.97
 
Register Descriptio n  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1 Registers Table  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
1.1 Int er rupt Status Regis ter (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
1.2 Interrupt Mask Register (Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
1.3 Line Asynchronous State Register (Read Only)  . . . . . . . . . . . . . . . . . . . .64
1.4 Input Line Address (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
1.5 Line Error Register (Read Only)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
1.6 Line Failed Register (Read Only)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
1.7 Input Online Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
1.8 Command Register (Read/Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
1.9 Priority Threshold Register (Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
1.10 Maximum Queue Length Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . .71
1.11 Processor Queue Length Register (Read/Write) . . . . . . . . . . . . . . . . . . . .72
1.12 Multicast Transfer Register (Read/Write)   . . . . . . .  . . . . . . . . . . . . . . . . . .72
1.13 Output Line Address/ Multicast Address Register (Write)   . . . . . . . . . .  . . .73
1 .14 Mainte n an ce  Regis te r (Wri te)   . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .74
1.15 Phase Align Test Register (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.16 Free Cells Count Register (Read/Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.17 Version Code Register (Read)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.18 Mode Register (Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1.19 Output Group Register (Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
1.20 Identification Register (Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
1.21 Filter Mask Register (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1.22 LIC Protection Switch Register (Write)  . . . . . . . . . . . . . . . . . . . . . . . . . . .88
1.23 Transmit Cell Register 0 (Write Only)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
1.24 Transmit Cell Register 1 (Write Only)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
1.25 Receive Cell Register (Read Only)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1 Example for System Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
1.1 Programming of the ASMs   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2 State after Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3 Test and Communication Channels   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
4 Error Detections and Indications  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
4.1 External Error Detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2 Internal Error Detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
5 Test of Err or Indications   . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Electrical Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
1 DC Charact eri stic s . . . . . . . . . . . . .  . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .104
2 AC Characteris tics (Conditions: See Operating Conditions, Section 7.5) 107
3 µP -Int erf a ce Si gn al s (S e e Timi ng  Figure 37)  . . . . . . . . . . . . . . . . . . . . .111

PXB 4310

Table of Contents Page

Semiconductor Group 5 12.97

7.4 Multicast RAM Int erface Signals (See Ti ming Figure 38) . . . . . . . . . . . .114

7.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

9 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

10 Overview Li sts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

10.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

10.2 Glossary and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

PXB 4310
List of Figures Page
Semiconductor Group 6 12.97
 
Figure 1: ATM Switch Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Figure 2: Mini Switch with 622 Mbit/s Throughput. . . . . . . . . . . . . . . . . . . . . . . . . . .  9
Figure 3: ASM Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
Figure 4: Ball Configuration - The Index Mark is at Ball A1. . . . . . . . . . . . . . . . . . .  13
Figure 5: Block Diagram of ASM .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   19
Figure 6: ATM Cell Path through a Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
Figure 7: Self-routing Principle for Point-to-Point Connections . . . . . . . . . . . . . . . .   21
Figure 8: Table Routing Principle for Multicast Connections. . . . . . . . . . . . . . . . . .   22
Figure 9: Definition of F ilter Field and Routing Field . . . . . . . . .  . . . . . . . . . . . .  . . .  23
Figure 10: Applications for the Output Multiplexer. . . . . . . . . . .  . . . . . . . . . . . . .  . . .  28
Figure 11: High Speed Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
Figure 12: MC-RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
Figure 13: Device Test  Interface . . . . . . . .  . . . . .  . . . . . . . . . . . .  . . . . . . . . . . . . .  . .  32
Figure 14: Test Interface (Signals, Loading) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   33
Figure 15: µP-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
Figure 16: Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   35
Figure 17: RESE T Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   36
Figure 18: Format of Self-routing ATM Cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   38
Figure 19: Format of Multicast ATM Cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   39
Figure 20: Format of Empty Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   41
Figure 21: Structure of Protection Switch Identifier Cell . . . . . . . . . . . . . . . . . . . . . .   42
Figure 22: 5 Gbit/s Switching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   43
Figure 23: 10 Gbit/s Switching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
Figure 24: 7-Chip Funnel for 20 Gbit/s Switching Network . . . . . . . . . . . . . . . . . . . .  45
Figure 25: Generic Banyan Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   47
Figure 26: 40 Gbit/s Banyan Switch with Bundles of 2 . . . . . . . . . . . . . . . . . . . . . . .   48
Figure 27: A Switching Network Expanded by Multiplexers  . . . . . . . . . . . . . . . . . . .   49
Figure 28: Single Chip Bidirectional Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
Figure 29: Output Cell Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
Figure 30: Linear Input Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  55
Figure 31: Examp le Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  92
Figure 32: Core Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   94
Figure 33: ASM Addressi ng Concept Us ing SSNs . . . . . . . . . . . . .  . . . . . . . . . . . .  .  98
Figure 34: Transition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  110
Figure 35: Clock/Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   110
Figure 36: Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  110
Figure 37: µP Read/Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   113
Figure 38: Multicast Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   116
Figure 39: Modeling an ASM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   119
Figure 40: Buffer Sizes for Cell Loss Probability 10 – 11 . . . . . . . . . . . . . . . . . . . . .  120
Figure 41: Cell Loss Rate versus Load  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   121
Figure 42: Cell Delay Probability . . . . . . . . . . . . .  . . . . . . . . . . . .  . . . . . . . . . . . . . .  122

PXB 4310
List of Tables Page
Semiconductor Group 7 12.97
 
Table 1: Description of Used Header Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 2: Si ze and Chip Count for Funnel-type Switching Networks. . . . . . . . . . . . .45
Table 3: Size and ASM Chip Count for Banyan  Networks . . . . . . . . . . . . . . . . . . . .48
Table 4: µP/Control Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 5: Grouping of the Output Ports Corresponding to Content of OG(14:0) . . . . 84
Table 6: Grouping of the Output Ports Corresponding to Content of OG(14:0) . . . . 85
Table 7: Grouping of the Output Ports Corresponding to Content of OG(14:0) . . . . 85
Table 8: Testing of Error Indications .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 9: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 10: Operating Condit ions . . . . . . . . . . . .  . . . . . . . . . . . .  . . . . . . . . . . . . .  . . .117
Table 11: Glossary and Abbreviations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

PXB 4310

Introduction

Semiconductor Group 8 12.97

1 Introduction

The second generation of the Siemens ATM layer chip set consists of the six chips

• PXB 4310 ATM Switching Matrix ASM

• P XB 43 25 AT M Sw itching Pr epro cessor A SP

• PXB 4330 ATM Buffer Manager ABM

• P XB 43 40 AT M OAM Pro c e ssor AOP

• PXB 4350 ATM Layer Process o r ALP.

• PXB 4360 Content Addressable Memor y Element CAME

These chips form a complete chip set to build an ATM switch. A generic ATM switch

consists of a switching fabric and switch ports as shown in Figure 1.

Figure 1 ATM Switch Basic Configuration

In the Siemens ATM layer chip set the sw it ching fabric only does c ell r outing using the

PXB 4310 ASM, which can be used stand alone or in arrays to scale switching netw ork

throughput from 2.5 Gbit/s up to more than 40 Gbit/s. All ot her ATM layer functions are

performed on the switch ports: policing, header translation and cell counting by the

PXB 4350 ALP and the PXB 4360 CAME, OAM functions by the PXB 4340 AOP and

traffic management by the PX B 4330 ABM. The PXB 4325 ASP is the access device to

the switching fabric and adds/removes the routing header. It also supports redundant

switching fabrics and does multicast.

Only two i nterfaces ar e used for data transfer: t he industry s tandard UTOPIA [1, 2] Level

2 multi-PHY interfaces and the proprietary Switch Link InterFace SLIF. This is a serial,

differential high speed link using LVDS [3] levels.

PXB 4350

ALP

PXB 4340

AOP

PXB 4325

ASP

UTOPIAUTOPIAUTOPIAUTOPIA SLIF

ATM

switching

fabric

consisting

PXB 4310

ASM

chips

Pol.

RAM Pointer

RAM

Conn.

RAM

Cell

RAM

PHYs

Conn.

RAM

ARC

Conn.

RAM

PXB 4330

ABM

Conn.

RAM Conn.

RAM

Conn.

RAM

Cell

RAM

Conn. R AM = connection data RA M

Pol . RAM = policing data RA M

ARC = address reduction ci rcuit

Cell RAM = ATM cell s torage RAM

switch port

PXB 4310

Introduction

Semiconductor Group 9 12.97

For low end applications a sing le board switch with 622 Mbit/s throughput can be built

with only one PXB 4350 ALP and one PXB 4330 ABM. Such a mini-switch is bas ically

one switch port stand alone, without switching networ k access via the PXB 4325 ASP. I f

the full OAM functionality is not needed the PXB 4340 AOP chip can be omitted as

shown in Figure 2. Minimum OAM and multicast functionality is also built into the

PXB 4350 ALP. The external Address Reduction Circuit (CAME) is not required if the

built-in address reduc tion is used.

Figur e 2 Mi ni S witch with 622 Mbit/s Throughput

Apart from the two applications of Figure 1 and 2, m any other combinat ions of the chip

set are possible in designing ATM switches. Functionality is selectable in many

combinations due to the modular function split of the chip set. Address reduction,

multicast, policing, redundant switching network and other functions can be

implemented by appropriate chip combinations. The number of supported connections

scales with the size of the external connection RAMs. The policing data RAM can be

omitted if this function is not required.Thus functionality and size of an ATM s witch c an

be tailored exactly to what the respective application requires, without carrying the

overhead of unnecessary functions.

PXB 435 0

ALP

UTOPIAUTOPIA

Pol.

RAM Pointer

RAM

Cell

RAM

PHYs

ARC

Conn.

RAM

PXB 4330

ABM

Conn.

RAM

Cell

RAM

Conn . RAM = connection data RA M

Pol. RAM = policing data RAM

ARC = ad dress reduction circu it

Cell RAM = ATM cell storage RAM

PXB 4310

Overview

Semiconductor Group 10 12.97

2 Overview

The ATM Switc hing Matrix is a member of t he Siemens ATM integrated Chip Set. It is a

true ATM cell switch wi th 32 inputs and 16 out puts each of which can transport a ST M-1

equivalent load. Total maximum throughput is 2.5 Gbit/s. A shared buffer architecture

with individual output queues allows ATM cell loads of 95 % of a STM-1 payload for each

output. An adjustable buffer lim it is provided to acc ount for low priority cells.

The ASM supports both self-routing (with the output port address contained in the cell

header) and multicast (using an external look-up table). The chip can be used stand-

alone or in a networked configuration. It can be configured in various operating mode s.

Multiple ASMs can be connected to build switching networks of arbitrary size.

A cont inuous growth from small to very large switching networks is poss ible.

Inputs and outputs are realized as serial, differential transmission lines, defined as

Switch Link Interface (SLIF). The serial interface allows a lower pin count and less power

dissipation compared to chips with parallel I/Os. Both features result in a smaller and

cheaper chip. The low pin count is an important feature if larger switching networks are

built which extend over multiple boards via backplane. No clock line is necessary to

transmit data, as each input of the ASM has an individual bit phase adaptation.

The ASM has the capability of bundling 2, 4, 8 or 16 lines to form pipes of higher bit rates

up to 2.5 Gbit/s. In these cases the transmitting ASM distributes the cells cyclically on the

lines of the bundle, so t hat the receiving ASM can reconstruct the correct sequence. This

feature facilitates the bandwidt h management for the interconnection lines of a swi tching

network and allows the later support of 622 Mbit/s and 2.5 Gbit/s line interfaces.

Electrical characteristics of the SLIF are according to the LVDS standard defined by

IEEE [7]. The LVDS signals have low voltage swing and use 50 Ω terminated

transmission lines. The low impedance and the differential signal guarantee a secure

data transmission, even via connectors, backplanes and t wisted or coaxial cable pairs of

up to some m ete rs length. This simplifies the construction of large switching networks.

The data format is the Siemens proprietary 64 byte ATM cell which contains the

standardized 53 byte ATM c ell extended by routing and housekeeping inf or mations.

The conversion from standardized 53 byte cell format to SLIF format is done by the

PXB 4325 ATM Swit ching Preprocessor ASP which connects to one, two or four lines of

the switching network. The ASP frees the user to cope with the da ta format inside the

switch; simply writing the des ired output port of the switch into the upstream translation

RAM of the ASP defines the path through the network . The ASP does all the necessary

conversions in both direc tions, i.e. at the s witch input port and at the switch output port.

It has a bidirectional throughput of one, two or four STM-1 equivalents.

The ASM is controlled via a generic 8-bit microprocessor interface with 8-bit address

bus.

P-BGA-352

Semiconductor Group 11 12.97

ATM Switching Matrix

PXB 4310

Version 1.1 CMOS

Type Ordering Code Packa ge

PXB 4310 Q67101-H6587 P-BGA-352

2.1 Features

• Self-routing switching matrix with built-in multicast

function and redundant switching architecture

support.

• High performance: 10 – 10 cell loss probability with

87 % Bernoulli type traffic (corresponds to 96 % load

on a STM-1/ OC-3 link).

• Internal speed-up concept reduces cell load inside

the switching network.

• Central buffer architecture provides minimum cell delay variation at high data

throughput.

• Routing Header provides 32-bit routing address, f reely configurable.

• Expan dable up to 256 ×256 non-blocking switching network core.

• Blocking switching networks up to 32768 ×32768 ports.

• Free programmable input filter function.

• Configurable as single chip multiplexer/demultiplexer.

• Prepared for 622-Mbit/s and 2.5-Gbit/s ports.

• Uses 200-Mbit/s serial, differential data link lines, the Swit ch Link Interface.

• Switch Link Interface uses LVDS levels for low crosstalk, less interference and low

power consu mption.

• Individual phase adaptation per in put; no separate clock required.

• Static output multiplexer allows flexible assignment of output queues to outputs e.g.

for prot ection switching support.

• Intel compatible 8-bit microprocessor interface f or chip control.

• 3.3-V 0.5-µ-CMOS technology.

• Power dissipation below 3 W.

• 352-pin bal l- gri d array.

PXB 4310

Overview

Semiconductor Group 12 12.97

2.2 Logic Symbol

Figur e 3 ASM Logic Symbol

PXB 4310

Overview

Semiconductor Group 13 12.97

2.3 Pin Configuration

(bottom view)

Figure 4 Ball Configuration - The Index Mark is at Ball A1

A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1 AE1 AF1

A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AC2 AD2 AE2 AF2

A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AD3 AE3 AF3

A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AC4 AD4 AE4 AF4

A5 B5 C5 D5 AC5 AD5 AE5 AF5

A6 B6 C6 D6 AC6 AD6 AE6 AF6

A7 B7 C7 D7 AC7 AD7 AE7 AF7

A8 B8 C8 D8 AC8 AD8 AE8 AF8

A9 B9 C9 D9 AC9 AD9 AE9 AF9

A10 B10 C10 D10 AC10 AD10 AE10 AF10

A11 B11 C11 D11 AC11 AD11 AE11 AF11

A12 B12 C12 D12 BGA 352 AC12 AD12 AE12 AF12

A13 B13 C13 D13 AC13 AD13 AE13 AF13

A14 B14 C14 D14 b o ttom v ie w AC14 AD14 AE14 AF14

A15 B15 C15 D15 AC15 AD15 AE15 AF15

A16 B16 C16 D16 AC16 AD16 AE16 AF16

A17 B17 C17 D17 AC17 AD17 AE17 AF17

A18 B18 C18 D18 AC18 AD18 AE18 AF18

A19 B19 C19 D19 AC19 AD19 AE19 AF19

A20 B20 C20 D20 AC20 AD20 AE20 AF20

A21 B21 C21 D21 AC21 AD21 AE21 AF21

A22 B22 C22 D22 AC22 AD22 AE22 AF22

A23 B23 C23 D23 E23 F23 G23 H23 J23 K23 L23 M23 N23 P23 R23 T23 U23 V23 W23 Y23 AA23 AB23 AC23 AD23 AE23 AF23

A24 B24 C24 D24 E24 F24 G24 H24 J24 K24 L24 M24 N24 P24 R24 T24 U24 V24 W24 Y24 AA24 AB24 AC24 AD24 AE24 AF24

A25 B25 C25 D25 E25 F25 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25 U25 V25 W25 Y25 AA25 AB25 AC25 AD25 AE25 AF25

A26 B26 C26 D26 E26 F26 G26 H26 J26 K26 L26 M26 N26 P26 R26 T26 U26 V26 W26 Y26 AA26 AB26 AC26 AD26 AE26 AF26

PXB 4310

Overview

Semiconductor Group 14 12.97

2.4 Pin Definitions and Functions

Pin No. Symbo l Func tion

Inputs

AD15, AC15 DI0, DI0 Differential data inputs.

AE15, AE14 DI1, DI1 Data rate up to 208 Mbit/s.

AC14, AD14 DI2, DI2

AD13, AC13 DI3, DI3

AC12, AD12 DI4, DI4

AD11, AC11 DI5, DI5

AE11, AE10 DI6, DI6

AC10, AD10 DI7, DI7

AD 9, AC9 DI8 , DI 8

AC 8, AD8 DI9 , DI 9

AD7, AC7 DI 10, DI10

AE7, AE6 DI11, DI11

AC6, AD6 DI 12, DI12

AD5, AC5 DI 13, DI13

AC3, AC4 DI 14, DI14

AC2, AB2 DI 15, DI15

AB4, AB3 DI16, DI16

AA3, AA4 DI17, DI17

Y4, Y3 DI18, DI18

W3, W4 DI19, DI19

W2, V2 DI20, DI20

V4, V3 DI21, DI21

U3, U4 DI22, DI22

T4, T3 DI23, DI23

R3, R4 DI24, DI24

R2, P2 DI25, DI25

P4, P3 DI26, DI26

PXB 4310

Overview

Semiconductor Group 15 12.97

N3, N4 DI27, DI27

M4, M3 DI28, DI28

L3, L4 DI29, DI29

L2, K2 DI30, DI30

K4, K3 DI31, DI31

G3 VREF Analog reference voltage input, used f or a pr ec is e

adjustment of t he internal current sources.

VR EF -value: (1 .2 ±0.1)V

C22, D22,

B22, D23,

D25, E25,

E2 3, E24

ADR0 … 7 Address bus of the µP-interface.

K23 CS Chip select signal of the µP- interface (low active).

L23 WR Write enable signal of the µP-interface (low active).

L26 RD Read enable signal of the µP-inte rf ace (lo w a ctiv e ).

F2 RESET Hardware reset, blocks all cell output data (DO) while

‘0’; starts internal reset procedure with the low to high

level transition.

D2 0 TMS Bo un da ry Sc a n Test Mode Select.

B20 TDI Boundary Scan Test Data Input.

B21 TRST Boundary Scan Test Reset.

G2 TMOD Device test mode status signal, cont rol s the

chip-internal generation of the phase-alignment

clocks. During nor mal operation, TMOD must be

kept at ‘0’ in normal operation.

AC21 TEST Test mode signal, for device test onl y. Must be

kept at ‘1’ in normal operation.

Outputs

D19, C19 DO0, DO0 Differential dat a outputs. The outpu ts operate

C18, D18 DO1, DO1 into a 50 Ω line terminated by a 50 Ω resistor.

D17, C17 DO2, DO2

C16, D16 DO3, DO3

D15, C15 DO4, DO4

Pin No. Symbol Function

PXB 4310

Overview

Semiconductor Group 16 12.97

C14, D14 DO5, DO5

D13, C13 DO6, DO6

C12, D12 DO7, DO7

D11, C11 DO8, DO8

C10, D10 DO9, DO9

D9, C9 DO10, DO10

C8, D8 DO11, DO11

D7, C7 DO12, DO12

C6, D6 DO13, DO13

D5, C5 DO14, DO14

C4, D4 DO15, DO15

G4 R0 Calibrat ion output, used for an external resist or

between R0 pin and ground.

Resistor value 12.1 kΩ±1%.

C20 R1 Calibrat ion output, used for an external resist or

between R1 pin and ground.

Resistor value 12.1 kΩ±1%.

J23 INT0 Interrupt 0 of the µP -interface, open drain

output (low active).

J24 INT1 Interrupt 1 of the µP -interface, open drain

output (low active).

K24 RDY Ready signal of the µP -i nterface, open drain

output (high act iv e).

W24, Y24,

Y23 , Y25 ,

AA25, AA23,

AA24, AB24,

AB25, AD23,

AC 23 , AE 23 ,

AE22, AC22,

AD 22 , AD21

MCADR0 … 15 Address bus f or Multicast RAM.

L24 MCWR Writ e signal for Multicast RAM (low active).

M24 MCOE Output enable signal for Multicast RAM (l ow active).

C21 TDO Boundary Scan Test Data Output.

Pin No. Symbo l Func tion

PXB 4310

Overview

Semiconductor Group 17 12.97

AE21, AE20 ,

AC20, AD20,

AD19, AC19,

AE19, AE18 ,

AC18, AD18

TCO0 … 9 Test control outputs, f or device test purpose only.

AD17, AC17,

AE17, AC16,

E3 , E4, E2

TFO0 … 6 A nalog test outputs, for device test only. Must be

left open.

F4 CSS Analog device test output, source follower; indicates

the cell starts, i.e. the 1st octet of the cells clocked out

at the data output DO0. Must be termi nated wit h 50 Ω

when used, otherwise open.

Bidirectional Pins

F24, F23,

G25, G23,

G24, H24,

H23, J25

DAT0 … 7 Data bus of the µP-interface.

N25, N23,

N24, P24,

P23, R25,

R23, R24,

T24, T23,

U25, U23,

U24, V24,

V23, W25

MCDAT0 … 15 Data bus for the Multicast RAM.

W23 MCP Parity bit f or the Multic ast RAM.

Clock Inputs and Outputs

J2 CL I Operating cloc k input with a frequency of up to

208 MHz.

H2 CL I Complementary clock input.

D21 TCK I B oundary Scan Test Clock Input.

Pin No. Symbol Function

PXB 4310

Overview

Semiconductor Group 18 12.97

M23 M CCLK O Clock output for Multicast RAM, frequency is 1/8 of

the operating clock.

F3 CLO O Analog device test clock output, source follower,

operates at a f requency of up to 208 MHz; the pos itive

edge clocks the output data and can be used to strobe

them. Mu st be terminated with 50 Ω.

Pin No. Sym bol

Power Supply

A1, B1, E1, F1, J1, K1, N1, P1, U1, V1, AA1, AB1, AE1, AF1, A2, C2,

N2, U2, A A2, AD2, AF2, B3, D3, H3, J3, AE3, B4, AD4, A5, AF5, A6,

B6, AF6, B8, AE8, A9, AF9, A10, B 10, AF10, B12, AE12, A13, AF13,

A14, B14, AF14, B16, AE16, A17, AF17, A18, B18, AF18, A21, AF21,

A22, AF22, C23, B24, AC24, AE24, A25, C25, AD25, A F25, A26, B26,

E26, F26, J26, K 26, N26, P26, U26, V26, AA26, AB26, AE26, AF26

C1, D1, G1, H1, L1, M1, R1, T1, W1, Y1, AC1, AD1, B2, D2, M2, T2,

Y2, AE2, A3, C3, AD3, AF3, A4, H4, J4, AE4, AF4, B5, AE 5, A7, B7,

AF7, A8, AF8, B9, AE9, A11, B 11, AF11, A12, AF12, B13, AE13, A15,

B15, AF15, A16, AD16, AF16, B17, A19, B19, AF19, A20, AF20, A23,

B23, AB23, AF23, A24, C24, AD24, AF24, B25, AC25, AE25, C26,

D26, G26, H26, L26, M26, R26, T26, W26, Y26, A C26, AD26

GND

D24, F25, H25, K25, M25, P25, T25, V25 not connected

Pin No. Symbo l Func tion

PXB 4310

Overview

Semiconductor Group 19 12.97

2.5 Functional Block Diagram

Figure 5 Blo ck Diagram of ASM

PXB 4310

Overview

Semiconductor Group 20 12.97

2.6 System Integration

The ASM needs the PXB 4 325 ATM Sw itching Preprocessor ASP as access device. A

generic circuit is shown in Figure 6. It shows the path of ATM cells through a switch.

ATM cells with standardized 53-octet cell format are input at the UTOPIA receive

interface of the ASP w hich expands the cells to 64-octet format by a dding routing and

housekeeping octets. The cells are output at the serial SLIF interface which is connected

to the ATM switching network ASN. The ASN m ay be of arbitrary size, consisting from

one stand-alone ASM up to an array of many ASM chips. In any case the routing header

of the cells defines a unique path through the ASN to the desired output port, which is

connected to an ASP. This chip does the necessary post-processing and reduces the

cell t o standardized 53-octet format, which is output at the UTOPIA transmit in terface.

The operating clock of up to 208 MHz is supplied to all ASM and ASP chips in the

system. It needs not necessarily come from t he same clock source, but the frequencies

must be within a certain range (refer to Section 7.2, page 107).

Figur e 6 ATM Cell Path thr ough a Switch

Figure 6 shows that the ASP chips allow the connection of two switching network planes

for redundancy or load sharing purposes.

ITS07425

208 MHz

UTOPIA

Receive i/f

Transmit i/f

UTOPIA

ASM

208 MHz 208 MHz

ASM

ASN = ATM Switching Network

Plane 0

Plane 1

SLIF SLIF

ASP

PXB 4310

Functio n a l D e s c r ipt ion

Semiconductor Group 21 12.97

3 Functional Description

The ASM has two main func tions, routing and queuing.

Routing is the true swit ching function of forwarding A TM cells f rom any i nput to a desired

output. The routing information is contained in the header of the ATM cells. The ASM

evaluates the routing header information with respect to its configuration.

Queuing occurs due to t he asynchronous nature of ATM. For a short time more cells may

arrive at the ASM inputs than can be forwar ded by the outputs and thus accumulate in

the internal buffer. Queuing thus means for the ASM to store cells and queue them to the

respective output ( s) by preserving the cell sequence f r om the inputs.

3.1 Routing

The ASM is capable to route ATM cells received at any input to one or more desired

outputs. It can switch two types of cells, point-to-point and point-to-multipoint

(=multicast) cells. For point-to-point cells the self routing principle is used, i.e. the cell

carries the information of the desired output directly in its own routing header.

Figure 7 sho ws the s elf routing principle. In this exam ple the cell c omes in at input line

6 of a switching element. It has a prepended routing header carrying the pattern

101bin =5

dec. and a bit identifying t he cel l as self-routing cell. The switching element uses

the pattern as encoded output number and programs the output multiplexer accordingly.

The cell is thus forwarded to output 5.

Fi gur e 7 Self- rou ti ng Pr i nc ip le fo r Po in t-to -P o in t Co nn ec ti o ns

For multicast cells the table r outing method is used, where a part of the cell header is

used as address to a routing table. Each entry of this table defines the outputs of the

(multicast) connection.

Figure 8 shows the table routing principle. The cell comes in at input line 6 of a swit ching

element. The prepended routing header has the same pattern as in the self-routing

PXB 4310

Functio n a l D e s c r ipt ion

Semiconductor Group 22 12.97

example with the excep tion that the cell is identified as table routing cell. The switching

element in this c ase uses the pat tern 101 bin as addres s to a table where the out put( s) of

the switching element are represented by a 8-bit patt ern. A „one“ means that the cells of

this connection are to be forwarded to the corresponding output. In the example of

Figure 8 bit the bit positions 2 and 3 are denoted at the table location 5 an d hence the

cell is output at outputs 2 and 3.

Figure 8 Table Routing Principle for Multicast Connections

Note that table routing could be used for point-to-point and point-to-multipoint

connections. However, it is recommended to use table routing only for multicast

connections, as self-routing does not require to handle table entries.

The lookup table for multicast is realized in the ASM as external RAM (MC-RAM) . The

size of the table determines the total number of multicast connections in the switch. A

maximum of 65536 multicast connections are supported by the ASM, limited by the

address bus width of the MC-RAM interface. If less multicast connecti ons are needed in

a switch a smaller MC-RAM can be connected. It can be omitted if the multicast

functionality is not required at all.

PXB 4310

Functio n a l D e s c r ipt ion

Semiconductor Group 23 12.97

Self routing

For self routing up to four bit are required to determine the output of an ASM. The four

bits must be contiguous. Their location within the 32-bit routing tag is programmable.

This offers maximu m flexibility in the design of switching networks.

If a switching network c onsists of several stages as sh own e.g. in Figure 25, the A SM

chips of each stage are p rogrammed to ’look’ at a different four b it group. A three stage

switching network would require three groups of four routing bits. If outputs are bundled

(see below) less than fou r bits are needed for rout ing.

Each of the switching elements shown in Figure 25 could be built with two ASMs

connected in parallel. To support such a configuration the ASM has the input filter

function.

Input filtering

The input filter function allows to connect the inputs of multiple ASMs in parallel. This

allows to build s witching networks as shown e.g. in Figure 22, where the right hand ASM

filters out (accepts) only the cells destined to outputs 0..15 and the left hand ASM

accepts only the cells for outputs 16..31.

The filter function also uses the 32-bit routing tag. The 32-bit fi lter mask regist er defines

an arbitrary part of the routing tag as filt er field as shown in the example of Figure 9. Th e

content of this field of each cell is compared to the respective part of the 32-bit

identification register. The cell is only accepted if the two pattern match. Masked bits

always match, so that when all bits are masked the cell is acc epted anyway.

Figur e 9 De finition of F ilter Fie ld a nd Ro uting Field

In the example of Figure 9 the filter field of the cell matches the content of the

identification register and the cell is accepted.

Separation of filter field and routing field is completely arbitrary. Both may even be

non-contiguous and spread over the whole 32-bit range. This arbitrary definition

31 20 0

1011 0100 0111 xxxx xxxx xx xx xxxx xx xx Routing tag of the cell

1111 1111 1111 0000 0000 0000 0000 0000 Filter mask regist er

←------ Filter field -----→ ←------- Routing field -------→

1011 0100 0111 xxxx xxxx xx xx xxxx xx xx Identification register

←------- Mat ch ! ----- --→

PXB 4310

Functio n a l D e s c r ipt ion

Semiconductor Group 24 12.97

possibility gives maximum flexibility for the design of switching networks. There are,

however, some restrictions which s hould be taken into account:

• Routing and filt er fields should not overlap.

• In split mode the 6 LSBs of the routing tag are reserv ed (see below).

• It may be useful to restrict the multicast function to s ome of the ASMs in a sw itching

network (see Fi gure 32).This avoids the MC-RAM at some of the ASMs. These ASMs

may be programmed to ignore multic ast c ells and treat them as s elf routing cells. The

filter and routing fields interpreted by these ASMs must use th e par t of t he r o uting t ag

which is not used as multicast address (AUX- bits of Figure 19).

Special routing functions

• Depending on the configurat ion of the output multiplexer (see Figure 10) the physical

output can be diff erent to the specified output num ber. It may also be configured that

the same cell is forwarde d to s everal outputs, a function whic h is independent o f the

multicast function.

• If SLIF bundles are declared (see below) the cell is output at any output within the

bundle. If e.g. the 4 routing bits specify output 2, and a 4-bundle is declared for outputs

0 … 3, the cell may be output at any output of this bundle, but not necessarily at

output 2.

• For the special case that all outputs form one 16-bundle the output number is

meaningless. If addi tionally the fi lter function is switched off (by masking all 32 rout ing

bits) the ASM works as a simple multiplexer. This mode i s used i n the m iddle stage of

Figure 24.

Split Mode

This is an additional fe ature to the self-routing mode. Normally the cells from all inputs

are treated identic ally . In split mode, t he 32 inputs can be split into two group s with the

cells input at different groups routed according to different routing bits. The two input

groups can be defined by programming a value n between 0 and 30 to the mode register

of the A SM . The respective routing is as follows:

• inputs 0..(n-1) , lower part : fixed routing according to the 4 LSBs of the rout ing tag (bi ts

0..3) with a sm all, fixed, 2-bit filter field (bits 4 and 5) . Unlike the normal filt er function

this filter field is not maskable.

• inputs n..31, higher part: n ormal routing tag ev aluation with filter option as des cribed

above.

Split mode is used for single chip multiplexers with concentrating upstream traffic and

distributing downstream traffic (see e. g. Figure 28).

PXB 4310

Functio n a l D e s c r ipt ion

Semiconductor Group 25 12.97

Communication and test cell routing

The ASM has the c apability to insert cells from the micr oprocessor interface int o the cell

stream and to extract cells from the cell stream and direct them to the microprocessor

interface. There are two applications for these features, system test and internal

communication.

System tests can be done in-service e.g. to check the availability of all interconnection

lines between the ASMs of a switching network and between ASM and ASP devices. For

this purpose test cells can be i nserted at s pecified output s, even i n bundle mode. It also

is not influenced by the setting of the output multiplexer, but uses always the default

path.

Communication cells could be used in large switches, where the switching network

consists of several boards. A dedicated µP could be used to control the ASM chips e.g.

on a switch board. A communic ation channel to this µP can be set-up via the data lines

to the system controller. One ASM will be selected to drop the communication cells.

To support this feature the ASM provides two transmit buffers of one cell size and a

receive buffer queue. To detect incoming test or communication cells the switching stage

number (SSN) field of the prepended routing header is used. A cell is extracted if the

SSN is non-zero and matches the SSN assigned to th e respective ASM chip.

Some features of this function are:

• The f ilter function is applied normal ly before comparing the SSN.

• The non-zero SSN fi eld overrides the multicast indication bit of the cell , i.e. these cells

are never treated as multicast cells.

• The acceptance of all other cells than communication or test cells can be disabled.

This is espec ially useful du ring the initialization phase of a c hip.

3.2 Queuing

Queuing occurs due to the asynchronous nature of A TM. As the arrival of ATM cells of

a given conn ection is not in a fixed time slot, it may happen that simultaneously two or

more cells destined to the same output may arrive at the inputs. As the output can

forwar d only one c ell at a time, the other cell(s) ha ve t o be st ored inte rme diately. If at a

later time no cells are destined to this output the ASM can work off the stored cells and

empty the buffer. The maximum number of cells which has to be stored for a gi ven output

load can be derived using statistical met hods (see appendix).

Throughput

The ASM is able to switch ATM cells with a data rate of up to 208 Mbit/s from up to 32

high speed inputs ports to 16 high speed output ports. 208 Mbit/s is the data rate of one

SLIF line. As the SLIF cell format is 64 octet, the effective data rate with reference to

standard, 53-oct et ATM cells is 208 Mbi t/ s x 53/64 = 172. 25 Mbit/s.

Its total effective throughput is thus 16 x 172.25 Mbit/s = 2.756 Gbit/s.

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Fairness Management

The fairness management determines the maximum number o f queue entries for each

output queue. It is recommended to specify a maximum queue length if more than one

output queue are configured. Otherwise one output queue - e.g. in an overload

situation - could occupy the whole buffer, so that all cells destined to any other output

are discarded.

The maximum queue sizes for a given load and for a cell loss probability of 10–11

can be

obtained from Figure 40. If as an example the ASM operates with a load of 90 % the

required total buffer size is 270 cells. The buffer limit for the single queue can be obtained

from the curve ‘X|1-Multiple xer’, which amounts to 12 8 cells approximately.

For bundles of 4 or 8 the maximum queue size is obtained from the curves

‘X|4-Multiplexer’ and ‘X|8-Multiplexer’, respectively. For the above example the values

are 160 and 202, respectively. For bundles of 2 the value can be extrapolated from

curves ‘X|1-Mult iplexer’ and ‘X|4-Multiplexer’.

For each sort of bundle group (also for single ports) the maximum number of queue

entries can be specified by a thr eshold defined via the µP-interface.

Output Grouping

The ASM is able to route A TM cells to a specified output or to a bundle of outputs. The

bundle size can be 2, 4, 8, or 16.

The input and output sections of the ASM are able to handle data streams of up to

16 ×155 Mbit/s = 2.5 Gbit/s without violating cell s equence integrity (see Section 4.7).

Priority Handling

A control feature incor por ated within the c hip- internal logic enables the device to handle

cells of two different priorities (high and low) by permanently evaluating the cell loss

priorit y bit CLP.

For low priority cells (CLP = 1, Figure 18 and 19) a threshold for t he total buffer fill can

be programmed. There is no individual queue limit f or low priority cells.

3.3 Other Functions

Cell check

All incoming cells are checked for correct header parity. Cells with false parity bit are

discarded. Empty1) cells defined b y a s pecial hou sekeeping pattern are disc arded. The

ASM generates new empty cells at the output ports if neces sary (cell rate decoupling).

1) The term ‘empty cel l’ is used to denote stuffing cells inside the swi tching network. These are proprietary ce lls

and must not be mixed up with the standardized unassigned or idl e cells. Empty cel ls never leave t he switching

network.

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High Speed Inpu t/Output Operation

The dat a inputs/outputs work with LVDS-compatible si gnal levels. The appr opr iate data

rate is c omm on for all t he I/Os and amounts to 208 M bit/s.

The LVDS-compatible system clock inputs operate with the single frequency clock of

208 MHz.

Bit Phase Alignment

In order to enable an asynchronous clock/data operation the switch is equipped with

32 internal phase-aligning c ircuits, each processing one of the dat a inputs.

Cell Start Detection

The ASM detects cell start using Sync byte with the MSB toggeling to prevent

mis-synchronization to possible payload pattern. Hence the Sync byte alternates

between E8H and 68H.

Output Mult iplexer

A static multiplexer located between output queues and parallel-to-serial converters

allows the arbitrary assignment of each out put to any output queue, i.e. each output can

be programme d to get the cells from an arbitrary output queue. Several outputs can be

assigned to one output queue. This means that multiple outputs get the (identic al) cell

stream from the same output queue.

Applications for this feature are 1:1 or n:1 redundancy schemes as shown in Figure 10

showing two applications. Outputs 0 and 1 are both connected to the same queue 0.

Hence both have the identical cell stream. This can be used to have two transmission

lines with 1:1 redundancy. The other outputs are configured as a 13:1 redundant system.

Outputs 2 … 14 are active, output 15 is redundant. If any of the transmission lines

connected to the active outputs fails output 15 can be switched to this output to take over.

In the example of Figur e 10 t he transmission line of output 2 has faile d.

The feature is eff ectively a protection of the line card or LIC and is therefore referenced

in this document as ‘LIC Protecti on Switch LPS’.

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Figure 10 Applications for the Output Multiplexer

Cells which are addressed to an output queue which is not connected to any output are

discarded. In t he example of Figure 10 the cells of queues 1 and 15 are discarded.

The change of queue to output assignment can be done in-service. To identify the

switch-over of any output queue, the ASM inserts a Protection Switch Identifier cell

(PSI-cell) between the last c ell of the ‘old’ central buffer output and the first cell of the

‘new’ central buffer output. E.g. in case of the above example before the switchover

queue 15 would receive no cells and thus on ly empty cells are produced at the output.

After the queue change comm and the PSI-c ell would be inserted at output 15 before the

first cell coming from central buffer output 2.

Immediately after the switchover comm and for a queue this queue could contain some

cells fr om the ‘old’ central buffer output, then a P SI-ce ll, and then the first cells from the

‘new’ central buf fer output.

Logic C ontrol

Control functions ar e implemented, to per manently s upervise the HW i ns ide and outside

the chip:

– Chec k of synchronization stat e (SYNC/ASYNC state) for each input port,

– P arity check of th e internal header oc tets used by the ASM (external parity),

– B yte-interleaved parity check made on the whole cell itself (chip internal parity),

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– Check of the correct chip-internal queue handling by parity protected multicast entries,

cell location data and cell entry usage count,

– Check of the actual buff e r occupation (buffer overf low, queue over flow).

Test of Control Functions

The control functions can be separately tested via the µP-interface of t he ASM. This can

be done during normal operation, i.e. without any need for disconnecting or even

removing the devic e, a fact that drastically relieves the supervision of the system and the

localization of pote ntial failures.

Device Test Functions

The ASM offers boundary scan for all inputs and outputs with the following restrictions :

– No self test and

– High speed input/output ports can only be monitored and not disconnected.

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3.4 Interfaces Description

3.4.1 Hig h Speed Data Interface

Figure 11 High Speed Data Interface

– Data Inputs (DI/DI)

There are 32 separ ate pairs of c omplement ary (‘differential’), high speed dat a inputs

DI0/DI0 … DI31/DI31. Each of these is a serial NRZ input, operating at up to

208 Mbit/s and at LVDS levels.

Note: Open data inputs should be hold at defined and complementa ry levels or should

be disabled in t he Input Online Register IO R.

– Data Outputs (DO, DO)

There are 16 separate pairs of complementary (‘ differential’), high-speed data outputs

DO0/DO0 … DO 15/DO 15. Each of these is a serial non-return to zero (NRZ) ou tput,

operating at up to 208 Mbit/s and at LVDS-levels. A termination resistor of 50 Ω has to

be connected to each output line. Every two matching resistors belonging to one

output pair are connected via a capacitor to the ground level.

Note: To avoid any improper high voltage operation potentially occurring with

unconnected outputs, it is strictly recommended to terminate them always by a

Ω

resistor.

– Precision Reference Voltage (VREF)

The precision reference voltage VREF [value: ( 1.2 ±0.1 )V] is used to define properly

the internal current source of the input-/output-circuits together with the precision

res istors R0 / R1.

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VREF is connected directly to standard voltage generators. The current dr awn by the

VREF pin is less than 1 A (diode current ).

– Resistor Pin R0

The external resistor R0, connecting the appropr iate R0 pi n and ground, is necessary

to define th e internal c urrent sources of e.g. the data and clock inputs to the required

current conditions.

Present value: R0 = 12.1 kΩ±1 % (precision resistor).

– Resistor Pin R1

The external resistor R1, connecting the appropr iate R1 pi n and ground, is necessary

to define the internal current source of the data outputs to the required current

conditions.

Present value: R1 = 12.1 kΩ±1 % (precision resistor).

3.4.2 Multicast RAM Interface

This in terface (Figure 12) is used for the connection of an ex ternal synchronous SRAM

(64 k ×18 bit) containing the multicast look-up table. It can be omitted if the multicast

function is not desired.

Figure 12 M C-RAM Interface

The interface consists of a sixteen-bit wide non multiplexed address bus (MCADR), a

sixteen-bit wide bidir ectional data bus ( MCDAT), 1 data parity line ( M CP), 1 c lock signal

(MCCLK) and two control lines (MCWR, MCOE) for the flow control. The clock line

supplies the RAM with the A SM-internal octet clock (1/8 of the operating clock of up to

208 MHz). All the signals work with LVCMOS logic lev els.

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3.4.3 Device Test Interface

The Device Test Interface (see Figure 13) is used for production test only. During

normal operation TMOD and TEST must always be connect ed to ‘0’ (GND potential), the

two test inputs TFI0,1 have to be held open or at ‘1’.

The Test Contr ol outputs TCO0 … 9 and TFO0 … 6 should be left open.

Only the CLO and CSS outputs may be used for test purposes.

Figure 13 Device Test I nterf ace

– Clock Output S ignal (CLO)

The clock output signal CLO given out via a source follower output allows the

observation of the operating clock of the ASM (frequency: up to 208 MHz) with an

oscilloscope. Its pos itive edge c loc ks out the data and can be us ed to strobe the dat a

output signals.

Since the output buffer employed is pulling up actively towards the s upply voltage VCC

only, it has to be provided externally with a pull-down resistor of the recommended

value of 50 Ω, to achieve a v oltage swing of about 490 m V typical.

– Cell Start Signal (CSS)

The cell start signal CSS given out via an source follower output defines the 1st octet

of the cells clocked out via the data out puts DO0/DO0.

Therefore it can be used as a cell trigger signal.

For a proper operation the output employed has to be provided externally with a

pull-down resistor of the recommended value of 50 Ω, to achieve a voltage swing of

about 490 mV typical.

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3.4.4 Boundary Scan

The boundary scan of the ASM complies the standard requirements according to JT AG

with the following restrictions:

• High speed data inputs and outputs can only be observed

• No self test possibility

Figure 14 Test Interface (S ignals , Loading)

– Test Clock Input (TCK)

This control in put needs a system-independent test clock.

– Tes t Mod e Se l ec t (T MS )

This control input is used for the initialization of the Test-Access-Port controller

(TAP controller).

– Test Data Input (TDI)

All test information is serially loaded into the ASM via this data input. The data are

taken over with the rising edge of TCK.

– Test Da ta Output (TDO)

All test information left the ASM via this data output with t he falling edge of TCK.

– Test Reset (TRST)

Asynchronous reset for the TAP controller (low active). The state of the TAP controll er

is not influenced by the system reset (RESET pin) of the ASM.

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3.4.5 Microprocessor-Interface

This i nterface consists of an eight bit wide, generic, non multi plexed microprocessor bus

as required for i nterfacing of 80x86 processors, and of additional c ontrol lines as shown

in Figure 15. All the signals work with LVCMOS logic levels.

Figure 15 µP-Interface

– Dat a Signals (DAT0 … DAT7)

There is a 8-bit wide bidirectional data i nterface between the µP and the ASM to gain

access to the different internal register sets inside the ASM. It is controlled by the

chip-select- (CS), read- (RD), and write-signals (WR). During the non-selecting phase

(CS inactive) the port is switched into the inactive high impedance state. With CS

ac tive (CS = ‘0’), the d ata bus is configured as an input por t during a wr ite cycle and

as an output port during a r ead cycle.

– Address Signals (ADR0 … ADR7)

The 8-bit wide common unidir ectional addr es s bus perfor ms t he s election of the ASM

internal registers f or the read or write cycles.

– Bus Control Input Signals ( CS, RD, WR )

There are three cont r ol inputs with common low active signals to select the chip (CS)

and t o d etermine the data direction for the pr oper read (RD) o r w rite (WR) operation

from or to t he selected register inside the AS M.

– Ready Output Signal ( RDY)

The active high ready signal realized as an open drain output suppor ts the interfaces

under different speed requirements. D uring a bus cy cle with a control line RD or WR

becoming active (High to Low transition) the ready signal will be forc ed low to indicate

that this access to an internal register may have to insert wait st ates (not ready state).

After the necessary reaction time of the AS M, it returns to a high level indicating that

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the data are stable and t hat t he bus cycle can be f inis hed by the microprocessor with

WR or RD returning to a high level.

Since the output is only pulling down actively to GND an external pull-up resistor has

to be pr ovided with the rec omm ended value of 2.5 kΩ.

– Interrupt Output Signal (INT0)

The active l ow interrupt (INT0), realized as an open drain output is provided to indicate

that a µP-cell was received or that an error has been detected by the ASM. After

reading the RCR register (at least octet 63) or r esetting the RX -bit (RX = ‘0’, bit 7) in

the command regi ster COR respectively after reading the interrupt status register ISR,

this signal will become high. Since the out put is only pulling down actively to GND an

external pull-up resistor has to be provided with the recommended value of 2.5 kΩ.

– Interrupt Output Signal (INT1)

The active l ow interrupt (INT1), realized as an open drain output is provided to indicate

that a communication cell (HK = 110 and MODR:EINT1 = 1) was received by the

ASM. After reading the RCR register (at least octet 63) or resetting the RX-bit

(RX = ‘0’, bit 7) in the command register COR this signal will become high. Since the

output is only pulling down actively to GND an external pull-up resistor has to be

provided with the recommended value of 2.5 kΩ.

3.4.6 Clo ck and Reset

Figure 16 Clock and Reset Interface

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– Clock Inputs (CL/CL)

The central operating clock is running at up to 208 MHz, which is identical to the

system frequency. It is complementarily fed in via the clock inputs CL and CL

(differential inputs).

Level: Both inputs work at the LVDS levels.

Note: The loss of the operating clock may cause an increase of the power dissipation.

In order to hold this increase low, it is strictly recommended, to supervise the board

clock operation: If the c lock fails, an active Hardware Res et (RES = 0) should be

delivered to the ASM devices concerned.

– Rese t Inpu t Si gn al (R ES ET )

The RESET-signal is fed in via a LVCMOS-compatible input. Whenever it is at the low

state ‘0’ ( GND) and then switched from the low state ‘0’ to the high s tate ‘ 1’, it c auses

a reset of the switch int ernal circuitry:

RE SET = ‘ 0’ act ive (reset of the converte r circu it s)

RESET = ‘0’ →‘1’ active (general reset of the control and clock circuitry )

RESET = ‘1’ inactive (no inf luence)

Figur e 1 7 RE SET Signal

An active HW-reset causes an initi alization of the whole ASM, including all the registers.

The influence of the RESET signal to the serial outputs is shown in Figure 17. During

the active RESET signal the differential outputs are held at constant values. After the

RESET signal becoming inactive an empty cell is sent out at each of the 16 outputs.

During that time the initialization of some internal circuits occurs. In the second cell slot

the first data cells may be transmitted, if any.

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– Software Reset

A Software reset is activated by the µP by setting the SRES-bit of COR to ‘1’. This

action cau ses the reinitialization of all the queues, of the FCL-RAM, MCC-RAM and

the maintenance regis ter MR.

The phase-alignment circuitry of the input lines and the cell synchronism of the

outputs remain unaffected by this operation, as the empty cell generator is act ivated

to permanently t ransmit empty cells as long as the software res et is kept act ive.

As soon as the reinitialization procedure is completed, the software reset is

deactivat ed by the ASM by setting SRES to ‘0’.

3.5 ATM Cell Format

The ASM uses a proprietary 64-octet ATM cell format. It is shown in Figure 18 for

self-routing and in Figure 19 for multic ast cells.

The shaded areas represent bit fields, which are transparent to the ASM, while the

‘open’ fields will be evaluated by the ASM (routing information).

The term ‘external header’ denotes the standardized, 5-octet header of the ATM cell.

The internal header is added by the ASP and comprises 10 octets. A one octet trailer is

appended at the end of the internal cell and c arries a checksum. It is not evaluated by

the AS M, but only by the ASP at the out going side.

Table 1 explains the used header bytes.

The MCRA 19 … 16 bits are not evaluated by the ASM. They are reserved for further

expansion of the number multicast connections.

The auxili ary bits AUX 20 … 31 can be used for routing information in multicast cells. As

some ASMs in the switching network may be programmed to treat the multic ast c el ls as

self-routing cells, these ASMs would be programmed to ‘look’ for routing bits within this

field.

The following two figures show the structure of empty cell (Figure 20) and Protection

Switch Identifier PSI cell (Figure 21).

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Figure 18 Format of Self- routi ng ATM Cell

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Figure 19 Fo rmat of Multicast ATM Cell

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Table 1 Description of U sed Header Fields

Abbr. Bits Meaning Comment

ADI 2 Addre ss identifier To identif y the RA type:

ADI RA field

X0 Routing address

X1 Multicast routing addres s

AUX 12 Auxiliary bits In cas e of DCMC = ‘1’ and EVMCI = ‘0’

in the MODR-r egister, the AUX-bits can

be used as routing address

CLP 1 Cell loss priority 1 = low priority cell ; 0 = high priorit y cell

HK 3 House keeping Cell type ide ntifier

HK Cell type

000 Empty cell

011 Maint enance control cell; not

influenced by output

multiplexer

110 Control cell ; cause a

INT1-reques t instead of an

interrupt INT0

other Standard operation

MCRA 20 Multicast ro uting address MCRA 19 … 16: Not evaluated by the

ASM. MC RA 15 … 0 : Address used for

the multicast look up table ( MLT, external

sync . SCRAM )

P 1 Header parity For internal header (octet 1 … 6), odd

parity

RA 32 Routing address Variable, depending on the initialization

of the ASM

Res 2 Reserved

SSN 4 Switch stage number To mark the A SM in t he diff erent stages;

for normal routing, not using the

µP-output of the ASM, the SSN has to be

set to SSN = 0000B

Sync. 8 Synchr oniz ation octet Cell start identifier with toggle bit (first bit

of transmission), hex-value: 68H/E8H

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Figure 20 Form at of Empty C ell

Octet 7 6 5 4 3 2 1 0 Hex-val.

0 T1101000 68/E8

1 00000001 01

2 00000000 00

3 00000000 00

4 00000000 00

5 00000000 00

6 00000000 00

7 00000000 00

8 00000000 00

9 00000000 00

10 00000000 00

11 00000000 00

12 00000000 00

13 00000001 01

14 00011001 19

15 01101010 6A

61 01101010 :

62 01101010 6A

63 11111001 F9

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Figure 21 Structure of Pro tec tion Switch Identifier Cell

Octet76543210 Hex-val.

0 T1101000 68/E8

1 00000001 01

2 00000000 00

3 00000000 00

4 00000000 00

5 00000000 00

6 00001010 00

7 00000000 00

8 00000000 00

9 00000000 00

10 00000000 00

11 00000000 00

12 00000000 00

13 00000001 01

14 01011000 19

15 01101010 6A

61 01101010 :

62 01101010 6A

63 11111001 F9

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3.6 Examples for System Integration

The ASM can be operated stand-alone as a 16 ×16 switch of 2.5 G bit/s throughput by

just leaving 16 inputs open. Larger switching networks can be built by interconnecting

several ASMs in arrays. Two possible expansion schemes are described in the following,

funnel-type and Banyan networks. Note, however, that many more options ex is t t o build

switching networks using other network types and/or combinations of them (see e.g. the

book of Händel, Schröder, Huber [5] for further study). Due to the flexible routing

header concept the switching net work can be optimized for each appl ication.

3.6.1 Funnel-Type Switching Networks

The simplest funnel-type switching network is obtained by connecting two ASMs in

parallel as shown in Figure 22 They constitute a 32 ×32 switching network. Each

incoming cell is input at both ASMs and each ASM filters out those cells which are

destined for its outputs and discards the other cells. Each line in Figure 22 stands for

16 parallel SLIF lines.

Figure 22 5 Gbit/s Switching Network

The next size of a funnel-type switching network is a 64 ×64 switch realized

with 12 ASM chi ps (see Figure 23).

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Figure 23 10 Gbit/s Switching Net w ork

The switching network of Figure 23 consists of 4 ‘funnels’, each built with 3 chips. The

2 ASMs of the first row have different filter values programmed for each funnel. Their

outputs are grouped as one 16-bundle, i.e. there is only one logical out put. The A SM of

the s econd r ow of each f unnel does the routing evaluation, i. e. it forwards the cells to t he

specified output or output bundle. See Chapter 6.1 for programming details.

The next size of a funnel-type switching network is a 128 ×128 switch realized with

56 ASM chips. It consists of 8 funnels of 7 ASMs with the 128 inputs of all funnels

connected in parallel. Figure 24 shows the f irst of t he 8 f unnels.

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Figure 24 7-Chip Funnel for 20 Gbit /s Switching Network

The following diagram shows possible switch sizes and the required number of

ASM chips for funnel-type switching networks.

The general expressions for funnel-type switching networks with s stages using a

2b×b switching chip are:

Number of funnels = 2s,

Nu mb er o f switch po rt s = b ×2s,

Number of switching chips = (2s–1)×2s.

Note that funne l- typ e switching networks are ‘non-blocking ’. This term is defined in the

following way in this document:

Table 2 Size and Chip Count for Funnel-type Switching Networks

No. of Stages No. of ASMs Switc h Size Switch Throughput [Gbit/s]

1232 × 32 5

21264 × 64 10

356128 × 128 20

4 240 256 × 256 40

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Note: A switching network is non-blocking if all input and output lines have the ATM cell

load L, the load L is not exceeded at any interconnection l ine between ASMs. This

means that any mixt ure of c onnecti ons can be set-up between inputs and out puts

without considering the inter connection lines.

If e.g. in a non-blocking switching network a connection is to be set-up from input j to

output k, it has just to be checked if input j and output k both have enough spare

bandwidth. If t his is the cas e the connection c an be s e t-up and there wi ll be no ov er load

on any of the used interconnection lines.

The non-blocking feature is easily checked for the funnel-type networks. If the output

load of a funnel has the value L, the input load of the last stage has the value L/2, the

input load of the last but one stage has the value L/4 and so on. The traff ic in the funnel

is more and more concentrated.

3.6.2 Banyan Switching Networks

Banyan networks belong to the class of single-path networks, i.e. there is only one s ingle

path from an input to a gi ven output. B anyan network have t he advantage to be less chip

consuming than funnel-type networks, but they are blocking. An implication for the

network control SW is that for Banyan networks it must keep track of the load on all

interconnection link s.

As described above depending on the distribution of connections between inputs and

outputs a new connection may have to be rejected because of an overload on an i nternal

line even if input and out put line have t he required capac ity available. The probability for

such a blocking event is depending on the load of th e network. As shown in a pap er by

Theimer [6] the b locking probability is negligible if the load is below 50 %. This can be

achieved by various means:

• The application itself has low average load. This could be the case e.g. in a LAN

environment, where most of the switch ports are connect ed to PCs. Banyan networks

are especially useful for LANs, as they allow to connect a large number of PCs .

• The traffic load can be reduced by using two switching network planes in the load

sharing mode.

• Another method to reduce the load on the interconnection lines is to use bundles.

This, however, reduces the maximum size of the sw itching network (Figure 26).

Figure 25 shows a generic Banyan netw ork with 3 stages consisting of b ×b switchin g

elements. It cont ains b times the 2-stage sub-network shown in t he frame.

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Figure 25 Gen eric Banyan Network

The 3-s tage switching network built with switching element s of size b ×b has b 3 port s.

Using ASM chips there are tw o possibilities for the b ×b element:

1. Either a single ASM can be used with 16 inputs unconnected giving a switching

element of size 16 ×16 or

2. Pairs of 2 ASMs can be built in a mini-funnel (see Figure 22) giving a switching

element of size or 32 ×32.

3. The non-blocking 10 Gbit/s funnel (Figure 23) can be used, giving b = 64.

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The switch sizes realizable with both possibilities are summarized in the table below

together with the required number of ASMs.

It can be seen that Banyan networks are much more effective than funnel-type

concerning chip count: E .g. with 56 ASMs a funnel-type s witch of size 128 ×128 can be

built, whereas 64 A SM s are required for a 1024 ×1024 Banyan-type switch.

The ASMs in Banyan networks do not need the filter function, but only the routing

functionality. In each stage the ASM chips will be programmed to evaluate different parts

of the rout ing field of the internal cell header.

As mentioned above the in terconnection lines between ASMs in B anyan netwo rks can

be bundled. An example is shown in Figure 26.

Figure 26 40 Gbit/s Banyan Switch wi th Bundles of 2

Each 32 ×32 switching element in Figure 26 consists of a mini-funnel as shown in

Figure 22. The 32 outputs of the switching elemen ts of the first stage a re combined to

16 2-bundles. This reduces the load on the interconnection lines to below 50 %. The

Table 3 Size and ASM Chip Count for Banyan Networks

Switching E lement No. of Stages No. of ASMs Switch Size

1116×16

16 ×16 2 32 256 ×256

3 1768 4096 ×4096

1232×32

32 ×32 2 64 1024 ×1024

3 3072 32768 ×32768

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switching network is still more chip saving than the funnel-type network of the same siz e:

It needs 64 ASMs instead of 240.

3.6.3 Multiplexers/Concentrators

Both funnel- and Banyan-type switching network cores can be expanded by adding

multiplexers to concentrate the incoming traffic. This is especially useful if

subscribers/terminals must be connected t o the switch. These are expected not to use

the available capacity completely all the time. Appropriate concentration allows more

efficient use of the precious switching core. A generic configuration of a switching

network core expanded by multiplexers is shown in Figure 27.

Figure 27 A Switching Network Expanded by Multiplexers

Some of the ports of the switch core in Figure 27 are connected directly to t he swit ching

core. These could be trunk ports (in WAN applications) or server ports (in LAN

applications). The other ports are expanded by multiplexers. Each multiplexer

concentrates traffic from subscribers (WAN) or terminals (LAN). In both cases

applications which are assumed to have low average traffic.

There are three different operation modes for t he ASM to support multiplex ers:

– The input multiplexer is used e.g. to concentrate the traffic of several

subscriber/ter minal ports to one (core) switch port. In this mode t he ASM forwards all

cells to one output bundle.

– The output multiplexer is used for demultiplexing an aggregate cell stream from a

switch core port to different access ports. In this mode the ASM evaluates a part of the

routing field of the internal cell header to determine the out put.

– In split mode one ASM operates as bot h input and output multiplexer. In this mode one

group of inputs is defined to operate in normal mode including filter, routing and

multicast options. Cells coming in at these inputs are forwarded to one output

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(bundle). The cells input at the ot her group of input lines are treated in a special way;

they are forwarded to the out puts using a predefined field of the routing field.

An application example of an ASM in split mode is shown in Figure 28 below. In this

example 12 (subscriber) line cards are multiplexed onto a bundle of 4 SLIF lines. A

bundle has th e advantage that the lo ad management has to consider only one logical

622 Mbit/s equivalent link instead of four 155 Mbit/s equivalent link s.

Inputs 0 … 3 work in MUXIN-mod e, all other inputs in MUX OUT-mode. Inpu ts 16 … 31

are not connected. It can be seen that each line card has a mean bit rate of

622 Mbit/s / 12 = 51.8 Mbit/s to the core – without taking the short path traffic into

account. The ASM allows short path connections from one L IC directly to an oth er LIC,

which do not influence the t raffic to the switch cor e. See Chapter 6.1 for a progr amming

example for a split mode multiplexer.

Figure 28 Single Chip Bidirectional Multiplexer

Note that an ASM could also operate s tand-alone in a configuration a s in Figure 28 by

omitting the lines to the switch core. In such a case it constitutes a 16 ×16 switching

network. Considering the bit rate of roughly 155 Mbit/s for each line, an AT M swit ch with

a total throughput of 2.48 Gbit /s can be realized with only one ASM.

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3.6.4 Multicast Op eration

The multicast function is usable in all modes except the multiplexer mode where al l cells

are forwarded to one output. I f a multicast header is detected by an ASM the MCRA field

of the routing header is used as address to the multicast lookup table. This is an external

RAM of 64 k entries of 17 bits which is init ializ ed by the mic roprocessor. 16 bits of each

entry are associated to the outputs of the ASM (the 17th bit is a parity bit). A cell is

forwarded to those outputs where the corresponding bit is set. Obviously the following

special cases are possible:

– No output bit is set ⇒ the multicast cell is discarded.

– Only one output bit is set ⇒ the c ell is forward ed to one output only as in th e normal

routing cas e.

– All output bits are set ⇒ full broadcast case, the cell is replicated to all outputs.

Note: For a multicast connection the same MCRA must be set-up in the whole switching

network, also in those ASMs where no branch of the mult icast connection passes

through. The reason is that at any t ime an additional branch could be added to a

multicast connection (via signalling). If t he same MCRA would be used for another

connection these two connections could not use the same ASMs. The total

number of multic ast connections in the whole switch is therefore lim ited to 64 k.

In a f unnel-type switching network only the las t stage needs a multicast l ookup table, the

other stages can be programmed to forward multicast cells as normal cells. Thus the

external RAM is only required once per funnel (s ee Figure 32).

Some Notes about Mult icast

Multicast connections requir e a significant amount of ‘work’ t o be set-up, i.e. the s witch

control has to check on all outgoing branches if capacity is available, has to find free

VCIs and load these onto the line cards; also for a 1:n multicast connection n backward

(merger) connections have to be set-up; it is almost the same effort as to set-up

individual one-to-one connections.

Also the OAM (operation, administration and maintenance) functions for one-to-many

connections are still unclear, e.g. in case that the connection fails a flood of backward

error notific ation cells will be produced .

However, not all of the multicast applications do translate into multicast connections on

the ATM layer; e.g. the many-to-many connections in LANs are resolved in ATM LANs

by a single one-t o-many c onnection from the server to the us er s, or as another example

a multi-party video conference does not require m ulticast ATM connections, as none of

the users will have the same picture on the screen; a video conference server will be

used to arrange the picture individually for each part y.

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4 Functiona l B loc k s Desc r iption

4.1 Bit Ph ase Alignmen t

Each of the data inputs is equipped with a Bit Phase A lignment Circuitry. Its main tasks

are to com pensate for both jitter and possible wander of the input data streams and to

align the incoming bit stream to the internal clock of the ASM.

4.2 Cell Detection

The Cell D etection Cir cuits are situated just behind the Phase Alignment B locks. Their

primary function is to identify and check the Synchronization Octet (<T110 1000>,

T = toggle bit), which defines the octet position and the cell start. The result of the check

is used to derive the line s tate.

If only one cell with invalid SYNC-octet occurs, i.e. the following cell has got a valid

SYNC-octet, the cell is passed through. The line errors are reported in the Line Failed

than one cells with invalid SYNC-octet are received the first is accepted the second is

discarded.The second cell also leads to asynchronous state where all cells are

discarded. Transition to synchronous state is achieved after 2 cells with valid

SYNC-octet. The third cell with valid SYNC-oct et is accepted.

The line state is mapped in to the L ine Asynchronous State Register LASR; line errors

are reported in the Line Failed Register LFR, the Line Error Register LER, and the

Interrupt Status Regist er ISR.

4.3 Deactivation of Input Ports

Ports can be deactivated via the Input Online Register IOR. This will discard all cells from

this ports without any header check, but t he line s tat us will s till be reported in LASR and

LER.

4.4 Check of Header Parity Bit

The octets 1 to 6 of the inter nal header are protected by a parity bit P, which is checked

for every cell. If a parity error has been detected, the cell is discarded. The error is

mapped into the Line Failed Regi ster LFR and the Interrupt Status Register ISR:PE.

4.5 Device-internal Cell Parity Byte

All cells are provided with a trailing odd parity byte covering the whole cell except the

Synchronization Octet. The parity generation is done in a byte interleaved way, with

every parity bit ‘i’ covering all the bytes at bit number ‘i’ through out the whole cell.

The parity byte is ch ecked at eac h out put port at the location wher e the data is in octet

format, before the final p/s conversion is done.

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An Internal Parity Error is reported in the Interrupt Status Register ISR:IPE. No further

action can be prov ided to mark this corrupted cell. The c ell will be discarded by the ASP

in downstream direction.

4.6 Empty Cell Removal/Insertion

All Empty Cells from the input ports are discarded. They are identified by the

Housekee ping B its <00 0>. Except the check of the header parity P no other inspection

is done, so t hat all cells with the Housekeeping < 000> are d iscarded independent from

any other cell data.

New Empty Cells are generated for an o utput port, if no other ce ll is available, i.e. the

output queue is empty, or the port is disabled.

Cells with House keeping <000> tha t have be en fed in via t he µP-interface, are t reated

as empty cells and ther efore discarded.

4.7 Output Port Bundling

Output ports can be bundled to make it possible to switch links with higher data rate.

Groups of 2, 4, 8, and all 16 outputs can be configured via the Output Group Register

OGR:OG. Each output port bundle uses one common output queue. The ports send the

cells in a staggered mode, so that the original cell sequence can be recovered by the

input scan algorithm of the following ASM or ASP. For groups of 16 input ports a different

algorithm is used (see Figure 30), and therefore they must be specified in the Mode

4.8 ATM Cell Sequence

Independent from any specified output bundle, the output ports transmit the cells in

staggered mode, i.e. the Cell Starts in the 16 output streams are not simultaneous but

have a fixed delay to each other. The cell sequence starts with port 0. Port 1 transmits

the next cell start 3 octet clocks (= 24 system clocks) delayed i n relati on t o the Cell Start

on port 0. The sequ ence is shown in Figure 29.

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Figure 29 Output Cell Sequence

In the case of port bundling, i.e. a group of ports gets the cells from the same output

queue, these staggered output makes it possible for the next ASM to recover the cell

sequence.

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Figure 30 Linear Input Scan

Figure 30 shows this scan while the input s receive a bundle of 8 and a bundle of 16. It

is easy to see that the scan scrambles the sequence of the bundle of 16, because it does

not comply with the condition 3. For that reason, another scan algorithm is used if a

bundle of 16 is defined via the Mode Register MODR :IG0 or IG1.

The sc an algorithm for bundles of 16 works as follows:

• The input ports are partitioned into 2 sections which can possibly receive bundles of

16, i.e. one group contains the ports 0 to 15, the other 16 to 31.

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• If the scan crosses an input bundle of 16 (change from ‘cell received’ to ‘no cell

available’), the scan leaves the actual section, scans the whole other section, and

continues with the port which has ‘no cell available’ before. Such a jump in the

sequence is possible only in the second half of the section.

• The possibility to jump is not enabled until one complete section has been scanned

and the second section has been started from the beginning.

Note: Pipelining in the implementation can cause that the scan restarts up to 4 ports

before that one where it has left the se ction.

4.9 Routing Ev aluation

The Switching Stage Number SSN(3:0) is compared with the Mode Register

MODR:SSN(3:0). Cells with matching SSN and if necessary matching routing address

are destined f or the local proces sor.

The Housekeeping HK (2:0) is decoded to distinguish E mpty C ells <000>, Maintenance

Control Cells <011>, Control Cells <110>, and the information ‘other’.

If the Address Identif ier ADI(0) is ‘0’, the Routing Address RA (31:0) is compared wit h the

Identification Register IDR:ID(31:0). The result can be masked with the Filter Mask

accept a cell. The Output Group Register OG R:OP TR(4:0) defines a four bit section of

the Routing A ddres s which contains the destination port num ber.

When the split mode is activated with MODR:IS(5:0) = n > 0, the cells from the input

ports (n – 1) … 0 are handled in a different manner: Only RA(5:4) is compared with

ASM_ID(5:4) and without masking, and RA(3:0) is interpreted as destination port

number.

If the Address Identifier ADI(0) is ‘1’, a part of the Routing Address RA(15:0), now

denoted as MultiCast I dentifier MCI(15:0), is used as address for the external M ulticast

Lookup Table MLT, which deliv er s the information about the dest ination port(s).

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4.10 Multicast Handling

The Multicast Lookup Table MLT is an external synchronous RAM with 64 k entries.

Each entry is 16 bits wide plus an odd parity bit. The bit positions 0 to 15 of an entry

denote the out put ports 0 to 15, bit 16 is the parit y. Since t he used external RAM is 18-bit

wide, bit 17 remains unused.

The entries can be written via the Multicast Transfer Register MTR and the Multicast

Address Regist er MCA.

A multicast cell normally has more than one destination port. That does not mean that

any cell copies are existing in t he Central Buffer; eac h accepted cell is writ ten only once.

But the cell location address is copied into the concerned output queues, and so the

location will be read repeatedly.

4.11 Output Queue Fairness Management

Queues with an unlimited num ber of entries have t he disadvantage that a burst of cells

for one output can fill the whole Central Buffer and therefore can block the traffic for the

other queues. For that reason a limit value for each type of queue ( si ngle por t, bundle of

2, 4, 8, or 16 ports) can be set via the Maximum Queue Length Register MQLR. When

the number of entries in a specific queue has reached the limit, this queue will reject all

additional cells. This will discard a normal pt-pt cell. A multicast cell must not be

discarded, if at least one ot her destination queue accept s the entry.

4.12 Cell Insertion via the Processor Interface

Two types of local processors may communicate with the processor interface: A

microprocessor and a protocol chip. Each has an own address space for one Transmit

Cell (TCR1 and TCR2). The processor must not send a Synchronization Octet, but it

must append the internal odd parity byte. The Transmit Cell is inserted into the data

stream via an internal 33rd input port. This port has no check for a Synchronization Octet,

but the complete header evaluation is exercised, so that the cell is treated like a cel l from

any other port.

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4.13 Cell Receiving via the Processor Interface

The ASM has a 17th int ernal output port with an own output queue, which holds the cells

destined for the local processor. The actual c ell from this inter nal port is available in the

Receive Cell R egister RCR . Two cell types are distinguished: A µP-cell is indicated by

an interrupt INT0, and a communication cell (µP-cell with HK = <110>) activates an

in te rru p t I N T1.

4.14 Procedures for System Failures

Overflows

All types of overflows (buffer-, threshold-, queue-, and µP-queue-overflow) forces that

new incoming cells concerned by the overflow are discarded. The different overflow

errors are indic ated in the interrupt stat us register ISR.

Line Faults

The inc oming c ell on eac h input l ine of the ASM is checked on SYNC-/ASYNC-state and

on parity er ror of the internal header . If a S YNC-error occur s, the cell is passed t hr ough.

In case of an ASYNC-error the incoming cells are discarded until the SYNC-status is

reached. In case of a parity error only the affected cell is discarded. All errors are

indicated in the corresponding registers. Output lines cannot be supervis ed by the ASM

itself. This must be done by the follo wing devices (refer to Figure 6).

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5 Register Descriptio n

The main task of the µP-Interface is to handle all the information which has to be

interchanged between the ASM and the exte r nal microprocessor such as:

• Error indications ISR, LASR, LER, LFR

• Input enable and masking ins tructions IMR, IOR

• Address information ILA, OLA/MCA

•µP Commands COR

• Definition of the thresholds PTR, MQLR

• Maintenance instructions MR

• Ope ration modes MO DR, OGR, IDR, FMR, LPSR

• Cell data: transmission TCR0, TCR1

reception RCR

• Multicast data exchange MTR

All the data are exchanged in a bytewise operation.

Note: The access to the

P-registers can only be done with a permanently running

operating clock.

The loss of the operating clock cuts off any access capability.

In all the register operations the µP acts as the master device; this implies the absolute

access prio rity to the µP -Interface whenever it is necessary (asynchronous operation).

5.1 Registers Table

The following section will give an introduction to the register functions. Additional marks

are given for certain functions like hardware reset or default values .

5.1.1 Interrupt Status Register ( Read Only)

Hardware reset value all 0

Software reset value (no change)

ISR ASYNC SYNCE PE CTRLE IPE MLTPE MCMR PCRCV 00H

0000BOVTOVQOVPQOV01

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The Interrupt S tatus Register ISR displays all event s which can cause an

interrupt INT0 to th e µP . If an event sets a bit in the ISR to ‘1’, it remains in

that state until the µP resets the flag. At the same time, an interr upt INT0 is

activated if t he bit is not masked in t he Interrupt Mask Register I MR and the

interrupt is not already active.

The µP read operation onto the ISR (00H, 01H) has no inf luence to the

present status of the ISR:A µP write access onto ISR (00H, 01H) with the

relevant bit set to ‘1’ clears the interrupt status bit. A write of ‘0’ has no

influence to an int errupt status bit. If the interrupt li ne INT0 has been ac tive,

the reset of the ISR flags force also the deactivation of the interrupt line.

Events that occur during the ‘clear bit ’ access of the µP are not lost due to

an internal shadow register which is not accessible for the µP. These events

are passed through to the IS R after the µP write access is finished.

Since in the res et phase all lines have been asynchronous for a t ime,

ASYNC will be ‘1’ and the µP should at first write the cor r esponding flag to

‘1’ to reset it.

ASYNC Asyn c h ron ou s St at e

A line is defi ned to be asynchronous, when two invalid Synchronization

Octets are detected successively. In that situation ASYNC is set if the very

line is not masked in the Inpu t On-line Register IOR. So AS YNC indicates

that one or more non-masked lines are asynchronous. The concerned input

lines can be read from the Line Asynchronous State Regist er LASR. During

the ASYNC-state of an input line incoming cells are di scarded.

SYNCE Synchronization Error

Has the same function as ASYNC, but it is s et if only one inv alid

Synchronization Octet is d etected and the next Synchronization Octet is

correct. So if a Synchronization Octet is corrupted, either SYNCE or ASYNC

is set. A SYNC-er ror on a line is only set if t he very line is not masked in the

Input Online Register IO R.

Cells with invalid Synchronization Octet causing an SYNC-error are passed

through. The concerned input lines can be read from the Line Asynchronous

State Register LASR. For test purposes, sync. errors can be generated by

MR:IVSYNC = 1 of the previous ASM.

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PE Parity Error

Result of the internal cell header parit y check of all i nput ports. All incoming

cells are checked for correct parity bit P within the internal cell header.

PE = 1 indicates that a parity bit on at l east one of t he active input lines was

found to be invalid. The cel ls with a parity error are discarded without further

evaluation.

The parit y checks are only done for lines which are not in the asynchronous

state; results from asynchronous lines are masked out.

A parity error on a line is only set if the very line is not masked in the I nput

Online Register IOR.

CTRLE Control Error

CTRLE indicates an internal hardware error in the addres s administration.

The 300 addresses pointing to all entries of th e Central Buffer are

permanent ly exchanged between t he Free Cell Lis t RAM (FCL) and one or

more output queues in t he common Queue RAM . The rea dout count is

stored in the Multicast Count RAM (MCC). All entries in these three RAMs

are protected by an additional parity bit. Every stated error is mapped as a

C on tro l Er ror C T RL E.

When a pari ty error in a Queue RAM occurs, the corresponding address will

be erased; this means that the entry under this address in the Central Buffer

allocated to this queue is lost. Since the address is not returned into the Free

Cell List, the num ber of available addr esses decreases. If the RAM has a

permanent failure, after a short time no addr esses will be left , resulting in a

Buffer Overflow BOV.

For test purposes a Control Error can be generated by setting INVM, INVQ,

or INVP in the Maintenance Register MR.

IPE Internal Parity Error

Indicates a parity error of the internal cell parity octet. That means that the

cell has been corrupted in the path between S/P converter, Central Buffer,

and P/S con ver t er.

For test purpo ses an IPE can be generated via appropriate test cells.

MLTPE Multicast Lookup Table Parity Error

Indicates a parity error in the external Multicast Lookup Table (MLT) RAM.

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MCMR Multicast Misrouting

MCMR indicates that a m ulticast cell is detected which is not destined for

the ASM, i.e. the multicast operat ion is disabled in t he command register

(DCMC = 1), so that the control logic does not support m ulticast. The

multicast cell will be discarded.

PCRCV µP -Cell in Receive Buff er

Indicates that a µP-cell is available in the receive buffer f or readout. When

the ASM sets PCRCV = 1, the RX-bit in the comm and register COR is

activated at the sam e time. After reading both bytes of IS R, PCRCV is

cleared to 0 aut omatically. The RX must be cleared independent from

PCRCV by the µP. The RX- bit can be c leared by reading out of the last cell

octet or by overwriting the RX- bit wit h the µP. After that the ASM will m ove

the next cell (if available) into the receive buffer and the whole process starts

again.

BOV Buffer Overflow

Indicates that a cell has been dis carded because no free cell entry is

available. In practice, it means that 296 to 300 cells are stored in the Central

Buffer. The uncertainty is due t o the fact that free entry addresses have

some clock cycles delay before they can be used again.

Note: A Control Error CTRLE (see above) may have decreased the number of

available cell entries.

TOV Threshold Overflow

Indicates that the number of cells in the Central Buf fer exceeds (or has

exceeded for a time) the limit defined in the Priority Threshold Register PTR.

In the T hreshold Overflow condition all incoming low-priority cells (with bit

CLP = 1 in the external cell header) are discarded.

QOV Queue Overflow

Indicates that a cell has been dis carded because no free queue entry is

available in the corresponding output queue. The common limit for each

type of output queue, except of the µP-queue, is defined in the Maximum

Queue Length Register MQL.

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5.1.2 Interrupt Mask Register (W rite)

Hardware reset value all 1

Software reset value (no change)

Readable for test purposes.

PQOV Microp rocessor Queue Overflow

Indicates that an inco ming µP/communication cell has been discar ded,

because the number of stored µP/communication cells has reached the limit

value for the Maximum Proc essor Queue Length Register PQLR.

IMR MASYNC MSYNCE MPE MCTRLE MIPE MMLTPE MMCMR 0 02H

0 0 0 0 MBOV MTOV MQOV MPQOV 03H

The Interrupt Status Register ISR can be masked by the IMR, by setting the

corresponding bit(s) of IMR to 1. That means that only the interrupt for the

masked ISR-bit is deacti vated. The actual stat us of the ISR-bit can be read

by the µP independent from the mask register.

Attention:

The PCRCV-bi t can not be masked, to prevent the bl ocking of the

µP-queue for commu nication cells because of not processed cells by

the µP.

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5.1.3 Line Asynchronous St ate Register (Read Only)

Hardware reset val ue undefined, see below

Software reset v alue (no change)

5.1.4 Input Line Address (Write)

Hardware reset val ue all 0

Software reset v alue (no change)

Readable for test purposes.

LASR 7004

15 8 05H

24 16 06H

31 25 07H

Bit i of LASR is assigned to the ASM-input line number i (0 i 31).

A line is defined to be async hronous , when two invalid Synchronization

Octets are det ected successively. An input line is marked as asynchronous

by setting the line-individual ASYNC bit in LASR. In addition the subsequent

parity error indication of the int ernal header is m asked.

During t he ASYNC- state of an input line incoming cells are discarded.

The content of the Input Online Register IOR has no influence for LASR.

The LASR indicates the actual status of all input line s, i.e. t he register is

actualized continuously by the ASM. Every time t he µP reads the register, it

gets the present status of the input lines .

74 0

ILA unused ILA(4:0) 08H

ILA defines the input line whose state can be observed in LASYNC,

LSYNCE, and LPE in the Line Error Register LER. Value Range 0 to 31.

Note: A change of ILA does not change the values of LER automatically. LER still

shows the state of the old ILA adjustment. Therefore after a change the

µP

should firs t read LSR to reset it .

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5.1.5 Line Error Register (Read Only)

Hardware reset value undefined

Software reset value (no change)

730

LER unused LSE LASYN LSYNC LPE 09H

The µP read operation resets the accessed byte to all 0.

LSE Line Sam ple Error

Indicates too much jit ter in t he alignment unit of the input specified in the

Input Line Address Register ILA.

LASYN Line Asynchronous State

Shows the state of the line specified in the Input Line Address Register ILA.

The line is defined to be asynchronous (LASYNC = 1), when two invalid

Synchronization Octets are detected successively. The content of the Input

Online Register IOR has no influence for LASYNC.

LSYNC Line Synchronization Error

Has the same function as LASYNC, but it is set (LSYNC = 1) if only one

invalid Synchronization Octet is detected and the next S ynchronization

Octet is correct. So if a Synchronizati on Octet is corrupted, either LSYNC or

LASYNC is set. If LSYNC=1 and LASYN=0 the data transfer on the

respective input is undisturbed.

LPE Line Parity Error

Result of the par ity check of the line, specified in the Input Line A ddres s

parity bit P in the internal cell header. LPE = 1 indicates that a parity error

was found on that line. This check is only evaluated if the line is in the

synchronous state.

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5.1.6 Li ne Failed Register (Read On ly)

Hardware reset val ue undefined, see below

Software reset v alue (no change)

LFR 700A

15 8 0BH

23 16 0CH

31 24 0DH

unused 32 0EH

The µP read operation reset s the acc es sed byte to all 0.

Bit i of the LFR represents the s tate of the input line i. If either a

Synchronization Error, Asynchronous Line State, or Parity Error is detected,

the failure is indicat ed at the appropriate bit position. If IOR disables a line,

parity errors from this line are als o masked.

Since in the rese t phase all lines have been asynchronous for a tim e, LFR

will be ‘all 1’ and the µP should at first read all bytes of LFR to reset it.

Bit 32 is used for the ASM internal µP input port indicates only parity bit

errors.

Note: Events PE, SYNCE, ASYNC that occur during read of LFR may cause loss of

infor mation as the line information is r eset before the interrupt proc edure is able

to process the new error.

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5.1.7 Input Online Register (Write)

Hardware reset value all 1

Software reset value (no change)

Readable for test purposes.

5.1.8 Command Register (Read/Write)

Hardware reset value all 0 ex cept RX=1

Software reset value (no change)

IOR 700F

15 8 10H

23 16 11H

31 24 12H

Bit i of the Input Online Regist er IOR defines the state of the input line i.

Bit i = 1 forces l ine i to the onl ine state. Bit i = 0 switches the input offline, i. e.

all cells from this line are discarded and all er rors are masked within the

Interrupt Status Register ISR and have no influence to PE, ASYNC, and

SYNC E. However, the stat us can be observed in the LASR, LFR and LER

(only SYNC/ASYNC-state).

COR RX TX1 TX0 LPSC WMLT RMLT MCINI SRES 13H

The required operation is initialized by writing a 1 to the corresponding

command bit. After the operat ion has been completed, the ASM resets that

bit to 0.

Note: RX has a different function: It is set by the ASM and reset by the

P or by the

ASM.

The ASM needs 76 octet clocks at maximum t o insert a communication/test

cell from the transmit buffer i nto the data st ream and t her efore to clear TX1/

TX0 and to accept new cells.

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RX Receive µP/Communication Cell

Indicates that a µP/communication cell is availabl e in the receive buf fer for

readout. When the ASM sets RX, the following actions are done depending

on the configuration of the ASM and the HK-bits in t he internal header of the

cell:

1. HK <2:0> of the cell header = 001

PCRCV in t he Interrupt Status Register ISR is set to 1, so that

ASM activates the interrupt line INT 0

2. HK <2:0> of the cell header = 001 and MO DR:EINT1 = 0

PCRCV in t he Interrupt Status Register ISR is set to 1, so that

ASM activates the interrupt line INT 0

3. HK <2:0> of the cell header = 011 and MO DR:EINT1 = 1

ASM activates the interrupt line INT 1

With the readout of the last cell octet, RX is clea red au toma tica lly. Af ter

uncompleted cell readout, RX must be cleared by the µP. After that the ASM

will move the next cell (if ava ilable) into the receive buff er and the whole

process starts a gain.

Note: A read access to the Receive Cell Register RCR is only possible if RX=0,

otherwise the data is invalid.

TX1 Transmit Communication Cell

The command TX1 = 1 forces the ASM to copy the communication cell from

the transmit buffer TCR1 into the Central Buffer, i.e. to insert it int o the data

path. With the write operation of the last cell oct et in TCR1 the bit TX1 is set

automatically. When t his operation is performed and the tr ansmit buffer is

available for th e next communication cell, TX1 is cleared.

The ASM needs 76 octet clocks at maximum to insert a communication cell

from the transmi t buffer into the data stream. Duri ng that time no further cell

can be in sert e d.

TX0 Transmit µP-Cell

The command TX0 = 1 forces the A SM to copy a µP-cell from th e tran smit

buffer TCR0 int o the Central Buffer, i.e. to insert it into the data path. With

the write operation of the last cell octet in TCR0 the bit TX0 is set

automatically. When t his operation is performed and the tr ansmit buffer is

available for th e next µP- cell , TX0 is c leared.

The ASM needs 76 octet clocks at max imum to insert a µP-cell from the

transmit buffer in to the data stream . During that time no fur ther cell can be

inserted.

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LPSC LIC Protection Swit ch Change

This command (LRSC = 1) forces the ASM to accept the adjustments made

in LIC Protection Swit ch Register LPSR. Previously the data has to be

written into t he LPSR.

The releas e of the LPSR forces additionally the output of one Prot ection

Switch Identifier cell (PSI-cell) on every output port, whose configuration has

been changed.

After the operation is done, t he ASM clears LPSC to 0.

WMLT Write Multicast Lookup Table (MC-RAM)

Write command bit (WMLT = 1), requesting a writ e access to the MC-RAM.

Previously the address has to be written into the Multicast Address Register

MCA , and the appropriate data in to the Multicast Transfer Register MTR.

When the operation is done, the ASM clears WMLT to 0. That may not be

immediately, because the ASM m ust wait for a cycle w here the MLT is no t

in use.

RMLT Read Multicast Lookup Table (MC-RAM)

Read command bit (RMLT = 1), requesting a read access to the MC-RAM.

Previously the address has to be written into the Multicast Address Register

MCA.

When the data is available in the Multicast Transfer Register MTR, the ASM

clears RMLT to 0. That may not be immediately, because the ASM must wait

for a cycle where the MLT is not in use.

MCINI M ulticast RAM Initialization

This command (MCINI = 1) forces the ASM to initialize the whole ext ernal

Multicast Lookup Table RAM (MC-RAM) with 0. When the operation is done,

the AS M cl ea rs M C INI .

Note: A fter HW -reset the connected Multicast RAM is not initialized.

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5.1.9 Priority Threshold Register (Write)

Hardware reset val ue 255D = FFH threshold value = 2 × PTR = 510 (no threshold)

Software reset v alue (no change)

Readable for test purposes.

SRES Software Reset

The Software Reset (SRES = 1) initializes the F ree Cell List, Multicast

Count RAM, Output Queue RA Ms, and the Operation and Maintenance

Multicast Lookup Table or the input/output cell synchronism, remain

unchanged. After this initialization is do ne, SRES is cleared (SRES = 0).

PTR PTR(7:0) 14H

The Priority T hreshold defines a li mit for the acceptance of low-priority cells.

Low-priority cells are defined by an external cell header with bit CLP = 1. As

long as the number of cells stored in t he Central Buffer ex c eeds the

threshold value, low-priority cells from the inputs are rejected. The threshold

value used for the comparison in the ASM results in the multiplic ation of the

Priority Threshold Register va lue by 2. So it is possible to define only even

threshold values. Values over 300D (PTR = 150D) exceed the Central Buffer

capability and therefore define no limit.

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5.1.10 Maximum Queue Length Register (Write)

Hardware reset value

MQLx(7:0) = 255D=FF

H queue length = 2 × MQLx = 510 (no threshold)

x = 1, 2, 4, 8

Software reset value (no change)

Readable for test purposes.

MQLR MQL1(7:0) 15H

MQL2(7:0) 16H

MQL4(7:0) 17H

MQL8(7:0) 18H

The Maximum Queue Length MQL defines a queue lengt h limit for each

type of output queue. MQL1(7:0) defines the queue limit for bundles of 1,

MQL2(7:0) the queue limit for bundles of 2, MQL4(7:0) for bundles of 4 and

MQL8(7:0) for bundles of 8 and 16. If the number of cel l loc ations stor ed in

a queue exceeds the threshold value, a QOV-error is indic ated and the cell

is not stor ed in this queue. The t hr eshold value used for the comparison in

the ASM results in th e multiplication of the Maximum Queue Length value

by 2. So it is possible to define only even threshold values.

The following values define the maximum limits for the various bundle sizes.

All values exceeding the maximum queue length are limited to the maximum

value.

MQL1(7:0) = 44D = 2C H = max. queue length from 88D

MQL2(7:0) = 88D = 58 H = max. queue length fr om 176D

MQL4(7:0) = 150D = 96 H = max. queue length from 300D

MQL8(7:0) = 150D = 96 H = max. queue length from 300D

Queue length values over 88D for bundles of 1 and 176D for bundles of 2

exceeds the capacity of the output queues. The queue length value over

300D for bundles of 4, 8 and 16 exceeds t he Central Buffer capability and

therefore define no lim it.

Note: MQL may be changed to smaller lim its only if t he actual amount of queue entries

is smaller t han the new limit to prevent malfunctions.

Note: M QL is not valid for the

P-queue to define a limit (see PQLR).

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5.1.11 Processor Queue Length Registe r (Read/Write)

Hardware reset val ue 255D=FF

Software reset v alue (no change)

5.1.12 Multicast Transfer Regis ter ( R e a d/Write)

Hardware reset val ue all 0

Software reset v alue (no change)

PQLR PQLR(7:0) 19H

The Processor Queue Length Register defines a limit for the acceptance of

the output µP queue. If the number of µP cells stored in t he Central Buffer

exceeds the threshold value, subsequent µP cells are discarded and PQOV

in the Int errupt Status Register is set.

The threshold value used for the com parison by the ASM results in the

multiplication of PQLR(7:0) by 2. Thus only even th resholds can be set.

Thresholds beyond 304D (PQLR(7:0)=152D) exceed the Central B uff er

Capacity and therefore define no limit.

Note: If the threshold is changed during the overflow of this queue the new limit will

come into ef fect after tr ansfer of one cell into the data s tream.

MTR Data(7:0) 1AH

Data(15:8) 1BH

The MTR is a data register f or the Multicast Lookup Table (MLT) RAM read/

write-access. The RAM address is defined in the Multicast Address Register

(MCA). Read or wr ite access is started with RMLT or WMLT in the

Command Register COR. If both are set, the read access has priority over

the write acc ess.

Read Access to MLT

• Wri t e ML T add re ss to MC A (1AH/1BH).

• Set RMLT = 1 in the Command Register COR (12H, bit 2).

• Wait for RMLT = 0.

• Read data from MTR.

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5.1.13 Output Line Address/ Multicast Address Register (Write)

Hardware reset value all 0

Software reset value (no change)

Readable for test purposes.

Write Access to M LT

• Wri te MLT addre s s to MC A (1 AH/1BH).

• Wri te data to MTR ( 18H, 19H).

• Set WMLT = 1 in the Command Register COR (12H, bit 3).

• Operation is performed when WMLT = 0.

OLA/MCA MCA(7:0) or OLA(3:0) 1CH

MCA(15:8) 1DH

Usage 1: OLA(3:0) defines the output line to be provided with an invalid

Synchronization Octet by setting IVSY NC in the Command Regis ter COR.

Used for test purposes. Value range is 0 to 15. Outpu t grouping does not

influence the function.

Usage 2: MCA(15:0) defines the RAM address to be used for µP read/write

access to the Multicast Lookup Table (MLT). The data to be transferred will

be placed into the Multicast Transfer Register M T R.

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5.1.14 Maintenance Register (Write)

Hardware reset val ue all 0

Software reset v alue address 1EH, bi t (5 … 1) = 0

other no change

Readable for test purposes.

MR 0 IVINP IVSYNC IVMLTP IVMCCP IVQRP IVFCP DPQ 1EH

0 0 0 DPA DOS SWPQ AANIC AAC 1FH

0 0 0 0 STCO(3:0) 20H

0 0 0 0 STFO(3:0) 21H

IVINP Invalidate Input Ports

This function (IV INP = 1) pe rmits the test of the asynchronous line

state detection. It falsifies the comparison values for the

synchronization octet of all input s as long as IVINP is set. For the

test IVINP must be set for at least 128 octet clocks.

IVSYNC Invalidate Sync Octet

This function (IV SYNC = 1) permits the test of the synchronization

error detection in t he input unit of a subsequent ASM or ASP chip.

It corrupts the toggle bit T i n t he synchronization octet ‘T110 1000’ .

The output line which shall be provided with this invalid

synchronization octet is specified in the Output Line Address

IVSYNC is cleared (IVSY NC = 0) by the ASM.

IVMLTP I nvalidate Multicast Lookup Table Parity

Device test f unction: When IVMLTP = 1, the parity bit of the

Multicast Lookup Table is inverted, causing a Multicast Lookup

Table Parity Error MLTPE in the Interrupt Status Register ISR. After

one parity bi t was corrupted, IV MCCP is clear ed (IVMCCP = 0) by

the ASM.

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IVMCCP Invalidate Multicast Count Parity

Device test function: When IVMCCP = 1, the parity bit of the

Multicast Count RAM is inverted, causing a Control Error in t he

Interrupt S tatus Register ISR. After one parity bit was corrupted,

IVMCCP is cleared (IVMCCP = 0) by the ASM.

IVQRP Invalidate Queue RAM Parity

Device test function: When INVQ = 1, the parity bit of the parity

checker obser ving the Output Queue RAM bus is inv erted, causing

an immediate Control Err or CTRLE in the I nterrupt Status Register

ISR. After one parity bit was c or r upted, IVQRP is cleared

(IVQ RP = 0 ) by the AS M.

IVFCP Invalidate Free Cells List Parit y

Device test function: When INVP = 1, t he parity bit of one Free Cell

List input is inverted, causing a Control Error CTRLE in the I nterr upt

Status Register ISR after the invalidat ed address has traversed the

Free Cell List FIFO. This test function works only with data cells at

the ASM inputs , not with empty cells. After one parity bit was

corrupted, IVFC P is cleare d (IVFCP = 0 ) by the ASM .

DPQ Disable Readout of µP-Queue

Device test function: When DPQ = 1, the readout of the µP-queue

entries is disabled; no int errupt is generated. Used to test the

Processor Queue Overflow PQOV in the Interrupt Status Register

ISR.

DPA Disable Phase Alignment

Device test function: When DPA = 1, t he phase alignment unit

works with a f ixed clock phase and therefore in a synchronous

manner.

DOS Disable Overscan

Device test function: When DOS = 1, the input scan is set to a fixed

relation to t he output scan. The scan sequence is <output0, input0,

input1, output1, input2, input3, …, output15, input30, input31, µP

output, none, none, µP- input, 12 ×none>.

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SWPQ Switch all Ac c epted Cells to the µP-Queue

Device test function: When SWPQ = 1, the cell destination unit is

disabled. All incoming cells ar e handled according to the initializ ed

operation mode. If the cell i s accepted by the cell acceptance unit,

the cell is routed to the µP-queue independent from any specified

output port.

This function can be combined with the AAC- or AANIC-bit.

AANIC Accept all non E mp ty Cells

Device test function: When AANIC = 1, all incoming data with

correct synchronization oct et from every ac tivated port ex c ept of

empty cells will be accepted. These cells wil l be routed according to

the initialized operation mode or to the µP output queue specified

by the RPQ-bit. The AANIC-bit will be disabled by the AAC-bit.

AAC Accept all Cells

Device test function: When AAC = 1, the cell acceptance unit is

disabled. All incoming cells with correct s ynchronization octet f r om

every port will be routed acc ording to the initialized operation mode

or to the µP out put queue i f specified by SWPQ. The enabled AAC-

bit disables AANIC-bit.

STCO(3:0) Select Test Cont rol Output

Device debugging function only: Reset value should not be

changed in normal operation.

STFO(3:0) Tes t Output Sel e ct

Device debugging function: Reset value should n ot be changed in

normal operation.

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5.1.15 Phase Ali gn Test Regi ster (Read)

Hardware reset value undefined

Software reset value (no change)

5.1.1 6 Free Cells Count Reg is ter ( R e a d/Write)

Hardware reset value 1001 100 0B=152

D =98

Software reset value (no change)

PATR PATR(7:0) 22H

Device test function only. Shows the current edge distribution of the input

specified by the I nput Line Address Register ILA .

FCNT FCNT(7:0) 23H

FCNT can be used for st atistical purposes. It has to be multiplied by 2 t o

obtain the number of free cells in the Central Buffer. The smallest num ber

since t he last read of FCNT is stored. After a read access the register is

loaded with the reset value 152D.

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5.1.17 Version Code Register (R ead )

Hardware reset val ue address 24H=2F

address 25H = D0H

address 26H = 0BH

address 27H = 0BH

Software reset v alue (no change)

The struc ture of the version code regis ter i s :

VERCR VERC(7:0) 24H

VERC(15:8) 25H

VERC(23:16) 26H

VERC(31:24) 27H

VERC(31:0) V ersion Code

The ver si on code of the ASM is identically to the boundary scan

identity code register and can be r ead out via the µP-interf ac e. The

version code register contains information about manufacturer,

ASIC number and version number.

Bit 31 … 28 Bit 27 … 12 Bit 11 … 1 Bit 0

Version number ASIC number Manufacturer

number 1

0000 1011 0000 1011 1101 0000 0010 111 1

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5.1.18 Mode Register (Write)

Hardware reset value address 28H = all 0 except of SSN(3:0) = 0 001

addr ess 29H = all 0

addr ess 2AH = all 1 except ACCEL = 0

Software reset value (no change)

Readable for test purposes.

MODR 0 0 IG1 IG0 SSN(3:0) 28H

0 AOPC IS(5:0) 29H

0 0 EVMCP DCMC EVMCI EVMCM ACCEL APCEL 2AH

IG1 In p ut Groupi ng 1

IG1 = 1 forc es the input scan unit to handle t he inputs 16 to 31 as a

bundle; that means that the cell sequence within the bundle remains

unchanged.

IG0 In p ut Groupi ng 0

IG0 = 1 forces the input scan unit to handle the inputs 0 to 15 as a

bundle; that means that the cell sequence within the bundle remains

unchanged.

SSN(3:0) Switch Level Stage Number

SSN allows to mark every AS M in a funnel st ructure with a specific

identification, making it possible to send a µP/communi cation cell to

one specific ASM (see Figure 33).

µP/communication cells are accepted only if SSN( 3:0) and t he

routing address is equal to the SSN and the val id routing address in

the intern al cell header.

The address comparison is done using the Filter Mask register

FMR.

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AOPC Accept Only Microprocessor Cells

When AOPC = 1, the cell acceptance unit accepts only

microprocessor cells identified by the correct switching stage

number SSN and by the valid routing address (depends on the

operation mode of t he ASM). All other incoming cells are discarded.

IS(5:0) Input Select for Split Oper ation Mode (NORMAL/SPLIT-mode)

Defines the t hreshold for normal and split mode handling of the

inputs:

32D … 63DFixed r outing evaluation for all inputs: RA(3:0) defines

the output

0 Normal routing evaluation for all inputs (default):

Position of routing bits determined by OPTR(4:0)

(32 > n > 0) Split mode: Normal routing evaluation for inputs

31 … n, fixed routing evaluation for inputs (n – 1) … 0

EVMCP Ev aluate Multicast Parity

As long as EVMCP = 1 the control logic is able to evaluate the parity

bit in the Mul ticast Look-up Table (M C-RA M). If a multicast look-up

table parity error MLTPE occurs this error is indicated in

ISR:MLTPE. In case of E VMCP = 0 the parity evaluation of the

ASM is disabled. Then a 16-bit wide MC-RAM can be connected to

the ASM (e.g. 64 k ×16 bit).

DCMC Discard Multicast

As long as DCMC = 1, the c ontrol logic does not support multicast

header types. All m ulticast cells will be dis carded and the MCMR-

flag in the I nterrupt Status Register ISR will be set. DCMC can only

be changed by the µP or with a Hardwar e Reset. The DCMC-bit is

independent from the value of EVMCI, i.e. the evaluation of the

DCMC-bit is done in the ASM previous to the EVMCI ev aluation.

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EVMCI Evaluate Multicast Identif ier

As long a s EVMCI = 1 the control logic is able to identify incoming

multicast cells by the ADI(0) = 1 in the internal routi ng header. In

case of EVMCI = 0, the ADI(0) bit is masked by the ASM. Thus, the

ASM treats incoming multicast cell as self-routing cells. The

evaluation of EVMCI can only be done if DCMC = 0 (see above).

EVMCM Evaluate Multicast Identif ier for Split Mode

This bit is identical t o the EVMCI bi t described above, except that it

applies to the speci al inputs with fixed routing evaluation in s plit

mode. The other, normal inputs of the split m ode operation mode

are controlled by the EVMCI bit. As long as EVMCM = 1 the control

logi c is abl e to i dentify incoming mult icast cells by ADI(0) = 1 in the

internal rout ing header. In case of EVMCI = 0 the cells are trea ted

as self-r outing cells.

ACCEL Accept Control Cells

APCEL Accep t µP-Cells

These two bit s control the ac ceptance of µP and c ontrol cells and

which int errupt line is activated at t he receptio n of these cells.

Control cells are cel ls destined to the receive buffer of the ASM (i.e.

they have mat ching SSN and the routing address RA(31:0)

matches the ID(31:0) after masking by FMR(31:0)) and the

housekeeping field in the cell header has the value HK = 110.

µP-cells denote cells which are destined to the receive buffer of the

ASM but have any ot her housekeeping value.

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5.1.19 Output Group Register (Write)

Hardware reset val ue all 0

Software reset v alue (no change)

Readable for test purposes.

Table 4 µP/Control Cell Handling

ACCEL APCEL HK Comment

00Don’t care µP and control cells are discarded, no

interrupts are activated.

01HK ≠ 110 µP-cells activate INT0.

0 1 HK = 110 Control cell s activate INT0.

10HK ≠ 110 µP-cells are discarded.

1 0 HK = 110 Control cell s activate INT1.

11HK ≠ 110 µP-cells activate INT0.

1 1 HK = 110 Control c ells activate I NT1.

OGR OPE(7:0) 2BH

OPE(15:8) 2CH

OG(7:0) 2DH

CBC OG(14:8) 2EH

0 0 0 OPTR(4:0) 2FH

OPE(15:0) Output Port Enable

OPE enables the output port i belonging to the bit position i in the

any output group. An overflow of the corresponding output queue

can be reached by disable of all belonging output ports. Further

incoming cells are discarded because of the queue overflow.

OPE(15:0) = all 0 can be used to test the Buffer Overflow BOV in

the Interrupt St atus Register ISR.

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CBC Change Bundle Configuration

This com m and (CBC = 1) forc es the ASM to disable the inputs of

the out put queue whi ch shall be c hanged. Thus, all affected output

queues run empty. After t hat, the new configuration is taken over by

the ASM, t he inputs of t he output queues are reactiv ated and CBC

is cl eared by the ASM (CBC = 0).

OG(14:0) Output Grouping

OG enables grouping of adjacent outputs wit h one commonly us ed

output queue per group.

All 0 No output grouping (default)

Bundle of 2 po rts:

OG(0) = 1 Grouping of output port s (1:0)

OG(1) = 1 Grouping of output port s (3:2)

...

OG(7) = 1 Grouping of output port s (15:14)

Bundle of 4 po rts:

OG(8) = 1 Grouping of output port s (3:0)

OG(9) = 1 Grouping of output port s (7:4)

...

OG(11) = 1 Grouping of output port s (15:12)

Bundle of 8 po rts:

OG(12) = 1 Grouping of output port s (7:0)

OG(13) = 1 Grouping of output port s (15:8)

Bundle of 16 p orts:

OG(14) = 1 Grouping of output port s (15:0)

Bits s et for a higher bundle overwrites all aff ected bits of lower

bundles, e.g. the bit OG(12) = 1 overwrites automatically the bit s

OG(9:8) and OG(3:0).

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For the following examples the nomenclature is:

1 = n-bundle enabled (n = 2, 4, 8 or 16)

0 = n-bundle disabled (n = 2, 4, 8 or 16)

x = don’t care, i.e. these bits can set to ’1’ but the setting has no effect on enabling

bundles, as the corresponding output ports are meanwhile used by present enabled

bundle(s) which are higher bundles (e.g. example 1 below : OG(11) is don’t care

because this 4-bundle uses the output ports 15-12 which are already used by the 8-

bundle; a 8-bundle is a higher bundle than a 4-bundle)

Exa m p le 1 :

Setting of O G(14:0): 010 xx00 xxxx 0001

(15:8): 8-bundle of output ports 15-8 due to ’1’ of OG(13)

(1:0): 2-bundle of output ports 1 and 0 due to ’1’ of O G(0)

76543210

15-14 13-12 11 -10 9-8 7-6 5- 4 3-2 1-0 Output ports

Bundle of 2 ports

14 13 12 11 10 9 8

15-0 15-8 7- 0 15-12 11-8 7-4 3-0 Output ports

Bundle of 16

ports Bundle of 8

ports Bundle of 4 ports

Table 5 Grouping of t he Out put Ports Corresponding to Content of OG(14:0)

port1514131211109876543210

(15:8) (1:0)

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Exampl e 2 :

Setting of OG(14:0): 000 0010 1000 xx00

(15:14): 2-bundle of output ports 15 and 14 due to ’1’ of OG(7)

(7:4): 4-bundle of output ports 7-4 due to ’1’ of OG(9)

Exampl e 3 :

Se tti ng of OG(14:0): 1xx xxxx xxx x xxx x

(15:0): 16-bundle of output ports 15-0 due to ’1’ of OG(14)

Table 6 Grouping of the Output Ports Corresponding to Content of OG(14:0)

port1514131211109876543210

(15:14) (7:4)

Table 7 Grouping of the Output Ports Corresponding to Content of OG(14:0)

port1514131211109876543210

(15:0)

OPTR(4:0) Output Pointer

OPN(4:0) defines a four bit output port wi ndow within the 32-bit

routing addres s of the inter nal cell. The value range is 0 … 28D.

Values fr om 29 … 31D are not allowed.

The pointer indica tes the least significant bit of the four bit word.

Cells are routed to the output port decoded out of the four bits. If the

output port belongs t o an output group defined in OPG(14:0), the

cells are routed to thi s output group.

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5.1.20 Identification Register (Write)

Hardware reset val ue all 0

Software reset v alue (no change)

Readable for test purposes.

IDR ID(7:0) 30H

ID(15:8) 31H

ID(23:16) 32H

ID(31:24) 33H

ID(31:0) ASM IDentificati on

ID(31:0) is used to distinguish between different ASMs connected

to the same inputs sources.

Cells are accepted if the valid bits within ID (31:0) are equal to the

valid routi ng address bits RA(31:0) in t he cell header . The valid bits

are defined by t he filter mask register FM (31:0) (see below).

In case of mult icast, the higher word of the Identification Register

ID(31:16) can be us ed for evaluatio n of t he routing address

RA(31:16), for M ulticast cells renamed as AUX.

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5.1.21 Filter Mask Register (Write)

Hardware reset value all 0

Software reset value (no change)

Readable for test purposes.

FMR FM(7:0) 34H

FM(15:8) 35H

FM(23:16) 36H

FM(31:24) 37H

FM(31:0) Filter Mask

FM(31:0) defines t he valid bits for the comparison of the routing

address RA(31:0) in the int ernal header with t he ASM-identification

Note: If t he Filter Mask is all 0, all cells will accepted by the ASM. This feature is used

e.g. in a multiplexer.

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5.1.22 LIC Protection Sw itch Register (Write)

Hardware reset value LPS0(3:0) = 0000

LP S1(3 : 0) = 0 00 1

LP S2(3 : 0) = 0 01 0

LP S3(3 : 0) = 0 01 1

LPS15(3:0) = 1111

Software reset v alue (no change)

Readable for test purposes.

These registers control the output multiplexer (refer to Figure 10).

LPSR LPS1(3:0) LPS0(3:0) 38H

LPS3(3:0) LPS2(3:0) 39H

LPS5(3:0) LPS4(3:0) 3AH

LPS7(3:0) LPS6(3:0) 3BH

LPS9(3:0) LPS8(3:0) 3CH

LPS11(3:0) LPS10(3:0) 3DH

LPS13(3:0) LPS12(3:0) 3EH

LPS15(3:0) LPS14(3:0) 3FH

LPS0 … 15(3:0) LIC Protection Switch

The 16 LPS-registers (LPS0 … LPS15) define which output queue

is switched to which output line. Here t he register LPS0 defi nes t he

queue for the output 0, LPS1 the queue for output 1 up to LPS15

the queue for output 1 5.

Cells routed t o an output port which is not connected to an ou tput

line, are dis carded. Several out puts may be connected to the same

output queue.

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5.1.2 3 Transm it Cell Regist e r 0 (Write Only)

Hardware reset value unknown

Software reset value (no change)

TCR0 Transmit Cell Octet # 1 40H

Transmit Cell O ctet # 63 7EH

Transmit Cell Par ity (co lumnwise, odd) 7FH

Via the Transmi t Cell Register the µP can insert test cells into the actual cell

data stream . Cells from this input are handled in the s ame way as if they

were receiv ed on any other ASM input port, but the cell format is different.

The first oct et, oc tet 0 = sync. oct et, is omi tted. Instead of this, after the last

octet (octet 63) an odd parity octet must be ins erted.

It is not required to exchange the complete contents of TCR0 if only a few

octets are different in the next cell . However, the parity octet must be

recalculated.

The internal cell transfer starts if TX0 in the Command Register COR has

been set t o 1 by the µP, and is completed when TX0 has been reset to 0 by

the ASM. After that TCR0 may be changed f or the next cell. The T X0-bit is

also set after writing the last oct et (octet 63).

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5.1.24 Transmit Cell Register 1 (Write Only)

Hardware reset val ue unknown

Software reset v alue (no change)

TCR1 Transmit Cell Octet # 1 80H

Transmit Cell Octet # 63 BEH

Transmit Cell Pa rity (columnwise, odd) BFH

The TCR1 register is identical to the TCR0. It allows an additional processor

or protocol chip t o insert communication cell into the act ual cell data stream.

The internal cell trans fer starts if TX1 in the Command Register COR has

been set by the µP, and is completed when TX1 has been reset by the ASM.

After that TCR1 may be set for the next cell . The TX1-bit is also set after

writing the last octet (octet 63).

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5.1.25 Receive Cell Register (Read On ly)

Hardware reset value unknown

Software reset value (no change)

RCR0 Rec eive Cell Octet # 1 C0H

Receive Cell Oct et # 63 FEH

Receive Cell Parity (columnwise, odd) FFH

RX = 1 in the Command Register COR indicates that a new cell i s available

in the Receive Cell Register. The cell forma t is identical t o the format in

TCR0/1.

When the last octet, which is the Receive Cell Parity (address FFH), has

been access ed for readout, the ASM resets RX automaticall y. Otherwise, if

the µP does not read t he complete cell, RX can be reset by the µP to start

the next internal cell transfer into RCR, if there is another cell available in the

µP ou tpu t queue.

Note: The cell parity is not checked by the ASM. This has to be done by the

P or

protocol chip.

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6 Application

6.1 Example for System Configuration

The following example explains the programming of the routing control registers for a

switching netw ork consisting of a 64 ×64 funnel-type switching network co re expanded

by single chip multiplexers MUX (see Figure 31). In the most general case a cell must

find it s way through the input multiplexer MUXIN, through the switching network core and

through an output multiplexer MUXOUT. If input and output of the cell path are at the

same multiplexer the way through the core should be omitted in order to avoid

unnecessary load inside the core. For the definition of MUXIN and MUXOUT see

Figure 27. Both are realized by one si ngle ASM working in s plit mode and connec ted to

the core with a bundle of 4 SLIF lines as shown in Figure 28.

Also multicast connec tions will be set-up w here a cell input at one port of the sw itching

network i s replicated and output at t wo or more output ports. Even the full broadcast case

is possible where the cell is replicated to all outputs. Some branches of a multicast

connection could be at the same multiplexer as the root branch and some other

branches at other multiplexers.

Several possibilities exist to address such a network; one of them is described in the

following.

Figure 31 Example Swi t ch

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The self-r outing ATM cell could have the following assignment of t he 32-bi t rout ing field:

– MUXIN: this field specifies the path through the input multiplexer. It allows short path

connections, i. e. connections between terminals at the same multiplexer.

– Funnels: This field specifies in a bit mapped form one of the four funnels. For

point-to-point connections only on e of the 4 bits is set to one, th e other 3 bits are set

to zero; e.g. funnel = 0100 selects the second funnel.

– Route: This field spec ifies the output of the s elected funnel.

– MUXO UT: This field spec ifies the output of the out put multiplexer/concentrator.

The multicas t ATM c ell could have the following assignment of the 32-bit routing field:

– Funnels: This field s pecifies the f unnel(s) whic h have to ac cept the cell. These will be

those funnels where the connection has branches. Several bits may be set, e.g.

funnels = 0101 determines that the cell is forwarded within the second and the f ourth

funnel. This measure avoids unnecessary cell traffic in the second stages of the first

and third funnel. If during the existence of the connection a further branch is

established, e.g. at the third funnel, the value of funnels may be changed to 0111.

This would not affect the existing branches.

– Multicast routing addr ess: This field is used by t he ASMs which have a multicast RAM

connected. They use th is field to addr ess the external RAM containing in each entry

the outputs to which the cell is to be forwarded in a bitmapped form.

Unused MUXIN Funnel Route Unused MUXOUT

444412 4

Unused Funnel Unused Multic ast routing address

8 4416

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6.1.1 P rog ramming of the ASMs

The switching network core in this example has the size 64 ×64 and is realized as two-

stage funnel network consisting of 4 funnels (Figure 32). The AS Ms in the fir st stage of

the funnels work as filt ers only. All accepted cells are forwarded to one output which is

defined as bundle of 16. The second stage accepts all cells and routes them to the output

specified in th e four ‘Route’ bits of the cell.

Figure 32 Core Programming Example

Programming of the ASMs in the First Stage

They have different mask register values:

The ASMs ‘Filt er 1000’:

FMR(31:0) = 0000 0000 10 00 0000 0000 0000 0000 0000

IDR(31:0) = 0000 0000 1000 0000 0000 0000 0000 0000

The ASMs ‘Filt er 0100’:

FMR(31:0) = 0000 0000 01 00 0000 0000 0000 0000 0000

IDR(31:0) = 0000 0000 0100 0000 0000 0000 0000 0000

The ASM ‘Filter 0010’:

FMR(31:0) = 0000 0000 00 10 0000 0000 0000 0000 0000

IDR(31:0) = 0000 0000 0010 0000 0000 0000 0000 0000

The ASM ‘Filter 0001’:

FMR(31:0) = 0000 0000 00 01 0000 0000 0000 0000 0000

IDR(31:0) = 0000 0000 0001 0000 0000 0000 0000 0000

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All ‘Filter’ ASMs have defined one outpu t bundle of 16:

OGR register:

OPE(15: 0) = 1111 1111 1111 1111 enables all outputs

– CBC = 1 to change the bundle configuration, this bit will be reset by the ASM

– OG(14) = 1 to define the bundle of 16, OG(13:0) are don’t care

– OPTR(4:0) = 00000, don’t care, as for one single output the routing bits are not

interpreted

The ASMs are programmed to treat also multicast cell s as s elf-routing cells by sett ing in

the Mode register the bit MODR:EVMCI = 0. Then also the multicast cells are filtered and

accepted by one or more funnels.

Programming of the A SMs in the Second Stage

FMR(31:0) = all ‘0 ’, i.e. without filter function

IDR(31:0) = don’t care

OGR register:

– OPE(15:0) = 1111 1111 1111 1111 enabl es all outputs

– CBC = 1 to change the bundle configuration, this bit will be reset by the ASM

– OG(11:8) = 1111 to define four b undle of 4, all other OGR bits ‘0’

– OPTR(4:0) = 10000, points to the 16th bit position of the routi ng header field of the cell,

thus the r outing header bits RA (19:16) indicate the output of the A SM .

The ASM inputs are programmed as two bundles of 16 by setting in the mode register

IG0 and IG1 to ‘1’.

Programming of the ASMs in the Multiplexers

FMR(31:0) = all ‘0 ’, i.e. without filter function

IDR(31:0) = don’t care

OGR register:

– OPE(15:0) = 1111 1111 1111 1111 enabl es all outputs

– CBC = 1 to change the bundle configuration (this b it will be reset by the ASM)

– OG(8) = 1 to define the bundle of 4 for outputs 0 … 3, all other OGR bits ‘0’

– OPTR(4:0) = 11000, points to the 24th bit position of the routi ng header field of the cell,

thus the r outing header bits RA (27:24) indicate the output of the A SM .

The ASM is programmed in split mode by defining inputs 0 … 3 as inputs with fixed

routing evaluation, i.e. using the four least significant bits of the routing header RA( 3:0).

This is done by programming in the Mode register MODR:IS(5:0) = 000100, i.e. the

decimal value 4. The cells input at inputs 4 … 31 are treated normally, with the RA(27:24)

bits defining the 4-bit field of t he output port.

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6.1.2 Examples

1) A self-routing cell has the routing header f ield

RA(31:0) = 0000 0000 0100 0110 0000 0000 1011

– MUXIN = 0000, i.e. the cell is forwarded to output 0 which is part of the output

bundle 0 … 3. The cell is forwarded to the core.

– Funnel = 0100, i .e. the second funnel accepts the cell

– Route = 0110, i.e. the cell is f or warded to out put 6 of the second funnel

– M UXOUT = 1011, i.e. the cell is forwa rded to output 11 of the output m ultiplexer

2) A multic ast cell has th e routing h eader field

RA(31:0) = 0000 0000 0101 0000 0000 0000 0001 1100

– The input multiplexer has a multicast RAM attached and uses the multicast routing

address field MCRA(15:0) = 0000 0000 0001 1100 to address the exter nal RAM. The

entry may contain the value 0001 0000 0000 0001, i.e. the cell is duplic ated to output

0 and to output 12 of this ASM. Output 12 leads to another terminal/subscriber

connected to the same ASM, whereas output 0 is part of the bundle of 4 going to the

core.

– F unnels = 0101, i.e . the cell is forwarded into the s econd and fourth funnel.

– T he ASMs of the second stages of the two funnels as well as the output multiplex ers

use the MCRA(15:0) to address their multicast RAM. The cells are forwarded

according to the pattern stored under the respective address in the RAMs.

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6.2 State after Reset

During the reset state (reset = low) all outputs provide a fixed potential

(P-output = high-level; N-output = low-level). When the reset is finished (low-high

transition), the ASM becomes active after a latency time, i.e. all output ports provides

empty cells. The register values now contain de fault values, which can be checked via

the µP-interface.

After a HW -reset only cells with the S SN = 001 are ac cepted by the AS M independent

from the routing address and are made available via the µP-queue. The output ports

deliver only empty cells.

The following section describes the operation state of the ASM after a HW-reset. All

specifies the operat ion mode of the ASM.

• All data inputs (0 … 31) are enabled

IOR(31:0) = ‘all 1’

• No input grouping for bundles of 16

MODR:IG0 = ‘0’ for input ports 0 … 15

MODR:IG1 = ‘0’ for input ports 16 … 31

•µP-cell acceptance with swit chi ng stage num ber SSN = ‘1’

MODR:SSN(3:0) = ‘0001’

• All inputs accept only mi croprocessor cells identified by the correct SSN; all other cells

are discarded.

MO D R:AOP C = ‘1 ’

• No µP-queue lim itation

MODR:PQL = ‘0’

• Interrupt for µP- cell s are enabled

MODR:ACCEL = ‘0’

• The INT1 for control cells is disabled, i.e. an incoming control cell with correct SSN

activates an interrupt INT0 and not the INT1.

MODR:APCEL = ‘1’

• All bits of the interrupt status register ISR except PCRCV are masked, i.e. only

µP cells (and no error states) can activate an interrupt.

IMR = ‘all 1’

• No routing address evaluation, i.e. the µP-cells are only checked for the SSN

FMR(31:0) = ‘all 0’

After reset the operation mode will be programmed into the ASM(s) of a switching

network. This is done using t he registers MODR, OGR, IDR and FMR. See the examples

described in Chapter 6.1 for t he usage of these registers.

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6.3 Test and Communication Channels

The ASM provides functions to support communication channels via the data lines. This

is useful for the c ommunication channel between processors and for testing data paths.

To s upport the c ommunication channels the A SM provides t wo insertion buffers and one

extraction buffer together with the associated transfer registers. A comparison

mechanism based on the switching stage number field SSN of the ATM cells determines

if a cell is to be extracted from the cell stream and directed to the µP. Two different

interrupts are f oreseen to inform the µP about t he extr act ion of a cell . Thus t wo diff erent

channels can be supported, e.g. one f or control and one for tes t.

Communicati on C ha nne l

Especially larger switching networks may extend over several boards, connected e.g. via

a backplane. On each board a local processor could be located. At board start-up the

on-board processor can be loaded from a main processor with data or program

information. During operation the communication channel can be used for conveying e.g.

maintenance information and (multicast) connection set-up information. See Figure 33

for an example configuration where the main processor is connected like a line card via

the PXB 4110 SARE chip.

Figure 33 ASM Addressing Concept Using SSNs

For the start-up phase where a large amount of data could be loaded to an on-board

processor additional features are provided. It is assumed that during the system

start-up phase no user data cel ls are transferred by the switching network. Theref ore the

MODR:AOPC bit of the destination ASM can be set to disable all other cells than

µP cells. In addition the MODR:PQL bit can be cleared to allocate the whole central

buffer for the µP queue.

During operation the control channel between on-board processor and main processor is

used to convey maintenance information and the set-up of multicast connections.

Maintenance informations are e.g. failure indications and st atus reports, as the resul ts of

ITS07447

Main

Processor SARE

PCI

Interface UTOPIA

Interface

ASM

SSN = 1 SSN = 2

ASM SSN = 3

ASM

Local

Processor

ASP

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routine checks. The set- up, releas e or modific ation of a m ulticast connection requires to

update the entries in all multicast tables in the switch for the multicast routing address.

No action in the switching network is required for the set-up of point-to-point connections,

as the address of self-rout ing cells is only added in the ASP.

Test Channel

The communication channels can also be used to test the data paths of the switching

network. To check the output data path of an ASM a test cell is inserted by the ASM

under test via one of the two transmit registers TCR0 and TCR1. The cell is received

either by a subsequent AS M or by t he ASP. T o check the i nput data path of an ASM test

cells are ins er ted by a preceding A SM or the ASP. The SSN(3:0) field of the internal c ell

header allows to destine the test cell specifically to a certai n ASM, where it is extracted.

Cells are only extracted by an ASM if SSN and routi ng address match. Figure 33 shows

in an example how the addr essing concept using the SSN works. Subsequent ASMs of

a multi-stage switching network have e.g. incr easing SSN numbers. So test cells can be

directed to every ASM.

The maintenance control cell (see Table 1) has a special behavior. This cell is not

influenced by the setti ng of the output multiplexer and uses always the default output. To

test the switchover of the output multiplexer test cells with other housekeeping

combination as 011b should be used.

Also the buffer limits for fairness management and low priority cells can be tested using

the test channel. For this purpose the readout of the output queues is disabled by

clearing the OGR:OPE(15: 0) bits. Then multiple tes t cells are sent to the diff er ent output

queues to check both the maximum and the adjustable limit. This can be done for

different combinations of output grouping.

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6.4 Error Detectio ns and Indications

6.4.1 E xt ernal Error Detection

The ASM supervises the high speed data inputs on the following errors:

– S ynchron ization State (SYNC/AS YNC)

The ASM checks the SYNC-octet of each incoming cell. If only one SYNC-octet of a cell

is invalid, t his error is indicated in the registers ISR, LFR, and LER (dependent on ILA).

The corrupted cell is not discarded.

If two or more consecutive cells with invalid SYNC-octet are detected, this error is

indicated in the regis ters ISR, LASR, LFR, and LER (dependent on ILA).

The transition to the ASYNC-state is attended with three additional actions:

• No header evaluation f or the affected line

• Discarding of the cor responding cells

• Restart of the synchronization mechanism. The synchronous state is established

again if at least two valid SY NC-o ctets have been detected in series.

– P arity Check of the Internal Header

The ASM checks the parity bit of the internal header (octet 1 … 6) for each incoming cell.

If a parity error occurs, this error is indicated in the registers ISR, LFR, and LER

(dependent on ILA). The corrupted c ell is dis card ed.

6.4.2 In ternal Error Detection

In the ASM the internal error detection is divided into the supervision of the data path and

the control path. The data path is checked by a cell parity byte, the control path is

supervised by an additional internal parity bit (e.g. for the cell location data) and by

internal plausibilit y checks.

– Internal Cell Parity Check

The internal cell is protected by an addit ional parity byte generated at each input port and

checked at each output port. If an internal parity error is detected, this erro r is indicated

in the I SR:IPE. The possibly cor rupted cell can not be di scarded in the ASM. A faulty cel l

can be detected in a following ASM or ASP.

– Co ntrol Path Check

If any failure occurs in the control path, a cont r ol error is indicated in the ISR-register. A

control err or means t hat cells ar e dis c arded. This ser ious er ror can only be corr ected by

a HW -reset.

– P arity Check for Multicast Lo oku p Table (MLT)

The MLT-entries are also protected with a parity bit. If a parity error occurs, this error is

indicated in the ISR:MLTPE. The multicast information of the corrupted entry will be

ignored, so t hat the cell will be dis carded.

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6.5 Test of Error Indications

The error indications of the ASM can be tested by the µP according to Table 8.

Note: Some of the tests cause loss of data cells and are therefore not executable in

service. These tests would only be done at sys tem/board start-up.

– ASYNC Error Test

Action: Is done by performing at least two successive IVSYNC operations

(by setting the bits MR:IVSYNC = ‘1’, OLA(3:0) = ‘binary coded output port

(0 to 15)’) on the same output line address (OLA) within a time frame of

2.46 µs at mos t.

Effect: Two successive cells of the output line selected are provided with a

corrupted Synchronization Octet, to gene rate an ASYNC error indication to

ISR, LASR, LER and LFR.

Note: ASYNC errors can be detect ed only by a A SM/ASP loc ated behind the generating

device; the cells concerned get lost in a ny case.

Table 8 Testing of Error Indications

Error Indic ation Abbr. Testability

Async St ate ASYNC Via at least 2 successive MR:IVSYNC operations;

causes loss of data.

Sync Error SYNCE Via one MR:IVSYNC operation.

Header Parity Error PE Via test cells; causes loss of dat a.

Control Error CTRLE Via MR:IVQ RP or MR:IVFC P operations;

causes loss of data.

Internal Parity Error IPE Via test c ells; causes los s of data.

MLT Parit y Error MLTPE Via MR:IVMCCP operations; may caus e loss of data.

Multicast Misrouting MCMR Via test cells; causes loss of data.

Buffer Overflow B O V V ia test c ells and/or via OG R :OPE;

causes loss of data.

Threshold Overflow TOV Via PTR equal to ‘0’; causes loss of low pr iority cells.

Queue Overflow QOV Via MQLR equal to ‘0’; causes loss of data.

Microprocessor

Queue Overflow PQOV Via test cells or via bit MR:DPQ.

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– S YNC Error Test

Action: Is done by setting the bits MR:IVSY NC = ‘1’ and OLA(3:0) = ‘binary coded

output port (0 to 15)’) to the required values.

Effect: One of the cells, read out from the selected queue, is provided with a

corrupted Synchronization Octet to generate a SYNC error indication to ISR,

LER and LFR.

Note: Synchronization Errors can be detected only by a ASM/ASP located behind the

generating device. I f under worst case c onditions the Sync Octet of the preceding

or successive cell is a lso corru pted by sporadic noise an ASYNC error instead of

a SYNC error is indicated. Cells concerned only from any single SYNC error do

not get lost.

– Head er Parity Error Test

Action: Insertion of test cells provided with corrupted parity bit i n the int ernal header.

Effect: Parity Errors are detected and mapped into ISR:PE, LER:LPE, and LFR.

Note: Via the

P-Interface test cells can be inserted into the data stream and are

evaluated direct ly in the header evaluation unit of the ASM.

– Co ntrol Error Test

Action: Is done by setting the bit MR:IVQRP = ‘1’ (invalidation of the queue RAM bus

checks) and/or the bit MR:IVFCP = ‘1’ (invalidation of the Free Cell list parity

bit) of the maint enance register.

Effect: Parity errors are produced within the protected queue path and

consequently are indicated as Control Error s CTRLE in ISR.

Note: The test described causes the los s of data in any case.

– Internal Parity Error Test

Action: Insertion of test cells provided with a corrupted IPE octet into the data

stream running vi a the Data Output Circuits.

Effect: Every par ity v iolation is detected in the out put chec kers and indicated as an

Intern al Parity Er ro r IP E in ISR .

Note: Test cells leaving the ASM via Output Queue 17 (i.e. the

P-interface) are not

parity checked and therefore cannot cause an IPE message (test cell r emoval via

Queue 17 is possible for all the ASMs, getting test cells with a valid SSN/

(RA) indication).

– Multicast Lookup Table Error Test

Action: Is done by setting the bit MR:IVMCCP = ‘1’ (invalidation of the MLT parity

bit).

Effect: Parity er rors are produced within the protected path and consequently are

indicated as Mult ic ast Lookup Table Parity Error MLTPE and in ISR.

Note: The test described may cause the loss of data.

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– Mul ticast Mis r outing Test

Action: Is done by inserting cells via TCR0/1 with ADI(0) = ‘1’ (actual cell = multicast

cell). Th e MODR:DCMC- bit has to be set to ‘1’.

Effect: The cell will not be accepted and ISR:MCM R will be set.

– Buffer Overfl ow Test

Action: Is done by sett ing the bits OGR:OGE = ‘all 0’ (disable of the Output Queues)

and selecting the bundle m ode 16 (to get one output queue with sufficient

queue entries to fill up the Central Buffer); the Central Buffer now can be

filled up by e.g. sending cells via the TCR0/1.

Effect: The Central Buffer is filled up by data cells to generate a Buffer Overflow

message to ISR:BOV.

– Threshold Overflow Test

Action: Is done by setting the Priority Threshold Register PTR to ‘0’.

Effect: Every cell, j ust going to be stored in the Central Buffer leads to a Threshold

Overflow indication TOV in ISR.

Note: Non-prioritized cells (characterized by a CLP bit = ‘1’) are rejected and lost.

– Threshold Overflow Test

Action: Is done by setting the Priority Threshold Register PTR equal to ‘0’.

Effect: Every cell, j ust going to be stored in the Central Buffer leads to a Threshold

Overflow indication TO in GE R.

Note: Non-prioritized cells (characterized by a CLP bit = ‘1’) are rejected and lost.

– Queue Overflow Test

Action: Is done by sett ing the thre s hold of the Maximum Queue Length Register for

the belonging output queue to ‘0’.

Effect: Every cell location entry, just going to be stored in the output queue RAM

leads to a Queue Overflow indication QOV in ISR.

Note: All inc oming cells are rejected and lost.

– Microprocessor Queue Overflow Test

Action: Is done by setting the threshold of the Microprocessor Queue

(MODR:PQL = ‘1’) and MR:DPQ = ‘1’ (disable readout of µP-queue).

Effect: Every cell location entry which exceeds the threshold value, leads to a

Microprocessor Queue Overflow indication PQ OV in I SR.

Note: All incoming cells exc eeding the threshold v alue are rejected and lost.

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7 Electrical Characteristics

7.1 DC Characteristics

Parameter S ymb ol L imit Values Unit Note

min. max.

(DI, DI)

Input high voltage VIH –1.9 V

Input low v oltage VIL 0.5 – V

Input differential voltage VID =VIH –VIL 0.100 – V 1)

(CL, C L)

Input high voltage VIH –1.9 V

Input low v oltage VIL 0.5 – V

Input differential voltage VID =VIH –VIL 0.100 – V 1)

1) For AC characterist ics, higher input swing is necessary.

Parameter Symbol Lim it Values Unit Note

min. max.

(DO, D O)

Output high voltage VOH 1.410 1.535 V 2)

O u t p ut low volta g e VOL 0.935 1.060 V 2)

Output differential voltage VOD =VOH –VOL 0.400 0.550 V

2) Each output l ine i s terminated by a 50 Ω resistor (50 Ω lines). Every two matching resistors belongi ng to one

output pair are connected via one cap acitor to groun d.

Without external t ermination resistors, the high level becomes VCC and the low level 0 V (time depends on

the capacitive load).

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Parameter Symbol Limit Values Unit Note

min. max.

(ADR0 … 7, DAT0 … 7, CS, RD, WR, TEST, TMOD, RES, TFI0 … 1)3)

Input high volt age VIH 2 VCC V 4)

Input low volt age VIL 0 0.8 V

(DAT0 … 7, TCO0 … 9)3)

Output high voltage VOH VCC – 0.6 – V

Output low voltage VOL –0.4V

(INT0 … 1, RDY)

Output high voltage VOH VCC – 0.6 – V 5)

Output low voltage VOL –0.4V

(TFO0 … 6)

Output high voltage VOH 6)

Output low voltage VOL 6)

(CLO, CSS)

Output high voltage VOL 6)

Output low voltage VOL 6)

3) LVCMOS level.

4) LVCMOS inputs have to be held on either low or high level to avoid floating input lines, when used.

5) The open drain outputs are connected to the supply voltage VCC via an external pull-up resistor.

6) The source-follower outputs are connected to the ground potent ial GND via an external 50 Ω resistor.

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Semiconductor Group 106 12.97

Note: The listed characteristics are ensu red over the operating range of the integr ated

circuit. Typical characteristics specify mean values expected over the produc tion

spread. If not otherwise specified, typical characteristics apply at

=25

C and

the given supply voltage.

Parameter Symbol L imit Values Unit Note

min. max.

Input Leakage Current

DI, DI; CL, CL;IIL – 1 1 µA

Control-, µP-signals IIL – 1 1 µA

Parameter Symbol L imit Values Unit Note

min. max.

(DO, D O)

Output high curre nt IOH 7)

Output low curren t IOL 7)

(TCO0 … 9, DAT0 … 7)

Output high curre nt IOH 8)

Output low curren t IOL 8)

7) 50 Ω, οut put volt age between 0 V and VCC.

8) LVCMOS level

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Semiconductor Group 107 12.97

7.2 AC Characteristics (Conditions: See Operating Conditions, Section 7.5)

Parameter Symbo l Limit Values Unit Note

min. max.

Clock Signal (CL, CL )

Input differential voltage VID =VIH –VIL 0.350 – V

Transition time tTHL 0.2 0.6 ns

tTLH 0.2 0.6 ns

Skew tSKHL – 0.1 0.1 ns

tSKLH – 0.1 0.1 ns

Width high tWH 2.26 ns

Width low tWL 2.26 ns

Jitter (peak-peak) tJPP 140 ps

Period tCLK 4.82 ns 9)

Clock/data frequency

deviation fD– 1.0 1. 0 kHz 10)

Input Data (DI, DI)

Input differential voltage VID =VIH –VIL 0.200 – V 11)

Input differential voltage VID =VIH –VIL 0.300 – V 12)

Transition time tTHL 0.2 1.0 ns

tTLH 0.2 1.0 ns 13)

Skew tSKHL – 0.2 0.2 ns

tSKLH – 0.2 0.2 ns

Jitter (peak-peak) tJPP 2ns

Width high tWH 2.82 6.82 ns

Width low tWL 2.82 6.82 ns

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Semiconductor Group 108 12.97

µP-, Test-Signals

Transition Time tTHL

tTLH

9) The nominal operating frequency is 207.36 MHz, i.e. tCLK = 4.82 ns.

10) The clock frequency fCLK and the data rate can differ at most by the specified value (± 1.0 kHz).

11) Standard jitter requirements.

12) Advanced jitter requirements.

13) The max. transition time should be 1.5 ns if t he differential input voltage is at least 0. 3 V.

Parameter Symbol Limi t Values Unit No te

min. max.

Reset Signal (RESET)

Transition time tTHL 320 ns

tTLH 320 ns

Signal width 100 ns 14)

Output clock (CLO)15)

Transition time tTHL 0.3 0.7 ns

tTLH 0.3 0.7 ns

Jitter (peak -peak) tJPP 400 ps

Width high tWH tCLK –0.6 tCLK +0.6 ns

Width low tWL tCLK –0.6 tCLK +0.6 ns

Cell Start Si gnal (CSS)

Transition time tTHL 0.3 0.7 ns

tTLH 0.3 0.7 ns

Jitter (peak -peak) tJPP 400 ps

Width high tWH 8 × tCLK –0.6 ns

Parameter Symbo l Limit Values Unit Note

min. max.

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Semiconductor Group 109 12.97

Note: The proposed solutions for the bit phase alignment circuitry presently can cope

with a maximum deviation of the data (and clock) of about

1 ns per cell assuming

a frequency deviation of better than 10

–5

(for asynchronous operation) .

Note: The listed characteristics are en sured over the operating ra nge of the integrated

circuit. Typical characteristics specify mea n v alues expected over the pr oduction

spread. If not otherwise specified, typical characteristics apply a t

=25

C and

the given suppl y voltage.

Output Data (DO, DO)

Transition time tTHL 0.2 0.6 ns

tTLH 0.2 0.6 ns

Jitter (peak-peak) tJPP 300 ps 17)

Width high 4.52 5.12 ns 16)

Width low 4.52 5.12 ns 16)

Skew – 0.10 0.10 ns

14) During the low frequency test (1 MHz), a minimum value of 2 ×tCLK has to be kept .

15) The clock output frequency is identical to the in put clock, i.e. fCLO = 207.36 MHz.

Attention:

The phase relat ion between the clock output and the output data differ to each port.

16) For nominal clock peri od = 4.82 ns.

17) In case of non terminated open outputs the jitter value for used adj acent outputs can increase to 400 ps.

Paramete r Symb ol Limit Value s Unit Note

min. max.

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Semiconductor Group 110 12.97

Figur e 3 4 T r a ns ition Timing

Figure 35 Clock/Data Timing

Figure 36 Jitter

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Semiconductor Group 111 12.97

7.3 µP-Interface Signals (See Timing Figure 37)

Paramete r Symbol Limit Values Unit Note

min. max.

Write Operation

ADR setup to w rite low tAW 0ns

CS low to write low tCW 0ns

Write low pulse width tWL 200 ns 17)

ADR, CS hold after write high tWC 0ns

Write inactive time tWI 20 ns

RDY (Ready) low delay fr om write low tWY 0 20 ns

RDY (Ready) low pulse width write tRYW 25 140 ns

Write high after ready high tRWH 0ns

Data setup to write high tDW 30 ns

Data hold after write high tWD 10 ns

Read Operation

ADR setup to read low tAR 0ns

CS low to read low tCR 0ns

Read low pulse width tRL 240 ns 17)

ADR, CS hold after read high tRC 0ns

Read inactiv e time tRI 20 ns

RDY (Ready) low delay fr om read low tRY 0 20 ns

RDY (Ready) low pulse width read tRYR 25 140 ns

Read high after ready high tRRH 0ns

Data valid aft er read low tRDV 180 ns

Data valid before ready high tDRY 10 ns

Data f loat after read high tDF 20 ns

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Semiconductor Group 112 12.97

Interrupt Inactive

Interrupt high after RD/WR high tIH 50 ns 18)

Interrupt inactive delay tID 100 ns

17) This MIN-value is necessary if no READY is used.

18) If an interrupt is pendi ng this will only occur when writ ing into the command regist er with RX-bit = 1 or

reading RCR(63) or reading ISR .

Parameter Symbol Limi t Values Unit Note

min. max.

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Semiconductor Group 113 12.97

Figure 37 µP Read/Wr ite Cycle

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Semiconductor Group 114 12.97

7.4 Multicast RAM Interface Signals (See Timing Figure 38)

Parameter Symbol Limit Values Unit Not e

min. max.

ASM Parameters

MC CL K cy cl e time tCLK 38.6 38.6 ns 19)

MC ADR set u p to MC CLK hig h tAS 5ns

MCADR hold after MCCLK high tAH 1ns

MCWR setup to MCCLK high tWS 5ns

MCWR hold after MCCLK high tWH 1ns

MCOE low to MCCLK high tES 15 ns

MCOE high after MCCLK high tEH 10 ns

MCDAT set up to MCCLK high tDS 5 ns

MCDAT hold after MCCLK high tDH 1ns

RAM Parameters

MCOE low to MCDAT low – Z tLZOE 010ns

MCOE high to MCDAT high – Z tHZOE 25ns

MC CL K hi gh to MCD A T va lid tCD 12 ns

19) MCCLK is derived from the inter nal Octet Clock, which is 1/8 of the operating clock.

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Semiconductor Group 115 12.97

ASM RAM (e.g. Samsung KM718BV 87)

MCCLK K

MCAD R 0 … 15 A 0 … 15

MCWR LW, UW

MCOE OEN

MCDA T 0 … 15 I/O 0 … 15

MCPAR I/O 16

Static ‘0 ’ CS, AD SP, AD SC

Static ‘1 ’ ADV

Not connected I/O 17

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Semiconductor Group 116 12.97

Figur e 3 8 Multica s t Timi ng

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Semiconductor Group 117 12.97

7.5 Power Supply

Note: Stresses above those listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for ex tended periods may affect

device reliability .

Note: All timing values are valid for the recommended operating frequency

of 207.36 MHz. This frequency has the advantage of having a simple relationship

of 4/3 t o the SDH/SONET frequency of 155.52 MHz.

Table 9 Absolute Maximum Ratings

Paramete r Symbol Limit Values Unit Note

min. max.

Storage temperat ure TS– 65 150 °C

Junction temperat ure TJ125 °C

Supply voltage VCC – 0.5 4.6 V

Input voltage VIN – 0.5 VCC +0.5 V

Output voltage VOUT

Input/output currents I– 20 20 mA 1)

Continuous output current – 25 25 mA 2)

Power dissipation P3.7 W

1) The cited f igur es are valid for i nput voltages of VIN < 0V, VIN >VCC respectivel y (input currents) and for output

voltages of VOUT <0V,VOUT > VCC (output currents) respectivel y.

2) The cited figures are valid for output vol tages VOUT bet ween 0 V and VCC (0 V < VOUT <VCC).

Table 10 Operating Conditions

Parameter Symbol Limi t Values Unit Note

min. max.

Supply voltage VCC 3.135 3.465 V 3)

Digital ground GND 0V

Ambient temperature TA070°C4)

Junction temperat ure TJ100 °C

3) The voltages VCC can be switched on and off in any given sequence.

4) The upper limit of the all owed ambient temperature st rongly depends upon the package, the mounting and

the air fl ow conditions. In any case the maximum chi p junct ion temperature of 100 °C must not be exceeded

for a proper chip operation (see dynamic charact eristics).

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Package Outlines

Semiconductor Group 118 12.97

8 Package Outlines

P-BGA-352

(Pla stic Ball Gri d Arra y Pa ckage)

GPA09112

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data B ook “Package Information”. Dimensions in mm

SMD = Surface Mounted Device

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Appendix

Semiconductor Group 119 12.97

9 Appendix

9.1 Performance

The ASM can be modeled in the following way. Each output is represented as a

multiplexer with N inputs and one output, each operating at the transmission speed R

(see Figure 39). The multiplexer has N times higher speed than the inputs, so that all

cells are forwarded to the output queue within one cell cycle. Each input receives an

equal cell load L/N, suc h that the out put load is L.

Figure 39 Modeling an ASM Output

Investigations have shown that t he behav ior of N|1 multiplexers is independent from the

value of N for N > 8. The reason is that if the number of inputs increases the load on each

input decreases, such that the probability that cells from different inputs arrive at the

same time remains constant. The phenomenon, that several cells arrive at the same time

leads to a filling of the out put queue. If it occurs repeatedly the output queue with a given

size S may overflow.

The important parameter to be determined is the probability that the output queue

overflows. It can be calculated i f a Bernoulli arri val process is assumed. This means that

in each cell cycle there is the same pr obabilit y for a cell arrival. Its value in the case of

Figure 39 is L/N. Theoretically the output queue could become infinitely large, but with

very low probability. This probability can be calculated using basic probability

calculation [4].

For this purpose a steady state is assume d, i.e. outp ut load L < 1 ( otherwise the buffer

would const antly f ill up). Then t he pr obabilities are calculated that the buffer is filled with

0, 1, 2, … S cells. If these values are summed up the result is the probability that the

buffer filling is less or equal to S. In a similar way the probabilities of the propagation

delays can be calc ulated.

The ASM has 16 outputs with 16 associated output queues. The cell s torage, however,

is done i n a common central buff er. With this concept the total required buffer s ize is not

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Appendix

Semiconductor Group 120 12.97

16 times the size of one buffer, but much les s. The reason is, t hat it is very unlikely that

at the same time all queues are filled to maximum value. Mathematically this is

expressed by the c onvolution of the pr obability distributions.

Numerical results are shown in the following figures. Figure 40 shows the required

buffer sizes for diff erent multiplexers depending on the load of t he out put. It can be seen

that the x|16 multi plexer needs much less than 16 tim es the x|1-multi plexer. This shows

that the shared buffer c oncept has a minimum buffer usage.

These curves are useful for the definition of fairness levels for outpu t bundles. If e.g. a

4-bundle is to be operated at a load of 0.85, the x|4-curve returns the value of

approximately 105 ce lls.

Figure 40 Buffer Sizes f or Cell Loss Probability 10 – 11

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Appendix

Semiconductor Group 121 12.97

Another main per formance parameter of the ASM, the ce ll loss probability depending on

the cell load, is shown in Figure 41.

Figure 41 Cell Loss Rate versus Load

Note: The s witch cell load m ust be converted to t he real load at th e output ports taking

into account the speed increase and the internal cell format. Given the external

ATM data rate the internal rate can be calculated.

Switch link load = external link load

64/53

external A TM rate/switch rate

e.g.

external link load = 149.76 Mbit/s (STS-3c or S T M-1 payload rate)

switch rate = 207.36 M bit/s (using clock speed 155.52

4/3 MHz)

external link load = 95 %

result: Switch link load = 82.85 % .

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Appendix

Semiconductor Group 122 12.97

The same model can be used to derive another important performance parameter of the

ASM, the cell delay variation CDV. In Figure 42 below the probabilities for cell

propagation delay through the ASM ar e shown for different load values. The horizontal

axis is sca led in cell c ycles. The vertical axis show s the probability for a cell to pass the

ASM with the respective delay. The minimum propagation delay of 2 cell cycles is the

pure cell forwarding delay determined by the HW. The additional delays are due to

queueing.

Figure 42 Cell Delay Probability

It can be seen that for a (overall) switch load of 0.8 the probability to experience no

queueing delay at all is 0.3, i.e. 30 % of the cells pass the ASM with minimum delay.

24 % of the cells experience a delay of 3 cell cycles, 16 % 4 cycles and so on. If the

values are summed up, 98 % of the cells experience a delay less or equal than 10 c ell

cycles. The remaining 2 % delay probabilit y for all values beyond 10 cell cycles i s cal led

0.02-quantile. Quantiles of special interest is listed the 10–9

… 10–11

-quantiles, as they

are used for dimensioning the maximum allowed load of the links.

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Overview Li sts

Semiconductor Group 123 12.97

10 Overview Li sts

10.1 References

1. UTOPIA Level 1 Specification Version 2.01, March 21, 1994, A TM Forum

2. UTOPIA Level 2 Specificat ion Version 1.0, June 1995, ATM Forum

3. IEEE 1596.3 Standard for Low-Voltage Differential Signals for SCI, Draft 1.3, Nov. 95

4. ‘Traffic Studies of a Multiplexer in an ATM Network and Applications to the future

Broadband ISDN’, D. Lampe, International Journal of Digital and Analog Cabled

Systems, Vol.2, 237-245, 1989

5. ‘ATM Networks: Concepts, Protocols, Applications’, Händel, Schröder, Huber,

Addison-Wesley, 1994, IS BN 0-201-42274-3

6. ‘Performance Comparison of Routing Strategies in ATM Switch Fabrics’, T.H.

Theimer, Proceedings of the XIII International Teletraffic Congress, Copenhagen,

1991, pp. 923-9 28

7. ‘IEEE Standard for L ow-Voltage Differentia l Signals for SCI (LVDS)’, Draft 1.0, IEEE

Std 1596.3-1994

10.2 Glossary and Abbreviations

Table 11 G lossary and Abbreviations

AAC Accept All Cells

AANIC Accept All Non Empty Cel ls

ACCEL Accept Control CELl

AMX ATM Multiplexer

AOPC Accept Only µP-Cells

APCEL Accept µP-CELl

ASN ATM Swit ching Network

ASYNC ASYNChronous State

ATM Asynchronous Transfer Mode

ATM-1 A TM for STM-1 channels with 155.52 Mbit/s

ATM-4 A TM for STM-4 channels with 622.08 Mbit/s

ATM-16 ATM for STM-16 channels with 2488.32 Mbit/s

BOV Buffer OVerflow

CBC Change Bundle Configuration

CLP Cell Loss Priority

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Semiconductor Group 124 12.97

COR COmm and Register

CTRLE ConTRoL Error

DCMC DisCard MultiCast

DOS Disable OverScan

DPA Disable Phase Alignment

DPQ Disable µP-Queue

EVMCI EValuate Mult iCast Identifier

EVMCM E Valuat e MultiCast identifier for split mode

EVMCP EValuate MultiCast Parity

FIFO First In First Out m emory

FM Filter Mask

FMR Filter Mask Regi ster

GND GrouND potential

I/O Input/Output

ID ASM ID e nti fi cati o n

IG Input Grouping

ILA Input Line Addres s

IMR Interr upt Mask Regi ster

IOR Line Online Register

IPE Interna l Pa rit y Error

IS Input Select

ISR Interrupt Status Regist er

IVFCP InVali date Free Cells List Parity

IVMCCP InValidate MCC Parity

IVQRP InValidate Queue RAM Parity

IVSYNC InValidate SYNChroniz ation Octet

LAN Local Area Network

LASR Line As y nchronous State Regist er

LASYNC Line ASYNChr onous State

LER Line Error Register

LFR Line Failed Register

Table 11 Glo ssary and Abbreviations

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Semiconductor Group 125 12.97

LIC Line Interface Circuit

LP E Line Pari t y Err o r

LPS LIC Protection Switch

LPSC LIC Protection Switch Change

LPSR LIC Protection Switch Register

LSB Least Signific ant Bit

LSYNC Line SYNChronization Error

LVCM OS Low Voltage CMOS

LVDS Low Voltage Differential Signals

MASYNC Mask ASYNChronous State

MBOV Mask Bu ffer OVerflow

MC MultiCast

MCA M ultiCast Address Register

MCINI MultiCast RAM INItialization

MCM R MultiCast MisRouting

MC-RAM MultiCast RAM

MCTRLE Mask Control Error

MIP E Mask I ntern al Parity Er ro r

MLT Multicast Lookup Table

MLTPE Multicast Lookup Table P arity Error

MMC MR Mask MultiCast M isRouting

MML TPE Mask Multicast Lookup Table Parity Error

MODR MODe Register

MPE M ask Parity Er ror

µP MicroProcessor

MPE M ask Parity Er ror b it

MPQOV Mask Microprocessor Queue Overflow

MQLR Maxim um Queue Length Register

MQO V Mask Queue Overflow

MR Maintenance Register

MSB Most Si gnificant Bit

Table 11 G lossary and Abbreviations

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Semiconductor Group 126 12.97

MSYNCE Mas k Synchroni zat i on Error

MTOV Mask Threshold Overflow

MTR Multicast Transfer Regist er

MUX MUltipleXer

NRZ Non-Return to Zero

OG Outpu t Grouping

OGE Output Por t Enable

OGR Output Group Register

OLA Output Line Address

OMR Operation and Maintenance Register

OPE Output Port Enable

OPQ OutPut Queue

OPTR Out p u t Poi nTeR

PParity

PCRCV µP-Cell in ReCeiVe buffer

PE Parity Error

POV Processor Queue OVerflow

PQL µP-Queue Length

PQOV MicroProcessor Queue OVerflow

P/S Parallel/Serial Converter

PSI Protection Switch Identifier

PTR Priority Thr eshold Register

PT-PT Point-to-Point

QOV Queue Overf low

RAM Random Access Memory

RCR Receive Cell Regist er

RMLT Read M ulticast Lookup Table (MC-RAM)

ROM Read Only Memory

RX Receiv e µP/comm unication Cell

S/P Serial/Parallel Converter

SCI Scalable Coherent Interface

Table 11 Glo ssary and Abbreviations

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Semiconductor Group 127 12.97

SLIF Switch Link I nter Face

SRES Software Reset

SSN Switch St age Number

STCO Select Test Cont rol Output

STFO Select Test Fullcus tom Output

ST M S yn chronou s T ran sf er Mo de

STM-1 STM basic s ignal with 155.52 Mbit/s

STM-4 STM multiplex signal wit h 622.08 Mbit/s

STM-16 STM mult iplex signal with 2488.32 Mbit/s

SWPQ SWi tch µP-Queue

SYNC SYNChronous state

SYNC E SYNChronization Error

t.b.d. To be defined

TCR Transmit Cell Register

TOS Te st Output Select

TOV Th reshold OVerflow

TRT Test Routing Bits

TX0 Trans mi t µP-cell

TX 1 Tra nsmit com m u nic atio n ce ll

VCC Supply Voltage

WA Wide Area Network

WMLT Write Multicast Lookup Table (MC-RAM)

Table 11 G lossary and Abbreviations