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Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. Copyright 2002 Xilinx, Inc. All Rights Reserved. Virtex-II Pro Platform FPGA Handbook UG012 (v1.0) January 31, 2002 Revision History The following table summarizes changes made to each version of this document. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Contents About This Handbook .............................................................................................................. Introduction to the Virtex-II Pro FPGA Family................................................ 7 11 Part 1: Virtex-II Pro Data Sheet Virtex-II Pro Platform FPGAs: Introduction and Overview Summary of Virtex-II Pro Features .......................................................................... General Description........................................................................................................ Architecture ........................................................................................................................ IP Core and Reference Support ................................................................................. Virtex-II Pro Device/Package Combinations and Maximum I/Os ............. Virtex-II Pro Ordering Information ......................................................................... Revision History ............................................................................................................... Virtex-II Pro Data Sheet Modules ............................................................................ 19 20 21 24 24 25 25 25 Virtex-II Pro Platform FPGAs: Functional Description Virtex-II Pro Array Functional Description ....................................................... Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) Functional Description: Processor Block .............................................................. Functional Description: PowerPC 405 Core ......................................................... Functional Description: FPGA ................................................................................... Revision History ............................................................................................................... Virtex-II Pro Data Sheet Modules ............................................................................ 27 27 33 36 39 69 69 Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Electrical Characteristics ................................................................... 71 Virtex-II Pro Performance Characteristics ............................................................ 77 Virtex-II Pro Switching Characteristics ................................................................. 79 Virtex-II Pro Pin-to-Pin Output Parameter Guidelines ................................ 101 Virtex-II Pro Pin-to-Pin Input Parameter Guidelines.................................... 103 DCM Timing Parameters............................................................................................ 104 Revision History ............................................................................................................. 109 Virtex-II Pro Data Sheet Modules .......................................................................... 109 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 3 R Part 2: Virtex-II Pro User Guide Chapter 1: Timing Models Summary ............................................................................................................................ Processor Block Timing Model ................................................................................ Rocket I/O Timing Model .......................................................................................... CLB / Slice Timing Model .......................................................................................... Block SelectRAM Timing Model............................................................................ Embedded Multiplier Timing Model ................................................................... IOB Timing Model ........................................................................................................ Pin-to-Pin Timing Model ........................................................................................... Digital Clock Manager Timing Model ................................................................. 113 114 121 126 135 139 141 151 154 Chapter 2: Design Considerations Summary ............................................................................................................................ Introduction ...................................................................................................................... Rocket I/O Transceiver ................................................................................................ Processor Block ............................................................................................................... Global Clock Networks ............................................................................................... Digital Clock Managers (DCMs) ............................................................................ Block SelectRAMTM Memory .................................................................................... Distributed SelectRAM Memory ............................................................................ Look-Up Tables as Shift Registers (SRLUTs) ................................................... Large Multiplexers ........................................................................................................ Sum of Products (SOP) Logic ................................................................................... Embedded Multipliers................................................................................................. Single-Ended SelectI/O Resources ......................................................................... Digitally Controlled Impedance (DCI) ................................................................ Double-Data-Rate (DDR) I/O ................................................................................... LVDS I/O ........................................................................................................................... Bitstream Encryption .................................................................................................... Platform Generator ........................................................................................................ CORE Generator System ............................................................................................ 161 161 162 180 202 222 243 260 269 279 289 296 303 333 348 363 368 372 372 Chapter 3: Configuration Summary ............................................................................................................................ Introduction ...................................................................................................................... Configuration Solutions ............................................................................................. Master Serial Programming Mode ......................................................................... Slave Serial Programming Mode ............................................................................ Master SelectMAP Programming Mode .............................................................. Slave SelectMAP Programming Mode ................................................................. JTAG/ Boundary Scan Programming Mode ...................................................... Configuration With MultiLINX .............................................................................. 4 www.xilinx.com 1-800-255-7778 389 389 396 403 404 406 408 412 431 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Details .................................................................................................. 431 Readback ............................................................................................................................ 441 Chapter 4: PCB Design Considerations Summary ............................................................................................................................ Pinout Information ........................................................................................................ Pinout Diagrams ............................................................................................................. Package Specifications................................................................................................. Flip-Chip Packages ........................................................................................................ Thermal Data ................................................................................................................... Printed Circuit Board Considerations .................................................................. Board Routability Guidelines .................................................................................. XPower ................................................................................................................................ IBIS Models ...................................................................................................................... BSDL and Boundary Scan Models ......................................................................... 447 447 459 489 497 497 499 505 511 511 516 Appendix A: BitGen and PROMGen Switches and Options Using BitGen .................................................................................................................... 517 Using PROMGen ........................................................................................................... 523 Appendix B: XC18V00 Series PROMs PROM Package Specifications ................................................................................. 529 XC18V00 Series of In-System Programmable Configuration PROMs Features ............................................................................................................................... Description ........................................................................................................................ Pinout and Pin Description ....................................................................................... Xilinx FPGAs and Compatible PROMs ............................................................... Capacity .............................................................................................................................. In-System Programming ............................................................................................. External Programming ................................................................................................. Reliability and Endurance ......................................................................................... Design Security ............................................................................................................... IEEE 1149.1 Boundary-Scan (JTAG)....................................................................... XC18V00 TAP Characteristics ................................................................................... TAP AC Parameters....................................................................................................... Connecting Configuration PROMs ....................................................................... Master Serial Mode Summary ................................................................................. 5V Tolerant I/Os ............................................................................................................. Reset Activation .............................................................................................................. Standby Mode ................................................................................................................. Customer Control Pins ................................................................................................ Absolute Maximum Ratings .................................................................................... Recommended Operating Conditions .................................................................. Quality and Reliability Characteristics................................................................ UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 533 533 534 536 536 536 537 537 537 537 539 539 539 540 543 543 543 543 544 544 544 5 R DC Characteristics Over Operating Conditions .............................................. 545 AC Characteristics Over Operating Conditions for XC18V04 and XC18V02 .................................................................................................................... 546 AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and XC18V256 .................................................................................................................. 547 AC Characteristics Over Operating Conditions When Cascading for XC18V04 and XC18V02 ................................................................................................ 548 AC Characteristics Over Operating Conditions When Cascading for XC18V01, XC18V512, and XC18V256 ..................................................................... 549 Ordering Information .................................................................................................. 550 Valid Ordering Combinations ................................................................................. 550 Marking Information ................................................................................................... 550 Revision History ............................................................................................................. 551 6 Glossary............................................................................................................................................. 553 Index ...................................................................................................................................................... 579 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R About This Handbook This document describes the function and operation of Virtex-II Pro devices and also includes information on FPGA configuration techniques and PCB design considerations. For Virtex-II Pro device specifications, refer to the Virtex-II Pro Data Sheet modules in Part I of this handbook: * * * Virtex-II Pro Platform FPGAs: Introduction and Overview Virtex-II Pro Platform FPGAs: Functional Description Virtex-II Pro Platform FPGAs: DC and Switching Characteristics For details on the following topics, see the Virtex-II Pro Platform FPGA User Guide in Part II of this handbook: * * * * * * Chapter 1: Timing Models Chapter 2: Design Considerations Chapter 3: Configuration Chapter 4: PCB Design Considerations Appendix A: BitGen and PROMGen Switches and Options Appendix B: XC18V00 Series PROMs The Data Sheet in Part I, together with Chapter 2 in Part II, provide an overview of the Rocket I/O multi-gigabit transceiver and PowerPC 405 processor. For details, the following documents, available at www.xilinx.com/virtex2pro, offer in-depth technical design information: * * * Rocket I/O User Guide PPC405 User Manual Processor Block Manual Additional Resources Resource Handbook Description/URL This site contains the latest Virtex-II Pro User Guide and Data Sheet: http://www.xilinx.com/products/virtex/handbook.htm Application Notes This site contains device-specific design techniques and approaches: http://www.xilinx.com/apps/appsweb.htm Xcell Journals This site contains quarterly journals for Xilinx programmable logic users: http://www.xilinx.com/xcell/xcell.htm UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 7 R Resource Tech Tips Description/URL See this site for the latest news, design tips, and patch information on the Xilinx design environment: http://www.xilinx.com/support/techsup/journals/index.htm Data Book The Programmable Logic Data Book describes device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging: http://www.xilinx.com/partinfo/databook.htm Answers Database This database provides a current listing of solution records for Xilinx software tools. Search this database using the search function at: http://www.xilinx.com/support/searchtd.htm Typographical Conventions The following typographical conventions are used in this manual: * Red text indicates a cross-reference to information within the document set you are currently reading. Click the red text to go to the referenced item. To return to the original page, right-click anywhere on the current page and select Back. * Blue-underlined text indicates a link to a Web page. Click blue-underlined text to browse the specified Web site. * The Courier (monospaced) typeface indicates prompts or program outputs displayed by the system: speed grade: 5 * The Courier bold typeface indicates literal commands that you enter in a syntactical statement. However, braces "{ }" in Courier bold are not literal, and square brackets "[ ]" in Courier bold are literal only in the case of bus specifications, such as bus[7:0]. rpt_del_net= Courier bold also indicates menu command sequences: File Open Courier bold also indicates filenames, file extensions, and/or file system paths: ... delete testfile.s ... ... and all *.p files ... ... in the \web\docs\source\ folder ... * Bold in the normal body text typeface indicates names of graphical user interface (GUI) items. * Italic denotes the following items: ... mark the Use All Search Terms checkbox and click OK ... - Inside angle brackets "< >", variables in command strings that are substituted with user-defined values: edif2ngd <design_name> - References to other documents: - Emphasis in text: See the Libraries Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. 8 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R * Square brackets "[ ]" indicate an optional entry or parameter. The brackets are not typed when entering the parameter in the command string. However, in bus specifications, such as bus [7:0], they are required. edif2ngd [<option_name>] <design_name> * Braces "{ }" enclose a list of items from which you must choose one or more; a vertical bar "|" separates items in a list of choices: * A vertical ellipsis indicates repetitive material that has been omitted. lowpwr = {on|off} IOB #1: Name = QOUT' IOB #2: Name = CLKIN' . . . * A horizontal ellipsis ". . ." indicates that an item can be repeated one or more times. allow block <block_name> <loc1> <loc2> ... <locn>; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 9 R 10 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Introduction to the Virtex-II Pro FPGA Family The Next Logical Revolution The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture "from the ground up." To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx co-developed the world's most advanced Platform FPGA silicon product. Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm. The result is the first Platform FPGA solution capable of implementing high performance system-on-a-chip designs previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. The Virtex-II Pro family marks the first paradigm change from programmable logic to programmable systems, with profound implications for leading-edge system architectures in networking applications, deeply embedded systems, and digital signal processing systems. It allows custom user-defined system architectures to be synthesized, next-generation connectivity standards to be seamlessly bridged, and complex hardware and software systems to be co-developed rapidly with in-system debug at system speeds. Together, these capabilities usher in the next programmable logic revolution. Built for Bandwidth The Virtex-II Pro family consists of five members, each with four to sixteen Rocket I/OTM multi-gigabit transceivers based on the Mindspeed SkyRailTM technology. Each Xilinx Rocket I/O block contains a complete set of user-configurable supporting circuitry that address real-life, system-level challenges. These include standard 8B/10B encode/decode, programmable signal integrity adjustments for varying PCB trace lengths and materials, support for synchronization of multiple channels, and programmable support for channel control commands. In addition, the Rocket I/O blocks are the first FPGA-embedded transceivers to reach a baud rate of 3.125 Gb/s. Four Rocket I/O blocks, employing 16 PCB traces, can be used to support a full-duplex 10 Gb/s channel by way of the Rocket I/O channel-bonding feature. This is equivalent to 256 traces of typical LVTTL buses or 68 traces of a high-speed, source-synchronous parallel LVDS bus. It allows a PCB trace reduction of up to 16X over conventional parallel buses, resulting in significant reductions in PCB complexity and EMI system noise. The Rocket I/O technology fulfills higher bandwidth system requirements than currently possible, with cost savings from faster time-to-market, reduced printed circuit board (PCB) complexity, and lower component count. The Virtex-II Pro members also incorporate small yet powerful PowerPC processor cores. Each of the larger Virtex-II Pro devices incorporates one to four IBM PowerPC 405 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 11 R processor cores, each capable of more than 300 MHz clock frequency and 420 Dhrystone MIPS. While each processor core occupies a small die area, these processor cores provide tremendous system flexibility where they are used. The PowerPC 405 cores are fully embedded within the FPGA fabric, where all processor nodes are controlled by the FPGA routing resources. This provides the utmost architectural capability, where complex applications may be efficiently divided between high-speed logic implementation and high-flexibility software implementations. For example, a packet processing application using only the FPGA logic today for high-speed packet routing may be augmented to include a slave high-performance processor for exception handling or in-system statistics monitoring. In contrast, using a separate processor externally requires hundreds of additional interface pins, which degrades the system performance, significantly increases FPGA I/O requirements, and overall board costs. The Virtex-II Pro products are based on the most advanced FPGA fabric available: the Virtex-II architecture with IP-ImmersionTM technology, which was developed for significant improvements in engineering productivity, silicon efficiency, and system flexibility. Unique features common in the Virtex-II Series--consisting of the Virtex-II and Virtex-II Pro families--include powerful SystemIOTM system connectivity solutions, digitally controlled impedance (DCI) technology, comprehensive clocking solutions, highspeed Active InterconnectTM routing architecture, and bitstream encryption. These features together constitute the most complete Platform FPGA solution available, optimized for high-performance system-level applications. The upward compatibility of the Virtex Series of products ensures benefits in engineering productivity, performance, design longevity, and continuing cost reduction. Legacy of Leadership Each of the Virtex families of FPGAs has been the most successful programmable product family in its class, starting with the introduction of the original Virtex family in 1998. The Virtex and Virtex-E families were recognized by the industry as the highest technology products available when they were first introduced. The Virtex-II family, which again achieved technology leadership in density, performance, and features, ushered in the era of Platform FPGAs--programmable devices with the system-level capability and performance to implement systems functionality. The Virtex-II Pro family continues the tradition of technology leadership as the most sophisticated Platform FPGA yet, again breaking the technology barrier for the benefit of leading-edge system architects. The Virtex-II Pro family is the first FPGA family to incorporate both serial transceiver technology and a hard processor core within a general-purpose FPGA device. This is significant for new high-bandwidth embedded processing applications such as packet processing, where both high device I/O bandwidth and high performance processor cores are needed together. The Virtex-II Pro devices are the industry's first FPGAs in a 0.13-micron process. The IBM nine-layer metal, all-copper, low-k process technology is among the most advanced in the semiconductor industry. The combination of advanced Active InterconnectTM architecture and advanced process technology makes the Virtex-II Pro family the highest performance FPGA in the world. The Rocket I/OTM multi-gigabit transceiver (MGT), based on industry-leading SkyRailTM technology, is the highest performance, most complete embedded serial transceiver available. It is user-configurable for up to 3.125 Gb/s baud rate per channel, which is over twice the performance of other embedded transceivers at 1.25 Gb/s. Each Rocket I/O block provides a complete set of common functionality available in standard SerDes transceivers. In contrast, "programmable ASSP" products with clock/data recovery (CDR) provide only the most basic transceiver capability. The IBM PowerPC 405 processor core used in the Virtex-II Pro family is the highest performance embedded core available in FPGAs. The PowerPC architecture is used in 12 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R many markets including communications, industrial control, test and measurement systems, and other performance-oriented markets. It is currently the most popular processor architecture in embedded applications. Packets Everywhere The Virtex-II Pro family provides a powerful new paradigm for network processing where low latency is required, such as storage area networks, wireless infrastructure, and voice-over-IP networks. The digital convergence phenomenon drives the need for packet routing based on type and priority. For example, live voice and video data packets require significantly lower latency than data file packets. New data networking applications must now handle higher bandwidth traffic as well as more complex types of prioritized packets. In many cases, Virtex-II Pro devices can offer higher overall performance than other solutions, including specialized network processors (NPs). Using the Virtex-II Pro architecture, the most common packets may be quickly read and routed using FPGA logic, without incurring the lengthy software run-time needed by NPs. The FPGA logic interrupts the PowerPC processor core only when processor instructions are needed for special packet types. For example, packets may be stored into a 16 KB dual-port memory area accessible by both the FPGA logic and the PowerPC 405 on-chip memory (OCM) port, allowing rapid change of control and packet disposition. By using the FPGA logic to process the most common packet types while the processor core handles the more specialized ones as a slave to the logic, the Virtex-II Pro architecture can provide higher overall performance than NPs, as well as more sophisticated processing capabilities than FPGA logic alone. Bridge, Anyone? Powerful protocol bridges for tying together disparate data stream formats are well-suited for the Virtex-II Pro solution. New interface standards and protocols include 3GIO, Infiniband, Gigabit Ethernet, XAUI/10 Gigabit Ethernet, RapidIO, and HyperTransport. These must interface seamlessly to one another, as well as to other standards such as PCI, Fibre Channel, POS Phy Level 4, Flexbus 4, and others. This presents a significant challenge to system developers because of changing standards, scarcity of off-the-shelf interface components, and the inflexibility of available solutions. System designers have had to assemble their own blend of FPGAs, discrete physical transceivers, and discrete communications processors to solve their complex system challenges. Even newer "programmable ASSPs" (application-specific standard products) with built-in serial transceivers fall short, because they frequently require companion FPGAs to supplement their logic capacity. The Virtex-II Pro solution, using the powerful Xilinx SystemIOTM capability to fully integrate silicon, software, and IP capabilities, provides the most flexible pre-engineered protocol bridge solutions available for fast time-to-market and low development cost. Simplifying Complexity The Virtex-II Pro solution offers a powerful paradigm for complex embedded systems found in signal processing, industrial control, image processing, networking, communications, and aeronautic applications. For the first time, complex embedded systems traditionally involving sophisticated hardware and software may be developed concurrently, emulated in actual hardware at speed, debugged in-system, and re-architected for performance within weeks, rather than months or years. In addition, full systems can be remotely upgraded as easily as software-only upgrades are performed today, using Compact Flash, CDROM, Internet, wireless transmission, or other flexible means. Hardware design is simplified using powerful development software and a large soft IP library to assemble logic- and processor-based platforms. Software development UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 13 R may be started earlier using the actual device in preconfigured sample platforms, without waiting for the new system board to be developed. In many cases, higher density Virtex-II Pro components may be used for early system development, whereby extra resources (including additional PowerPC processor cores) may be used to easily emulate board-level components yet to be developed. This flexibility, obviously unavailable in custom ASICs or ASSPs, allows systems to be emulated at speed, rather than simulated using software simulators at 100 or 1000 times slower. In-system debugging is further enhanced by the Xilinx ChipScope Pro tool, which provides comprehensive logic analysis--from probing internal nodes to full bus analysis with bus protocol adherence checks using an external logic analyzer via the IEEE 1149.1 (JTAG) test access port. Using ChipScope Pro can result in orders of magnitude of improvement in engineering productivity. Complex systems can be optimally repartitioned between FPGA logic and processor cores, allowing a continuum of possible trade-offs between the speed of logic and the flexibility of software code. For example, a first implementation of an echo cancellation algorithm might be all-software in compiled C code running on a PowerPC core, in order to allow the system software development to start. As the system is further optimized, part of the DSP algorithm could be retargeted using Matlab Simulink into FPGA logic to achieve a significantly faster but functionally identical system for production release. In another example, an encryption application might implement the Diffie-Hellman key exchange algorithm, whereby exponentiation and message management could be optimally partitioned into FPGA logic and an embedded processor, respectively. In this way, the programmable systems paradigm offers tremendous flexibility to allow system designers and architects to optimize the trade-offs in development time, system performance, and system costs. It is significant that the embedded systems enabled by Virtex-II Pro solutions are "all-soft," in that both logic and software code are controlled by a soft data file. Because of this, the low cost of design maintenance and degree of design reuse is greatly enhanced. Whole system upgrades, including both hardware and software, can now be accomplished with one unified soft file using System ACETM configuration solutions, offering the same low cost and ease of use as software-only upgrades. Time Is Money The Virtex-II Series, comprising both the Virtex-II and Virtex-II Pro families, offers significantly faster time-to-market and lower development costs than ASICs. Compared to a full-custom ASIC, the Virtex-II Pro solution eliminates the need for exhaustive verification during development, and allows hardware-software debug at system speeds rather than slow software simulation speeds. In addition, the Virtex-II Pro features of signal integrity, pre-engineered clocking capabilities, and an abundance of soft IP cores, significantly reduce development time. The Virtex-II Series offers significantly lower development costs than ASICs, due to lower tool costs, lower third-party IP costs, and absence of NRE costs. The Virtex-II Series also increases engineering productivity by accelerating hardware availability for software development and increasing software debug speed. In addition, the availability of powerful development tools enables straightforward retargeting of other embedded processors into the PowerPC platform. Compared to other processor architectures, the PowerPC 405 core in most cases allows higher performance and more powerful capabilities, and thus can be used to accelerate preproduction of performance-sensitive applications. 14 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Flexibility Is Money The flexibility inherent in the Virtex-II Series allows system architects to fine-tune their architectural partitioning after the initial prototype is developed. That is, each subsystem function can be freely implemented as hardware only, software only, or any combination within the hardware-software continuum, depending on the trade-off between performance and complexity. For example, a wireless infrastructure system might initially implement a rake filter function in hardware, and then change to a firmware implementation as more software control is necessary during later development. This repartitioning would be impossible in custom ASICs without significant time and cost penalties. The Virtex-II Series offers significantly more flexibility than fixed chip sets and ASSPs, allowing end user product differentiation and future proofing. For a design requirement that can generally be met either by ASSPs or by Virtex-II Platform FPGAs, the initial design investment for an FPGA implementation may be higher. However, the advantages for Platform FPGA implementations include customizing of functionality, ease of design reuse, ability to fix design bugs, differentiation of user end products, and ownership and control of the entire system. These are important advantages in highly competitive markets where ASSPs have standing errata lists and unpredictable future availability. In contrast, properly developed Platform FPGA designs are soft designs that may be readily maintained and reused as needed. Therefore, FPGA methodologies can provide system manufacturers with greater competitive advantage in the short term, and greater ownership and control over their products in the long term. Not Being Discrete Many high bandwidth systems today use large FPGAs together with discrete SerDes transceivers, discrete communications processors, or other discrete components. The Virtex-II Pro family can incorporate many of these components for time-to-market, performance, and even system cost benefits. Multi-chip solutions using FPGAs typically require over a hundred I/O pins to interface to each discrete quad 3.125 Gb/s SerDes transceiver or discrete microprocessor. The result is increased PCB complexity necessary to accommodate hundreds of traces, reduced system performance due to on-chip/off-chip connections, and higher overall system costs. In some cases, the increased FPGA pin-count requirement may force a higher-density FPGA to be used, increasing the overall cost. In these cases, the Virtex-II Pro devices can integrate the discrete components to achieve faster system development, higher system performance, and lower costs. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 15 R 16 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Part I: Virtex-II Pro Data Sheet This section contains the Virtex-II Pro advance product specification (DS083). The latest version of this information is available online (at www.xilinx.com/apps/virtexapp.htm). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 17 R 18 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook 0 Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 (v1.0) January 31, 2002 0 Advance Product Specification 0 Summary of Virtex-II Pro Features * * * * High-performance Platform FPGA solution including - Up to sixteen Rocket I/OTM embedded multi-gigabit transceiver blocks (based on Mindspeed's SkyRailTM technology) - Up to four IBM(R) PowerPCTM RISC processor blocks Based on VirtexTM-II Platform FPGA technology - Flexible logic resources - SRAM-based in-system configuration - Active InterconnectTM technology - SelectRAMTM memory hierarchy - Dedicated 18-bit x 18-bit multiplier blocks - High-performance clock management circuitry - SelectI/OTM-Ultra technology - Digitally Controlled Impedance (DCI) I/O * * * * * * * PowerPC RISC Core Features The members and resources of the Virtex-II Pro family are shown in Table 1. Rocket I/O Features * * * * * Full-duplex serial transceiver (SERDES) capable of baud rates from 622 Mb/s to 3.125 Gb/s 80 Gb/s duplex data rate (16 channels) Monolithic clock synthesis and clock recovery (CDR) Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and Infiniband-compliant transceivers 8-, 16-, or 32-bit selectable internal FPGA interface 8B /10B encoder and decoder 50 /75 on-chip selectable transmit and receive terminations Programmable comma detection Channel bonding support (two to sixteen channels) Rate matching via insertion/deletion characters Four levels of selectable pre-emphasis Five levels of output differential voltage Per-channel internal loopback modes 2.5V transceiver supply voltage * * * * * * * * * * * * Embedded 300+ MHz Harvard architecture core Low power consumption: 0.9 mW/MHz Five-stage data path pipeline Hardware multiply/divide unit Thirty-two 32-bit general purpose registers 16 KB two-way set-associative instruction cache 16 KB two-way set-associative data cache Memory Management Unit (MMU) - 64-entry unified Translation Look-aside Buffers (TLB) - Variable page sizes (1 KB to 16 MB) Dedicated on-chip memory (OCM) interface Supports IBM CoreConnectTM bus architecture Debug and trace support Timer facilities Table 1: Virtex-II Pro FPGA Family Members CLB (1 CLB = 4 slices = Max 128 bits) Device Rocket I/O Transceiver Blocks PowerPC Processor Array Blocks Row x Col Slices Block SelectRAM Maximum 18 X 18 Bit Distributed Multiplier RAM (Kb) Blocks 18 Kb Blocks Max Block RAM (Kb) DCMs Max I/O Pads XC2VP2 4 0 16 x 22 1,408 44 12 12 216 4 204 XC2VP4 4 1 40 x 22 3,008 94 28 28 504 4 348 XC2VP7 8 1 40 x 34 4,928 154 44 44 792 4 396 XC2VP20 8 2 56 x 46 9,280 290 88 88 1,584 8 564 XC2VP50 16 4 88 x 70 22,592 706 216 216 3,888 8 852 (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-1 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 19 R General Description Virtex-II Pro Platform FPGA Technology * * * * * * * SelectRAM memory hierarchy - Up to 4 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources - Up to 706 Kb of distributed SelectRAM resources - High-performance interfaces to external memory Arithmetic functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible logic resources - Up to 45,184 internal registers/latches with Clock Enable - Up to 45,184 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state busing High-performance clock management circuitry - Up to eight Digital Clock Manager (DCM) modules * Precise clock de-skew * Flexible frequency synthesis * High-resolution phase shifting - 16 global clock multiplexer buffers in all parts Active Interconnect technology - Fourth-generation segmented routing structure - Fast, predictable routing delay, independent of fanout - Deep sub-micron noise immunity benefits SelectI/O-Ultra technology - Up to 852 user I/Os - Twenty two single-ended standards and five differential standards - Programmable LVTTL and LVCMOS sink/source current (2 mA to 24 mA) per I/O - Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI support(1) - Differential signaling * 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers * Bus LVDS I/O * HyperTransport (LDT) I/O with current driver buffers * Built-in DDR input and output registers - Proprietary high-performance SelectLink technology for communications between Xilinx devices * High-bandwidth data path * Double Data Rate (DDR) link * Web-based HDL generation methodology * * * * * * SRAM-based in-system configuration - Fast SelectMAPTM configuration - Triple Data Encryption Standard (DES) security option (bitstream encryption) - IEEE1532 support - Partial reconfiguration - Unlimited reprogrammability - Readback capability Supported by Xilinx FoundationTM and AllianceTM series development systems - Integrated VHDL and Verilog design flows - ChipScopeTM Integrated Logic Analyzer 0.13-m, nine-layer copper process with 90 nm high-speed transistors 1.5V (VCCINT) core power supply, dedicated 2.5V VCCAUX auxiliary and VCCO I/O power supplies IEEE 1149.1 compatible boundary-scan logic support Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in standard 1.00 mm pitch Each device 100% factory tested General Description The Virtex-II Pro family is a platform FPGA for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU cores in Virtex-II Pro Series FPGA architecture. It empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The leading-edge 0.13m CMOS nine-layer copper process and the Virtex-II Pro architecture are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the Virtex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gate arrays. 1. PCI supported in some banks only. 20 www.xilinx.com 1-800-255-7778 DS083-1 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Introduction and Overview Architecture channel can be operated at a maximum data transfer rate of 3.125 Gb/s. Virtex-II Pro Array Overview Each Rocket I/O core implements the following functionality: Virtex-II Pro devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-II Pro devices implement the following functionality: * * * * * * * Embedded high-speed serial transceivers enable data bit rate up to 3.125 Gb/s per channel. Embedded IBM PowerPC 405 RISC CPU cores provide performance of 300+ MHz. SelectI/O-Ultra blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by the programmable IOBs. Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources. Block SelectRAM memory modules provide large 18 Kb storage elements of True Dual-Port RAM. Embedded multiplier blocks are 18-bit x 18-bit dedicated multipliers. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division, and coarse- and fine-grained clock phase shifting. A new generation of programmable routing resources called Active Interconnect Technology interconnects all of these elements. The general routing matrix (GRM) is an array of routing switches. Each programmable element is tied to a switch matrix, allowing multiple connections to the general routing matrix. The overall programmable interconnection is hierarchical and designed to support high-speed designs. * * * * * * * * * * * * * * * PowerPC 405 Processor Block The PPC405 RISC CPU can execute instructions at a sustained rate of one instruction per cycle. On-chip instruction and data cache reduce design complexity and improve system throughput. The PPC405 features include: * All programmable elements, including the routing resources, are controlled by values stored in static memory cells. These values are loaded in the memory cells during configuration and can be reloaded to change the functions of the programmable elements. Virtex-II Pro Features This section briefly describes Virtex-II Pro features. Rocket I/O Multi-Gigabit Transceiver Cores The Rocket I/O Multi-Gigabit Transceiver core, based on Mindspeed's SkyRail technology, is a flexible parallel-to-serial and serial-to-parallel transceiver embedded core used for high-bandwidth interconnection between buses, backplanes, or other subsystems. Multiple user instantiations in an FPGA are possible, providing up to 80 Gb/s of full-duplex raw data transfer. Each DS083-1 (v1.0) January 31, 2002 Advance Product Specification Serializer and deserializer (SERDES) Monolithic clock synthesis and clock recovery (CDR) Fibre Channel, Gigabit Ethernet, XAUI, and Infiniband compliant transceivers 8-, 16-, or 32-bit selectable FPGA interface 8B/10B encoder and decoder with bypassing option on each channel Channel bonding support (two to sixteen channels) - Elastic buffers for inter-chip deskewing and channel-to-channel alignment Receiver clock recovery tolerance of up to 75 non-transitioning bits 50 /75 on-chip selectable TX and RX terminations Programmable comma detection Rate matching via insertion/deletion characters Automatic lock-to-reference function Optional TX and RX data inversion Four levels of pre-emphasis support Per-channel serial and parallel transmitter-to-receiver internal loopback modes Cyclic Redundancy Check (CRC) support * PowerPC RISC CPU - Implements the PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications - Thirty-two 32-bit general purpose registers (GPRs) - Static branch prediction - Five-stage pipeline with single-cycle execution of most instructions, including loads/stores - Unaligned and aligned load/store support to cache, main memory, and on-chip memory - Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide) - Enhanced string and multiple-word handling - Big/little endian operation support Storage Control - Separate instruction and data cache units, both two-way set-associative and non-blocking - Eight words (32 bytes) per cache line - 16 KB array Instruction Cache Unit (ICU), 16 KB array Data Cache Unit (DCU) www.xilinx.com 1-800-255-7778 21 R Architecture * * * * * * Operand forwarding during instruction cache line fill Copy-back or write-through DCU strategy Doubleword instruction fetch from cache improves branch latency Virtual mode memory management unit (MMU) - Translation of the 4 GB logical address space into physical addresses - Software control of page replacement strategy - Supports multiple simultaneous page sizes ranging from 1 KB to 16 MB OCM controllers provide dedicated interfaces between Block SelectRAM memory and processor core instruction and data paths for high-speed access PowerPC timer facilities - 64-bit time base - Programmable interval timer (PIT) - Fixed interval timer (FIT) - Watchdog timer (WDT) Debug Support - Internal debug mode - External debug mode - Debug Wait mode - Real Time Trace debug mode - Enhanced debug support with logical operators - Instruction trace and trace-back support - Forward or backward trace Two hardware interrupt levels support Advanced power management support Input/Output Blocks (IOBs) IOBs are programmable and can be categorized as follows: * * * Input block with an optional single data rate (SDR) or double data rate (DDR) register Output block with an optional SDR or DDR register and an optional 3-state buffer to be driven directly or through an SDR or DDR register Bidirectional block (any combination of input and output configurations) These registers are either edge-triggered D-type flip-flops or level-sensitive latches. IOBs support the following single-ended I/O standards: * * * * * * LVDS and Extended LVDS (2.5V only) BLVDS (Bus LVDS) ULVDS LDT Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the routing resources. Configurable Logic Blocks (CLBs) CLB resources include four slices and two 3-state buffers. Each slice is equivalent and contains: * * * * * * * Two function generators (F & G) Two storage elements Arithmetic logic gates Large multiplexers Wide function capability Fast carry look-ahead chain Horizontal cascade chain (OR gate) The function generators F & G are configurable as 4-input look-up tables (LUTs), as 16-bit shift registers, or as 16-bit distributed SelectRAM memory. In addition, the two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches. Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources. Block SelectRAM Memory The block SelectRAM memory resources are 18 Kb of True Dual-Port RAM, programmable from 16K x 1 bit to 512 x 36 bit, in various depth and width configurations. Each port is totally synchronous and independent, offering three "read-during-write" modes. Block SelectRAM memory is cascadable to implement large embedded storage blocks. Supported memory configurations for dual-port and single-port modes are shown in Table 2. Table 2: Dual-Port and Single-Port Configurations 16K x 1 bit 4K x 4 bits 1K x 18 bits 8K x 2 bits 2K x 9 bits 512 x 36 bits 18 X 18 Bit Multipliers A multiplier block is associated with each SelectRAM memory block. The multiplier block is a dedicated 18 x 18-bit 2s complement signed multiplier, and is optimized for operations based on the block SelectRAM content on one port. The 18 x 18 multiplier can be used independently of the block SelectRAM resource. Read/multiply/accumulate operations and DSP filter structures are extremely efficient. LVTTL LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) PCI (33 and 66 MHz) GTL and GTLP HSTL 1.5V and 1.8V (Class I, II, III, and IV) SSTL (3.3V and 2.5V, Class I and II) The DCI I/O feature automatically provides on-chip termination for each single-ended I/O standard. The IOB elements also support the following differential signaling I/O standards: 22 * * * * Both the SelectRAM memory and the multiplier resource are connected to four switch matrices to access the general routing resources. www.xilinx.com 1-800-255-7778 DS083-1 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Introduction and Overview Global Clocking The DCM and global clock multiplexer buffers provide a complete solution for designing high-speed clock schemes. Up to eight DCM blocks are available. To generate deskewed internal or external clocks, each DCM can be used to eliminate clock distribution delay. The DCM also provides 90-, 180-, and 270-degree phase-shifted versions of its output clocks. Fine-grained phase shifting offers high-resolution phase adjustments in increments of 1/256 of the clock period. Very flexible frequency synthesis provides a clock output frequency equal to a fractional or integer multiple of the input clock frequency. For exact timing parameters, see Virtex-II Pro Platform FPGAs: DC and Switching Characteristics. Virtex-II Pro devices have 16 global clock MUX buffers, with up to eight clock nets per quadrant. Each clock MUX buffer can select one of the two clock inputs and switch glitch-free from one clock to the other. Each DCM can send up to four of its clock outputs to global clock buffers on the same edge. Any global clock pin can drive any DCM on the same edge. Routing Resources The IOB, CLB, block SelectRAM, multiplier, and DCM elements all use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the performance of high-speed designs. There are a total of 16 global clock lines, with eight available per quadrant. In addition, 24 vertical and horizontal long lines per row or column, as well as massive secondary and local routing resources, provide fast interconnect. Virtex-II Pro buffered interconnects are relatively unaffected by net fanout, and the interconnect layout is designed to minimize crosstalk. Horizontal and vertical routing resources for each row or column include: * * * * 24 long lines 120 hex lines 40 double lines 16 direct connect lines (total in all four directions) uring Virtex-II Pro devices, complying with IEEE standards 1149.1 and 1532. A system mode and a test mode are implemented. In system mode, a Virtex-II Pro device will continue to function while executing non-test boundary-scan instructions. In test mode, boundary-scan test instructions control the I/O pins for testing purposes. The Virtex-II Pro Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE, and USERCODE non-test instructions. The EXTEST, INTEST, and HIGHZ test instructions are also supported. Configuration Virtex-II Pro devices are configured by loading the bitstream into internal configuration memory using one of the following modes: * * * * * Slave-serial mode Master-serial mode Slave SelectMAP mode Master SelectMAP mode Boundary-Scan mode (IEEE 1532) A Data Encryption Standard (DES) decryptor is available on-chip to secure the bitstreams. One or two triple-DES key sets can be used to optionally encrypt the configuration data. The Xilinx System Advanced Configuration Enviornment (System ACE) family offers high-capacity and flexible solution for FPGA configuration as well as program/data storage for the processor. See DS080, System ACE CompactFlash Solution for more information. Readback and Integrated Logic Analyzer Configuration data stored in Virtex-II Pro configuration memory can be read back for verification. Along with the configuration data, the contents of all flip-flops/latches, distributed SelectRAM, and block SelectRAM memory resources can be read back. This capability is useful for real-time debugging. The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores and Integrated Bus Analyzer (IBA) cores, along with the ChipScope Pro Analyzer software, provide a complete solution for accessing and verifying user designs within Virtex-II Pro devices. Boundary Scan Boundary-scan instructions and associated data registers support a standard methodology for accessing and config- DS083-1 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 23 R IP Core and Reference Support IP Core and Reference Support Intellectual Property is part of the Platform FPGA solution. In addition to the existing FPGA fabric cores, the list below shows some of the currently available hardware and software intellectual properties specially developed for Virtex-II Pro by Xilinx. Each IP core is modular, portable, Real-Time Operating System (RTOS) independent, and CoreConnect compatible for ease of design migration. Refer to www.xilinx.com for the latest and most complete list of cores. Hardware Cores * Bus Infrastructure cores (arbiters, bridges, and more) * * * Memory cores (Flash, SRAM, and more) Peripheral cores (UART, IIC, and more) Networking cores (ATM, Ethernet, and more) Software Cores * * * * * * Boot code Test code Device drivers Protocol stacks RTOS integration Customized board support package Virtex-II Pro Device/Package Combinations and Maximum I/Os Offerings include ball grid array (BGA) packages with 1.0 mm pitch. In addition to traditional wire-bond interconnects, flip-chip interconnect is used in some of the BGA offerings. The use of flip-chip interconnect offers more I/Os than are possible in wire-bond versions of the similar packages. Flip-chip construction offers the combination of high pin count and excellent power dissipation. The Virtex-II Pro device/package combination table (Table 3) details the maximum number of I/Os for each device and package using wire-bond or flip-chip technology. * * * FG denotes wire-bond fine-pitch BGA (1.00 mm pitch). FF denotes flip-chip fine-pitch BGA (1.00 mm pitch). BF denotes flip-chip fine-ptich BGA (1.27 mm pitch). Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os (Advance Information) User Available I/Os 24 Package Pitch (mm) Size (mm) XC2VP2 XC2VP4 XC2VP7 FG256 1.00 17 x 17 140 140 FG456 1.00 23 x 23 156 248 248 FF672 1.00 27 x 27 204 348 396 FF896 1.00 31 x 31 FF1152 1.00 35 x 35 FF1517 1.00 40 x 40 BF957 1.27 40 x 40 396 XC2VP20 XC2VP50 556 564 692 852 564 www.xilinx.com 1-800-255-7778 584 DS083-1 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Introduction and Overview Virtex-II Pro Ordering Information Virtex-II Pro ordering information is shown in Figure 1. Example: XC2VP7-7FG456C Device Type Speed Grade (-6, -7, -8) Temperature Range: C = Commercial (Tj = 0C to +85C) I = Industrial (Tj = -40C to +100C) Number of Pins Package Type DS083_02_102301 Figure 1: Virtex-II Pro Ordering Information NOTE: Maximum serial transceiver baud rates for flipchip and wirebond packages are 3.125 Gb/s and 2.5 Gb/s respectively. Revision History This section records the change history for this module of the data sheet. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II Pro Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II Pro Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II Pro Platform FPGAs: Functional Description (Module 2) * Virtex-II Pro Platform FPGAs: Pinout Information (Module 4) DS083-1 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 25 R Virtex-II Pro Data Sheet Modules 26 www.xilinx.com 1-800-255-7778 DS083-1 (v1.0) January 31, 2002 Advance Product Specification 0 Virtex-II Pro Platform FPGAs: Functional Description R DS083-2 (v1.0) January 31, 2002 0 0 Virtex-II Pro Array Functional Description CLB For detailed Rocket I/O digital and analog design considerations, refer to the Rocket I/O User Guide. All of the documents above, as well as a complete listing and description of Xilinx-developed Intellectual Property cores for Virtex-II Pro, are available on the Xilinx website at www.xilinx.com/virtex2pro. Virtex-II Pro Compared to Virtex-II Devices Virtex-II Pro is built on the Virtex-II FPGA architecture. Most FPGA features are identical to Virtex-II. The differences are described below: CLB * CLB Configurable Logic SelectI/OTM-Ultra * DS083-1_01_010802 Figure 1: Virtex-II Pro Generic Architecture Overview * This module describes the following VirtexTM-II Pro functional components, as shown in Figure 1: * * FPGA fabric based on Virtex-II architecture. For a detailed description of the PPC405 core programming models and internal core operations, refer to the PowerPC 405 User Manual and the Processor Block Manual. Rocket I/OTM Multi-Gigabit Transceiver CLB Multipliers and Block SelectRAM * Processor Block DCM Advance Product Specification Embedded Rocket I/OTM Multi-Gigabit Transceivers (MGTs) Processor Blocks containing embedded IBM(R) PowerPCTM 405 RISC CPU (PPC405) cores and integration circuitry. Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) * Virtex-II Pro is the first FPGA family incorporating embedded PPC405 cores and Rocket I/O MGTs. VCCAUX, the auxiliary supply voltage, is 2.5V instead of 3.3V as for Virtex-II devices. Advanced processing at 0.13 m has resulted in a smaller die, faster speed, and lower power consumption. The Virtex-II Pro family is neither bitstream-compatible nor pin-compatible with the Virtex-II family. However, Virtex-II designs can be compiled into Virtex-II Pro devices. All banks support 2.5V (and below) I/O standards. 3.3V I/O standards including PCI are supported in certain banks only. (See Table 4-1, page 448.) LVPECL, LVDS_33, LVDSEXT_33, LVDCI_DV2_33, and AGP-2X are not supported. . Table 1: Standards Supported by the Rocket I/O MGT This section summarizes the features of the Rocket I/O multi-gigabit transceiver. For an in-depth discussion of the Rocket I/O MGT, refer to the Rocket I/O User Guide. Overview The embedded Rocket I/O multi-gigabit transceiver core is based on Mindspeed's SkyRailTM technology. Up to sixteen transceiver cores are available. The transceiver core is designed to operate at any baud rate in the range of 622 Mb/s to 3.125 Gb/s per channel. This includes specific baud rates used by various standards as listed in Table 1. I/O Baud Rate (Gb/s) Internal Clock Rate (REFCLK) (MHz) 1.06 53 2.12 106 Mode Channels (Lanes) Fibre Channel 1 Gbit Ethernet 1 1.25 62.5 XAUI 4 3.125 156.25 1, 4, 12 2.5 125 Aurora (Xilinx) 1, 2, 3, 4, ... 0.840 - 3.125 42.00-156.25 Custom mode 1, 2, 3, 4, ... up to 3.125 up to 156.25 Infiniband (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 27 R Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) The serial bit rate need not be configured in the transceiver, as the operating frequency is implied by the received data and reference clock applied. The Rocket I/O transceiver core consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the serializer and deserializer. The PCS contains the bypassable 8B/10B encoder/ PACKAGE PINS AVCCAUXRX VTRX decoder, elastic buffers, and Cyclic Redundancy Check (CRC) units. The encoder and decoder handle the 8B/10B coding scheme. The elastic buffers support the clock correction (rate matching) and channel bonding features. The CRC units perform CRC generation and checking. Figure 2 shows the Rocket I/O high-level block diagram and FPGA interface signals. MULTI-GIGABIT TRANSCEIVER CORE FPGA FABRIC Power Down 2.5V RX POWERDOWN RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN Termination Supply RX CRC Check RXCHECKINGCRC RXCRCERR RXDATA[15:0] RXDATA[31:16] RXP Comma Detect Realign RXN Clock Manager 8B/10B Decoder RXNOTINTABLE[3:0] RXDISPERR[3:0] RXCHARISK[3:0] RXCHARISCOMMA[3:0] RXRUNDISP[3:0] RXBUFSTATUS[1:0] ENCHANSYNC CHBONDDONE CHBONDI[3:0] CHBONDO[3:0] Channel Bonding and Clock Correction Parallel Loopback Path Serial Loopback Path Deserializer RX Elastic Buffer RXLOSSOFSYNC RXCLKCORCNT TXBUFERR TXFORCECRCERR TXDATA[15:0] TXDATA[31:16] TX FIFO TXP TXN Serializer 8B/10B Encoder Output Polarity CRC TXBYPASS8B10B[3:0] TXCHARISK[3:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXKERR[3:0] TXRUNDISP[3:0] TXPOLARITY TXINHIBIT GNDA AVCCAUXTX VTTX LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 TX/RX GND 2.5V TX Termination Supply TX DS083-2_04_010202 Figure 2: Rocket I/O Block Diagram 28 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Clock Synthesizer Synchronous serial data reception is facilitated by a clock/data recovery circuit. This circuit uses a fully monolithic Phase Lock Loop (PLL), which does not require any external components. The clock/data recovery circuit extracts both phase and frequency from the incoming data stream. The recovered clock is presented on output RXRECCLK at 1/20 of the serial received data rate. The gigabit transceiver multiplies the reference frequency provided on the reference clock input (REFCLK) by 20. The multiplication of the clock is achieved by using a fully monolithic PLL that does not require any external components. No fixed phase relationship is assumed between REFCLK, RXRECCLK, and/or any other clock that is not tied to either of these clocks. When the 4-byte or 1-byte receiver data path is used, RXUSRCLK and RXUSRCLK2 have different frequencies, and each edge of the slower clock is aligned to a falling edge of the faster clock. The same relationships apply to TXUSRCLK and TXUSRCLK2. as standard data. If the K-character input is High, and a user applies other than one of the twelve possible combinations, TXKERR indicates the error. Disparity Control The 8B/10B encoder is initialized with a negative running disparity. Unique control allows forcing the current running disparity state. TXRUNDISP signals its current running disparity. This may be useful in those cases where there is a need to manipulate the initial running disparity value. Bits TXCHARDISPMODE and TXCHARDISPVAL control the generation of running disparity before each byte. For example, the transceiver can generate the sequence K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+ by specifying inverted running disparity for the second and fourth bytes. Clock and Data Recovery Transmit FIFO The clock/data recovery (CDR) circuits will lock to the reference clock automatically if the data is not present. For proper operation, the frequency of the reference clock must be within 100 ppm of the nominal frequency. Proper operation of the circuit is only possible if the FPGA clock (TXUSRCLK) is frequency-locked to the reference clock (REFCLK). Phase variations up to one clock cycle are allowable. The FIFO has a depth of four. Overflow or underflow conditions are detected and signaled at the interface. Bypassing of this FIFO is programmable. It is critical to keep power supply noise low in order to minimize common and differential noise modes into the clock/data recovery circuitry. Refer to the Rocket I/O User Guide for more details. Transmitter FPGA Transmit Interface The FPGA can send either one, two, or four characters of data to the transmitter. Each character can be either 8 bits or 10 bits wide. If 8-bit data is applied, the additional inputs become control signals for the 8B/10B encoder. When the 8B/10B encoder is bypassed, the 10-bit character order is generated as follows: TXCHARDISPMODE[0] (first bit transmitted) TXCHARDISPVAL[0] TXDATA[7:0] (last bit transmitted is TXDATA[0]) 8B/10B Encoder A bypassable 8B/10B encoder is included. The encoder uses the same 256 data characters and 12 control characters that are used for Gigabit Ethernet, Fibre Channel, and InfiniBand. The encoder accepts 8 bits of data along with a K-character signal for a total of 9 bits per character applied, and generates a 10 bit character for transmission. If the K-character signal is High, the data is encoded into one of the twelve possible K-characters available in the 8B/10B code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v1.0) January 31, 2002 Advance Product Specification Serializer The multi-gigabit transceiver multiplies the reference frequency provided on the reference clock input (REFCLK) by 20. Clock multiplication is achieved by using a fully monolithic PLL requiring no external components. Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs. Bit 0 is transmitted first and bit 19 is transmitted last. The electrical connection of TXP and TXN can be interchanged through configuration. This option can be controlled by an input (TXPOLARITY) at the FPGA transmitter interface. This facilitates recovery from situations where printed circuit board traces have been reversed. Transmit Termination On-chip termination is provided at the transmitter, eliminating the need for external termination. Programmable options exist for 50 (default) and 75 termination. Pre-Emphasis Circuit and Swing Control Four selectable levels of pre-emphasis (10% [default], 20%, 25%, and 33%) are available. Optimizing this setting allows the transceiver to drive up to 20 inches of FR4 at the maximum baud rate. The programmable output swing control can adjust the differential output level between 400 mV and 800 mV in four increments of 100 mV. www.xilinx.com 1-800-255-7778 29 R Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) Receiver Deserializer The Rocket I/O transceiver core accepts serial differential data on its RXP and RXN inputs. The clock/data recovery circuit extracts the clock and retimes incoming data to this clock. It uses a fully monolithic PLL requiring no external components. The clock/data recovery circuitry extracts both phase and frequency from the incoming data stream. The recovered clock is presented on output RXRECCLK at 1/20 of the received serial data rate. The receiver is capable of handling either transition-rich 8B/10B streams or scrambled streams, and can withstand a string of up to 75 non-transitioning bits without an error. Word alignment is dependent on the state of comma detect bits. If comma detect is enabled, the transceiver will recognize up to two 10-bit preprogrammed characters. Upon detection of the character or characters, the comma detect output is driven high and the data is synchronously aligned. If a comma is detected and the data is aligned, no further alignment alteration will take place. If a comma is received and realignment is necessary, the data is realigned and an indication is given at the receiver interface. The realignment indicator is a distinct output. The transceiver will continuously monitor the data for the presence of the 10-bit character(s). Upon each occurrence of the 10-bit character, the data is checked for word alignment. If comma detect is disabled, the data will not be aligned to any particular pattern. The programmable option allows a user to align data on comma+, comma-, both, or a unique user-defined and programmed sequence. The receiver can be configured to reverse the RXP and RXN inputs. This can be useful in the event that printed circuit board traces have been reversed. Receiver Termination On-chip termination is provided at the receiver, eliminating the need for external termination. The receiver includes programmable on-chip termination circuitry for 50 (default) or 75 impedance. 8B/10B Decoder An optional 8B/10B decoder is included. A programmable option allows the decoder to be bypassed. When the 8B/10B decoder is bypassed, the 10-bit character order is, for example, RXCHARISK[0] RXRUNDISP[0] RXDATA[7:0] (first bit received) (last bit received is RXDATA[0]) The decoder uses the same table that is used for Gigabit Ethernet, Fibre Channel, and InfiniBand. In addition to decoding all data and K-characters, the decoder has several extra features. The decoder separately detects both "disparity errors" and "out-of-band" errors. A disparity error is the reception of 10-bit character that exists within the 30 8B/10B table but has an incorrect disparity. An out-of-band error is the reception of a 10-bit character that does not exist within the 8B/10B table. It is possible to obtain an out-of-band error without having a disparity error. The proper disparity is always computed for both legal and illegal characters. The current running disparity is available at the RXRUNDISP signal. The 8B/10B decoder performs a unique operation if out-of-band data is detected. If out-of-band data is detected, the decoder signals the error and passes the illegal 10-bits through and places them on the outputs. This can be used for debugging purposes if desired. The decoder also signals the reception of one of the 12 valid K-characters. In addition, a programmable comma detect is included. The comma detect signal registers a comma on the receipt of any comma+, comma-, or both. Since the comma is defined as a 7-bit character, this includes several out-of-band characters. Another option allows the decoder to detect only the three defined commas (K28.1, K28.5, and K28.7) as comma+, comma-, or both. In total, there are six possible options, three for valid commas and three for "any comma." It should be noted that all bytes (1, 2, or 4) at the RX FPGA interface will each have their own individual 8B/10B indicators (K-character, disparity error, out-of-band error, current running disparity, and comma detect). Loopback In order to facilitate testing without having the need to either apply patterns or measure data at GHz rates, two programmable loop-back features are available. One option, serial loopback, places the gigabit transceiver into a state where transmit data is directly fed back to the receiver. An important point to note is that the feedback path is at the output pads of the transmitter. This tests the entirety of the transmitter and receiver. The second loopback path is a parallel path that checks the digital circuitry. When the parallel option is enabled, the serial loopback path is disabled. However, the transmitter outputs remain active and data is transmitted over a link. If TXINHIBIT is asserted, TXP is forced to 0 until TXINHIBIT is de-asserted. Elastic and Transmitter Buffers Both the transmitter and the receiver include buffers (FIFOs) in the datapath. This section gives the reasons for including the buffers and outlines their operation. Receiver Buffer The receiver buffer is required for two reasons: * * Clock corection to accommodate the slight difference in frequency between the recovered clock RXRECCLK and the internal FPGA user clock RXUSRCLK Channel bonding to allow realignment of the input www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description stream to ensure proper alignment of data being read through multiple transceivers The receiver uses an elastic buffer, where "elastic" refers to the ability to modify the read pointer for clock correction and channel bonding. Clock Correction Clock RXRECCLK (the recovered clock) reflects the data rate of the incoming data. Clock RXUSRCLK defines the rate at which the FPGA fabric consumes the data. Ideally, these rates are identical. However, since the clocks typically have different sources, one of the clocks will be faster than the other. The receiver buffer accommodates this difference between the clock rates. See Figure 3. Read RXUSRCLK Write RXRECCLK "Nominal" condition: buffer half-full Read Write Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer will fill up over time. The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA fabric byte stream. This is shown in the bottom buffer, Figure 3, where the solid read pointer increments to the value represented by the dashed pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design will skip a single byte sequence when necessary to partially empty a buffer. If attribute CLK_COR_REPEAT_WAIT is 0, the transceiver may also skip two consecutive removable byte sequences in one step to further empty the buffer when necessary. These operations require the clock correction logic to recognize a byte sequence that can be freely repeated or omitted in the incoming data stream. This sequence is generally an IDLE sequence, or other sequence comprised of special values that occur in the gaps separating packets of meaningful data. These gaps are required to occur sufficiently often to facilitate the timely execution of clock correction. Channel Bonding Read Buffer less than half -full (emptying) Repeatable sequence Write Some gigabit I/O standards such as Infiniband specify the use of multiple transceivers in parallel for even higher data rates. Words of data are split into bytes, with each byte sent over a separate channel (transceiver). See Figure 4. Buffer more than half-full (filling up) Removable sequence DS083-2_15_100901 In Transmitters: Full word SSSS sent over four channels, one byte per channel Figure 3: Clock Correction in Receiver Nominally, the buffer is always half full. This is shown in the top buffer, Figure 3, where the shaded area represents buffered data not yet read. Received data is inserted via the write pointer under control of RXRECCLK. The FPGA fabric reads data via the read pointer under control of RXUSRCLK. The half full/half empty condition of the buffer gives a cushion for the differing clock rates. This operation continues indefinitely, regardless of whether or not "meaningful" data is being received. When there is no meaningful data to be received, the incoming data will consist of IDLE characters or other padding. If RXUSRCLK is faster than RXRECCLK, the buffer becomes more empty over time. The clock correction logic corrects for this by decrementing the read pointer to reread a repeatable byte sequence. This is shown in the middle buffer, Figure 3, where the solid read pointer decrements to the value represented by the dashed pointer. By decrementing the read pointer instead of incrementing it in the usual fashion, the buffer is partially refilled. The transceiver design will repeat a single repeatable byte sequence when necessary to refill a buffer. If the byte sequence length is greater than one, and if attribute CLK_COR_REPEAT_WAIT is 0, then the transceiver may repeat the same sequence multiple times until the buffer is refilled to the desired extent. DS083-2 (v1.0) January 31, 2002 Advance Product Specification PQRS T Channel (lane) 0 PQRS T Channel (lane) 1 PQRS T Channel (lane) 2 PQRS T Channel (lane) 3 Read RXUSRCLK PQRS T PQRS T In Receivers: Read RXUSRCLK PQRS T PQRS T PQRS T PQRS T PQRS T PQRS T Before channel bonding After channel bonding DS083-2_16_010202 Figure 4: Channel Bonding (Alignment) The top half of the figure shows the transmission of words split across four transceivers (channels or lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the four channels. www.xilinx.com 1-800-255-7778 31 R Functional Description: Rocket I/O Multi-Gigabit Transceiver (MGT) The bottom-left portion of the figure shows the initial situation in the FPGA's receivers at the other end of the four channels. Due to variations in transmission delay--especially if the channels are routed through repeaters--the FPGA fabric may not correctly assemble the bytes into complete words. The bottom-left illustration shows the incorrect assembly of data words PQPP, QRQQ, RSRR, etc. To support correction of this misalignment, the data stream will include special byte sequences that define corresponding points in the several channels. In the bottom half of Figure 4, the shaded "P" bytes represent these special characters. Each receiver recognizes the "P" channel bonding character, and remembers its location in the buffer. At some point, one transceiver designated as the master instructs all the transceivers to align to the channel bonding character "P" (or to some location relative to the channel bonding character). After this operation, the words transmitted to the FPGA fabric will be properly aligned: RRRR, SSSS, TTTT, etc., as shown in the bottom-right portion of Figure 4. To ensure that the channels remain properly aligned following the channel bonding operation, the master transceiver must also control the clock correction operations described in the previous section for all channel-bonded transceivers. Transmitter Buffer The transmitter's buffer write pointer (TXUSRCLK) is frequency-locked to its read pointer (REFCLK). Therefore, clock correction and channel bonding are not required. The purpose of the transmitter's buffer is to accommodate a phase difference between TXUSRCLK and REFCLK. A simple FIFO suffices for this purpose. A FIFO depth of four will permit reliable operation with simple detection of overflow or underflow, which could occur if the clocks are not frequency-locked. CRC The Rocket I/O transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, FibreChannel, and Gigabit Ethernet. On the transmitter side, the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC. For Gigabit Ethernet and FibreChannel, transmitter CRC may adjust certain trailing bytes to generate the required running disparity at the end of the packet. On the receiver side, the CRC logic verifies the received CRC value, supporting the same standards as above. The CRC logic also supports a user mode, with a simple data packet stucture beginning and ending with user-defined SOP and EOP characters. trolled by configuration. Xilinx implementation software supports 16 transceiver primitives, as shown in Table 2. Table 2: Supported Rocket I/O Transceiver Primitives GT_CUSTOM Fully customizable by user GT_FIBRE_CHAN_1 Fibre Channel, 1-byte data path GT_FIBRE_CHAN_2 Fibre Channel, 2-byte data path GT_FIBRE_CHAN_4 Fibre Channel, 4-byte data path GT_ETHERNET_1 Gigabit Ethernet, 1-byte data path GT_ETHERNET_2 Gigabit Ethernet, 2-byte data path GT_ETHERNET_4 Gigabit Ethernet, 4-byte data path GT_XAUI_1 10-gigabit Ethernet, 1-byte data path GT_XAUI_2 10-gigabit Ethernet, 2-byte data path GT_XAUI_4 10-gigabit Ethernet, 4-byte data path GT_INFINIBAND_1 Infiniband, 1-byte data path GT_INFINIBAND_2 Infiniband, 2-byte data path GT_INFINIBAND_4 Infiniband, 4-byte data path GT_AURORA_1 Xilinx protocol, 1-byte data path GT_AURORA_2 Xilinx protocol, 2-byte data path GT_AURORA_4 Xilinx protocol, 4-byte data path Each of the above primitives defines default values for the configuration attributes, allowing some number of them to be modified by the user. Refer to the Rocket I/O User Guide for more details. Reset / Power Down The receiver and transmitter have their own synchronous reset inputs. The transmitter reset recenters the transmission FIFO, and resets all transmitter registers and the 8B/10B decoder. The receiver reset recenters the receiver elastic buffer, and resets all receiver registers and the 8B/10B encoder. Neither reset signal has any effect on the PLLs. The Power Down module is controlled by the POWERDOWN input pin on the transceiver core. The Power down pin on the FPGA package has no effect on the transceiver core. Power Sequencing Although applying power in a random order does not damage the device, it is recommended to apply power in the following sequence to minimize power-on current: 1. Apply FPGA fabric power supplies (VCCINT and VCCAUX) in any order. Configuration 2. Apply AVCCAUXRX. This section outlines functions that may be selected or con- 3. Apply AVCCAUXTX, VTTX, and VTRX in any order. 32 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Functional Description: Processor Block consumption. Specially designed interface logic integrates the core with the surrounding CLBs, block RAMs, and general routing resources. Up to four Processor Blocks can be available in a single Virtex-II Pro device. CPU-FPGA Interfaces BRAM The PPC405 core implements the PowerPC User Instruction Set Architecture (UISA), user-level registers, programming model, data types, and addressing modes for 32-bit fixed-point operations. 64-bit operations, auxiliary processor operations, and floating-point operations are trapped and can be emulated in software. BRAM Most of the PPC405 core features are compatible with the specifications for the PowerPC Virtual Environment Architecture (VEA) and Operating Environment Architecture (OEA). They also provide a number of optimizations and extensions to the lower layers of the PowerPC Architecture. The full architecture of the PPC405 is defined by the PowerPC Embedded Environment and the PowerPC UISA. FPGA CLB Array PPC 405 Core OCM Controller OCM Controller Control On-Chip Memory (OCM) Controllers Introduction BRAM BRAM Interface Logic Processor Block = CPU Core + Interface Logic + CPU-FPGA Interface DS083-2_03a_060701 Figure 5: Processor Block Architecture This section briefly describes the interfaces and components of the Processor Block. The subsequent section, Functional Description: PowerPC 405 Core beginning on page 36, offers a summary of major PPC405 core features. For an in-depth discussion on both Processor Block and PPC405, refer to the Processor Block Manual and the PPC405 User Manual. Processor Block Overview Figure 5 shows the internal architecture of the Processor Block. Within the Virtex-II Pro Processor Block, there are four components: * * * * Embedded IBM PowerPC 405-D5 RISC CPU core On-Chip Memory (OCM) controllers and interfaces Clock/control interface logic CPU-FPGA Interfaces * * * * The PowerPC 405D5 core is a 0.13 m implementation of the IBM PowerPC 405D4 core. The advanced process technology enables the embedded PowerPC 405 (PPC405) core to operate at 300+ MHz while maintaining low power ISBRAM only DSBRAM only Both ISBRAM and DSBRAM No ISBRAM and no DSBRAM One of OCM's primary advantages is that it guarantees a fixed latency of execution for a higher level of determinism. Additionally, it reduces cache pollution and thrashing, since the cache remains available for caching code from other memory resources. Typical applications for DSOCM include scratch-pad memory, as well as use of the dual-port feature of block RAM to enable bidirectional data transfer between processor and FPGA. Typical applications for ISOCM include storage of interrupt service routines. Functional Features Common Features * Embedded PowerPC 405 RISC Core DS083-2 (v1.0) January 31, 2002 Advance Product Specification The OCM controllers serve as dedicated interfaces between the block RAMs in the FPGA fabric (see 18 Kb Block SelectRAM Resources, page 56) and OCM signals available on the embedded PPC405 core. The OCM signals on the PPC405 core are designed to provide very quick access to a fixed amount of instruction and data memory space. The OCM controller provides an interface to both the 64-bit Instruction-Side Block RAM (ISBRAM) and the 32-bit Data-Side Block RAM (DSBRAM). The designer can choose to implement: * * Separate Instruction and Data memory interface between Processor core and BRAMs in FPGA Dedicated interface to Device Control Register (DCR) bus for ISOCM and DSOCM Single-cycle and multi-cycle mode option for I-side and D-side interfaces www.xilinx.com 1-800-255-7778 33 R Functional Description: Processor Block * * * * Single cycle = one clock cycle; multi-cycle = minimum of two and maximum of eight clock cycles FPGA configurable DCR addresses within DSOCM and ISOCM Independent 16 MB logical memory space available within PPC405 memory map for each of the DSOCM and ISOCM. The number of block RAMs in the device may limit the maximum amount of OCM supported. Maximum of 64K and 128K bytes addressable from DSOCM and ISOCM interfaces, respectively, using address outputs from OCM directly without additional decoding logic Data-Side OCM (DSOCM) * * * * * * 32-bit Data Read bus and 32-bit Data Write bus Byte write access to DSBRAM support Second port of dual port DSBRAM is available to read/write from an FPGA interface 22-bit address to DSBRAM port 8-bit DCR Registers: DSCNTL, DSARC Three alternatives to write into DSBRAM: BRAM initialization, CPU, FPGA H/W using second port fore processor signals have the same routability as other non-Processor Block user signals. Longlines and hex lines travel across the Processor Block both vertically and horizontally, allowing signals to route through the Processor Block. Processor Local Bus (PLB) Interfaces The PPC405 core accesses high-speed system resources through PLB interfaces on the instruction and data cache controllers. The PLB interfaces provide separate 32-bit address/64-bit data buses for the instruction and data sides. The cache controllers are both PLB masters. PLB arbiters can be implemented on FPGA fabric and are available as soft IP cores. Device Control Register (DCR) Bus Interface The device control register (DCR) bus has 10 bits of address space for components external to the PPC405 core. Using the DCR bus to manage status and configuration registers reduces PLB traffic and improves system integrity. System resources on the DCR bus are protected or isolated from wayward code since the DCR bus is not part of the system memory map. Instruction-Side OCM (ISOCM) On-Chip Memory (OCM) Interfaces The ISOCM interface contains a 64-bit read only port, for instruction fetches, and a 32-bit write only port, to initialize or test the ISBRAM. When implementing the read only port, the user must deassert the write port inputs. The preferred method of initializing the ISBRAM is through the configuration bitstream. Access to optional, user-configurable direct-mapped memory is through the OCM interfaces. The OCM interfaces can have the same access time as a cache hit, depending on the clock frequency and block RAM size. OCM may be attached to the PPC405 core through the instruction OCM interface and/or the data OCM interface. * * * * * * Instruction side OCM is often used to hold critical code such as an interrupt handler that requires guaranteed low-latency deterministic access. Data side OCM offers the same fixed low-latency access and is used to hold critical data such as filter coefficients for a DSP application or packets for fast processing. Refer to On-Chip Memory (OCM) Controllers, page 33, for more information. 64-bit Data Read Only bus (two instructions per cycle) 32-bit Data Write Only bus (through DCR) Separate 21-bit address to ISBRAM 8-bit DCR Registers: ISCNTL, ISARC 32-bit DCR Registers: ISINIT, ISFILL Two alternatives to write into ISBRAM: BRAM initialization, DCR and write instruction Clock/Control Interface Logic The clock/control interface logic provides proper initialization and connections for PPC405 clock/power management, resets, PLB cycle control, and OCM interfaces. It also couples user signals between the FPGA fabric and the PPC405 CPU core. The processor clock connectivity is similar to CLB clock pins. It can connect either to global clock nets or general routing resources. Therefore the processor clock source can come from DCM, CLB, or user package pin. External Interrupt Controller (EIC) Interface Two level-sensitive user interrupt pins (critical and non-critical) are available. They can be either driven by user defined logic or Xilinx soft interrupt controller IP core outside the Processor Block. Clock/Power Management (CPM) Interface The CPM interface supports several methods of clock distribution and power management.Three modes of operation that reduce power consumption below the normal operational level are available. Reset Interface CPU-FPGA Interfaces All Processor Block user pins link up with the general FPGA routing resources through the CPU-FPGA interface. There- 34 There are three user reset input pins (core, chip, and system) and three user reset output pins for different levels of reset, if required. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description CoreConnectTM Bus Architecture The JTAG port complies with IEEE Std 1149.1, which defines a test access port (TAP) and boundary scan architecture. Extensions to the JTAG interface provide debuggers with processor control that includes stopping, starting, and stepping the PPC405 core. These extensions are compliant with the IEEE 1149.1 specifications for vendor-specific extensions. The Trace port provides instruction execution trace information to an external trace tool. The PPC405 core is capable of back trace and forward trace. Back trace is the tracing of instructions prior to a debug event while forward trace is the tracing of instructions after a debug event. The processor JTAG port can be accessed independently from the FPGA JTAG port, or the two can be programmatically linked together and accessed via the FPGA's dedicated JTAG pins. System Core Arbiter System Core System Core DCR Bus Peripheral Core Bus Bridge Processor Local Bus Peripheral Core On-Chip Peripheral Bus Arbiter Debugging interfaces on the PPC405 core, consisting of the JTAG and Trace ports, offer access to resources internal to the core and assist in software development. The JTAG port provides basic JTAG chip testing functionality as well as the ability for external debug tools to gain control of the processor for debug purposes. The Trace port furnishes programmers with a mechanism for acquiring instruction execution traces. DCR Bus Debug Interface CoreConnect Bus Architecture Instruction Data Processor Block DCR Bus DS083-2_02a_010202 Figure 6: CoreConnect Block Diagram The Processor Block is compatible with the CoreConnectTM bus architecture. Any CoreConnect compliant cores including Xilinx soft IP can integrate with the Processor Block through this high-performance bus architecture implemented on FPGA fabric. The CoreConnect architecture provides three buses for interconnecting Processor Blocks, Xilinx soft IP, third party IP, and custom logic, as shown in Figure 6: * * * Processor Local Bus (PLB) On-Chip Peripheral Bus (OPB) Device Control Register (DCR) bus High-performance peripherals connect to the high-bandwidth, low-latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB, resulting in greater overall system performance. For more information, refer to: http://www-3.ibm.com/chips/techlib/techlib.nfs /productfamilies/CoreConnect_Bus_Architecture/ DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 35 R Functional Description: PowerPC 405 Core PLB Master Interface Instruction OCM MMU I-Cache Array I-Cache Controller Instruction Cache Unit Cache Units Data Cache Unit D-Cache Array D-Cache Controller Instruction Shadow TLB (4 Entry) Fetch & Decode 3-Element Fetch Fetch Queue and Decode (PFB1, PFB0, Logic DCD) (FIT, PIT, Watchdog) Timers & Debug Unified TLB (64 Entry) Data Shadow TLB (8 Entry) Timers Execution Unit (EXU) 32 x 32 GPR ALU Debug Logic MAC Execution Unit PLB Master Interface Data OCM JTAG Instruction Trace DS083-2_01_062001 Figure 7: PPC405 Core Block Diagram Functional Description: PowerPC 405 Core This section offers a brief overview of the various functional blocks shown in Figure 7. PPC405 Core The PPC405 core is a 32-bit Harvard architecture processor. It consists of the following functional blocks as shown in Figure 7: * * * * * * The PPC405 core accesses external memory through the instruction (ICU) and data cache units (DCU). The cache units each include a 64-bit PLB master interface, cache arrays, and a cache controller. The ICU and DCU handle cache misses as requests over the PLB to another PLB device such as an external bus interface unit. Cache hits are handled as single cycle memory accesses to the instruction and data caches. Instruction Cache Unit (ICU) The ICU provides one or two instructions per cycle to the instruction queue over a 64-bit bus. A line buffer (built into the output of the array for manufacturing test) enables the ICU to be accessed only once for every four instructions, to reduce power consumption by the array. Cache units Memory Management unit Fetch Decode unit Execution unit Timers Debug logic unit It operates on instructions in a five stage pipeline consisting of a fetch, decode, execute, write-back, and load write-back stage. Most instructions execute in a single cycle, including loads and stores. The ICU can forward any or all of the four or eight words of a line fill to the EXU to minimize pipeline stalls caused by cache misses. The ICU aborts speculative fetches abandoned by the EXU, eliminating unnecessary line fills and enabling the ICU to handle the next EXU fetch. Aborting abandoned requests also eliminates unnecessary external bus activity, thereby increasing external bus utilization. Instruction and Data Cache Data Cache Unit (DCU) The PPC405 core provides an instruction cache unit (ICU) and a data cache unit (DCU) that allow concurrent accesses and minimize pipeline stalls. The instruction and data cache array are 16 KB each. Both cache units are two-way set associative. Each way is organized into 256 lines of 32 bytes (eight words). The instruction set provides a rich assortment of cache control instructions, including instructions to read tag information and data arrays. The DCU transfers one, two, three, four, or eight bytes per cycle, depending on the number of byte enables presented by the CPU. The DCU contains a single-element command and store data queue to reduce pipeline stalls; this queue enables the DCU to independently process load/store and cache control instructions. Dynamic PLB request prioritization reduces pipeline stalls even further. When the DCU is busy with a low-priority request while a subsequent storage 36 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description operation requested by the CPU is stalled; the DCU automatically increases the priority of the current request to the PLB. The DCU provides additional features that allow the programmer to tailor its performance for a given application. The DCU can function in write-back or write-through mode, as controlled by the Data Cache Write-through Register (DCWR) or the Translation Look-aside Buffer (TLB); the cache controller can be tuned for a balance of performance and memory coherency. Write-on-allocate, controlled by the store word on allocate (SWOA) field of the Core Configuration Register 0 (CCR0), can inhibit line fills caused by store misses, to further reduce potential pipeline stalls and unwanted external bus traffic. Fetch and Decode Logic The PPC405 core has a 4 GB address space, which is presented as a flat address space. The MMU provides address translation, protection functions, and storage attribute control for embedded applications. The MMU supports demand-paged virtual memory and other management schemes that require precise control of logical-to-physical address mapping and flexible memory protection. Working with appropriate system-level software, the MMU provides the following functions: * * * The fetch and decode logic maintains a steady flow of instructions to the execution unit by placing up to two instructions in the fetch queue. The fetch queue consists of three buffers: pre-fetch buffer 1 (PFB1), pre-fetch buffer 0 (PFB0) and decode (DCD). The fetch logic ensures that instructions proceed directly to decode when the queue is empty. Static branch prediction as implemented on the PPC405 core takes advantage of some standard statistical properties of code. Branches with negative address displacement are by default assumed taken. Branches that do not test the condition or count registers are also predicted as taken. The PPC405 core bases branch prediction upon these default conditions when a branch is not resolved and speculatively fetches along the predicted path. The default prediction can be overridden by software at assembly or compile time. Branches are examined in the decode and pre-fetch buffer 0 fetch queue stages. Two branch instructions can be handled simultaneously. If the branch in decode is not taken, the fetch logic fetches along the predicted path of the branch instruction in pre-fetch buffer 0. If the branch in decode is taken, the fetch logic ignores the branch instruction in pre-fetch buffer 0. Execution Unit The PPC405 core has a single issue execution unit (EXU), which contains the register file, arithmetic logic unit (ALU), and the multiply-accumulate (MAC) unit. The execution unit performs all 32-bit PowerPC integer instructions in hardware. The register file is comprised of thirty-two 32-bit general purpose registers (GPR), which are accessed with three read ports and two write ports. During the decode stage, data is read out of the GPRs and fed to the execution unit. Likewise, during the write-back stage, results are written to the GPR. The use of the five ports on the register file enables either a load or a store operation to execute in parallel with an ALU operation. DS083-2 (v1.0) January 31, 2002 Advance Product Specification Memory Management Unit (MMU) * * * Translation of the 4 GB effective address space into physical addresses Independent enabling of instruction and data translation/protection Page-level access control using the translation mechanism Software control of page replacement strategy Additional control over protection using zones Storage attributes for cache policy and speculative memory access control The MMU can be disabled under software control. If the MMU is not used, the PPC405 core provides other storage control mechanisms. Translation Look-Aside Buffer (TLB) The Translation Look-Aside Buffer (TLB) is the hardware resource that controls translation and protection. It consists of 64 entries, each specifying a page to be translated. The TLB is fully associative; a given page entry can be placed anywhere in the TLB. The translation function of the MMU occurs pre-cache. Cache tags and indexing use physical addresses. Software manages the establishment and replacement of TLB entries. This gives system software significant flexibility in implementing a custom page replacement strategy. For example, to reduce TLB thrashing or translation delays, software can reserve several TLB entries in the TLB for globally accessible static mappings. The instruction set provides several instructions used to manage TLB entries. These instructions are privileged and require the software to be executing in supervisor state. Additional TLB instructions are provided to move TLB entry fields to and from GPRs. The MMU divides logical storage into pages. Eight page sizes (1 KB, 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, and 16 MB) are simultaneously supported, such that, at any given time, the TLB can contain entries for any combination of page sizes. In order for a logical to physical translation to exist, a valid entry for the page containing the logical address must be in the TLB. Addresses for which no TLB entry exists cause TLB-Miss exceptions. To improve performance, four instruction-side and eight data-side TLB entries are kept in shadow arrays. The www.xilinx.com 1-800-255-7778 37 R Functional Description: PowerPC 405 Core shadow arrays allow single-cycle address translation and also help to avoid TLB contention between load/store and instruction fetch operations. Hardware manages the replacement and invalidation of shadow-TLB entries; no system software action is required. Memory Protection for system error recovery in the event of software or system lockups. Users may select one of four time periods for the interval and the type of reset generated if the WDT expires twice without an intervening clear from software. If enabled, the watchdog timer generates a reset unless an exception handler updates the WDT status bit before the timer has completed two of the selected timer intervals. When address translation is enabled, the translation mechanism provides a basic level of protection. The Zone Protection Register (ZPR) enables the system software to override the TLB access controls. For example, the ZPR provides a way to deny read access to application programs. The ZPR can be used to classify storage by type; access by type can be changed without manipulating individual TLB entries. Time Base (Incrementer) TBL (32 bits) External Clock Source 0 The PowerPC Architecture provides WIU0GE (write-back / write-through, cacheability, user-defined 0, guarded, endian) storage attributes that control memory accesses, using bits in the TLB or, when address translation is disabled, storage attribute control registers. TBU (32 bits) 31 0 Bit 3 (229 clocks) Bit 7 (225 clocks) Bit 11 (221 clocks) Bit 11 (221 clocks) Bit 15 (217 clocks) Bit 19 (213 clocks) FIT Events Bit 23 (2 9 clocks) PIT (Decrementer) (32 bits) 0 31 Zero Detect Timers PIT Events DS083-2_06_062001 The PPC405 core contains a 64-bit time base and three timers, as shown in Figure 8: Figure 8: Relationship of Timer Facilities to Base Clock Interrupts Programmable Interval Timer (PIT) Fixed Interval Timer (FIT) Watchdog Timer (WDT) The time base counter increments either by an internal signal equal to the CPU clock rate or by a separate external timer clock signal. No interrupts are generated when the time base rolls over. The three timers are synchronous with the time base. The PIT is a 32-bit register that decrements at the same rate as the time base is incremented. The user loads the PIT register with a value to create the desired delay. When the register reaches zero, the timer stops decrementing and generates a PIT interrupt. Optionally, the PIT can be programmed to auto-reload the last value written to the PIT register, after which the PIT continues to decrement. The FIT generates periodic interrupts based on one of four selectable bits in the time base. When the selected bit changes from 0 to 1, the PPC405 core generates a FIT interrupt. The WDT provides a periodic critical-class interrupt based on a selected bit in the time base. This interrupt can be used 38 WDT Events Bit 15 (217 clocks) When address translation is enabled, storage attribute control bits in the TLB control the storage attributes associated with the current page. When address translation is disabled, bits in each storage attribute control register control the storage attributes associated with storage regions. Each storage attribute control register contains 32 fields. Each field sets the associated storage attribute for a 128 MB memory region. * * * 31 The PPC405 provides an interface to an interrupt controller that is logically outside the PPC405 core. This controller combines the asynchronous interrupt inputs and presents them to the core as a single interrupt signal. The sources of asynchronous interrupts are external signals, the JTAG/debug unit, and any implemented peripherals. Debug Logic All architected resources on the PPC405 core can be accessed through the debug logic. Upon a debug event, the PPC405 core provides debug information to an external debug tool. Three different types of tools are supported depending on the debug mode: ROM monitors, JTAG debuggers, and instruction trace tools. In internal (intrusive) debug mode, a debug event enables exception-handling software at a dedicated interrupt vector to take over the CPU core and communicate with a debug tool. The debug tool has read-write access to all registers and can set hardware or software breakpoints. ROM monitors typically use the internal debug mode. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description In external (non-intrusive) debug mode, the CPU core enters stop state (stops instruction execution) when a debug event occurs. This mode offers a debug tool non-intrusive read-write access to all registers in the PPC405 core. Once the CPU core is in stop state, the debug tool can start the CPU core, step an instruction, freeze the timers, or set hardware or software break points. In addition to CPU core control, the debug logic is capable of writing instructions into the instruction cache, eliminating the need for external memory during initial board bring up. Communication to a debug tool using external debug mode is through the JTAG port. Real-time trace debug mode is always enabled. The debug logic continuously broadcasts instruction trace information to the trace port. When a debug event occurs, the debug logic signals an external debug tool to save instruction trace information before and after the event. The number of instructions traced depends on the trace tool. Debug wait mode offers the same functionality as external debug mode with one exception. In debug wait mode, the CPU core goes into wait state instead of stop state after a debug event. Wait state is identical to stop state until an interrupt occurs. In wait state, the PPC405 core can vector to an exception handler, service an interrupt and return to wait state. This mode is particularly useful when debugging real time control systems. The PPC405 core supports big endian or little endian byte ordering for instructions stored in external memory. Since the PowerPC architecture is big endian internally, the ICU rearranges the instructions stored as little endian into the big endian format. Therefore, the instruction cache always contains instructions in big endian format so that the byte ordering is correct for the execution unit. This feature allows the 405 core to be used in systems designed to function in a little endian environment. Functional Description: FPGA standard used. For exact supply voltage absolute maximum ratings, see Virtex-II Pro Platform FPGAs: DC and Switching Characteristics (Module 3). Input/Output Blocks (IOBs) Virtex-II Pro I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as input and/or output for single-ended I/Os. Two IOBs can be used as a differential pair. A differential pair is always connected to the same switch matrix, as shown in Figure 9. Debug events signal the debug logic to stop the CPU core, put the CPU core in debug wait state, cause a debug exception or save instruction trace information. Big Endian and Little Endian Support Table 3: Supported Single-Ended I/O Standards Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS33 3.3 3.3 N/A N/A IOB PAD3 LVCMOS25 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A IOB PAD2 LVCMOS15 1.5 1.5 N/A N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A GTL Note (1) Note (1) 0.8 1.2 GTLP Note (1) Note (1) 1.0 1.5 IOB PAD4 I/O Standard Differential Pair Switch Matrix Differential Pair IOB PAD1 DS083-2_30_010202 Figure 9: Virtex-II Pro Input/Output Tile IOB blocks are designed for high-performance I/Os, supporting 22 single-ended standards, as well as differential signaling with LVDS, LDT, and bus LVDS. HSTL_I 1.5 N/A 0.75 0.75 HSTL_II 1.5 N/A 0.75 0.75 HSTL_III 1.5 N/A 0.9 1.5 Supported I/O Standards HSTL_IV 1.5 N/A 0.9 1.5 Virtex-II Pro IOB blocks feature SelectI/O inputs and outputs that support a wide variety of I/O signaling standards. In addition to the internal supply voltage (VCCINT = 1.5V), output driver supply voltage (VCCO) is dependent on the I/O standard (see Table 3 and Table 4). An auxiliary supply voltage (VCCAUX = 2.5V) is required, regardless of the I/O HSTL_I_18 1.8 N/A 0.9 0.9 HSTL_II_18 1.8 N/A 0.9 0.9 HSTL_III _18 1.8 N/A 1.08 1.8 HSTL_IV_18 1.8 N/A 1.08 1.8 DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 39 R Functional Description: FPGA Table 3: Supported Single-Ended I/O Standards Table 5: Supported DCI I/O Standards (Continued) Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) SSTL2_I 2.5 N/A 1.25 1.25 SSTL2_II 2.5 N/A 1.25 1.25 SSTL3_I 3.3 N/A 1.5 1.5 SSTL3_II 3.3 N/A 1.5 1.5 I/O Standard Notes: 1. VCCO of GTL or GTLP should not be lower than the termination voltage or the voltage seen at the I/O pad. Table 4: Supported Differential Signal I/O Standards I/O Standard Output VCCO Input VCCO Input VREF Output VOD LDT_25 2.5 N/A N/A 0.500 - 0.740 LVDS_25 2.5 N/A N/A 0.250 - 0.400 LVDSEXT_25 2.5 N/A N/A 0.330 - 0.700 BLVDS_25 2.5 N/A N/A 0.250 - 0.450 ULVDS_25 2.5 N/A N/A I/O Standard Output VCCO Input VCCO Input VREF Termination Type HSTL_I_DCI_18 1.8 1.8 0.9 Split HSTL_II_DCI_18 1.8 1.8 0.9 Split HSTL_III_DCI_18 1.8 1.8 1.08 Single HSTL_IV_DCI_18 1.8 1.8 1.08 Single SSTL2_I_DCI (2) 2.5 2.5 1.25 Split SSTL2_II_DCI (2) 2.5 2.5 1.25 Split SSTL3_I_DCI (2) 3.3 3.3 1.5 Split SSTL3_II_DCI (2) 3.3 3.3 1.5 Split Notes: 1. LVDCI_XX is LVCMOS controlled impedance buffers, matching the reference resistors or half of the reference resistors. 2. These are SSTL compatible. IOB DDR mux Input Reg 0.500 - 0.740 OCK1 Reg ICK1 All of the user IOBs have fixed-clamp diodes to VCCO and to ground. The IOBs are not compatible or compliant with 5V I/O standards (not 5V tolerant). Reg OCK2 Table 5 lists supported I/O standards with Digitally Controlled Impedance. See Digitally Controlled Impedance (DCI), page 44. 3-State Reg ICK2 DDR mux Reg Table 5: Supported DCI I/O Standards I/O Standard OCK1 PAD Output VCCO Input VCCO Input VREF Termination Type LVDCI_33 (1) 3.3 3.3 N/A Series LVDCI_25 2.5 2.5 N/A Series LVDCI_DV2_25 2.5 2.5 N/A Series LVDCI_18 1.8 1.8 N/A Series LVDCI_DV2_18 1.8 1.8 N/A Series Logic Resources LVDCI_15 1.5 1.5 N/A Series LVDCI_DV2_15 1.5 1.5 N/A Series IOB blocks include six storage elements, as shown in Figure 10. GTL_DCI 1.2 1.2 0.8 Single GTLP_DCI 1.5 1.5 1.0 Single HSTL_I_DCI 1.5 1.5 0.75 Split HSTL_II_DCI 1.5 1.5 0.75 Split HSTL_III_DCI 1.5 1.5 0.9 Single HSTL_IV_DCI 1.5 1.5 0.9 Single 40 Reg OCK2 Output DS031_29_100900 Figure 10: Virtex-II Pro IOB Block Each storage element can be configured either as an edge-triggered D-type flip-flop or as a level-sensitive latch. On the input, output, and 3-state path, one or two DDR registers can be used. Double data rate is directly accomplished by the two registers on each path, clocked by the rising edges (or falling edges) from two different clock nets. The two clock signals are generated by the DCM and must be 180 degrees out of phase, as shown in Figure 11. There are two input, output, and 3-state data signals, each being alternately clocked out. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description This DDR mechanism can be used to mirror a copy of the clock on the output. This is useful for propagating a clock along the data that has an identical delay. It is also useful for multiple clock generation, where there is a unique clock driver for every clock load. Virtex-II Pro devices can produce many copies of a clock with very little skew. DCM DCM 0 180 0 FDDR FDDR D1 D1 Q1 Q1 CLK1 CLK1 DDR MUX Q DDR MUX D2 Q D2 Q2 Q2 CLK2 CLK2 DS083-2_26_122001 Figure 11: Double Data Rate Registers Each group of two registers has a clock enable signal (ICE for the input registers, OCE for the output registers, and TCE for the 3-state registers). The clock enable signals are active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. For each storage element, the SRHIGH, SRLOW, INIT0, and INIT1 attributes are independent. Synchronous or asynchronous set / reset is consistent in an IOB block. Each IOB block has common synchronous or asynchronous set and reset (SR and REV signals). Each register or latch, independent of all other registers or latches, can be configured as follows: SR forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic 1. SRLOW forces a logic "0". When SR is used, a second input (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition. The initial state after configuration or global initialization state is defined by a separate INIT0 and INIT1 attribute. By default, the SRLOW attribute forces INIT0, and the SRHIGH attribute forces INIT1. * * * * * * * All the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed. No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear) The synchronous reset overrides a set, and an asynchronous clear overrides a preset. Refer to Figure 12. DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 41 R Functional Description: FPGA (O/T) 1 FF LATCH D1 (O/T) CE Q1 Attribute INIT1 INIT0 SRHIGH SRLOW CE CK1 SR REV (O/T) CLK1 SR Shared by all registers REV FF1 DDR MUX FF2 (OQ or TQ) FF LATCH D2 Q2 CE CK2 SR REV (O/T) CLK2 Attribute INIT1 INIT0 SRHIGH SRLOW (O/T) 2 Reset Type SYNC ASYNC DS031_25_110300 Figure 12: Register / Latch Configuration in an IOB Block Input/Output Individual Options VCCO Each device pad has optional pull-up/pull-down resistors and weak-keeper circuit in the LVCMOS SelectI/O configuration, as illustrated in Figure 13. Values of the optional pull-up and pull-down resistors fall within a range of 40 K to 120 K when VCCO = 2.5V (from 2.38V to 2.63V only). The clamp diode is always present, even when power is not. Clamp Diode OBUF VCCO Program Current Weak Keeper 40K - 120K PAD VCCO 40K - 120K VCCAUX = 2.5V VCCINT = 1.5V Program Delay IBUF The optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low. If the pin is connected to a multiple-source signal, the weak-keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. An enabled pull-up or pull-down overrides the weak-keeper circuit. DS083-2_07_101801 Figure 13: LVCMOS SelectI/O Standard 42 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description LVTTL sinks and sources current up to 24 mA. The current is programmable for LVTTL and LVCMOS SelectI/O standards (see Table 6). Drive strength and slew rate controls for each output driver minimize bus transients. For LVDCI and LVDCI_DV2 standards, drive strength and slew rate controls are not available. Table 6: LVTTL and LVCMOS Programmable Currents (Sink and Source) SelectI/O Programmable Current (Worst-Case Guaranteed Minimum) LVTTL 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS33 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS25 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA LVCMOS18 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a LVCMOS15 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA n/a Figure 14 shows the SSTL2 and HSTL configurations. HSTL can sink current up to 48 mA. (HSTL IV) VCCO Clamp Diode OBUF Input Path The Virtex-II Pro IOB input path routes input signals directly to internal logic and / or through an optional input flip-flop or latch, or through the DDR input registers. An optional delay element at the D-input of the storage element eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the Virtex-II Pro device, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signaling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in the same bank. See I/O banking description. PAD Output Path VREF VCCAUX = 2.5V VCCINT = 1.5V DS031_24_100900 Figure 14: SSTL or HSTL SelectI/O Standards All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. Virtex-II Pro uses two memory cells to control the configuration of an I/O as an input. This is to reduce the probability of an I/O configured as an input from flipping to an output when subjected to a single event upset (SEU) in space applications. Prior to configuration, all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive. The dedicated pin HSWAP_EN controls the pull-up resistors prior to configuration. By default, HSWAP_EN is set High, which disables the pull-up resistors on user I/O pins. When HSWAP_EN is set Low, the pull-up resistors are activated on user I/O pins. All Virtex-II Pro IOBs (except Rocket I/O pins) support IEEE 1149.1 and IEEE 1532 compatible boundary scan testing. DS083-2 (v1.0) January 31, 2002 Advance Product Specification The output path includes a 3-state output buffer that drives the output signal onto the pad. The output and / or the 3-state signal can be routed to the buffer directly from the internal logic or through an output / 3-state flip-flop or latch, or through the DDR output / 3-state registers. Each output driver can be individually programmed for a wide range of low-voltage signaling standards. In most signaling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in the same bank. See I/O banking description. I/O Banking Some of the I/O standards described above require VCCO and VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOB blocks, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from dividing each edge of the FPGA into two banks, as shown in Figure 15 and Figure 16. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. www.xilinx.com 1-800-255-7778 43 R Functional Description: FPGA Table 7: Compatible Output Standards Bank 5 Figure 15: Virtex-II Pro I/O Banks: Top View for Wire-Bond Packages (CS, FG, and BG) Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 7. GTL and GTLP appear under all voltages because their open-drain outputs do not depend on VCCO. Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this role. 2.5V SSTL2 (I & II), LVCMOS25, GTL, GTLP, LVDS_25, LVDSEXT_25, LVDCI_25, LVDCI_DV2_25, SSTL2_DCI (I & II), LDT, ULVDS, BLVDS 1.8V HSTL (I, II, III, & IV), HSTL_DCI (I,II, III & IV), LVCMOS18, GTL, GTLP, LVDCI_18, LVDCI_DV2_18 1.5V HSTL (I, II, III, & IV), HSTL_DCI (I,II, III & IV), LVCMOS15, GTL, GTLP, LVDCI_15, LVDCI_DV2_15, GTLP_DCI 1.2V GTL_DCI Bank 2 Bank 7 Bank 6 Notes: 1. LVPECL, LVDS_33, LVDSEXT_33, and AGP-2X are not supported. 2. Perfect impedance matching is required for 3.3V standards. 3. For optimum performance, it is recommended that PCI be used in conjunction with LVDCI_33. Contact Xilinx for more details. Digitally Controlled Impedance (DCI) Today's chip output signals with fast edge rates require termination to prevent reflections and maintain signal integrity. High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Bank 5 ds031_66_112900 Figure 16: Virtex-II Pro I/O Banks: Top View for Flip-Chip Packages (FF and BF) VREF pins within a bank are interconnected internally, and consequently only one VREF voltage can be used within each bank. However, for correct operation, all VREF pins in the bank must be connected to the external reference voltage source. The VCCO and the VREF pins for each bank appear in the device pinout tables. Within a given package, the number of VREF and VCCO pins can vary depending on the size of 44 PCI (3), LVTTL, SSTL3 (I & II), LVCMOS33, LVDCI_33, SSTL3_DCI (I & II) (1) All VREF pins for the largest device anticipated must be connected to the VREF voltage and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or, if necessary, they can be connected to the VCCO voltage to permit migration to a larger device. Bank 0 Bank 3 Bank 4 3.3V (2) Bank 4 ug002_c2_014_112900 Bank 1 Compatible Standards (1) VCCO Bank 3 Bank 6 Bank 2 Bank 1 Bank 7 Bank 0 device. In larger devices, more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. Virtex-II Pro DCI provides controlled impedance drivers and on-chip termination for single-ended I/Os. This eliminates the need for external resistors, and improves signal integrity. The DCI feature can be used on any IOB by selecting one of the DCI I/O standards. When applied to inputs, DCI provides input parallel termination. When applied to outputs, DCI provides controlled impedance drivers (series termination) or output parallel termination. DCI operates independently on each I/O bank. When a DCI I/O standard is used in a particular I/O bank, external reference resistors must be connected to two dual-function pins www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description on the bank. These resistors, voltage reference of N transistor (VRN) and the voltage reference of P transistor (VRP) are shown in Figure 17. Table 8: SelectI/O Controlled Impedance Buffers VCCO DCI DCI Half Impedance 3.3V LVDCI_33 N/A DCI 2.5V LVDCI_25 LVDCI_DV2_25 DCI 1.8V LVDCI_18 LVDCI_DV2_18 1.5V LVDCI_15 LVDCI_DV2_15 1 Bank DCI Controlled Impedance Terminations (Parallel Termination) DCI VCCO DCI also provides on-chip termination for SSTL3, SSTL2, HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or transmitters on bidirectional lines. RREF (1%) VRN Table 9 lists the on-chip parallel terminations available in Virtex-II Pro devices. VCCO must be set according to Table 5. Note that there is a VCCO requirement for GTL_DCI and GTLP_DCI, due to the on-chip termination resistor. VRP RREF (1%) GND Table 9: SelectI/O Buffers With On-Chip Parallel Termination DS031_50_101200 Figure 17: DCI in a Virtex-II Pro Bank When used with a terminated I/O standard, the value of the resistors are specified by the standard (typically 50). When used with a controlled impedance driver, the resistors set the output impedance of the driver within the specified range (20 to 100). For all series and parallel terminations listed in Table 8 and Table 9, the reference resistors must have the same value for any given bank. One percent resistors are recommended. The DCI system adjusts the I/O impedance to match the two external reference resistors, or half of the reference resistors, and compensates for impedance changes due to voltage and/or temperature fluctuations. The adjustment is done by turning parallel transistors in the IOB on or off. Controlled Impedance Drivers (Series Termination) External Termination On-Chip Termination SSTL3 Class I SSTL3_I SSTL3_I_DCI (1) SSTL3 Class II SSTL3_II SSTL3_II_DCI (1) SSTL2 Class I SSTL2_I SSTL2_I_DCI (1) SSTL2 Class II SSTL2_II SSTL2_II_DCI (1) HSTL_I HSTL_I_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II HSTL_II_DCI HSTL_II_18 HSTL_II_DCI_18 HSTL_III HSTL_III_DCI HSTL_III_18 HSTL_III_DCI_18 HSTL_IV HSTL_IV_DCI HSTL_IV_18 HSTL_IV_DCI_18 GTL GTL GTL_DCI GTLP GTLP GTLP_DCI HSTL Class I HSTL Class II HSTL Class III DCI can be used to provide a buffer with a controlled output impedance. It is desirable for this output impedance to match the transmission line impedance (Z0). Virtex-II Pro input buffers also support LVDCI and LVDCI_DV2 I/O standards. HSTL Class IV Notes: 1. SSTL Compatible IOB Z I/O Standard Z Virtex-II Pro DCI VCCO = 3.3V, 2.5 V, 1.8 V, or 1.5 V DS083-2_09_122001 Figure 18: Internal Series Termination DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 45 R Functional Description: FPGA Figure 19 provides examples illustrating the use of the HSTL_IV_DCI, HSTL_II_DCI, and SSTL2_DCI I/O standards. HSTL_IV VCCO HSTL_II VCCO/2 VCCO R R R SSTL2_I VCCO/2 VCCO/2 R R Z0 Z0 Z0 HSTL_IV_DCI Transmitter HSTL_II_DCI Transmitter VCCO VCCO VCCO R R VCCO/2 VCCO/2 2R R R Z0 Z0 Z0 2R Virtex-II Pro DCI Virtex-II Pro DCI Virtex-II Pro DCI VCCO VCCO/2 VCCO Z0 HSTL_IV_DCI Transmitter and Receiver HSTL_II_DCI Transmitter and Receiver VCCO R 2R Virtex-II Pro DCI 2R Virtex-II Pro DCI Virtex-II Pro DCI R 2R 2R Z0 Z0 VCCO VCCO VCCO R R R SSTL2_I_DCI Receiver HSTL_II_DCI Receiver HSTL_IV_DCI Receiver SSTL2_I_DCI Transmitter and Receiver VCCO VCCO VCCO 2R 2R 2R Z0 Z0 Z0 2R Virtex-II Pro DCI SSTL2_I_DCI Transmitter Virtex-II Pro DCI 2R Virtex-II Pro DCI Virtex-II Pro DCI Virtex-II Pro DCI 2R Virtex-II Pro DCI DS083-2_08_122001 Figure 19: DCI Usage Examples 46 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Configurable Logic Blocks (CLBs) Slice Description The Virtex-II Pro configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the general routing matrix, as shown in Figure 20. A CLB element comprises 4 similar slices, with fast local feedback within the CLB. The four slices are split in two columns of two slices with two independent carry logic chains and one common shift chain. Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. As shown in Figure 21, each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM memory, or a 16-bit variable-tap shift register element. ORCY RAM16 COUT TBUF TBUF Switch Matrix MUXFx Slice X1Y1 SRL16 LUT G Slice X1Y0 COUT Slice X0Y0 Register/ Latch RAM16 MUXF5 SHIFT Slice X0Y1 CY CIN SRL16 Fast Connects to neighbors LUT F CY Register/ Latch Arithmetic Logic CIN DS083-2_32_122001 DS083-2_31_122001 Figure 20: Virtex-II Pro CLB Element DS083-2 (v1.0) January 31, 2002 Advance Product Specification Figure 21: Virtex-II Pro Slice Configuration www.xilinx.com 1-800-255-7778 47 R Functional Description: FPGA The output from the function generator in each slice drives both the slice output and the D input of the storage element. Figure 22 shows a more detailed view of a single slice. COUT SHIFTIN ORCY SOPIN SOPOUT 0 Dual-Port Shift-Reg G4 G3 G2 G1 WG4 WG3 WG2 WG1 A4 LUT A3 RAM A2 ROM A1 D WG4 G WG3 WG2 MC15 WG1 WS DI YBMUX I YB MUXCY O I GYMUX Y DY XORG FF LATCH ALTDIG MULTAND 1 0 DYMUX G2 PROD G1 CYOG BY CE CLK D Q Q Y CE CK SR REV BY SLICEWE[2:0] WSG WE[2:0] WE CLK SR SHIFTOUT DIG MUXCY I O WSF CE CLK Shared between x & y Registers SR CIN DS031_01_110600 Figure 22: Virtex-II Pro Slice (Top Half) Configurations input of the storage element, or go to the MUXF5 (not shown in Figure 22). Look-Up Table Virtex-II Pro function generators are implemented as 4-input look-up tables (LUTs). Four independent inputs are provided to each of the two function generators in a slice (F and G). These function generators are each capable of implementing any arbitrarily defined boolean function of four inputs. The propagation delay is therefore independent of the function implemented. Signals from the function generators can exit the slice (X or Y output), can input the XOR dedicated gate (see arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the D 48 In addition to the basic LUTs, the Virtex-II Pro slice contains logic (MUXF5 and MUXFX multiplexers) that combines function generators to provide any function of five, six, seven, or eight inputs. The MUXFX is either MUXF6, MUXF7, or MUXF8 according to the slice considered in the CLB. Selected functions up to nine inputs (MUXF5 multiplexer) can be implemented in one slice. The MUXFX can also be a MUXF6, MUXF7, or MUXF8 multiplexer to map any function of six, seven, or eight inputs and selected wide logic functions. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Register/Latch The storage elements in a Virtex-II Pro slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D input can be directly driven by the X or Y output via the DX or DY input, or by the slice inputs bypassing the function generators via the BX or BY input. The clock enable signal (CE) is active High by default. If left unconnected, the clock enable for that storage element defaults to the active state. In addition to clock (CK) and clock enable (CE) signals, each slice has set and reset signals (SR and BY slice inputs). SR forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic 1 when SR is asserted. SRLOW forces a logic 0. When SR is used, an optional second input (BY) forces the storage element into the opposite state via the REV pin. The reset condition is predominant over the set condition. (See Figure 23.) The initial state after configuration or global initial state is defined by a separate INIT0 and INIT1 attribute. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. For each slice, set and reset can be set to be synchronous or asynchronous. Virtex-II Pro devices also have the ability to set INIT0 and INIT1 independent of SRHIGH and SRLOW. The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both storage elements in one slice. All of the control signals have independent polarity. Any inverter placed on a control input is automatically absorbed. FFY FF LATCH DY D Q CE CK SR REV BY DX CE CLK SR BX D YQ Attribute INIT1 INIT0 SRHIGH SRLOW The set and reset functionality of a register or a latch can be configured as follows: * * * * * * * No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear) The synchronous reset has precedence over a set, and an asynchronous clear has precedence over a preset. Distributed SelectRAM Memory Each function generator (LUT) can implement a 16 x 1-bit synchronous RAM resource called a distributed SelectRAM element. The SelectRAM elements are configurable within a CLB to implement the following: * * * * * * * Single-Port 16 x 8-bit RAM Single-Port 32 x 4-bit RAM Single-Port 64 x 2-bit RAM Single-Port 128 x 1-bit RAM Dual-Port 16 x 4-bit RAM Dual-Port 32 x 2-bit RAM Dual-Port 64 x 1-bit RAM Distributed SelectRAM memory modules are synchronous (write) resources. The combinatorial read access time is extremely fast, while the synchronous write simplifies high-speed designs. A synchronous read can be implemented with a storage element in the same slice. The distributed SelectRAM memory and the storage element share the same clock input. A Write Enable (WE) input is active High, and is driven by the SR input. Table 10 shows the number of LUTs (2 per slice) occupied by each distributed SelectRAM configuration. Table 10: Distributed SelectRAM Configurations RAM Number of LUTs 16 x 1S 1 FFX 16 x 1D 2 FF LATCH 32 x 1S 2 32 x 1D 4 64 x 1S 4 64 x 1D 8 128 x 1S 8 Q CE CK SR REV XQ Attribute INIT1 INIT0 SRHIGH SRLOW Reset Type SYNC ASYNC Notes: 1. S = single-port configuration; D = dual-port configuration DS083-2_22_122001 Figure 23: Register / Latch Configuration in a Slice DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 49 R Functional Description: FPGA For single-port configurations, distributed SelectRAM memory has one address port for synchronous writes and asynchronous reads. For dual-port configurations, distributed SelectRAM memory has one port for synchronous writes and asynchronous reads and another port for asynchronous reads. The function generator (LUT) has separated read address inputs (A1, A2, A3, A4) and write address inputs (WG1/WF1, WG2/WF2, WG3/WF3, WG4/WF4). RAM 16x1D 4 DPRA[3:0] 4 A[3:0] dual_port RAM G[4:1] D DPO WG[4:1] WS DI (BY) D In single-port mode, read and write addresses share the same address bus. In dual-port mode, one function generator (R/W port) is connected with shared read and write addresses. The second function generator has the A inputs (read) connected to the second read-only port address and the W inputs (write) shared with the first read/write port address. WSG WE CK Figure 24, Figure 25, and Figure 26 illustrate various example configurations. 4 A[3:0] dual_port RAM G[4:1] D SPO WG[4:1] WS DI RAM 16x1S A[3:0] 4 D (SR) WE CK Registered Output Q DI (BY) DS031_04_110100 Figure 26: Dual-Port Distributed SelectRAM (RAM16x1D) (optional) WSG WE WCLK WE WCLK Output D WG[4:1] WS D WSG RAM A[4:1] 4 (SR) WE CK DS031_02_100900 Figure 24: Distributed SelectRAM (RAM16x1S) Similar to the RAM configuration, each function generator (LUT) can implement a 16 x 1-bit ROM. Five configurations are available: ROM16x1, ROM32x1, ROM64x1, ROM128x1, and ROM256x1. The ROM elements are cascadable to implement wider or/and deeper ROM. ROM contents are loaded at configuration. Table 11 shows the number of LUTs occupied by each configuration. RAM 32x1S A[4] Table 11: ROM Configuration (BX) 4 A[3:0] RAM G[4:1] D WG[4:1] WS D WE WCLK WSG WE0 WE CK WSF 4 Number of LUTs 16 x 1 1 32 x 1 2 64 x 1 4 128 x 1 8 (1 CLB) 256 x 1 16 (2 CLBs) DI (BY) (SR) ROM WS DI RAM D Output F5MUX D Registered Output Q (optional) F[4:1] Shift Registers WF[4:1] DS083-2_10_050901 Figure 25: Single-Port Distributed SelectRAM (RAM32x1S) 50 Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 27. A dynamic read access is performed through the 4-bit address bus, A[3:0]. The configurable 16-bit shift regis- www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description ter cannot be set or reset. The read is asynchronous; however, the storage element or flip-flop is available to implement a synchronous read. Any of the 16 bits can be read out asynchronously by varying the address. The storage element should always be used with a constant address. For example, when building an 8-bit shift register and configuring the addresses to point to the 7th bit, the 8th bit can be the flip-flop. The overall system performance is improved by using the superior clock-to-out of the flip-flops. 1 Shift Chain in CLB DI D SRLC16 MC15 IN DI D SRLC16 MC15 FF FF SLICE S3 SRLC16 SHIFTIN SHIFTOUT SHIFT-REG A[3:0] 4 A[4:1] SHIFTIN Output D MC15 D WS Q DI Registered Output DI D SRLC16 MC15 FF DI D SRLC16 MC15 FF D(BY) WSG CE (SR) CLK (optional) WE CK SLICE S2 SHIFTOUT SHIFTOUT DS031_05_110600 SHIFTIN Figure 27: Shift Register Configurations An additional dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the ordinary LUT output. (See Figure 28.) Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the MUXF5, MUXF6, and MUXF7 multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one CLB. DI D SRLC16 MC15 FF DI D SRLC16 MC15 FF SLICE S1 SHIFTOUT SHIFTIN DI D SRLC16 MC15 FF DI D SRLC16 MC15 FF SLICE S0 OUT CLB CASCADABLE OUT DS031_06_110200 Figure 28: Cascadable Shift Register DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 51 R Functional Description: FPGA Multiplexers Virtex-II Pro function generators and associated multiplexers can implement the following: 4:1 multiplexer in one slice 8:1 multiplexer in two slices 16:1 multiplexer in one CLB element (4 slices) 32:1 multiplexer in two CLB elements (8 slices) F8 * * * * Each Virtex-II Pro slice has one MUXF5 multiplexer and one MUXFX multiplexer. The MUXFX multiplexer implements the MUXF6, MUXF7, or MUXF8, as shown in Figure 29. Each CLB element has two MUXF6 multiplexers, one MUXF7 multiplexer and one MUXF8 multiplexer. Examples of multiplexers are shown in the Virtex-II Pro User Guide. Any LUT can implement a 2:1 multiplexer. G F5 Slice S3 MUXF8 combines the two MUXF7 outputs (Two CLBs) F6 F G F5 Slice S2 MUXF6 combines the two MUXF5 outputs from slices S2 and S3 F7 F F5 G Slice S1 MUXF7 combines the two MUXF6 outputs from slices S0 and S2 Slice S0 MUXF6 combines the two MUXF6 outputs from slices S0 and S1 F6 F F5 G F CLB DS031_08_110200 Figure 29: MUXF5 and MUXFX multiplexers Fast Lookahead Carry Logic Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-II Pro CLB has two separate carry chains, as shown in the Figure 30. 52 The height of the carry chains is two bits per slice. The carry chain in the Virtex-II Pro device is running upward. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description COUT to S0 of the next CLB COUT to CIN of S2 of the next CLB O I MUXCY FF LUT (First Carry Chain) SLICE S3 O I MUXCY FF LUT CIN COUT O I MUXCY FF LUT SLICE S2 O I O I MUXCY MUXCY FF LUT FF LUT O I SLICE S1 MUXCY FF LUT CIN COUT O I (Second Carry Chain) MUXCY FF LUT O I SLICE S0 MUXCY FF LUT CIN CIN CLB DS031_07_110200 Figure 30: Fast Carry Logic Path Arithmetic Logic The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, DS083-2 (v1.0) January 31, 2002 Advance Product Specification a dedicated AND (MULT_AND) gate (shown in Figure 22) improves the efficiency of multiplier implementation. www.xilinx.com 1-800-255-7778 53 R Functional Description: FPGA implementing large, flexible SOP chains. One input of each ORCY is connected through the fast SOP chain to the output of the previous ORCY in the same slice row. The second input is connected to the output of the top MUXCY in the same slice, as shown in Figure 31. Sum of Products Each Virtex-II Pro slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain are designed for ORCY ORCY ORCY ORCY SOP 4 LUT MUXCY 4 LUT Slice 1 4 LUT MUXCY 4 LUT MUXCY LUT MUXCY MUXCY LUT Slice 3 4 LUT MUXCY 4 LUT MUXCY Slice 0 4 4 LUT VCC LUT MUXCY Slice 1 4 LUT MUXCY 4 LUT MUXCY Slice 2 4 MUXCY 4 Slice 3 4 LUT MUXCY 4 LUT MUXCY Slice 0 4 MUXCY LUT VCC MUXCY Slice 2 4 LUT MUXCY VCC VCC CLB CLB ds031_64_110300 Figure 31: Horizontal Cascade Chain LUTs and MUXCYs can implement large AND gates or other combinatorial logic functions. Figure 32 illustrates LUT and MUXCY resources configured as a 16-input AND gate. OUT 4 MUXCY 0 1 LUT "0" 4 Slice MUXCY LUT 0 1 "0" 16 4 AND OUT MUXCY 0 1 LUT "0" 4 Slice MUXCY LUT 0 1 VCC DS031_41_110600 Figure 32: Wide-Input AND Gate (16 Inputs) 54 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description 3-State Buffers The 3-state buffer logic is implemented using AND-OR logic rather than 3-state drivers, so that timing is more predictable and less load dependant especially with larger devices. Introduction Each Virtex-II Pro CLB contains two 3-state drivers (TBUFs) that can drive on-chip buses. Each 3-state buffer has its own 3-state control pin and its own input pin. Each of the four slices have access to the two 3-state buffers through the switch matrix, as shown in Figure 33. TBUFs in neighboring CLBs can access slice outputs by direct connects. The outputs of the 3-state buffers drive horizontal routing resources used to implement 3-state buses. Locations / Organization Four horizontal routing resources per CLB are provided for on-chip 3-state buses. Each 3-state buffer has access alternately to two horizontal lines, which can be partitioned as shown in Figure 34. The switch matrices corresponding to SelectRAM memory and multiplier or I/O blocks are skipped. Number of 3-State Buffers Table 12 shows the number of 3-state buffers available in each Virtex-II Pro device. The number of 3-state buffers is twice the number of CLB elements. TBUF TBUF Slice S3 Switch Matrix Table 12: Virtex-II Pro 3-State Buffers 3-State Buffers per Row Total Number of 3-State Buffers XC2VP2 44 704 XC2VP4 44 1,760 XC2VP7 68 2,720 Slice S2 Device Slice S1 Slice S0 DS031_37_060700 XC2VP20 92 5,152 XC2VP50 140 12,320 Figure 33: Virtex-II Pro 3-State Buffers 3 - state lines Programmable connection Switch matrix CLB-II Switch matrix CLB-II DS031_09_032700 Figure 34: 3-State Buffer Connection to Horizontal Lines CLB/Slice Configurations Table 13 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be imple- mented in one of the configurations listed. Table 14 shows the available resources in all CLBs. Table 13: Logic Resources in One CLB Slices LUTs Flip-Flops MULT_ANDs Arithmetic & Carry-Chains SOP Chains Distributed SelectRAM Shift Registers TBUF 4 8 8 8 2 2 128 bits 128 bits 2 DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 55 R Functional Description: FPGA Table 14: Virtex-II Pro Logic Resources Available in All CLBs Number of LUTs Max Distributed SelectRAM or Shift Register (bits) Number of Flip-Flops Number of Carry Chains (1) Number of SOP Chains (1) 1,408 2,816 45,056 2,816 44 32 40 x 22 3,008 6,016 96,256 6,016 44 80 XC2VP7 40 x 34 4,928 9,856 157,696 9,856 68 80 XC2VP20 56 x 46 9,280 18,560 296,960 18,560 92 112 XC2VP50 88 x 70 22,592 45,184 722,944 45,184 140 176 CLB Array: Row x Column Number of Slices XC2VP2 16 x 22 XC2VP4 Device Notes: 1. The carry-chains and SOP chains can be split or cascaded. 18 Kb Block SelectRAM Resources Introduction Virtex-II Pro devices incorporate large amounts of 18 Kb block SelectRAM. These complement the distributed SelectRAM resources that provide shallow RAM structures implemented in CLBs. Each Virtex-II Pro block SelectRAM is an 18 Kb true dual-port RAM with two independently clocked and independently controlled synchronous ports that access a common storage area. Both ports are functionally identical. CLK, EN, WE, and SSR polarities are defined through configuration. Each port has the following types of inputs: Clock and Clock Enable, Write Enable, Set/Reset, and Address, as well as separate Data/parity data inputs (for write) and Data/parity data outputs (for read). 1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb memory locations in any of the 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations. The advantage of the 9-bit, 18-bit and 36-bit widths is the ability to store a parity bit for each eight bits. Parity bits must be generated or checked externally in user logic. In such cases, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored and behave exactly as the other bits, including the timing parameters. Video applications can use the 9-bit ratio of Virtex-II Pro block SelectRAM memory to advantage. Each block SelectRAM cell is a fully synchronous memory as illustrated in Figure 35. Input data bus and output data bus widths are identical. 18-Kbit Block SelectRAM DI DIP ADDR Operation is synchronous; the block SelectRAM behaves like a register. Control, address and data inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a configuration option) clock edge. Data outputs change as a result of the same clock edge. WE EN SSR CLK Configuration The Virtex-II Pro block SelectRAM supports various configurations, including single- and dual-port RAM and various data/address aspect ratios. Supported memory configurations for single- and dual-port modes are shown in Table 15. 2K x 9 bits 8K x 2 bits 1K x 18 bits 4K x 4 bits 512 x 36 bits DS031_10_102000 Figure 35: 18 Kb Block SelectRAM Memory in Single-Port Mode Dual-Port Configuration Table 15: Dual- and Single-Port Configurations 16K x 1 bit DO DOP As a dual-port RAM, each port of block SelectRAM has access to a common 18 Kb memory resource. These are fully synchronous ports with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. Table 16 illustrates the different configurations available on ports A and B. Single-Port Configuration As a single-port RAM, the block SelectRAM has access to the 18 Kb memory locations in any of the 2K x 9-bit, 56 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Table 16: Dual-Port Mode Configurations Port A 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 16K x 1 Port B 16K x 1 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Port A 8K x 2 8K x 2 8K x 2 8K x 2 8K x 2 Port B 8K x 2 4K x 4 2K x 9 1K x 18 512 x 36 Port A 4K x 4 4K x 4 4K x 4 4K x 4 Port B 4K x 4 2K x 9 1K x 18 512 x 36 Port A 2K x 9 2K x 9 2K x 9 Port B 2K x 9 1K x 18 512 x 36 Port A 1K x 18 1K x 18 Port B 1K x 18 512 x 36 Port A 512 x 36 Port B 512 x 36 If both ports are configured in either 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations, the 18 Kb block is accessible from port A or B. If both ports are configured in either 16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit block is accessible from Port A or Port B. All other configurations result in one port having access to an 18 Kb memory block and the other port having access to a 16 K-bit subset of the memory block equal to 16 Kbs. 18-Kbit Block SelectRAM DIA DIPA ADDRA WEA ENA SSRA CLKA CLKB Width Depth Address Bus Data Bus Parity Bus 1 16,384 ADDR[13:0] DATA[0] N/A 2 8,192 ADDR[12:0] DATA[1:0] N/A 4 4,096 ADDR[11:0] DATA[3:0] N/A 9 2,048 ADDR[10:0] DATA[7:0] Parity[0] 18 1,024 ADDR[9:0] DATA[15:0] Parity[1:0] 36 512 ADDR[8:0] DATA[31:0] Parity[3:0] The Virtex-II Pro block SelectRAM read operation is fully synchronous. An address is presented, and the read operation is enabled by control signal ENA or ENB. Then, depending on clock polarity, a rising or falling clock edge causes the stored data to be loaded into output registers. DOB DOPB DS031_11_102000 Figure 36: 18 Kb Block SelectRAM in Dual-Port Mode Each block SelectRAM cell is a fully synchronous memory, as illustrated in Figure 36. The two ports have independent inputs and outputs and are independently clocked. Port Aspect Ratios Table 17 shows the depth and the width aspect ratios for the 18 Kb block SelectRAM. Virtex-II Pro block SelectRAM also DS083-2 (v1.0) January 31, 2002 Advance Product Specification Table 17: 18 Kb Block SelectRAM Port Aspect Ratio Read/Write Operations DOA DOPA DIB DIPB ADDRB WEB ENB SSRB includes dedicated routing resources to provide an efficient interface with CLBs, block SelectRAM, and multipliers. The write operation is also fully synchronous. Data and address are presented, and the write operation is enabled by control signals WEA and WEB in addition to ENA or ENB. Then, again depending on the clock input mode, a rising or falling clock edge causes the data to be loaded into the memory cell addressed. A write operation performs a simultaneous read operation. Three different options are available, selected by configuration: 1. WRITE_FIRST The WRITE_FIRST option is a transparent mode. The same clock edge that writes the data input (DI) into the www.xilinx.com 1-800-255-7778 57 R Functional Description: FPGA memory also transfers DI into the output registers DO, as shown in Figure 37. Data_in DI Internal Memory NO_CHANGE, only a read operation loads a new value in the output register DO, as shown in Figure 39. Data_in DO DI Data_out = Data_in Internal Memory DO No change during write CLK CLK WE WE Data_in New Address aa RAM Contents Old Data_in New Address aa RAM Contents Old New New Data_out Last Read Cycle Content (no change) New Data_out DS083-2_12_050901 DS083-2_14_050901 Figure 39: NO_CHANGE Mode Figure 37: WRITE_FIRST Mode Control Pins and Attributes 2. READ_FIRST The READ_FIRST option is a read-before-write mode. The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell addressed into the data output registers DO, as shown in Figure 38. Data_in DI Internal Memory DO Virtex-II Pro SelectRAM memory has two independent ports with the control signals described in Table 18. All control inputs including the clock have an optional inversion. Table 18: Control Functions Control Signal Prior stored data CLK WE Data_in New Address aa RAM Contents Old Data_out Function CLK Read and Write Clock EN Enable affects Read, Write, Set, Reset WE Write Enable SSR Set DO register to SRVAL (attribute) Initial memory content is determined by the INIT_xx attributes. Separate attributes determine the output register value after device configuration (INIT) and SSR is asserted (SRVAL). Both attributes (INIT_B and SRVAL) are available for each port when a block SelectRAM resource is configured as dual-port RAM. New Old Total Amount of SelectRAM Memory DS083-2_13_050901 Virtex-II Pro SelectRAM memory blocks are organized in multiple columns. The number of blocks per column depends on the row size, the number of Processor Blocks, and the number of Rocket I/O transceivers. Figure 38: READ_FIRST Mode 3. NO_CHANGE The NO_CHANGE option maintains the content of the output registers, regardless of the write operation. The clock edge during the write mode has no effect on the content of the data output register DO. When the port is configured as 58 Table 19 shows the number of columns as well as the total amount of block SelectRAM memory available for each Virtex-II Pro device. The 18 Kb SelectRAM blocks are cascadable to implement deeper or wider single- or dual-port memory resources. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Total SelectRAM Memory Device Columns Blocks in Kb in Bits XC2VP2 4 12 216 221,184 XC2VP4 4 28 504 516,096 XC2VP7 6 44 792 811,008 XC2VP20 8 88 1,584 1,622,016 XC2VP50 12 216 3,888 3,981,312 Each SelectRAM memory and multiplier block is tied to four switch matrices, as shown in Figure 41. Switch Matrix Switch Matrix 18-Kbit block SelectRAM Switch Matrix Figure 40 shows the layout of the block RAM columns in the XC2VP4 device. DCM Rocket I/O TM Serial Transceivers BRAM Multiplier Blocks 18 x 18 Multiplier Table 19: Virtex-II Pro SelectRAM Memory Available Switch Matrix DCM DS031_33_101000 CLBs CLBs Figure 41: SelectRAM and Multiplier Blocks Association With Block SelectRAM Memory CLBs DCM CLBs CLBs The interconnect is designed to allow SelectRAM memory and multiplier blocks to be used at the same time, but some interconnect is shared between the SelectRAM and the multiplier. Thus, SelectRAM memory can be used only up to 18 bits wide when the multiplier is used, because the multiplier shares inputs with the upper data bits of the SelectRAM memory. PPC405 CPU Rocket I/OTM Serial Transceivers DCM DS083-2_11_010802 Figure 40: XC2VP4 Block RAM Column Layout This sharing of the interconnect is optimized for an 18-bit-wide block SelectRAM resource feeding the multiplier. The use of SelectRAM memory and the multiplier with an accumulator in LUTs allows for implementation of a digital signal processor (DSP) multiplier-accumulator (MAC) function, which is commonly used in finite and infinite impulse response (FIR and IIR) digital filters. Configuration 18-Bit x 18-Bit Multipliers Introduction A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2's complement signed multiplier. Virtex-II Pro devices incorporate many embedded multiplier blocks. These multipliers can be associated with an 18 Kb block SelectRAM resource or can be used independently. They are optimized for high-speed operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices. The multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). Both A and B are 18-bit-wide inputs, and the output is 36 bits. Figure 42 shows a multiplier block. Multiplier Block A[17:0] MULT 18 x 18 P[35:0] B[17:0] DS031_40_100400 Figure 42: Multiplier Block DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 59 R Functional Description: FPGA Locations / Organization Multiplier organization is identical to the 18 Kb SelectRAM organization, because each multiplier is associated with an 18 Kb block SelectRAM resource. Table 20: Multiplier Resources Device Columns Total Multipliers XC2VP2 4 12 XC2VP4 4 28 XC2VP7 6 44 XC2VP20 8 88 XC2VP50 12 216 Each global clock multiplexer buffer can be driven either by the clock pad to distribute a clock directly to the device, or by the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM), page 62. Each global clock multiplexer buffer can also be driven by local interconnects. The DCM has clock output(s) that can be connected to global clock multiplexer buffer inputs, as shown in Figure 44. Clock Pad Clock Pad CLKIN DCM Local Interconnect CLKOUT In addition to the built-in multiplier blocks, the CLB elements have dedicated logic to implement efficient multipliers in logic. (Refer to Configurable Logic Blocks (CLBs), page 47). Clock Multiplexer I Global Clock Multiplexer Buffers Clock Buffer Virtex-II Pro devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads center on both the top edge and the bottom edge of the device, as illustrated in Figure 43. The global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution in Virtex-II Pro devices. Like the clock pads, eight global clock multiplexer buffers are on the top edge of the device and eight are on the bottom edge. O Clock Distribution DS083-2_43_122001 Figure 44: Virtex-II Pro Clock Multiplexer Buffer Configuration Global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in CLBs and IOBs, and SelectRAM blocks. Eight global clocks can be used in each quadrant of the Virtex-II Pro device. Designers should consider the clock distribution detail of the device prior to pin-locking and floorplanning. (See the Virtex-II Pro User Guide.) 8 clock pads Virtex-II Pro Device 8 clock pads DS083-2_42_061401 Figure 43: Virtex-II Pro Clock Pads 60 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Figure 45 shows clock distribution in Virtex-II Pro devices. 8 BUFGMUX NE NW NW 8 BUFGMUX NE 8 8 8 max 16 Clocks 16 Clocks 8 SW 8 BUFGMUX SE 8 SE SW 8 BUFGMUX DS083-2_45_122001 Figure 45: Virtex-II Pro Clock Distribution In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB rows (eight up and eight down). To reduce power consumption, any unused clock branches remain static. Global clocks are driven by dedicated clock buffers (BUFG), which can also be used to gate the clock (BUFGCE) or to multiplex between two independent clock inputs (BUFGMUX). itives. The falling clock edge option uses the BUFGCE_1 and BUFGMUX_1 primitives. BUFGCE If the CE input is active (High) prior to the incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through the clock buffer. Any level change of CE during the incoming clock High time has no effect. BUFGCE The most common configuration option of this element is as a buffer. A BUFG function in this (global buffer) mode, is shown in Figure 46. I CE BUFG I DS031_62_101200 Figure 47: Virtex-II Pro BUFGCE Function O DS031_61_101200 Figure 46: Virtex-II Pro BUFG Function The Virtex-II Pro global clock buffer BUFG can also be configured as a clock enable/disable circuit (Figure 47), as well as a two-input clock multiplexer (Figure 48). A functional description of these two options is provided below. Each of them can be used in either of two modes, selected by configuration: rising clock edge or falling clock edge. This section describes the rising clock edge option. For the opposite option, falling clock edge, just change all "rising" references to "falling" and all "High" references to "Low", except for the description of the CE and S levels. The rising clock edge option uses the BUFGCE and BUFGMUX prim- DS083-2 (v1.0) January 31, 2002 Advance Product Specification O If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High time has no effect. CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output. BUFGMUX BUFGMUX can switch between two unrelated, even asynchronous clocks. Basically, a Low on S selects the I0 input, a High on S selects the I1 input. Switching from one clock to the other is done in such a way that the output High and Low time is never shorter than the shortest High or Low time of www.xilinx.com 1-800-255-7778 61 R Functional Description: FPGA either input clock. As long as the presently selected clock is High, any level change of S has no effect . BUFGMUX I0 I1 Digital Clock Manager (DCM) The Virtex-II Pro DCM offers a wide range of powerful clock management features. * Clock De-skew: The DCM generates new system clocks (either internally or externally to the FPGA), which are phase-aligned to the input clock, thus eliminating clock distribution delays. * Frequency Synthesis: The DCM generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. * Phase Shifting: The DCM provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control. O S DS083-2_63_121701 Figure 48: Virtex-II Pro BUFGMUX Function If the presently selected clock is Low while S changes, or if it goes Low after S has changed, the output is kept Low until the other ("to-be-selected") clock has made a transition from High to Low. At that instant, the new clock starts driving the output. The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock; that is, prior to the rising edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output. All Virtex-II Pro devices have 16 global clock multiplexer buffers. The DCM utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. It also utilizes fully digital feedback systems, operating dynamically to compensate for temperature and voltage variations during operation. Up to four of the nine DCM clock outputs can drive inputs to global clock buffers or global clock multiplexer buffers simultaneously (see Figure 50). All DCM clock outputs can simultaneously drive general routing resources, including routes to output buffers. DCM Figure 49 shows a switchover from CLK0 to CLK1. CLKIN CLKFB Wait for Low S RST CLK0 DSSEN Switch CLK1 CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV PSINCDEC CLKFX PSEN CLKFX180 PSCLK LOCKED Out STATUS[7:0] DS083-2_46_121701 clock signal Figure 49: Clock Multiplexer Waveform Diagram PSDONE control signal * * * * * * 62 The current clock is CLK0. S is activated High. If CLK0 is currently High, the multiplexer waits for CLK0 to go Low. Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to Low. When CLK1 transitions from High to Low, the output switches to CLK1. No glitches or short pulses can appear on the output. DS031_67_112900 Figure 50: Digital Clock Manager The DCM can be configured to delay the completion of the Virtex-II Pro configuration process until after the DCM has achieved lock. This guarantees that the chip does not begin operating until after the system clocks generated by the DCM have stabilized. The DCM has the following general control signals: * RST input pin: resets the entire DCM * LOCKED output pin: asserted High when all enabled DCM circuits have locked. * STATUS output pins (active High): shown in Table 21. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Table 21: DCM Status Pins Status Pin Function 0 Phase Shift Overflow 1 CLKIN Stopped 2 CLKFX Stopped 3 N/A 4 N/A 5 N/A 6 N/A 7 N/A All frequency synthesis outputs automatically have 50/50 duty cycles, with the exception of the CLKDV output when performing a non-integer divide in high-frequency mode. See Table 22 for more details. Note that CLK2X and CLK2X180 are not available in high-frequency mode. Table 22: CLKDV Duty Cycle for Non-integer Divides CLKDV_DIVIDE Duty Cycle 1.5 1/ 3 2.5 2/5 3.5 3/ 7 4.5 4/9 5.5 5 / 11 6.5 6 / 13 7.5 7 / 15 Clock De-skew The DCM de-skews the output clocks relative to the input clock by automatically adjusting a digital delay line. Additional delay is introduced so that clock edges arrive at internal registers and block RAMs simultaneously with the clock edges arriving at the input clock pad. Alternatively, external clocks, which are also de-skewed relative to the input clock, can be generated for board-level routing. All DCM output clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock. To achieve clock de-skew, the CLKFB input must be connected, and its source must be either CLK0 or CLK2X. Note that CLKFB must always be connected, unless only the CLKFX or CLKFX180 outputs are used and de-skew is not required. Frequency Synthesis The DCM provides flexible methods for generating new clock frequencies. Each method has a different operating frequency range and different AC characteristics. The CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output creates divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. The CLKFX and CLKFX180 outputs can be used to produce clocks at the following frequency: The DCM provides additional control over clock skew through either coarse or fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by 1/4 of the input clock period relative to each other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode. Fine-phase adjustment affects all nine DCM output clocks. When activated, the phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the input clock period. In variable mode, the PHASE_SHIFT value can also be dynamically incremented or decremented as determined by PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 51 illustrates the effects of fine-phase shifting. For more information on DCM features, see the Virtex-II Pro User Guide. Table 23 lists fine-phase shifting control pins, when used in variable mode. Table 23: Fine Phase Shifting Control Pins FREQ CLKFX = ( M D ) * FREQ CLKIN Control Pin where M and D are two integers. Specifications for M and D are provided under DCM Timing Parameters. By default, M = 4 and D = 1, which results in a clock output frequency four times faster than the clock input frequency (CLKIN). CLK2X180 is phase shifted 180 degrees relative to CLK2X. CLKFX180 is phase shifted 180 degrees relative to CLKFX. DS083-2 (v1.0) January 31, 2002 Advance Product Specification Phase Shifting Direction Function PSINCDEC In Increment or decrement PSEN In Enable phase shift PSCLK In Clock for phase shift PSDONE www.xilinx.com 1-800-255-7778 Out Active when completed 63 R Functional Description: FPGA CLKIN CLKOUT_PHASE_SHIFT CLKFB = NONE CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED (PS/256) x PERIODCLKIN (PS/256) x PERIODCLKIN (PS negative) (PS positive) CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB (PS/256) x PERIODCLKIN (PS/256) x PERIODCLKIN (PS positive) (PS negative) DS031_48_110300 Figure 51: Fine-Phase Shifting Effects Two separate components of the phase shift range must be understood: PHASE_SHIFT attribute range * * FINE_SHIFT_RANGE DCM timing parameter range The PHASE_SHIFT attribute is the numerator in the following equation: Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN The full range of this attribute is always -255 to +255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE component, which represents the total delay achievable by the phase shift delay line. Total delay is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be as specified under DCM Timing Parameters. thus dividing the total delay line range in half. In fixed mode, since the PHASE_SHIFT value never changes after configuration, the entire delay line is available for insertion into either the CLKIN or CLKFB path (to create either positive or negative skew). Taking both of these components into consideration, the following are some usage examples: * If PERIODCLKIN = 2 * FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 128, and in variable mode it is limited to 64. * If PERIODCLKIN = FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 255, and in variable mode it is limited to 128. * If PERIODCLKIN 0.5 * FINE_SHIFT_RANGE, then PHASE_SHIFT is limited to 255 in either mode. Absolute range (fixed mode) = FINE_SHIFT_RANGE Operating Modes Absolute range (variable mode) = FINE_SHIFT_RANGE/2 The frequency ranges of DCM input and output clocks depend on the operating mode specified, either low-frequency mode or high-frequency mode, according to Table 24. For actual values, see Virtex-II Pro Switching Characteristics (Module 3). The CLK2X, CLK2X180, The reason for the difference between fixed and variable modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the delay line, Table 24: DCM Frequency Ranges Low-Frequency Mode Output Clock High-Frequency Mode CLKIN Input CLK Output CLKIN Input CLK Output CLK0, CLK180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF CLK90, CLK270 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF NA NA CLK2X, CLK2X180 CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF NA NA CLKDV CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF CLKFX, CLKFX180 CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF 64 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description CLK90, and CLK270 outputs are not available in high-frequency mode. * High or low-frequency mode is selected by an attribute. * Routing DCM and MGT Locations/Organization Virtex-II Pro DCMs and serial transceivers (MGTs) are placed on the top and bottom of each block RAM and multiplier column in some combination, as shown in Table 25. The number of DCMs and Rocket I/O transceiver cores total to twice the number of columns in the device. Refer to Figure 40, page 59 for an illustration of this in the XC2VP4 device. Table 25: DCM Organization Device * * The long lines are bidirectional wires that distribute signals across the device. Vertical and horizontal long lines span the full height and width of the device. The hex lines route signals to every third or sixth block away in all four directions. Organized in a staggered pattern, hex lines can only be driven from one end. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). The double lines route signals to every first or second block away in all four directions. Organized in a staggered pattern, double lines can be driven only at their endpoints. Double-line signals can be accessed either at the endpoints or at the midpoint (one block from the source). The direct connect lines route signals to neighboring blocks: vertically, horizontally, and diagonally. The fast connect lines are the internal CLB local interconnections from LUT outputs to LUT inputs. Columns DCMs MGTs XC2VP2 4 4 4 XC2VP4 4 4 4 XC2VP7 6 4 8 XC2VP20 8 8 8 In addition to the global and local routing resources, dedicated signals are available. XC2VP50 12 8 16 * * Dedicated Routing Place-and-route software takes advantage of this regular array to deliver optimum system performance and fast compile times. The segmented routing resources are essential to guarantee IP cores portability and to efficiently handle an incremental design flow that is based on modular implementations. Total design time is reduced due to fewer and shorter design iterations. Hierarchical Routing Resources * * Most Virtex-II Pro signals are routed using the global routing resources, which are located in horizontal and vertical routing channels between each switch matrix. As shown in Figure 52, page 66, Virtex-II Pro has fully buffered programmable interconnections, with a number of resources counted between any two adjacent switch matrix rows or columns. Fanout has minimal impact on the performance of each net. DS083-2 (v1.0) January 31, 2002 Advance Product Specification * * There are eight global clock nets per quadrant. (See Global Clock Multiplexer Buffers, page 60.) Horizontal routing resources are provided for on-chip 3-state buses. Four partitionable bus lines are provided per CLB row, permitting multiple buses within a row. (See 3-State Buffers, page 55.) Two dedicated carry-chain resources per slice column (two per CLB column) propagate carry-chain MUXCY output signals vertically to the adjacent slice. (See CLB/Slice Configurations, page 55.) One dedicated SOP chain per slice row (two per CLB row) propagate ORCY output logic signals horizontally to the adjacent slice. (See Sum of Products, page 54.) One dedicated shift-chain per CLB connects the output of LUTs in shift-register mode to the input of the next LUT in shift-register mode (vertically) inside the CLB. (See Shift Registers, page 50.) www.xilinx.com 1-800-255-7778 65 R Functional Description: FPGA * 24 Horizontal Long Lines 24 Vertical Long Lines 120 Horizontal Hex Lines 120 Vertical Hex Lines 40 Horizontal Double Lines 40 Vertical Double Lines 16 Direct Connections (total in all four directions) 8 Fast Connects DS031_60_110200 Figure 52: Hierarchical Routing Resources Configuration Virtex-II Pro devices are configured by loading application specific configuration data into the internal configuration memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used as general purpose inputs and outputs once configuration is complete. Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M2, M1 and M0 are dedicated pins. An additional pin, HSWAP_EN is used in conjunction with the mode pins to select whether user I/O pins have pull-ups during configuration. By default, HSWAP_EN is tied High (internal pull-up) which shuts off the pull-ups on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during configuration. Other dedicated pins are CCLK (the configuration clock pin), DONE, PROG_B, and the boundary-scan pins: TDI, TDO, TMS, and TCK. Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or an input accepting an externally generated clock. The configuration pins and boundary scan pins are independent of the VCCO. The auxiliary power supply (VCCAUX) of 2.5V is used for these pins. See Virtex-II Pro Switching Characteristics (Module 3). A persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. If the persist option is 66 not selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan related pins. The persist feature is valuable in applications which employ partial reconfiguration or reconfiguration on the fly. Virtex-II Pro supports the following five configuration modes: * * * * * Slave-Serial Mode Master-Serial Mode Slave SelectMAP Mode Master SelectMAP Mode Boundary-Scan (JTAG, IEEE 1532) Mode Refer to Table 26, page 67. A detailed description of configuration modes is provided in the Virtex-II Pro User Guide. Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of configuration data. The CCLK pin on the FPGA is an input in this mode. The serial bitstream must be setup at the DIN input pin a short time before each rising edge of the externally generated CCLK. Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been config- www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description ured, the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the rising edge of CCLK. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback using the persist option. Slave-serial mode is selected by applying [111] to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. Multiple Virtex-II Pro FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by deasserting the CS_B pin of each device in turn and writing the appropriate data. Master-Serial Mode In master-serial mode, the CCLK pin is an output pin. It is the Virtex-II Pro FPGA device that drives the configuration clock on the CCLK pin to a Xilinx Serial PROM which in turn feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. Master SelectMAP Mode This mode is a master version of the SelectMAP mode. The device is configured byte-wide on a CCLK supplied by the Virtex-II Pro FPGA device. Timing is similar to the Slave SerialMAP mode except that CCLK is supplied by the Virtex-II Pro FPGA. The interface is identical to slave serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Boundary-Scan (JTAG, IEEE 1532) Mode In boundary-scan mode, dedicated pins are used for configuring the Virtex-II Pro device. The configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP). Virtex-II Pro device configuration using Boundary scan is compliant with IEEE 1149.1-1993 standard and the new IEEE 1532 standard for In-System Configurable (ISC) devices. The IEEE 1532 standard is backward compliant with the IEEE 1149.1-1993 TAP and state machine. The IEEE Standard 1532 for In-System Configurable (ISC) devices is intended to be programmed, reprogrammed, or tested on the board via a physical and logical protocol. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. Slave SelectMAP Mode The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the Virtex-II Pro FPGA device with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, an active Low Chip Select (CS_B) signal and a Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If RDWR_B is asserted, configuration data is read out of the FPGA as part of a readback operation. Table 26: Virtex-II Pro Configuration Mode Pin Settings M2 M1 M0 CCLK Direction Data Width Serial DOUT (2) Master Serial 0 0 0 Out 1 Yes Slave Serial 1 1 1 In 1 Yes Master SelectMAP 0 1 1 Out 8 No Slave SelectMAP 1 1 0 In 8 No Boundary Scan 1 0 1 N/A 1 No Configuration Mode (1) Notes: 1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pullups are used. 2. Daisy chaining is possible only in modes where Serial DOUT is used. For example, in SelectMAP modes, the first device does NOT support daisy chaining of downstream devices. DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 67 R Functional Description: FPGA Table 27 lists the total number of bits required to configure each device. Table 27: Virtex-II Pro Bitstream Lengths Device Number of Configuration Bits XC2VP2 1,305,440 XC2VP4 3,006,560 XC2VP7 4,485,472 XC2VP20 8,214,624 XC2VP50 19,021,408 Readback In this mode, configuration data from the Virtex-II Pro FPGA device can be read back. Readback is supported only in the SelectMAP (master and slave) and Boundary Scan mode. Configuration Sequence The configuration of Virtex-II Pro devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user. The INIT_B pin can be held Low using an open-drain driver. An open-drain is required since INIT_B is a bidirectional open-drain pin that is held Low by a Virtex-II Pro FPGA device while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded. The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is signaled by the INIT_B pin going High, and the completion of the entire process is signaled by the DONE pin going High. The Global Set/Reset (GSR) signal is pulsed after the last frame of configuration data is written but before the start-up sequence. The GSR signal resets all flip-flops on the device. The default start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Write Enable (GWE) signal is released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. 68 The relative timing of these events can be changed via configuration options in software. In addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start synchronously. The sequence can also be paused at any stage, until lock has been achieved on any or all DCMs, as well as DCI. Along with the configuration data, it is possible to read back the contents of all registers, distributed SelectRAM, and block RAM resources. This capability is used for real-time debugging. For more detailed configuration information, see the Virtex-II Pro User Guide. Bitstream Encryption Virtex-II Pro devices have an on-chip decryptor using one or two sets of three keys for triple-key Data Encryption Standard (DES) operation. Xilinx software tools offer an optional encryption of the configuration data (bitstream) with a triple-key DES determined by the designer. The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the VBATT pin, when the device is not powered. Virtex-II Pro devices can be configured with the corresponding encrypted bitstream, using any of the configuration modes described previously. A detailed description of how to use bitstream encryption is provided in the Virtex-II Pro User Guide. Your local FAE can also provide specific information on this feature. Partial Reconfiguration Partial reconfiguration of Virtex-II Pro devices can be accomplished in either Slave SelectMAP mode or Boundary-Scan mode. Instead of resetting the chip and doing a full configuration, new data is loaded into a specified area of the chip, while the rest of the chip remains in operation. Data is loaded on a column basis, with the smallest load unit being a configuration "frame" of the bitstream (device size dependent). Partial reconfiguration is useful for applications that require different designs to be loaded into the same area of a chip, or that require the ability to change portions of a design without having to reset or reconfigure the entire chip. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: Functional Description Revision History This section records the change history for this module of the data sheet. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II Pro Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II Pro Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II Pro Platform FPGAs: Functional Description (Module 2) * Virtex-II Pro Platform FPGAs: Pinout Information (Module 4) DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 69 R Virtex-II Pro Data Sheet Modules 70 www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product Specification 6 0 Virtex-II Pro Platform FPGAs: DC and Switching Characteristics R DS083-3 (v1.0) January 31, 2002 0 0 Advance Product Specification Virtex-II Pro Electrical Characteristics VirtexTM-II Pro devices are provided in -8, -7, and -6 speed grades, with -8 having the highest performance. commercial device). However, only selected speed grades and/or devices might be available in the industrial range. Virtex-II Pro DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -6 speed grade industrial device are the same as for a -6 speed grade All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Contact Xilinx for design considerations requiring more detailed information. All specifications are subject to change without notice. Virtex-II Pro DC Characteristics Table 1: Absolute Maximum Ratings Symbol Description Units VCCINT Internal supply voltage relative to GND -0.5 to 1.65 V VCCAUX Auxiliary supply voltage relative to GND -0.5 to 3.45 V VCCO Output drivers supply voltage relative to GND -0.5 to 3.45 V VBATT Key memory battery backup supply -0.5 to 3.45 V VREF Input reference voltage -0.5 to 3.45 V VIN Input voltage relative to GND (user and dedicated I/Os) -0.5 (2) to 3.45 (4) V VTS Voltage applied to 3-state output (user and dedicated I/Os) -0.5 (3) to 3.45 (5) V VCCAUXRX Auxilliary supply voltage relative to analog ground, GNDA (Rocket I/O pins) -0.5 to 3.45 V VCCAUXTX Auxilliary supply voltage relative to analog ground, GNDA (Rocket I/O pins) -0.5 to 3.45 V VTTX Terminal transmit supply voltage relative to GND (Rocket I/O pins) -0.5 to 3.45 V VTRX Terminal receive supply voltage relative to GND (Rocket I/O pins) -0.5 to 3.45 V TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature +220 C TJ Operating junction temperature +125 C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For 3.3V I/O standards only, I/O input pin voltage, including negative undershoot, must not fall below 0.0V, either on a continuous or transient basis (i.e., no negative undershoot is allowed). See Table 6, page 74. 3. For 3.3V I/O standards only, I/O output pin voltage while in 3-state mode must not fall below 0.0V, either on a continuous or transient basis. See Table 6, page 74. 4. I/O input pin voltage, including overshoot, must not exceed 3.45V, either on a continuous or transient basis. 5. I/O output pin voltage while in 3-state mode must not exceed 3.45V, either on a continuous or transient basis. (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 71 R Virtex-II Pro Electrical Characteristics Table 2: Recommended Operating Conditions Symbol VCCINT VCCAUX(1) VCCO(2) VBATT(3) VCCAUXRX, VCCAUXTX VTTX, VTRX Description Min Max Units Commercial 1.425 1.575 V Industrial 1.425 1.575 V Commercial 2.375 2.625 V Industrial 2.375 2.625 V Commercial 1.2 3.45 (4) V Industrial 1.2 3.45 (4) V Commercial 1.0 2.63 V Industrial 1.0 2.63 V Auxilliary supply voltage relative to GNDA Commercial 2.375 2.625 V Auxilliary supply voltage relative to GNDA Industrial 2.375 2.625 V Terminal supply voltage relative to GND Commercial 1.8 2.625 V Terminal supply voltage relative to GND Industrial 1.8 2.625 V Internal supply voltage relative to GND, TJ = 0 C to +85C Internal supply voltage relative to GND, TJ = -40C to +100C Auxiliary supply voltage relative to GND, TJ = 0 C to +85C Auxiliary supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Battery voltage relative to GND, TJ = 0 C to +85C Battery voltage relative to GND, TJ = -40C to +100C Notes: 1. For LVDS operation, VCCAUX min is 2.37V and max is 2.63V. 2. Configuration data is retained even if VCCO drops to 0V. 3. If battery is not used, do not connect VBATT. 4. For 3.3V operation, see Table 4-1, page 448, for banking information. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Device Min 1.2 Typ Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) All VDRI Data retention VCCAUX voltage (below which configuration data might be lost) All V IREF VREF current per bank All A Input or output leakage current per pin All A CIN Input capacitance (sample tested) All pF IRPU Pad pull-up (when selected) @ Vin = 0V, VCCO = 3.3V (sample tested) All Note (1) mA IRPD Pad pull-down (when selected) @ Vin = 3.6V (sample tested) All Note (1) mA IL V I CCAUXTX Operating VCCAUXTX supply current 60 mA I CCAUXRX Operating VCCAUXRX supply current 35 mA Operating ITTX supply current when transmitter is AC coupled 30 mA Operating ITTX supply current when transmitter is DC coupled 15 mA Operating ITRX supply current when receiver is AC coupled TBD mA Operating ITRX supply current when receiver is DC coupled 15 mA ITTX ITRX 72 Description www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions (Continued) Symbol PCPU PRXTX Description Device Min Typ Max Units mW / MHz Power dissipation of PowerPC 405 processor block Power dissipation of Rocket I/O @ 3.125 Gb/s per channel 350 mW Power dissipation of Rocket I/O @ 2.5 Gb/s per channel 310 mW Power dissipation of Rocket I/O @ 1.25 Gb/s per channel 230 mW Notes: 1. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. Table 4: Quiescent Supply Current Symbol ICCINTQ ICCOQ ICCAUXQ Description Device Quiescent VCCINT supply current Quiescent VCCO supply current Quiescent VCCAUX supply current Min Typ Max Units XC2VP2 mA XC2VP4 mA XC2VP7 mA XC2VP20 mA XC2VP50 mA XC2VP2 mA XC2VP4 mA XC2VP7 mA XC2VP20 mA XC2VP50 mA XC2VP2 mA XC2VP4 mA XC2VP7 mA XC2VP20 mA XC2VP50 mA Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 2. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWERTM. Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power supply. The VCCINT, VCCAUX , and VCCO power supplies must ramp on no faster than 100 s and no slower than 50 ms. Ramp on is defined as: 0 VDC to minimum supply voltages (see Table 2, page 72). VCCAUX and VCCO for bank 4 must be connected together (2.5 VDC) to meet the following specification. DS083-3 (v1.0) January 31, 2002 Advance Product Specification Table 5, page 74, shows the minimum current required by Virtex-II Pro devices for proper power on and configuration. Power supplies can be turned on in any sequence, as long as VCCAUX and VCCO are connected together for bank 4. If any VCCO bank powers up before VCCAUX , then each bank draws up to 600 mA, worst case, until the VCCAUX powers on. This does not harm the device. (Note that the 600 mA is peak transient current, which eventually dissipates even if VCCAUX does not power on.) www.xilinx.com 1-800-255-7778 73 R Virtex-II Pro Electrical Characteristics If the currents minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. Once initialized and configured, use the power calculator to estimate current drain on these supplies. Table 5: Power-On Current for Virtex-II Pro Devices Device Symbol XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP50 Units ICCINTMIN 250 250 250 250 500 mA ICCAUXMIN 250 250 250 250 250 mA ICCOMIN 10 10 10 10 10 mA SelectI/O DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are cho- sen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 6: DC Input and Output Levels VIH VOL VOH IOL IOH V, max V, Max V, Min mA mA 2.0 VCCO 0.4 2.4 24 -24 0.8 2.0 VCCO 0.4 VCCO - 0.4 24 -24 -0.5 0.7 1.7 VCCO + 0.4 0.4 VCCO - 0.4 24 -24 LVCMOS18 -0.5 20% VCCO 70% VCCO VCCO + 0.4 0.4 VCCO - 0.45 16 -16 LVCMOS15 -0.5 20% VCCO 70% VCCO VCCO + 0.4 0.4 VCCO - 0.45 16 -16 PCI33_3 (2) 0.0 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO PCI66_3 (2) 0.0 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO GTLP -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.6 n/a 36 n/a GTL -0.5 VREF - 0.05 VREF + 0.05 VCCO + 0.4 0.4 n/a 40 n/a HSTL I -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 8(3) -8(3) HSTL II -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 16(3) -16(3) HSTL III -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 24(3) -8(3) HSTL IV -0.5 VREF - 0.1 VREF + 0.1 VCCO + 0.4 0.4(3) VCCO - 0.4 48(3) -8(3) SSTL3 I 0.0 VREF - 0.2 VREF + 0.2 VCCO VREF - 0.6 VREF + 0.6 8 -8 SSTL3 II 0.0 VREF - 0.2 VREF + 0.2 VCCO VREF - 0.8 VREF + 0.8 16 -16 SSTL2 I -0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.4 VREF - 0.61 VREF + 0.65 7.6 -7.6 SSTL2 II -0.5 VREF - 0.2 VREF + 0.2 VCCO + 0.4 VREF - 0.80 VREF + 0.80 15.2 -15.2 VIL Input/Output Standard V, min V, max V, min LVTTL(1) 0.0 0.8 LVCMOS33 0.0 LVCMOS25 Notes: 1. VOL and VOH for lower drive currents are sample tested. The DONE pin is always CMOS 2.5 12 mA. 2. For optimum performance, it is recommended that PCI be used in conjunction with LVDCI_33. Contact Xilinx for more details. 3. This applies to 1.5V and 1.8V HSTL. 74 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics LDT DC Specifications (LDT_25) Table 7: LDT DC Specifications DC Parameter Supply Voltage Symbol Conditions VCCO Differential Output Voltage VOD Change in VOD Magnitude VOD Output Common Mode Voltage VOCM RT = 100 ohm across Q and Q signals Min Typ Max Units 2.38 2.5 2.63 V 500 600 700 mV 15 mV 640 mV 15 mV 1000 mV 15 mV 700 mV 15 mV -15 RT = 100 ohm across Q and Q signals 560 VOCM -15 Input Differential Voltage VID 200 Change in VID Magnitude VID -15 Input Common Mode Voltage VICM 500 VICM -15 Change in VOS Magnitude Change in VICM Magnitude 600 600 600 LVDS DC Specifications (LVDS_25) Table 8: LVDS DC Specifications DC Parameter Supply Voltage Symbol Conditions VCCO Min Typ Max Units 2.38 2.5 2.63 V 1.475 V Output High Voltage for Q and Q VOH RT = 100 across Q and Q signals Output Low Voltage for Q and Q VOL RT = 100 across Q and Q signals 0.925 Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High VODIFF RT = 100 across Q and Q signals 250 350 400 mV Output Common-Mode Voltage VOCM RT = 100 across Q and Q signals 1.125 1.2 1.275 V Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High VIDIFF Common-mode input voltage = 1.25V 100 350 600 mV Input Common-Mode Voltage VICM Differential input voltage = 350 mV 0.3 1.2 2.2 V Min Typ Max Units 2.38 2.5 2.63 V 1.70 V V Extended LVDS DC Specifications (LVDSEXT_25) Table 9: Extended LVDS DC Specifications DC Parameter Supply Voltage Symbol Conditions VCCO Output High Voltage for Q and Q VOH RT = 100 across Q and Q signals Output Low Voltage for Q and Q VOL RT = 100 across Q and Q signals 0.705 Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High VODIFF RT = 100 across Q and Q signals 440 Output Common-Mode Voltage VOCM RT = 100 across Q and Q signals 1.125 Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High VIDIFF Common-mode input voltage = 1.25V 100 Input Common-Mode Voltage VICM Differential input voltage = 350 mV 0.3 DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 V 1.200 1.2 820 mV 1.275 V 1000 mV 2.2 V 75 R Virtex-II Pro Electrical Characteristics Rocket I/O DC Input and Output Levels Table 10: Rocket I/O DC Specifications DC Parameter Peak-to-Peak Differential Input Voltage Peak-to-Peak Differential Output Voltage (1,2) Symbol Conditions DVIN DVOUT Min Typ Max Units 175 mV 800 mV 1000 mV 1200 mV 1400 mV 1600 mV Notes: 1. Output swing levels are selectable using TX_DIFF_CTRL attribute. See the Rocket I/O Transceiver section in Chapter 2, or refer to the Rocket I/O User Manual for details. 2. Output preemphasis levels are selectable at 10% (default), 20%, 25%, and 33% using the TX_PREEMPHASIS attribute. See the Rocket I/O Transceiver section in Chapter 2 or the Rocket I/O User Manual for details. 76 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-II Pro devices. The numbers reported here are fully characterized worst-case values. Note that these values are subject to the same guidelines as Virtex-II Pro Switching Characteristics, page 79 (speed files). Table 11 provides pin-to-pin values (in nanoseconds) including IOB delays; that is, delay through the device from input pin to output pin. In the case of multiple inputs and outputs, the worst delay is reported. Table 11: Pin-to-Pin Performance Description Pin-to-Pin (w/ I/O delays) Device Used & Speed Grade Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Combinatorial (pad to LUT to pad) Memory: Block RAM Pad to setup Clock to Pad Distributed RAM Pad to setup Clock to Pad Table 12 shows internal (register-to-register) performance. Values are reported in MHz. Table 12: Register-to-Register Performance Description Register-to-Register Performance Device Used & Speed Grade Basic Functions: 16-bit Address Decoder 32-bit Address Decoder 64-bit Address Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register to LUT to Register 8-bit Adder 16-bit Adder DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 77 R Virtex-II Pro Performance Characteristics Table 12: Register-to-Register Performance (Continued) Description Register-to-Register Performance Device Used & Speed Grade 64-bit Adder 64-bit Counter 64-bit Accumulator Multiplier 18x18 (with Block RAM inputs) Multiplier 18x18 (with Register inputs) Memory: Block RAM Single-Port 4096 x 4 bits Single-Port 2048 x 9 bits Single-Port 1024 x 18 bits Single-Port 512 x 36 bits Dual-Port A:4096 x 4 bits & B:1024 x 18 bits Dual-Port A:1024 x 18 bits & B:1024 x 18 bits Dual-Port A:2048 x 9 bits & B: 512 x 36 bits Distributed RAM Single-Port 32 x 8-bit Single-Port 64 x 8-bit Single-Port 128 x 8-bit Dual-Port 16 x 8 Dual-Port 32 x 8 Dual-Port 64 x 8 Dual-Port 128 x 8 Shift Registers 128-bit SRL 256-bit SRL FIFOs (Async. in Block RAM) 1024 x 18-bit 1024 x 18-bit FIFOs (Sync. in SRL) 128 x 8-bit 128 x 16-bit CAMs in Block RAM 32 x 9-bit 64 x 9-bit 128 x 9-bit 256 x 9-bit 78 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 12: Register-to-Register Performance (Continued) Description Register-to-Register Performance Device Used & Speed Grade CAMs in SRL 32 x 16-bit 64 x 32-bit 128 x 40-bit 256 x 48-bit 1024 x 16-bit 1024 x 72-bit Virtex-II Pro Switching Characteristics Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Note that Virtex-II Pro Performance Characteristics, page 77 are subject to these guidelines, as well. Each designation is defined as follows: Advance: These speed files are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary: These speed files are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production: These speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each DS083-3 (v1.0) January 31, 2002 Advance Product Specification device. Table 13 correlates the current status of each Virtex-II Pro device with a corresponding speed file designation. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Table 13: Virtex-II Pro Device Speed Grade Designations Speed Grade Designations Device Advance XC2VP2 -8, -7, -6 XC2VP4 -8, -7, -6 XC2VP7 -8, -7, -6 XC2VP20 -8, -7, -6 XC2VP50 -8, -7, -6 Preliminary Production Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-II Pro devices. www.xilinx.com 1-800-255-7778 79 R Virtex-II Pro Switching Characteristics PowerPC Switching Characteristics Table 14: Processor Clocks Absolute AC Characteristics Speed Grade -8 Description Min -7 Max Min -6 Max Min Max Units CPMC405CLOCK frequency MHz JTAGC405TCK frequency (1) MHz Notes: 1. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is dependent on the system, and will be much less Table 15: Processor Block Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (CPMC405CLOCK) Device Control Register Bus control inputs TPCCK_DCR/TPCKC_DCR ns, min Device Control Register Bus data inputs TPDCK_DCR/TPCKD_DCR ns, min Clock and Power Management control inputs TPCCK_CPM/TPCKC_CPM ns, min Reset control inputs TPCCK_RST/TPCKC_RST ns, min Debug control inputs TPCCK_DBG/TPCKC_DBG ns, min Trace control inputs TPCCK_TRC/TPCKC_TRC ns, min TPCCK_EIC/TPCKC_EIC ns, min Device Control Register Bus control outputs TPCKCO_DCR ns, max Device Control Register Bus address outputs TPCKAO_DCR ns, max Device Control Register Bus data outputs TPCKDO_DCR ns, max Clock and Power Management control outputs TPCKCO_CPM ns, max Reset control outputs TPCKCO_RST ns, max Debug control outputs TPCKCO_DBG ns, max Trace control outputs TPCKCO_TRC ns, max External Interrupt Controller control inputs Clock to Out 80 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 15: Processor Block Switching Characteristics (Continued) Speed Grade Description Symbol -8 -7 -6 Units CPMC405CLOCK minimum pulse width, high TCPWH ns, min CPMC405CLOCK minimum pulse width, low TCPWL ns, min Clock Table 16: Processor Block PLB Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (PLBCLK) Processor Local Bus(ICU/DCU) control inputs TPCCK_PLB/TPCKC_PLB ns, min Processor Local Bus (ICU/DCU) data inputs TPDCK_PLB/TPCKD_PLB ns, min Processor Local Bus(ICU/DCU) control outputs TPCKCO_PLB ns, max Processor Local Bus(ICU/DCU) address bus outputs TPCKAO_PLB ns, max Processor Local Bus(ICU/DCU) data bus outputs TPCKDO_PLB ns, max PLBCLK minimum pulse width, high TPPWH ns, min PLBCLK minimum pulse width, low TPPWL ns, min Clock to Out Clock Table 17: Processor Block JTAG Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (JTAGC405TCK) JTAG control inputs JTAG reset input TPCCK_JTAG/TPCKC_JTAG ns, min TPCCK_JTAGRST/ TPCKC_JTAGRST ns, min TPCKCO_JTAG ns, max Clock to Out JTAG control outputs DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 81 R Virtex-II Pro Switching Characteristics Table 17: Processor Block JTAG Switching Characteristics (Continued) Speed Grade Description Symbol -8 -7 -6 Units Clock JTAGC405TCK minimum pulse width, high TJPWH ns, min JTAGC405TCK minimum pulse width, low TJPWL ns, min Table 18: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (BRAMDSOCMCLK) Data-Side On-Chip Memory data bus inputs TPDCK_DSOCM/TPCKD_DSOCM ns, min Data-Side On-Chip Memory control outputs TPCKCO_DSOCM ns, max Data-Side On-Chip Memory address bus outputs TPCKAO_DSOCM ns, max Data-Side On-Chip Memory data bus outputs TPCKDO_DSOCM ns, max BRAMDSOCMCLK minimum pulse width, high TDPWH ns, min BRAMDSOCMCLK minimum pulse width, low TDPWL ns, min Clock to Out Clock Table 19: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (BRAMISOCMCLK) Instruction-Side On-Chip Memory data bus inputs TPDCK_ISOCM/TPCKD_ISOCM ns, min Instruction-Side On-Chip Memory control outputs TPCKCO_ISOCM ns, max Instruction-Side On-Chip Memory address bus outputs TPCKAO_ISOCM ns, max Instruction-Side On-Chip Memory data bus outputs TPCKDO_ISOCM ns, max Clock to Out 82 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 19: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics (Continued) Speed Grade Description Symbol -8 -7 -6 Units BRAMISOCMCLK minimum pulse width, high TIPWH ns, min BRAMISOCMCLK minimum pulse width, low TIPWL ns, min Clock Rocket I/O Switching Characteristics Table 20: Rocket I/O Reference Clock Switching Characteristics All Speed Grades Description Symbol Conditions Min Typ Max Units 40 Note(1) 156.25 MHz 100 ppm REFCLK frequency range (1) FGCLK REFCLK frequency tolerance FGTOL REFCLK rise time TRCLK 20% - 80% ns REFCLK fall time TFCLK 20% - 80% ns REFCLK duty cycle TDCREF REFCLK total jitter TGJTT Clock recovery frequency acquisition time TLOCK 10 s Clock recovery phase acquisition time TPHASE 960 bits Bit error rate 45 50 peak-to-peak 55 % 40 ps 10 -12 BER Notes: 1. REFCLK frequency is typically 1/20 of serial data rate. TRCLK 80% REFCLK 20% TFCLK DS083-3_01_101801 Figure 1: Reference Clock (REFCLK) Timing Parameters DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 83 R Virtex-II Pro Switching Characteristics Table 21: Rocket I/O Receiver Switching Characteristics Description Symbol Conditions Min Typ Max Units Receive total jitter tolerance TJTOL 0.65 UI (1) Receive deterministic jitter tolerance TDJTOL 0.41 UI Receive latency (2) TRXLAT 25 42 RXUSR CLK cycles RXUSRCLK duty cycle TRXDC 45 50 55 % RXUSRCLK2 duty cycle TRX2DC 45 50 55 % Bit error rate 10 -12 BER Notes: 1. UI = Unit Interval 2. Receive latency delay from RXP/RXN to RXDATA DATA ORIGINATES . . . . . 1 2 20 21 22 . . . . . 820 821 822 . . . . . 840 841 842 . . . . RXP/RXN TRXLAT DATA ARRIVES RXDATA[16:0] 0 1 41 42 RXUSRCLK2 DS083-3_02_082301 Figure 2: Receive Latency (Maximum) 84 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 22: Rocket I/O Transmitter Switching Characteristics Description Symbol Serial data rate, full-speed clock FGTX Serial data rate, half-speed clock Conditions Min Flipchip packages Typ Max Units 0.800 3.125 Gb/s Wirebond packages 0.800 2.5 Gb/s Flipchip packages 0.600 1.0 Gb/s Wirebond packages 0.600 1.0 Gb/s Serial data output deterministic jitter TDJ 0.18 UI (1) Serial data output random jitter TRJ 0.17 UI TX rise time TRTX TX fall time TFTX Transmit latency (2) TTXLAT TXUSRCLK duty cycle TTXDC TXUSRCLK2 duty cycle TTX2DC 20% - 80% 120 ps 120 ps Including CRC 14 17 Excluding CRC 8 11 TXUSR CLK cycles 45 50 55 % 45 50 55 % Notes: 1. UI = Unit Interval 2. Transmit latency delay from TXDATA to TXP/TXN 1 2 . . . . . 20 21 22 . . . . . 320 321 322 . . . . . 340 341 342 . . . . TXP/TXN TTXLAT DATA ARRIVES DATA ORIGINATES TXDATA[16:0] 0 1 16 17 TXUSRCLK2 DS083-3_03_082301 Figure 3: Transmit Latency (Maximum, Including CRC) DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 85 R Virtex-II Pro Switching Characteristics Table 23: Rocket I/O RXUSRCLK Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (RXUSRCLK) CHBONDI control inputs TGCCK_CHBI/TGCKC_CHBI ns, min TGCKCO_CHBO ns, max RXUSRCLK minimum pulse width, High TGPWH_RX ns, min RXUSRCLK minimum pulse width, Low TGPWL_RX ns, min Clock to Out CHBONDO control outputs Clock Table 24: Rocket I/O RXUSRCLK2 Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (RXUSRCLK2) RXRESET control input TGCCK_RRST/TGCKC_RRST ns, min RXPOLARITY control input TGCCK_RPOL/TGCKC_RPOL ns, min ENCHANSYNC control input TGCCK_ECSY/TGCKC_ECSY ns, min TGCKST_RNIT ns, max RXDISPERR status outputs TGCKST_RDERR ns, max RXCHARISCOMMA status outputs TGCKST_RCMCH ns, max RXREALIGN status output TGCKST_ALIGN ns, max RXCOMMADET status output TGCKST_CMDT ns, max RXLOSSOFSYNC status outputs TGCKST_RLOS ns, max RXCLKCORCNT status outputs TGCKST_RCCCNT ns, max RXBUFSTATUS status outputs TGCKST_RBSTA ns, max RXCHECKINGCRC status output TGCKST_RCCRC ns, max RXCRCERR status output TGCKST_RCRCE ns, max CHBONDDONE status output TGCKST_CHBD ns, max RXCHARISK status outputs TGCKST_RKCH ns, max RXRUNDISP status outputs TGCKST_RRDIS ns, max RXDATA data outputs TGCKDO_RDAT ns, max RXUSRCLK2 minimum pulse width, High TGPWH_RX2 ns, min RXUSRCLK2 minimum pulse width, Low TGPWL_RX2 ns, min Clock to Out RXNOTINTABLE status outputs Clock 86 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 25: Rocket I/O TXUSRCLK Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Setup and Hold Relative to Clock (TXUSRCLK2) CONFIGENABLE control input TGCCK_CFGEN/TGCKC_CFGEN ns, min TXBYPASS8B10B control inputs TGCCK_TBYP/TGCKC_TBYP ns, min TXFORCECRCERR control input TGCCK_TCRCE/TGCKC_TCRCE ns, min TXPOLARITY control input TGCCK_TPOL/TGCKC_TPOL ns, min TXINHIBIT control inputs TGCCK_TINH/TGCKC_TINH ns, min TGCCK_LBK/TGCKC_LBK ns, min TXRESET control input TGCCK_TRST/TGCKC_TRST ns, min TXCHARISK control inputs TGCCK_TKCH/TGCKC_TKCH ns, min TXCHARDISPMODE control inputs TGCCK_TCDM/TGCKC_TCDM ns, min TXCHARDISPVAL control inputs TGCCK_TCDV/TGCKC_TCDV ns, min TGDCK_CFGIN/TGCKD_CFGIN ns, min TGDCK_TDAT/TGCKD_TDAT ns, min TXBUFERR status output TGCKST_TBERR ns, max TXKERR status outputs TGCKST_TKERR ns, max TXRUNDISP status outputs TGCKST_TRDIS ns, max TGCKDO_CFGOUT ns, max TXUSRCLK minimum pulse width, High TGPWH_TX ns, min TXUSRCLK minimum pulse width, Low TGPWL_TX ns, min TXUSRCLK2 minimum pulse width, High TGPWH_TX2 ns, min TXUSRCLK2 minimum pulse width, Low TGPWL_TX2 ns, min LOOPBACK control inputs CONFIGIN data input TXDATA data inputs Clock to Out CONFIGOUT data output Clock DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 87 R Virtex-II Pro Switching Characteristics IOB Input Switching Characteristics Input delays associated with the pad are specified for LVCMOS 2.5V levels. For other standards, adjust the delays with the values shown in IOB Input Switching Characteristics Standard Adjustments, page 89. Table 26: IOB Input Switching Characteristics Speed Grade Description Symbol Device -8 Pad to I output, no delay TIOPI All ns, max Pad to I output, with delay TIOPID XC2VP2 ns, max XC2VP4 ns, max XC2VP7 ns, max XC2VP20 ns, max XC2VP50 ns, max TIOPLI All ns, max TIOPLID XC2VP2 ns, max XC2VP4 ns, max XC2VP7 ns, max XC2VP20 ns, max XC2VP50 ns, max TIOCKIQ All ns, max TIOPICK/TIOICKP All ns, min TIOPICKD/TIOICKPD XC2VP2 ns, max XC2VP4 ns, max XC2VP7 ns, max XC2VP20 ns, max XC2VP50 ns, max TIOICECK/TIOCKICE All ns, min TIOSRCKI All ns, min SR input to IQ (asynchronous) TIOSRIQ All ns, max GSR to output IQ TGSRQ All ns, max -7 -6 Units Propagation Delays Propagation Delays Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay Clock CLK to output IQ Setup and Hold Times With Respect to Clock at IOB Input Register Pad, no delay Pad, with delay ICE input SR input (IFF, synchronous) Set/Reset Delays Notes: 1. Input timing for LVCMOS25 is measured at 1.25V. For other I/O standards, see Table 30. 88 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics IOB Input Switching Characteristics Standard Adjustments Table 27: IOB Input Switching Characteristics Standard Adjustments Speed Grade Description Symbol Standard -8 TILVTTL LVTTL ns TILVCMOS33 LVCMOS33 ns TILVCMOS25 LVCMOS25 ns TILVCMOS18 LVCMOS18 ns TILVCMOS15 LVCMOS15 ns TILVDS_25 LVDS_25 ns TILVDS_25_EXT LVDS_25_EXT ns TIPCI33_3 PCI, 33 MHz, 3.3V ns TIPCI66_3 PCI, 66 MHz, 3.3V ns TIGTL GTL ns TIGTLPLUS GTLP ns TIHSTL_I HSTL I ns TIHSTL_II HSTL II ns TIHSTL_III HSTL III ns TIHSTL_IV HSTL IV ns TIHSTL_I_18 HSTL_I_18 ns TIHSTL_II_18 HSTL_II_18 ns TIHSTL_III_18 HSTL_III_18 ns TIHSTL_IV_18 HSTL_IV_18 ns TISSTL2_I SSTL2 I ns TISSTL2_II SSTL2 II ns TISSTL3_I SSTL3 I ns TISSTL3_II SSTL3 II ns TILVDCI33 LVDCI_33 ns TILVDCI25 LVDCI_25 ns TILVDCI18 LVDCI_18 ns TILVDCI15 LVDCI_15 ns TILVDCI_DV2_25 LVDCI_DV2_25 ns TILVDCI_DV2_18 LVDCI_DV2_18 ns TILVDCI_DV2_15 LVDCI_DV2_15 ns TIGTL_DCI GTL_DCI ns TIGTLP_DCI GTLP_DCI ns TIHSTL_I_DCI HSTL_I_DCI ns -7 -6 Units Data Input Delay Adjustments Standard-specific data input delay adjustments DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 89 R Virtex-II Pro Switching Characteristics Table 27: IOB Input Switching Characteristics Standard Adjustments (Continued) Speed Grade -7 -8 -6 Units Description Symbol Standard Standard-specific data input delay adjustments (continued) TIHSTL_II_DCI HSTL_II_DCI ns TIHSTL_III_DCI HSTL_III_DCI ns TIHSTL_IV_DCI HSTL_IV_DCI ns TIHSTL_I_DCI_18 HSTL_I_DCI_18 ns TIHSTL_II_DCI_18 HSTL_II_DCI_18 ns TIHSTL_III_DCI_18 HSTL_III_DCI_18 ns TIHSTL_IV_DCI_18 HSTL_IV_DCI_18 ns TISSTL2_I_DCI SSTL2_I_DCI ns TISSTL2_II_DCI SSTL2_II_DCI ns TISSTL3_I_DCI SSTL3_I_DCI ns TISSTL3_II_DCI SSTL3_II_DCI ns TILDT_25 LDT_25 ns TIULVDS_25 ULVDS_25 ns Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 30. IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 91. Table 28: IOB Output Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Propagation Delays O input to Pad TIOOP ns, max O input to Pad via transparent latch TIOOLP ns, max T input to Pad high-impedance (2) TIOTHZ ns, max T input to valid data on Pad TIOTON ns, max T input to Pad high-impedance via transparent latch (2) TIOTLPHZ ns, max T input to valid data on Pad via transparent latch TIOTLPON ns, max TGTS ns, max Clock CLK to Pad TIOCKP ns, max Clock CLK to Pad high-impedance (synchronous) (2) TIOCKHZ ns, max Clock CLK to valid data on Pad (synchronous) TIOCKON ns, max 3-State Delays GTS to Pad high-impedance (2) Sequential Delays 90 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 28: IOB Output Switching Characteristics (Continued) Speed Grade Description Symbol -7 -8 -6 Units Setup and Hold Times Before/After Clock CLK O input TIOOCK/TIOCKO ns, min OCE input TIOOCECK/TIOCKOCE ns, min SR input (OFF) TIOSRCKO/TIOCKOSR ns, min TIOTCK/TIOCKT ns, min 3-State Setup Times, TCE input TIOTCECK/TIOCKTCE ns, min 3-State Setup Times, SR input (TFF) TIOSRCKT/TIOCKTSR ns, min SR input to Pad (asynchronous) TIOSRP ns, max SR input to Pad high-impedance (asynchronous) (2) TIOSRHZ ns, max SR input to valid data on Pad (asynchronous) TIOSRON ns, max GSR to Pad TIOGSRQ ns, max 3-State Setup Times, T input Set/Reset Delays Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. The 3-state turn-off delays should not be adjusted. IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Table 29: IOB Output Switching Characteristics Standard Adjustments Speed Grade Description Symbol Standard -8 TOLVTTL_S2 LVTTL, Slow, 2 mA ns TOLVTTL_S4 4 mA ns TOLVTTL_S6 6 mA ns TOLVTTL_S8 8 mA ns TOLVTTL_S12 12 mA ns TOLVTTL_S16 16 mA ns TOLVTTL_S24 24 mA ns TOLVTTL_F2 LVTTL, Fast, 2 mA ns TOLVTTL_F4 4 mA ns TOLVTTL_F6 6 mA ns TOLVTTL_F8 8 mA ns TOLVTTL_F12 12 mA ns -7 -6 Units Output Delay Adjustments Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 91 R Virtex-II Pro Switching Characteristics Table 29: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) (continued) 92 -6 Units Standard TOLVTTL_F16 16 mA ns TOLVTTL_F24 24 mA ns TOLVDS_25 LVDS ns TOLVDSEXT_25 LVDS ns TOLDT_25 LDT ns TOBLVDS_25 BLVDS ns TOULVDS_25 ULVDS ns TOPCI33_3 PCI, 33 MHz, 3.3V ns TOPCI66_3 PCI, 66 MHz, 3.3V ns TOGTL GTL ns TOGTLP GTLP ns TOHSTL_I HSTL I ns TOHSTL_II HSTL II ns TOHSTL_IIII HSTL III ns TOHSTL_IV HSTL IV ns TOHSTL_I_18 HSTL_I_18 ns TOHSTL_II_18 HSTL_II_18 ns TOHSTL_IIII_18 HSTL_III_18 ns TOHSTL_IV_18 HSTL_IV_18 ns TOSSTL2_I SSTL2 I ns TOSSTL2_II SSTL2 II ns TOSSTL3_I SSTL3 I ns TOSSTL3_II SSTL3 II ns TOLVCMOS33_S2 LVCMOS33, Slow, 2 mA ns TOLVCMOS33_S4 4 mA ns TOLVCMOS33_S6 6 mA ns TOLVCMOS33_S8 8 mA ns TOLVCMOS33_S12 12 mA ns TOLVCMOS33_S16 16 mA ns TOLVCMOS33_S24 24 mA ns TOLVCMOS33_F2 LVCMOS33, Fast, 2 mA ns TOLVCMOS33_F4 4 mA ns TOLVCMOS33_F6 6 mA ns TOLVCMOS33_F8 8 mA ns TOLVCMOS33_F12 12 mA ns www.xilinx.com 1-800-255-7778 -8 -7 Symbol DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 29: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) (continued) DS083-3 (v1.0) January 31, 2002 Advance Product Specification -6 Units Standard TOLVCMOS33_F16 16 mA ns TOLVCMOS33_F24 24 mA ns TOLVCMOS25_S2 LVCMOS25, Slow, 2 mA ns TOLVCMOS25_S4 4 mA ns TOLVCMOS25_S6 6 mA ns TOLVCMOS25_S8 8 mA ns TOLVCMOS25_S12 12 mA ns TOLVCMOS25_S16 16 mA ns TOLVCMOS25_S24 24 mA ns TOLVCMOS25_F2 LVCMOS25, Fast, 2 mA ns TOLVCMOS25_F4 4 mA ns TOLVCMOS25_F6 6 mA ns TOLVCMOS25_F8 8 mA ns TOLVCMOS25_F12 12 mA ns TOLVCMOS25_F16 16 mA ns TOLVCMOS25_F24 24 mA ns TOLVCMOS18_S2 LVCMOS18, Slow, 2 mA ns TOLVCMOS18_S4 4 mA ns TOLVCMOS18_S6 6 mA ns TOLVCMOS18_S8 8 mA ns TOLVCMOS18_S12 12 mA ns TOLVCMOS18_S16 16 mA ns TOLVCMOS18_F2 LVCMOS18, Fast, 2 mA ns TOLVCMOS18_F4 4 mA ns TOLVCMOS18_F6 6 mA ns TOLVCMOS18_F8 8 mA ns TOLVCMOS18_F12 12 mA ns TOLVCMOS18_F16 16 mA ns TOLVCMOS15_S2 LVCMOS15, Slow, 2 mA ns TOLVCMOS15_S4 4 mA ns TOLVCMOS15_S6 6 mA ns TOLVCMOS15_S8 8 mA ns TOLVCMOS15_S12 12 mA ns TOLVCMOS15_S16 16 mA ns www.xilinx.com 1-800-255-7778 -8 -7 Symbol 93 R Virtex-II Pro Switching Characteristics Table 29: IOB Output Switching Characteristics Standard Adjustments (Continued) Speed Grade Description Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl) (continued) 94 -6 Units Standard TOLVCMOS15_F2 LVCMOS15, Fast, 2 mA ns TOLVCMOS15_F4 4 mA ns TOLVCMOS15_F6 6 mA ns TOLVCMOS15_F8 8 mA ns TOLVCMOS15_F12 12 mA ns TOLVCMOS15_F16 16 mA ns TOLVDCI33 LVDCI_33 ns TOLVDCI25 LVDCI_25 ns TOLVDCI18 LVDCI_18 ns TOLVDCI15 LVDCI_15 ns TOLVDCI_DV2_25 LVDCI_DV2_25 ns TOLVDCI_DV2_18 LVDCI_DV2_18 ns TOLVDCI_DV2_15 LVDCI_DV2_15 ns TOGTL_DCI GTL_DCI ns TOGTLP_DCI GTLP_DCI ns TOHSTL_I_DCI HSTL_I_DCI ns TOHSTL_II_DCI HSTL_II_DCI ns TOHSTL_III_DCI HSTL_III_DCI ns TOHSTL_IV_DCI HSTL_IV_DCI ns TOHSTL_I_DCI_18 HSTL_I_DCI_18 ns TOHSTL_II_DCI_18 HSTL_II_DCI_18 ns TOHSTL_III_DCI_18 HSTL_III_DCI_18 ns TOHSTL_IV_DCI_18 HSTL_IV_DCI_18 ns TOSSTL2_I_DCI SSTL2_I_DCI ns TOSSTL2_II_DCI SSTL2_II_DCI ns TOSSTL3_I_DCI SSTL3_I_DCI ns TOSSTL3_II_DCI SSTL3_II_DCI ns www.xilinx.com 1-800-255-7778 -8 -7 Symbol DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 30: Delay Measurement Methodology VL (1) VH (1) Meas. Point VREF (Typ) (2) LVTTL 0 3 1.4 - LVCMOS33 0 3.3 1.65 - LVCMOS25 0 2.5 1.25 - LVCMOS18 0 1.8 0.9 - LVCMOS15 0 1.5 0.75 - Standard PCI33_3 Per PCI Specification - PCI66_3 Per PCI Specification - GTL VREF - 0.2 VREF + 0.2 VREF 0.80 GTLP VREF - 0.2 VREF + 0.2 VREF 1.0 HSTL Class I VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class II VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class III VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL Class IV VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL Class I (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 HSTL Class II (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 HSTL Class III (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 HSTL Class IV (1.8V) VREF - 0.5 VREF + 0.5 VREF 1.08 SSTL3 I & II VREF - 1.0 VREF + 1.0 VREF 1.5 SSTL2 I & II VREF - 0.75 VREF + 0.75 VREF 1.25 LVDS_25 1.2 - 0.125 1.2 + 0.125 1.2 LVDSEXT_25 1.2 - 0.125 1.2 + 0.125 1.2 ULVDS_25 0.6 - 0.125 0.6 + 0.125 0.6 LDT_25 0.6 - 0.125 0.6 + 0.125 0.6 Notes: 1. Input waveform switches between VLand VH. 2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 95 R Virtex-II Pro Switching Characteristics Table 31: Standard Capacitive Loads Standard Csl (pF) LVTTL Fast Slew Rate, 2mA drive 35 LVTTL Fast Slew Rate, 4mA drive 35 LVTTL Fast Slew Rate, 6mA drive 35 LVTTL Fast Slew Rate, 8mA drive 35 LVTTL Fast Slew Rate, 12mA drive 35 LVTTL Fast Slew Rate, 16mA drive 35 LVTTL Fast Slew Rate, 24mA drive 35 LVTTL Slow Slew Rate, 2mA drive 35 LVTTL Slow Slew Rate, 4mA drive 35 LVTTL Slow Slew Rate, 6mA drive 35 LVTTL Slow Slew Rate, 8mA drive 35 LVTTL Slow Slew Rate, 12mA drive 35 LVTTL Slow Slew Rate, 16mA drive 35 LVTTL Slow Slew Rate, 24mA drive 35 LVCMOS33 35 LVCMOS25 35 LVCMOS18 35 LVCMOS15 35 PCI 33MHZ 3.3V 10 PCI 66 MHz 3.3V 10 GTL 0 GTLP 0 HSTL Class I (1.5V and 1.8V) 20 HSTL Class II (1.5Vand 1.8V 20 HSTL Class III (1.5Vand 1.8V 20 HSTL Class IV1.5Vand 1.8V 20 SSTL2 Class I 30 SSTL2 Class II 30 SSTL3 Class I 30 SSTL3 Class II 30 Notes: 1. I/O parameter measurements are made with the capacitance values shown above. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. 3. Use of IBIS models results in a more accurate prediction of the propagation delay: a. Model the output in an IBIS simulation into the standard capacitive load. b. Record the relative time to the VOH or VOL transition of interest. c. Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS models for driven devices. d. Record the results from the new simulation. e. Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should be added or subtracted from the value above to predict the actual delay. 96 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Clock Distribution Switching Characteristics Table 32: Clock Distribution Switching Characteristics Speed Grade Description Symbol Global Clock Buffer I input to O output -8 -7 -6 TGIO Units ns, max CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used (see Figure 22 in Data Sheet Module 1). The values listed below are worst-case. Precise values are provided by the timing analyzer. Table 33: CLB Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Combinatorial Delays 4-input function: F/G inputs to X/Y outputs TILO ns, max 5-input function: F/G inputs to F5 output TIF5 ns, max 5-input function: F/G inputs to X output TIF5X ns, max FXINA or FXINB inputs to Y output via MUXFX TIFXY ns, max FXINA input to FX output via MUXFX TINAFX ns, max FXINB input to FX output via MUXFX TINBFX ns, max SOPIN input to SOPOUT output via ORCY TSOPSOP ns, max Incremental delay routing through transparent latch to XQ/YQ outputs TIFNCTL ns, max FF Clock CLK to XQ/YQ outputs TCKO ns, max Latch Clock CLK to XQ/YQ outputs TCKLO ns, max BX/BY inputs TDICK/TCKDI ns, min DY inputs TDYCK/TCKDY ns, min DX inputs TDXCK/TCKDX ns, min CE input TCECK/TCKCE ns, min TRCK/TCKR ns, min Minimum Pulse Width, High TCH ns, min Minimum Pulse Width, Low TCL ns, min TRPW ns, min Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) TRQ ns, max Toggle Frequency (MHz) (for export control) FTOG MHz Sequential Delays Setup and Hold Times Before/After Clock CLK SR/BY inputs (synchronous) Clock CLK Set/Reset Minimum Pulse Width, SR/BY inputs Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 97 R Virtex-II Pro Switching Characteristics CLB Distributed RAM Switching Characteristics Table 34: CLB Distributed RAM Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Sequential Delays Clock CLK to X/Y outputs (WE active) in 16 x 1 mode TSHCKO16 ns, max Clock CLK to X/Y outputs (WE active) in 32 x 1 mode TSHCKO32 ns, max Clock CLK to F5 output TSHCKOF5 ns, max BX/BY data inputs (DIN) TDS/TDH ns, min F/G address inputs TAS/TAH ns, min TWES/TWEH ns, min Minimum Pulse Width, High TWPH ns, min Minimum Pulse Width, Low TWPL ns, min Minimum clock period to meet address write cycle time TWC ns, min Setup and Hold Times Before/After Clock CLK CE input (WE) Clock CLK Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. CLB Shift Register Switching Characteristics Table 35: CLB Shift Register Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Sequential Delays Clock CLK to X/Y outputs TREG ns, max Clock CLK to X/Y outputs TREG32 ns, max Clock CLK to XB output via MC15 LUT output TREGXB ns, max Clock CLK to YB output via MC15 LUT output TREGYB ns, max Clock CLK to Shiftout TCKSH ns, max Clock CLK to F5 output TREGF5 ns, max TSRLDS/TSRLDH ns, min TWSS/TWSH ns, min Minimum Pulse Width, High TSRPH ns, min Minimum Pulse Width, Low TSRPL ns, min Setup and Hold Times Before/After Clock CLK BX/BY data inputs (DIN) CE input (WS) Clock CLK Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 98 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Multiplier Switching Characteristics Table 36: Multiplier Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Propagation Delay to Output Pin Input to Pin35 TMULT_P35 ns, max Input to Pin34 TMULT_P34 ns, max Input to Pin33 TMULT_P33 ns, max Input to Pin32 TMULT_P32 ns, max Input to Pin31 TMULT_P31 ns, max Input to Pin30 TMULT_P30 ns, max Input to Pin29 TMULT_P29 ns, max Input to Pin28 TMULT_P28 ns, max Input to Pin27 TMULT_P27 ns, max Input to Pin26 TMULT_P26 ns, max Input to Pin25 TMULT_P25 ns, max Input to Pin24 TMULT_P24 ns, max Input to Pin23 TMULT_P23 ns, max Input to Pin22 TMULT_P22 ns, max Input to Pin21 TMULT_P21 ns, max Input to Pin20 TMULT_P20 ns, max Input to Pin19 TMULT_P19 ns, max Input to Pin18 TMULT_P18 ns, max Input to Pin17 TMULT_P17 ns, max Input to Pin16 TMULT_P16 ns, max Input to Pin15 TMULT_P15 ns, max Input to Pin14 TMULT_P14 ns, max Input to Pin13 TMULT_P13 ns, max Input to Pin12 TMULT_P12 ns, max Input to Pin11 TMULT_P11 ns, max Input to Pin10 TMULT_P10 ns, max Input to Pin9 TMULT_P9 ns, max Input to Pin8 TMULT_P8 ns, max Input to Pin7 TMULT_P7 ns, max Input to Pin6 TMULT_P6 ns, max Input to Pin5 TMULT_P5 ns, max Input to Pin4 TMULT_P4 ns, max Input to Pin3 TMULT_P3 ns, max Input to Pin2 TMULT_P2 ns, max Input to Pin1 TMULT_P1 ns, max Input to Pin0 TMULT_P0 ns, max DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 99 R Virtex-II Pro Switching Characteristics Block SelectRAM Switching Characteristics Table 37: Block SelectRAM Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Sequential Delays Clock CLK to DOUT output TBCKO ns, max ADDR inputs TBACK/TBCKA ns, min DIN inputs TBDCK/TBCKD ns, min EN input TBECK/TBCKE ns, min RST input TBRCK/TBCKR ns, min WEN input TBWCK/TBCKW ns, min Minimum Pulse Width, High TBPWH ns, min Minimum Pulse Width, Low TBPWL ns, min Setup and Hold Times Before Clock CLK Clock CLK Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. TBUF Switching Characteristics Table 38: TBUF Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units Combinatorial Delays IN input to OUT output TIO ns, max TRI input to OUT output high-impedance TOFF ns, max TRI input to valid data on OUT output TON ns, max JTAG Test Access Port Switching Characteristics Table 39: JTAG Test Access Port Switching Characteristics Speed Grade Description Symbol -8 -7 -6 Units TMS and TDI Setup times before TCK TTAPTK ns, min TMS and TDI Hold times after TCK TTCKTAP ns, min Output delay from clock TCK to output TDO TTCKTDO ns, max FTCK MHz, max Maximum TCK clock frequency 100 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted. Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Table 40: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Speed Grade Description Symbol Device -8 TICKOFDCM XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 91. Global Clock and OFF with DCM Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 30. 3. DCM output jitter is already included in the timing calculation. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 101 R Virtex-II Pro Pin-to-Pin Output Parameter Guidelines Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Table 41: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Speed Grade Description Symbol Device -8 TICKOF XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DCM. For data output with different standards, adjust the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 91. Global Clock and OFF without DCM Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see Table 30. 3. DCM output jitter is already included in the timing calculation. 102 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Virtex-II Pro Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM Table 42: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM Speed Grade Description Symbol Device -8 TPSDCM/TPHDCM XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 89. No Delay Global Clock and IFF with DCM Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DCM output jitter is already included in the timing calculation. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 103 R DCM Timing Parameters Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM , Table 43: Global Clock Set-Up and Hold for LVCMOS25 Standard, Without DCM Speed Grade Description Symbol Device -8 TPSFD/TPHFD XC2VP2 ns XC2VP4 ns XC2VP7 ns XC2VP20 ns XC2VP50 ns -7 -6 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Switching Characteristics Standard Adjustments, page 89. Full Delay Global Clock and IFF without DCM Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DCM Timing Parameters Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605; all devices are 100% functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The fol- lowing guidelines reflect worst-case values across the recommended operating conditions. All output jitter and phase specifications are determined through statistical measurement at the package pins. Operating Frequency Ranges e Table 44: Operating Frequency Ranges Speed Grade Description Symbol Constraints -8 -7 -6 Units Output Clocks (Low Frequency Mode) CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180 104 CLKOUT_FREQ_1X_LF_MIN MHz CLKOUT_FREQ_1X_LF_MAX MHz CLKOUT_FREQ_2X_LF_MIN MHz CLKOUT_FREQ_2X_LF_MAX MHz CLKOUT_FREQ_DV_LF_MIN MHz CLKOUT_FREQ_DV_LF_MAX MHz CLKOUT_FREQ_FX_LF_MIN MHz CLKOUT_FREQ_FX_LF_MAX MHz www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Table 44: Operating Frequency Ranges (Continued) Speed Grade Description Symbol Constraints -8 -7 -6 Units Input Clocks (Low Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN (using CLKFX outputs) (2) PSCLK CLKIN_FREQ_DLL_LF_MIN MHz CLKIN_FREQ_DLL_LF_MAX MHz CLKIN_FREQ_FX_LF_MIN MHz CLKIN_FREQ_FX_LF_MAX MHz PSCLK_FREQ_LF_MIN MHz PSCLK_FREQ_LF_MAX MHz Output Clocks (High Frequency Mode) CLK0, CLK180 CLKDV CLKFX, CLKFX180 CLKOUT_FREQ_1X_HF_MIN MHz CLKOUT_FREQ_1X_HF_MAX MHz CLKOUT_FREQ_DV_HF_MIN MHz CLKOUT_FREQ_DV_HF_MAX MHz CLKOUT_FREQ_FX_HF_MIN MHz CLKOUT_FREQ_FX_HF_MAX MHz CLKIN_FREQ_DLL_HF_MIN MHz CLKIN_FREQ_DLL_HF_MAX MHz CLKIN_FREQ_FX_HF_MIN MHz CLKIN_FREQ_FX_HF_MAX MHz PSCLK_FREQ_HF_MIN MHz PSCLK_FREQ_HF_MAX MHz Input Clocks (High Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN (using CLKFX outputs) (2) PSCLK Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 105 R DCM Timing Parameters Input Clock Tolerances Table 45: Input Clock Tolerances Speed Grade -8 Description Symbol Constraints Min -7 Max Min -6 Max Min Max Units Input Clock Low/high Pulse Width PSCLK PSCLK_PULSE < 1MHz ns CLKIN (3) CLKIN_PULSE 1 - 10 MHz ns 10 - 25 MHz ns 25 - 50 MHz ns 50 - 100 MHz ns 100 - 150 MHz ns 150 - 200 MHz ns 200 - 250 MHz ns 250 - 300 MHz ns 300 - 350 MHz ns 350 - 400 MHz ns > 400 MHz ns Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_CYC_JITT_DLL_LF ps CLKIN (using CLKFX outputs) (2) CLKIN_CYC_JITT_FX_LF ps Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_CYC_JITT_DLL_HF ps CLKIN (using CLKFX outputs) (2) CLKIN_CYC_JITT_FX_HF ps Input Clock Period Jitter (Low Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_PER_JITT_DLL_LF ns CLKIN (using CLKFX outputs) (2) CLKIN_PER_JITT_FX_LF ns Input Clock Period Jitter (High Frequency Mode) CLKIN (using DLL outputs) (1) CLKIN_PER_JITT_DLL_HF ns CLKIN (using CLKFX outputs) (2) CLKIN_PER_JITT_FX_HF ns Feedback Clock Path Delay Variation CLKFB off-chip feedback ns CLKFB_DELAY_VAR_EXT Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. If both DLL and CLKFX outputs are used, follow the more restrictive specification. 3. Specification also applies to PSCLK. 106 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Output Clock Jitter Table 46: Output Clock Jitter Speed Grade -8 Description Symbol Constraints Min -7 Max Min -6 Max Min Max Units Clock Synthesis Period Jitter CLK0 CLKOUT_PER_JITT_0 ps CLK90 CLKOUT_PER_JITT_90 ps CLK180 CLKOUT_PER_JITT_180 ps CLK270 CLKOUT_PER_JITT_270 ps CLK2X, CLK2X180 CLKOUT_PER_JITT_2X ps CLKDV (integer division) CLKOUT_PER_JITT_DV1 ps CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 ps CLKFX, CLKFX180 CLKOUT_PER_JITT_FX ps Output Clock Phase Alignment Table 47: Output Clock Phase Alignment Speed Grade -8 Description Symbol Constraints Min -7 Max Min -6 Max Min Max Units Phase Offset Between CLKIN and CLKFB CLKIN/CLKFB CLKIN_CLKFB_PHASE ps Phase Offset Between Any DCM Outputs All CLK outputs CLKOUT_PHASE ps DLL outputs (1) CLKOUT_DUTY_CYCLE_DLL ps CLKFX outputs CLKOUT_DUTY_CYCLE_FX ps Duty Cycle Precision Notes: 1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 107 R DCM Timing Parameters Miscellaneous Timing Parameters Table 48: Miscellaneous Timing Parameters Speed Grade Description Symbol Constraints FCLKIN -8 -7 -6 Units Time Required to Achieve LOCK Using DLL outputs (1) Using CLKFX outputs Additional lock time with fine phase shifting LOCK_DLL: LOCK_DLL_60 > 60MHz us LOCK_DLL_50_60 50 - 60 MHz us LOCK_DLL_40_50 40 - 50 MHz us LOCK_DLL_30_40 30 - 40 MHz us LOCK_DLL_24_30 24 - 30 MHz us LOCK_FX_MIN ms LOCK_FX_MAX ms LOCK_DLL_FINE_SHIFT us FINE_SHIFT_RANGE ns DCM_TAP_MIN ps DCM_TAP_MAX ps Fine Phase Shifting Absolute shifting range Delay Lines Tap delay resolution Notes: 1. ""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. Frequency Synthesis Table 49: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 32 CLKFX_DIVIDE 1 32 108 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Virtex-II Pro Platform FPGAs: DC and Switching Characteristics Parameter Cross-Reference Table 50: Parameter Cross-Reference Libraries Guide Data Sheet DLL_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_{1X|2X|DV}_LF DFS_CLKOUT_{MIN|MAX}_LF CLKOUT_FREQ_FX_LF DLL_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_DLL_LF DFS_CLKIN_{MIN|MAX}_LF CLKIN_FREQ_FX_LF DLL_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_{1X|DV}_HF DFS_CLKOUT_{MIN|MAX}_HF CLKOUT_FREQ_FX_HF DLL_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_DLL_HF DFS_CLKIN_{MIN|MAX}_HF CLKIN_FREQ_FX_HF Revision History This section records the change history for this module of the data sheet. Date Version 01/31/02 1.0 Revision Initial Xilinx release. Virtex-II Pro Data Sheet Modules The Virtex-II Pro Data Sheet contains the following modules: * Virtex-II Pro Platform FPGAs: Introduction and Overview (Module 1) * Virtex-II Pro Platform FPGAs: DC and Switching Characteristics (Module 3) * Virtex-II Pro Platform FPGAs: Functional Description (Module 2) * Virtex-II Pro Platform FPGAs: Pinout Information (Module 4) DS083-3 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 109 R Virtex-II Pro Data Sheet Modules 110 www.xilinx.com 1-800-255-7778 DS083-3 (v1.0) January 31, 2002 Advance Product Specification R Part II: Virtex-II Pro User Guide This section contains information on how to configure and use Virtex-II Pro devices. The following topics are covered: Chapter 1: Timing Models Chapter 2: Design Considerations Chapter 3: Configuration Chapter 4: PCB Design Considerations Appendix A: BitGen and PROMGen Switches and Options Appendix B: XC18V00 Series PROMs UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 111 R 112 Chapter : www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Chapter 1 Timing Models Summary The following topics are covered in this chapter: * Processor Block Timing Model * Rocket I/O Timing Model * CLB / Slice Timing Model * Block SelectRAM Timing Model * Embedded Multiplier Timing Model * IOB Timing Model * Pin-to-Pin Timing Model * Digital Clock Manager Timing Model Introduction Due to the large size and complexity of Virtex-II Pro FPGAs, understanding the timing associated with the various paths and functional elements has become a difficult and important problem. Although it is not necessary to understand the various timing parameters in order to implement most designs using Xilinx software, a thorough timing model can assist advanced users in analyzing critical paths, or planning speed-sensitive designs. The Timing Model chapter is broken up into sections consisting of three basic components: * Functional Element Diagram - basic architectural schematic illustrating pins and connections. * * Timing Parameters - Virtex-II Pro Data Sheet timing parameter definitions. Timing Diagram - illustrates functional element timing parameters relative to each other. This chapter was written with the Xilinx Timing Analyzer software (TRCE) in mind. All pin names, parameter names, and paths are consistent with Post Route Timing and PreRoute Static Timing reports. Use the models in this chapter in conjunction with both the Timing Analyzer software and the section on switching characteristics in the Virtex-II Pro Data Sheet. Most of the timing parameters found in the section on switching characteristics are described in this chapter. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 113 R Chapter 1: Timing Models Processor Block Timing Model Introduction This section explains all of the timing parameters associated with the IBM PPC405 Processor Block. It is intended to be used in conjunction with Module 3 of the Virtex-II Pro Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the data sheet. CPM INPUT OCM INPUT CPM OUTPUT OCM OUTPUT RESET INPUT DCR INPUTS RESET OUTPUT DCR OUTPUTS PPC INPUT JTAG INPUTS PPC OUTPUT JTAG OUTPUTS PLB INPUT TRACE INPUTS PLB OUTPUT EIC INPUT DEBUG INPUTS TRACE OUTPUTS IBM PPC405 Processor Block DEBUG OUTPUTS CPMC405CLOCK JTGC405TCK PLBCLK BRAMISCOMCLK BRAMDSOCMCLK UG012_C1_01_121701 Figure 1-1: PowerPC 405 Processor Block (Simplified) There are hundreds of signals entering and exiting the processor block. The model presented in this section treats the processor block as a "black box." Propagation delays internal to the processor block and core logic are ignored. Signals are characterized with setup and hold times for inputs and clock to valid output times for outputs. Signals are grouped by which interface block they originate from: Processor Local Bus (PLB) , Device Control Register (DCR), External Interrupt Controller (EIC), Reset (RST), Clock and Power Management (CPM), Debug (DBG), PowerPC miscellaneous (PPC), Trace Port (TRC), JTAG, Instruction-Side On-Chip Memory (ISOCM), and Data-Side On-Chip Memory (DSOCM). 114 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block Timing Model Table 1-1 associates five clocks with their corresponding interface blocks. All signal parameters discussed in this section are characterized at a rising clock edge. Exceptions to this rule, such as for the JTAG signals, are pointed out where applicable. Table 1-1: Clocks and Corresponding Processor Interface Blocks CLOCK SIGNAL DESCRIPTION INTERFACE CPMC405CLOCK Main processor core clock DCR EIC RST CPM DBG PPC TRC PLBCLK Processor Local Bus clock PLB JTAGC405TCK Clock for JTAG logic within the processor core JTAG BRAMISOCMCLK Clock for the ISOCM Controller ISOCM BRAMDSOCMCLK Clock for the DSOCM Controller DSOCM Timing Parameters Parameter designations are constructed to reflect the functions they perform, as well as the interface blocks and clocks they correspond to. The following three sections explain the meaning of each of the basic timing parameter designations used in the tables: Setup/Hold Times of Inputs Relative to Clock Basic Format: ParameterName_BLOCK where ParameterName = T with subscript string defining the timing relationship BLOCK name of applicable PPC405 processor interface block (refer to Table 1-1) = ParameterName Format: TPxCK = TPCKx = Setup time before clock edge Hold time after clock edge where x = C D (Control inputs) (Data inputs) Setup/Hold Time (Examples): TPCCK _PLB/TPCKC _PLB Setup/hold times of PLB Control inputs relative to rising edge of PLB clock TPDCK _ISOCM/TPCKD _ISOCM Setup/hold times of BRAMISOCM Data inputs relative to rising edge of BRAMISOCM clock UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 115 R Chapter 1: Timing Models Clock to Output Delays Basic Format: ParameterName_BLOCK where ParameterName = T with subscript string defining the timing relationship BLOCK name of applicable PPC405 processor interface block (refer to Table 1-1) = ParameterName Format: TPCKx = Delay time from clock edge to output where x = AO CO DO (Address outputs) (Control outputs) (Data outputs) Output Delay Time (Examples): TPCKAO _ISOCM TPCKCO _DCR TPCKDO _PLB Rising edge of BRAMISOCM clock to BRAMISOCM Address outputs Rising edge of Core clock to DCR Control outputs Rising edge of PLB clock to PLB Data outputs Clock Pulse Width ParameterName Format: TxPWH = TxPWL = Minimum pulse width, High state Minimum pulse width, Low state where x = C P J I D (Core) (PLB) (JTAG) (ISOCM) (DSOCM) Pulse Width (Examples): TCPWH TPPWL Minimum pulse width, core clock, High state Minimum pulse width, PLB clock, Low state Timing Parameter Tables and Diagram The following five tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table 1-1, along with the signals from the processor block that correspond to each parameter. A timing diagram (Figure 1-2) illustrates the timing relationships. * * * * * 116 Table 1-2, Parameters Relative to the Core Clock (CPMC405CLOCK), page 117 Table 1-3, Parameters Relative to the PLB Clock (PLBCLK), page 118 Table 1-4, Parameters Relative to the JTAG Clock (JTAGC405TCK), page 119 Table 1-5, Parameters Relative to the ISOCM Clock (BRAMISOCMCLK), page 119 Table 1-6, Parameters Relative to the DSOCM Clock (BRAMDSOCMCLK), page 120 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block Timing Model Table 1-2: Parameters Relative to the Core Clock (CPMC405CLOCK) Parameter Function Signals Setup/Hold: TPCCK_DCR/TPCKC_DCR Control inputs DCRC405ACK TPDCK_DCR/TPCKD_DCR Data inputs DCRC405DBUSIN[0:31] TPCCK_CPM/TPCKC_CPM Control inputs CPMC405TIMERTICK CPMC405CPUCLKEN CPMC405TIMERCLKEN CPMC405JTAGCLKEN TPCCK_RST/TPCKC_RST Control inputs RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS TPCCK_DBG/TPCKC_DBG Control inputs DBGC405DEBUGHALT DBGC405UNCONDDEBUGEVENT TPCCK_TRC/TPCKC_TRC Control inputs TRCC405TRACEDISABLE TRCC405TRIGGEREVENTIN TPCCK_EIC/TPCKC_EIC Control inputs EICC405CRITINPUTIRQ EICC405EXTINPUTIRQ TPCKCO_DCR Control outputs C405DCRREAD C405DCRWRITE TPCKAO_DCR Address outputs C405DCRABUS[0:9] TPCKDO_DCR Data outputs C405DCRDBUSOUT[0:31] TPCKCO_CPM Control outputs C405CPMMSREE C405CPMMSRCE C405CPMTIMERIRQ C405CPMTIMERRESETREQ C405CPMCORESLEEPREQ TPCKCO_RST Control outputs C405RSTCHIPRESETREQ C405RSTCORERESETREQ C405RSTSYSRESETREQ TPCKCO_DBG Control outputs C405DBGMSRWE C405DBGSTOPACK C405DBGWBCOMPLETE C405DBGWBFULL C405DBGWBIAR[0:29] TPCKCO_PPC Control outputs C405XXXMACHINECHECK TPCKCO_TRC Control outputs C405TRCCYCLE C405TRCEVENEXECUTIONSTATUS[0:1] C405TRCODDEXECUTIONSTATUS[0:1] C405TRCTRACESTATUS[0:3] C405TRCTRIGGEREVENTOUT C405TRCTRIGGEREVENTTYPE[0:10] TCPWH Clock pulse width, High state CPMC405CLOCK TCPWL Clock pulse width, Low state CPMC405CLOCK Clock to Out: Clock: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 117 R Table 1-3: Chapter 1: Timing Models Parameters Relative to the PLB Clock (PLBCLK) Parameter Function Signals Setup/Hold: TPCCK_PLB/TPCKC_PLB Contol inputs PLBC405DCUADDRACK PLBC405DCUBUSY PLBC405DCUERR PLBC405DCURDDACK PLBC405DCUSSIZE1 PLBC405DCUWRDACK PLBC405ICURDWDADDR[1:3] PLBC405DCURDWDADDR[1:3] PLBC405ICUADDRACK PLBC405ICUBUSY PLBC405ICUERR PLBC405ICURDDACK PLBC405ICUSSIZE1 TPDCK_PLB/TPCKD_PLB Data inputs PLBC405ICURDDBUS[0:63] PLBC405DCURDDBUS[0:63] TPCKCO_PLB Control outputs C405PLBDCUABORT C405PLBDCUBE[0:7] C405PLBDCUCACHEABLE C405PLBDCUGUARDED C405PLBDCUPRIORITY[0:1] C405PLBDCUREQUEST C405PLBDCURNW C405PLBDCUSIZE2 C405PLBDCUU0ATTR C405PLBDCUWRITETHRU C405PLBICUABORT C405PLBICUCACHEABLE C405PLBICUPRIORITY[0:1] C405PLBICUREQUEST C405PLBICUSIZE[2:3] C405PLBICUU0ATTR TPCKDO_PLB Data outputs C405PLBDCUWRDBUS[0:63] TPCKAO_PLB Address outputs C405PLBDCUABUS[0:31] C405PLBICUABUS[0:29] TPPWH Clock pulse width, High state PLBCLK TPPWL Clock pulse width, Low state PLBCLK Clock to Out: Clock: 118 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block Timing Model Table 1-4: Parameters Relative to the JTAG Clock (JTAGC405TCK) Parameter Function Signals Setup/Hold: TPCCK_JTAG/TPCKC_JTAG Control inputs JTGC405BNDSCANTDO JTGC405TDI JTGC405TMS JTGC405TRSTNEG CPMC405CORECLKINACTIVE DBGC405EXTBUSHOLDACK Control outputs C405JTGCAPTUREDR C405JTGEXTEST (1) C405JTGPGMOUT (2) C405JTGSHIFTDR C405JTGTDO (1) C405JTGTDOEN (1) C405JTGUPDATEDR TJPWH Clock pulse width, High state JTGC405TCK TJPWL Clock pulse width, Low state JTGC405TCK Clock to Out: TPCKCO_JTAG Clock: Notes: 1. Synchronous to the negative edge of JTGC405TCK 2. Synchronous to CPMC405CLOCK Table 1-5: Parameters Relative to the ISOCM Clock (BRAMISOCMCLK) Parameter Function Signals Setup/Hold: TPDCK_ISOCM/TPCKD_ISOCM Data inputs BRAMISOCMRDDBUS[0:63] TPCKCO_ISOCM Control outputs ISOCMBRAMEN ISOCMBRAMODDWRITEEN ISOCMBRAMEVENWRITEEN TPCKAO_ISOCM Address outputs ISOCMBRAMRDABUS[8:28] ISOCMBRAMWRABUS[8:28] TPCKDO_ISOCM Data outputs ISOCMBRAMWRDBUS[0:31] TIPWH Clock pulse width, High state BRAMISOCMCLK TIPWL Clock pulse width, Low state BRAMISOCMCLK Clock to Out: Clock: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 119 R Table 1-6: Chapter 1: Timing Models Parameters Relative to the DSOCM Clock (BRAMDSOCMCLK) Parameter Function Signals Setup/Hold: TPDCK_DSOCM/TPCKD_DSOCM Data inputs BRAMDSOCMRDDBUS[0:31] TPCKCO_DSOCM Control outputs DSOCMBRAMEN DSOCMBRAMBYTEWRITE[0:3] DSOCMBUSY TPCKDO_DSOCM Data outputs DSOCMBRAMWRDBUS[0:31] TPCKAO_DSOCM Address outputs DSOCMBRAMABUS[8:29] TDPWH Clock, Pulse width high BRAMDSOCMCLK TDPWL Clock, Pulse width low BRAMDSOCMCLK Clock to Out: Clock: 1 2 Tx PWL Tx PWH CLOCK TPCCK TPCKC CONTROL INPUTS TPCKCO CONTROL OUTPUTS TPCKDO DATA OUTPUTS TPDCK TPCKD DATA INPUTS TPCKAO ADDRESS OUTPUTS UG012_C1_02_121701 Figure 1-2: 120 Processor Block Timing Relative to Clock Edge www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Timing Model Rocket I/O Timing Model Introduction This section explains all of the timing parameters associated with the Rocket I/OTM transceiver core. It is intended to be used in conjunction with Module 3 of the Virtex-II Pro Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the data sheet. There are many signals entering and exiting the Rocket I/O core. (Refer to Figure 1-3.) The model presented in this section treats the Rocket I/O core as a "black box." Propagation delays internal to the Rocket I/O core logic are ignored. Signals are characterized with setup and hold times for inputs, and with clock to valid output times for outputs. There are five clocks associated with the Rocket I/O core, but only three of these clocks-- RXUSRCLK, RXUSRCLK2, and TXUSRCLK2--have I/Os that are synchronous to them. The following table gives a brief description of all of these clocks. For an in-depth discussion of clocking the Rocket I/O core, refer to the Rocket I/O Users Guide. Table 1-7: Rocket I/O Clock Descriptions CLOCK SIGNAL DESCRIPTION REFCLK Main reference clock for Rocket I/O TXUSRCLK Clock used for writing the TX buffer. Frequency-locked to REFCLK. TXUSRCLK2 Clocks transmission data and status and reconfiguration data between the transceiver and the FPGA core. Relationship between TXUSRCLK2 and TXUSRCLK depends on width of transmission data path. RXUSRCLK Clock used for reading the RX elastic buffer. Clocks CHBONDI and CHBONO into and out of the transceiver. Typically the same as TXUSRCLK. RXUSRCLK2 Clocks receiver data and status between the transceiver and the FPGA core. Typically the same as TXUSRCLK2. Relationship between RXUSRCLK2 and RXUSRCLK depends on width of receiver data path. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 121 R Chapter 1: Timing Models PACKAGE PINS AVCCAUXRX VTRX MULTI-GIGABIT TRANSCEIVER CORE FPGA FABRIC Power Down 2.5V RX POWERDOWN RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN Termination Supply RX CRC Check RXCHECKINGCRC RXCRCERR RXDATA[15:0] RXDATA[31:16] RXP Comma Detect Realign RXN 8B/10B Decoder Clock Manager RXNOTINTABLE[3:0] RXDISPERR[3:0] RXCHARISK[3:0] RXCHARISCOMMA[3:0] RXRUNDISP[3:0] RXBUFSTATUS[1:0] ENCHANSYNC CHBONDDONE CHBONDI[3:0] CHBONDO[3:0] Channel Bonding and Clock Correction Parallel Loopback Path Serial Loopback Path Deserializer RX Elastic Buffer RXLOSSOFSYNC RXCLKCORCNT TXBUFERR TXFORCECRCERR TXDATA[15:0] TXDATA[31:16] TX FIFO TXP TXN 8B/10B Encoder CRC Output Polarity Serializer TXBYPASS8B10B[3:0] TXCHARISK[3:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXKERR[3:0] TXRUNDISP[3:0] TXPOLARITY TXINHIBIT GNDA AVCCAUXTX VTTX LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 TX/RX GND 2.5V TX Termination Supply TX DS083-2_04_010202 Figure 1-3: Rocket I/O Block Diagram Timing Parameters Parameter designations are constructed to reflect the functions they perform, as well as the I/O signals to which they are synchronous. The following subsections explain the meaning of each of the basic timing parameter designations used in the tables. 122 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Timing Model Setup/Hold Times of Inputs Relative to Clock Basic Format: ParameterName_SIGNAL where ParameterName = SIGNAL = T with subscript string defining the timing relationship name of Rocket I/O signal synchronous to the clock ParameterName Format: TGxCK = TGCKx = where x = Setup time before clock edge Hold time after clock edge C D (Control inputs) (Data inputs) Setup/Hold Time (Examples): TGCCK _RRST/TGCKC _PLB TGDCK _TDAT/TGCKD _TDAT Setup/hold times of RX Reset input relative to rising edge of RXUSRCLK2 Setup/hold times of TX Data inputs relative to rising edge of TXUSRCLK2 Clock to Output Delays Basic Format: ParameterName_SIGNAL where ParameterName = T with subscript string defining the timing relationship SIGNAL = name of Rocket I/O signal synchronous to the clock ParameterName Format: TGCKx = where x = Delay time from clock edge to output CO DO ST (Control outputs) (Data outputs) (Status outputs) Output Delay Time (Examples): TGCKCO _CHBO TGCKDO _RDAT TGCKST _TBERR Rising edge of RXUSRCLK to Channel Bond outputs Rising edge of RXUSRCLK2 to RX Data outputs Rising edge of TXUSRCLK2 to TX Buffer Err output Clock Pulse Width ParameterName Format: TxPWH = TxPWL = where x = Minimum pulse width, High state Minimum pulse width, Low state REF TX TX2 RX RX2 (REFCLK) (TXUSRCLK) (TXUSRCLK2) (RXUSRCLK) (RXUSRCLK2) Pulse Width (Examples): TTX2PWL TREFPWH UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Minimum pulse width, TX2 clock, Low state Minimum pulse width, Reference clock, High state www.xilinx.com 1-800-255-7778 123 R Chapter 1: Timing Models Timing Parameter Tables and Diagram The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table 1-7, along with the Rocket I/O signals that are synchronous to each clock. (No signals are synchronous to REFCLK or TXUSRCLK.) A timing diagram (Figure 1-4) illustrates the timing relationships. * * * * Table 1-8: Table 1-8, Parameters Relative to the RX User Clock (RXUSRCLK), page 124 Table 1-9, Parameters Relative to the RX User Clock2 (RXUSRCLK2), page 124 Table 1-10, Parameters Relative to the TX User Clock2 (TXUSRCLK2), page 125 Table 1-11, Miscellaneous Clock Parameters, page 125 Parameters Relative to the RX User Clock (RXUSRCLK) Parameter Function Signals Setup/Hold: TGCCK_CHBI/TGCKC_CHBI Control inputs CHBONDI[3:0] Control outputs CHBONDO[3:0] TRXPWH Clock pulse width, High state RXUSRCLK TRXPWL Clock pulse width, Low state RXUSRCLK Clock to Out: TGCKCO_CHBO Clock: Table 1-9: Parameters Relative to the RX User Clock2 (RXUSRCLK2) Parameter Function Signals Setup/Hold: TGCCK_RRST/TGCKC_RRST Control input RXRESET TGCCK_RPOL/TGCKC_RPOL Control input RXPOLARITY TGCCK_ECSY/TGCKC_ECSY Control input ENCHANSYNC TGCKST_RNIT Status outputs RXNOTINTABLE[3:0] TGCKST_RDERR Status outputs RXDISPERR[3:0] TGCKST_RCMCH Status outputs RXCHARISCOMMA[3:0] TGCKST_ALIGN Status output RXREALIGN TGCKST_CMDT Status output RXCOMMADET TGCKST_RLOS Status outputs RXLOSSOFSYNC[1:0] TGCKST_RCCCNT Status outputs RXCLKCORCNT[2:0] TGCKST_RBSTA Status outputs RXBUFSTATUS[1:0] TGCKST_RCCRC Status output RXCHECKINGCRC TGCKST_RCRCE Status output RXCRCERR TGCKST_CHBD Status output CHBONDDONE TGCKST_RKCH Status outputs RXCHARISK[3:0] TGCKST_RRDIS Status outputs RXRUNDISP[3:0] TGCKDO_RDAT Data outputs RXDATA[31:0] TRX2PWH Clock pulse width, High state RXUSRCLK2 TRX2PWH Clock pulse width, Low state RXUSRCLK2 Clock to Out: Clock: 124 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Timing Model Table 1-10: Parameters Relative to the TX User Clock2 (TXUSRCLK2) Parameter Function Signals Setup/Hold: TGCCK_CFGEN/TGCKC_CFGEN Control inputs CONFIGENABLE TGCCK_TBYP/TGCKC_TBYP Control inputs TXBYPASS8B10B[3:0] TGCCK_TCRCE/TGCKC_TCRCE Control inputs TXFORCECRCERR TGCCK_TPOL/TGCKC_TPOL Control inputs TXPOLARITY TGCCK_TINH/TGCKC_TINH Control inputs TXINHIBIT TGCCK_LBK/TGCKC_LBK Control inputs LOOPBACK[1:0] TGCCK_TRST/TGCKC_TRST Control inputs TXRESET TGCCK_TKCH/TGCKC_TKCH Control inputs TXCHARISK[3:0] TGCCK_TCDM/TGCKC_TCDM Control inputs TXCHARDISPMODE[3:0] TGCCK_TCDV/TGCKC_TCDV Control inputs TXCHARDISPVAL[3:0] TGDCK_CFGIN/TGCKD_CFGIN Data inputs CONFIGIN TGDCK_TDAT/TGCKD_TDAT Data inputs TXDATA[31:0] TGCKST_TBERR Status outputs TXBUFERR TGCKST_TKERR Status outputs TXKERR[3:0] TGCKDO_TRDIS Data outputs TXRUNDISP[3:0] TGCKDO_CFGOUT Data outputs CONFIGOUT TTX2PWH Clock pulse width, High state TXUSRCLK2 TTX2PWH Clock pulse width, Low state TXUSRCLK2 Clock to Out: Clock: Table 1-11: Miscellaneous Clock Parameters Parameter Function Signals Clock: TREFPWH Clock pulse width, High state REFCLK (1) TREFPWL Clock pulse width, Low state REFCLK (1) TTXPWH Clock pulse width, High state TXUSRCLK (2) TTXPWL Clock pulse width, Low state TXUSRCLK (2) Notes: 1. REFCLK is not synchronous to any Rocket I/O signals. 2. TXUSRCLK is not synchronous to any Rocket I/O signals. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 125 R Chapter 1: Timing Models 1 2 TxGWL TxGWH CLOCK TGCCK TGCKC CONTROL INPUTS TGCKCO CONTROL OUTPUTS TGCKDO DATA OUTPUTS TGDCK TGCKD DATA INPUTS UG012_106_02_100101 Figure 1-4: Rocket I/O Timing Relative to Clock Edge CLB / Slice Timing Model Introduction This section describes all timing parameters reported in the Virtex-II Pro Data Sheet that are associated with slices and Configurable Logic Blocks (CLBs). It consists of three parts corresponding to their respective (switching characteristics) sections in the data sheet: 126 * * General Slice Timing Model and Parameters (CLB Switching Characteristics) * Slice SRL Timing Model and Parameters (CLB SRL Switching Characteristics) Slice Distributed RAM Timing Model and Parameters (CLB Distributed RAM Switching Characteristics) www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CLB / Slice Timing Model General Slice Timing Model and Parameters Figure 1-5 illustrates the details of a Virtex-II Pro slice. Note: Some elements of the Virtex-II Pro slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. FXINA FX MUXFX FXINB Y DY D LUT G inputs Q YQ FF/LAT CE D CLK SR REV BY F5 MUXF5 X LUT F inputs DX D D Q XQ FF/LAT CE CLK SR REV BX CE CLK SR UG002_C3_017_113000 Figure 1-5: General Slice Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 127 R Chapter 1: Timing Models Timing Parameters Parameter Function Control Signal Description Combinatorial Delays TILO F/G inputs to X/Y outputs Propagation delay from the F/G inputs of the slice, through the look-up tables (LUTs), to the X/Y outputs of the slice. TIF5 F/G inputs to F5 output Propagation delay from the F/G inputs of the slice, through the LUTs and MUXF5 to the F5 output of the slice. TIF5X F/G inputs to X output Propagation delay from the F/G inputs of the slice, through the LUTs and MUXF5 to the X output of the slice. TIFXY FXINA/FXINB inputs to Y output Propagation delay from the FXINA/FXINB inputs, through MUXFX to the Y output of the slice. TIFNCTL Transparent Latch input to XQ/YQ outputs Incremental delay through a transparent latch to XQ/YQ outputs. Sequential Delays TCKO FF Clock (CLK) to XQ/YQ outputs Time after the clock that data is stable at the XQ/YQ outputs of the slice sequential elements (configured as a flip-flop). TCKLO Latch Clock (CLK) to XQ/YQ outputs Time after the clock that data is stable at the XQ/YQ outputs of the slice sequential elements (configured as a latch). Setup and Hold for Slice Sequential Elements TxxCK = Setup time (before clock edge) TCKxx = Hold time (after clock edge) TDICK/TCKDI TDYCK/TCKDY TDXCK/TCKDX TCECK/TCKCE 128 The following descriptions are for setup times only. BX/BY inputs Time before Clock (CLK) that data from the BX or BY inputs of the slice must be stable at the D-input of the slice sequential elements (configured as a flip-flop). DY input Time before Clock (CLK) that data from the DY input of the slice must be stable at the D-input of the slice sequential elements (configured as a flip-flop). DX input Time before Clock (CLK) that data from the DX input of the slice must be stable at the D-input of the slice sequential elements (configured as a flip-flop). CE input Time before Clock (CLK) that the CE (Clock Enable) input of the slice must be stable at the CE-input of the slice sequential elements (configured as a flip-flop). www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CLB / Slice Timing Model Parameter TRCK/TCKR Function Control Signal Description Time before CLK that the SR (Set/Reset) and the BY (Rev) inputs of the slice must be stable at the SR/Rev-inputs of the slice sequential elements (configured as a flipflop). Synchronous set/reset only. SR/BY inputs Clock CLK TCH Minimum Pulse Width, High. TCL Minimum Pulse Width, Low. Set/Reset Minimum Pulse Width for the SR (Set/Reset) and BY (Rev) pins. TRPW Propagation delay for an asynchronous Set/Reset of the slice sequential elements. From SR/BY inputs to XQ/YQ outputs. TRQ Toggle Frequency - Maximum Frequency that a CLB flip-flop can be clocked: FTOG 1/(TCH+TCL) Figure 1-6 illustrates general timing characteristics of a Virtex-II Pro slice. 1 2 3 CLK TCECK CE TDYCK DY (DATA) TRCK SR (RESET) TCKO TCKO YQ (OUT) UG002_C3_018_101600 Figure 1-6: General Slice Timing Diagram * At time TCECK before Clock Event 1, the Clock-Enable signal becomes valid-high at the CE input of the slice register. * At time TDYCK before Clock Event 1, data from the DY input becomes valid-high at the D input of the slice register and is reflected on the YQ pin at time TCKO after Clock Event 1*. * At time TRCK before Clock Event 3, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting the slice register, and this is reflected on the YQ pin at time TCKO after Clock Event 3. * NOTE: In most cases software uses the DX/DY inputs to route data to the slice registers when at all possible. This is the fastest path to the slice registers and saves other slice routing resources. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 129 R Chapter 1: Timing Models Slice Distributed RAM Timing Model and Parameters Figure 1-7 illustrates the details of distributed RAM implemented in a Virtex-II Pro slice. Note: Some elements of the Virtex-II Pro slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. MUXFX FXINA FX FXINB ADDRESS RAM G4 G3 G2 G1 D WS Y DI BY DATA_IN or Address SLICEWE[2:0] WSGEN WE CK MUXF5 F5 WS ADDRESS DI RAM G4 G3 G2 G1 X D BX DATA_IN or Address CLK SR (Write Enable) UG002_C3_019_1204 00 Figure 1-7: 130 Slice Distributed RAM Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CLB / Slice Timing Model Timing Parameters Parameter Function Control Signal Description Sequential Delays for Slice LUT Configured as RAM (Distributed RAM) TSHCKO16 CLK to X/Y outputs (WE active) in 16x1 mode Time after the Clock (CLK) of a WRITE operation that the data written to the distributed RAM (in 16x1 mode) is stable on the X/Y outputs of the slice. TSHCKO32 CLK to X/Y outputs (WE active) in 32x1 mode Time after the Clock (CLK) of a WRITE operation that the data written to the distributed RAM (in 32x1 mode) is stable on the X/Y outputs of the slice. TSHCKOF5 CLK to F5 output (WE active) Time after the Clock (CLK) of a WRITE operation that the data written to the distributed RAM is stable on the F5 output of the slice. Setup and Hold for Slice LUT Configured as RAM (Distributed RAM) TxS = Setup time (before clock edge) TxH = Hold time (after clock edge) The following descriptions are for setup times only. TDS/TDH BX/BY Data inputs (DI) Time before the clock that data must be stable at the DI input of the slice LUT (configured as RAM), via the slice BX/BY inputs. TAS/TAH F/G Address inputs Time before the clock that address signals must be stable at the F/G inputs of the slice LUT (configured as RAM). WE input (SR) Time before the clock that the Write Enable signal must be stable at the WE input of the slice LUT (configured as RAM). TWES/TWEH Clock CLK TWPH Minimum Pulse Width, High (for a Distributed RAM clock). TWPL Minimum Pulse Width, Low (for a Distributed RAM clock). TWC Minimum clock period to meet address write cycle time. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 131 R Chapter 1: Timing Models Figure 1-8 illustrates the timing characteristics of a 16-bit distributed RAM implemented in a Virtex-II Pro slice (LUT configured as RAM). 1 TWC 2 3 4 5 6 7 TWPH TWPL CLK ADDR TAS 2 F 3 4 0 1 5 E TDS DATA_IN 1 X TWES WE DATA_OUT (X/Y Output) X 0 TILO TILO TSHCK016 1 WRITE MEM(F) READ 0 1 0 WRITE WRITE WRITE MEM(E) READ UG002_C3_020_031301 Figure 1-8: Slice Distributed RAM Timing Diagram Clock Event 1: WRITE Operation During a WRITE operation, the contents of the memory at the address on the ADDR inputs is changed. The data written to this memory location is reflected on the X/Y outputs synchronously. * At time TWES before Clock Event 1, the Write Enable signal (WE) becomes valid-high, enabling the RAM for the following WRITE operation. * At time TAS before Clock Event 1, the address (2) becomes valid at the F/G inputs of the RAM. * At time TDS before Clock Event 1, the DATA becomes valid (1) at the DI input of the RAM and is reflected on the X/Y output at time TSHCKO16 after Clock Event 1. Clock Event 2: READ Operation All READ operations are asynchronous in distributed RAM. As long as write-enable (WE) is Low, the address bus can be asserted at any time, and the contents of the RAM at that address are reflected on the X/Y outputs after a delay of length TILO (propagation delay through a LUT). Note that the Address (F) is asserted after Clock Event 2, and that the contents of the RAM at that location are reflected on the output after a delay of length TILO. 132 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CLB / Slice Timing Model Slice SRL Timing Model and Parameters Figure 1-9 illustrates shift register implementation in a Virtex-II Pro slice. Note: Some elements of the Virtex-II Pro slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. Shift_In MUXFX FXINA FX FXINB Y YB ADDRESS SRL G3 G2 G1 G0 D MC15 WS DI BY (DATA_IN or ADDRESS) WSGEN WE CK MUXF5 Shift_In F5 WS X DI ADDRESS F3 F2 F1 F0 SRL D XB MC15 SR CLK BX (DATA_IN or ADDRESS) Shift_Out UG002_C3_021_113000 Figure 1-9: Slice SLR Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 133 R Chapter 1: Timing Models Timing Parameters Parameter Control Signal Function Description Sequential Delays for Slice LUT Configured as SRL (Select Shift Register) CLK to X/Y outputs Time after the Clock (CLK) of a WRITE operation that the data written to the SRL is stable on the X/Y outputs of the slice. TCKSH CLK to Shiftout Time after the Clock (CLK) of a WRITE operation that the data written to the SRL is stable on the Shiftout or XB/YB outputs of the slice. TREGF5 CLK to F5 output Time after the Clock (CLK) of a WRITE operation that the data written to the SRL is stable on the F5 output of the slice. TREG Setup/Hold for Slice LUT Configured as SRL (Select Shift Register) TxxS = Setup time (before clock edge) TxxH= Hold time (after clock edge) The following descriptions are for setup times only. TSRLDS/ TSRLDH BX/BY Data inputs (DI) Time before the clock that data must be stable at the DI input of the slice LUT (configured as SRL), via the slice BX/BY inputs. TWSS/TWSH CE input (WE) Time before the clock that the Write Enable signal must be stable at the WE input of the slice LUT (configured as SRL). Clock CLK TSRPH Minimum Pulse Width, High (for an SRL clock). TSRPL Minimum Pulse Width, Low (for an SRL clock). Figure 1-10 illustrates the timing characteristics of a 16-bit shift register implemented in a Virtex-II Pro slice (LUT configured as SRL). 1 TSRPH 2 3 4 5 6 TSRPL CLK TWSS Write Enable (SR) TSRLDS Shift_In (DI) 0 Address Data Out (D) X 1 0 TREG 0 1 0 1 0 2 1 TILO 1 1 0 TILO 1 1 0 1 16 TREGXB MSB (MC15) X X X X X X X 0 UG002_C3_022_102700 Figure 1-10: Slice SLR Timing Diagram 134 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAM Timing Model Clock Event 1: Shift_In During a WRITE (Shift_In) operation, the single-bit content of the register at the address on the ADDR inputs is changed, as data is shifted through the SRL. The data written to this register is reflected on the X/Y outputs synchronously, if the address is unchanged during the clock event. If the ADDR inputs are changed during a clock event, the value of the data at the addressable output (D) is invalid. * At time TWSS before Clock Event 1, the Write Enable signal (SR) becomes valid-high, enabling the SRL for the WRITE operation that follows. * At time TSRLDS before Clock Event 1 the data becomes valid (0) at the DI input of the SRL and is reflected on the X/Y output after a delay of length TREG after Clock Event 1*. * Note: Since the address 0 is specified at Clock Event 1, the data on the DI input is reflected at the D output, because it is written to Register 0. Clock Event 2: Shift_In * At time TSRLDS before Clock Event 2, the data becomes valid (1) at the DI input of the SRL and is reflected on the X/Y output after a delay of length TREG after Clock Event 2*. * Note: Since the address 0 is still specified at Clock Event 2, the data on the DI input is reflected at the D output, because it is written to Register 0. Clock Event 3: Shift_In / Addressable (Asynchronous) READ All READ operations are asynchronous. If the address is changed (between clock events), the contents of the register at that address are reflected at the addressable output (X/Y outputs) after a delay of length TILO (propagation delay through a LUT). * At time TSRLDS before Clock Event 3 the Data becomes valid (1) at the DI input of the SRL, and is reflected on the X/Y output TREG time after Clock Event 3. * Notice that the address is changed (from 0 to 2) some time after Clock Event 3. The value stored in Register 2 at this time is a 0 (in this example, this was the first data shifted in), and it is reflected on the X/Y output after a delay of length TILO. Clock Event 16: MSB (Most Significant Bit) Changes * At time TREGXB after Clock Event 16, the first bit shifted into the SRL becomes valid (logical 0 in this case) on the XB output of the slice via the MC15 output of the LUT (SRL). Block SelectRAM Timing Model Introduction This section describes the timing parameters associated with the block SelectRAM (illustrated in Figure 1-11) in Virtex-II Pro FPGA devices. This section is intended to be used with the section on switching characteristics in the Virtex-II Pro Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the switching characteristics section in the Virtex-II Pro Data Sheet. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 135 R Chapter 1: Timing Models DI DIP ADDR WE EN SSR DO DOP CLK DS031_10_102000 Figure 1-11: Block SelectRAM Block Diagram Timing Parameters Parameter Function Control Signal Description Setup and Hold Relative to Clock (CLK) TBxCK = Setup time (before clock edge) TBCKx = Hold time (after clock edge) TBACK/TBCKA Address inputs ADDR The following descriptions are for setup times only. Time before the clock that address signals must be stable at the ADDR inputs of the block RAM. TBDCK/TBCKD Data inputs DI Time before the clock that data must be stable at the DI inputs of the block RAM. TBECK/TBCKE Enable EN Time before the clock that the enable signal must be stable at the EN input of the block RAM. TBRCK/TBCKR Synchronous Set/Reset SSR Time before the clock that the synchronous set/reset signal must be stable at the SSR input of the block RAM. TBWCK/TBCKW Write Enable WE Time before the clock that the write enable signal must be stable at the WE input of the block RAM. Clock to Out TBCKO Clock to Output CLK to Time after the clock that the output data is DO stable at the DO outputs of the block RAM. Clock 136 TBPWH Clock CLK Minimum pulse width, high. TBPWL Clock CLK Minimum pulse width, low. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAM Timing Model The timing diagram in Figure 1-12 describes a single-port block RAM in Write-First mode. The timing for Read-First and No-Change modes are similar (see Design Considerations.) 1 2 3 TBPWH 4 5 TBPWL CLK TBACK 00 TBDCK ADDR DI DDDD TBCKO MEM (00) DO 0F 7E 8F 20 CCCC BBBB AAAA 0000 CCCC* MEM (7E) 0101** TBECK EN TBRCK SSR TBWCK WE Disabled Read Write Read Reset Disabled * Write Mode = "WRITE_FIRST" ** SRVAL = 0101 ug002_c3_002_100300 Figure 1-12: Block SelectRAM Timing Diagram At time 0, the block RAM is disabled; EN (enable) is low. Clock Event 1 READ Operation: During a read operation, the contents of the memory at the address on the ADDR inputs are unchanged. * TBACK before Clock Event 1, address 00 becomes valid at the ADDR inputs of the block RAM. * At time TBECK before Clock Event 1, Enable goes High at the EN input of the block RAM, enabling the memory for the READ operation that follows. * At time TBCKO after Clock Event 1, the contents of the memory at address 00 become stable at the DO pins of the block RAM. Clock Event 2 WRITE Operation: During a write operation, the content of the memory at the location specified by the address on the ADDR inputs is replaced by the value on the DI pins and is immediately reflected on the output latches (in WRITE-FIRST mode); EN (enable) is high. * At time TBACK before Clock Event 2, address 0F becomes valid at the ADDR inputs of the block RAM. * At time TBDCK before Clock Event 2, data CCCC becomes valid at the DI inputs of the block RAM. * At time TBWCK before Clock Event 2, Write Enable becomes valid at the WE following the block RAM. * At time TBCKO after Clock Event 2, data CCCC becomes valid at the DO outputs of the block RAM. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 137 R Chapter 1: Timing Models Clock Event 4 SSR (Synchronous Set/Reset) Operation During an SSR operation, initialization parameter value SRVAL is loaded into the output latches of the block SelectRAM. The SSR operation does NOT change the contents of the memory and is independent of the ADDR and DI inputs. * At time TBRCK before Clock Event 4, the synchronous set/reset signal becomes valid (High) at the SSR input of the block RAM. * At time TBCKO after Clock Event 4, the SRVAL 0101 becomes valid at the DO outputs of the block RAM. Clock Event 5 Disable Operation: De-asserting the enable signal EN disables any write, read or SSR operation. The disable operation does NOT change the contents of the memory or the values of the output latches. * At time TBECK before Clock Event 5, the enable signal becomes valid (Low) at the EN input of the block RAM. * After Clock Event 5, the data on the DO outputs of the block RAM is unchanged. Timing Model Figure 1-13 illustrates the delay paths associated with the implementation of block SelectRAM. This example takes the simplest paths on and off chip (these paths can vary greatly depending on the design). This timing model demonstrates how and where the block SelectRAM timing parameters are used. FPGA Block SelectRAM Data Address Write Enable Enable Synchronous Set/Reset [TIOPI + NET] + TBDCK [TIOPI + NET] + TBACK [TIOPI + NET*] + TBWCK [TIOPI + NET] + TBECK [TIOPI + NET] + TBRCK DI ADDR WE EN SSR CLK DO TBCKO + [NET + TIOOP] Data [TGI0O + NET] BUFGMUX Clock [TIOPI + NET] ug002_c3_003_121701 Figure 1-13: Block SelectRAM Timing Model NET = Varying interconnect delays TIOPI = Pad to I-output of IOB delay TIOOP = O-input of IOB to pad delay TGI0O = BUFGMUX delay 138 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Embedded Multiplier Timing Model Embedded Multiplier Timing Model Introduction This section explains all timing parameters associated with the use of embedded 18-bit x 18-bit multipliers in Virtex-II Pro FPGAs (see Figure 1-14). The propagation delays through the embedded multiplier differ based on the size of the multiplier function implemented. The longest delay through the multiplier is to the highest order bit output (P35). Therefore, if an 18-bit x 18-bit signed multiplier is implemented, the worst-case delay for this function is the longest delay associated with the embedded multiplier block. If smaller (LSB) multipliers are used, shorter delays can be realized. This section is intended to be used in conjunction with the section on switching characteristics in the Virtex-II Pro Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the Virtex-II Pro Data Sheet. Multiplier Block A[17:0] MULT 18 x 18 P[35:0] B[17:0] DS031_40_100400 Figure 1-14: Embedded 18-bit x 18-bit Multiplier Block Timing Parameters Propagation Delays (All Worst-Case) Table 1-12 lists the different values for the TMULT timing parameter reported by the Timing Analyzer software. These values correspond to the propagation delay through the multiplier to a specific output pin of the multiplier block. Table 1-12: Multiplier Switching Characteristics Description Symbol Propagation Delay to Output Pin Input to Pin35 TMULT Input to Pin34 TMULT Input to Pin33 TMULT Input to Pin32 TMULT Input to Pin31 TMULT Input to Pin30 TMULT Input to Pin29 TMULT Input to Pin28 TMULT Input to Pin27 TMULT Input to Pin26 TMULT Input to Pin25 TMULT Input to Pin24 TMULT Input to Pin23 TMULT UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 139 R Chapter 1: Timing Models Table 1-12: Multiplier Switching Characteristics (Continued) Description Symbol Input to Pin22 TMULT Input to Pin21 TMULT Input to Pin20 TMULT Input to Pin19 TMULT Input to Pin18 TMULT Input to Pin17 TMULT Input to Pin16 TMULT Input to Pin15 TMULT Input to Pin14 TMULT Input to Pin13 TMULT Input to Pin12 TMULT Input to Pin11 TMULT Input to Pin10 TMULT Input to Pin9 TMULT Input to Pin8 TMULT Input to Pin7 TMULT Input to Pin6 TMULT Input to Pin5 TMULT Input to Pin4 TMULT Input to Pin3 TMULT Input to Pin2 TMULT Input to Pin1 TMULT Input to Pin0 TMULT The shortest delay is to pin 0 and the longest delay to pin 35. Notice that the delay-to-pin ratio is essentially linear (see Figure 1-15). This implies that smaller multiply functions are faster than larger ones. This is true as long as the LSB inputs are used. Pin 35 Pin 0 Delay UG002_C3_023_092500 Figure 1-15: Pin-to-Delay Ratio Curve 140 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IOB Timing Model Figure 1-16 illustrates the result (outputs) of a 4-bit x 4-bit unsigned multiply implemented in an embedded multiplier block. Time 0 input [3..0] 1111 input [3..0] 1111 TMULT (P0) P0 X 1 TMULT (P1) P1 X 0 TMULT (P2) P2 0 X TMULT (P3) P3 0 X TMULT (P4) P4 0 X TMULT (P5) P5 1 X TMULT (P6) P6 1 X TMULT (P7) P7 1 X UG002_C3_024_101300 Figure 1-16: Embedded Multiplier Block Timing Diagram At time 0 the two 4-bit numbers to be multiplied become valid at the A[0..3], B[0..3] inputs to the embedded multiplier. The result appears on the output pins P[0..7] in a staggered fashion. First, P0 becomes valid at time TMULT(P0), followed by each subsequent output pin, until P7 becomes valid at time TMULT (P7). In this case, the delay for this multiply function should correspond to that of Pin 7. In other words, the result is not valid until all output pins become valid. IOB Timing Model Introduction This section describes all timing parameters associated with the Virtex-II Pro IOB. The section consists of three parts: * * IOB Input Timing Model and Parameters IOB Output Timing Model and Parameters UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 141 R Chapter 1: Timing Models * IOB 3-State Timing Model and Parameters This section is intended to be used in conjunction with the section on switching characteristics in the Virtex-II Pro Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the Virtex-II Pro Data Sheet. A Note on I/O Standard Adjustments: The "IOB Input and Output Switching Characteristics Standard Adjustments" tables in the switching characteristics section of the Virtex-II Pro Data Sheet are delay adders (+/-) to be added to all timing parameter values associated with the IOB and the Global Clock (see Pin-to-Pin Timing Model, page 151), if an I/O standard other than LVTTL is used. All values specified in the Virtex-II Pro Data Sheet for the parameters covered in this section are specified for LVTTL. If another I/O standard is used, these delays change. However, there are several exceptions. The following parameters associated with the pad going to high-impedance (3-State buffer OFF) should NOT be adjusted: * TIOTHZ * TIOTLPHZ * TGTS * TIOCKHZ * TIOSRHZ IOB Input Timing Model and Parameters Figure 1-17 illustrates IOB inputs. PAD I FF LATCH D1 Q1 IQ1 CE ICLK1 SR REV ICE FF LATCH D2 Q2 IQ2 CE ICLK2 SR REV SR REV UG002_C3_004_101300 Figure 1-17: Virtex-II Pro IOB Input Diagram 142 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IOB Timing Model Timing Parameters Parameter Function Control Signal Description Propagation Delays TIOPI Propagation delay from the pad to I output of the IOB with no delay adder. TIOPID Propagation delay from the pad to I output of the IOB with the delay adder. TIOPLI Propagation delay from the pad to IQ output of the IOB via transparent latch with no delay adder. TIOPLID Propagation delay from the pad to IQ output of the IOB via transparent latch with the delay adder. Setup and Hold With Respect to Clock at IOB Input Register TxxCK = Setup time (before clock edge) TxxCKxx = Hold time (after clock edge) The following descriptions are for setup times only. TIOPICK/TIOICKP ID input with NO delay Time before the clock that the input signal from the pad must be stable at the ID input of the IOB Input Register, with no delay. TIOPICKD/TIOICKPD ID input with delay Time before the clock that the input signal from the pad must be stable at the ID input of the IOB Input Register, with delay. TIOICECK/TIOCKICE ICE input TIOSRCKI SR input (IFF, synchronous) Time before the clock that the Clock Enable signal must be stable at the ICE input of the IOB Input Register. Time before the clock that the Set/Reset signal must be stable at the SR input of the IOB Input Register. Clock to Out Clock (CLK) to (IQ) output Time after the clock that the output data is stable at the IQ output of the IOB Input Register. TIOSRIQ SR Input to IQ (asynchronous) Time after the Set/Reset signal of the IOB is toggled that the output of the IOB input register (IQ) reflects the signal. TGSRQ GSR to output IQ Time after the Global Set/Reset is toggled that the output of the IOB input register (IQ) reflects the set or reset. TIOCKIQ Set/Reset Delays UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 143 R Chapter 1: Timing Models Figure 1-18 illustrates IOB input register timing. 1 2 3 4 5 CLK TIOPICK I TIOICECK ICE TIOSRCKI SR (reset) TIOCKIQ TIOCKIQ IQ UG002_c3_005_112700 Figure 1-18: IOB Input Register Timing Diagram Clock Events * At time TIOICECK before Clock Event 1, the input clock enable signal becomes valid-high at the ICE input of the input register, enabling the input register for incoming data. * At time TIOPICK before Clock Event 1, the input signal becomes valid-high at the I input of the input register and is reflected on the IQ output of the input register at time TIOCKIQ after Clock Event 1. * At time TIOSRCKI before Clock Event 4 the SR signal (configured as synchronous reset in this case) becomes valid-high resetting the input register and reflected at the IQ output of the IOB at time TIOCKIQ after Clock Event 4. Figure 1-19 illustrates IOB DDR input register timing. 1 2 3 4 5 6 7 8 9 10 11 ICLK1 ICLK2 TIOPICK I TIOPICK TIOICECK ICE TIOSRCK SR (reset) TIOCKIQ IQ1 TIOCKIQ TIOCKIQ TIOCKIQ IQ2 UG002_c3_006_112700 Figure 1-19: IOB DDR Input Register Timing Diagram 144 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IOB Timing Model Clock Events * At time TIOICECK before Clock Event 1 the input clock enable signal becomes validhigh at the ICE input of both of the DDR input registers, enabling them for incoming data. Since the ICE and I signals are common to both DDR registers, care must be taken to toggle these signals between the rising edges of ICLK1 and ICLK2 as well as meeting the register setup-time relative to both clocks. * At time TIOPICK before Clock Event 1 (rising edge of ICLK1) the input signal becomes valid-high at the I input of both registers and is reflected on the IQ1 output of inputregister 1 at time TIOCKIQ after Clock Event 1. * At time TIOPICK before Clock Event 2 (rising edge of ICLK2) the input signal becomes valid-low at the I input of both registers and is reflected on the IQ2 output of inputregister 2 at time TIOCKIQ after Clock Event 2 (no change in this case). * At time TIOSRCKI before Clock Event 9 the SR signal (configured as synchronous reset in this case) becomes valid-high resetting input-register 1 (IQ1) at time TIOCKIQ after Clock Event 9, and input-register 2 (IQ2) at time TIOCKIQ after Clock Event 10. IOB Output Timing Model and Parameters Figure 1-20 illustrates IOB outputs. O1 FF LATCH Q1 D1 OCE Attribute INIT1 INIT0 SRHIGH SRLOW CE CK1 SR REV OTCLK1 SR Shared by all registers REV FF1 DDR MUX FF2 3-State Control OQ PAD FF LATCH D2 Q2 CE CK2 SR REV OTCLK2 Attribute INIT1 INIT0 SRHIGH SRLOW Reset Type SYNC ASYNC O2 UG002_C3_007_101300 Figure 1-20: Virtex-II Pro IOB Output Diagram Timing Parameters Parameter Function Control Signal Description Propagation Delays TIOOP Propagation delay from the O input of the IOB to the pad. TIOOLP Propagation delay from the O input of the IOB to the pad via transparent latch. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 145 R Chapter 1: Timing Models Parameter Control Signal Function Description Setup and Hold With Respect to Clock at IOB Output Register TxxCK = Setup time (before clock edge) TxxCKxx = Hold time (after clock edge) The following descriptions are for setup times only. TIOOCK/TIOCKO O input Time before the clock that data must be stable at the O input of the IOB Output Register. TIOOCECK/TIOCKOCE OCE input Time before the clock that the Clock Enable signal must be stable at the OCE input of the IOB Output Register. TIOSRCKO/TIOCKOSR SR input (OFF) Time before the clock that the Set/Reset signal must be stable at the SR input of the IOB Output Register. Clock to Out TIOCKP Clock (CLK) to pad Time after the clock that the output data is stable at the pad. TIOSRP SR Input to pad (asynchronous) Time after the Set/Reset input of the IOB is toggled that the pad reflects the set or reset. TIOGSRQ GSR to pad Time after the Global Set/Reset is toggled that the pad reflects the set or reset. Set/Reset Delays Figure 1-21 illustrates IOB output register timing. 1 2 3 4 5 CLK TIOOCK O TIOOCECK OCE TIOSRCKO SR (reset) TIOCKP PAD UG002_C3_008_112700 Figure 1-21: IOB Output Register Timing Diagram Clock Events 146 * At time TIOOCECK before Clock Event 1, the output clock enable signal becomes validhigh at the OCE input of the output register, enabling the output register for incoming data. * At time TIOOCK before Clock Event 1, the output signal becomes valid-high at the O input of the output register and is reflected on the pad at time TIOCKP after Clock Event 1. * At time TIOSRCKO before Clock Event 4, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting the output register and reflected on www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IOB Timing Model the pad at time TIOCKP after Clock Event 4. Figure 1-22 illustrates IOB DDR output register timing. 1 2 3 4 5 6 7 8 9 10 11 OTCLK1 OTCLK2 TIOOCK O1 TIOOCK O2 TIOOCECK OCE TIOSRCKO SR TIOCKP TIOCKP PAD UG002_c3_009_112700 Figure 1-22: IOB DDR Output Register Timing Diagram Clock Events * At time TIOOCECK before Clock Event 1, the output clock enable signal becomes validhigh at the OCE input of both of the DDR output registers, enabling them for incoming data. Since the OCE signal is common to both DDR registers, care must be taken to toggle this signal between the rising edges of OTCLK1 and OTCLK2 as well as meeting the register setup-time relative to both clocks. * At time TIOOCK before Clock Event 1 (rising edge of OTCLK1), the output signal O1 becomes valid-high at the O1 input of output register 1 and is reflected on the pad at time TIOCKP after Clock Event 1. * At time TIOOCK before Clock Event 2 (rising edge of OTCLK2), the output signal O2 becomes valid-high at the O2 input of output register 2 and is reflected on the pad at time TIOCKP after Clock Event 2 (no change on the pad in this case). * At time TIOSRCKO before Clock Event 9, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting output-register 1 (reflected on the pad at time TIOCKP after Clock Event 9) (no change in this case) and output-register 2 (reflected on the pad at time TIOCKP after Clock Event 10) (no change in this case). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 147 R Chapter 1: Timing Models IOB 3-State Timing Model and Parameters Figure 1-23 illustrates IOB 3-state timing T1 FF LATCH TCE OTCLK1 Q1 D1 Attribute INIT1 INIT0 SRHIGH SRLOW CE CK1 SR REV SR Shared by all registers REV FF1 DDR MUX FF2 TQ PAD FF LATCH D2 Q2 CE OTCLK2 CK2 SR REV Attribute INIT1 INIT0 SRHIGH SRLOW Reset Type SYNC ASYNC T2 UG002_C3_010_120600 Figure 1-23: Virtex-II Pro IOB 3-State Diagram Timing Parameters Parameter Function Control Signal Description Propagation Delays TIOTHZ Time after T input of the IOB is toggled that the pad goes to high-impedance. TIOTON Time after the T input of the IOB is toggled that the pad goes from high-impedance to valid data. TIOTLPHZ Time after the T input of the IOB via transparent latch is toggled that the pad goes to highimpedance. TIOTLPON Time after the T input of the IOB via transparent latch is toggled that the pad goes from high-impedance to valid data. TGTS Time after the Global 3-state signal is asserted that the pad goes to high-impedance. Setup and Hold With Respect to Clock at IOB 3-State Register TxxCK = Setup time (before clock edge) TxxCKxx = Hold time (after clock edge) TIOTCK/TIOCKT 148 T input The following descriptions are for setup times only. Time before the clock that the signal must be stable at the T input of the IOB 3-state Register. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IOB Timing Model Control Signal Parameter Function TIOTCECK/TIOCKTCE TCE input TIOSRCKT/TIOCKTSR SR input (TFF) Description Time before the clock that the clock enable signal must be stable at the TCE input of the IOB 3-state Register. Time before the clock that the set/reset signal. Clock to Out TIOCKHZ Clock (CLK) to pad High-Z TIOCKON Clock (CLK) to valid data on pad Time after clock that the pad goes to highimpedance. Time after clock that the pad goes from highimpedance to valid data. Set/Reset Delays TIOSRHZ SR Input to pad High-Z (asynchronous) Time after the SR signal is toggled that the pad goes to high-impedance. TIOSRON SR Input to valid data on pad (asynchronous) Time after the SR signal is toggled that the pad goes from high-impedance to valid data. Figure 1-24 illustrates IOB 3-state register timing. 1 2 3 4 5 CLK TIOTCK T TIOTCECK TCE TIOSRCKT SR TIOCKHZ PAD TIOCKON DATA Z DATA Z DATA UG002_c3_011_101300 Figure 1-24: IOB 3-State Register Timing Diagram Clock Events * At time TIOTCECK before Clock Event 1, the 3-state clock enable signal becomes validhigh at the TCE input of the 3-state register, enabling the 3-state register for incoming data. * At time TIOTCK before Clock Event 1 the 3-state signal becomes valid-high at the T input of the 3-state register, returning the pad to high-impedance at time TIOCKHZ after Clock Event 1. * At time TIOSRCKT before Clock Event 2, the SR signal (configured as synchronous reset in this case) becomes valid-high, resetting the 3-state register and returning the pad to valid data at time TIOSRON after Clock Event 2. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 149 R Chapter 1: Timing Models Figure 1-25 illustrates IOB DDR 3-state register timing. 1 2 3 4 5 6 7 8 9 10 11 OTCLK1 OTCLK2 TIOTCK T1 TIOTCK T2 TIOTCECK TCE TIOSRCKT SR TIOSRON TIOCKON TIOCKHZ PAD DATA Z DATA Z DATA Z UG002_c3_012_101300 Figure 1-25: IOB DDR 3-State Register Timing Diagram Clock Events 150 * At time TIOTCECK before Clock Event 1, the 3-state clock enable signal becomes validhigh at the TCE input of both of the DDR 3-state registers, enabling them for incoming data. Since the TCE signal is common to both DDR registers, care must be taken to toggle this signal between the rising edges of OTCLK1 and OTCLK2 as well as meeting the register setup-time relative to both clocks. * At time TIOTCK before Clock Event 2 (rising edge of OTCLK2), the 3-state signal T2 becomes valid-high at the T2 input of 3-state register 2, switching the pad to highimpedance at time TIOCKHZ after Clock Event 2. * At time TIOTCK before Clock Event 3 (rising edge of OTCLK1), the 3-state signal T1 becomes valid-high at the T1 input of 3-state register 1, keeping the pad at highimpedance for another half clock cycle (half the period of OTCLK1 or 2). * At time TIOTCK before Clock Event 4 (rising edge of OTCLK2), the 3-state signal T2 becomes valid-low at the T2 input of 3-state register 2, switching the pad to valid data at time TIOCKON after Clock Event 4. This is repeated for 3-state signal T1 at the following clock event (5) maintaining valid data on the pad until Clock Event 8. * At time TIOTCK before Clock Event 8 (rising edge of OTCLK2), the 3-state signal T2 becomes valid-high at the T2 input of 3-state register 2, switching the pad to highimpedance at time TIOCKHZ after Clock Event 8. * At time TIOSRCKT before Clock Event 9 (rising edge of OTCLK1), the SR signal (configured as synchronous reset in this case) becomes valid-high at the SR input of 3-state Register 1, returning the pad to valid data at time TIOSRON after Clock Event 9. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pin-to-Pin Timing Model Pin-to-Pin Timing Model Introduction This section explains the delays and timing parameters associated with the use of the Global Clock network and the DCM. These delays are true pin-to-pin delays relative to the Global Clock pin and an output or input pin with or without the DCM. This section consists of two parts: * * Global Clock Input to Output Global Clock Setup and Hold The former describes the delay from the Global Clock pin (with and without the DCM) to an output pin via an Output flip-flop. The latter describes the set-up time for an Input flipflop from an input pin relative to the Global Clock pin (with and without the DCM). The values reported in the switching characteristics section of the Virtex-II Pro Data Sheet are for LVTTL I/O standards. For different I/O standards, adjust these values with those shown in the "IOB Switching Characteristics Standard Adjustments" tables. This section is intended to be used in conjunction with the section on switching characteristics in the Virtex-II Pro Data Sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the Virtex-II Pro Data Sheet. Global Clock Input to Output Figure 1-26 illustrates the paths associated with the timing parameters defined in this section. Note that they differ only in their use of the DCM. Global Clock Pin IOB Output Register BUFGMUX Data D Output Pin Q IOB Output Register Output Pin Q D Data DCM BUFGMUX Global Clock Pin UG002_C3_013_101300 Figure 1-26: Global Clock Input to Output Model UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 151 R Chapter 1: Timing Models Timing Parameters Parameter Description TICKOFDLL Time after the Global Clock (pin), using the DCM, that the output data from an IOB Output flip-flop is stable at the output pin. TICKOF Time after the Global Clock (pin), without the DCM, that the output data from an IOB Output flip-flop is stable at the output pin. The waveforms depicted in Figure 1-27 demonstrate the relation of the Global Clock pin, the output data, and the use of the timing parameters. Global Clock Pin (No DCM) D-input of IOB Output Register TICKOF Output Pin Global Clock Pin (With DCM) D-input of IOB Output Register TICKOFDLL Output Pin UG002_C3_015_101300 Figure 1-27: Global Clock Input to Output Timing Diagram 152 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pin-to-Pin Timing Model Global Clock Setup and Hold Figure 1-28 illustrates the paths associated with the timing parameters defined in this section. Note, they differ only in their use of the DCM. Global Clock Pin IOB BUFGMUX Q Input Pin D IOB Input Pin D Q DCM BUFGMUX Global Clock Pin UG002_C3_014_101300 Figure 1-28: Global Clock Setup and Hold Model Timing Parameters Setup and Hold for Input Registers Relative to the Global Clock (pin): * TPSDLL / TPHDLL - Time before the Global Clock (pin), with DCM, that the input signal must be stable at the D-input of the IOB input register. * TPSFD / TPHFD - Time before the Global Clock (pin), without DCM, that the input signal must be stable at the D-input of the IOB input register. Note: TPSFD = Setup time (before clock edge) and TPHFD = Hold time (after clock edge). The previous descriptions are for setup times only. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 153 R Chapter 1: Timing Models The waveforms depicted in Figure 1-29 demonstrate the relation of the Global Clock pin, the input data, and the use of the timing parameters. Global Clock Pin (No DCM) Input Pin TPHFD TPSFD Global Clock Pin (With DCM) Input Pin TPHDLL TPSDLL UG002_C3_016_101300 Figure 1-29: Global Clock Setup and Hold Timing Diagram Digital Clock Manager Timing Model This section describes the timing parameters associated with the Digital Clock Manager (DCM), which are reported in the Virtex-II Pro Data Sheet. Note that these parameters are not used by the Timing Analyzer software in the production of timing reports; they are all measured values and are fully characterized in silicon. For specific timing parameter values, refer to the Virtex-II Pro Data Sheet. This section discusses the following: * Operating Frequency Ranges: The minimum and maximum frequencies supported by the DCM for all clock inputs and outputs. * Input Clock Tolerances: Input clock period (pulse widths), jitter, and drift requirements for proper function of the DCM for all clock inputs. * Output Clock Precision: Output clock period jitter, phase offsets, and duty cycle for all clock outputs of the DCM (worst case). * Miscellaneous Timing Parameters: DCM lock times, Tap delay and shifting range. For a detailed description of input clock tolerance, jitter, and phase offset see the waveforms at the end of this section. 154 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Manager Timing Model Operating Frequency Ranges Figure 1-30 illustrates the DCM functional block and corresponding timing parameters for all clock inputs and outputs. DCM CLK0 - CLKOUT_FREQ_1X_(LF & HF) CLK90 - CLKOUT_FREQ_1X_LF CLK180 - CLKOUT_FREQ_1X_(LF & HF) CLK270 - CLKOUT_FREQ_1X_LF CLK2X - CLKOUT_FREQ_2X_LF CLK2X180 - CLKOUT_FREQ_2X_LF CLKDV - CLKOUT_FREQ_DV_(LF & HF) CLKIN (CLKIN_FREQ_(DLL & FX)_(LF & HF)) CLKFB CLKFX - CLKOUT_FREQ_FX_(LF & HF) CLKFX180 - CLKOUT_FREQ_FX_(LF & HF) PSINCDEC PSEN PSCLK_FREQ_(LF & HF) PSDONE DSSEN LOCKED STATUS RST ug002_c1_004_112800 Figure 1-30: DCM Functional Block: Operating Frequency Ranges Timing Parameters Parameter Description Low Frequency Mode CLKOUT_FREQ_1X_LF The minimum and maximum frequency for the CLK0, CLK90, CLK180, CLK270 outputs of the DCM in lowfrequency mode. CLKOUT_FREQ_2X_LF The minimum and maximum frequency for the CLK2X and CLK2X180 outputs of the DCM in low-frequency mode. CLKOUT_FREQ_DV_LF The minimum and maximum frequency for the CLKDV output of the DCM in low-frequency mode. CLKOUT_FREQ_FX_LF The minimum and maximum frequency for the CLKFX and CLKFX180 outputs of the DCM in low-frequency mode. CLKIN_FREQ_DLL_LF1 The minimum and maximum frequency for the CLKIN input to the DCM in low-frequency mode when using the delay-locked loop (DLL) outputs. CLKIN_FREQ_FX_LF2 The minimum and maximum frequency for the CLKIN input to the DCM in low-frequency mode when using the FX outputs. PSCLK_FREQ_LF The minimum and maximum frequency for the PSCLK input to the DCM in low-frequency mode. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 155 R Chapter 1: Timing Models Parameter Description High Frequency Mode CLKOUT_FREQ_1X_HF The minimum and maximum frequency for the CLK0, CLK180 outputs of the DCM in high-frequency mode. CLKOUT_FREQ_DV_HF The minimum and maximum frequency for the CLKDV output of the DCM in high-frequency mode. CLKOUT_FREQ_FX_HF The minimum and maximum frequency for the CLKFX and CLKFX180 outputs of the DCM in high-frequency mode. CLKIN_FREQ_DLL_HF The minimum and maximum frequency for the CLKIN input to the DCM in high-frequency mode when using the DLL outputs. CLKIN_FREQ_FX_HF The minimum and maximum frequency for the CLKIN input to the DCM in high-frequency mode when using the FX outputs. PSCLK_FREQ_HF The minimum and maximum frequency for the PSCLK input to the DCM in high-frequency mode. Notes: 1. Delay-locked loop (DLL) outputs include: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. FX outputs include: CLKFX and CLKFX180 Input Clock Tolerances Timing Parameters Parameter Description PSCLK_PULSE1 The minimum pulse width (HIGH and LOW) that the PSCLK input to the DCM can have over a range of frequencies. CLKIN_PULSE The minimum pulse width (HIGH and LOW) that the CLKIN input to the DCM can have over a range of frequencies. Also applies to PSCLK. CLKFB_DELAY_VAR_EXT The maximum allowed variation in delay (across environmental changes) of the feedback clock path when routed externally for board-level de-skew. Low Frequency Mode 156 CLKIN_CYC_JITT_DLL_LF The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the DLL outputs in low-frequency mode. CLKIN_CYC_JITT_FX_LF The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the FX outputs in lowfrequency mode. CLKIN_PER_JITT_DLL_LF The maximum period jitter the CLKIN input to the DCM can have when using the DLL outputs in lowfrequency mode. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Manager Timing Model Parameter Description CLKIN_PER_JITT_FX_LF The maximum period jitter the CLKIN input to the DCM can have when using the FX outputs in lowfrequency mode. High Frequency Mode CLKIN_CYC_JITT_DLL_HF The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the DLL outputs in high-frequency mode. CLKIN_CYC_JITT_FX_HF The maximum cycle-to-cycle jitter the CLKIN input to the DCM can have when using the FX outputs in highfrequency mode. CLKIN_PER_JITT_DLL_HF The maximum period jitter the CLKIN input to the DCM can have when using the DLL outputs in highfrequency mode. CLKIN_PER_JITT_FX_HF The maximum period jitter the CLKIN input to the DCM can have when using the FX outputs in highfrequency mode. Notes: 1. The frequencies applicable to CLKIN_PULSE range from 1 to >400 MHz. These frequencies also apply to PSCLK_PULSE. Since PSCLK can be less than 1 MHz, the pulse width under this condition is specified for PSCLK only. Output Clock Precision Timing Parameters Parameter Description CLKOUT_PER_JITT_0 The maximum period jitter of the CLK0 output clock from the DCM (worst case). CLKOUT_PER_JITT_90 The maximum period jitter of the CLK90 output clock from the DCM (worst case). CLKOUT_PER_JITT_180 The maximum period jitter of the CLK180 output clock from the DCM (worst case). CLKOUT_PER_JITT_270 The maximum period jitter of the CLK270 output clock from the DCM (worst case). CLKOUT_PER_JITT_2X The maximum period jitter of the CLK2X and CLK2X180 output clocks from the DCM (worst case). CLKOUT_PER_JITT_DV1 The maximum period jitter of the CLKDV (integer division) output clock from the DCM (worst case). CLKOUT_PER_JITT_DV2 The maximum period jitter of the CLKDV (non-integer division) output clock from the DCM (worst case). CLKOUT_PER_JITT_FX The maximum period jitter of the FX output clocks from the DCM (worst case). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 157 R Chapter 1: Timing Models Parameter Description CLKIN_CLKFB_PHASE Maximum phase offset between the CLKIN and CLKFB inputs to the DCM. CLKOUT_PHASE Maximum phase offset between any DCM clock outputs. CLKOUT_DUTY_CYCLE_DLL The duty-cycle precision for all DLL outputs. CLKOUT_DUTY_CYCLE_FX The duty-cycle precision for the FX outputs. Miscellaneous DCM Timing Parameters Table 1-13: Miscellaneous DCM Timing Parameters Parameter Description LOCK_DLL Time required for DCM to lock over a range of clock frequencies when using the DLL outputs. LOCK_FX Time required for DCM to lock when using the FX outputs. LOCK_DLL_FINE_SHIFT Additional lock time when performing fine phase shifting. FINE_SHIFT_RANGE Absolute range for fine phase shifting. DCM_TAP Resolution of delay line. The waveforms in Figure 1-31 demonstrate the relationship between clock tolerance, jitter, and phase. Period Tolerance: the allowed input clock period change in nanoseconds. TCLKIN +_ Input Clock Jitter TCLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Phase Offset and Maximum Phase Difference Ideal Period Actual Period + Jitter +/- Jitter + Maximum Phase Difference + Phase Offset ds022_24_112800 Figure 1-31: DCM Jitter, Phase, and Tolerance Timing Waveforms Output jitter is period jitter measured on the DLL output clocks, excluding input clock jitter. Phase offset between CLKIN and CLKFB is the worst-case fixed time difference between rising edges of CLKIN and CLKFB, excluding output jitter and input clock jitter. 158 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Manager Timing Model Phase offset between clock outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding output jitter and input clock jitter. Maximum phase difference between CLKIN an CLKFB is the sum of output jitter and phase offset between CLKIN and CLKFB, or the greatest difference between CLKIN and CLKFB rising edges due to DLL alone (excluding input clock jitter). Maximum phase difference between clock outputs on the DLL is the sum of output jitter and phase offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 159 R 160 Chapter 1: Timing Models www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Chapter 2 Design Considerations Summary This chapter covers the following topics: * * * * * * * * * * * * * * * * * Rocket I/O Transceiver Processor Block Global Clock Networks Digital Clock Managers (DCMs) Block SelectRAMTM Memory Distributed SelectRAM Memory Look-Up Tables as Shift Registers (SRLUTs) Large Multiplexers Sum of Products (SOP) Logic Embedded Multipliers Single-Ended SelectI/O Resources Digitally Controlled Impedance (DCI) Double-Data-Rate (DDR) I/O LVDS I/O Bitstream Encryption Platform Generator CORE Generator System Introduction This chapter describes how to take advantage of the many special features of the Virtex-II Pro architecture to achieve maximum density and performance. In many cases, the functions described can be automatically generated using the Xilinx CORE GeneratorTM tool. This is noted throughout the chapter, in the following sections specifically: * * * * * Block SelectRAMTM Memory Distributed SelectRAM Memory Look-Up Tables as Shift Registers (SRLUTs) Large Multiplexers Embedded Multipliers UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 161 R Chapter 2: Design Considerations Rocket I/O Transceiver Introduction Virtex-II Pro devices provide up to sixteen multi-gigabit transceivers capable of various high-speed serial standards such as Gigabit Ethernet, FiberChannel, Infiniband, and XAUI. In addition, the channel-bonding feature aggregates multiple channels allowing for even higher data transfer rate. The following sections summarize the Rocket I/O primitive ports and attributes, and give a simple usage example. For more information on Rocket I/O features, design examples, power considerations, and board layout suggestions, refer to the Rocket I/O User Guide or www.xilinx.com/virtex2pro. List of Available Ports The Rocket I/O transceiver primitives contain 50 ports, with the exception of the 46-port GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP, TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN). Table 2-1 contains the port descriptions of all primitives. Table 2-1: GT_CUSTOM (1), GT_AURORA, GT_FIBRE_CHAN (2), GT_ETHERNET (2), GT_INFINIBAND, and GT_XAUI Primitive Ports I/O Port Size (3) CHBONDDONE O 1 Indicates a receiver has successfully completed channel bonding when asserted High. CHBONDI I 4 The channel bonding control that is used only by "slaves" which is driven by a transceiver's CHBONDO port. CHBONDO O 4 Channel bonding control that passes channel bonding and clock correction control to other transceivers. CONFIGENABLE I 1 Reconfiguration enable input (unused) CONFIGIN I 1 Data input for reconfiguring transceiver (unused) CONFIGOUT O 1 Data output for configuration readback (unused) ENCHANSYNC I 1 Comes from the core to the transceiver and enables the transceiver to perform channel bonding ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus-comma. High realigns serial bitstream byte boundary when minus-comma is detected. ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus-comma. High realigns serial bitstream byte boundary when plus-comma is detected. LOOPBACK I 2 Selects the two loopback test modes. Bit 1 is for serial loopback and bit 0 is for internal parallel loopback. POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the transceiver when asserted High. This decreases the power consumption while the transceiver is shut down. Port 162 Definition www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Table 2-1: GT_CUSTOM (1), GT_AURORA, GT_FIBRE_CHAN (2), GT_ETHERNET (2), GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) I/O Port Size (3) REFCLK I 1 High-quality reference clock driving transmission (reading TX FIFO, and multiplied for parallel/serial conversion) and clock recovery. REFCLK frequency is accurate to 100 ppm. This clock originates off the device, is routed through fabric interconnect, and is selected by the REFCLKSEL. REFCLK2 I 1 An alternative to REFCLK. Can be selected by the REFCLKSEL. REFCLKSEL I 1 Selects the reference clock to use REFCLK or REFCLK2. Deasserted is REFCLK. Asserted is REFCLK2. RXBUFSTATUS O 2 Receiver elastic buffer status. Bit 1 indicates if an overflow/underflow error has occurred when asserted High. Bit 0 indicates if the buffer is at least half-full when asserted High. RXCHARISCOMMA O 1, 2, 4 Similar to RXCHARISK except that the data is a comma. RXCHARISK O 1, 2, 4 If 8B/10B decoding is enabled, it indicates that the received data is a "K" character when asserted High. Included in Byte-mapping. If 8B/10B encoding bypassed, it becomes the 10th bit of the 10-bit encoded data. RXCHECKINGCRC O 1 CRC status for the receiver. Asserts High to indicate that the receiver has recognized the end of a data packet. Only meaningful if RX_CRC_USE = TRUE. RXCLKCORCNT O 3 Status that denotes occurrence of clock correction or channel bonding. This status is synchronized on the incoming RXDATA. See Rocket I/O User Guide. RXCOMMADET O 1 Signals that a comma has been detected in the data stream. RXCRCERR O 1 Indicates if the CRC code is incorrect when asserted High. Only meaningful if RX_CRC_USE = TRUE. RXDATA O 8,16,32 Up to four bytes of decoded (8B/10B encoding) or encoded (8B/10B bypassed) receive data. RXDISPERR O 1, 2, 4 Port UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Definition If 8B/10B encoding is enabled it indicates whether a disparity error has occurred on the serial line. Included in Byte-mapping scheme. www.xilinx.com 1-800-255-7778 163 R Chapter 2: Design Considerations Table 2-1: GT_CUSTOM (1), GT_AURORA, GT_FIBRE_CHAN (2), GT_ETHERNET (2), GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) Port RXLOSSOFSYNC I/O Port Size (3) O 2 Definition Status related to byte-stream synchronization (RX_LOSS_OF_SYNC_FSM) If RX_LOSS_OF_SYNC_FSM = TRUE, this outputs the state of the FSM. Bit 1 signals a loss of sync. Bit 0 indicates a resync state. If RX_LOSS_OF_SYNC_FSM = FALSE, this indicates if received data is invalid (Bit 1) and if the channel bonding sequence is recognized (Bit 0). 164 RXN (4) I 1 RXNOTINTABLE O 1, 2, 4 RXP (4) I 1 Serial differential port (FPGA external) RXPOLARITY I 1 Similar to TXPOLARITY, but for RXN and RXP. When deasserted, assumes regular polarity. When asserted, reverses polarity. RXREALIGN O 1 Signal from the PMA denoting that the byte alignment with the serial data stream changed due to a comma detection. Asserted High when alignment occurs. RXRECCLK O 1 Recovered clock that is divided by 20. RXRESET I 1 Synchronous RX system reset that "recenters" the receive elastic buffer. It also resets 8B/10B decoder, comma detect, channel bonding, clock correction logic, and other internal receive registers. It does not reset the receiver PLL. RXRUNDISP O 1, 2, 4 Signals the running disparity (negative/positive) in the received serial data. If 8B/10B encoding bypassed, it becomes the 9th bit of the 10-bit encoded data. RXUSRCLK I 1 Clock from a DCM that is used for reading the RX elastic buffer. It also clocks CHBONDI and CHBONDO in and out of the transceiver. Typically, the same as TXUSRCLK. RXUSRCLK2 I 1 Clock output from a DCM that clocks the receiver data and status between the transceiver and the FPGA core. Typically the same as TXUSRCLK2. The relationship between RXUSRCLK and RXUSRCLK2 depends on the width of the RXDATA. TXBUFERR O 1 Provides status of the transmission FIFO. If asserted High, an overflow/underflow has occurred. When this bit becomes set, it can only be reset by asserting TXRESET. Serial differential port (FPGA external) Status of encoded data when the data is not a valid character when asserted High. Applies to the bytemapping scheme. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Table 2-1: GT_CUSTOM (1), GT_AURORA, GT_FIBRE_CHAN (2), GT_ETHERNET (2), GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) I/O Port Size (3) TXBYPASS8B10B I 1, 2, 4 This control signal determines whether the 8B/10B encoding is enabled or bypassed. If the signal is asserted High, the encoding is bypassed. This creates a 10-bit interface to the FPGA core. See the 8B/10B section for more details. TXCHARDISPMODE I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what mode of disparity is to be sent. When 8B/10B is bypassed, this becomes the 10th bit of the 10-bit encoded TXDATA bus for each byte specified by the byte-mapping section. TXCHARDISPVAL I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what type of disparity is to be sent. When 8B/10B is bypassed, this becomes the 9th bit of the 10-bit encoded TXDATA bus for each byte specified by the byte-mapping section. TXCHARISK I 1, 2, 4 If 8B/10B encoding is enabled, this control bus determines if the transmitted data is a "K" character or a Data character. A logic High indicating a K character. TXDATA I 8,16,32 Transmit data that can be 1, 2, or 4 bytes wide, depending on the primitive used. TXDATA [7:0] is always the last byte transmitted. The position of the first byte depends on selected TX data path width. TXFORCECRCERR I 1 Specifies whether to insert error in computed CRC. When TXFORCECRCERR = TRUE, the transmitter corrupts the correctly computed CRC value by XORing with the bits specified in attribute TX_CRC_FORCE_VALUE. This input can be used to test detection of CRC errors at the receiver. TXINHIBIT I 1 If a logic High, the TX differential pairs are forced to be a constant 1/0. TXN = 1, TXP = 0 TXKERR O 1, 2, 4 If 8B/10B encoding is enabled, this signal indicates (asserted High) when the "K" character to be transmitted is not a valid "K" character. Bits correspond to the byte-mapping scheme. TXN (4) O 1 Transmit differential port (FPGA external) TXP (4) O 1 Transmit differential port (FPGA external) TXPOLARITY I 1 Specifies whether or not to invert the final transmitter output. Able to reverse the polarity on the TXN and TXP lines. Deasserted sets regular polarity. Asserted reverses polarity. TXRESET I 1 Synchronous TX system reset that "recenters" the transmit elastic buffer. It also resets 8B/10B encoder and other internal transmission registers. It does not reset the transmission PLL. Port UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Definition www.xilinx.com 1-800-255-7778 165 R Chapter 2: Design Considerations Table 2-1: GT_CUSTOM (1), GT_AURORA, GT_FIBRE_CHAN (2), GT_ETHERNET (2), GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) I/O Port Size (3) TXRUNDISP O 1, 2, 4 TXUSRCLK I 1 Clock output from a DCM that is clocked with the REFCLK (or other reference clock). This clock is used for writing the TX buffer and is frequencylocked to the REFCLK. TXUSRCLK2 I 1 Clock output from a DCM that clocks transmission data and status and reconfiguration data between the transceiver an the FPGA core. The ratio between the TXUSRCLK and TXUSRCLK2 depends on the width of the TXDATA. Port Definition Signals the running disparity after this byte is encoded. Zero equals negative disparity and positive disparity for a one. Notes: 1. The GT_CUSTOM ports are always the maximum port size. 2. GT_FIBRE_CHAN and GT_ETHERNET ports do not have the three CHBOND** or ENCHANSYNC ports. 3. The port sizes change with relation to the primitive selected and also correlate to the byte mapping. 4. External ports only accessible from package pins. Primitive Attributes The primitives also contain attributes set by default to specific values controlling each specific primitive's protocol parameters. Included are channel-bonding settings (for primitives supporting channel bonding), clock correction sequences, and CRC. Table 2-2 shows a brief description of each attribute. Table 2-3 and Table 2-4 have the default values of each primitive. Table 2-2: Rocket I/O Transceiver Attributes Attribute ALIGN_COMMA_MSB Description True/False controls the alignment of detected commas within the transceivers 2-byte wide data path. False: Align commas within a 10-bit alignment range. As a result the comma is aligned to either RXDATA[15:8} byte or RXDATA [7:0] byte in the transceivers internal data path. True: Aligns comma with 20-bit alignment range. As a result aligns on the RXDATA[15:8] byte. NOTE: If protocols (like Gigabit Ethernet) are oriented in byte pairs with commas always in even (first) byte formation, this can be set to True. Otherwise, it should be set to False. CHAN_BOND_LIMIT 166 Integer 1-31 that defines maximum number of bytes a slave receiver can read following a channel bonding sequence and still successfully align to that sequence. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Table 2-2: Rocket I/O Transceiver Attributes (Continued) Attribute CHAN_BOND_MODE Description STRING OFF, MASTER, SLAVE_1_HOP, SLAVE_2_HOPS OFF: No channel bonding involving this transceiver. MASTER: This transceiver is master for channel bonding. Its CHBONDO port directly drives CHBONDI ports on one or more SLAVE_1_HOP transceivers. SLAVE_1_HOP: This transceiver is a slave for channel bonding. SLAVE_1_HOP's CHBONDI is directly driven by a MASTER transceiver CHBONDO port. SLAVE_1_HOP's CHBONDO port can directly drive CHBONDI ports on one or more SLAVE_2_HOPS transceivers. SLAVE_2_HOPS: This transceiver is a slave for channel bonding. SLAVE_2_HOPS CHBONDI is directly driven by a SLAVE_1_HOP CHBONDO port. CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for realignment. It specifies the first elastic buffer read address that all channelbonded transceivers have immediately after channel bonding. CHAN_BOND_WAIT specifies the number of bytes that the master transceiver passes to RXDATA, starting with the channel bonding sequence, before the transceiver executes channel bonding (alignment) across all channel-bonded transceivers. CHAN_BOND_OFFSET specifies the first elastic buffer read address that all channel-bonded transceivers have immediately after channel bonding (alignment), as a positive offset from the beginning of the matched channel bonding sequence in each transceiver. For optimal performance of the elastic buffer, CHAN_BOND_WAIT and CHAN_BOND_OFFSET should be set to the same value (typically 8). CHAN_BOND_ONE_SHOT True/False that controls repeated execution of channel bonding. False: Master transceiver initiates channel bonding whenever possible (whenever channel-bonding sequence is detected in the input) as long as input ENCHANSYNC is High and RXRESET is Low. True: Master transceiver initiates channel bonding only the first time it is possible (channel bonding sequence is detected in input) following negated RXRESET and asserted ENCHANSYNC. After channel-bonding alignment is done, it does not occur again until RXRESET is asserted and negated, or until ENCHANSYNC is negated and reasserted. Slave transceivers should always have CHAN_BOND_ONE_SHOT set to False. CHAN_BOND_SEQ_*_* 11-bit vectors that define the channel bonding sequence. The usage of these vectors also depends on CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE. See Rocket I/O User Guide for format. CHAN_BOND_SEQ_2_USE Controls use of second channel bonding sequence. False: Channel bonding uses only one channel bonding sequence defined by CHAN_BOND_SEQ_1_1..4. True: Channel bonding uses two channel bonding sequences defined by: CHAN_BOND_SEQ_1_1..4 and CHAN_BOND_SEQ_2_1..4 as further constrained by CHAN_BOND_SEQ_LEN. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 167 R Table 2-2: Chapter 2: Design Considerations Rocket I/O Transceiver Attributes (Continued) Attribute Description CHAN_BOND_SEQ_LEN Integer 1-4 defines length in bytes of channel bonding sequence. This defines the length of the sequence the transceiver matches to detect opportunities for channel bonding. CHAN_BOND_WAIT Integer 1-15 that defines the length of wait (in bytes) after seeing channel bonding sequence before executing channel bonding. CLK_COR_INSERT_IDLE_FLAG True/False controls whether RXRUNDISP input status denotes running disparity or inserted-idle flag. False: RXRUNDISP denotes running disparity when RXDATA is decoded data. True: RXRUNDISP is raised for the first byte of each inserted (repeated) clock correction ("Idle") sequence (when RXDATA is decoded data). CLK_COR_KEEP_IDLE True/False controls whether or not the final byte stream must retain at least one clock correction sequence. False: Transceiver can remove all clock correction sequences to further recenter the elastic buffer during clock correction. True: In the final RXDATA stream, the transceiver must leave at least one clock correction sequence per continuous stream of clock correction sequences. CLK_COR_REPEAT_WAIT Integer 0 - 31 controls frequency of repetition of clock correction operations. This attribute specifies the minimum number of RXUSRCLK cycles without clock correction that must occur between successive clock corrections. If this attribute is zero, no limit is placed on how frequently clock correction can occur. CLK_COR_SEQ_*_* 11-bit vectors that define the sequence for clock correction. The attribute used depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE. CLK_COR_SEQ_2_USE True/False Control use of second clock correction sequence. False: Clock correction uses only one clock correction sequence defined by CLK_COR_SEQ_1_1..4. True: Clock correction uses two clock correction sequences defined by: CLK_COR_SEQ_1_1..4 and CLK_COR_SEQ_2_1..4 as further constrained by CLK_COR_SEQ_LEN. CLK_COR_SEQ_LEN Integer that defines the length of the sequence the transceiver matches to detect opportunities for clock correction. It also defines the size of the correction, since the transceiver executes clock correction by repeating or skipping entire clock correction sequences. CLK_CORRECT_USE True/False controls the use of clock correction logic. False: Permanently disable execution of clock correction (rate matching). Clock RXUSRCLK must be frequency-locked with RXRECCLK in this case. True: Enable clock correction (normal mode). COMMA_10B_MASK 168 This 10-bit vector defines the mask that is ANDed with the incoming serial-bit stream before comparison against PCOMMA_10B_VALUE and MCOMMA_10B_VALUE. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Table 2-2: Rocket I/O Transceiver Attributes (Continued) Attribute Description CRC_END_OF_PKT K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7 End-of-packet (EOP) K-character for USER_MODE CRC. Must be one of the 12 legal K-character values. CRC_FORMAT ETHERNET, INFINIBAND, FIBRE_CHAN, USER_MODE CRC algorithm selection. Modifiable only for GT_AURORA_n, GT_XAUI_n, and GT_CUSTOM. USER_MODE allows user definition of start-of-packet and end-of-packet K-characters. CRC_START_OF_PKT K28_0, K28_1, K28_2, K28_3, K28_4, K28_5, K28_6, K28_7, K23_7, K27_7, K29_7, K30_7 Start-of-packet (SOP) K-character for USER_MODE CRC. Must be one of the 12 legal K-character values. DEC_MCOMMA_DETECT True/False controls the raising of per-byte flag RXCHARISCOMMA on minus-comma. DEC_PCOMMA_DETECT True/False controls the raising of per-byte flag RXCHARISCOMMA on plus-comma. DEC_VALID_COMMA_ONLY True/False controls the raising of RXCHARISCOMMA on an invalid comma. False: Raise RXCHARISCOMMA on: 0011111xxx (if DEC_PCOMMA_DETECT is TRUE) and/or on: 1100000xxx (if DEC_MCOMMA_DETECT is TRUE) regardless of the settings of the xxx bits. True: Raise RXCHARISCOMMA only on valid characters that are in the 8B/10B translation. MCOMMA_10B_VALUE This 10-bit vector defines minus-comma for the purpose of raising RXCOMMADET and realigning the serial bit stream byte boundary. This definition does not affect 8B/10B encoding or decoding. Also see COMMA_10B_MASK. MCOMMA_DETECT True/False indicates whether to raise or not raise the RXCOMMADET when minus-comma is detected. PCOMMA_10B_VALUE This 10-bit vector defines plus-comma for the purpose of raising RXCOMMADET and realigning the serial bit stream byte boundary. This definition does not affect 8B/10B encoding or decoding. Also see COMMA_10B_MASK. PCOMMA_DETECT True/False indicates whether to raise or not raise the RXCOMMADET when plus-comma is detected. RX_BUFFER_USE Always set to True. RX_CRC_USE, TX_CRC_USE True/False determines if CRC is used or not. RX_DATA_WIDTH, TX_DATA_WIDTH Integer (1, 2, or 4). Relates to the data width of the FPGA fabric interface. RX_DECODE_USE This determines if the 8B/10B decoding is bypassed. False denotes that it is bypassed. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 169 R Table 2-2: Chapter 2: Design Considerations Rocket I/O Transceiver Attributes (Continued) Attribute Description RX_LOS_INVALID_INCR Power of two in a range of 1 to 128 that denotes the number of valid characters required to "cancel out" appearance of one invalid character for loss of sync determination. RX_LOS_THRESHOLD Power of two in a range of 4 to 512. When divided by RX_LOS_INVALID_INCR, denotes the number of invalid characters required to cause FSM transition to "sync lost" state. RX_LOSS_OF_SYNC_FSM True/False denotes the nature of RXLOSSOFSYNC output. True: RXLOSSOFSYNC outputs the state of the FSM bit. See RXLOSSOFSYNC, page 164, for details. SERDES_10B Denotes whether the reference clock runs at 1/20 or 1/10 the serial bit rate. True denotes 1/10 and False denotes 1/20. False supports a serial bitstream range of 800 Mb/s to 3.125 Gb/s. True supports a range of 500 Mb/s to 1.0 Gb/s. TERMINATION_IMP Integer (50 or 75). Termination impedance of either 50 or 75. Refers to both the RX and TX. TX_BUFFER_USE Always set to True. TX_CRC_FORCE_VALUE 8-bit vector. Value to corrupt TX CRC computation when input TXFORCECRCERR is high. This value is XORed with the correctly computed CRC value, corrupting the CRC if TX_CRC_FORCE_VALUE is nonzero. This can be used to test CRC error detection in the receiver downstream. TX_DIFF_CTRL This is an integer value either 400 mV, 500 mV, 600 mV, 700 mV, or 800 mV. It determines the amount of voltage difference between the differential lines. Twice the value is the peak-peak value. TX_PREEMPHASIS This is an integer value 0-3 that sets the output driver pre-emphasis to improve output waveform shaping for various load conditions. Larger value denotes stronger pre-emphasis. See pre-emphasis values in Table 4-2, page 67. 170 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Modifiable Primitives As shown in Table 2-3 and Table 2-4, only certain attributes are modifiable for any primitive. These attributes help to define the protocol used by the primitive. Only the GT_CUSTOM primitive allows the user to modify all of the attributes to a protocol not supported by another transceiver primitive. This allows for complete flexibility. The other primitives allow modification of the analog attributes of the serial data lines and several channel-bonding values. Table 2-3: Default Attribute Values for GT_AURORA, GT_CUSTOM, GT_ETHERNET Default GT_AURORA Default GT_CUSTOM (1) Default GT_ETHERNET ALIGN_COMMA_MSB False False False CHAN_BOND_LIMIT 16 16 1 CHAN_BOND_MODE OFF (2) OFF OFF CHAN_BOND_OFFSET 8 8 0 Falso (2) False True CHAN_BOND_SEQ_1_1 00101111100 00000000000 00000000000 CHAN_BOND_SEQ_1_2 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_1_3 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_1_4 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_2_1 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_2_2 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_2_3 00000000000 00000000000 00000000000 CHAN_BOND_SEQ_2_4 00000000000 00000000000 00000000000 False False False CHAN_BOND_SEQ_LEN 1 1 1 CHAN_BOND_WAIT 8 8 7 CLK_COR_INSERT_IDLE_FLAG False (2) False False (2) CLK_COR_KEEP_IDLE False (2) False False (2) 1 (2) 1 1 (2) CLK_COR_SEQ_1_1 00100011100 00000000000 00110111100 CLK_COR_SEQ_1_2 00100011100 (4) 00000000000 00001010000 CLK_COR_SEQ_1_3 00100011100 (5) 00000000000 00000000000 CLK_COR_SEQ_1_4 00100011100 (5) 00000000000 00000000000 CLK_COR_SEQ_2_1 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_2 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_3 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_4 00000000000 00000000000 00000000000 Attribute CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_2_USE CLK_COR_REPEAT_WAIT UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 171 R Chapter 2: Design Considerations Table 2-3: Default Attribute Values for GT_AURORA, GT_CUSTOM, GT_ETHERNET (Continued) Default GT_AURORA Default GT_CUSTOM (1) Default GT_ETHERNET CLK_COR_SEQ_2_USE False False False CLK_COR_SEQ_LEN N (3) 1 2 CLK_CORRECT_USE True True True COMMA_10B_MASK 1111111111 1111111000 1111111000 K29_7 K29_7 K29_7 USER_MODE USER_MODE ETHERNET K27_7 K27_7 K27_7 DEC_MCOMMA_DETECT True True True DEC_PCOMMA_DETECT True True True DEC_VALID_COMMA_ONLY True True True 1100000101 1100000000 1100000000 True True True 0011111010 0011111000 0011111000 PCOMMA_DETECT True True True RX_BUFFER_USE True True True False (2) False False (2) RX_DATA_WIDTH N (3) 2 N (3) RX_DECODE_USE True True True RX_LOS_INVALID_INCR 1 (2) 1 1 (2) RX_LOS_THRESHOLD 4 (2) 4 4 (2) RX_LOSS_OF_SYNC_FSM True (2) True True (2) SERDES_10B False (2) False False (2) TERMINATION_IMP 50 (2) 50 50 (2) TX_BUFFER_USE True True True 11010110 (2) 11010110 11010110 (2) False (2) False False (2) N (3) 2 N (3) 500 (2) 500 500 (2) 0 (2) 0 0 (2) Attribute CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE RX_CRC_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS Notes: 1. All GT_CUSTOM attributes are modifiable. 2. Modifiable attribute for specific primitives. 3. Depends on primitive used: either 1, 2, or 4. 4. Attribute value only when RX_DATA_WIDTH is 2 or 4. When RX_DATA_WIDTH is 1, attribute value is 0. 5. Attribute value only when RX_DATA_WIDTH is 4. When RX_DATA_WIDTH is 1 or 2, attribute value is 0. 172 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Table 2-4: Default Attribute Values for GT_FIBRE_CHAN, GT_INFINIBAND, and GT_XAUI Default GT_FIBRE_CHAN Default GT_INFINIBAND Default GT_XAUI ALIGN_COMMA_MSB False False False CHAN_BOND_LIMIT 1 16 16 CHAN_BOND_MODE OFF OFF (1) OFF (1) CHAN_BOND_OFFSET 0 8 8 True False (1) False (1) CHAN_BOND_SEQ_1_1 00000000000 00110111100 00101111100 CHAN_BOND_SEQ_1_2 00000000000 Lane ID (Modify with Lane ID) 00000000000 CHAN_BOND_SEQ_1_3 00000000000 00001001010 00000000000 CHAN_BOND_SEQ_1_4 00000000000 00001001010 00000000000 CHAN_BOND_SEQ_2_1 00000000000 00110111100 00000000000 CHAN_BOND_SEQ_2_2 00000000000 Lane ID (Modify with Lane ID) 00000000000 CHAN_BOND_SEQ_2_3 00000000000 00001000101 00000000000 CHAN_BOND_SEQ_2_4 00000000000 00001000101 00000000000 False True False CHAN_BOND_SEQ_LEN 1 4 1 CHAN_BOND_WAIT 7 8 8 CLK_COR_INSERT_IDLE_FLAG False (1) False (1) False (1) CLK_COR_KEEP_IDLE False (1) False (1) False (1) 2 (1) 1 (1) 1 (1) CLK_COR_SEQ_1_1 00110111100 00100011100 00100011100 CLK_COR_SEQ_1_2 00010010101 00000000000 00000000000 CLK_COR_SEQ_1_3 00010110101 00000000000 00000000000 CLK_COR_SEQ_1_4 00010110101 00000000000 00000000000 CLK_COR_SEQ_2_1 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_2 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_3 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_4 00000000000 00000000000 00000000000 False False False CLK_COR_SEQ_LEN 4 1 1 CLK_CORRECT_USE True True True COMMA_10B_MASK 1111111000 1111111000 1111111000 Attribute CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_2_USE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_2_USE UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 173 R Chapter 2: Design Considerations Table 2-4: Default Attribute Values for GT_FIBRE_CHAN, GT_INFINIBAND, and GT_XAUI (Continued) Default GT_FIBRE_CHAN Default GT_INFINIBAND Default GT_XAUI K29_7 Note (3) K29_7 (1) FIBRE_CHAN INFINIBAND USER_MODE (1) CRC_START_OF_PKT K27_7 Note (3) K27_7 (1) DEC_MCOMMA_DETECT True True True DEC_PCOMMA_DETECT True True True DEC_VALID_COMMA_ONLY True True True Lane ID(INFINBAND ONLY) NA 00000000000 (1) NA 1100000000 1100000000 1100000000 True True True 0011111000 0011111000 0011111000 PCOMMA_DETECT True True True RX_BUFFER_USE True True True False (1) False (1) False (1) RX_DATA_WIDTH N (2) N (2) N (2) RX_DECODE_USE True True True RX_LOS_INVALID_INCR 1 (1) 1 (1) 1 (1) RX_LOS_THRESHOLD 4 (1) 4 (1) 4 (1) RX_LOSS_OF_SYNC_FSM True (1) True (1) True (1) SERDES_10B False (1) False (1) False (1) TERMINATION_IMP 50 (1) 50 (1) 50 (1) TX_BUFFER_USE True True True 11010110 (1) 11010110 (1) 11010110 (1) False (1) False (1) False (1) N (2) N (2) N (2) 500 (1) 500 (1) 500 (1) 0 (1) 0 (1) 0 (1) Attribute CRC_END_OF_PKT CRC_FORMAT MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE RX_CRC_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS Notes: 1. Modifiable attribute for specific primitives. 2. Depends on primitive used: either 1, 2, or 4. 3. CRC_EOP and CRC_SOP are not applicable for this primitive. 174 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Byte Mapping Most of the 4-bit wide status and control buses correlate to a specific byte of the TXDATA or RXDATA. This scheme is shown in Table 2-5. This creates a way to tie all the signals together regardless of the data path width needed for the GT_CUSTOM. All other primitives with specific data width paths and all byte-mapped ports are affected by this situation. For example, a 1-byte wide data path has only 1-bit control and status bits (TXKERR[0]) correlating to the data bits TXDATA[7:0]. Note 3 in Table 2-1 shows the ports that use byte mapping. Table 2-5: Control/Status Bus Association to Data Bus Byte Paths. Control/Status Bit Data Bits [0] [7:0] [1] [15:8] [2] [23:16] [3] [31:24] Clocking Clock Signals There are five clock inputs into each Rocket I/O transceiver instantiation (Table 2-6). REFCLK is a clock generated from an external source. REFCLK is connected to the REFCLK of the Rocket I/O transceiver. It also clocks a Digital Clock Manager (DCM) to generate all of the other clocks for the gigabit transceiver. Typically, TXUSRCLK = RXUSRCLK and TXUSRCLK2 = RXUSRCLK2. The transceiver uses one or two clocks generated by the DCM. As an example, the USRCLK and USRCLK2 clocks run at the same speed if the 2-byte data path is used. The USRCLK must always be frequency-locked to the reference clock, REFCLK of the Rocket I/O transceiver. NOTE: The REFCLK must be at least 40 MHz with a duty cycle between 45% and 55%, and should have a frequency stability of 100 ppm or better, with jitter as low as possible. Module 3 of the Virtex-II Pro data sheet gives further details. Table 2-6: Clock Ports Clock I/Os RXRECCLK Output Recovered clock (from serial data stream) divided by 20 REFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for parallel-to-serial conversion (20X) REFCLK2 Input Reference clock used to read the TX FIFO and multiplied by 20 for parallel-to-serial conversion (20X) REFCLKSEL Input Selects which reference clock is used. 0 selects REFCLK; 1 selects REFCLK2. RXUSRCLK Input Clock from FPGA used for reading the RX Elastic Buffer. Clock signals CHBONDI and CHBONDO into and out of the transceiver. This clock is typically the same as TXUSRCLK. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Description www.xilinx.com 1-800-255-7778 175 R Chapter 2: Design Considerations Table 2-6: Clock Ports (Continued) Clock I/Os Description TXUSRCLK Input Clock from FPGA used for writing the TX Buffer. This clock must be frequency locked to REFCLK for proper operation. RXUSRCLK2 Input Clock from FPGA used to clock RX data and status between the transceiver and FPGA fabric. The relationship between RXUSRCLK2 and RXUSRCLK depends on the width of the receiver data path. RXUSRCLK2 is typically the same as TXUSRCLK2. TXUSRCLK2 Input Clock from FPGA used to clock TX data and status between the transceiver and FPGA fabric. The relationship between TXUSRCLK2 and TXUSRCLK depends on the width of the transmission data path. Clock Ratio USRCLK2 clocks the data buffers. The ability to send parallel data to the transceiver at three different widths requires the user to change the frequency of USRCLK2. This creates a frequency ratio between USRCLK and USRCLK2. The falling edges of the clocks must align. Finally, for a 4-byte data path, the 1-byte data path creates a clocking scheme where USRCLK2 is phase-shifted 180 and at twice the rate of USRCLK. Table 2-7: Data Width Clock Ratios Data Width Frequency Ratio of USRCLK\USRCLK2 1 byte 1:2 (1) 2 byte 1:1 4 byte 2:1 (1) Notes: 1. Each edge of slower clock must align with falling edge of faster clock Digital Clock Manager (DCM) Examples With at least three different clocking schemes possible on the transceiver, a DCM is the best way to create these schemes. Table 2-8 shows typical DCM connections for several transceiver clocks. REFCLK is the input reference clock for the DCM. The other clocks are generated by the DCM. The DCM establishes a desired phase relationship between RXUSRCLK, TXUSRCLK, etc. in the FPGA fabric and REFCLK at the pad. Table 2-8: 176 DCM Outputs for Different DATA_WIDTHs SERDES_10B TX_DATA_WIDTH RX_DATA_WIDTH REFCLK TXUSRCLK RXUSRCLK TXUSRCLK2 RXUSRCLK2 False 1 CLKIN CLK0 CLK2X180 False 2 CLKIN CLK0 CLK0 False 4 CLKIN CLK180 (1) CLKDV (divide by 2) True 1 CLKIN CLKDV (divide by 2) CLK180 (1) www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver Table 2-8: DCM Outputs for Different DATA_WIDTHs SERDES_10B TX_DATA_WIDTH RX_DATA_WIDTH REFCLK True 2 True 4 TXUSRCLK RXUSRCLK TXUSRCLK2 RXUSRCLK2 CLKIN CLKDV (divide by 2) CLKDV (divide by 2) CLKIN CLKFX180 (divide by 2) CLKDV (divide by 4) Notes: 1. Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver's local inverter, saving a global buffer (BUFG). Example : Two-Byte Clock The following HDL codes are examples of a simple clock scheme using 2-byte data with both USRCLK and USRCLK2 at the same frequency. USRCLK_M is the input for both USRCLK and USRCLK2. Be sure to check the Xilinx Virtex-II Pro web page at www.xilinx.com/virtex2pro for the latest code files. MGT + DCM for 2-Byte Data Path Clocks for 2-Byte Data Path REFCLK GT_std_2 TXUSRCLK RXUSRCLK 0 IBUFG TXUSRCLK2 REFCLK RXUSRCLK2 DCM CLKIN CLKFB RST CLK0 REFCLKSEL REFCLK TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK BUFG ug024_02_021102 Figure 2-1: Two-Byte Clock VHDL Template -- Module: TWO_BYTE_CLK -- Description: VHDL submodule -DCM for 2-byte GT --- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity TWO_BYTE_CLK is port ( REFCLKIN : in std_logic; RST : in std_logic; USRCLK_M : out std_logic; REFCLK : out std_logic; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 177 R Chapter 2: Design Considerations LOCK : out std_logic ); end TWO_BYTE_CLK; -architecture TWO_BYTE_CLK_arch of TWO_BYTE_CLK is --- Components Declarations: component BUFG port ( I : in std_logic; O : out std_logic ); end component; -component DCM port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector ( 7 downto 0 ) ); end component; --- Signal Declarations: -signal GND : std_logic; signal CLK0_W : std_logic; signal CLK1X_W : std_logic; begin GND -CLK1X --- DCM U_DCM: port 178 <= '0'; <= CLK1X_W; Instantiation DCM map ( CLKIN => CLKFB => DSSEN => PSINCDEC => PSEN => PSCLK => RST => CLK0 => REFCLK, USRCLK_M, GND, GND, GND, GND, RST, CLK0_W, www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Rocket I/O Transceiver LOCKED ); => LOCK --- BUFG Instantiation U_BUFG: BUFG port map ( I => REFCLKIN, O => REFCLK ); U2_BUFG: BUFG port map ( I => CLK0_W, O => USRCLK_M ); end TWO_BYTE_CLK_arch; Verilog Template //Module: //Description: // // // Device: TWO_BYTE_CLK Verilog Submodule DCM for 2-byte GT Virtex-II Pro Family module TWO_BYTE_CLK ( REFCLKIN, REFCLK, DCM_LOCKED ); input output output output REFCLKIN; REFCLK; USRCLK_M; DCM_LOCKED; wire wire wire wire wire wire REFCLKIN; REFCLK; USRCLK_M; DCM_LOCKED; REFCLKINBUF; clk_i; DCM dcm1 ( .CLKFB .CLKIN .PSCLK .PSEN .PSINCDEC .RST .CLK0 .CLK90 .CLK180 .CLK270 .CLK2X .CLK2X180 .CLKDV .CLKFX .CLKFX180 .LOCKED .PSDONE .STATUS UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( USRCLK_M, USRCLK_M ), REFCLKINBUF ), .DSSEN( 1'b0 ), 1'b0 ), 1'b0 ), 1'b0 ), 1'b0 ), clk_i ), ), ), ), ), ), ), ), ), DCM_LOCKED ), ), ) www.xilinx.com 1-800-255-7778 179 R Chapter 2: Design Considerations ); BUFG buf1 ( .I ( clk_i ), .O ( USRCLK_M ) ); BUFG buf2 ( .I ( REFCLKIN ), .O ( REFCLKINBUF )); endmodule Processor Block Introduction This section briefly describes the processor block user signals. Examples of HDL instatiation templates are also shown. Two addtional user manuals detail the hardware and software design aspects of the processor block. The Processor Block Manual provides information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation. The PPC405 User Manual serves as a stand-alone reference for application and system programmers of the PPC405 processor core. For the latest information, visit www.xilinx.com/virtex2pro. The following table summarizes the processor block user signals. For more details, refer to the Processor Block Manual. Table 2-9: PPC405 Interface Signals in Alphabetical Order I/O Type If Unused BRAMDSOCMCLK I 0 BRAMDSOCMRDDBUS[0:31] I 0x0000_0000 BRAMISOCMCLK I 0 BRAMISOCMRDDBUS[0:63] I 0x0000_0000 _0000_0000 64-bit read data from block RAMs, two instructions per cycle, to ISOCM. C405CPMCORESLEEPREQ O No Connect Indicates the core is requesting to be put into sleep mode. C405CPMMSRCE O No Connect Indicates the value of MSR[CE]. C405CPMMSREE O No Connect Indicates the value of MSR[EE]. C405CPMTIMERIRQ O No Connect Indicates a timer-interrupt request occurred. C405CPMTIMERRESETREQ O No Connect Indicates a watchdog-timer reset request occurred. C405DBGMSRWE O No Connect Indicates the value of MSR[WE]. C405DBGSTOPACK O No Connect Indicates the PPC405 is in debug halt mode. C405DBGWBCOMPLETE O No Connect Indicates the current instruction in the PPC405 writeback pipeline stage is completing. C405DBGWBFULL O No Connect Indicates the PPC405 writeback pipeline stage is full. C405DBGWBIAR[0:29] O No Connect The address of the current instruction in the PPC405 writeback pipeline stage. Signal 180 www.xilinx.com 1-800-255-7778 Function Clocks the DSOCM controller. 32-bit Read data from block RAMs to DSOCM. Clocks the ISOCM controller. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block Table 2-9: PPC405 Interface Signals in Alphabetical Order (Continued) I/O Type If Unused C405DCRABUS[0:9] O No Connect Specifies the address of the DCR access request. C405DCRDBUSOUT[0:31] O No Connect or attach to input bus The 32-bit DCR write-data bus. C405DCRREAD O No Connect Indicates a DCR read request occurred. C405DCRWRITE O No Connect Indicates a DCR write request occurred. C405JTGCAPTUREDR O No Connect Indicates the TAP controller is in the capture-DR state. C405JTGEXTEST O No Connect Indicates the JTAG EXTEST instruction is selected. C405JTGPGMOUT O No Connect Indicates the state of a general purpose program bit in the JTAG debug control register (JDCR). C405JTGSHIFTDR O No Connect Indicates the TAP controller is in the shift-DR state. C405JTGTDO O No Connect JTAG TDO (test-data out). C405JTGTDOEN O No Connect Indicates the JTAG TDO signal is enabled. C405JTGUPDATEDR O No Connect Indicates the TAP controller is in the update-DR state. C405PLBDCUABORT O No Connect Indicates the DCU is aborting an unacknowledged data-access request. C405PLBDCUABUS[0:31] O No Connect Specifies the memory address of the data-access request. C405PLBDCUBE[0:7] O No Connect Specifies which bytes are transferred during singleword transfers. C405PLBDCUCACHEABLE O No Connect Indicates the value of the cacheability storage attribute for the target address. C405PLBDCUGUARDED O No Connect Indicates the value of the guarded storage attribute for the target address. C405PLBDCUPRIORITY[0:1] O No Connect Indicates the priority of the data-access request. C405PLBDCUREQUEST O No Connect Indicates the DCU is making a data-access request. C405PLBDCURNW O No Connect Specifies whether the data-access request is a read or a write. C405PLBDCUSIZE2 O No Connect Specifies a single word or eight-word transfer size. C405PLBDCUU0ATTR O No Connect Indicates the value of the user-defined storage attribute for the target address. C405PLBDCUWRDBUS[0:63] O No Connect The DCU write-data bus used to transfer data from the DCU to the PLB slave. C405PLBDCUWRITETHRU O No Connect Indicates the value of the write-through storage attribute for the target address. C405PLBICUABORT O No Connect Indicates the ICU is aborting an unacknowledged fetch request. C405PLBICUABUS[0:29] O No Connect Specifies the memory address of the instructionfetch request. Bits 30:31 of the 32-bit address are assumed to be zero. Signal UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 Function 181 R Table 2-9: Chapter 2: Design Considerations PPC405 Interface Signals in Alphabetical Order (Continued) I/O Type If Unused C405PLBICUCACHEABLE O No Connect Indicates the value of the cacheability storage attribute for the target address. C405PLBICUPRIORITY[0:1] O No Connect Indicates the priority of the ICU fetch request. C405PLBICUREQUEST O No Connect Indicates the ICU is making an instruction-fetch request. C405PLBICUSIZE[2:3] O No Connect Specifies a four word or eight word line-transfer size. C405PLBICUU0ATTR O No Connect Indicates the value of the user-defined storage attribute for the target address. C405RSTCHIPRESETREQ O Required Indicates a user-defined chip-reset request occurred. C405RSTCORERESETREQ O Required Indicates a user-defined core-reset request occurred. C405RSTSYSRESETREQ O Required Indicates a user-defined system-reset request occurred. C405TRCCYCLE O No Connect Specifies the trace cycle. C405TRCEVENEXECUTIONSTATUS[0:1] O No Connect Specifies the execution status collected during the first of two processor cycles. C405TRCODDEXECUTIONSTATUS[0:1] O No Connect Specifies the execution status collected during the second of two processor cycles. C405TRCTRACESTATUS[0:3] O No Connect Specifies the trace status. C405TRCTRIGGEREVENTOUT O Wrap to TRCC405 TRIGGER EVENTIN C405TRCTRIGGEREVENTTYPE[0:10] O No Connect Specifies which debug event caused the trigger event. C405XXXMACHINECHECK O No Connect Indicates a machine-check error has been detected by the PPC405. CPMC405CLOCK I 1 PPC405 clock input (for all non-JTAG logic, including timers). CPMC405CORECLKINACTIVE I 0 Indicates the CPM logic disabled the clocks to the core. CPMC405CPUCLKEN I 1 Enables the core clock zone. CPMC405JTAGCLKEN I 1 Enables the JTAG clock zone. CPMC405TIMERCLKEN I 1 Enables the timer clock zone. CPMC405TIMERTICK I 1 Increments or decrements the PPC405 timers every time it is active with the CPMC405CLOCK. DBGC405DEBUGHALT I 0 Indicates the external debug logic is placing the processor in debug halt mode. DBGC405EXTBUSHOLDACK I 0 Indicates the bus controller has given control of the bus to an external master. DBGC405UNCONDDEBUGEVENT I 0 Indicates the external debug logic is causing an unconditional debug event. Signal 182 www.xilinx.com 1-800-255-7778 Function Indicates a trigger event occurred. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block Table 2-9: PPC405 Interface Signals in Alphabetical Order (Continued) I/O Type If Unused DCRC405ACK I 0 DCRC405DBUSIN[0:31] I 0x0000_0000 or attach to output bus DSARCVALUE[0:7] I 0x00 Default value that needs to be loaded into DSARC register at FPGA power up. DSCNTLVALUE[0:7] I 0x40 Default value that needs to be loaded into DSCNTL register at FPGA power up. DSOCMBRAMABUS[8:29] O No Connect Read or Write address from DSOCM to DSBRAM. A write address is accompanied by a write enable signal for each byte lane of data. Corresponds to CPU address bits [8:29]. DSOCMBRAMBYTEWRITE[0:3] O No Connect Four Write Enable signals to allow independent byte-wide data writes into block RAMs. DSOCMBRAMEN O No Connect The block RAM Enable signal is asserted for both read and writes to the DSBRAM. DSOCMBRAMWRDBUS[0:31] O No Connect 32-bit Write data from DSOCM to block RAMs. DSOCMBUSY O No Connect This control signal reflects the value of the DSCNTL[2] bit out to the FPGA fabric. EICC405CRITINPUTIRQ I 0 Indicates an external critical interrupt occurred. EICC405EXTINPUTIRQ I 0 Indicates an external noncritical interrupt occurred. ISARCVALUE[0:7] I 0x00 Default value that needs to be loaded into ISARC register, at FPGA power up. ISCNTLVALUE[0:7] I 0x00 Default value that needs to be loaded into ISCNTL register, at FPGA power up. ISOCMBRAMEN O No Connect Block RAM read enable from ISOCM to block RAMs. ISOCMBRAMODDWRITEEN O No Connect Write enable to qualify a valid write into a block RAM. ISOCMBRAMRDABUS[8:28] O No Connect Read address from ISOCM to block RAM. Corresponds to CPU address bits [8:28]. ISOCMBRAMWRABUS[8:28] O No Connect Write address from ISOCM to block RAMs. Initially set to value in ISINIT register. (Optional. Used in dual-port BRAM interface designs only.) ISOCMBRAMWRDBUS[0:31] O No Connect 32-bit Write data from ISOCM to block RAMs. Connect to both the even and odd write only ISBRAM data input ports. Initially set to value in ISFILL register. (Optional. Used in dual-port BRAM interface designs only.) JTGC405BNDSCANTDO I 0 JTAG boundary scan input from the previous boundary scan element TDO output. JTGC405TCK I 1 JTAG TCK (test clock). JTGC405TDI I 1 JTAG TDI (test-data in). Signal UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 Function Indicates a DCR access has been completed by a peripheral. The 32-bit DCR read-data bus. 183 R Table 2-9: Chapter 2: Design Considerations PPC405 Interface Signals in Alphabetical Order (Continued) I/O Type If Unused JTGC405TMS I 1 JTAG TMS (test-mode select). JTGC405TRSTNEG I 1 Performs a JTAG test reset. MCBCPUCLKEN I 1 Indicates the PPC405 clock enable should follow GWE during a partial reconfiguration. MCBJTAGEN I 1 Indicates the JTAG clock enable should follow GWE during a partial reconfiguration. MCBTIMEREN I 1 Indicates the timer clock enable should follow GWE during a partial reconfiguration. MCPPCRST I 1 Indicates the PPC405 should be reset when GSR is asserted during a partial reconfiguration. PLBC405DCUADDRACK I 0 Indicates a PLB slave acknowledges the current data-access request. PLBC405DCUBUSY I 0 Indicates the PLB slave is busy performing an operation requested by the DCU. PLBC405DCUERR I 0 Indicates an error was detected by the PLB slave during the transfer of data to or from the DCU. PLBC405DCURDDACK I 0 Indicates the DCU read-data bus contains valid data for transfer to the DCU. PLBC405DCURDDBUS[0:63] I 0x0000_0000 _0000_0000 The DCU read-data bus used to transfer data from the PLB slave to the DCU. PLBC405DCURDWDADDR[1:3] I 0b000 Indicates which word or doubleword of an eightword line transfer is present on the DCU read-data bus. PLBC405DCUSSIZE1 I 0 Specifies the bus width (size) of the PLB slave that accepted the request. PLBC405DCUWRDACK I 0 Indicates the data on the DCU write-data bus is being accepted by the PLB slave. PLBC405ICUADDRACK I 0 Indicates a PLB slave acknowledges the current ICU fetch request. PLBC405ICUBUSY I 0 Indicates the PLB slave is busy performing an operation requested by the ICU. PLBC405ICUERR I 0 Indicates an error was detected by the PLB slave during the transfer of instructions to the ICU. PLBC405ICURDDACK I 0 Indicates the ICU read-data bus contains valid instructions for transfer to the ICU. PLBC405ICURDDBUS[0:63] I 0x0000_0000 _0000_0000 The ICU read-data bus used to transfer instructions from the PLB slave to the ICU. PLBC405ICURDWDADDR[1:3] I 0b000 Indicates which word or doubleword of a four-word or eight-word line transfer is present on the ICU read-data bus. PLBC405ICUSSIZE1 I 0 Specifies the bus width (size) of the PLB slave that accepted the request. PLBCLK I 1 PLB clock. Signal 184 www.xilinx.com 1-800-255-7778 Function UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block Table 2-9: PPC405 Interface Signals in Alphabetical Order (Continued) I/O Type If Unused RSTC405RESETCHIP I 0 User-defined chip reset. It has no effect on FPGA fabric global set/reset. RSTC405RESETCORE I 0 Reset request for the PPC405 core logic, data cache, instruction cache, and the on-chip memory controller (OCM). RSTC405RESETSYS I 0 User-defined system reset request. It has no effect on FPGA fabric global set/reset. TIEC405DETERMINISTICMULT I 0 Specifies whether all multiply operations complete in a fixed number of cycles or have an early-out capability. TIEC405DISOPERANDFWD I 1 Disables operand forwarding for load instructions. TIEC405MMUEN I 1 Enables the memory-management unit (MMU) TIEDSOCMDCRADDR[0:7] I 0x00 Top 8 bits of DCR address space for DSOCM DCR registers. The DCR address space is 10 bits wide. The two least significant bits are predefined in DSOCM controller. TIEISOCMDCRADDR[0:7] I 0x00 Top 8 bits of DCR address space for ISOCM DCR registers. The DCR address space is 10 bits wide. The two least significant bits are predefined in ISOCM controller. TRCC405TRACEDISABLE I 0 TRCC405TRIGGEREVENTIN I Wrap to C405TRC TRIGGER EVENTOUT Signal Function Disables trace collection and broadcast. Indicates a trigger event occurred and that trace status is to be generated. Instantiation Templates VHDL and Verilog instantiation templates are available as examples for all submodules. In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. As examples, the PPC405_SUBM.vhd VHDL template and PPC405_SUBM.v Verilog template are shown. (Be sure to check the Xilinx Virtex-II Pro web page at www.xilinx.com/virtex2pro for the latest code files.0 VHDL Template -- Module: Proc_blk_template -- Description: Verilog Module -- Processor Block instantiation template --- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 185 R Chapter 2: Design Considerations Port ( -- user defined port list ); end top; architecture arch of top is ---------------------------------------------------------------------- The following convention is used for signal names throughout this -- document: -- PREFIX1PREFIX2SIGNAME1[SIGNAME1][NEG][(m:n)] -- The components of a signal name are as follows: --* ----- PREFIX1 is an uppercase prefix identifying the source of the signal. This prefix specifies either a unit (for example, CPU) or a type of interface (for example, DCR). If PREFIX1 specifies the processor block, the signal is considered an output signal. Otherwise, it is an input signal. --* ----- PREFIX2 is an uppercase prefix identifying the destination of the signal. This prefix specifies either a unit (for example, CPU) or a type of interface (for example, DCR). If PREFIX2 specifies the processor block, the signal is considered an input signal. Otherwise, it is an output signal. --* SIGNAME1 is an uppercase name identifying the primary function of -- the signal. --* [SIGNAME1] is an uppercase name identifying the primary function of -- the signal. --* [NEG] is an optional notation that indicates a signal is active low. -- If this notation is not use, the signal is active high. --* [m:n] is an optional notation that indicates a bused signal. "m" -- designates the most-significant bit of the bus and "n" designates -- the least-significant bit of the bus. -- The following table defines the prefixes used in the signal names. ---------------- Prefix1/2 Definition ====================== CPM Clock and power management C405 Processor block DBG Debug unit DCR Device control register DSOCM Data-side on-chip memory (DSOCM EIC External interrupt controller ISOCM Instruction-side on-chip memory (ISOCM) JTG JTAG PLB Processor local bus RST Reset TIE TIE (signal tied statically to GND or VDD) TRC Trace XXX FPGA unit --Refer to Processor Block Manual for detailed interface descriptions. --------------------------------------------------------------------*/ 186 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block component PPC405 port ( CPMC405CLOCK : CPMC405CORECLKINACTIVE : CPMC405CPUCLKEN : CPMC405JTAGCLKEN : CPMC405TIMERCLKEN : CPMC405TIMERTICK : C405CPMCORESLEEPREQ : C405CPMMSRCE : C405CPMMSREE : C405CPMTIMERIRQ : C405CPMTIMERRESETREQ : PLBC405ICUADDRACK : PLBC405ICUBUSY : PLBC405ICUERR : PLBC405ICURDDACK : PLBC405ICURDDBUS : PLBC405ICURDWDADDR : PLBC405ICUSSIZE1 : PLBCLK : C405PLBICUABORT : C405PLBICUABUS : C405PLBICUCACHEABLE : C405PLBICUPRIORITY : C405PLBICUREQUEST : C405PLBICUSIZE : C405PLBICUU0ATTR : PLBC405DCUADDRACK : PLBC405DCUBUSY : PLBC405DCUERR : PLBC405DCURDDACK : PLBC405DCURDDBUS : PLBC405DCURDWDADDR : PLBC405DCUSSIZE1 : PLBC405DCUWRDACK : C405PLBDCUABORT : C405PLBDCUABUS : C405PLBDCUBE : C405PLBDCUCACHEABLE : C405PLBDCUGUARDED : C405PLBDCUPRIORITY : C405PLBDCUREQUEST : C405PLBDCURNW : C405PLBDCUSIZE2 : C405PLBDCUU0ATTR : C405PLBDCUWRDBUS : C405PLBDCUWRITETHRU : DCRC405ACK : DCRC405DBUSIN : C405DCRABUS : C405DCRDBUSOUT : C405DCRREAD : C405DCRWRITE : BRAMDSOCMCLK : BRAMDSOCMRDDBUS : BRAMISOCMCLK : BRAMISOCMRDDBUS : DSOCMBRAMABUS : DSOCMBRAMBYTEWRITE : DSOCMBRAMEN : DSOCMBRAMWRDBUS : UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; out std_logic; out std_logic; out std_logic; out std_logic; out std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(0 to 63); in std_logic_vector(1 to 3); in std_logic; in std_logic; out std_logic; out std_logic_vector(0 to 29); out std_logic; out std_logic_vector(0 to 1); out std_logic; out std_logic_vector(2 to 3); out std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(0 to 63); in std_logic_vector(1 to 3); in std_logic; in std_logic; out std_logic; out std_logic_vector(0 to 31); out std_logic_vector(0 to 7); out std_logic; out std_logic; out std_logic_vector(0 to 1); out std_logic; out std_logic; out std_logic; out std_logic; out std_logic_vector(0 to 63); out std_logic; in std_logic; in std_logic_vector(0 to 31); out std_logic_vector(0 to 9); out std_logic_vector(0 to 31); out std_logic; out std_logic; in std_logic; in std_logic_vector(0 to 31); in std_logic; in std_logic_vector(0 to 63); out std_logic_vector(8 to 29); out std_logic_vector(0 to 3); out std_logic; out std_logic_vector(0 to 31); 187 R 188 Chapter 2: Design Considerations DSOCMBUSY : ISOCMBRAMEN : ISOCMBRAMEVENWRITEEN : ISOCMBRAMODDWRITEEN : ISOCMBRAMRDABUS : ISOCMBRAMWRABUS : ISOCMBRAMWRDBUS : TIEDSOCMDCRADDR : TIEISOCMDCRADDR : DSARCVALUE : DSCNTLVALUE : ISARCVALUE : ISCNTLVALUE : DBGC405DEBUGHALT : DBGC405EXTBUSHOLDACK : DBGC405UNCONDDEBUGEVENT : C405DBGMSRWE : C405DBGSTOPACK : C405DBGWBCOMPLETE : C405DBGWBFULL : C405DBGWBIAR : JTGC405BNDSCANTDO : JTGC405TCK : JTGC405TDI : JTGC405TMS : JTGC405TRSTNEG : C405JTGCAPTUREDR : C405JTGEXTEST : C405JTGPGMOUT : C405JTGSHIFTDR : C405JTGTDO : C405JTGTDOEN : C405JTGUPDATEDR : TRCC405TRACEDISABLE : TRCC405TRIGGEREVENTIN : C405TRCCYCLE : C405TRCEVENEXECUTIONSTATUS : C405TRCODDEXECUTIONSTATUS : C405TRCTRACESTATUS : C405TRCTRIGGEREVENTOUT : C405TRCTRIGGEREVENTTYPE : RSTC405RESETCHIP : RSTC405RESETCORE : RSTC405RESETSYS : C405RSTCHIPRESETREQ : C405RSTCORERESETREQ : C405RSTSYSRESETREQ : EICC405CRITINPUTIRQ : EICC405EXTINPUTIRQ : TIEC405DETERMINISTICMULT : TIEC405DISOPERANDFWD : TIEC405MMUEN : C405XXXMACHINECHECK : MCBCPUCLKEN : MCBJTAGEN : MCBTIMEREN : MCPPCRST : end component; out std_logic; out std_logic; out std_logic; out std_logic; out std_logic_vector(8 to 28); out std_logic_vector(8 to 28); out std_logic_vector(0 to 31); in std_logic_vector (0 to 7); in std_logic_vector (0 to 7); in std_logic_vector (0 to 7); in std_logic_vector (0 to 7); in std_logic_vector (0 to 7); in std_logic_vector (0 to 7); in std_logic; in std_logic; in std_logic; out std_logic; out std_logic; out std_logic; out std_logic; out std_logic_vector (0 to 29); in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; out std_logic; out std_logic; out std_logic; out std_logic; out std_logic; out std_logic; out std_logic; in std_logic; in std_logic; out std_logic; out std_logic_vector(0 to 1); out std_logic_vector(0 to 1); out std_logic_vector(0 to 3); out std_logic; out std_logic_vector(0 to 10); in std_logic; in std_logic; in std_logic; out std_logic; out std_logic; out std_logic; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic; out std_logic; in std_logic; in std_logic; in std_logic; in std_logic); signal signal signal std_logic; std_logic; std_logic; CPMC405CLOCK : CPMC405CORECLKINACTIVE : CPMC405CPUCLKEN : www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook CPMC405JTAGCLKEN : CPMC405TIMERCLKEN : CPMC405TIMERTICK : C405CPMCORESLEEPREQ : C405CPMMSRCE : C405CPMMSREE : C405CPMTIMERIRQ : C405CPMTIMERRESETREQ : PLBC405ICUADDRACK : PLBC405ICUBUSY : PLBC405ICUERR : PLBC405ICURDDACK : PLBC405ICURDDBUS : PLBC405ICURDWDADDR : PLBC405ICUSSIZE1 : PLBCLK : C405PLBICUABORT : C405PLBICUABUS : C405PLBICUCACHEABLE : C405PLBICUPRIORITY : C405PLBICUREQUEST : C405PLBICUSIZE : C405PLBICUU0ATTR : PLBC405DCUADDRACK : PLBC405DCUBUSY : PLBC405DCUERR : PLBC405DCURDDACK : PLBC405DCURDDBUS : PLBC405DCURDWDADDR : PLBC405DCUSSIZE1 : PLBC405DCUWRDACK : C405PLBDCUABORT : C405PLBDCUABUS : C405PLBDCUBE : C405PLBDCUCACHEABLE : C405PLBDCUGUARDED : C405PLBDCUPRIORITY : C405PLBDCUREQUEST : C405PLBDCURNW : C405PLBDCUSIZE2 : C405PLBDCUU0ATTR : C405PLBDCUWRDBUS : C405PLBDCUWRITETHRU : DCRC405ACK : DCRC405DBUSIN : C405DCRABUS : C405DCRDBUSOUT : C405DCRREAD : C405DCRWRITE : BRAMDSOCMCLK : BRAMDSOCMRDDBUS : BRAMISOCMCLK : BRAMISOCMRDDBUS : DSOCMBRAMABUS : DSOCMBRAMBYTEWRITE : DSOCMBRAMEN : DSOCMBRAMWRDBUS : DSOCMBUSY : ISOCMBRAMEN : ISOCMBRAMEVENWRITEEN : ISOCMBRAMODDWRITEEN : ISOCMBRAMRDABUS : www.xilinx.com 1-800-255-7778 std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(0 std_logic_vector(1 std_logic; std_logic; std_logic; std_logic_vector(0 std_logic; std_logic_vector(0 std_logic; std_logic_vector(2 std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(0 std_logic_vector(1 std_logic; std_logic; std_logic; std_logic_vector(0 std_logic_vector(0 std_logic; std_logic; std_logic_vector(0 std_logic; std_logic; std_logic; std_logic; std_logic_vector(0 std_logic; std_logic; std_logic_vector(0 std_logic_vector(0 std_logic_vector(0 std_logic; std_logic; std_logic; std_logic_vector(0 std_logic; std_logic_vector(0 std_logic_vector(8 std_logic_vector(0 std_logic; std_logic_vector(0 std_logic; std_logic; std_logic; std_logic; std_logic_vector(8 to 63); to 3); to 29); to 1); to 3); to 63); to 3); to 31); to 7); to 1); to 63); to 31); to 9); to 31); to 31); to 63); to 29); to 3); to 31); to 28); 189 R Chapter 2: Design Considerations signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal ISOCMBRAMWRABUS : ISOCMBRAMWRDBUS : TIEDSOCMDCRADDR : TIEISOCMDCRADDR : DSARCVALUE : DSCNTLVALUE : ISARCVALUE : ISCNTLVALUE : DBGC405DEBUGHALT : DBGC405EXTBUSHOLDACK : DBGC405UNCONDDEBUGEVENT : C405DBGMSRWE : C405DBGSTOPACK : C405DBGWBCOMPLETE : C405DBGWBFULL : C405DBGWBIAR : JTGC405BNDSCANTDO : JTGC405TCK : JTGC405TDI : JTGC405TMS : JTGC405TRSTNEG : C405JTGCAPTUREDR : C405JTGEXTEST : C405JTGPGMOUT : C405JTGSHIFTDR : C405JTGTDO : C405JTGTDOEN : C405JTGUPDATEDR : TRCC405TRACEDISABLE : TRCC405TRIGGEREVENTIN : C405TRCCYCLE : C405TRCEVENEXECUTIONSTATUS : C405TRCODDEXECUTIONSTATUS : C405TRCTRACESTATUS : C405TRCTRIGGEREVENTOUT : C405TRCTRIGGEREVENTTYPE : RSTC405RESETCHIP : RSTC405RESETCORE : RSTC405RESETSYS : C405RSTCHIPRESETREQ : C405RSTCORERESETREQ : C405RSTSYSRESETREQ : EICC405CRITINPUTIRQ : EICC405EXTINPUTIRQ : TIEC405DETERMINISTICMULT : TIEC405DISOPERANDFWD : TIEC405MMUEN : C405XXXMACHINECHECK : MCBCPUCLKEN : MCBJTAGEN : MCBTIMEREN : MCPPCRST : std_logic_vector(8 to 28); std_logic_vector(0 to 31); std_logic_vector (0 to 7); std_logic_vector (0 to 7); std_logic_vector (0 to 7); std_logic_vector (0 to 7); std_logic_vector (0 to 7); std_logic_vector (0 to 7); std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector (0 to 29); std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(0 to 1); std_logic_vector(0 to 1); std_logic_vector(0 to 3); std_logic; std_logic_vector(0 to 10); std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; begin -- Processor Block Instantiation ProcessorBlock : PPC405 port map ( -- Clock and Power management interface CPMC405CLOCK => CPMC405CLOCK, 190 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block CPMC405CORECLKINACTIVE CPMC405CPUCLKEN CPMC405JTAGCLKEN CPMC405TIMERCLKEN CPMC405TIMERTICK C405CPMCORESLEEPREQ C405CPMMSRCE C405CPMMSREE C405CPMTIMERIRQ C405CPMTIMERRESETREQ => => => => => => => => => => CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, -- CPU Control Interface TIEC405DETERMINISTICMULT TIEC405DISOPERANDFWD TIEC405MMUEN C405XXXMACHINECHECK => => => => TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, C405XXXMACHINECHECK, -- Reset Interface RSTC405RESETCHIP RSTC405RESETCORE RSTC405RESETSYS C405RSTCHIPRESETREQ C405RSTCORERESETREQ C405RSTSYSRESETREQ => => => => => => RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, -- Processor Local Bus clock PLBCLK => PLBCLK, -- Instruction-side Processor Local Bus Interface PLBC405ICUADDRACK => PLBC405ICUADDRACK, PLBC405ICUBUSY => PLBC405ICUBUSY, PLBC405ICUERR => PLBC405ICUERR, PLBC405ICURDDACK => PLBC405ICURDDACK, PLBC405ICURDDBUS => PLBC405ICURDDBUS, PLBC405ICURDWDADDR => PLBC405ICURDWDADDR, PLBC405ICUSSIZE1 => PLBC405ICUSSIZE1, C405PLBICUABORT => C405PLBICUABORT, C405PLBICUABUS => C405PLBICUABUS, C405PLBICUCACHEABLE => C405PLBICUCACHEABLE, C405PLBICUPRIORITY => C405PLBICUPRIORITY, C405PLBICUREQUEST => C405PLBICUREQUEST, C405PLBICUSIZE => C405PLBICUSIZE, C405PLBICUU0ATTR => C405PLBICUU0ATTR, -- Data-side Processor Local Bus Interface PLBC405DCUADDRACK => PLBC405DCUADDRACK, PLBC405DCUBUSY => PLBC405DCUBUSY, PLBC405DCUERR => PLBC405DCUERR, PLBC405DCURDDACK => PLBC405DCURDDACK, PLBC405DCURDDBUS => PLBC405DCURDDBUS, PLBC405DCURDWDADDR => PLBC405DCURDWDADDR, PLBC405DCUSSIZE1 => PLBC405DCUSSIZE1, PLBC405DCUWRDACK => PLBC405DCUWRDACK, C405PLBDCUABORT => C405PLBDCUABORT, C405PLBDCUABUS => C405PLBDCUABUS, C405PLBDCUBE => C405PLBDCUBE, C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE, C405PLBDCUGUARDED => C405PLBDCUGUARDED, C405PLBDCUPRIORITY => C405PLBDCUPRIORITY, C405PLBDCUREQUEST => C405PLBDCUREQUEST, C405PLBDCURNW => C405PLBDCURNW, C405PLBDCUSIZE2 => C405PLBDCUSIZE2, UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 191 R Chapter 2: Design Considerations C405PLBDCUU0ATTR C405PLBDCUWRDBUS C405PLBDCUWRITETHRU -- Device Control Register Interface DCRC405ACK DCRC405DBUSIN C405DCRABUS C405DCRDBUSOUT C405DCRREAD C405DCRWRITE => C405PLBDCUU0ATTR, => C405PLBDCUWRDBUS, => C405PLBDCUWRITETHRU, => => => => => => DCRC405ACK, DCRC405DBUSIN, C405DCRABUS, C405DCRDBUSOUT, C405DCRREAD, C405DCRWRITE, -- External Interrupt Controller Interface EICC405CRITINPUTIRQ => EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ => EICC405EXTINPUTIRQ, 192 -- On-Chip Memory Controller Interface BRAMDSOCMCLK BRAMDSOCMRDDBUS BRAMISOCMCLK BRAMISOCMRDDBUS DSOCMBRAMABUS DSOCMBRAMBYTEWRITE DSOCMBRAMEN DSOCMBRAMWRDBUS DSOCMBUSY ISOCMBRAMEN ISOCMBRAMEVENWRITEEN ISOCMBRAMODDWRITEEN ISOCMBRAMRDABUS ISOCMBRAMWRABUS ISOCMBRAMWRDBUS DSARCVALUE DSCNTLVALUE ISARCVALUE ISCNTLVALUE TIEDSOCMDCRADDR TIEISOCMDCRADDR => => => => => => => => => => => => => => => => => => => => => BRAMDSOCMCLK, BRAMDSOCMRDDBUS, BRAMISOCMCLK, BRAMISOCMRDDBUS, DSOCMBRAMABUS, DSOCMBRAMBYTEWRITE, DSOCMBRAMEN, DSOCMBRAMWRDBUS, DSOCMBUSY, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, ISOCMBRAMWRDBUS, DSARCVALUE, DSCNTLVALUE, ISARCVALUE, ISCNTLVALUE, TIEDSOCMDCRADDR, TIEISOCMDCRADDR, -- JTAG Interface JTGC405BNDSCANTDO JTGC405TCK JTGC405TDI JTGC405TMS JTGC405TRSTNEG C405JTGCAPTUREDR C405JTGEXTEST C405JTGPGMOUT C405JTGSHIFTDR C405JTGTDO C405JTGTDOEN C405JTGUPDATEDR => => => => => => => => => => => => JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, C405JTGCAPTUREDR, C405JTGEXTEST, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, -- Debug Interface DBGC405DEBUGHALT DBGC405EXTBUSHOLDACK DBGC405UNCONDDEBUGEVENT C405DBGMSRWE C405DBGSTOPACK C405DBGWBCOMPLETE C405DBGWBFULL C405DBGWBIAR => => => => => => => => DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405DBGWBIAR, www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block -- Trace Interface TRCC405TRACEDISABLE TRCC405TRIGGEREVENTIN C405TRCCYCLE C405TRCEVENEXECUTIONSTATUS C405TRCODDEXECUTIONSTATUS C405TRCTRACESTATUS C405TRCTRIGGEREVENTOUT C405TRCTRIGGEREVENTTYPE -- Special Interface MCBCPUCLKEN MCBJTAGEN MCBTIMEREN MCPPCRST ); => => => => => => => => TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN, C405TRCCYCLE, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405TRCTRACESTATUS, C405TRCTRIGGEREVENTOUT, C405TRCTRIGGEREVENTTYPE, => => => => MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST --Top 8 bits of DCR address space for DSOCM DCR registers. The DCR --address space is 10 bits wide. The two least significant bits are --predefined in DSOCM controller. --For example, -- if TIEDSOCMDCRADDR = 00 0001 11 -- then, address of DSARC = 00 0001 1110 = 0x01E -address of DSCNTL = 00 0001 1111 = 0x01F DSARCVALUE DSCNTLVALUE TIEDSOCMDCRADDR <= "<user defined value>"; <= "<user defined value>"; <= "<user defined value>"; --Top 8 bits of DCR address space for ISOCM DCR registers. The DCR --address space is 10 bits wide. The two least significant bits are --predefined in ISOCM controller. --For example, -- if TIEISOCMDCRADDR = 00 0010 11 -- then, address of ISINIT = 00 0010 1100 = 0x02C -address of ISFILL = 00 0010 1101 = 0x02D -address of ISARC = 00 0010 1110 = 0x02E -address of ISCNTL = 00 0010 1111 = 0x02F ISARCVALUE ISCNTLVALUE TIEISOCMDCRADDR <= "<user defined value>"; <= "<user defined value>"; <= "<user defined value>"; end arch; Verilog Template // Module: Proc_blk_template // Description: Verilog Module // Processor Block instantiation template // // Device: Virtex-II Pro Family //------------------------------------------------------------------module top ( // user defined port list ); // user defined port declaration UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 193 R Chapter 2: Design Considerations // Processor Block Instantiation /* -----------------------------------------------------------------The following convention is used for signal names throughout this document: PREFIX1PREFIX2SIGNAME1[SIGNAME1][NEG][(m:n)] The components of a signal name are as follows: * PREFIX1 is an uppercase prefix identifying the source of the signal. This prefix specifies either a unit (for example, CPU) or a type of interface (for example, DCR). If PREFIX1 specifies the processor block, the signal is considered an output signal. Otherwise, it is an input signal. * PREFIX2 is an uppercase prefix identifying the destination of the signal. This prefix specifies either a unit (for example, CPU) or a type of interface (for example, DCR). If PREFIX2 specifies the processor block, the signal is considered an input signal. Otherwise, it is an output signal. * SIGNAME1 is an uppercase name identifying the primary function of the signal. * [SIGNAME1] is an uppercase name identifying the primary function of the signal. * [NEG] is an optional notation that indicates a signal is active low. If this notation is not use, the signal is active high. * [m:n] is an optional notation that indicates a bused signal. "m" designates the most-significant bit of the bus and "n" designates the least-significant bit of the bus. The following table defines the prefixes used in the signal names. Prefix1/2 CPM C405 DBG DCR DSOCM EIC ISOCM JTG PLB RST TIE TRC XXX Definition Clock and power management Processor block Debug unit Device control register Data-side on-chip memory (DSOCM External interrupt controller Instruction-side on-chip memory (ISOCM) JTAG Processor local bus Reset TIE (signal tied statically to GND or VDD ) Trace FPGA unit Refer to Processor Block Manual for further interface descriptions. -------------------------------------------------------------------*/ PPC405 ProcessorBlock ( // Clock and Power management interface .CPMC405CLOCK ( .CPMC405CORECLKINACTIVE ( .CPMC405CPUCLKEN ( .CPMC405JTAGCLKEN ( 194 www.xilinx.com 1-800-255-7778 CPMC405CLOCK ), CPMC405CORECLKINACTIVE CPMC405CPUCLKEN ), CPMC405JTAGCLKEN ), ), UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block .CPMC405TIMERCLKEN .CPMC405TIMERTICK .C405CPMCORESLEEPREQ .C405CPMMSRCE .C405CPMMSREE .C405CPMTIMERIRQ .C405CPMTIMERRESETREQ ( ( ( ( ( ( ( CPMC405TIMERCLKEN ), CPMC405TIMERTICK ), C405CPMCORESLEEPREQ ), C405CPMMSRCE ), C405CPMMSREE ), C405CPMTIMERIRQ ), C405CPMTIMERRESETREQ ), // CPU Control Interface .TIEC405DETERMINISTICMULT .TIEC405DISOPERANDFWD .TIEC405MMUEN .C405XXXMACHINECHECK ( ( ( ( TIEC405DETERMINISTICMULT TIEC405DISOPERANDFWD ), TIEC405MMUEN ), C405XXXMACHINECHECK ), // Reset Interface .RSTC405RESETCHIP .RSTC405RESETCORE .RSTC405RESETSYS .C405RSTCHIPRESETREQ .C405RSTCORERESETREQ .C405RSTSYSRESETREQ ( ( ( ( ( ( RSTC405RESETCHIP ), RSTC405RESETCORE ), RSTC405RESETSYS ), C405RSTCHIPRESETREQ ), C405RSTCORERESETREQ ), C405RSTSYSRESETREQ ), // Processor Local Bus clock .PLBCLK ( PLBCLK ), ), // Instruction-side Processor Local Bus Interface .PLBC405ICUADDRACK ( PLBC405ICUADDRACK ), .PLBC405ICUBUSY ( PLBC405ICUBUSY ), .PLBC405ICUERR ( PLBC405ICUERR ), .PLBC405ICURDDACK ( PLBC405ICURDDACK ), .PLBC405ICURDDBUS ( PLBC405ICURDDBUS ), .PLBC405ICURDWDADDR ( PLBC405ICURDWDADDR ), .PLBC405ICUSSIZE1 ( PLBC405ICUSSIZE1 ), .C405PLBICUABORT ( C405PLBICUABORT ), .C405PLBICUABUS ( C405PLBICUABUS ), .C405PLBICUCACHEABLE ( C405PLBICUCACHEABLE ), .C405PLBICUPRIORITY ( C405PLBICUPRIORITY ), .C405PLBICUREQUEST ( C405PLBICUREQUEST ), .C405PLBICUSIZE ( C405PLBICUSIZE ), .C405PLBICUU0ATTR ( C405PLBICUU0ATTR ), // Data-side Processor Local Bus Interface .PLBC405DCUADDRACK ( PLBC405DCUADDRACK ), .PLBC405DCUBUSY ( PLBC405DCUBUSY ), .PLBC405DCUERR ( PLBC405DCUERR ), .PLBC405DCURDDACK ( PLBC405DCURDDACK ), .PLBC405DCURDDBUS ( PLBC405DCURDDBUS ), .PLBC405DCURDWDADDR ( PLBC405DCURDWDADDR ), .PLBC405DCUSSIZE1 ( PLBC405DCUSSIZE1 ), .PLBC405DCUWRDACK ( PLBC405DCUWRDACK ), .C405PLBDCUABORT ( C405PLBDCUABORT ), .C405PLBDCUABUS ( C405PLBDCUABUS ), .C405PLBDCUBE ( C405PLBDCUBE ), .C405PLBDCUCACHEABLE ( C405PLBDCUCACHEABLE ), .C405PLBDCUGUARDED ( C405PLBDCUGUARDED ), .C405PLBDCUPRIORITY ( C405PLBDCUPRIORITY ), .C405PLBDCUREQUEST ( C405PLBDCUREQUEST ), .C405PLBDCURNW ( C405PLBDCURNW ), .C405PLBDCUSIZE2 ( C405PLBDCUSIZE2 ), .C405PLBDCUU0ATTR ( C405PLBDCUU0ATTR ), .C405PLBDCUWRDBUS ( C405PLBDCUWRDBUS ), .C405PLBDCUWRITETHRU ( C405PLBDCUWRITETHRU ), UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 195 R Chapter 2: Design Considerations // Device Control Register Interface .DCRC405ACK .DCRC405DBUSIN .C405DCRABUS .C405DCRDBUSOUT .C405DCRREAD .C405DCRWRITE ( ( ( ( ( ( DCRC405ACK ), DCRC405DBUSIN ), C405DCRABUS ), C405DCRDBUSOUT ), C405DCRREAD ), C405DCRWRITE ), // External Interrupt Controller Interface .EICC405CRITINPUTIRQ ( EICC405CRITINPUTIRQ ), .EICC405EXTINPUTIRQ ( EICC405EXTINPUTIRQ ), 196 // On-Chip Memory Controller Interface .BRAMDSOCMCLK .BRAMDSOCMRDDBUS .BRAMISOCMCLK .BRAMISOCMRDDBUS .DSOCMBRAMABUS .DSOCMBRAMBYTEWRITE .DSOCMBRAMEN .DSOCMBRAMWRDBUS .DSOCMBUSY .ISOCMBRAMEN .ISOCMBRAMEVENWRITEEN .ISOCMBRAMODDWRITEEN .ISOCMBRAMRDABUS .ISOCMBRAMWRABUS .ISOCMBRAMWRDBUS .DSARCVALUE .DSCNTLVALUE .ISARCVALUE .ISCNTLVALUE .TIEDSOCMDCRADDR .TIEISOCMDCRADDR ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( BRAMDSOCMCLK ), BRAMDSOCMRDDBUS ), BRAMISOCMCLK ), BRAMISOCMRDDBUS ), DSOCMBRAMABUS ), DSOCMBRAMBYTEWRITE ), DSOCMBRAMEN ), DSOCMBRAMWRDBUS ), DSOCMBUSY ), ISOCMBRAMEN ), ISOCMBRAMEVENWRITEEN ), ISOCMBRAMODDWRITEEN ), ISOCMBRAMRDABUS ), ISOCMBRAMWRABUS ), ISOCMBRAMWRDBUS ), DSARCVALUE ), DSCNTLVALUE ), ISARCVALUE ), ISCNTLVALUE ), TIEDSOCMDCRADDR ), TIEISOCMDCRADDR ), // JTAG Interface .JTGC405BNDSCANTDO .JTGC405TCK .JTGC405TDI .JTGC405TMS .JTGC405TRSTNEG .C405JTGCAPTUREDR .C405JTGEXTEST .C405JTGPGMOUT .C405JTGSHIFTDR .C405JTGTDO .C405JTGTDOEN .C405JTGUPDATEDR ( ( ( ( ( ( ( ( ( ( ( ( JTGC405BNDSCANTDO ), JTGC405TCK ), JTGC405TDI ), JTGC405TMS ), JTGC405TRSTNEG ), C405JTGCAPTUREDR ), C405JTGEXTEST ), C405JTGPGMOUT ), C405JTGSHIFTDR ), C405JTGTDO ), C405JTGTDOEN ), C405JTGUPDATEDR ), // Debug Interface .DBGC405DEBUGHALT .DBGC405EXTBUSHOLDACK .DBGC405UNCONDDEBUGEVENT .C405DBGMSRWE .C405DBGSTOPACK .C405DBGWBCOMPLETE .C405DBGWBFULL .C405DBGWBIAR ( ( ( ( ( ( ( ( DBGC405DEBUGHALT ), DBGC405EXTBUSHOLDACK ), DBGC405UNCONDDEBUGEVENT ), C405DBGMSRWE ), C405DBGSTOPACK ), C405DBGWBCOMPLETE ), C405DBGWBFULL ), C405DBGWBIAR ), // Trace Interface .TRCC405TRACEDISABLE ( TRCC405TRACEDISABLE www.xilinx.com 1-800-255-7778 ), UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block .TRCC405TRIGGEREVENTIN .C405TRCCYCLE .C405TRCEVENEXECUTIONSTATUS .C405TRCODDEXECUTIONSTATUS .C405TRCTRACESTATUS .C405TRCTRIGGEREVENTOUT .C405TRCTRIGGEREVENTTYPE // Special Interface .MCBCPUCLKEN .MCBJTAGEN .MCBTIMEREN .MCPPCRST ); // OCM attribute signals wire [0:7] wire [0:7] wire [0:7] wire [0:7] wire [0:7] wire [0:7] ( TRCC405TRIGGEREVENTIN ), ( C405TRCCYCLE ), ( C405TRCEVENEXECUTIONSTATUS ), ( C405TRCODDEXECUTIONSTATUS ), ( C405TRCTRACESTATUS ), ( C405TRCTRIGGEREVENTOUT ), ( C405TRCTRIGGEREVENTTYPE ), ( ( ( ( MCBCPUCLKEN ), MCBJTAGEN ), MCBTIMEREN ), MCPPCRST ) TIEDSOCMDCRADDR; TIEISOCMDCRADDR; DSARCVALUE; DSCNTLVALUE; ISARCVALUE; ISCNTLVALUE; /* ---------------------------------------------------------------Top 8 bits of DCR address space for DSOCM DCR registers. The DCR address space is 10 bits wide. The two least significant bits are predefined in DSOCM controller. For example, if TIEDSOCMDCRADDR = 00 0001 11 then, address of DSARC = 00 0001 1110 = 0x01E address of DSCNTL= 00 0001 1111 = 0x01F -------------------------------------------------------------------*/ assign DSARCVALUE = <user_defined_value>; assign DSCNTLVALUE = <user_defined_value>; assign TIEDSOCMDCRADDR = <user_defined_value>; /*----------------------------------------------------------------Top 8 bits of DCR address space for ISOCM DCR registers. The DCR address space is 10 bits wide. The two least significant bits are predefined in ISOCM controller. For example, if TIEISOCMDCRADDR = 00 0010 11 then, address of ISINIT = 00 0010 1100 = 0x02C address of ISFILL = 00 0010 1101 = 0x02D address of ISARC = 00 0010 1110 = 0x02E address of ISCNTL = 00 0010 1111 = 0x02F --------------------------------------------------------------------*/ assign ISARCVALUE = 8'hFF; assign ISCNTLVALUE = 8'hFF; assign TIEISOCMDCRADDR = 8'b00_0010_11; endmodule //-------------------------------------------------------// Processor Block module declaration // This declaration can be omitted if not using Synplicity //-------------------------------------------------------module PPC405 ( BRAMDSOCMCLK, BRAMDSOCMRDDBUS, BRAMISOCMCLK, UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 197 R Chapter 2: Design Considerations BRAMISOCMRDDBUS, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGMSRWE, C405DBGSTOPACK, C405DCRABUS, C405DCRDBUSOUT, C405DBGWBIAR, C405DBGWBCOMPLETE, C405DBGWBFULL, C405DCRREAD, C405DCRWRITE, C405JTGCAPTUREDR, C405JTGEXTEST, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUABUS, C405PLBDCUBE, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUPRIORITY, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRDBUS, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUABUS, C405PLBICUCACHEABLE, C405PLBICUPRIORITY, C405PLBICUREQUEST, C405PLBICUSIZE, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE, C405TRCEVENEXECUTIONSTATUS, C405TRCTRACESTATUS, C405TRCTRIGGEREVENTOUT, C405TRCTRIGGEREVENTTYPE, C405TRCODDEXECUTIONSTATUS, C405XXXMACHINECHECK, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DCRC405ACK, DCRC405DBUSIN, 198 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block DSARCVALUE, DSCNTLVALUE, DSOCMBRAMABUS, DSOCMBRAMBYTEWRITE, DSOCMBRAMEN, DSOCMBRAMWRDBUS, DSOCMBUSY, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ, ISARCVALUE, ISCNTLVALUE, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, ISOCMBRAMWRDBUS, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCURDDBUS, PLBC405DCURDWDADDR, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICURDDBUS, PLBC405ICURDWDADDR, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN, TIEDSOCMDCRADDR, TIEISOCMDCRADDR ); // synthesis syn_black_box // Above Synplicity synthesis directive is needed for black box // instantiation // Port Declarations // See PowerPC 405 Processor Block Manual for detailed signal // descriptions. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 199 R Chapter 2: Design Considerations // Clock and Power Management Interface input CPMC405CLOCK; input CPMC405CORECLKINACTIVE; input CPMC405CPUCLKEN; input CPMC405JTAGCLKEN; input CPMC405TIMERCLKEN; input CPMC405TIMERTICK; output C405CPMCORESLEEPREQ; output C405CPMMSRCE; output C405CPMMSREE; output C405CPMTIMERIRQ; output C405CPMTIMERRESETREQ; // Processor Local Bus clock input PLBCLK; // Instruction Cache Unit Interface input PLBC405ICUADDRACK; input PLBC405ICUBUSY; input PLBC405ICUERR; input PLBC405ICURDDACK; input [0:63] PLBC405ICURDDBUS; input [1:3] PLBC405ICURDWDADDR; input PLBC405ICUSSIZE1; output C405PLBICUABORT; output [0:29] C405PLBICUABUS; output C405PLBICUCACHEABLE; output [0:1] C405PLBICUPRIORITY; output C405PLBICUREQUEST; output [2:3] C405PLBICUSIZE; output C405PLBICUU0ATTR; // Data Cache input input input input input [0:63] input [1:3] input input output output [0:31] output [0:7] output output output [0:1] output output output output output [0:63] output Unit Interface PLBC405DCUADDRACK; PLBC405DCUBUSY; PLBC405DCUERR; PLBC405DCURDDACK; PLBC405DCURDDBUS; PLBC405DCURDWDADDR; PLBC405DCUSSIZE1; PLBC405DCUWRDACK; C405PLBDCUABORT; C405PLBDCUABUS; C405PLBDCUBE; C405PLBDCUCACHEABLE; C405PLBDCUGUARDED; C405PLBDCUPRIORITY; C405PLBDCUREQUEST; C405PLBDCURNW; C405PLBDCUSIZE2; C405PLBDCUU0ATTR; C405PLBDCUWRDBUS; C405PLBDCUWRITETHRU; // Device Control Register Interface input DCRC405ACK; input [0:31] DCRC405DBUSIN; output [0:9] C405DCRABUS; output [0:31] C405DCRDBUSOUT; output C405DCRREAD; output C405DCRWRITE; 200 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Processor Block // On-Chip Memory Controller Interface input BRAMDSOCMCLK; input [0:31] BRAMDSOCMRDDBUS; input BRAMISOCMCLK; input [0:63] BRAMISOCMRDDBUS; output [8:29] DSOCMBRAMABUS; output [0:3] DSOCMBRAMBYTEWRITE; output DSOCMBRAMEN; output [0:31] DSOCMBRAMWRDBUS; output DSOCMBUSY; output ISOCMBRAMEN; output ISOCMBRAMEVENWRITEEN; output ISOCMBRAMODDWRITEEN; output [8:28] ISOCMBRAMRDABUS; output [8:28] ISOCMBRAMWRABUS; output [0:31] ISOCMBRAMWRDBUS; input [0:7] DSARCVALUE; input [0:7] DSCNTLVALUE; input [0:7] ISARCVALUE; input [0:7] ISCNTLVALUE; input [0:7] TIEDSOCMDCRADDR; input [0:7] TIEISOCMDCRADDR; // Debug Interface input DBGC405DEBUGHALT; input DBGC405EXTBUSHOLDACK; input DBGC405UNCONDDEBUGEVENT; output C405DBGMSRWE; output C405DBGSTOPACK; output C405DBGWBCOMPLETE; output C405DBGWBFULL; output [0:29] C405DBGWBIAR; // JTAG Interface input JTGC405BNDSCANTDO; input JTGC405TCK; input JTGC405TDI; input JTGC405TMS; input JTGC405TRSTNEG; output C405JTGCAPTUREDR; output C405JTGEXTEST; output C405JTGPGMOUT; output C405JTGSHIFTDR; output C405JTGTDO; output C405JTGTDOEN; output C405JTGUPDATEDR; // Trace Interface input TRCC405TRACEDISABLE; input TRCC405TRIGGEREVENTIN; output C405TRCCYCLE; output [0:1] C405TRCEVENEXECUTIONSTATUS; output [0:1] C405TRCODDEXECUTIONSTATUS; output [0:3] C405TRCTRACESTATUS; output C405TRCTRIGGEREVENTOUT; output [0:10] C405TRCTRIGGEREVENTTYPE; // Reset Interface input RSTC405RESETCHIP; input RSTC405RESETCORE; input RSTC405RESETSYS; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 201 R Chapter 2: Design Considerations output output output C405RSTCHIPRESETREQ; C405RSTCORERESETREQ; C405RSTSYSRESETREQ; // Interrupt Interface input EICC405CRITINPUTIRQ; input EICC405EXTINPUTIRQ; // CPU Control Interface input TIEC405DETERMINISTICMULT; input TIEC405DISOPERANDFWD; input TIEC405MMUEN; output C405XXXMACHINECHECK; // Special Interface input MCBCPUCLKEN; input MCBJTAGEN; input MCBTIMEREN; input MCPPCRST; endmodule Global Clock Networks Introduction Virtex-II Pro devices support very high frequency designs and thus require low-skew advanced clock distribution. With device density up to 10 million system gates, numerous global clocks are necessary in most designs. Therefore, to provide a uniform and portable solution (soft-IP), all Virtex-II Pro devices from XC2VP2 to XC2VP50 have 16 global clock buffers and support 16 global clock domains. Up to eight of these clocks can be used in any quadrant of the device by the synchronous logic elements (that is, registers, 18Kb block RAM, pipeline multipliers) and the IOBs. The software tools place and route these global clocks automatically. If the design uses between 8 and 16 clocks, it must be partitioned into quadrants, with up to 8 clocks per quadrant. If more than 16 clocks are required, the backbone (24 horizontal and vertical long lines routing resources) can be used as additional clock network. In addition to clock distribution, the 16 clock buffers are also "glitch-free" synchronous 2:1 multiplexers. These multiplexers are capable of switching between two asynchronous (or synchronous) clocks at any time. No particular phase relations between the two clocks are needed. The clock multiplexers can also be configured as a global clock buffer with a clock enable. The clock can be stopped High or Low at the clock buffer output. Clock Distribution Resources The various resources available to manage and distribute the clocks include: 202 * Sixteen clock pads that can be used as regular user I/Os if not used as clock inputs. The sixteen clock pads can be configured for any I/O standard, including differential standards (for example, LVDS). * Sixteen "IBUFG" elements that represent the clock inputs in a VHDL or Verilog design. * Eight "IBUFGDS" elements (that is, attributes LVDS_25, LDT_25, or ULVDS_25) that represent the differential clock input pairs in a VHDL or Verilog design. Each IBUFGDS replaces two IBUFG elements. * Four to eight Digital Clock Managers (DCMs), depending on the device size, to de- www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks skew and generate the clocks. For more information on DCMs, see Digital Clock Managers (DCMs), page 222. * Sixteen "BUFGMUX" elements that can consist of up to sixteen global clock buffers (BUFG), global clock buffers with a clock enable (BUFGCE), or global clock multiplexers (BUFGMUX). Figure 2-2 illustrates the placement of these clock resources in Virtex-II Pro devices (the XC2VP20 through the XC2VP50) that have eight DCMs. 8 GCLK Pads User I/Os User I/Os IBUFG IBUFG 8 BUFGMUX DCM BRAM Multiplier CLB DCM DCM DCM BRAM Multiplier BRAM Multiplier CLB BRAM Multiplier BRAM Multiplier CLB BRAM Multiplier 16 Clock Domains BRAM Multiplier DCM CLB BRAM Multiplier DCM DCM DCM 8 BUFGMUX IBUFG IBUFG User I/Os User I/Os 8 GCLK Pads Figure 2-2: UG002_C2_092_120100 Clock Resources in Virtex-II Pro Devices The simple scheme to distribute an external clock in the device is to implement a clock pad with an IBUFG input buffer connected to a BUFG global buffer, as shown in Figure 2-3 and Figure 2-4, page 204. The primary (GCLKP) and secondary (GCLKS) clock pads have no relationship with the P-side and N-side of differential clock inputs. In banks 0 and 1, the GCLKP corresponds to the N-side, and the GCLKS corresponds to the P-side of a differential clock input. In banks 4 and 5, this correspondence is reversed. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 203 R Chapter 2: Design Considerations IBUFG GCLK I O I PAD BUFG Clock Distribution O Clock Input IBUFGDS GCLKP P I GCLKS N IB BUFG I O Differential Clock Input Clock Distribution O (Bank 4 and 5 Scheme) UG002_C2_084_080601 Figure 2-3: Simple Clock Distribution (Bank 0 and 1 Scheme) . IBUFG GCLK I O I PAD BUFG Clock Distribution O Clock Input IBUFGDS GCLKS P I GCLKP N IB BUFG I O Clock Distribution (Bank 0 and 1 Scheme) UG002_C2_105_080601 O Differential Clock Input Figure 2-4: Simple Clock Distribution (Bank 0 and 1 Scheme) Major synthesis tools automatically infer the IBUFG and BUFG when the corresponding input signal is used as a clock in the VHDL or Verilog code. A high frequency or adapted (frequency, phase, and so forth) clock distribution with low skew is implemented by using a DCM between the output of the IBUFG and the input of the BUFG, as shown in Figure 2-5. Digital Clock Managers (DCMs), page 222 provides details about DCMs and their use. DCM IBUFG GCLK Pad I O BUFG CLKIN CLX0 I O Clock Distribution CLKFB UG002_C2_085_120200 Figure 2-5: Clock Distribution with DCM Clock distribution from internal sources is also possible with a BUFG only or with a DCM, as shown in Figure 2-6, page 205. 204 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks BUFG Logic I Clock Distribution O DCM BUFG Logic CLKIN CLXO I Clock Distribution O CLKFB UG002_C2_086_120200 Figure 2-6: Internal Logic Driving Clock Distribution Global Clock Inputs The clock buffer inputs are fed either by one of the 16 clock pads (refer to the Virtex-II Pro Data Sheet), by the outputs of the DCM, or by local interconnect. Each clock buffer can be a synchronous "glitch-free" 2:1 multiplexer with two clock inputs and one select input. Internal logic (or alternatively a regular IOB) can feed the clock inputs. Any internal or external signal can drive the select input or clock enable input. The possible inputs driving a global clock buffer or multiplexer are summarized in Table 2-10. Table 2-10: Inputs Driving Global Clock Buffers or DCMs Destination Source BUFG(I) or BUFGCE(I) BUFGCE (CE) BUFGMUX (I0 or I1) BUFGMUX (S) DCM (CLKIN) External Clock via IBUFG(O) Dedicated in same quadrant1 NA Dedicated in same quadrant1 NA Same edge DCM Clock Outputs Same edge (top or bottom)2 NA Same edge (top or bottom)2 NA General interconnect3 Internal Logic General interconnect General interconnect General interconnect General interconnect General interconnect3 User I/O Pad via IBUF(O) (not IBUFG) General interconnect General interconnect General interconnect General interconnect General interconnect3 NA NA NA NA Global clock net NA NA General interconnect NA Global clock net BUFG(O) BUFGMUX(O) Notes: 1. Not all IBUFGs in the quadrant have a dedicated connection to a specific BUFG. Others would require general interconnect to be hooked up. 2. Same edge (top or bottom) enables use of dedicated routing resources. 3. Pad to DCM input skew is not compensated. All BUFG (BUFGCE, BUFGMUX) outputs are available at the quadrant boundaries. The output of the global clock buffer can be routed to non-clock pins. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 205 R Chapter 2: Design Considerations Primary and Secondary Global Multiplexers Each global clock buffer is a self-synchronizing circuit called a clock multiplexer. The 16 global clock buffers or multiplexers are divided as follows: * * Eight primary clock multiplexers Eight secondary clock multiplexers No hardware difference exists between a primary and a secondary clock multiplexer. However, some restrictions apply to primary/secondary multiplexers, because they share input connections, as well as access to a quadrant. Each Virtex-II Pro device is divided into four quadrants: North-West, South-West, NorthEast, and South-East. Each quadrant has two primary and two secondary clock multiplexers. The clock multiplexers are indexed 0 to 7, with one primary and one secondary for each index, alternating on the top and on the bottom (i.e., clock multiplexer "0P" at the bottom is facing clock multiplexer "0S" at the top). In each device, the eight top/bottom clock multiplexers are divided into four primary and four secondary, indexed 0 to 7, as shown in Figure 2-7. 7P 7S 6S 6P 5P 4S 3P 2S NW NE SW SE 5S 4P 3S 2P 1P 0S 1S 0P BUFGMUX BUFGMUX UG002_C2_087_113000 Figure 2-7: Primary and Secondary Clock Multiplexer Locations 206 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks Primary/Secondary: Rule 1 Considering two "facing" clock multiplexers (BUFG#P and BUFG#S), one or the other of these clock outputs can enter any quadrant of the chip to drive a clock within that quadrant, as shown in Figure 2-8. Note that the clock multiplexers "xP" and "xS" compete for quadrant access. For example, BUFG0P output cannot be used in the same quadrant as BUFG0S. 1P 0S NW NE SW SE 1S 0P UG002_C2_088_113000 Figure 2-8: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Facing BUFG#P and BUFG#S Connections www.xilinx.com 1-800-255-7778 207 R Chapter 2: Design Considerations Primary/Secondary: Rule 2 In a BUFGCE or BUFGMUX configuration, shared inputs have to be considered. Any two adjacent clock multiplexers share two inputs, as shown in Figure 2-9. The clock multiplexer "1P" and "0S" have common I0/I1 and I1/I0 inputs. I1 S I0 BUFGMUX 1P I1 I0 BUFGMUX 0S S O O UG002_C2_089_113000 Figure 2-9: Clock Multiplexer Pair Sharing Clock Multiplexer Inputs Table 2-11 lists the clock multiplexer pairs in any Virtex-II Pro device. The primary multiplexer inputs I1/I0 are common with the corresponding secondary multiplexer inputs I0/I1 (i.e., Primary I1 input is common with secondary I0 input, and primary I0 input is common with secondary I1 input). Table 2-11: Primary I1/I0 1P 3P 5P 7P Secondary I0/I1 0S 2S 4S 6S Table 2-12: 208 Top Clock Multiplexer Pairs Bottom Clock Multiplexer Pairs Primary I1/I0 0P 2P 4P 6P Secondary I0/I1 1S 3S 5S 7S www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks Primary/Secondary Usage For up to eight global clocks, it is safe to use the eight primary global multiplexers (1P, 3P, 5P, 7P on the top and 0P, 2P, 4P, 6P on the bottom). Because of the shared inputs, a maximum of eight independent global clock multiplexers can be used in a design, as shown in Figure 2-10. GCLK5P GCLK7P GCLK1P GCLK3P IBUFG/IBUFGDS 7P 5P 3P 1P NW NE 8 clocks 8 clocks 8 8 8 clocks 8 8 8 clocks 8 clocks SW SE 6P 4P 2P 0P IBUFG/IBUFGDS GCLK6P GCLK4P GCLK2P GCLK0P UG002_C2_090_113000 Figure 2-10: Eight Global Clocks Design DCM Clocks The four clock pins (IBUFG) in a quadrant can feed all DCMs in the same edge of the device. The clock-to-out and setup times are identical for all DCMs. Up to four clock outputs per DCM can be used to drive any clock multiplexer on the same edge (top or bottom), as shown in Figure 2-11. BUFG Exclusivity Each DCM has a restriction on the number of BUFGs it can drive on its (top or bottom) edge. Pairs of buffers with shared dedicated routing resources exist such that only one buffer from each dedicated pair can be driven by a single DCM. The exclusive pairs for each edge are: 1:5, 2:6, 3:7, and 4:8. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 209 R Chapter 2: Design Considerations GCLK7P GCLK6S GCLK5P GCLK4S GCLK3P GCLK2S GCLK1P GCLK0S IBUFG DCM 4 DCM 4 IBUFG DCM DCM 4 4 8 BUFGMUX DCM 7P 4 DCM 4 8 6S 5P 4S 3P 2S 1P 0S BUFGMUX UG002_C2_091_080601 Figure 2-11: DCM Clocks Clock Output The clock distribution is based on eight clock trees per quadrant. Each clock multiplexer output is driving one global clock net. The Virtex-II Pro device has eight dedicated lowskew clock nets. The device is divided into four quadrants (NW, NE, SW and SE) with eight global clocks available per quadrant. Eight clock buffers are in the middle of the top edge and eight are in the middle of the bottom edge. Any of these 16 clock buffer outputs can be used in any quadrant, up to a maximum of eight clocks per quadrant, as illustrated in Figure 2-12, provided there is not a primary vs. secondary conflict. 8 BUFGMUX NE NW NW 8 BUFGMUX NE 8 8 8 max 16 Clocks 16 Clocks 8 SW 8 BUFGMUX SE 8 SE SW 8 BUFGMUX Figure 2-12: 210 DS031_45_120200 Clock Buffer Outputs per Quadrant www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks Designs with more than eight clocks must be floorplanned manually or automatically, distributing the clocks in each quadrant. As an example, a design with 16 clocks can be floorplanned as shown in Figure 2-13. CLK_ A B C D E F G H NW NE 7S 7P CLK_A 5P 0S CLK_I CLK_H CLK_C 6S 2P 6S CLK_B 3P CLK_B CLK_N CLK_E 2S CLK_F 4S 0P 5S CLK_D CLK_P 5 clocks CLK_K 1S 8 clocks CLK_O 16 Clocks 1P 7P CLK_A 0S CLK_H 7P CLK_G 3S CLK_M CLK_A 5P 6P CLK_C CLK_J 0P 4P CLK_L CLK_P 2P CLK_N 7 clocks 3 clocks SW SE CLK_ I J K L M N O P UG002_C2_079_120200 Figure 2-13: 16-Clock Floorplan The clock nets and clock buffers in this example are associated as shown in Table 2-13. Table 2-13: Clock Net Association With Clock Buffers Clock Net (top edge) BUFG Clock Net (bottom edge) BUFG CLK_A CLK_B CLK_C CLK_D CLK_E CLK_F CLK_G CLK_H 7P 6S 5P 4S 3P 2S 1P 0S CLK_I CLK_J CLK_K CLK_L CLK_M CLK_N CLK_O CLK_P 7S 6P 5S 4P 3S 2P 1S 0P Quadrant NW CLK_A CLK_B CLK_C - - CLK_F - CLK_P Quadrant SW CLK_A - CLK_C CLK_L CLK_M CLK_N CLK_G CLK_H Quadrant NE CLK_I CLK_B CLK_K CLK_D CLK_E CLK_N CLK_O CLK_H Quadrant SE CLK_A CLK_J - - - - - CLK_P UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 211 R Chapter 2: Design Considerations CLK_A is used in three quadrants, and the other clocks are used in one or two quadrants, regardless of the position of the clock buffers (multiplexers), as long as they are not competing to access the same quadrant. (That is, CLK_A (BUFG7P) cannot be used in the same quadrant with CLK_I (BUFG7S). Refer to Primary/Secondary: Rule 1, page 207.) In other words, two buffers with the same index (0 to 7) cannot be used in the same quadrant. Each register, block RAM, registered multiplier, or DDR register (IOB) can be connected to any of the eight clock nets available in a particular quadrant. Note that if a global clock (primary buffer) is used in four quadrants, the corresponding secondary buffer is not available. Power Consumption Clock trees have been designed for low skew and low-power operation. Any unused branch is disconnected, as shown in Figure 2-14. 8 BUFGMUX 2 2 2 2 6 NW 6 4 16 Clocks 1 2 SE SW 8 BUFGMUX Figure 2-14: ug002_c2_093_113000 Low-Power Clock Network Also available to reduce overall power consumption are the BUFGCE feature, for dynamically driving a clock tree only when the corresponding module is used, and the BUFGMUX feature, for switching from a high-frequency clock to a low-frequency clock. The frequency synthesizer capability of the DCM can generate the low (or high) frequency clock from a single source clock, as illustrated in Figure 2-15. (See Digital Clock Managers (DCMs), page 222). DCM BUFGMUX 250 MHz CLKIN CLK0 250 MHz I0 CLKFB (/10) CLKDV Clock Tree 25 MHz I1 S BUFG UG002_C2_094_121101 Figure 2-15: Dynamic Power Reduction Scheme 212 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks Library Primitives and Submodules The primitives in Table 2-14 are available with the input, output, and control pins listed. Table 2-14: Clock Primitives Primitive Input Output Control I O - I, IB O - I O - BUFGMUX I0, I1 O S BUFGMUX_1 I0, I1 O S IBUFG IBUFGDS BUFG Refer to Single-Ended SelectI/O Resources, page 303 for a list of the attributes available for IBUFG and Refer to LVDS I/O, page 363 for a list of the attributes available for IBUFGDS. The submodules in Table 2-15 are available with the input, output, and control pins listed. Table 2-15: Clock Submodules Submodule Input Output Control BUFGCE I O CE BUFGCE_1 I O CE Primitive Functions IBUFG IBUFG is an input clock buffer with one clock input and one clock output. IBUFGDS IBUFGDS is a differential input clock buffer with two clock inputs (positive and negative polarity) and one clock output. BUFG All Virtex-II Pro devices have 16 global clock buffers (each of which can be used as BUFG, BUFGMUX, or BUFGCE). BUFG is a global clock buffer with one clock input and one clock output, driving a lowskew clock distribution network. The output follows the input, as shown in Figure 2-16. BUFG(I) BUFG(O) UG002_C2_099_120100 Figure 2-16: BUFG Waveforms BUGMUX and BUFGMUX_1 BUFGMUX (see Figure 2-17) can switch between two unrelated, even asynchronous clocks. Basically, a Low on S selects the I0 input, a High on S selects the I1 input. Switching from one clock to the other is done in such a way that the output High and Low time is never shorter than the shortest High or Low time of either input clock. As long as the presently selected clock is High, any level change of S has no effect . UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 213 R Chapter 2: Design Considerations BUFGMUX is the preferred circuit for rising edge clocks, while BUFGMUX_1 is preferred for falling edge clocks. BUFGMUX I0 I1 O S DS083-2_63_121701 Figure 2-17: Virtex-II Pro BUFGMUX or BUFGMUX_1 Function Operation of the BUFGMUX Circuit If the presently selected clock is Low while S changes, or if it goes Low after S has changed, the output is kept Low until the other ("to-be-selected") clock has made a transition from High to Low. At that instant, the new clock starts driving the output. The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock; that is, prior to the rising edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output. Figure 2-18 shows a switchover from CLK0 to CLK1. Wait for Low S CLK0 Switch CLK1 Out DS083-2_46_121701 Figure 2-18: BUFGMUX Waveform Diagram * * * * The current clock is CLK0. * * When CLK1 transitions from High to Low, the output switches to CLK1. S is activated High. If CLK0 is currently High, the multiplexer waits for CLK0 to go Low. Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to Low. No glitches or short pulses can appear on the output. Operation of the BUFGMUX_1 Circuit If the presently selected clock is High while S changes, or if it goes High after S has changed, the output is kept High until the other ("to-be-selected") clock has made a transition from Low to High. At that instant, the new clock starts driving the output. The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the falling edge of the presently selected clock; that is, prior to the falling edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output. 214 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks Figure 2-19 shows a switchover from CLK0 to CLK1. Wait for High S CLK0 CLK1 Out DS083-2_46a_121701 Figure 2-19: BUFGMUX_1 Waveform Diagram * * * * The current clock is CLK0. * * When CLK1 transitions from Low to High, the output switches to CLK1. S is activated High. If CLK0 is currently Low, the multiplexer waits for CLK0 to go High. Once CLK0 is High, the multiplexer output stays High until CLK1 transitions Low to High. No glitches or short pulses can appear on the output. Submodules BUFGCE and BUFGCE_1 BUFGCE and BUFGCE_1 are submodules based on BUFGMUX and BUFGMUX_1, respectively. BUFGCE and BUFGCE_1 are global clock buffers incorporating a smart enable function that avoids output glitches or runt pulses. The select signal must meet the setup time for the clock. BUFGCE is the preferred circuit for clocking on the rising edge, while BUFGCE_1 is preferred when clocking on the falling edge. Operation of the BUFGCE Circuit If the CE input (see Figure 2-20) is active (High) prior to the incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through the clock buffer. Any level change of CE during the incoming clock High time has no effect. BUFGCE I O CE DS031_62_101200 Figure 2-20: Virtex-II Pro BUFGCE or BUFGCE_1 Function If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High time has no effect. CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 215 R Chapter 2: Design Considerations This means the output stays Low when the clock is disabled, but it completes the clockHigh pulse when the clock is being disabled, as shown in Figure 2-21. BUFGCE(I) BUFGCE(CE) Wait Low BUFGCE(O) Clock Stops Low UG002_C2_100_120100 Figure 2-21: BUFGCE Waveforms Operation of the BUFGCE_1 circuit If the CE input is active (High) prior to the incoming falling clock edge, this High-to-Lowto-High clock pulse passes through the clock buffer. Any level change of CE during the incoming clock Low time has no effect. If the CE input is inactive (Low) prior to the incoming falling clock edge, the following clock pulse does not pass through the clock buffer, and the output stays High. Any level change of CE during the incoming clock Low time has no effect. CE must not change during a short setup window just prior to the falling clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output. This means the output stays High when the clock is disabled, but it completes the clockLow pulse when the clock is being disabled, as shown in Figure 2-22. BUFGCE_1(I) BUFGCE_1(CE) BUFGCE_1(O) Switch High Figure 2-22: Clock Stops High UG002_C2_101_120100 BUFGCE_1 Waveforms When BUFGCE (or BUFGCE_1) is used with DCM outputs, a second BUFG can be used for clock feedback. Buffer sharing the inputs with BUFGCE is the preferred solution. Summary Table 2-16 shows the maximum resources available per Virtex-II Pro device. Table 2-16: Resources per Virtex-II Pro Device (from XC2VP2 to XC2VP50) Resource Maximum Number Single-ended IBUFG (pads) 16 Differential IBUFGDS (pairs) 8 BUFG (Global Clock Buffer) 16 BUFGCE (or BUFGCE_1) 8 BUFGMUX (or BUFGMUX_1) 8 Characteristics The following are characteristics of global clocks in Virtex-II Pro devices: * * 216 Low-skew clock distribution. Synchronous "glitch-free" multiplexer that avoids runt pulses. Switching between two asynchronous clock sources is usually considered unsafe, but it is safe with the Virtex-II Pro global clock multiplexer. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks * Any level change on S must meet a setup time requirement with respect to the signal on the output O (rising edge for BUFGMUX, falling edge for BUFGMUX_1). Any level change on CE must meet a setup time requirement with respect to the signal on the Input I (rising edge for BUFGCE, falling edge for BUFGCE_1). * Two BUFGMUX (or BUFGMUX_1) resources can be cascaded to create a 3 to 1 clock multiplexer. Location Constraints BUFGMUX and BUFGMUX_1 (primitives) and IBUFG (IBUFGDS) instances can have LOC properties attached to them to constrain placement. The LOC properties use the following form to constrain a clock net: NET "clock_name" LOC="BUFGMUX#P/S"; Each clock pad (or IBUFG) has a direct connection with a specific global clock multiplexer (input I0). A placement that does not conform to this rule causes the software to send a warning. If the clock pad (or IBUFG) has LOC properties attached, the DCM allows place and route software maximum flexibility, as compared to a direct connection to the global clock buffer (BUFG). Secondary Clock Network If more clocks are required, the 24 horizontal and vertical long lines in Virtex-II Pro devices can be used to route additional clock nets. Skew is minimized by the place and route software, if the USELOWSKEWLINES constraint is attached to the net. VHDL and Verilog Instantiation VHDL and Verilog instantiation templates are available as examples (see "The following are templates for primitives:" on page 217) for all primitives and submodules. In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. The following are templates for primitives: * * BUFGMUX_INST * * BUFGCE_SUBM BUFGMUX_1_INST The following are templates for submodules: BUFGCE_1_SUBM As examples, the BUFGMUX_INST.vhd, BUFGMUX_1_INST.vhd, BUFGCE_SUBM.vhd, and BUFGCE_1_SUBM.vhd VHDL templates are shown. In addition, the BUFGMUX_INST.v, BUFGMUX_1_INST.v, BUFGCE_1_SUBM.v, and BUFGCE_SUBM.v Verilog templates are shown. VHDL Template -- Module: BUFGMUX_INST -- Description: VHDL instantiation template -- Global Clock Multiplexer (Switch Low) -- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Component Declarations: -component BUFGMUX port ( UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 217 R Chapter 2: Design Considerations I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- Architecture section: --- Global Clock Buffer Instantiation U_BUFGMUX: BUFGMUX port map ( I0 => , -- insert clock input used when select (S) is Low I1 => , -- insert clock input used when select (S) is High S => , -- insert Mux-Select input O => -- insert clock output ); ----------------------------------------------------------------------- Module: BUFGMUX_1_INST -- Description: VHDL instantiation template -- Global Clock Multiplexer (Switch High) --- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Component Declarations: component BUFGMUX_1 port ( I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- Architecture section: --- Global Clock Buffer Instantiation U_BUFGMUX_1: BUFGMUX_1 port map ( I0 => , -- insert clock input used when select (S) is Low I1 => , -- insert clock input used when select (S) is High S => , -- insert Mux-Select input O => -- insert clock output ); ----------------------------------------------------------------------- Module: BUFGCE_SUBM -- Description: VHDL instantiation template -- Global Clock Buffer with Clock Enable: -- Input Clock Buffer to BUFGMUX - Clock disabled = Low -- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity BUFGCE_SUBM is 218 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks port ( I: in std_logic; CE: in std_logic; O: out std_logic ); end BUFGCE_SUBM; -architecture BUFGCE_SUBM_arch of BUFGCE_SUBM is --- Component Declarations: component BUFGMUX port ( I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- signal declarations signal GND : std_logic; signal CE_B : std_logic; -begin GND <= '0'; -CE_B <= not CE; --- Global Clock Buffer Instantiation U_BUFGMUX: BUFGMUX port map ( I0 => I, I1 => GND, S => CE_B, O => O ); -end BUFGCE_SUBM_arch; ---------------------------------------------------------------------- Module: BUFGCE_1_SUBM -- Description: VHDL instantiation template -- Global Clock Buffer with Clock Enable: -- Input Clock Buffer to BUFGMUX_1 - Clock disabled = High -- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity BUFGCE_1_SUBM is port ( I: in std_logic; CE: in std_logic; O: out std_logic ); end BUFGCE_1_SUBM; -architecture BUFGCE_1_SUBM_arch of BUFGCE_1_SUBM is UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 219 R Chapter 2: Design Considerations --- Component Declarations: component BUFGMUX_1 port ( I0 : in std_logic; I1 : in std_logic; S : in std_logic; O : out std_logic ); end component; --- signal declarations signal VCC : std_logic; -signal CE_B : std_logic; -begin VCC <= '1'; -CE_B <= not CE; --- Global Clock Buffer Instantiation U_BUFGMUX_1: BUFGMUX_1 port map ( I0 => I, I1 => VCC, S => CE_B, O => O ); -end BUFGCE_1_SUBM_arch; Verilog Template //------------------------------------------------------------------// Module: BUFGMUX_INST // Description: Verilog Instantiation Template // Global Clock Multiplexer (Switch Low) // // // Device: Virtex-II Pro Family //------------------------------------------------------------------// //BUFGMUX Instantiation BUFGMUX U_BUFGMUX (.I0(), // insert clock input used when select(S) is Low .I1(), // insert clock input used when select(S) is High .S(), // insert Mux-Select input .O() // insert clock output ); //------------------------------------------------------------------// Module: BUFGMUX_1_INST // Description: Verilog Instantiation Template // Global Clock Multiplexer (Switch High) // // // Device: Virtex-II Pro Family //------------------------------------------------------------------// //BUFGMUX_1 Instantiation BUFGMUX_1 U_BUFGMUX_1 (.I0(), // insert clock input used when select(S) is Low 220 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Global Clock Networks .I1(), // insert clock input used when select(S) is High .S(), // insert Mux-Select input .O() // insert clock output ); //------------------------------------------------------------------// Module: BUFGCE_SUBM // Description: Verilog Submodule // Global Clock Buffer with Clock Enable: // Input Clock Buffer to BUFGMUX - Clock disabled = Low // // Device: Virtex-II Pro Family //------------------------------------------------------------------module BUFGCE_SUBM (I, CE, O); input I, CE; output O; wire GND; assign GND = 1'b0; BUFGMUX U_BUFGMUX (.I0(I), .I1(GND), .S(~CE), .O(O) ); // endmodule //------------------------------------------------------------------// Module: BUFGCE_1_SUBM // Description: Verilog Submodule // Global Clock Buffer with Clock Enable: // Input Clock Buffer to BUFGMUX_1 - Clock disabled = High // // Device: Virtex-II Pro Family //------------------------------------------------------------------module BUFGCE_1_SUBM (I, CE, O); input I, CE; output O; wire VCC; assign VCC = 1'b1; BUFGMUX_1 U_BUFGMUX_1 (.I0(I), .I1(VCC), .S(~CE), .O(O) ); // endmodule UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 221 R Chapter 2: Design Considerations Digital Clock Managers (DCMs) Overview Virtex-II Pro devices have four to eight DCMs, and each DCM provides a wide range of powerful clock management features: * Clock De-skew: The DCM contains a digitally-controlled feedback circuit (delaylocked loop) that can completely eliminate clock distribution delays. Clock de-skew works as follows: The incoming clock drives a long chain of delay elements (individual small buffers). A wide multiplexer selects any one of these buffers as an output. A controller drives the select inputs of this multiplexer. The phase detector in this controller compares the incoming clock signal (CLKIN) against a feedback input (CLKFB), which must be another version of the same clock signal, usually from the far end of the internal clock distribution network (but it can also be from an output pin). The phase detector steers the controller to adjust the tap selection, and thus the through-delay in the DCM, in such a way that the two inputs to the phase comparator coincide.( This is a typical servo loop.) The tap controller adds exactly the right amount of delay to the clock distribution network to give it a total delay of one full clock period. For a repetitive clock signal, this effectively eliminates the clock distribution delay completely. * Frequency Synthesis: Separate outputs provide a doubled frequency (CLK2X and CLK2X180). Another output (CLKDV) provides a frequency that is a specified fraction of the input frequency (/1.5, /2, /2.5, and so forth, up to /15 and /16.) Two other outputs (CLKFX and CLKFX180) provide an output frequency that is derived from the input clock by simultaneous frequency division and multiplication. The user can specify any integer multiplier (M) and divisor (D) within the range specified in the DCM Timing Parameters section of the Virtex-II Pro Data Sheet. An internal calculator figures out the appropriate tap selection, so that the output edge coincides with the input clock whenever that is mathematically possible. For example, M=9 and D=5, multiply the frequency by 1.8, and the output rising edge is coincident with the input rising edge every 5 input periods = every 9 output periods. * Phase Shifting: Three outputs drive the same frequency as CLK0 but are delayed by 1/4, 1/2, and 3/4 of a clock period. An additional control optionally shifts all nine clock outputs by a fixed fraction of the clock period (defined during configuration, and described in multiples of the clock period divided by 256). The user can also dynamically and repetitively move the phase forwards or backwards by one unit of the clock period divided by 256. Note that any such phase shift is always invoked as a specific fraction of the clock period, but is always implemented by moving delay taps with a resolution of DCM_TAP (see DCM Timing Parameters in the Virtex-II Pro Data Sheet). * 222 General Control Signals: The RST input, when High, resets the entire DCM. The LOCKED output is High when all enabled DCM circuits have locked. The active High STATUS outputs indicate the following: - Phase Shift Overflow (STATUS[0]) - CLKIN Stopped (STATUS[1]) - CLKFX Stopped (STATUS[2]) www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) Clock De-Skew The Virtex-II Pro Digital Clock Manager (DCM) offers a fully digital, dedicated on-chip deskew circuit providing zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These features can be used to implement several circuits that improve and simplify system level design. Any four of the nine outputs of the DCM can be used to drive a global clock network. All DCM outputs can drive general interconnect at the same time; for example, DCM output can be used to generate board-level clocks. The well-buffered global clock distribution network minimizes clock skew caused by loading differences. By monitoring a sample of the output clock (CLK0 or CLK2X), the de-skew circuit compensates for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device. Figure 2-23 shows all of the inputs and outputs relevant to the DCM de-skew feature. DCM CLKIN CLKFB CLK0 RST LOCKED STATUS[7:0] clock signal control signal DS031_67a_101101 Figure 2-23: Clock De-Skew Outputs The de-skew feature can also act as a clock mirror. By driving the CLK0 or CLK2X output off-chip and then back in again, the de-skew feature can be used to de-skew a board-level clock serving multiple devices. By taking advantage of the de-skew circuit to remove on-chip clock delay, the designer can greatly simplify and improve system level design involving high-fanout, highperformance clocks. Operation A de-skew circuit in its simplest form consists of variable delay line and control logic. The delay line produces a delayed version of the input clock (CLKIN). The clock distribution network routes the clock to all internal registers and to the clock feedback CLKFB pin. The control logic samples the input clock, as well as the feedback clock, and adjusts the delay line. For optimum performance, the Virtex-II Pro DCM uses a discrete digital delay line, which is a series of buffer elements each with an intrinsic delay of less than DCM_TAP (see AC characteristics in the Virtex-II Pro Data Sheet). A de-skew circuit works by inserting delay between the input clock and the feedback clock until the two rising edges align, putting the two clocks 360 degrees out of phase, which means they are in phase. When the edges from the input clock line up with the edges from the feedback clock, the DCM achieves "lock." The two clocks have no discernible UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 223 R Chapter 2: Design Considerations difference. Thus, the DCM output clock compensates for the delay in the clock distribution network, effectively removing the delay between the source clock and its loads. Input Clock Requirements The clock input of the DCM can be driven either by an IBUFG, an IBUF, or a BUFGMUX. An LVDS clock can also be used as input. The output clock signal of a DCM, essentially a delayed version of the input clock signal, reflects any instability on the input clock in the output waveform. A DCM cannot improve the input jitter. The DCM input clock requirements are specified in the Virtex-II Pro Data Sheet. Once locked, the DCM can tolerate input clock period variations of up to the value specified by CLKIN_CYC_JITT_DLL_HF (at high frequencies) or CLKIN_CYC_JITT_DLL_LF (at low frequencies). Larger frequency changes can cause the DCM to lose lock, which is indicated by the LOCKED output going low. The user must then reset the DCM. The cycle-to-cycle input jitter must be kept to less than CLKIN_PER_JITT_DLL_LF in the low frequencies and CLKIN_PER_JITT_DLL_HF for the high frequencies. Input Clock Changes Changing the period of the input clock beyond the maximum drift amount requires a manual reset of the DCM. Failure to reset the DCM produces an unreliable lock signal and output clock. It is possible to stop the input clock with little impact to the de-skew circuit. The clock should be stopped for no more than 100 ms to minimize the effect of device cooling, which would change the tap delays. The clock should be stopped during a Low phase, and when restored, must generate a full High half-period. During this time, LOCKED stays High and remains High when the clock is restored. So a High on LOCKED does not necessarily mean that a valid clock is available. When the clock is being stopped, one to four more clock cycles are still generated as the delay line is flushed. When the clock is restarted, the output clock cycles are not generated for one to four clocks as the delay line is filled. The most common case is two or three clocks. In a similar manner, a phase shift of the input clock is also possible. The phase shift propagates to the output one to four clocks after the original shift, with no disruption to the DCM control. Output Clocks Some restrictions apply regarding the connectivity of the output pins. The DCM clock outputs can each drive an OBUF, a global clock buffer BUFGMUX, or they can route directly to the clock input of a synchronous element. The DCM clock outputs can drive BUFGMUXs that are on the same edge of the device (top or bottom). Do not use the DCM output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. Characteristics of the De-skew Circuit 224 * Can eliminate clock distribution delay by effectively adding one clock period delay. Clocks are de-skewed to within CLKOUT_PHASE, specified in the Virtex-II Pro Data Sheet. * * * * Can be used to eliminate on-chip as well as off-chip clock delay. * De-skew circuit is part of the DCM, which also includes phase adjustment, frequency synthesis, and spread spectrum techniques that are described in this document. Has no restrictions on the delay in the feedback clock path. Requires a continuously running input clock. Adapts to a wide range of frequencies. However, once locked to a frequency, cannot tolerate large variations of the input frequency. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) * Does not eliminate jitter. The de-skew circuit output jitter is the sum of input jitter and some jitter value that the de-skew circuit might add. * The completion of configuration can be delayed until after DCM locks to guarantee the system clock is established prior to initiating the device. Port Signals Source Clock Input -- CLKIN The CLKIN pin provides the user source clock (the clock signal on which the de-skew circuit operates) to the DCM. The CLKIN frequency must fall in the ranges specified in the Virtex-II Pro Data Sheet. The clock input signal can be provided by one of the following: IBUF -- Input buffer IBUFG -- Global clock input buffer on the same edge of the device (top or bottom) BUFGMUX -- Internal global clock buffer Feedback Clock Input -- CLKFB A reference or feedback signal is required to delay-compensate the output. Connect only the CLK0 or CLK2X DCM outputs to the feedback clock input (CLKFB) pin to provide the necessary feedback to the DCM. The feedback clock input signal can be driven by an internal global clock buffer (BUFGMUX), one of the global clock input buffers (IBUFG) on the same edge of the device (top or bottom), or IBUF (the input buffer.) If an IBUFG sources the CLKFB pin, the following special rules apply: 1. An external input port must source the signal that drives the IBUFG input pin. 2. That signal must directly drive only OBUFs and nothing else. Reset Input -- RST When the reset pin is activated, the LOCKED signal deactivates within four source clock cycles. The RST pin, active High, must either connect to a dynamic signal or be tied to ground. As the DCM delay taps reset to zero, glitches can occur on the DCM clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock output pins. Furthermore, the DCM output clocks no longer de-skew with respect to one another. For these reasons, use the reset pin only when reconfiguring the device or changing the input frequency. The reset input signal is asynchronous and should be held HIGH for at least 2 ns. It takes approximately 120 s for the DCM to achieve lock after a reset in the slowest frequency range. The DCM locks faster at higher frequencies. See the LOCK_DLL teiming parameter in the Virtex-II Pro Data Sheet. Locked Output -- LOCKED In order to achieve lock, the DCM may need to sample several thousand clock cycles. After the DCM achieves lock, the LOCKED signal goes High. The DCM timing parameter section of the Virtex-II Pro Data Sheet provides estimates for locking times. To guarantee that the system clock is established prior to the device "waking up," the DCM can delay the completion of the device configuration process until after the DCM locks. The STARTUP_WAIT attribute activates this feature. Until the LOCKED signal activates, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. In particular, the CLK2X output appears as a 1x clock with a 25/75 duty cycle. Status - STATUS The STATUS output is an 8-bit output, of which STATUS[1] reveals the loss of the input clock, CLKIN to the DCM. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 225 R Chapter 2: Design Considerations Attributes The following attributes provide access to some of the Virtex-II Pro Series de-skew features, (for example, clock division and duty cycle correction). Frequency Mode The de-skew feature of the DCM is achieved with a delay-locked loop (DLL). This attribute specifies either the high or low-frequency mode of the DLL. The default is low-frequency mode. In high-frequency mode, the only outputs available from the DLL are the CLK0, CLK180, CLKDV, and LOCKED. (CLK90, CLK270, CLK2X, and CLK2X180 are not available in high-frequency mode.) The frequency ranges for both frequency modes are specified in the Virtex-II Pro Data Sheet. To set the DLL to high-frequency mode, attach the DLL_FREQUENCY_MODE=HIGH attribute in the source code or schematic. Feedback Input This attribute specifies the feedback input to the DCM (CLK0, or CLK2x). CLK0 is the default feedback. When both the CLK0 and the CLK2x outputs are used internally or externally to the device, the feedback input can be either the CLK0 or CLK2x. In order to set the feedback to CLK2X, attach the CLK_FEEDBACK=2X attribute in the source code or schematic. Duty Cycle Correction The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270, use the duty cycle corrected default such that they exhibit a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION attribute (by default TRUE) controls this feature. To deactivate the DCM duty cycle correction for the 1x clock outputs, attach the DUTY_CYCLE_CORRECTION=FALSE attribute in the source code or schematic. This makes the output clocks have the same duty cycle as the source clock. Startup Delay The default value of the STARTUP_WAIT attribute is FALSE. When STARTUP_WAIT is set to TRUE, and the LCK_cycle BitGen option is used, then the configuration startup sequence waits in the specified cycle until the DCM locks. For details, see Chapter 3: Configuration and Appendix A: BitGen and PROMGen Switches and Options. Legacy Support The Virtex/Virtex-E library primitives/sub modules are supported in Virtex-II Pro for legacy purposes. The following are supported primitives/submodules: * * * * CLKDLL CLKDLLE CLKDLLHF BUFGDLL Library Primitive Only a single library primitive is available for the DLL, a part of the DCM. It is labeled the 'DCM' primitive. 226 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) Submodules BUFGMUX clk_in CLKIN clko_w CLK0 DCM clk1x IO "1" CLKFB UG002_C2_061_112800 Figure 2-24: BUFG_CLK0_SUBM BUFGMUX clk_in CLKIN CLK2X clk2x_w DCM clk2x IO "1" CLKFB UG002_C2_062_112800 Figure 2-25: BUFG_CLK2X_SUBM clk_in clk_in_w CLKIN CLK0 clk1x_ext DCM0_ext clkfb clkfb_w CLKFB clko_int_w CLKIN CLK0 clk1x_int_w IO DCM1_int CLKFB "1" UG002_C2_063_100901 Figure 2-26: BUFG_CLK0_FB_SUBM UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 227 R Chapter 2: Design Considerations clk_in clk_in_w CLKIN CLK2X clk2x_ext DCM_ext clkfb clkfb_w CLKFB clk2x_int_w CLKIN IO CLK2X clk2x_int DCM_int "1" CLKFB UG002_C2_064_100901 Figure 2-27: BUFG_CLK2X_FB_SUBM BUFGMUX clk_in CLKIN CLK0 clk0_w clk1x IO CLKDV "1" DCM clkdiv_w IO clk_div CLKFB "1" UG002_C2_065_110700 Figure 2-28: BUFG_CLKDV_SUBM Frequency Synthesis The DCM provides several flexible methods for generating new clock frequencies. Each method has a different operating frequency range and different AC characteristics. The CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output provides divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. The DCM also offers a fully digital, dedicated Frequency Synthesizer output (CLKFX) and its opposite phase (CLKFX180). The output frequency can be any function of the input clock frequency described by M / D, where M is the multipler (numerator) and D is the divisor (denominator). The two counter-phase frequency synthesized outputs can drive global clock routing networks within the device. The well-buffered global clock distribution network minimizes clock skew due to differences in distance or loading. See Figure 2-29. Operation The DCM clock output CLKFX is any M/D product of the clock input to the DCM. Specifications for M and D, as well as input and output frequency ranges for the frequency synthesizer, are provided in the Virtex-II Pro Data Sheet. The frequency synthesizer output 228 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) is phase aligned to the clock output, CLK0, only if feedback is provided to the CLKFB input of the DCM. DCM CLKIN CLKFB RST CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED STATUS[7:0] clock signal control signal ug002__c2_081_101101 Figure 2-29: Frequency Synthesis Outputs The internal operation of the frequency synthesizer is complex and beyond the scope of this document. The frequency synthesizer multiplies the incoming frequencies by the precalculated quotient M/D and generates the correct output frequencies as long as it is within the range specified in the Virtex-II Pro Data Sheet. For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note that M and D values have no common factors and hence cannot be reduced). The output frequency is correctly 156.25 MHz, although 25 x 50 MHz = 1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far outside the range of the input frequency. Frequency Synthesizer Characteristics * The frequency synthesizer provides an output frequency equal to the input frequency multiplied by M and divided by D. * * The outputs CLKFX and CLKFX180 always have a 50/50 duty-cycle. * The outputs are phase aligned with CLK0 when CLKFB is connected. Smaller M and D values achieve faster lock times. The user should divide M and D by the largest common factor. Port Signals Source Clock Input -- CLKIN The CLKIN pin provides the user source clock to the DCM. The CLKIN frequency must fall in the ranges specified in the Virtex-II Pro Data Sheet. The clock input signal can be provided by one of the following: * * * IBUF -- Input buffer IBUFG -- Global clock input buffer BUFGMUX -- Internal global clock buffer 2x Clock Output -- CLK2X The CLK2X output provides a frequency-doubled clock with an automatic 50/50 dutycycle correction. This output is not available in high-frequency mode. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 229 R Chapter 2: Design Considerations Until the DCM has achieved lock, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty cycle. This behavior allows the DCM to lock on the correct edge with respect to source clock. Clock Divide Output -- CLKDV The clock divide output pin CLKDV provides a lower frequency version of the source clock. The CLKDV_DIVIDE property controls CLKDV such that the source clock is divided by N where N is either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16. This feature provides automatic duty cycle correction such that the CLKDV output pin has a 50/50 duty cycle always in low-frequency mode, as well as for all all integer values of the division factor N in high-frequency mode. Frequency Synthesized Clock Output - CLKFX The CLKFX output provides a frequency-synthesized clock (M/D * CLKIN) with a 50/50 duty cycle. For the CLKFX output to be phase-aligned with CLKIN, the clock feedback (CLK0) must be provided at the CLKFB input. With M and D adjusted such that they have no common factor, the alignment occurs only once every D input clock cycles. Frequency Synthesized Clock Output 180o Phase Shifted - CLKFX180 The CLKFX180 output is a 180o phase shifted version of the CLKFX clock output, also with a 50/50 duty cycle. Locked Output -- LOCKED The LOCKED signal is activated after the DCM has achieved the parameter values set by the user parameters. To guarantee that the system clock is established prior to the device "waking up," the DCM can delay the completion of the device configuration process until after the DCM locks. The STARTUP_WAIT attribute activates this feature. Until the LOCKED signal activates, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious signals. Reset Input -- RST When the reset pin activates, the LOCKED signal deactivates within four source clock cycles. The M and D values at configuration are maintained after the reset. The RST pin, active High, must either connect to a dynamic signal or be tied to ground. Activation of the RST pin can also severely affect the duty cycle of the clock output pins. For this reason, activate the reset pin only when reconfiguring the device or changing the input frequency. The reset input signal is asynchronous and should be held High for at least 2 ns. Status - STATUS The STATUS output is an 8-bit output: * STATUS[1] indicates the loss of the input clock, CLKIN, only when CLKFB is connected. * STATUS[2] indicates loss of CLKFX and CLKFX180 even though LOCKED might still be High. Note that this "CLKFX stopped" status functions only when CLKIN is present. Attributes The following attributes provide access to some of the Virtex-II Pro Series frequency synthesis features, (for example, clock multiplication, clock division). Clock Divide The CLKDV_DIVIDE attribute specifies how the signal on the CLKDV pin is frequency divided with respect to the CLK0 pin. The values allowed for this attribute are 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16; the default value is 2. 230 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) Frequency Mode for Frequency Synthesis This attribute specifies either the high or low-frequency mode of the frequency synthesizer. The default is low-frequency mode. The frequency ranges for both frequency modes are specified in the Virtex-II Pro Data Sheet. To set the frequency synthesizer to high-frequency mode, attach the DFS_FREQUENCY_MODE=HIGH attribute in the source code or schematic. Multiply/Divide Attribute The M and D values can be set using the CLKFX_MULTIPLY and the CLKFX_DIVIDE attributes. The default settings are M = 4 and D = 1. Startup Delay The default value of the STARTUP_WAIT attribute is FALSE. When STARTUP_WAIT is set to TRUE, and the LCK_cycle BitGen option is used, then the configuration startup sequence waits in the specified cycle until the DCM locks. For details, see Chapter 3: Configuration and Appendix A: BitGen and PROMGen Switches and Options. Submodules clk_in CLKIN rst CLKFX clkfx clkfx_w RST DCM "1" CLKFX180 LOCKED clkfx180 clkfx180_w lock "1" UG002_C2_074_110800 Figure 2-30: BUFG_DFS_SUBM clk_in CLKIN CLK0 clk1x clk1x_w "1" CLKFB clkfx clkfx_w CLKFX DCM "1" rst RST CLKFX180 clkfx180 clkfx180_w "1" lock LOCKED UG002_C2_075_110800 Figure 2-31: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook BUFG_DFS_FB_SUBM www.xilinx.com 1-800-255-7778 231 R Chapter 2: Design Considerations Phase Shifting The DCM can also provide coarse and fine-grained phase shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by 1/4 of the input clock period relative to each other, providing coarse phase control. Note that CLK90 and CLK270 are not available in high-frequency mode. Operation Figure 2-32 shows a block diagram of the DCM and all of the outputs affected by the circuitry of the phase shift feature. Figure 2-33 DCM CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 PSINCDEC LOCKED PSEN PSCLK STATUS[7:0] PSDONE ug002_c2_082_101201 Figure 2-32: Phase Shift Outputs Fine-phase adjustment affects all nine DCM output clocks. When activated, the phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the input clock period. In variable mode, the PHASE_SHIFT value can also be dynamically incremented or decremented as determined by PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 2-33 illustrates the effects of fine-phase shifting. CLKIN CLKOUT_PHASE_SHIFT CLKFB = NONE CLKIN CLKOUT_PHASE_SHIFT CLKFB = FIXED (PS/256) x PERIODCLKIN (PS/256) x PERIODCLKIN (PS negative) (PS positive) CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB (PS/256) x PERIODCLKIN (PS negative) (PS/256) x PERIODCLKIN (PS positive) DS031_48_101201 Figure 2-33: Phase Shift Effects 232 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) Two separate components of the phase shift range must be understood: * * PHASE_SHIFT attribute range FINE_SHIFT_RANGE DCM timing parameter range The PHASE_SHIFT attribute is the numerator in the following equation: Phase Shift (ns) = (PHASE_SHIFT/256) * PERIODCLKIN The full range of this attribute is always -255 to +255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE component, which represents the total delay achievable by the phase shift delay line. Total delay is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be as specified in the DCM Timing Parameters section of the Virtex-II Pro Data Sheet. Absolute range (fixed mode) = FINE_SHIFT_RANGE Absolute range (variable mode) = FINE_SHIFT_RANGE/2 The reason for the difference between fixed and variable modes is as follows. For variable mode to allow symmetric, dynamic sweeps from -255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the delay line, thus dividing the total delay line range in half. In fixed mode, since the PHASE_SHIFT value never changes after configuration, the entire delay line is available for insertion into either the CLKIN or CLKFB path (to create either positive or negative skew). Taking both of these components into consideration, the following are some usage examples: * If PERIODCLKIN = two times FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 128, and in variable mode it is limited to 64. * If PERIODCLKIN = FINE_SHIFT_RANGE, then PHASE_SHIFT in fixed mode is limited to 255, and in variable mode it is limited to 128. * If PERIODCLKIN half of the FINE_SHIFT_RANGE, then PHASE_SHIFT is limited to 255 in either mode. In variable mode, the phase factor can be changed by activating PSEN for one period of PSCLK. Increments or decrements to the phase factor can be made by setting the PSINCDEC pin to a High or Low, respectively. When the de-skew circuit has completed an increment or decrement operation, the signal PSDONE goes High for a single PSCLK cycle. This indicates to the user that the next change may be made. The user interface and the physical implementation are different. The user interface describes the phase shift as a fraction of the clock period (N/256). The physical implementation adds the appropriate number of buffer stages (each DCM_TAP) to the clock delay. The DCM_TAP granularity limits the phase resolution at higher clock frequencies. Phase Shift Characteristics * Offers fine-phase adjustment with a resolution of 1/256 of the clock period (or one DCM_TAP, whichever is greater) by configuration and also dynamically under user control. * * The phase shift settings affect all nine DCM outputs. VCC and temperature do not affect the phase shift. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 233 R Chapter 2: Design Considerations Port Signals 1x Clock Outputs -- CLK[0|90|180|270] The 1x clock output pin CLK0 represents a delay-compensated version of the source clock (CLKIN) signal. In low-frequency mode, the DCM provides three phase-shifted versions of the CLK0 signal (CLK90, CLK180, and CLK270), whereas in high-frequency mode, only the 180 phase-shifted version is provided. All four (including CLK0) of the phase shifted outputs can be used simultaneously in low-frequency mode. The relationship between phase shift and the corresponding period shift appears in Table 2-17. The timing diagrams in Figure 2-34 illustrate the DLL clock output characteristics. Table 2-17: Relationship of Phase-Shifted Output Clock to Period Shift Phase (degrees) % Period Shift 0 0% 90 25% 180 50% 270 75% By default, the DCM provides a 50/50 duty cycle correction on all 1x clock outputs. The DUTY_CYCLE_CORRECTION attribute (TRUE by default), controls this feature. Attach the DUTY_CYCLE_CORRECTION=FALSE property to the DCM symbol in order to deactivate the DCM duty cycle correction. With duty cycle correction deactivated, the output clocks have the same duty cycle as the source clock. The DCM clock outputs can drive an OBUF, a BUFGMUX, or they can route directly to the clock input of a synchronous element. 0 90 180 270 0 90 180 270 t CLKIN CLK2X CLKDV_DIVIDE=2 CLKDV DUTY_CYCLE_CORRECTION=FALSE CLK0 CLK90 CLK180 CLK270 DUTY_CYCLE_CORRECTION=TRUE CLK0 CLK90 CLK180 CLK270 x132_07_092599 Figure 2-34: 234 DLL Output Characteristics www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) Source Clock Input -- CLKIN The CLKIN pin provides the user source clock to the DCM. The CLKIN frequency must fall in the ranges specified in the Virtex-II Pro Data Sheet. The clock input signal can be provided by one of the following: * * * IBUF -- Input buffer IBUFG -- Global clock input buffer BUFGMUX -- Internal global clock buffer Feedback Clock Input -- CLKFB A DCM requires a reference or feedback signal to provide delay-compensated output. Connect only the CLK0 or CLK2X DCM outputs to the feedback clock input (CLKFB) pin to provide the necessary feedback to the DCM. The feedback clock input signal can be driven by an internal global clock buffer (BUFGMUX), one of the global clock input buffers (IBUFG) on the same edge of the device (top or bottom), or IBUF (the input buffer.) If an IBUFG sources the CLKFB pin, the following special rules apply: 1. An external input port must source the signal that drives the IBUFG input pin. 2. That signal must directly drive only OBUFs and nothing else. Phase Shift Clock - PSCLK The PSCLK input can be sourced by the CLKIN signal to the DCM, or it can be a lower or higher frequency signal provided from any clock source (external or internal). The frequency range of PSCLK is defined by PSCLK_FREQ_LF/HF (see the Virtex-II Pro Data Sheet). This input has to be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED. Phase Shift Increment/Decrement - PSINCDEC The PSINCDEC signal is synchronous to PSCLK and is used to increment or decrement the phase shift factor. In order to increment or decrement the phase shift by 1/256 of clock period, the PSINCDEC signal must be High for increment or Low for decrement. This input has to be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED. Phase Shift Enable - PSEN To initiate a variable phase-shift operation, the PSEN input must be activated for one period of PSCLK. The phase change becomes effective after up to 100 CLKIN pulse cycles plus three PSCLK cycles, and is indicated by a High pulse on PSDONE. During the phase transition there are no sporadic changes or glitches on any output. PSEN must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED. Reset Input -- RST When the reset pin is activated, the LOCKED signal deactivates within four source clock cycles. After reset, the phase shift value is set to its value at configuration in both the fixed and variable modes. The RST pin, active High, must either connect to a dynamic signal or be tied to ground. Activation of the RST pin can also severely affect the duty cycle of the clock output pins. For this reason, activate the reset pin only when reconfiguring the device or changing the input frequency. The reset input signal is asynchronous and should be held High for at least 2 ns. Locked Output -- LOCKED The LOCKED signal activates after the DCM has achieved lock. To guarantee that the system clock is established prior to the device "waking up," the DCM can delay the completion of the device configuration process until after the DCM locks. The STARTUP_WAIT attribute activates this feature. Until the LOCKED signal activates, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. For details, see Chapter 3: Configuration. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 235 R Chapter 2: Design Considerations Phase Shift DONE - PSDONE The PSDONE signal is synchronous to PSCLK and it indicates, by pulsing High for one period of PSCLK, that the requested phase shift was achieved. This signal also indicates to the user that a new change to the phase shift numerator can be made. This output signal is not valid if the phase shift feature is not being used or is in FIXED mode. Status - STATUS STATUS[0] indicates the overflow of the phase shift numerator and that the absolute delay range of the phase shift delay line is exceeded. Attributes The following attributes provide access to the Virtex-II Pro fine-phase adjustment capability. Clock Out Phase Shift The CLKOUT_PHASE_SHIFT attribute controls the use of the PHASE_SHIFT value. It can be set to NONE, FIXED, or VARIABLE. By default, this attribute is set to NONE, indicating that the phase shift feature is not being used. When this attribute is set to NONE, the PHASE_SHIFT value has no effect on the DCM outputs. If the CLKOUT_PHASE_SHIFT attribute is set to FIXED or NONE, then the PSEN, PSINCDEC, and the PSCLK inputs must be tied to ground. The effects of the CLKOUT_PHASE_SHIFT attribute are shown in Figure 2-33. PHASE_SHIFT This attribute specifies the phase shift numerator as any value from -255 to 255. Submodules DCM clk_in CLKIN CLK0 clk0_w IO CLKFB "1" rst RST CLKFX clkfx_w clkfx IO "1" psindec PSINCDEC CLKFX180 clkfx180_w clkfx180 IO "1" psen PSEN LOCKED lock PSCLK PSDONE psdone ioUG002_C2_076_112900 Figure 2-35: 236 BUFG_PHASE_CLKFX_FB_SUBM www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) DCM clk_in CLKIN CLKFB rst psindec psen clk1x clk0_w CLK0 "1" lock LOCKED RST PSINCDEC PSEN PSCLK PSDONE psdone UG002_C2_071_101201 Figure 2-36: BUFG_PHASE_CLK0_SUBM DCM clk_in CLKIN clk2x_w CLKFB rst psindec psen clk2x CLK2X "1" lock LOCKED RST PSINCDEC PSEN psdone PSCLK PSDONE UG002_C2_072_101201 Figure 2-37: BUFG_PHASE_CLK2X_SUBM DCM clk_in CLKIN clk0_w CLKFB rst psindec psen RST clk1x CLK0 "1" CLKDV clk_div PSINCDEC PSEN LOCKED PSCLK PSDONE lock psdone UG002_C2_073_101201 Figure 2-38: BUFG_PHASE_CLKDV_SUBM UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 237 R Chapter 2: Design Considerations VHDL and Verilog Instantiation VHDL and Verilog instantiation templates are available as examples (see "VHDL and Verilog Templates" on page 238) for all submodules. In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. VHDL and Verilog Templates The following submodules described in this section are available: * * * * * * * * * * * BUFG_CLK0_SUBM BUFG_CLK2X_SUBM BUFG_CLK0_FB_SUBM BUFG_CLK2X_FB_SUBM BUFG_CLKDV_SUBM BUFG_DFS_SUBM BUFG_DFS_FB_SUBM BUFG_PHASE_CLKFX_FB_SUBM BUFG_PHASE_CLK0_SUBM BUFG_PHASE_CLK2X_SUBM BUFG_PHASE_CLKDV_SUBM The corresponding submodules must be synthesized with the design. The BUFG_CLK0_SUBM submodule is provided in VHDL and Verilog as an example. VHDL Template -- Module: BUFG_CLK0_SUBM -- Description: VHDL submodule -- DCM with CLK0 deskew -- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity BUFG_CLK0_SUBM is port ( CLK_IN : in std_logic; RST : in std_logic; CLK1X : out std_logic; LOCK : out std_logic ); end BUFG_CLK0_SUBM; -architecture BUFG_CLK0_SUBM_arch of BUFG_CLK0_SUBM is -- Components Declarations: component BUFG port ( I : in std_logic; O : out std_logic ); end component; component DCM 238 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) -- pragma translate_off generic ( DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE; STARTUP_WAIT : boolean := FALSE ); -- pragma translate_on port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; -- Attributes attribute DLL_FREQUENCY_MODE : string; attribute DUTY_CYCLE_CORRECTION : string; attribute STARTUP_WAIT : string; attribute DLL_FREQUENCY_MODE of U_DCM: label is "LOW"; attribute DUTY_CYCLE_CORRECTION of U_DCM: label is "TRUE"; attribute STARTUP_WAIT of U_DCM: label is "FALSE"; -- Signal Declarations: signal GND : std_logic; signal CLK0_W: std_logic; signal CLK1X_W: std_logic; begin GND <= '0'; CLK1X <= CLK1X_W; -- DCM Instantiation U_DCM: DCM port map ( CLKIN => CLK_IN, CLKFB => CLK1X_W, DSSEN => GND, PSINCDEC => GND, PSEN => GND, PSCLK => GND, RST => RST, CLK0 => CLK0_W, LOCKED => LOCK ); -- BUFG Instantiation U_BUFG: BUFG port map ( I => CLK0_W, O => CLK1X_W ); end BUFG_CLK0_SUBM_arch; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 239 R Chapter 2: Design Considerations Verilog Template // Module: BUFG_CLK0_SUBM // Description: Verilog Submodule // DCM with CLK0 deskew // // Device: Virtex-II Pro Family //------------------------------------------------------------------module BUFG_CKL0_SUBM ( CLK_IN, RST, CLK1X, LOCK ); input CLK_IN; input RST; output CLK1X; output LOCK; wire CLK0_W; wire GND; assign GND = 1'b0; //BUFG Instantiation // BUFG U_BUFG (.I(CLK0_W), .O(CLK1X) ); // Attributes for functional simulation// // synopsys translate_off defparam U_DCM.DLL_FREQUENCY_MODE = "LOW"; defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE"; defparam U_DCM.STARTUP_WAIT = "FALSE"; // synopsys translate_on // Instantiate the DCM primitive// DCM U_DCM ( .CLKFB(CLK1X), .CLKIN(CLK_IN), .DSSEN(GND), .PSCLK(GND), .PSEN(GND), .PSINCDEC(GND), .RST(RST), .CLK0(CLK0_W), .LOCKED(LOCK) ); // synthesis attribute declarations /* synopsys attribute DLL_FREQUENCY_MODE "LOW" DUTY_CYCLE_CORRECTION "TRUE" STARTUP_WAIT "FALSE" */ endmodule 240 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digital Clock Managers (DCMs) DCM Waveforms The DCM waveforms shown below are the results of functional simulation using Model Technology's ModelSim EE/Plus 5.3a_p1 simulator. Note that the time scale for these simulations were set to 1ns/1ps. It is important to set the unused inputs of the DCM to logic 0 and to set the attribute values to the correct data types. For example, the PHASE_SHIFT, CLKFX_DIVIDE, and CLKFX_MULTIPLY attributes are integers and should be set to values as shown. defparam U_DCM.DFS_FREQUENCY_MODE = "LOW"; defparam U_DCM.CLKFX_DIVIDE = 1; (this value's range is specified under Frequency Synthesis in the Virtex-II Pro Data Sheet) defparam U_DCM.CLKFX_MULTIPLY = 4; (this value's range is specified under Frequency Synthesis in the Virtex-II Pro Data Sheet) defparam U_DCM.CLKOUT_PHASE_SHIFT = "FIXED"; defparam U_DCM.PHASE_SHIFT = 150; (Any value from 1 to 255) defparam U_DCM.STARTUP_WAIT = "FALSE"; The input clock, 'clk_in' (CLKIN input of DCM) in all these waveforms is 50 MHz. The DCM_DLL waveforms in Figure 2-39 shows four DCM outputs, namely, clk1x (CLK0 output of DCM), clk2x (CLK2X output of DCM), clk90 (CLK90 output of DCM), and clk180 (CLK180 output of DCM). ug002_c2_095_113000 Figure 2-39: DCM_DLL Waveforms The DCM_DFS Waveforms in Figure 2-40 shows four DCM outputs namely, clk1x (CLK0 output of DCM), clk2x (CLK2X output of DCM), clkfx (CLKFX output of DCM), and clkfx180 (CLKFX180 output of DCM). In this case the attributes, CLKFX_DIVIDE = 1, and the CLKFX_MULTIPLY = 3. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 241 R Chapter 2: Design Considerations ug002_c2_096_113000 Figure 2-40: DCM_DFS Waveforms The DCM_DPS waveforms in Figure 2-41 shows four DCM outputs, namely, clk1x (CLK0 output of DCM), clk2x (CLK2X output of DCM), clk90 (CLK90 output of DCM), and clk180 (CLK180 output of DCM). In this case, the attribute PHASE_SHIFT = 150 which translates to a phase shift of (150 x 20 ns)/256 = 11.719 ns, where 20 ns is the clock period. ug002_c2_097_113000 Figure 2-41: 242 DCM_DPS Waveforms www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory The DCM_DPS_DFS waveforms in Figure 2-42 shows four DCM outputs namely, clk1x (CLK0 output of DCM), clk90 (CLK90 output of DCM), clkfx (CLKFX output of DCM), and clkfx180 (CLKFX180 output of DCM). In this case, the attributes, CLKFX_DIVIDE = 1, and the CLKFX_MULTIPLY = 4. The attribute, PHASE_SHIFT = 150 which translates to a phase shift of (150 x 20 ns)/256 = 11.719 ns, where 20 ns is the clock period. ug002_c2_098_113000 Figure 2-42: DCM_DPS_DFS Waveforms Block SelectRAMTM Memory Introduction In addition to distributed SelectRAM memory, Virtex-II Pro devices feature a large number of 18 Kb block SelectRAM memories. The block SelectRAM memory is a True Dual-PortTM RAM, offering fast, discrete, and large blocks of memory in the device. The memory is organized in columns, and the total amount of block SelectRAM memory depends on the size of the Virtex-II Pro device. The 18 Kb blocks are cascadable to enable a deeper and wider memory implementation, with a minimal timing penalty incurred through specialized routing resources. Embedded dual- or single-port RAM modules, ROM modules, synchronous FIFOs, and data width converters are easily implemented using the Xilinx CORE Generator "Block Memory" modules. Asynchronous FIFOs can be generated using the CORE Generator Asynchronous FIFO and "Block Memory" module. Starting with IP Update #3, the designer can also generate synchronous FIFOs using Block Memory. Synchronous Dual-Port and Single-Port RAM Data Flow The 18Kb block SelectRAM dual-port memory consists of an 18 Kb storage area and two completely independent access ports, A and B. The structure is fully symmetrical, and both ports are interchangeable. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 243 R Chapter 2: Design Considerations Data can be written to either port and can be read from the same or the other port. Each port is synchronous, with its own clock, clock enable, and write enable. Note that the read operation is also synchronous and requires a clock edge. 18-Kbit Block SelectRAM DIA DIPA ADDRA Port A WEA ENA SSRA DOA DOPA CLKA 18 Kb Memory Array DIB DIPB ADDRB WEB ENB SSRB DOB DOPB Port B CLKB ug002_c2_080_111300 Figure 2-43: Dual-Port Data Flows As described below, there are three options for the behavior of the data output during a write operation on its port. There is no dedicated monitor to arbitrate the result of identical addresses on both ports. It is up to the user to time the two clocks appropriately. However, conflicting simultaneous writes to the same location never cause any physical damage. Operating Modes To maximize utilization of the True Dual-Port memory at each clock edge, the block SelectRAM memory supports three different write modes for each port. The "read during write" mode offers the flexibility of using the data output bus during a write operation on the same port. Output behavior is determined by the configuration. This choice increases the efficiency of block SelectRAM memory at each clock cycle and allows designs that use maximum bandwidth. Read Operation The read operation uses one clock edge. The read address is registered on the read port, and the stored data is loaded into the output latches after the RAM access interval passes. Write Operations A write operation is a single clock-edge operation. The write address is registered on the write port, and the data input is stored in memory. Three different modes are used to determine data available on the output latches after a write clock edge. 244 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory WRITE_FIRST or Transparent Mode (Default) In WRITE_FIRST mode, the input data is simultaneously written into memory and stored in the data output (transparent write), as shown in Figure 2-44. CLK WE Data_in XXXX Address aa Data_out 0000 1111 2222 bb cc MEM(aa) 1111 XXXX dd 2222 MEM(dd) ENABLE DISABLED READ WRITE MEM(bb)=1111 WRITE MEM(cc)=2222 READ DS031_19_040400 Figure 2-44: WRITE_FIRST Mode Waveforms READ_FIRST or Read-Before-Write Mode In READ_FIRST mode, data previously stored at the write address appears on the output latches, while the input data is being stored in memory (read before write). See Figure 2-45. CLK WE Data_in XXXX Address aa Data_out 0000 MEM(aa) 1111 2222 bb cc old MEM(bb) XXXX dd old MEM(cc) MEM(dd) ENABLE DISABLED READ WRITE MEM(bb)=1111 WRITE MEM(cc)=2222 READ DS031_18_040400 Figure 2-45: READ_FIRST Mode Waveforms UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 245 R Chapter 2: Design Considerations NO_CHANGE Mode In NO_CHANGE mode, the output latches remain unchanged during a write operation. As shown in Figure 2-46, data output is still the last read data and is unaffected by a write operation on the same port. Mode selection is set by configuration. One of these three modes is set individually for each port by an attribute. The default mode is WRITE_FIRST. CLK WE Data_in XXXX Address aa Data_out 0000 1111 2222 bb cc MEM(aa) XXXX dd MEM(dd) ENABLE DISABLED READ WRITE MEM(bb)=1111 WRITE MEM(cc)=2222 READ DS031_17_040400 Figure 2-46: NO_CHANGE Mode Waveforms 246 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory Conflict Resolution Virtex-II Pro block SelectRAM memory is a True Dual-Port RAM that allows both ports to simultaneously access the same memory cell. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a read) within the clock-to-clock setup window. Figure 2-47 describes this asynchronous operation. B A B A READ Port CLK_A Address_A aa bb WE_A Data_out_A UNKNOWN 4444 WRITE Port CLK_B Data_in_B 3333 Address_B aa WE_B MEM(aa)= 3333 4444 2222 bb cc MEM(bb)= 4444 MEM(cc)= 2222 Clock-to-clock setup violation Figure 2-47: UG002_C2_026_081800 READ-WRITE Conditions If port A and port B are configured with different widths, only the overlapping bits are invalid when conflicts occur. Asynchronous Clocks The first CLK_A clock edge violates the clock-to-clock setup parameter, because it occurs too soon after the last CLK_B clock edge. The write operation on port B is valid, and the read operation on port A is invalid. At the second rising edge of the CLK_B pin, the write operation is valid. The memory location (bb) contains 4444. The second rising edge of CLK_A reads the new data at the same location (bb), which now contains 4444. The clock-to-clock setup timing parameter is specified together with other block SelectRAM switching characteristics in the Virtex-II Pro Data Sheet. Synchronous Clocks When both clocks are synchronous or identical, the result of simultaneous accesses from both ports to the same memory cell is best described in words: * If both ports read simultaneously from the same memory cell: Both Data_out ports will have the same data. * If both ports write simultaneously into the same memory cell: The data stored in that cell becomes invalid (unless both ports write identical data). * If one port writes and the other one reads from the same memory cell: The write operation succeeds, and the write port's Data_out behaves as determined by the read output mode (write_first, read_first, or no_change). If the write port is in read_first mode, the read port's Data_out represents the previous content of the memory cell. If the write port is in write_first mode or in no_change mode, the read port's Data_out becomes invalid. Obviously, the read port's mode setting does not affect this operation. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 247 R Chapter 2: Design Considerations Characteristics * * * A write operation requires only one clock edge. * All outputs have a read-through function or one of three read-during-write functions, depending on the state of the WE pin. The outputs relative to the port clock are available after the clock-to-out timing interval. * Block SelectRAM cells are true synchronous RAM memories and do not have a combinatorial path from the address to the output. * The ports are completely independent of each other (that is, clocking, control, address, read/write functions, initialization, and data width) without arbitration. * Output ports are latched with a self-timed circuit, guaranteeing glitch-free reads. The state of the output port does not change until the port executes another read or write operation. * Data input and output signals are always buses; that is, in a 1-bit width configuration, the data input signal is DI[0] and the data output signal is DO[0]. A read operation requires only one clock edge. All inputs are registered with the port clock and have a setup-to-clock timing specification. Library Primitives The input and output data buses are represented by two buses for 9-bit width (8+1), 18-bit width (16+2), and 36-bit width (32+4) configurations. The ninth bit associated with each byte can store parity or error correction bits. No specific function is performed on this bit. The separate bus for parity bits facilitates some designs. However, other designs safely use a 9-bit, 18-bit, or 36-bit bus by merging the regular data bus with the parity bus. Read/write and storage operations are identical for all bits, including the parity bits. Figure 2-48 shows the generic dual-port block RAM primitive. DIA, DIPA, ADDRA, DOA, DOPA, and the corresponding signals on port B are buses. RAMB16_S#_S# DIA[#:0] DIPA[#:0] ADDRA[#:0] WEA ENA SSRA CLKA DOA[#:0] DOPA[#:0] DIB[#:0] DIPB[#:0] ADDRB[#:0] WEB ENB SSRB CLKB DOB[#:0] DOPB[#:0] DS031_20_040500 Figure 2-48: 248 Dual-Port Block RAM Primitive www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory Table 2-18 lists the available dual-port primitives for synthesis and simulation. Table 2-18: Dual-Port Block RAM Primitives Primitive Port A Width Port B Width RAMB16_S1_S1 1 RAMB16_S1_S2 2 RAMB16_S1_S4 4 1 RAMB16_S1_S9 (8+1) RAMB16_S1_S18 (16+2) RAMB16_S1_S36 (32+4) RAMB16_S2_S2 2 RAMB16_S2_S4 4 RAMB16_S2_S9 2 (8+1) RAMB16_S2_S18 (16+2) RAMB16_S2_S36 (32+4) RAMB16_S4_S4 4 RAMB16_S4_S9 (8+1) 4 RAMB16_S4_S18 (16+2) RAMB16_S4_S36 (32+4) RAMB16_S9_S9 (8+1) RAMB16_S9_S18 (8+1) (16+2) RAMB16_S9_S36 (32+4) RAMB16_S18_S18 (16+2) (16+2) RAMB16_S18_S36 RAMB16_S36_S36 (32+4) (32+4) (32+4) Figure 2-49 shows the generic single-port block RAM primitive. DI, DIP, ADDR, DO, and DOP are buses. RAMB16_S# DI[#:0] DIP[#:0] ADDR[#:0] WE EN SSR CLK DO[#:0] DOP[#:0] DS031_21_040500 Figure 2-49: Single-Port Block RAM Primitive Table 2-19 lists all of the available single-port primitives for synthesis and simulation. Table 2-19: Single-Port Block RAM Primitives Primitive Port Width RAMB16_S1 1 RAMB16_S2 2 RAMB16_S4 4 RAMB16_S9 (8+1) RAMB16_S18 (16+2) RAMB16_S36 (32+4) UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 249 R Chapter 2: Design Considerations VHDL and Verilog Instantiation VHDL and Verilog instantiation templates are available as examples (see "VHDL and Verilog Templates" on page 254). In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. The SelectRAM_Ax templates (with x = 1, 2, 4, 9, 18, or 36) are single-port modules and instantiate the corresponding RAMB16_Sx module. SelectRAM_Ax_By templates (with x = 1, 2, 4, 9, 18, or 36 and y = = 1, 2, 4, 9, 18, or 36) are dual-port modules and instantiate the corresponding RAMB16_Sx_Sy module. Port Signals Each block SelectRAM port operates independently of the other while accessing the same set of 18K-bit memory cells. Clock - CLK[A|B] Each port is fully synchronous with independent clock pins. All port input pins have setup time referenced to the port CLK pin. The data bus has a clock-to-out time referenced to the CLK pin. Clock polarity is configurable (rising edge by default). Enable - EN[A|B] The enable pin affects the read, write, and set/reset functionality of the port. Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells. Enable polarity is configurable (active High by default). Write Enable - WE[A|B] Both EN and WE are active when the contents of the data input bus is written to memory at the address pointed to by the address bus. The output latches are loaded or not loaded according to the write configuration (WRITE_FIRST, READ_FIRST, NO_CHANGE). When inactive, a read operation occurs, and the contents of the memory cells referenced by the address bus reflect on the data-out bus, regardless of the write mode attribute. Write enable polarity is configurable (active High by default). Set/Reset - SSR[A|B] The SSR pin forces the data output latches to contain the value "SRVAL" (see "Attributes" on page 252). The data output latches are synchronously asserted to 0 or 1, including the parity bit. In a 36-bit width configuration, each port has an independent SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM memory cells and does not disturb write operations on the other port. Like the read and write operation, the set/reset function is active only when the enable pin of the port is active. Set/reset polarity is configurable (active High by default). Address Bus - ADDR[A|B]<#:0> The address bus selects the memory cells for read or write. The width of the port determines the required address bus width, as shown in Table 2-20. 250 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory Table 2-20: Port Aspect Ratio Port Data Width Depth ADDR Bus DI Bus / DO Bus DIP Bus / DOP Bus 1 16,384 <13:0> <0> NA 2 8,192 <12:0> <1:0> NA 4 4,096 <11:0> <3:0> NA 9 2,048 <10:0> <7:0> <0> 18 1,024 <9:0> <15:0> <1:0> 36 512 <8:0> <31:0> <3:0> Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0> Data-in buses provide the new data value to be written into RAM. The regular data-in bus (DI) and the parity data-in bus (when available) have a total width equal to the port width. For example the 36-bit port data width is represented by DI<31:0> and DIP<3:0>, as shown in Table 2-20. Data-Out Buses - DO[A|B]<#:0> & DOP[A|B]<#:0> Data-out buses reflect the contents of memory cells referenced by the address bus at the last active clock edge during a read operation. During a write operation (WRITE_FIRST or READ_FIRST configuration), the data-out buses reflect either the data-in buses or the stored value before write. During a write operation in NO_CHANGE mode, data-out buses are not affected. The regular data-out bus (DO) and the parity data-out bus (DOP) (when available) have a total width equal to the port width, as shown in Table 2-20. Inverting Control Pins For each port, the four control pins (CLK, EN, WE, and SSR) each have an individual inversion option. Any control signal can be configured as active High or Low, and the clock can be active on a rising or falling edge (active High on rising edge by default) without requiring other logic resources. Unused Inputs Non-connected Data and/or address inputs should be connected to logic "1". GSR The global set/reset (GSR) signal of a Virtex-II Pro device is an asynchronous global signal that is active at the end of device configuration. The GSR can also restore the initial Virtex-II Pro state at any time. The GSR signal initializes the output latches to the INIT, or to the INIT_A and INIT_B value (see "Attributes" on page 252). A GSR signal has no impact on internal memory contents. Because it is a global signal, the GSR has no input pin at the functional level (block SelectRAM primitive). Address Mapping Each port accesses the same set of 18,432 memory cells using an addressing scheme dependent on the width of the port. The physical RAM locations addressed for a particular width are determined using the following formula (of interest only when the two ports use different aspect ratios): END = ((ADDR + 1) * Width) -1 START= ADDR * Width Table 2-21 shows low-order address mapping for each port width. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 251 R Chapter 2: Design Considerations Table 2-21: Port Address Mapping Port Parity Width Locations 1 31 2 N.A. 4 8+1 16 + 2 32 + 4 Data Locations 30 29 15 28 27 26 14 13 24 23 12 7 22 21 11 20 19 10 6 3 2 1 0 1 25 18 9 16 8 5 3 17 4 15 14 13 7 6 11 10 9 8 7 6 5 4 3 2 1 0 5 3 2 0 12 4 3 2 1 1 2 1 1 0 0 0 0 0 0 Attributes Content Initialization - INIT_xx INIT_xx attributes define the initial memory contents. By default block SelectRAM memory is initialized with all zeros during the device configuration sequence. The 64 initialization attributes from INIT_00 through INIT_3F represent the regular memory contents. Each INIT_xx is a 64-digit hex-encoded bit vector. The memory contents can be partially initialized and are automatically completed with zeros. The following formula is used for determining the bit positions for each INIT_xx attribute. Given yy = conversion hex-encoded to decimal (xx), INIT_xx corresponds to the memory cells as follows: * * from [(yy + 1) * 256] -1 * * * yy = conversion hex-encoded to decimal X"1F" = 31 to (yy) * 256 For example, for the attribute INIT_1F, the conversion is as follows: from [(31+1) * 256] -1 = 8191 to 31 * 256 = 7936 More examples are given in Table 2-22. Table 2-22: Block SelectRAM Initialization Attributes Attribute 252 Memory Cell from to INIT_00 255 0 INIT_01 511 256 INIT_02 767 512 ... ... ... INIT_0E 3839 3584 INIT_0F 4095 3840 INIT_10 4351 4096 ... ... ... INIT_1F 8191 7936 INIT_20 8447 8192 ... ... ... INIT_2F 12287 12032 INIT_30 12543 12288 .. ... ... INIT_3F 16383 16128 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory Content Initialization - INITP_xx INITP_xx attributes define the initial contents of the memory cells corresponding to DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros. The eight initialization attributes from INITP_00 through INITP_07 represent the memory contents of parity bits. Each INITP_xx is a 64-digit hex-encoded bit vector and behaves like a regular INIT_xx attribute. The same formula can be used to calculate the bit positions initialized by a particular INITP_xx attribute. Output Latches Initialization - INIT (INIT_A & INIT_B) The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output latches values after configuration. The width of the INIT (INIT_A & INIT_B) attribute is the port width, as shown in Table 2-23. These attributes are hex-encoded bit vectors and the default value is 0. Output Latches Synchronous Set/Reset - SRVAL (SRVAL_A & SRVAL_B) The SRVAL (single-port) or SRVAL_A and SRVAL_B (dual-port) attributes define output latch values when the SSR input is asserted. The width of the SRVAL (SRVAL_A and SRVAL_B) attribute is the port width, as shown in Table 2-23. These attributes are hexencoded bit vectors and the default value is 0. Table 2-23: Port Width Values Port Data Width DOP Bus DO Bus INIT / SRVAL 1 NA <0> 1 2 NA <1:0> 2 4 NA <3:0> 4 9 <0> <7:0> (1+8) = 9 18 <1:0> <15:0> (2+16) = 18 36 <3:0> <31:0> (4 + 32) = 36 Initialization in VHDL or Verilog Codes Block SelectRAM memory structures can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the attributes are attached to the block SelectRAM instantiation and are copied in the EDIF output file to be compiled by Xilinx Alliance SeriesTM tools. The VHDL code simulation uses a generic parameter to pass the attributes. The Verilog code simulation uses a defparam parameter to pass the attributes. The XC2V_RAMB_1_PORT block SelectRAM instantiation code examples (in VHDL and Verilog) illustrate these techniques (see "VHDL and Verilog Templates" on page 254). Location Constraints Block SelectRAM instances can have LOC properties attached to them to constrain placement. Block SelectRAM placement locations differ from the convention used for naming CLB locations, allowing LOC properties to transfer easily from array to array. The LOC properties use the following form: LOC = RAMB16_X#Y# The RAMB16_X0Y0 is the bottom-left block SelectRAM location on the device. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 253 R Chapter 2: Design Considerations Applications Creating Larger RAM Structures Block SelectRAM columns have specialized routing to allow cascading blocks with minimal routing delays. Wider or deeper RAM structures are achieved with a smaller timing penalty than is encountered when using normal routing resources. The CORE Generator program offers the designer a painless way to generate wider and deeper memory structures using multiple block SelectRAM instances. This program outputs VHDL or Verilog instantiation templates and simulation models, along with an EDIF file for inclusion in a design. Multiple RAM Organizations The flexibility of block SelectRAM memories allows designs with various types of RAM in addition to regular configurations. Application notes at www.xilinx.com describe some of these designs, with VHDL and Verilog reference designs included. Virtex-II Pro block SelectRAM can be used as follows: * * * Two independent single-port RAM resources One 72-bit single-port RAM resource One triple-port (1 Read/Write and 2 Read ports) RAM resource Application notes with VHDL and Verilog reference designs at www.xilinx.com also describe other implementations using block SelectRAM memory, such as: * * xapp258 "FIFOs Using Virtex-II Pro Block RAM" xapp260 "Fast Read/Write CAM Solution" VHDL and Verilog Templates VHDL and Verilog templates are available for all single-port and dual-port primitives. The A and B numbers indicate the width of the ports. The following are single-port templates: * * * * * * SelectRAM_A1 * * * * * * * * * * * * SelectRAM_A1_B1 SelectRAM_A2 SelectRAM_A4 SelectRAM_A9 SelectRAM_A18 SelectRAM_A36 The following are dual-port templates: 254 SelectRAM_A1_B2 SelectRAM_A1_B4 SelectRAM_A1_B9 SelectRAM_A1_B18 SelectRAM_A1_B36 SelectRAM_A2_B2 SelectRAM_A2_B4 SelectRAM_A2_B9 SelectRAM_A2_B18 SelectRAM_A2_B36 SelectRAM_A4_B4 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory * * * * * * * * * SelectRAM_A4_B9 SelectRAM_A4_B18 SelectRAM_A4_B36 SelectRAM_A9_B9 SelectRAM_A9_B18 SelectRAM_A9_B36 SelectRAM_A18_B18 SelectRAM_A18_B36 SelectRAM_A36_B36 VHDL Template As an example, the XC2V_RAMB_1_PORT.vhd file uses the SelectRAM_A36 template: -- Module: XC2V_RAMB_1_PORT -- Description: 18Kb Block SelectRAM example -- Single Port 512 x 36 bits -- Use template "SelectRAM_A36.vhd" --- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --- Syntax for Synopsys FPGA Express -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on -entity XC2V_RAMB_1_PORT is port ( DATA_IN : in std_logic_vector (35 downto 0); ADDRESS : in std_logic_vector (8 downto 0); ENABLE: in std_logic; WRITE_EN : in std_logic; SET_RESET : in std_logic; CLK : in std_logic; DATA_OUT : out std_logic_vector (35 downto 0) ); end XC2V_RAMB_1_PORT; -architecture XC2V_RAMB_1_PORT_arch of XC2V_RAMB_1_PORT is --- Components Declarations: -component BUFG port ( I : in std_logic; O : out std_logic ); end component; --- Syntax for Synopsys FPGA Express component RAMB16_S36 -- pragma translate_off generic ( -- "Read during Write" attribute for functional simulation WRITE_MODE : string := "READ_FIRST" ; -- WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 255 R Chapter 2: Design Considerations -- Output value after configuration INIT : bit_vector(35 downto 0) := X"000000000"; -- Output value if SSR active SRVAL : bit_vector(35 downto 0) := X"012345678"; -- Plus bits initial content INITP_00 : bit_vector(255 downto 0) := X"000000000000000000000000000000000000000000000000FEDCBA9876543210"; INITP_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; -- Regular bits initial content INIT_00 : bit_vector(255 downto 0) := X"000000000000000000000000000000000000000000000000FEDCBA9876543210"; INIT_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; ... (cut) INIT_3E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- pragma translate_on port ( DI : in std_logic_vector (31 downto 0); DIP : in std_logic_vector (3 downto 0); ADDR : in std_logic_vector (8 downto 0); EN : in STD_LOGIC; WE : in STD_LOGIC; SSR : in STD_LOGIC; CLK : in STD_LOGIC; DO : out std_logic_vector (31 downto 0); DOP : out std_logic_vector (3 downto 0) ); end component; --- Attribute Declarations: attribute WRITE_MODE : string; attribute INIT: string; attribute SRVAL: string; -attribute INITP_00: string; attribute INITP_01: string; attribute INITP_02: string; attribute INITP_03: string; attribute INITP_04: string; attribute INITP_05: string; attribute INITP_06: string; attribute INITP_07: string; -- 256 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory attribute INIT_00: string; attribute INIT_01: string; attribute INIT_02: string; ... (cut) attribute INIT_3E: string; attribute INIT_3F: string; --- Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE attribute WRITE_MODE of U_RAMB16_S36: label is "READ_FIRST"; attribute INIT of U_RAMB16_S36: label is "000000000"; attribute SRVAL of U_RAMB16_S36: label is "012345678"; --- RAMB16 memory initialization for Alliance -- Default value is "0" / Partial initialization strings are padded -- with zeros to the left attribute INITP_00 of U_RAMB16_S36: label is "000000000000000000000000000000000000000000000000FEDCBA9876543210"; attribute INITP_01 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_02 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_03 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_04 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_05 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_06 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_07 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; -attribute INIT_00 of U_RAMB16_S36: label is "000000000000000000000000000000000000000000000000FEDCBA9876543210"; attribute INIT_01 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_02 of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; ... (cut) attribute INIT_3E of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3F of U_RAMB16_S36: label is "0000000000000000000000000000000000000000000000000000000000000000"; ---- Signal Declarations: --- signal VCC : std_logic; -- signal GND : std_logic; signal CLK_BUFG: std_logic; signal INV_SET_RESET : std_logic; -begin -- VCC <= '1'; -- GND <= '0'; --- Instantiate the clock Buffer U_BUFG: BUFG port map ( I => CLK, O => CLK_BUFG UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 257 R Chapter 2: Design Considerations ); --- Use of the free inverter on SSR pin INV_SET_RESET <= NOT SET_RESET; -- Block SelectRAM Instantiation U_RAMB16_S36: RAMB16_S36 port map ( DI => DATA_IN (31 downto 0), -- insert 32 bits data-in bus (<31 downto 0>) DIP => DATA_IN (35 downto 32), -- insert 4 bits parity datain bus (or <35 downto 32>) ADDR => ADDRESS (8 downto 0), -- insert 9 bits address bus EN => ENABLE, -- insert enable signal WE => WRITE_EN, -- insert write enable signal SSR => INV_SET_RESET, -- insert set/reset signal CLK => CLK_BUFG, -- insert clock signal DO => DATA_OUT (31 downto 0), -- insert 32 bits data-out bus (<31 downto 0>) DOP => DATA_OUT (35 downto 32) -- insert 4 bits parity dataout bus (or <35 downto 32>) ); -end XC2V_RAMB_1_PORT_arch; --------------------------------------------------------------------- Verilog Template // Module: XC2V_RAMB_1_PORT // Description: 18Kb Block SelectRAM-II example // Single Port 512 x 36 bits // Use template "SelectRAM_A36.v" // // Device: Virtex-II Pro Family //------------------------------------------------------------------module XC2V_RAMB_1_PORT (CLK, SET_RESET, ENABLE, WRITE_EN, ADDRESS, DATA_IN, DATA_OUT); input CLK, SET_RESET, ENABLE, WRITE_EN; input [35:0] DATA_IN; input [8:0] ADDRESS; output [35:0] DATA_OUT; wire CLK_BUFG, INV_SET_RESET; //Use of the free inverter on SSR pin assign INV_SET_RESET = ~SET_RESET; // initialize block ram for simulation // synopsys translate_off defparam //"Read during Write" attribute for functional simulation U_RAMB16_S36.WRITE_MODE = "READ_FIRST", //WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE //Output value after configuration U_RAMB16_S36.INIT = 36'h000000000, //Output value if SSR active U_RAMB16_S36.SRVAL = 36'h012345678, 258 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Block SelectRAMTM Memory //Plus bits initial content U_RAMB16_S36.INITP_00 = 256'h0123456789ABCDEF000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000, //Regular bits initial content U_RAMB16_S36.INIT_00 = 256'h0123456789ABCDEF000000000000000000000000000000000000000000000000, U_RAMB16_S36.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000, ...<cut> U_RAMB16_S36.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000, U_RAMB16_S36.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; // synopsys translate_on //Instantiate the clock Buffer BUFG U_BUFG ( .I(CLK), .O(CLK_BUFG)); //Block SelectRAM Instantiation RAMB16_S36 U_RAMB16_S36 ( .DI(DATA_IN[31:0]), .DIP(DATA_IN-PARITY[35:32]), .ADDR(ADDRESS), .EN(ENABLE), .WE(WRITE_EN), .SSR(INV_SET_RESET), .CLK(CLK_BUFG), .DO(DATA_OUT[31:0]), .DOP(DATA_OUT-PARITY[35:32])); // synthesis attribute declarations /* synopsys attribute WRITE_MODE "READ_FIRST" INIT "000000000" SRVAL "012345678" INITP_00 "0123456789ABCDEF000000000000000000000000000000000000000000000000" INITP_01 "0000000000000000000000000000000000000000000000000000000000000000" INITP_02 "0000000000000000000000000000000000000000000000000000000000000000" INITP_03 "0000000000000000000000000000000000000000000000000000000000000000" UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 259 R Chapter 2: Design Considerations INITP_04 "0000000000000000000000000000000000000000000000000000000000000000" INITP_05 "0000000000000000000000000000000000000000000000000000000000000000" INITP_06 "0000000000000000000000000000000000000000000000000000000000000000" INITP_07 "0000000000000000000000000000000000000000000000000000000000000000" INIT_00 "0123456789ABCDEF000000000000000000000000000000000000000000000000" INIT_01 "0000000000000000000000000000000000000000000000000000000000000000" INIT_02 "0000000000000000000000000000000000000000000000000000000000000000" ...<cut> INIT_3E "0000000000000000000000000000000000000000000000000000000000000000" INIT_3F "0000000000000000000000000000000000000000000000000000000000000000" */ endmodule Distributed SelectRAM Memory Introduction In addition to 18Kb SelectRAM blocks, Virtex-II Pro devices feature distributed SelectRAM modules. Each function generator or LUT of a CLB resource can implement a 16 x 1-bit synchronous RAM resource. Distributed SelectRAM memory writes synchronously and reads asynchronously. However, a synchronous read can be implemented using the register that is available in the same slice. This 16 x 1-bit RAM is cascadable for a deeper and/or wider memory implementation, with a minimal timing penalty incurred through specialized logic resources. Distributed SelectRAM modules up to a size of 128 x 1 are available as primitives. Two 16 x 1 RAM resources can be combined to form a dual-port 16 x 1 RAM with one dedicated read/write port and a second read-only port. One port writes into both 16 x1 RAMs simultaneously, but the second port reads independently. This section provides generic VHDL and Verilog reference code examples implementing n-bit-wide single-port and dual-port distributed SelectRAM memory. Distributed SelectRAM memory enables many high-speed applications that require relatively small embedded RAM blocks, such as FIFOs, which are close to the logic that uses them. Virtex-II Pro Distributed SelectRAM memories can be generated using the CORE Generator Distributed Memory module (V2.0 or later). The user can also generate Distributed RAM-based Asynchronous and Synchronous FIFOs using the CORE Generator. Single-Port and Dual-Port RAM Data Flow Distributed SelectRAM memory supports the following: * * 260 Single-port RAM with synchronous write and asynchronous read Dual-port RAM with one synchronous write and two asynchronous read ports www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Distributed SelectRAM Memory As illustrated in the Figure 2-50, the dual port has one read/write port and an independent read port. Single-Port RAM D R/W Port Address Write Dual-Port RAM D O R/W Port SPO Address Read Write Read WCLK WCLK Read Port DPO Address Read ug002_c2_001_061400 Figure 2-50: Single-Port and Dual-Port Distributed SelectRAM Any read/write operation can occur simultaneously with and independently of a read operation on the other port. Write Operations The write operation is a single clock-edge operation, with a write enable that is active High by default. When the write enable is Low, no data is written into the RAM. When the write enable is High, the clock edge latches the write address and writes the data on D into the RAM. Read Operation The read operation is a combinatorial operation. The address port (single or dual port) is asynchronous with an access time equivalent to the logic delay. Read During Write When new data is synchronously written, the output reflects the data in the memory cell addressed (transparent mode). The timing diagram in Figure 2-51 illustrates a write operation, with the previous data read on the output port, before the clock edge and then the new data. WCLK DATA_IN d ADDRESS aa WRITE_EN twrite tread DATA_OUT tread MEM(aa) d Previous Data New Data DS031_27_041300 Figure 2-51: Write Timing Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 261 R Chapter 2: Design Considerations Characteristics * * * * A write operation requires only one clock edge. * For dual-port RAM, one address is the write and read address, the other address is an independent read address. A read operation requires only the logic access time. Outputs are asynchronous and dependent only on the logic delay. Data and address inputs are latched with the write clock and have a setup-to-clock timing specification. There is no hold time requirement. Library Primitives Seven library primitives from 16 x 1-bit to 128 x 1-bit are available. Four primitives are single-port RAM and three primitives are True Dual-Port RAM, as shown in Table 2-24. Table 2-24: Single-Port and Dual-Port Distributed SelectRAM Primitive RAM Size Type Address Inputs RAM16X1S 16 bits single-port A3, A2, A1, A0 RAM32X1S 32 bits single-port A4, A3, A2, A1, A0 RAM64X1S 64 bits single-port A5, A3, A2, A1, A0 RAM128X1S 128 bits single-port A6, A4, A3, A2, A1, A0 RAM16X1D 16 bits dual-port A3, A2, A1, A0 RAM32X1D 32 bits dual-port A4, A3, A2, A1, A0 RAM64X1D 64 bits dual-port A5, A4, A3, A2, A1, A0 The input and output data are 1-bit wide. However, several distributed SelectRAM memories can be used to implement wide memory blocks. Figure 2-52 shows generic single-port and dual-port distributed SelectRAM primitives. The A and DPRA signals are address buses. RAMyX1S RAMyX1D D D O WE SPO WE WCLK WCLK A[#:0] A[#:0] R/W Port DPO RAMyX8S DPRA[#:0] Read Port D[7:0] WE O[7:0] WCLK A[..]+ ug002_c2_003_101600 Figure 2-52: 262 Single-Port and Dual-Port Distributed SelectRAM Primitive www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Distributed SelectRAM Memory As shown in Table 2-25, wider library primitives are available for 2-bit, 4-bit, and 8-bit RAM. Table 2-25: Primitive Wider Library Primitives RAM Size Data Inputs Address Inputs Data Outputs RAM16x2S 16 x 2-bit D1, D0 A3, A2, A1, A0 O1, O0 RAM32X2S 32 x 2-bit D1, D0 A4, A3, A2, A1, A0 O1, O0 RAM64X2S 64 x 2-bit D1, D0 A5, A4, A3, A2, A1, A0 O1, O0 RAM16X4S 16 x 4-bit D3, D2, D1, D0 A3, A2, A1, A0 O3, O2, O1, O0 RAM32X4S 32 x 4-bit D3, D2, D1, D0 A4,A3, A2, A1, A0 O3, O2, O1, O0 RAM16X8S 16 x 8-bit D <7:0> A3, A2, A1, A0 O <7:0> RAM32X8S 32 x 8-bit D <7:0> A4,A3, A2, A1, A0 O <7:0> VHDL and Verilog Instantiation VHDL and Verilog instantiations templates are available as examples (see "VHDL and Verilog Templates" on page 267). In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. The SelectRAM_xS templates (with x = 16, 32, 64, or 128) are single-port modules and instantiate the corresponding RAMxX1S primitive. SelectRAM_xD templates (with x = 16, 32, or 64) are dual-port modules and instantiate the corresponding RAMxX1D primitive. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 263 R Chapter 2: Design Considerations Ports Signals Each distributed SelectRAM port operates independently of the other while reading the same set of memory cells. Clock - WCLK The clock is used for the synchronous write. The data and the address input pins have setup time referenced to the WCLK pin. Enable - WE The enable pin affects the write functionality of the port. An inactive Write Enable prevents any writing to memory cells. An active Write Enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs. Address - A0, A1, A2, A3 (A4, A5, A6) The address inputs select the memory cells for read or write. The width of the port determines the required address inputs. Note that the address inputs are not a bus in VHDL or Verilog instantiations. Data In - D The data input provides the new data value to be written into the RAM. Data Out - O, SPO, and DPO The data out O (Single-Port or SPO) and DPO (Dual-Port) reflects the contents of the memory cells referenced by the address inputs. Following an active write clock edge, the data out (O or SPO) reflects the newly written data. Inverting Control Pins The two control pins (WCLK and WE) each have an individual inversion option. Any control signal, including the clock, can be active at 0 (negative edge for the clock) or at 1 (positive edge for the clock) without requiring other logic resources. GSR The global set/reset (GSR) signal does not affect distributed SelectRAM modules. Attributes Content Initialization - INIT With the INIT attributes, users can define the initial memory contents after configuration. By default distributed SelectRAM memory is initialized with all zeros during the device configuration sequence. The initialization attribute INIT represents the specified memory contents. Each INIT is a hex-encoded bit vector. Table 2-26 shows the length of the INIT attribute for each primitive. Table 2-26: 264 INIT Attributes Length Primitive Template INIT Attribute Length RAM16X1S SelectRAM_16S 4 digits RAM32X1S SelectRAM_32S 8 digits RAM64X1S SelectRAM_64S 16 digits RAM128X1S SelectRAM_128S 32 digits RAM16X1D SelectRAM_16S 4 digits RAM32X1D SelectRAM_32S 8 digits RAM64X1D SelectRAM_64S 16 digits www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Distributed SelectRAM Memory Initialization in VHDL or Verilog Codes Distributed SelectRAM memory structures can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the attributes are attached to the distributed SelectRAM instantiation and are copied in the EDIF output file to be compiled by Xilinx Alliance SeriesTM tools. The VHDL code simulation uses a generic parameter to pass the attributes. The Verilog code simulation uses a defparam parameter to pass the attributes. The distributed SelectRAM instantiation templates (in VHDL and Verilog) illustrate these techniques (see "VHDL and Verilog Templates" on page 267). Location Constraints The CLB has four slices S0, S1, S2 and S3. As an example, in the bottom left CLB, the slices have the coordinates shown below: Slice S3 Slice S2 Slice S1 Slice S0 X1Y1 X1Y0 X0Y1 X0Y0 Distributed SelectRAM instances can have LOC properties attached to them to constrain placement. The RAM16X1S primitive fits in any LUT of slices S0 or S1. For example, the instance U_RAM16 is placed in slice X0Y0 with the following LOC properties: INST "U_RAM16" LOC = "SLICE_X0Y0"; The RAM16X1D primitive occupies half of two slices, as shown in Figure 2-53. The first slice (output SPO) implements the read/write port with the same address A[3:0] for read and write. The second slice implements the second read port with the address DPRA[3:0] and is written simultaneously with the first slice to the address A[3:0]. RAM16X1D D SPO Reg DPO DPRA[3:0] Reg A[3:0] Reg Slice S0 (or S1) Reg Slice S2 (or S3) ug002_c2_004_011002 Figure 2-53: RAM16X1D Placement In the same CLB module, the dual-port RAM16X1D either occupies half of slices S0 (X0Y0) and S2 (X1Y0), or half of slices S1 (X0Y1) and S3 (X1Y1). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 265 R Chapter 2: Design Considerations If a dual-port 16 x 2-bit module is built, the two RAM16X1D primitives occupy two slices, as long as they share the same clock and write enable, as illustrated in Figure 2-54. RAM16X1D Bit 0 D[0] SPO[0] D[1] SPO[1] DPO[0] Reg DPO[1] Reg Reg Reg Slice S2 Slice S0 RAM16X1D Bit 1 ug002_c2_005_011002 Figure 2-54: Two RAM16X1D Placement A RAM32X1S primitive fits in one slice, as shown in Figure 2-55. Virtex-II Slice D Reg A4 F5 A[3:0] O Reg ug002_c2_006_061300 Figure 2-55: RAM32X1S Placement Following the same rules, a RAM32X1D primitive fits in two slices, with one slice implementing the read/write port and the second slice implementing the second read port. The RAM64X1S primitive occupies two slices and the RAM64X1D primitive occupies four slices (one CLB element), with two slices implementing the read/write port and two other slices implementing the second read port. The RAM64X1S read path is built on the MUXF5 and MUXF6 multiplexers. The RAM128X1S primitive occupies four slices, equivalent to one CLB element. Distributed SelectRAM placement locations use the slice location naming convention, allowing LOC properties to transfer easily from array to array. 266 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Distributed SelectRAM Memory Applications Creating Larger RAM Structures The memory compiler program generates wider and/or deeper memory structures using distributed SelectRAM instances. Along with an EDIF file for inclusion in a design, this program produces VHDL and Verilog instantiation templates and simulation models. Table 2-27 shows the generic VHDL and Verilog distributed SelectRAM examples provided to implement n-bit-wide memories. Table 2-27: VHDL and Verilog Submodules Submodules Primitive Size Type XC2V_RAM16XN_S_SUBM RAM16X1S 16 words x n-bit single-port XC2V_RAM32XN_S_SUBM RAM32X1S 32 words x n-bit single-port XC2V_RAM64XN_S_SUBM RAM64X1S 64 words x n-bit single-port XC2V_RAM128XN_S_SUBM RAM128X1S 128 words x n-bit single-port XC2V_RAM16XN_D_SUBM RAM16X1D 16 words x n-bit dual-port XC2V_RAM32XN_D_SUBM RAM32X1D 32 words x n-bit dual-port XC2V_RAM64XN_D_SUBM RAM64X1D 64 words x n-bit dual-port By using the read/write port for the write address and the second read port for the read address, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effective throughput of the memory. VHDL and Verilog Templates VHDL and Verilog templates are available for all single-port and dual-port primitives. The number in each template indicates the number of bits (for example, SelectRAM_16S is the template for the 16 x 1-bit RAM); S indicates single-port, and D indicates dual-port. In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. The following are single-port templates: - SelectRAM_16S - SelectRAM_32S - SelectRAM_64S - SelectRAM_128S The following are dual-port templates: - SelectRAM_16D - SelectRAM_32D - SelectRAM_64D Templates for the SelectRAM_16S module are provided in VHDL and Verilog code as examples. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 267 R Chapter 2: Design Considerations VHDL Template --- Module: SelectRAM_16S --- Description: VHDL instantiation template -Distributed SelectRAM -Single Port 16 x 1 -can be used also for RAM16X1S_1 --- Device: Virtex-II Pro Family ------------------------------------------------------------------------ Components Declarations: -component RAM16X1S -- pragma translate_off generic ( -- RAM initialization ("0" by default) for functional simulation: INIT : bit_vector := X"0000" ); -- pragma translate_on port ( D : in std_logic; WE : in std_logic; WCLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; O : out std_logic ); end component; ------------------------------------------------------------------------ Architecture section: --- Attributes for RAM initialization ("0" by default): attribute INIT: string; -attribute INIT of U_RAM16X1S: label is "0000"; --- Distributed SelectRAM Instantiation U_RAM16X1S: RAM16X1S port map ( D => , -- insert input signal WE => , -- insert Write Enable signal WCLK => , -- insert Write Clock signal A0 => , -- insert Address 0 signal A1 => , -- insert Address 1 signal A2 => , -- insert Address 2 signal A3 => , -- insert Address 3 signal O => -- insert output signal ); ---------------------------------------------------------------------- 268 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Look-Up Tables as Shift Registers (SRLUTs) Verilog Template // // Module: SelectRAM_16S // // Description: Verilog instantiation template // Distributed SelectRAM // Single Port 16 x 1 // can be used also for RAM16X1S_1 // // Device: Virtex-II Pro Family // //------------------------------------------------------------------// // // Syntax for Synopsys FPGA Express // synopsys translate_off defparam //RAM initialization ("0" by default) for functional simulation: U_RAM16X1S.INIT = 16'h0000; // synopsys translate_on //Distributed SelectRAM Instantiation RAM16X1S U_RAM16X1S ( .D(), // insert input signal .WE(), // insert Write Enable signal .WCLK(), // insert Write Clock signal .A0(), // insert Address 0 signal .A1(), // insert Address 1 signal .A2(), // insert Address 2 signal .A3(), // insert Address 3 signal .O() // insert output signal ); // synthesis attribute declarations /* synopsys attribute INIT "0000" */ Look-Up Tables as Shift Registers (SRLUTs) Introduction Virtex-II Pro can configure any look-up table (LUT) as a 16-bit shift register without using the flip-flops available in each slice. Shift-in operations are synchronous with the clock, and output length is dynamically selectable. A separate dedicated output allows the cascading of any number of 16-bit shift registers to create whatever size shift register is needed. Each CLB resource can be configured using the 8 LUTs as a 128-bit shift register. This section provides generic VHDL and Verilog submodules and reference code examples for implementing from 16-bit up to 128-bit shift registers. These submodules are built from 16-bit shift-register primitives and from dedicated MUXF5, MUXF6, MUXF7, and MUXF8 multiplexers. These shift registers enable the development of efficient designs for applications that require delay or latency compensation. Shift registers are also useful in synchronous FIFO and content-addressable memory (CAM) designs. To quickly generate a Virtex-II Pro shift UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 269 R Chapter 2: Design Considerations register without using flip-flops (i.e., using the SRL16 element(s)), use the CORE Generator RAM-based Shift Register module. Shift Register Operations Data Flow Each shift register (SRL16 primitive) supports: * * * Synchronous shift-in Asynchronous 1-bit output when the address is changed dynamically Synchronous shift-out when the address is fixed In addition, cascadable shift registers (SRLC16) support synchronous shift-out output of the last (16th) bit. This output has a dedicated connection to the input of the next SRLC16 inside the CLB resource. Two primitives are illustrated in Figure 2-56. SRLC16E D Q Address SRL16E CE Q15 CLK D Q Address SRLC16E CE CLK D Q Address CE CLK Q15 UG002_C2_007_061400 Figure 2-56: Shift Register and Cascadable Shift Register Shift Operation The shift operation is a single clock-edge operation, with an active High clock enable feature. When enable is High, the input (D) is loaded into the first bit of the shift register, and each bit is shifted to the next highest bit position. In a cascadable shift register configuration (such as SRLC16), the last bit is shifted out on the Q15 output. The bit selected by the 4-bit address appears on the Q output. Dynamic Read Operation The Q output is determined by the 4-bit address. Each time a new address is applied to the 4-input address pins, the new bit position value is available on the Q output after the time delay to access the LUT. This operation is asynchronous and independent of the clock and clock enable signals. 270 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Look-Up Tables as Shift Registers (SRLUTs) Figure 2-57 illustrates the shift and dynamic read operations. CLK CE D tshift Q Q15 Shift Timing Diagram 7 Address Q 10 Position (7) taccess Position (10) taccess Dynamic Length Timing Diagram UG002_C2_011_061300 Figure 2-57: Shift- and Dynamic-Length Timing Diagrams Static Read Operation If the 4-bit address is fixed, the Q output always uses the same bit position. This mode implements any shift register length up 1 to 16 bits in one LUT. Shift register length is (N+1) where N is the input address. The Q output changes synchronously with each shift operation. The previous bit is shifted to the next position and appears on the Q output. Characteristics * * * * * * A shift operation requires one clock edge. Dynamic-length read operations are asynchronous (Q output). Static-length read operations are synchronous (Q output). The data input has a setup-to-clock timing specification. In a cascadable configuration, the Q15 output always contains the last bit value. The Q15 output changes synchronously after each shift operation. Library Primitives and Submodules Eight library primitives are available that offer optional clock enable (CE), inverted clock (CLK) and cascadable output (Q15) combinations. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 271 R Chapter 2: Design Considerations Table 2-28 lists all of the available primitives for synthesis and simulation. Table 2-28: Shift Register Primitives Primitive Length Control Address Inputs Output SRL16 16 bits CLK A3,A2,A1,A0 Q SRL16E 16 bits CLK, CE A3,A2,A1,A0 Q SRL16_1 16 bits CLK A3,A2,A1,A0 Q SRL16E_1 16 bits CLK, CE A3,A2,A1,A0 Q SRLC16 16 bits CLK A3,A2,A1,A0 Q, Q15 SRLC16E 16 bits CLK, CE A3,A2,A1,A0 Q, Q15 SRLC16_1 16 bits CLK A3,A2,A1,A0 Q, Q15 SRLC16E_1 16 bits CLK, CE A3,A2,A1,A0 Q, Q15 In addition to the 16-bit primitives, three submodules that implement 32-bit, 64-bit, and 128-bit cascadable shift registers are provided in VHDL and Verilog code. Table 2-29 lists available submodules. Table 2-29: Shift Register Submodules Submodule Length Control Address Inputs Output SRLC32E_SUBM 32 bits CLK, CE A4,A3,A2,A1,A0 Q, Q31 SRLC64E_SUBM 64 bits CLK, CE A5, A4, A3,A2,A1,A0 Q, Q63 SRLC128E_SUBM 128 bits CLK, CE A6, A5, A4, A3,A2,A1,A0 Q, Q127 The submodules are based on SRLC16E primitives, which are associated with dedicated multiplexers (MUXF5, MUXF6, and so forth). This implementation allows a fast static- and dynamic-length mode, even for very large shift registers. Figure 2-58 represents the cascadable shift registers (32-bit and 64-bit) implemented by the submodules in Table 2-29. 272 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Look-Up Tables as Shift Registers (SRLUTs) A4 Add. A5, A4 5 Add. A3, A2, A1, A0 D A3, A2, A1, A0 D 4 A5 6 D Q D 4 A[3:0] A4 Q A[3:0] CE CE Q15 Q15 SRLC16E SRLC16E Q MUXF5 D 4 MUXF5 Q D 4 A[3:0] CE Q A[3:0] CE Q31 Q15 Q15 SRLC16E SRLC16E Q 32-bit Shift Register MUXF6 D 4 Q A[3:0] CE Q15 SRLC16E MUXF5 D 4 Q A[3:0] CE Q15 Q63 SRLC16E 64-bit Shift Register UG002_C2_008_061300 Figure 2-58: Shift-Register Submodules (32-bit, 64-bit) A 128-bit shift register is built on the same scheme and uses MUXF7 (address input A6). All clock enable (CE) and clock (CLK) inputs are connected to one global clock enable and one clock signal per submodule. If a global static- or dynamic-length mode is not required, the SRLC16E primitive can be cascaded without multiplexers. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 273 R Chapter 2: Design Considerations Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the attribute is attached to the 16-bit shift register instantiation and is copied in the EDIF output file to be compiled by Xilinx Alliance Series tools. The VHDL code simulation uses a generic parameter to pass the attributes. The Verilog code simulation uses a defparam parameter to pass the attributes. The V2_SRL16E shift register instantiation code examples (in VHDL and Verilog) illustrate these techniques (see "VHDL and Verilog Templates" on page 278). V2_SRL16E.vhd and .v files are not a part of the documentation. Port Signals Clock - CLK Either the rising edge or the falling edge of the clock is used for the synchronous shift-in. The data and clock enable input pins have set-up times referenced to the chosen edge of CLK. Data In - D The data input provides new data (one bit) to be shifted into the shift register. Clock Enable - CE (optional) The clock enable pin affects shift functionality. An inactive clock enable pin does not shift data into the shift register and does not write new data. Activating the clock enable allows the data in (D) to be written to the first location and all data to be shifted by one location. When available, new data appears on output pins (Q) and the cascadable output pin (Q15). Address - A0, A1, A2, A3 Address inputs select the bit (range 0 to 15) to be read. The nth bit is available on the output pin (Q). Address inputs have no effect on the cascadable output pin (Q15), which is always the last bit of the shift register (bit 15). Data Out - Q The data output Q provides the data value (1 bit) selected by the address inputs. Data Out - Q15 (optional) The data output Q15 provides the last bit value of the 16-bit shift register. New data becomes available after each shift-in operation. Inverting Control Pins The two control pins (CLK, CE) have an individual inversion option. The default is the rising clock edge and active High clock enable. GSR The global set/reset (GSR) signal has no impact on shift registers. Attributes Content Initialization - INIT The INIT attribute defines the initial shift register contents. The INIT attribute is a hexencoded bit vector with four digits (0000).The left-most hexadecimal digit is the most significant bit. By default the shift register is initialized with all zeros during the device configuration sequence, but any other configuration value can be specified. 274 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Look-Up Tables as Shift Registers (SRLUTs) Location Constraints Each CLB resource has four slices: S0, S1, S2, and S3. As an example, in the bottom left CLB resource, each slice has the coordinates shown in Table 2-30. Table 2-30: Slice Coordinates in the Bottom-Left CLB Resource Slice S3 Slice S2 Slice S1 Slice S0 X1Y1 X1Y0 X0Y1 X0Y0 To constrain placement, shift register instances can have LOC properties attached to them. Each 16-bit shift register fits in one LUT. A 32-bit shift register in static or dynamic address mode fits in one slice (two LUTs and one MUXF5). This shift register can be placed in any slice. A 64-bit shift register in static or dynamic address mode fits in two slices. These slices are either S0 and S1, or S2 and S3. Figure 2-59 illustrates the position of the four slices in a CLB resource. The dedicated CLB shift chain runs from the top slice to the bottom slice. The data input pin must either be in slice S1 or in S3. The address selected as the output pin (Q) is the MUXF6 output. A 128-bit shift register in static or dynamic address mode fits in a four-slice CLB resource. The data input pin has to be in slice S3. The address selected as the output pin (Q) is the MUXF7 output. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 275 R Chapter 2: Design Considerations F8 D LUT F5 LUT Slice S3 b F6 LUT F5 LUT Slice S2 b a F7 (output SRLC128E when 2 F6 outputs are connected) LUT F5 LUT Slice S1 a (output SRLC64E) F6 LUT F5 LUT SRLC64E Q63 Slice S0 CLB UG002_C2_009_120400 Figure 2-59: Shift Register Placement Fully Synchronous Shift Registers All shift-register primitives and submodules do not use the register(s) available in the same slice(s). To implement a fully synchronous read and write shift register, output pin Q must be connected to a flip-flop. Both the shift register and the flip-flop share the same clock, as shown in Figure 2-60. 276 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Look-Up Tables as Shift Registers (SRLUTs) FF D Q SRLC16E D Synchronous Output Q Address CE (Write Enable) Q15 CLK UG002_C2_010_101600 Figure 2-60: Fully Synchronous Shift Register This configuration provides a better timing solution and simplifies the design. Because the flip-flop must be considered to be the last register in the shift-register chain, the static or dynamic address should point to the desired length minus one. If needed, the cascadable output can also be registered in a flip-flop. Static-Length Shift Registers The cascadable16-bit shift register implements any static length mode shift register without the dedicated multiplexers (MUXF5, MUXF6,...). Figure 2-61 illustrates a 40-bit shift register. Only the last SRLC16E primitive needs to have its address inputs tied to "0111". Alternatively, shift register length can be limited to 39 bits (address tied to "0110") and a flip-flop can be used as the last register. (In an SRLC16E primitive, the shift register length is the address input + 1.) D D D D LUT LUT Q15 SRLC16 Q15 SRLC16 D D LUT LUT Q15 SRLC16 Q15 SRLC16 FF "0111" 4 D Q A[3:0] LUT OUT (40-bit SRL) "0110" Q15 SRLC16 D Q A[3:0] LUT D Q OUT (40-bit SRL) Q15 SRLC16 UG002_C2_012_032901 Figure 2-61: 40-bit Static-Length Shift Register UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 277 R Chapter 2: Design Considerations VHDL and Verilog Instantiation VHDL and Verilog instantiation templates are available for all primitives and submodules. In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. The ShiftRegister_C_x (with x = 16, 32, 64, 128, or 256) templates are cascadable modules and instantiate the corresponding SRLCxE primitive (16) or submodule (32, 64, 128, or 256). The ShiftRegister_16 template can be used to instantiate an SRL16 primitive. VHDL and Verilog Templates In template names, the number indicates the number of bits (for example, SHIFT_SELECT_16 is the template for the 16-bit shift register) and the "C" extension means the template is cascadable. The following are templates for primitives: * * SHIFT_REGISTER_16 SHIFT_REGISTER_16_C The following are templates for submodules: * * * SHIFT_REGISTER_32_C (submodule: SRLC32E_SUBM) SHIFT_REGISTER_64_C (submodule: SRLC64E_SUBM) SHIFT_REGISTER_128_C (submodule: SRLC128E_SUBM) The corresponding submodules have to be synthesized with the design. Templates for the SHIFT_REGISTER_16_C module are provided in VHDL and Verilog code as an example. VHDL Template: -- Module: SHIFT_REGISTER_C_16 -- Description: VHDL instantiation template -- CASCADABLE 16-bit shift register with enable (SRLC16E) -- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Components Declarations: -component SRLC16E -- pragma translate_off generic ( -- Shift Register initialization ("0" by default) for functional simulation: INIT : bit_vector := X"0000" ); -- pragma translate_on port ( D : in std_logic; CE : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic; Q15 : out std_logic ); end component; -- Architecture Section: 278 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Large Multiplexers --- Attributes for Shift Register initialization ("0" by default): attribute INIT: string; -attribute INIT of U_SRLC16E: label is "0000"; --- ShiftRegister Instantiation U_SRLC16E: SRLC16E port map ( D => , -- insert input signal CE => , -- insert Clock Enable signal (optional) CLK => , -- insert Clock signal A0 => , -- insert Address 0 signal A1 => , -- insert Address 1 signal A2 => , -- insert Address 2 signal A3 => , -- insert Address 3 signal Q => , -- insert output signal Q15 => -- insert cascadable output signal ); Verilog Template: // Module: SHIFT_REGISTER_16 // Description: Verilog instantiation template // Cascadable 16-bit Shift Register with Clock Enable (SRLC16E) // Device: Virtex-II Pro Family //------------------------------------------------------------------// Syntax for Synopsys FPGA Express // synopsys translate_off defparam //Shift Register initialization ("0" by default) for functional simulation: U_SRLC16E.INIT = 16'h0000; // synopsys translate_on //SelectShiftRegister-II Instantiation SRLC16E U_SRLC16E ( .D(), .A0(), .A1(), .A2(), .A3(), .CLK(), .CE(), .Q(), .Q15() ); // synthesis attribute declarations /* synopsys attribute INIT "0000" */ Large Multiplexers Introduction Virtex-II Pro slices contain dedicated two-input multiplexers (one MUXF5 and one MUXFX per slice). These multiplexers combine the 4-input LUT outputs or the outputs of UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 279 R Chapter 2: Design Considerations other multiplexers. Using the multiplexers MUXF5, MUXF6, MUXF7 and MUXF8 allows to combine 2, 4, 8 and 16 LUTs. Specific routing resources are associated with these 2-input multiplexers to guarantee a fast implementation of any combinatorial function built upon LUTs and MUXFX. The combination of the LUTs and the MUXFX offers an unique solution to the design of wide-input functions. This section illustrates the implementation of large multiplexers up to 32:1. Any Virtex-II Pro slice can implement a 4:1 multiplexer, any CLB can implement a 16:1 multiplexer, and 2 CLBs can implement a 32:1 multiplexer. Such multiplexers are just one example of wide-input combinatorial function taking advantage of the MUXFX feature. Many other logic functions can be mapped in the LUT and MUXFX features. This section provides generic VHDL and Verilog reference code implementing multiplexers. These submodules are built from LUTs and the dedicated MUXF5, MUXF6, MUXF7, and MUXF8 multiplexers. To automatically generate large multiplexers using these dedicated elements, use the CORE Generator Bit Multiplexer and Bus Multiplexer modules. For applications like comparators, encoder-decoders or "case" statement in VHDL or Verilog, these resources offer an optimal solution. Virtex-II Pro CLB Resources Slice Multiplexers Each Virtex-II Pro slice has a MUXF5 to combine the outputs of the 2 LUTs and an extra MUXFX. Figure 2-62 illustrates a combinatorial function with up to 9 inputs in one slice. MUXFX 4 LUT Reg OUT_F5 MUXF5 4 LUT Reg S_F5 Any Slice UG002_C2_016_081500 Figure 2-62: LUTs and MUXF5 in a Slice Each Virtex-II Pro CLB contains 4 slices. The second MUXFX implements a MUXF6, MUXF7 or MUXF8 according to the position of the slice in the CLB. These MUXFX are designed to allow LUTs combination up to 16 LUTs in two adjacent CLBs. 280 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Large Multiplexers Figure 2-63 shows the relative position of the slices in the CLB. MUXF8 Slice S3 MUXF6 Slice S2 MUXF7 Slice S1 MUXF6 Slice S0 CLB UG002_C2_017_081600 Figure 2-63: Slice Positions in a CLB Slices S0 and S2 have a MUXF6, designed to combine the outputs of two MUXF5 resources. Figure 2-64 illustrates a combinatorial function up to 18 inputs in the slices S0 and S1, or in the slices S2 and S3. Slice S1 (or S3) MUXFX 4 LUT Reg MUXF5 4 LUT Reg S_F6 OUT_F6 MUXF6 4 LUT Reg MUXF5 4 LUT Reg S_F5 Slice S0 (or S2) Figure 2-64: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook UG002_C2_018_081800 LUTs and (MUXF5 and MUXF6) in Two Slices www.xilinx.com 1-800-255-7778 281 R Chapter 2: Design Considerations The slice S1 has a MUXF7, designed to combine the outputs of two MUXF6. Figure 2-65 illustrates a combinatorial function up to 35 inputs in a Virtex-II Pro CLB. Slice S3 MUXF8 4 LUT Reg MUXF5 4 LUT Reg S_F5 S_F6 Slice S2 MUXF6 4 LUT Reg MUXF5 4 LUT Reg S_F5 S_F7 Slice S1 OUT_F MUXF7 4 LUT Reg MUXF5 4 LUT Reg S_F5 S_F6 Slice S0 MUXF6 4 LUT Reg MUXF5 4 LUT Reg S_F5 UG002_C2_019_081600 Figure 2-65: LUTs and (MUXF5, MUXF6, and MUXF7) in One CLB 282 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Large Multiplexers The slice S3 of each CLB has a MUXF8. combinatorial functions of up to 68 inputs fit in two CLBs as shown in Figure 2-66. The outputs of two MUXF7 are combined through dedicated routing resources between two adjacent CLBs in a column. MUXF8 Slice S3 MUXF6 Slice S2 MUXF7 Slice S1 MUXF6 Slice S0 CLB MUXF8 OUT_F8 Slice S3 MUXF6 Slice S2 MUXF7 Slice S1 MUXF6 Slice S0 CLB UG002_C2_020_081600 Figure 2-66: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook MUXF8 Combining Two Adjacent CLBs www.xilinx.com 1-800-255-7778 283 R Chapter 2: Design Considerations Wide-Input Multiplexers Each LUT can implement a 2:1 multiplexer. In each slice, the MUXF5 and two LUTs can implement a 4:1 multiplexer. As shown in Figure 2-67, the MUXF6 and two slices can implement a 8:1 multiplexer. The MUFXF7 and the four slices of any CLB can implement a 16:1 and the MUXF8 and two CLBs can implement a 32:1 multiplexer. DATA[0] DATA[1] LUT 8:1 (S2 & S3) DATA[7:0] F5 DATA[2] DATA[3] LUT 16:1 output S1 8:1 Output DATA[4] DATA[5] F7 F6 LUT F5 8:1 (S0 & S1) DATA[15:8] DATA[6] DATA[7] LUT S0 SELECT[0] SELECT[1] SELECT[2:0] SELECT[2] SELECT[3] CLB 8:1 MUX 16:1 MUX UG002_C2_015_081800 Figure 2-67: 8:1 and 16:1 Multiplexers Characteristics * * 284 Implementation in one level of logic (LUT) and dedicated MUXFX Full combinatorial path www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Large Multiplexers Library Primitives and Submodules Four library primitives are available that offer access to the dedicated MUXFX in each slice. In the example shown in Table 2-31, MUXF7 is available only in slice S1. Table 2-31: MUXFX Resources Primitive Slice Control Input Output MUXF5 S0, S1, S2, S3 S I0, I1 O MUXF6 S0, S2 S I0, I1 O MUXF7 S1 S I0, I1 O MUXF8 S3 S I0, I1 O In addition to the primitives, five submodules that implement multiplexers from 2:1 to 32:1 are provided in VHDL and Verilog code. Synthesis tools can automatically infer the above primitives (MUXF5, MUXF6, MUXF7, and MUXF8); however, the submodules described in this section used instantiation of the new MUXFX to guarantee an optimized result. Table 2-32 lists available submodules: Table 2-32: Available Submodules Submodule Multiplexer Control Input Output MUX_2_1_SUBM 2:1 SELECT_I DATA_I[1:0] DATA_O MUX_4_1_SUBM 4:1 SELECT_I[1:0] DATA_I[3:0] DATA_O MUX_8_1_SUBM 8:1 SELECT_I[2:0] DATA_I[8:0] DATA_O MUX_16_1_SUBM 16:1 SELECT_I[3:0] DATA_I[15:0] DATA_O MUX_32_1_SUBM 32:1 SELECT_I[4:0] DATA_I[31:0] DATA_O Port Signals Data In - DATA_I The data input provides the data to be selected by the SELECT_I signal(s). Control In - SELECT_I The select input signal or bus determines the DATA_I signal to be connected to the output DATA_O. For example, the MUX_4_1_SUBM multiplexer has a 2-bit SELECT_I bus and a 4-bit DATA_I bus. Table 2-33 shows the DATA_I selected for each SELECT_I value. Table 2-33: Selected Inputs SELECT_I[1:0] DATA_O 00 DATA_I[0] 01 DATA_I[1] 10 DATA_I[2] 11 DATA_I[3] Data Out - DATA_O The data output O provides the data value (1 bit) selected by the control inputs. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 285 R Chapter 2: Design Considerations Applications Multiplexers are used in various applications. These are often inferred by synthesis tools when a "case" statement is used (see the example below). Comparators, encoder-decoders and wide-input combinatorial functions are optimized when they are based on one level of LUTs and dedicated MUXFX resources of the Virtex-II Pro CLBs. VHDL and Verilog Instantiation The primitives (MUXF5, MUXF6, and so forth) can be instantiated in VHDL or Verilog code, to design wide-input functions. The submodules (MUX_2_1_SUBM, MUX_4_1_SUBM, and so forth) can be instantiated in VHDL or Verilog code to implement multiplexers. However the corresponding submodule must be added to the design directory as hierarchical submodule. For example, if a module is using the MUX_16_1_SUBM, the MUX_16_1_SUBM.vhd file (VHDL code) or MUX_16_1_SUBM.v file (Verilog code) must be compiled with the design source code. The submodule code can also be "cut and pasted" into the designer source code. VHDL and Verilog Submodules VHDL and Verilog submodules are available to implement multiplexers up to 32:1. They illustrate how to design with the MUXFX resources. When synthesis infers the corresponding MUXFX resource(s), the VHDL or Verilog code is behavioral code ("case" statement). Otherwise, the equivalent "case" statement is provided in comments and the correct MUXFX are instantiated. However, most synthesis tools support the inference of all of the MUXFX. The following examples can be used as guidelines for designing other wide-input functions. The following submodules are available: * * * * * MUX_2_1_SUBM (behavioral code) MUX_4_1_SUBM MUX_8_1_SUBM MUX_16_1_SUBM MUX_32_1_SUBM The corresponding submodules have to be synthesized with the design The submodule MUX_16_1_SUBM in VHDL and Verilog are provided as example. VHDL Template -- Module: MUX_16_1_SUBM -- Description: Multiplexer 16:1 --- Device: Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; -- Syntax for Synopsys FPGA Express -- pragma translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- pragma translate_on entity MUX_16_1_SUBM is port ( DATA_I: in std_logic_vector (15 downto 0); SELECT_I: in std_logic_vector (3 downto 0); DATA_O: out std_logic ); 286 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Large Multiplexers end MUX_16_1_SUBM; architecture MUX_16_1_SUBM_arch of MUX_16_1_SUBM is -- Component Declarations: component MUXF7 port ( I0: in std_logic; I1: in std_logic; S: in std_logic; O: out std_logic ); end component; --- Signal Declarations: signal DATA_MSB : std_logic; signal DATA_LSB : std_logic; -begin --- If synthesis tools support MUXF7 : --SELECT_PROCESS: process (SELECT_I, DATA_I) --begin --case SELECT_I is -- when "0000" => DATA_O <= DATA_I (0); -- when "0001" => DATA_O <= DATA_I (1); -- when "0010" => DATA_O <= DATA_I (2); -- when "0011" => DATA_O <= DATA_I (3); -- when "0100" => DATA_O <= DATA_I (4); -- when "0101" => DATA_O <= DATA_I (5); -- when "0110" => DATA_O <= DATA_I (6); -- when "0111" => DATA_O <= DATA_I (7); -- when "1000" => DATA_O <= DATA_I (8); -- when "1001" => DATA_O <= DATA_I (9); -- when "1010" => DATA_O <= DATA_I (10); -- when "1011" => DATA_O <= DATA_I (11); -- when "1100" => DATA_O <= DATA_I (12); -- when "1101" => DATA_O <= DATA_I (13); -- when "1110" => DATA_O <= DATA_I (14); -- when "1111" => DATA_O <= DATA_I (15); -- when others => DATA_O <= 'X'; --end case; --end process SELECT_PROCESS; --- If synthesis tools DO NOT support MUXF7 : SELECT_PROCESS_LSB: process (SELECT_I, DATA_I) begin case SELECT_I (2 downto 0) is when "000" => DATA_LSB <= DATA_I (0); when "001" => DATA_LSB <= DATA_I (1); when "010" => DATA_LSB <= DATA_I (2); when "011" => DATA_LSB <= DATA_I (3); when "100" => DATA_LSB <= DATA_I (4); when "101" => DATA_LSB <= DATA_I (5); when "110" => DATA_LSB <= DATA_I (6); when "111" => DATA_LSB <= DATA_I (7); when others => DATA_LSB <= 'X'; end case; end process SELECT_PROCESS_LSB; -SELECT_PROCESS_MSB: process (SELECT_I, DATA_I) begin case SELECT_I (2 downto 0) is UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 287 R Chapter 2: Design Considerations when "000" => DATA_MSB <= DATA_I when "001" => DATA_MSB <= DATA_I when "010" => DATA_MSB <= DATA_I when "011" => DATA_MSB <= DATA_I when "100" => DATA_MSB <= DATA_I when "101" => DATA_MSB <= DATA_I when "110" => DATA_MSB <= DATA_I when "111" => DATA_MSB <= DATA_I when others => DATA_MSB <= 'X'; end case; end process SELECT_PROCESS_MSB; --- MUXF7 instantiation U_MUXF7: MUXF7 port map ( I0 => DATA_LSB, I1 => DATA_MSB, S => SELECT_I (3), O => DATA_O ); -end MUX_16_1_SUBM_arch; -- (8); (9); (10); (11); (12); (13); (14); (15); Verilog Template // Module: MUX_16_1_SUBM // // Description: Multiplexer 16:1 // Device: Virtex-II Pro Family //------------------------------------------------------------------// module MUX_16_1_SUBM (DATA_I, SELECT_I, DATA_O); input [15:0]DATA_I; input [3:0]SELECT_I; output DATA_O; wire [2:0]SELECT; reg DATA_LSB; reg DATA_MSB; assign SELECT[2:0] = SELECT_I[2:0]; /* //If synthesis tools supports MUXF7 : always @ (DATA_I or SELECT_I) case (SELECT_I) 4'b0000 : DATA_O <= 4'b0001 : DATA_O <= 4'b0010 : DATA_O <= 4'b0011 : DATA_O <= 4'b0100 : DATA_O <= 4'b0101 : DATA_O <= 4'b0110 : DATA_O <= 4'b0111 : DATA_O <= 4'b1000 : DATA_O <= 4'b1001 : DATA_O <= 4'b1010 : DATA_O <= 4'b1011 : DATA_O <= 288 DATA_I[0]; DATA_I[1]; DATA_I[2]; DATA_I[3]; DATA_I[4]; DATA_I[5]; DATA_I[6]; DATA_I[7]; DATA_I[8]; DATA_I[9]; DATA_I[10]; DATA_I[11]; www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Sum of Products (SOP) Logic 4'b1100 : 4'b1101 : 4'b1110 : 4'b1111 : default : endcase */ DATA_O DATA_O DATA_O DATA_O DATA_O <= <= <= <= <= DATA_I[12]; DATA_I[13]; DATA_I[14]; DATA_I[15]; 1'bx; always @ (SELECT or DATA_I) case (SELECT) 3'b000 : DATA_LSB <= DATA_I[0]; 3'b001 : DATA_LSB <= DATA_I[1]; 3'b010 : DATA_LSB <= DATA_I[2]; 3'b011 : DATA_LSB <= DATA_I[3]; 3'b100 : DATA_LSB <= DATA_I[4]; 3'b101 : DATA_LSB <= DATA_I[5]; 3'b110 : DATA_LSB <= DATA_I[6]; 3'b111 : DATA_LSB <= DATA_I[7]; default : DATA_LSB <= 1'bx; endcase always @ (SELECT or DATA_I) case (SELECT) 3'b000 : DATA_MSB <= DATA_I[8]; 3'b001 : DATA_MSB <= DATA_I[9]; 3'b010 : DATA_MSB <= DATA_I[10]; 3'b011 : DATA_MSB <= DATA_I[11]; 3'b100 : DATA_MSB <= DATA_I[12]; 3'b101 : DATA_MSB <= DATA_I[13]; 3'b110 : DATA_MSB <= DATA_I[14]; 3'b111 : DATA_MSB <= DATA_I[15]; default : DATA_MSB <= 1'bx; endcase // MUXF7 instantiation MUXF7 U_MUXF7 (.I0(DATA_LSB), .I1(DATA_MSB), .S(SELECT_I[3]), .O(DATA_O) ); endmodule // */ Sum of Products (SOP) Logic Introduction Virtex-II Pro slices contain a dedicated two-input multiplexer (MUXCY) and a two-input OR gate (ORCY) to perform operations involving wide AND and OR gates. These combine the four-input LUT outputs. These gates can be cascaded in a chain to provide the wide AND functionality across slices. The output from the cascaded AND gates can then be combined with the dedicated ORCY to produce the Sum of Products (SOP). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 289 R Chapter 2: Design Considerations Virtex-II Pro CLB Resources Each Virtex-II Pro slice has a MUXCY, which uses the output from the LUTs as a SELECT signal. Depending on the width of data desired, several slices can be used to provide the SOP output. Figure 2-68 illustrates the logic involved in designing a 16-input AND gate. It utilizes the 4-input LUT to provide the necessary SELECT signal for the MUXCY. Only when all of the input signals are High, can the VCC at the bottom reach the output. This use of carry logic helps to perform AND functions at high speed and saves logic resources. ORCY 4 MUXCY 0 1 LUT Slice 4 MUXCY LUT 0 4 1 MUXCY 0 1 LUT Slice 4 MUXCY LUT 0 1 VCC UG002_c2_51_120400 Figure 2-68: Implementing a 16-bit Wide AND Gate Using MUXCY & ORCY The output from the chain of AND gates is passed as one of the inputs of the dedicated OR gate, ORCY. To calculate the SOP, these AND chains can be cascaded vertically across several CLBs, depending on the width of the input data. Figure 2-69 illustrates how the AND outputs are then passed in through the ORCY gates in a horizontal cascade, the sum of which is the Sum of Products. 290 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Sum of Products (SOP) Logic ORCY ORCY SOP 4 LUT MUXCY 4 LUT 4 LUT MUXCY 4 LUT MUXCY 4 LUT Slice 3 4 LUT MUXCY 4 LUT MUXCY Slice 3 Slice 2 4 LUT 4 LUT Slice 2 MUXCY Vcc ORCY ORCY MUXCY 4 LUT LUT 4 LUT MUXCY MUXCY 4 LUT MUXCY 4 LUT MUXCY LUT 4 LUT Vcc Slice 1 Slice 0 4 MUXCY MUXCY Slice 1 4 MUXCY Slice 0 MUXCY MUXCY CLB Vcc Vcc CLB UG002_c2_42_120400 Figure 2-69: 64-bit Input SOP Design Port Signals AND_WIDTH Parameter The width of each AND gate used in the cascade. PROD_TERM Parameter The number of AND gates used along each vertical cascade. AND_IN Parameter Data input to the AND gates. The total width of data is calculated from the product of AND_WIDTH and PROD_TERM SOP_OUT Parameter The Sum of Products (SOP) output data from the cascade chain. Applications These logic gates can be used in various applications involving very wide AND gates and Sum of Products (SOP) functions. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 291 R Chapter 2: Design Considerations VHDL and Verilog Instantiation To implement wide-input AND functions, MUXCY and ORCY primitives can be instantiated in VHDL or Verilog code. The submodule code provided can be used to implement wide-input AND gates for any width of input data. VHDL and Verilog Submodules VHDL and Verilog submodules are available to implement the cascade chain of wideinput AND gates and OR gates to calculate the Sum of Products (SOP). The VHDL module provided uses a generic case, where the width of data and the product terms can be specified in the case. The Verilog module provides a 64-bit input example, using four wide AND chains, each of which handle 16 bits of data. VHDL Templates -- Module : AND_CHAIN -- Description : 16 input AND gate --- Device : Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.ALL; entity AND_CHAIN is generic ( input_width : integer); --must be a 4x value port ( data_in : in std_logic_vector( input_width-1 downto 0); carry_in : in std_logic; out_andor_chain : out std_logic); end AND_CHAIN; architecture AND_CHAIN_arch of AND_CHAIN is component ORCY port( i : std_logic; ci : in std_logic; o : out std_logic); end component; component AND_LOGIC port( sel_data : in std_logic_vector(3 downto 0); data_cin : in std_logic; data_out : out std_logic); end component; signal VCC, GND : std_logic; signal cout : std_logic_vector(input_width/4 downto 0); signal out_and_chain : std_logic; begin VCC <= '1'; GND <= '0'; --initialization of first input for MUXCY cout(0) <= VCC; and_chain_x : for i in (input_width/4) - 1 downto 0 generate 292 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Sum of Products (SOP) Logic AND_LOGIC_inst : AND_LOGIC port map ( sel_data => data_in((4 * i + 3) downto (4 * i)), data_cin => cout(i), data_out => cout(i + 1)); end generate; out_and_chain <= cout(input_width/4); orcy_inst : ORCY port map( i => out_and_chain, ci => carry_in, o => out_andor_chain); end AND_CHAIN_arch; ---------------------------------------------------------------------- Module AND_LOGIC -- Description : 4-input AND gate --- Device : Virtex-II Pro Family --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.ALL; entity AND_LOGIC port( sel_data : signal for MUXCY data_cin : data_out : end AND_LOGIC; is in std_logic_vector(3 downto 0); -- data for select from LUT in std_logic; -- result from previous stage out std_logic); architecture AND_LOGIC_arch of AND_LOGIC is component MUXCY port( DI : in std_logic; CI : in std_logic; s : in std_logic; o : out std_logic); end component; signal GND : std_logic; signal sel:std_logic; begin GND <= '0'; sel <= sel_data(0) and sel_data(1) and sel_data(2) and sel_data(3); --Wide AND gate using MUXCY MUX : MUXCY port map ( DI => GND, CI => data_cin, s => sel, o => data_out); end AND_LOGIC_arch; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 293 R Chapter 2: Design Considerations ---------------------------------------------------------------------- Module : SOP_SUBM -- Description : Implementing SOP using MUXCY and ORCY --- Device : Virtex-II Pro Family --------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; --library UNISIM; --use UNISIM.VCOMPONENTS.ALL; entity SOP_SUBM is generic( and_width : integer :=16 ; prod_term : integer := 4 ); port( and_in : in std_logic_vector(and_width * prod_term - 1 downto 0); sop_out : out std_logic); end SOP_SUBM; architecture SOP_SUBM_arch of SOP_SUBM is component AND_CHAIN generic ( input_width : integer); --must be a 4x value port ( data_in : in std_logic_vector( input_width-1 downto 0); carry_in : in std_logic; out_andor_chain : out std_logic); end component; signal VCC, GND : std_logic; signal carry : std_logic_vector(prod_term downto 0); begin VCC <= '1'; GND <= '0'; carry(0) <= GND; andor_inst : for i in 0 to (prod_term - 1) generate and_chainx : AND_CHAIN generic map( input_width => and_width) port map( data_in => and_in((and_width * i + (and_width -1)) downto (and_width * i)), carry_in => carry(i), out_andor_chain => carry(i + 1)); end generate; sop_out <= carry(prod_term); end SOP_SUBM_arch; 294 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Sum of Products (SOP) Logic Verilog Templates // Module : AND_CHAIN // Description : 16 input AND gate // // Device : Virtex-II Family //------------------------------------------------------------------module AND_CHAIN(data_in, carry_in, out_andor_chain); input [15:0] data_in; input carry_in; output out_andor_chain; wire VCC = 1'b1; wire out_and_chain; wire dat_out1, data_out2, data_out3; AND_LOGIC_OR u4(.sel_data(data_in[15:12]), .data_cin(data_out3), .carry_in(carry_in), .data_out(out_andor_chain)); AND_LOGIC u3(.sel_data(data_in[11:8]), .data_cin(data_out2), .data_out(data_out3)); AND_LOGIC u2(.sel_data(data_in[7:4]), .data_cin(data_out1), .data_out(data_out2)); AND_LOGIC u1(.sel_data(data_in[3:0]), .data_cin(VCC), .data_out(data_out1)); endmodule //------------------------------------------------------------------// Module AND_LOGIC // Description : 4-input AND gate // // Device : Virtex-II Family //------------------------------------------------------------------// Module : init_and // module AND_LOGIC(sel_data, data_cin, data_out); input[3:0] sel_data; input data_cin; output data_out; wire GND = 1'b0; wire VCC = 1'b1; wire and_out; assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0]; MUXCY muxcy_inst (.DI(GND), .CI(data_cin), .S(and_out), .O(data_out)); endmodule // Module AND_LOGIC + ORCY module AND_LOGIC_OR(sel_data, data_cin, carry_in, data_out); input[3:0] sel_data; input data_cin; input carry_in; output data_out; wire data_mux_out; wire GND = 1'b0; wire VCC = 1'b1; wire and_out; assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0]; MUXCY muxcy_inst (.DI(GND), .CI(data_cin), .S(and_out), .O(data_mux_out)) /* synthesis RLOC="x0y0" */; ORCY u5(.I(carry_in), .CI(data_mux_out), .O(data_out)) /* synthesis RLOC="x0y0" */; endmodule UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 295 R Chapter 2: Design Considerations //------------------------------------------------------------------// Module : SOP_SUBM // Description : Implementing SOP using MUXCY and ORCY // // Device : Virtex-II Family //------------------------------------------------------------------module SOP_SUBM(and_in, sop_out); input [63:0] and_in; output sop_out; wire out_andor_chain1, out_andor_chain2, out_andor_chain3; wire GND = 1'b0; AND_CHAIN u4(.data_in(and_in[63:48]), .carry_in(out_andor_chain3), .out_andor_chain(sop_out)); AND_CHAIN u3(.data_in(and_in[47:32]), .carry_in(out_andor_chain2), .out_andor_chain(out_andor_chain3)); AND_CHAIN u2(.data_in(and_in[31:16]), .carry_in(out_andor_chain1), .out_andor_chain(out_andor_chain2)); AND_CHAIN u1(.data_in(and_in[15:0]), .carry_in(GND), .out_andor_chain(out_andor_chain1)); endmodule Embedded Multipliers Introduction Virtex-II Pro devices feature a large number of embedded 18-bit X 18-bit two'scomplement embedded multipliers. The embedded multipliers offer fast, efficient means to create 18-bit signed by 18-bit signed multiplication products. The multiplier blocks share routing resources with the Block SelectRAM memory, allowing for increased efficiency for many applications. Cascading of multipliers can be implemented with additional logic resources in local Virtex-II Pro slices. Applications such as signed-signed, signed-unsigned, and unsigned-unsigned multiplication, logical, arithmetic, and barrel shifters, two's-complement and magnitude return are easily implemented. Using the CORE Generator, the designer can quickly generate multipliers that make use of the embedded 18-bit x 18-bit two's-complement multipliers (V2.0 or later) of the Multiplier core for Virtex-II Pro devices. Two's-Complement Signed Multiplier Data Flow Each embedded multiplier block (MULT18X18 primitive) supports two independent dynamic data input ports: 18-bit signed or 17-bit unsigned. The MULT18X18 primitive is illustrated in Figure 2-70. 296 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Embedded Multipliers In addition, efficient cascading of multipliers up to 35-bit X 35-bit signed can be accomplished by using 4 embedded multipliers, one 36-bit adder, and one 53-bit adder. See Figure 2-71. 18 A 36 P 18 B MULT18X18 UG002_C2_025_082100 Figure 2-70: Embedded Multiplier Library Primitives and Submodules One library primitive (MULT18X18) is available. Table 2-34 lists the attributes of this primitive. Table 2-34: Embedded Multiplier Primitive Primitive MULT18X18 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook A width B width P width Signed/Unsigned 18 18 36 Signed (2's complement) www.xilinx.com 1-800-255-7778 297 R Chapter 2: Design Considerations In addition to the primitive, 15 submodules that implement various widths of signed and unsigned multipliers and two's-complement return functions are provided in VHDL and Verilog code. Multipliers using cascaded MULT18X18 primitives are included with registers between stages causing three cycles of latency. Multipliers that make use of the embedded Virtex-II Pro 18-bit by 18-bit two's complement multipliers can be easily generated using V2.0 of the CORE Generator Multiplier module. Table 2-35 lists cascaded multiplier submodules. Table 2-35: Embedded Multiplier Submodules - Cascaded MULT18X18 Submodule A Width B Width P Width Signed/Unsigned MULT35X35_S 35 35 70 Signed MULT34X34_U 34 34 68 Unsigned Figure 2-71 represents the cascaded scheme used to implement a 35-bit by 35-bit signed multiplier utilizing four embedded multipliers and two adders. A[34:17] B[34:17] A P B MULT 18 x 18 36 36 36 O,A[16:0] O,B[16:0] A P B MULT 18 x 18 34 34 69:34 34 33:0 + A[34:17] O,B[16:0] A P B MULT 18 x 18 36 B[34:17] A P B MULT 18x18 36 70 36 + O,A[16:0] 70 36 36 36 36 36 0 * * 0 69 52 51:17 16 * * 0 UG002_C2_021_081800 Figure 2-71: MULT35X35_S Submodule The fixed adder is 53 bits wide (17 LSBs are always 0 on one input). The 34-bit by 34-bit unsigned submodule is constructed in a similar manner with the most significant bit on each operand being tied to logic low. Table 2-35 lists multipliers and two's-complement return functions that utilize one MULT18X18 primitive and are not registered. 298 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Embedded Multipliers Table 2-36: Embedded Multiplier Submodules - Single MULT18X18 Submodule A width B width P width Signed/Unsigned MULT17X17_U 17 17 34 Unsigned MULT8X8_S 8 8 16 Signed MULT8X8_U 8 8 16 Unsigned MULT4X4_S 4 4 8 Signed MULT4X4_U 4 4 8 Unsigned MULT_6X6S_5X5U 6 5 6 5 12 10 Signed Unsigned MULT_5X5S_6X6U 5 6 5 6 10 12 Signed Unsigned MULT_5X5U_5X5U 5 5 5 5 10 10 Unsigned Unsigned MULT_4X4S_7X7U 4 7 4 7 8 14 Signed Unsigned MULT_4X4S_3X3S 4 3 4 3 8 6 Signed Signed TWOS_CMP18 18 - 18 - TWOS_CMP9 9 - 9 - MAGNTD_18 18 - 17 - Multipliers of form MULT_aXaS_bXbU use one embedded multiplier to implement two multipliers with separate outputs. The submodules listed above use optimized pin assignments to achieve shortest possible through-delay. Figure 2-72 and Figure 2-73 represent 4-bit by 4-bit signed multiplier and 4-bit by 4-bit unsigned multiplier implementations, respectively. O * * * O A3 A3 A3 A3 A[3:0] 17 * * * 8 7 6 A 5 4 [3:0] 35:8 P O * * * O B3 B3 B3 B3 B[3:0] 7:0 NC P[7:0] 17 * * * 8 7 6 B 5 4 [3:0] MULT 18 x 18 UG002_C2_022_032901 Figure 2-72: MULT4X4_S Submodule UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 299 R Chapter 2: Design Considerations O * * * O A 3:0 17 * * * 4 A 3:0 P O * * * O B 3:0 17 * * * 4 35:8 7:0 NC P 7:0 B 3:0 MULT 18 x 18 UG002_C2_023_081600 Figure 2-73: MULT4X4_U Submodule Submodule MAGNTD_18 performs a magnitude return (i.e., absolute value) of a two'scomplement number. An incoming negative number returns with a positive number, while an incoming positive number remains unchanged. Submodules TWOS_CMP18 and TWOS_CMP9 perform a two's-complement return function. The incoming number in two's-complement form (either signed or unsigned) is complemented when the DO_COMP pin is asserted High. Additional slice logic can be used with these submodules to efficiently convert sign-magnitude to two's-complement or vice-versa. Figure 2-74 shows the connections to a MULT18X18 to create the submodule TWOS_CMP9. X000 [17:9] A [8:0] [8:0] A NC [35:9] P X000 [17:9] X111 [8:0] P [8:0] [8:0] B MULT18X18 UG002_C2_027_081800 Figure 2-74: TWOS_CMP9 Submodule Two Multipliers in a Single Primitive Two multipliers can be implemented in a single primitive. For simplified illustration purposes, an assumption of two squares being implemented in the same MULT18X18 primitive is used. The following equation shows the form of the multiplication. Two Multipliers per Primitive: (X * 2n + Y)(X * 2n + Y) = (X2 * 22n) + (Y2) + (XY * 2n+1) (X * 2n) is the input X appearing on the MSBs while Y appears on the LSBs to form the value (X * 2n + Y). Two multipliers can coexist in one MULT18X18 primitive, if the conditions in the following inequalities are met when neither X nor Y are 0. 300 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Embedded Multipliers Inequality Conditions for Two Multipliers per Primitive: (X2 * 22n)min > (XY * 2n+1)max, (XY * 2n+1)min > (Y2)max For values 0 on X or Y, the equation becomes: X2 * 22n {Y=0} Y2 {X=0} 0 {X=0, Y=0} Figure 2-75 represents the MULT_6X6S_5X5U submodule. A_6S 17:12 X00 11:5 A_5U A 4:0 35:24 P P_6S 23:10 NC 9:0 B_6S P_5U 17:12 X00 11:5 B_5U 4:0 B MULT 18 x 18 UG002_C2_024_081800 Figure 2-75: MULT_6X6S_5X5U -- Connections to a MULT18X18 Primitive Table 2-37 shows values for X and Y where these conditions are met. Table 2-37: Two Multipliers per MULT18X18 Allowable Sizes X*X Y*Y Signed Size Unsigned Size Signed Size Unsigned Size 7X7 6X6 - 4X4 6X6 5X5 - 5X5 5X5 4X4 3X3 6X6 4X4 3X3 3X3 7X7 3X3 2X2 4X4 8X8 VHDL and Verilog Instantiation VHDL and Verilog instantiation templates are available as examples of primitives and submodules (see VHDL and Verilog Templates, page 302). In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signals names. Port Signals Data In - A The data input provides new data (up to 18 bits) to be used as one of the multiplication operands. Data In - B The data input provides new data (up to 18 bits) to be used as one of the multiplication operands. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 301 R Chapter 2: Design Considerations Data Out - P The data output bus P provides the data value (up to 36 bits) of two's-complement multiplication for operands A and B. Location Constraints Each embedded multiplier has location coordinates of the form XrowYcolumn. To constrain placement, multiplier instances can have LOC properties attached to MULT18X18 embedded multiplier instances can have LOC properties attached to them to constrain placement. MULT18X18 placement locations differ from the convention used for naming CLB locations, allowing LOC properties to transfer easily from array to array. The LOC properties use the following form: LOC = MULT18X18_X#Y# For example, MULT18X18_X0Y0 is the bottom-left MULT18X18 location on the device. VHDL and Verilog Templates VHDL and Verilog templates are available for the primitive and submodules. The following is a template for the primitive: * SIGNED_MULT_18X18 (primitive: MULT18X18) The following are templates for submodules: * * * * * * * * * * * * * * * SIGNED_MULT_35X35 (submodule: MULT35X35_S) UNSIGNED_MULT_34X34 (submodule: MULT34X34_U) UNSIGNED_MULT_17X17 (submodule: MULT17X17_U) SIGNED_MULT_8X8 (submodule: MULT8X8_S) UNSIGNED_MULT_8X8 (submodule: MULT8X8_U) SIGNED_MULT_4X4 (submodule: MULT4X4_S) UNSIGNED_MULT_4X4 (submodule: MULT4X4_U) DUAL_MULT_6X6S_5X5U (submodule: MULT_6X6S_5X5U) DUAL_MULT_5X5S_6X6U (submodule: MULT_5X5S_6X6U) DUAL_MULT_5X5U_5X5U (submodule: MULT_5X5U_5X5U) DUAL_MULT_4X4S_7X7U (submodule: MULT_4X4S_7X7U) DUAL_MULT_4X4S_3X3S (submodule: MULT_4X4S_3X3S) TWOS_COMPLEMENTER_18BIT (submodule: TWOS_CMP18) TWOS_COMPLEMENTER_9BIT (submodule: TWOS_CMP9) MAGNITUDE_18BIT (submodule: MAGNTD_18) The corresponding submodules have to be synthesized with the design. Templates for the SIGNED_MULT_18X18 module are provided in VHDL and Verilog code as an example. 302 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources VHDL Template: -- Module: SIGNED_MULT_18X18 -- Description: VHDL instantiation template -- 18-bit X 18-bit embedded signed multiplier (asynchronous) --- Device: Virtex-II Pro Family ---------------------------------------------------------------------- Components Declarations component MULT18X18 port( A : in std_logic_vector (17 downto 0); B : in std_logic_vector (17 downto 0); P : out std_logic_vector (35 downto 0) ); end component; --- Architecture Section -U_MULT18X18 : MULT18X18 port map ( A => , -- insert input signal #1 B => , -- insert input signal #2 P => -- insert output signal ); Verilog Template: // Module: SIGNED_MULT_18X18 // Description: Verilog instantiation template // 18-bit X 18-bit embedded signed multiplier (asynchronous) // // Device: Virtex-II Pro Family //------------------------------------------------------------------// Instantiation Section // MULT18X18 U_MULT18X18 ( .A () , // insert input signal #1 .B () , // insert input signal #2 .P () // insert output signal ); Single-Ended SelectI/O Resources Summary The Virtex-II Pro FPGA Series includes a highly configurable, high-performance singleended SelectI/O resource that supports a wide variety of I/O standards. The SelectI/O resource includes a robust set of features, including programmable control of output drive strength, slew rate, and input delay and hold time. Taking advantage of the flexibility of SelectI/O features and the design considerations described in this document can improve and simplify system-level design. Introduction As FPGAs continue to grow in size and capacity, the larger and more complex systems designed for them demand an increased variety of I/O standards. Furthermore, as system clock speeds continue to increase, the need for high-performance I/O becomes more UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 303 R Chapter 2: Design Considerations important. Chip-to-chip delays have an increasingly substantial impact on overall system speed. The task of achieving the desired system performance is becoming more difficult with the proliferation of low-voltage I/O standards. SelectI/O resolves this potential problem by providing a highly configurable, high-performance alternative to I/O resources used in more conventional programmable devices. Virtex-II Pro SelectI/O blocks can support up to 19 single-ended I/O standards. Supporting such a variety of I/O standards allows support for a wide variety of applications. Each Input/Output Block (IOB) includes six registers, two each from the input, output, and 3-state signals within the IOB. These registers are optionally configured as either a D-type flip-flop or as a level-sensitive latch. The purpose of having six registers is to allow designers to design double-data-rate (DDR) logic in the I/O blocks. Each pair of the flipflop (FF) has different clocks so that the flip-flops can be driven by two clocks with a 180degree phase shift to achieve DDR. All I/O flip-flops still share the same reset/preset line. The input buffer has an optional delay element used to guarantee a zero hold time requirement for input signals registered within the IOB. Virtex-II Pro SelectI/O features also provide dedicated resources for input reference voltage (VREF) and input output source voltage (VCCO), along with a convenient banking system that simplifies board design. Virtex-II Pro inputs and outputs are powered from VCCO. Differential amplifier inputs, such as GTL and SSTL, are powered from VREF. Fundamentals Modern bus applications, pioneered by the largest and most influential components in the digital electronics industry, are commonly introduced with a new I/O standard tailored specifically to the needs of that application. The bus I/O standards provide specifications to other vendors who create products designed to interface with these applications. Each standard often has its own specifications for current, voltage, I/O buffering, and termination techniques. The ability to provide the flexibility and time-to-market advantages of programmable logic is increasingly dependent on the capability of the programmable logic device to support an ever increasing variety of I/O standards. SelectI/O resources feature highly configurable input and output buffers that provide support for a wide variety of I/O standards. An input buffer can be configured as either a simple buffer or as a differential amplifier input. An output buffer can be configured as either a Push-Pull output or as an Open Drain output. Table 2-38 illustrates all of the supported single-ended I/O standards in Virtex-II Pro devices. Each buffer type can support a variety of current and voltage requirements. Table 2-38: I/O Standard 304 Supported Single-Ended I/O Standards Input Reference Input Source Output Source Board Termination Voltage (VTT) Voltage (VREF) Voltage (VCCO) Voltage (VCCO) LVTTL N/A 3.3 3.3 N/A LVCMOS15 N/A 1.5 1.5 N/A LVCMOS18 N/A 1.8 1.8 N/A LVCMOS25 N/A 2.5 2.5 N/A LVCMOS33 N/A 3.3 3.3 N/A PCI33_3 N/A 3.3 3.3 N/A PCI66_3 N/A 3.3 3.3 N/A PCIX N/A 3.3 3.3 N/A GTL 0.80 N/A N/A 1.2 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-38: I/O Standard Supported Single-Ended I/O Standards (Continued) Input Reference Input Source Output Source Board Termination Voltage (VTT) Voltage (VREF) Voltage (VCCO) Voltage (VCCO) GTL+ 1.0 N/A N/A 1.5 HSTL_I 0.75 N/A 1.5 0.75 HSTL_II 0.75 N/A 1.5 0.75 HSTL_III 0.9 N/A 1.5 1.5 HSTL_IV 0.9 N/A 1.5 1.5 SSTL3_I 1.5 N/A 3.3 1.5 SSTL3_II 1.5 N/A 3.3 1.5 SSTL2_I 1.25 N/A 2.5 1.25 SSTL2_II 1.25 N/A 2.5 1.25 3.3V I/O Support Due to process geometry, only certain banks support PCI and other 3.3V single-ended I/O standards. Table 4-1, page 448, details the total number of 3.3V I/Os per bank, as well as bank locations. Overview of Supported I/O Standards This section provides a brief overview of I/O standards supported by all Virtex-II Pro devices. While most I/O standards specify a range of allowed voltages, this document records typical voltage values only. Detailed information on each specification can be found on the Electronic Industry Alliance JEDEC website at: http://www.jedec.org LVTTL - Low-Voltage TTL The low-voltage TTL, or LVTTL, standard is a general purpose EIA/JESDSA standard for 3.3V applications that use an LVTTL input buffer and a Push-Pull output buffer. This standard requires a 3.3V input and output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a termination voltage (VTT). LVCMOS33 - 3.3-Volt Low-Voltage CMOS This standard is an extension of the LVCMOS standard (JESD 8.-5). It is used in general purpose 3.3V applications.The standard requires a 3.3V input/output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a termination voltage (VTT). LVCMOS25 - 2.5-Volt Low-Voltage CMOS This standard is an extension of the LVCMOS standard (JESD 8.-5). It is used in general purpose 2.5 volts or lower applications. This standard requires a 2.5V input /output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a board termination voltage (VTT). LVCMOS18 - 1.8-Volt Low-Voltage CMOS This standard is an extension of the LVCMOS standard. It is used in general purpose 1.8V applications. The use of a reference voltage (VREF) or board termination voltage (VTT) is not required. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 305 R Chapter 2: Design Considerations LVCMOS15 - 1.5-Volt Low-Voltage CMOS This standard is an extension of the LVCMOS standard. It is used in general purpose 1.5V applications. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. PCI - Peripheral Component Interface The PCI standard specifies support for 33 MHz, 66 MHz and 133 MHz PCI bus applications. It uses a LVTTL input buffer and a Push-Pull output buffer. This standard does not require the use of a reference voltage (VREF) or a board termination voltage (VTT), however, it does require 3.3V input output source voltage (VCCO). GTL -Gunning Transceiver Logic Terminated The GTL standard is a high-speed bus standard (JESD8.3) invented by Xerox. Xilinx has implemented the terminated variation for this standard. This standard requires a differential amplifier input buffer and a open Drain output buffer. GTL+ - Gunning Transceiver Logic Plus The Gunning Transceiver Logic Plus, or GTL+ standard is a high-speed bus standard (JESD8.3) first used by the Pentium Pro Processor. HSTL - High-speed Transceiver Logic The high-speed Transceiver Logic, or HSTL standard is a general purpose high-speed, 1.5V bus standard sponsored by IBM (EIA/JESD8-6). This standard has four variations or classes. Virtex-II Pro SelectI/O supports all four Classes. This standard requires a Differential Amplifier input buffer and a Push-pull output buffer. SSTL3 - Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3.3V, or SSTL3 standard is a general purpose 3.3V memory bus standard also sponsored by Hitachi and IBM (JESD8-8). This standard has two classes, I and II. Virtex-II Pro SelectI/O supports both classes for the SSTL3 standard. This standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL2 - Stub Series Terminated Logic for 2.5V The Stub Series Terminated Logic for 2.5V, or SSTL2 standard is a general purpose 2.5V memory bus standard also sponsored by Hitachi and IBM (JESD8-8). This standard has two classes, I and II. Virtex-II Pro SelectI/O supports both classes for the SSTL2 standard. This standard requires a Differential Amplifier input buffer and a Push-Pull output buffer Library Symbols The Xilinx library includes an extensive list of symbols designed to provide support for the variety of SelectI/O features. Most of these symbols represent variations of the five generic SelectI/O symbols. * * * * * IBUF (input buffer) IBUFG (clock input buffer) OBUF (output buffer) OBUFT (3-state output buffer) IOBUF (input/output buffer) IBUF Signals used as inputs to a Virtex-II Pro device must source an input buffer (IBUF) via an external input port. The generic Virtex-II Pro IBUF symbol is shown in Figure 2-76. The 306 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources extension to the base name defines which I/O standard the IBUF uses. The assumed standard is LVTTL when the generic IBUF has no specified extension. IBUF I O x133_01_111699 Figure 2-76: Input Buffer (IBUF) Symbols Table 2-39 details variations of the IBUF symbol for single-ended Virtex-II Pro I/O standards: Table 2-39: Variations of the IBUF Symbol IBUF IBUF_HSTL_III IBUF_LVCMOS15 IBUF_HSTL_IV IBUF_LVCMOS18 IBUF_SSTL2_I IBUF_LVCMOS25 IBUF_SSTL2_II IBUF_LVCMOS33 IBUF_SSTL3_I IBUF_APG IBUF_SSTL3_II IBUF_GTL IBUF_PCI33_3 IBUF_GTLP IBUF_PCI66_3 IBUF_HSTL_I IBUF_PCIX IBUF_HSTL_II When the IBUF symbol supports an I/O standard that requires a differential amplifier input, the IBUF is automatically configured as a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. The voltage reference signal is "banked" within the Virtex-II Pro device on a half-edge basis, such that for all packages there are eight independent VREF banks internally. For a representation of the Virtex-II Pro I/O banks, see Figure 2-78. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUF placement restrictions require that any differential amplifier input signals within a bank be of the same standard. How to specify a specific location for the IBUF via the LOC property is described below. Table 2-40 summarizes compatibility requirements of Virtex-II Pro input standards. An optional delay element in the input data path is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element is activated by default to ensure a zero hold-time requirement at the device input pin. The IOBDELAY = NONE property overrides this default, thus reducing the input set-up time, but risking a hold-time requirement. When the IBUF does not drive a flip-flop within the IOB, the delay element is deactivated by default to provide a shorter input set-up time. To delay the input signal, activate the delay element with the IOBDELAY = BOTH property. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 307 R Chapter 2: Design Considerations Bank 4 Bank 5 Bank 6 Bank 3 Bank 7 Bank 0 Bank 2 Bank 1 ds031_66_112900 Figure 2-77: Virtex-II Pro I/O Banks: Top View for Flip-Chip Packages (FF & BF) Bank 5 Bank 4 Bank 3 Bank 6 Bank 2 Bank 1 Bank 7 Bank 0 ug002_c2_014_112900 Figure 2-78: Table 2-40: Virtex-II Pro I/O Banks: Top View for Wire-Bond Package (FG) Xilinx Input Standard Compatibility Requirements Rule 1 Standards with the same VCCO, and VREF can be placed within the same bank. Rule 2 Standards that don't require a VREF can be placed within the same bank with the standards that have the same VCCO values Each bank has its own VCCO and VREF voltage. Details on compatible input standards for each VCCO / VREF voltage combination are available in the Virtex-II Pro Data Sheet . OBUF An OBUF must drive outputs through an external output port. Figure 2-79 shows the generic output buffer (OBUF) symbol. OBUF I O x133_04_111699 Figure 2-79: Virtex-II Pro Output Buffer (OBUF) Symbol 308 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources The extension to the base name defines which I/O standard the OBUF uses. With no extension specified for the generic OBUF symbol, the assumed standard is slew rate limited LVCMOS25 with 12mA drive strength. The LVTTL and LVCMOS OBUFs can additionally support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients, when switching non-critical signals. LVTTL and LVCMOS output buffers have selectable drive strengths. The format for these OBUF symbol names is as follows: OBUF_<slew_rate>_<drive_strength> <slew_rate> is either F (fast) or S (slow) and <drive_strength> is specified in milliamperes. For LVTTL, LVCMOS25, and LVCMOS33, the supported drive strengths are 2, 4, 6, 8, 12, 16, and 24. For LVCMOS15, and LVCMOS18, the supported drive strengths are 2, 4, 6, 8, 12, and 16. Table 2-41 details variations of the OBUF symbol. Table 2-41: Variations of the OBUF Symbol OBUF OBUF_LVCMOS18_S_2 OBUF_LVCMOS33_S_4 OBUF_S_2 OBUF_LVCMOS18_S_4 OBUF_LVCMOS33_S_6 OBUF_S_4 OBUF_LVCMOS18_S_6 OBUF_LVCMOS33_S_8 OBUF_S_6 OBUF_LVCMOS18_S_8 OBUF_LVCMOS33_S_12 OBUF_S_8 OBUF_LVCMOS18_S_12 OBUF_LVCMOS33_S_16 OBUF_S_12 OBUF_LVCMOS18_S_16 OBUF_LVCMOS33_S_24 OBUF_S_16 OBUF_LVCMOS18_F_2 OBUF_LVCMOS33_F_2 OBUF_S_24 OBUF_LVCMOS18_F_4 OBUF_LVCMOS33_F_4 OBUF_F_2 OBUF_LVCMOS18_F_6 OBUF_LVCMOS33_F_6 OBUF_F_4 OBUF_LVCMOS18_F_8 OBUF_LVCMOS33_F_8 OBUF_F_6 OBUF_LVCMOS18_F_12 OBUF_LVCMOS33_F_12 OBUF_F_8 OBUF_LVCMOS18_F_16 OBUF_LVCMOS33_F_16 OBUF_F_12 OBUF_LVCMOS25 OBUF_LVCMOS33_F_24 OBUF_F_16 OBUF_LVCMOS25_S_2 OBUF_PCI33_3 OBUF_F_24 OBUF_LVCMOS25_S_4 OBUF_PCI66-3 OBUF_LVCMOS15 OBUF_LVCMOS25_S_6 OBUF_PCIX OBUF_LVCMOS15_S_2 OBUF_LVCMOS25_S_8 OBUF_GTL OBUF_LVCMOS15_S_4 OBUF_LVCMOS25_S_12 OBUF_GTLP OBUF_LVCMOS15_S_6 OBUF_LVCMOS25_S_16 OBUF_HSTL_I OBUF_LVCMOS15_S_8 OBUF_LVCMOS25_S_24 OBUF_HSTL_II OBUF_LVCMOS15_S_12 OBUF_LVCMOS25_F_2 OBUF_HSTL_III OBUF_LVCMOS15_S_16 OBUF_LVCMOS25_F_4 OBUF_HSTL_IV OBUF_LVCMOS15_F_2 OBUF_LVCMOS25_F_6 OBUF_SSTL3_I OBUF_LVCMOS15_F_4 OBUF_LVCMOS25_F_8 OBUF_SSTL3_II OBUF_LVCMOS15_F_6 OBUF_LVCMOS25_F_12 OBUF_SSTL2_I OBUF_LVCMOS15_F_8 OBUF_LVCMOS25_F_16 OBUF_SSTL2_II UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 309 R Chapter 2: Design Considerations Table 2-41: Variations of the OBUF Symbol (Continued) OBUF_LVCMOS15_F_12 OBUF_LVCMOS25_F_24 OBUF_LVCMOS15_F_16 OBUF_LVCMOS33 OBUF_LVCMOS18 OBUF_LVCMOS33_S_2 OBUF placement restrictions require that within a given VCCO bank each OBUF share the same output source drive voltage. Input buffers with the same VCCO and output buffers that do not require VCCO can be placed within any VCCO bank. Table 2-42 summarizes Virtex-II Pro output compatibility requirements. The LOC property can specify a location for the OBUF. Table 2-42: Output Standards Compatibility Requirements Rule 1 Only outputs with standards which share compatible VCCO can be used within the same bank. Rule 2 There are no placement restrictions for outputs with standards that do not require a VCCO Each bank has its own VCCO voltage. Details on compatible output standards for each VCCO voltage combination are available in the Virtex-II Pro Data Sheet . OBUFT The generic 3-state output buffer OBUFT, shown in Figure 2-80, typically implements 3-state outputs or bidirectional I/O. T OBUFT O I x133_05_111699 Figure 2-80: 3-State Output Buffer Symbol (OBUFT) The extension to the base name defines which I/O standard OBUFT uses. With no extension specified for the generic OBUFT symbol, the assumed standard is slew rate limited LVCMOS with 12mA drive strength. The LVTTL and LVCMOS OBUFTs additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients, when switching non-critical signals. LVTTL and LVCMOS 3-state buffers have selectable drive strengths. The format for these OBUFT symbol names is as follows: OBUFT_<slew_rate>_<drive_strength> <slew_rate> is either F(fast) or S(slow) and <drive_strength> is specified in milliamperes. For LVTTL, LVCMOS25, and LVCMOS33, the supported drive strengths are 2, 4, 6, 8, 12, 16, and 24. For LVCMOS15 and LVCMOS18, the supported drive strengths are 2, 4, 6, 8, 12, and 16. Table 2-43 details variations of the OBUFT symbol. Table 2-43: 310 Variations of the OBUFT Symbol OBUFT OBUFT_LVCMOS18_S_2 OBUFT_LVCMOS33_S_4 OBUFT_S_2 OBUFT_LVCMOS18_S_4 OBUFT_LVCMOS33_S_6 OBUFT_S_4 OBUFT_LVCMOS18_S_6 OBUFT_LVCMOS33_S_8 OBUFT_S_6 OBUFT_LVCMOS18_S_8 OBUFT_LVCMOS33_S_12 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-43: Variations of the OBUFT Symbol (Continued) OBUFT_S_8 OBUFT_LVCMOS18_S_12 OBUFT_LVCMOS33_S_16 OBUFT_S_12 OBUFT_LVCMOS18_S_16 OBUFT_LVCMOS33_S_24 OBUFT_S_16 OBUFT_LVCMOS18_F_2 OBUFT_LVCMOS33_F_2 OBUFT_S_24 OBUFT_LVCMOS18_F_4 OBUFT_LVCMOS33_F_4 OBUFT_F_2 OBUFT_LVCMOS18_F_6 OBUFT_LVCMOS33_F_6 OBUFT_F_4 OBUFT_LVCMOS18_F_8 OBUFT_LVCMOS33_F_8 OBUFT_F_6 OBUFT_LVCMOS18F_12 OBUFT_LVCMOS33_F_12 OBUFT_F_8 OBUFT_LVCMOS18_F_16 OBUFT_LVCMOS33_F_16 OBUFT_F_12 OBUFT_LVCMOS25 OBUFT_LVCMOS33_F_24 OBUFT_F_16 OBUFT_LVCMOS25_S_2 OBUFT_PCI33_3 OBUFT_F_24 OBUFT_LVCMOS25_S_4 OBUFT_PCI66-3 OBUFT_LVCMOS15 OBUFT_LVCMOS25_S_6 OBUFT_PCIX OBUFT_LVCMOS15_S_2 OBUFT_LVCMOS25_S_8 OBUFT_GTL OBUFT_LVCMOS15_S_4 OBUFT_LVCMOS25_S_12 OBUFT_GTLP OBUFT_LVCMOS15_S_6 OBUFT_LVCMOS25_S_16 OBUFT_HSTL_I OBUFT_LVCMOS15_S_8 OBUFT_LVCMOS25_S_24 OBUFT_HSTL_II OBUFT_LVCMOS15_S_12 OBUFT_LVCMOS25_F_2 OBUFT_HSTL_III OBUFT_LVCMOS15_S_16 OBUFT_LVCMOS25_F_4 OBUFT_HSTL_IV OBUFT_LVCMOS15_F_2 OBUFT_LVCMOS25_F_6 OBUFT_SSTL3_I OBUFT_LVCMOS15_F_4 OBUFT_LVCMOS25_F_8 OBUFT_SSTL3_II OBUFT_LVCMOS15_F_6 OBUFT_LVCMOS25_F_12 OBUFT_SSTL2_I OBUFT_LVCMOS15_F_8 OBUFT_LVCMOS25_F_16 OBUFT_SSTL2_II OBUFT_LVCMOS15_F_12 OBUFT_LVCMOS25_F_24 OBUFT_LVCMOS15_F_16 OBUFT_LVCMOS33 OBUFT_LVCMOS18 OBUFT_LVCMOS33_S_2 OBUFT placement restrictions require that within a given VCCO bank each OBUFT share the same output source drive voltage. Input buffers with the same VCCO and output buffers that do not require VCCO can be placed within any VCCO bank. The LOC property can specify a location for the OBUFT. 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the OBUFT (PULLUP, PULLDOWN, or KEEPER). The weak "keeper" circuit requires the input buffer within the IOB to sample the I/O signal. Thus, OBUFTs programmed for an I/O standard that requires a VREF have automatic placement of a VREF in the bank with an OBUFT configured with a weak "keeper" typically implement a bidirectional I/O. In this case, the IBUF (and the corresponding VREF) are placed explicitly. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 311 R Chapter 2: Design Considerations IOBUF Use the IOBUF symbol for bidirectional signals that require both an input buffer and a 3-state output buffer with an active High 3-state pin. Figure 2-81 shows the generic input/output IOBUF buffer. T IOBUF I IO O x133_06_111699 Figure 2-81: Input/Output Buffer Symbol (IOBUF) The extension to the base name defines which I/O standard the IOBUF uses. With no extension specified for the generic IOBUF symbol, the assumed standard is LVTTL input buffer and slew rate limited LVCMOS with 12mA drive strength for the output buffer. The LVTTL and LVCMOS IOBUFs can additionally support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients, when switching non-critical signals. LVTTL and LVCMOS output buffers have selectable drive strengths. The format for these OBUF symbol names is as follows: OBUF_<slew_rate>_<drive_strength> <slew_rate> is either F (fast) or S (slow) and <drive_strength> is specified in milliamperes. For LVTTL, LVCMOS25 and LVCMOS33, the supported drive strengths are 2, 4, 6, 8, 12, 16, and 24. For LVCMOS15, and LVCMOS18, the supported drive strengths are 2, 4, 6, 8, 12, and 16. Table 2-44 details variations of the IOBUF symbol. Table 2-44: 312 Variations of the IOBUF Symbol IOBUF IOBUF_LVCMOS18_S_2 IOBUF_LVCMOS33_S_4 IOBUF_S_2 IOBUF_LVCMOS18_S_4 IOBUF_LVCMOS33_S_6 IOBUF_S_4 IOBUF_LVCMOS18_S_6 IOBUF_LVCMOS33_S_8 IOBUF_S_6 IOBUF_LVCMOS18_S_8 IOBUF_LVCMOS33_S_12 IOBUF_S_8 IOBUF_LVCMOS18_S_12 IOBUF_LVCMOS33_S_16 IOBUF_S_12 IOBUF_LVCMOS18_S_16 IOBUF_LVCMOS33_S_24 IOBUF_S_16 IOBUF_LVCMOS18_F_2 IOBUF_LVCMOS33_F_2 IOBUF_S_24 IOBUF_LVCMOS18_F_4 IOBUF_LVCMOS33_F_4 IOBUF_F_2 IOBUF_LVCMOS18_F_6 IOBUF_LVCMOS33_F_6 IOBUF_F_4 IOBUF_LVCMOS18_F_8 IOBUF_LVCMOS33_F_8 IOBUF_F_6 IOBUF_LVCMOS18F_12 IOBUF_LVCMOS33_F_12 IOBUF_F_8 IOBUF_LVCMOS18_F_16 IOBUF_LVCMOS33_F_16 IOBUF_F_12 IOBUF_LVCMOS25 IOBUF_LVCMOS33_F_24 IOBUF_F_16 IOBUF_LVCMOS25_S_2 IOBUF_PCI33_3 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-44: Variations of the IOBUF Symbol (Continued) IOBUF_F_24 IOBUF_LVCMOS25_S_4 IOBUF_PCI66-3 IOBUF_LVCMOS15 IOBUF_LVCMOS25_S_6 IOBUF_PCIX IOBUF_LVCMOS15_S_2 IOBUF_LVCMOS25_S_8 IOBUF_GTL IOBUF_LVCMOS15_S_4 IOBUF_LVCMOS25_S_12 IOBUF_GTLP IOBUF_LVCMOS15_S_6 IOBUF_LVCMOS25_S_16 IOBUF_HSTL_I IOBUF_LVCMOS15_S_8 IOBUF_LVCMOS25_S_24 IOBUF_HSTL_II IOBUF_LVCMOS15_S_12 IOBUF_LVCMOS25_F_2 IOBUF_HSTL_III IOBUF_LVCMOS15_S_16 IOBUF_LVCMOS25_F_4 IOBUF_HSTL_IV IOBUF_LVCMOS15_F_2 IOBUF_LVCMOS25_F_6 IOBUF_SSTL3_I IOBUF_LVCMOS15_F_4 IOBUF_LVCMOS25_F_8 IOBUF_SSTL3_II IOBUF_LVCMOS15_F_6 IOBUF_LVCMOS25_F_12 IOBUF_SSTL2_I IOBUF_LVCMOS15_F_8 IOBUF_LVCMOS25_F_16 IOBUF_SSTL2_II IOBUF_LVCMOS15_F_12 IOBUF_LVCMOS25_F_24 IOBUF_LVCMOS15_F_16 IOBUF_LVCMOS33 IOBUF_LVCMOS18 IOBUF_LVCMOS33_S_2 When the IOBUF symbol supports an I/O standard that requires a differential amplifier input, IOBUF is automatically configured as a differential amplifier input buffer. Lowvoltage I/O standards with a differential amplifier input require an external reference voltage input VREF. The voltage reference signal is "banked" within the Virtex-II Pro device on a half-edge basis, such that for all packages there are eight independent VREF banks internally. For a representation of the Virtex-II Pro I/O banks, see Figure 2-78. Within each bank approximately one of every twelve I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IOBUF placement restrictions require any differential amplifier input signals within a bank be of the same standard. Additional restrictions on Virtex-II Pro SelectI/O IOBUF placement require that within a given VCCO bank each IOBUF share the same output source drive voltage. Input buffers with the same VCCO and output buffers that do not require VCCO can be placed within any VCCO bank. The LOC property can specify a location for the OBUF. An optional delay element is associated with the input path in each IOBUF. When the IOBUF drives an input flip-flop within the IOB, the delay element is activated by default to ensure the zero hold-time requirement. Override this default with the IOBDELAY = NONE property. In the case when the IOBUF does not drive an input flip-flop within the IOB, the delay element is deactivated by default to provide higher performance. To delay the input signal, deactivate the delay element with the IOBDELAY = BOTH property. 3-state output buffers and bidirectional buffers can have a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the IOBUF (PULLUP, PULLDOWN, or KEEPER). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 313 R Chapter 2: Design Considerations SelectI/O Properties Access to some SelectI/O features (for example, location constraints, input delay, output drive strength, and slew rate) is available through properties associated with these features. Input Delay Properties An optional delay element is associated with the input path in each IBUF. When the IBUF drives an input flip-flop within the IOB, the delay element activates by default to ensure the zero hold-time requirement. Override this default with the IOBDELAY = NONE property. In the case when the IBUF does not drive an input flip-flop within the IOB, the delay element is deactivated by default to provide higher performance. To delay the input signal, activate the delay element with the IOBDELAY = BOTH property. IOB Flip-Flop/Latch Properties The Virtex-II Pro Series I/O block (IOB) includes two optional registers on the input path, two optional registers on the output path, and two optional registers on the 3-state control pin. The design implementation software automatically takes advantage of these registers when the following option for the MAP program is specified. Map -pr b <filename> Alternatively, the IOB = TRUE property can be placed on a register to force the mapper to place the register in an IOB. The two registers for each path makes designing double-data-rate (DDR) logic much simpler. Each pair of the registers has separate clock inputs, which can be driven by either the positive edge or the negative edge of the clock. Users can use both edges of the clocks to clock data in and out from the IOB. For details on DDR, see Double-Data-Rate (DDR) I/O, page 348. Location Constraints Specify the location of each SelectI/O symbol with the location constraint LOC attached to the SelectI/O symbol. The external port identifier indicates the value of the location constrain. The format of the port identifier depends on the package chosen for the specified design. The LOC properties use the following form: * * LOC=A42; LOC=P37; Output Slew Rate Property As mentioned above, a variety of symbol names provide the option of choosing the desired slew rate for the output buffers. In the case of the LVTTL or LVCMOS output buffers (OBUF, OBUFT, and IOBUF), slew rate control can be alternatively programmed with the SLEW = property. By the default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. The SLEW = property has one of the two following values: * * SLEW = SLOW SLEW = FAST Output Drive Strength Property The desired output drive strength can be additionally specified by choosing the appropriate library symbol. The Xilinx library also provides an alternative method for specifying this feature. For the LVTTL, and LVCMOS output buffers (OBUF, OBUFT, and 314 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources IOBUF), the desired drive strength can be specified with the DRIVE = property. This property could have one of the following values: * * * * * * * DRIVE = 2 DRIVE = 4 DRIVE = 6 DRIVE = 8 DRIVE = 12 DRIVE = 16 DRIVE = 24 Design Considerations Reference Voltage (VREF) Pins Low-voltage I/O standards with a differential amplifier input buffer require an input reference voltage (VREF). Provide the VREF as an external signal to the device. The voltage reference signal is "banked" within the Virtex-II Pro device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 2-78 for a representation of the Virtex-II Pro I/O banks. Within each bank approximately one of every twelve I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. Within each VREF bank, any input buffers that require a VREF signal must be of the same type. Output buffers that have the same VCCO values as the input buffers can be placed within the same VREF bank. Output Drive Source Voltage (VCCO) Pins Many of the low-voltage I/O standards supported by SelectI/O devices require a different output drive source voltage (VCCO). As a result each device can often have to support multiple output drive source voltages. Output buffers within a given VCCO bank must share the same output drive source voltage. Input buffers for LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33, PCI33_3, PCI66_3, PCIX use the VCCO voltage for input VCCO voltage. Transmission Line Effects The delay of an electrical signal along a wire is dominated by the rise and fall times when the signal travels a short distance. Transmission line delays vary with inductance and capacitance. But a well-designed board can experience delays of approximately 180ps per inch. Transmission line effects, or reflections, typically start at 1.5" for fast (1.5ns) rise and fall times. Poor (or non-existent) termination or changes in the transmission line impedance cause these reflections and can cause additional delay in longer traces. As a system speeds continue to increase, the effect of I/O delays can become a limiting factor and therefore transmission line termination becomes increasingly more important. Termination Techniques A variety of termination techniques reduce the impact of transmission line effects. The following are output termination techniques: * * * * None Series Parallel (Shunt) Series and Parallel (Series-Shunt) UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 315 R Chapter 2: Design Considerations The following are input termination techniques: * * None Parallel (Shunt) These termination techniques can be applied in any combination. A generic example of each combination of termination methods appears in Figure 2-82. Double Parallel Terminated Unterminated VTT VTT Z=50 Z=50 VREF Unterminated Output Driving a Parallel Terminated Input Series Terminated Output Driving a Parallel Terminated Input VTT VTT Z=50 Z=50 VREF VREF Series-Parallel Terminated Output Driving a Parallel Terminated Input VTT Series Terminated Output VTT Z=50 Z=50 VREF VREF x133_07_111699 Figure 2-82: Overview of Standard Input and Output Termination Methods Simultaneous Switching Guidelines Ground bounce can occur with high-speed digital ICS when multiple outputs change states simultaneously, causing undesired transient behavior on an output or in the internal logic. This problem is also referred to as the Simultaneous Switching Output (SSO) problem. Ground bounce is primarily due to current changes in the combined inductance of ground pins, bond wires, and group metallization. The IC internal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects stable low outputs and all inputs because they interpret the incoming signal by comparing it to the internal ground. If the ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input can be interpreted as a short pulse with a polarity opposite to the ground bounce. Table 2-45 provides the guidelines for the maximum number of simultaneously switching outputs allowed per output power/ground pair to avoid the effects of ground bounce. (See Note 1 at the end of the table for qualifications.) Refer to Table 2-46 for the number of effective output power/ground pairs for each Virtex-II Pro device and package combination. Table 2-45: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair Standard 316 Package: FG, FF, BF LVTTL2_slow 68 LVTTL4_slow 41 LVTTL6_slow 29 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-45: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued) Standard Package: FG, FF, BF LVTTL8_slow 22 LVTTL12_slow 15 LVTTL16_slow 11 LVTTL24_slow 7 LVTTL2_fast 40 LVTTL4_fast 24 LVTTL6_fast 17 LVTTL8_fast 13 LVTTL12_fast 10 LVTTL16_fast 8 LVTTL24_fast 5 LVDCI_15 50 impedance 10 LVDCI_DV2_15 25 impedance 5 LVCMOS15_2_slow 51 LVCMOS15_4_slow 31 LVCMOS15_6_slow 22 LVCMOS15_8_slow 17 LVCMOS15_12_slow 11 LVCMOS15_16_slow 8 LVCMOS15_2_fast 30 LVCMOS15_4_fast 18 LVCMOS15_6_fast 13 LVCMOS15_8_fast 10 LVCMOS15_12_fast 8 LVCMOS15_16_fast 6 LVDCI_18 50 impedance 11 LVDCI_DV2_18 25 impedance 5 LVCMOS18_2_slow 58 LVCMOS18_4_slow 35 LVCMOS18_6_slow 25 LVCMOS18_8_slow 19 LVCMOS18_12_slow 13 LVCMOS18_16_slow 10 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 317 R Chapter 2: Design Considerations Table 2-45: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued) Standard 318 Package: FG, FF, BF LVCMOS18_2_fast 34 LVCMOS18_4_fast 20 LVCMOS18_6_fast 15 LVCMOS18_8_fast 11 LVCMOS18_12_fast 9 LVCMOS18_16_fast 7 LVDCI_25 50 impedance 13 LVDCI_DV2_25 25 impedance 6 LVCMOS25_2_slow 68 LVCMOS25_4_slow 41 LVCMOS25_6_slow 29 LVCMOS25_8_slow 22 LVCMOS25_12_slow 15 LVCMOS25_16_slow 11 LVCMOS25_24_slow 7 LVCMOS25_2_fast 40 LVCMOS25_4_fast 24 LVCMOS25_6_fast 17 LVCMOS25_8_fast 13 LVCMOS25_12_fast 10 LVCMOS25_16_fast 8 LVCMOS25_24_fast 5 LVDCI_33 50 impedance 13 LVDCI_DV2_33 25 impedance 6 LVCMOS33_2_slow 68 LVCMOS33_4_slow 41 LVCMOS33_6_slow 29 LVCMOS33_8_slow 22 LVCMOS33_12_slow 15 LVCMOS33_16_slow 11 LVCMOS33_24_slow 7 LVCMOS33_2_fast 40 LVCMOS33_4_fast 24 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-45: Guidelines for Maximum Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued) Standard Package: FG, FF, BF LVCMOS33_6_fast 17 LVCMOS33_8_fast 13 LVCMOS33_12_fast 10 LVCMOS33_16_fast 8 LVCMOS33_24_fast 5 PCI33/66/X 8 GTL 4 GTL_DCI 3 GTL+ 4 GTL+_DCI 3 HSTLI 20 HSTLI_DCI 15 HSTLII 10 HSTLII_DCI 7 HSTLIII 8 HSTLIII_DCI 8 HSTLIV 4 HSTLIV_DCI 4 SSTL2I 15 SSTL2I_DCI 7 SSTL2II 10 SSTL2II_DCI 5 SSTL3I 12 SSTL3I_DCI 6 SSTL3II 8 SSTL3II_DCI 4 Notes: 1. The maximum number of simultaneously switching outputs per power/ground pair may be less than the number given in this table if the external bypass capacitor solution has a high series inductance. This table presumes the use of ultra-low inductance bypass capacitors. Refer to VCC Decoupling, page 500. Since some of the ground pins are shared inside the package, the effective power/ground pairs per bank may be fewer than the physical power/ground pair pins. The following tables show the number of equivalent power/ground pairs. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 319 R Chapter 2: Design Considerations Table 2-46 shows the number of pairs in banks 0, 1, 4, and 5 (top and bottom edges of the die), while Table 2-47 shows the numbers in banks 2, 3, 6, and 7. This is because MGTs reside on the top and bottom edge only. Table 2-46: Virtex-II Pro Equivalent Power/Ground Pairs per Bank, Top/Bottom For Banks 0, 1, 4, and 5 (Top/Bottom Sides): Package 2VP2 2VP4 2VP7 FG256 3 3 FG456 3 3 4 FG672 3 3 5 5 FF896 FF1152 2VP20 2VP50 7 7 12 12 FF1517 BF957 7 Table 2-47: 12 Virtex-II Pro Equivalent Power/Ground Pairs per Bank, Left/Right For Banks 2, 3, 6, and 7 (Left/Right Sides): Package 2VP2 2VP4 2VP7 FG256 2 5 FG456 2 5 5 FG672 2 7 7 7 FF896 FF1152 2VP20 2VP50 9 9 FF1517 16 16 9 BF957 16 Application Example Creating a design with the SelectI/O feature requires either assignment of the IOSTANDARD attribute in the constraint file or instantiation of the desired library symbol within the design code. To enter the IOSTANDARD attribute in the constraint file (UCF file), the following syntax can be used: NET <pad net name> IOSTANDARD=<the name of the standard> For example, to enter PCIX standard, use NET <pad net name> IOSTANDARD=PCIX; To instantiate a library symbol in the HDL code, use the proper input or output buffer name, and follow the standard syntax of instantiation. For example, to instantiate a GTL input buffer in VHDL, the following syntax can be used: GTL_buffer : IBUF_GTL port map (I=>data_in, O=>data_gtl_in); At the board level, designers need to know the termination techniques required for each I/O standard. 320 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources This section describes some common application examples illustrating the termination techniques recommended by each of the single-ended standard supported by the SelectI/O features. Termination Example Circuit examples involving typical termination techniques for each of the SelectI/O standards follow. For a full range of accepted values for the DC voltage specifications for each standard, refer to the table associated with each figure. The resistors used in each termination technique example and the transmission lines depicted represent board level components and are not meant to represent components on the device. GTL A sample circuit illustrating a valid termination technique for GTL is shown in Figure 2-83. VCCO = N/A VTT = 1.2V VTT = 1.2V 50 50 Z = 50 VREF = 0.8V UG012_C2_008_121101 Figure 2-83: GTL Terminated Table 2-48 lists DC voltage specifications. Table 2-48: GTL Voltage Specifications Parameter Min Typ Max - N/A - VREF = N x VTT1 0.74 0.8 0.86 VTT 1.14 1.2 1.26 VIH VREF + 0.05 0.79 0.85 - VIL VREF - 0.05 - 0.75 0.81 VOH - - - VOL - 0.2 0.4 IOH at VOH (mA) - - - IOLat VOL (mA) at 0.4V 32 - - IOLat VOL (mA) at 0.2V - - 40 VCCO Notes: 1. N must be greater than or equal to 0.653 and less than or equal to 0.68. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 321 R Chapter 2: Design Considerations GTL + Figure 2-84 shows a sample circuit illustrating a valid termination technique for GTL+. VTT = 1.5V VTT = 1.5V 50 50 VCCO = N/A Z = 50 VREF = 1.0V UG012_C2_009_121101 Figure 2-84: GTL+ Terminated Table 2-49 lists DC voltage specifications. Table 2-49: GTL+ Voltage Specifications Parameter Min Typ Max - - - VREF = N x VTT1 0.88 1.0 1.12 VTT 1.35 1.5 1.65 VIH VREF + 0.1 0.98 1.1 - VIL VREF - 0.1 - 0.9 1.02 VOH - - - VOL 0.3 0.45 0.6 - - - IOLat VOL (mA) at 0.6V 36 - - IOLat VOL (mA) at 0.3V - - 48 VCCO IOH at VOH (mA) Notes: 1. N must be greater than or equal to 0.653 and less than or equal to 0.68. HSTL Class I Figure 2-89 shows a sample circuit illustrating a valid termination technique for HSTL_I. VTT = 0.75V VCCO = 1.5V 50 Z = 50 VREF = 0.75V UG012_C2_010_121101 Figure 2-85: 322 Terminated HSTL Class I www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-54 lists DC voltage specifications. Table 2-50: HSTL Class I Voltage Specification Parameter MIN TYP MAX VCCO 1.40 1.50 1.60 VREF 0.68 0.75 0.90 VTT - VCCO x 0.5 - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - HSTL Class II Figure 2-90 shows a sample circuit illustrating a valid termination technique for HSTL_II. VCCO = 1.5V VTT = 0.75V 50 VTT = 0.75V 50 Z = 50 VREF = 0.75V UG012_C2_013a_121101 Figure 2-86: Terminated HSTL Class II Table 2-55 lists DC voltage specifications. Table 2-51: HSTL Class II Voltage Specification Parameter MIN TYP MAX 1.40 1.50 1.60 VREF (1) - 0.75 - VTT - VCCO x 0.5 - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - VCCO Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user." UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 323 R Chapter 2: Design Considerations HSTL Class III Figure 2-91 shows a sample circuit illustrating a valid termination technique for HSTL_III. VTT = 1.5V VCCO = 1.5V 50 Z = 50 VREF = 0.9V UG012_C2_011_121101 Figure 2-87: Terminated HSTL Class III Table 2-56 lists DC voltage specifications. Table 2-52: HSTL Class III Voltage Specification Parameter MIN TYP MAX 1.40 1.50 1.60 VREF (1) - 0.90 - VTT - VCCO - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 24 - - VCCO Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user." HSTL Class IV Figure 2-92 shows a sample circuit illustrating a valid termination technique for HSTL_IV. VTT = 1.5V VCCO = 1.5V 50 VTT = 1.5V 50 Z = 50 VREF = 0.9V UG012_C2_012_121101 Figure 2-88: Terminated HSTL Class IV Table 2-57 lists DC voltage specifications. Table 2-53: HSTL Class IV Voltage Specification Parameter 324 MIN TYP MAX VCCO 1.40 1.50 1.60 VREF - 0.90 - VTT - VCCO - www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-53: HSTL Class IV Voltage Specification Parameter MIN TYP MAX VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 48 - - Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user. HSTL Class I (1.8V) Figure 2-89 shows a sample circuit illustrating a valid termination technique for HSTL_I. VTT = 0.9V VCCO = 1.8V 50 Z = 50 VREF = 0.9V UG012_C2_010a_121101 Figure 2-89: Terminated HSTL Class I (1.8V) Table 2-54 lists DC voltage specifications. Table 2-54: HSTL Class I (1.8V) Voltage Specification Parameter MIN TYP MAX VCCO 1.7 1.8 1.9 VREF 0.8 0.9 1.1 VTT - VCCO x 0.5 - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 325 R Chapter 2: Design Considerations HSTL Class II (1.8V) Figure 2-90 shows a sample circuit illustrating a valid termination technique for HSTL_II. VCCO = 1.5V VTT = 0.75V 50 VTT = 0.75V 50 Z = 50 VREF = 0.75V UG012_C2_013a_121101 Figure 2-90: Terminated HSTL Class II (1.8V) Table 2-55 lists DC voltage specifications. Table 2-55: HSTL Class II (1.8V) Voltage Specification Parameter MIN TYP MAX 1.7 1.8 1.9 VREF (1) - 0.9 - VTT - VCCO x 0.5 - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - VCCO Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user." HSTL Class III (1.8V) Figure 2-91 shows a sample circuit illustrating a valid termination technique for HSTL_III. VTT = 1.8V VCCO = 1.8V 50 Z = 50 VREF = 1.1V UG012_C2_011a_121101 Figure 2-91: Terminated HSTL Class III (1.8V) Table 2-56 lists DC voltage specifications. Table 2-56: HSTL Class III (1.8V) Voltage Specification Parameter MIN TYP MAX 1.7 1.8 1.9 VREF (1) - 1.1 - VTT - VCCO - VCCO 326 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-56: HSTL Class III (1.8V) Voltage Specification Parameter MIN TYP MAX VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 24 - - Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user." HSTL Class IV (1.8V) Figure 2-92 shows a sample circuit illustrating a valid termination technique for HSTL_IV. VTT = 1.8V VTT = 1.8V 50 50 VCCO = 1.8V Z = 50 VREF = 1.1V UG012_C2_012a_121101 Figure 2-92: Terminated HSTL Class IV (1.8V) Table 2-57 lists DC voltage specifications. Table 2-57: HSTL Class IV (1.8V) Voltage Specification Parameter MIN TYP MAX VCCO 1.7 1.8 1.9 VREF - 1.1 - VTT - VCCO - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 48 - - Notes: 1. Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 327 R Chapter 2: Design Considerations SSTL3_I Figure 2-93 shows a sample circuit illustrating a valid termination technique for SSTL3_I. VTT = 1.5V VCCO = 3.3V 50 25 Z = 50 VREF = 1.5V UG012_C2_013_121101 Figure 2-93: Terminated SSTL3_I Table 2-58 lists DC voltage specifications. Table 2-58: SSTL3_I Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF = 0.45 x VCCO 1.3 1.5 1.7 VTT = VREF 1.3 1.5 1.7 VIH VREF + 0.2 1.5 1.7 3.9(1) VIL VREF - 0.2 -0.3(2) 1.3 1.5 VOH VREF + 0.6 1.9 2.1 - VOL VREF - 0.6 - 0.9 1.1 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula SSTL3_II Figure 2-94 shows a sample circuit illustrating a valid termination technique for SSTL3_II. VCCO = 3.3V 25 VTT = 1.5V VTT = 1.5V 50 50 Z = 50 VREF = 1.5V UG012_C2_014_121101 Figure 2-94: 328 www.xilinx.com 1-800-255-7778 Terminated SSTL3_II UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources Table 2-59 lists DC voltage specifications. Table 2-59: SSTL3_II Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF = 0.45 x VCCO 1.3 1.5 1.7 VTT = VREF 1.3 1.5 1.7 VIH VREF + 0.2 1.5 1.7 3.9(1) VIL VREF - 0.2 -0.3(2) 1.3 1.5 VOH VREF + 0.8 2.1 2.3 - VOL VREF - 0.8 - 0.7 0.9 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula SSTL2_I Figure 2-95 shows a sample circuit illustrating a valid termination technique for SSTL2_I. VTT = 1.25V VCCO = 2.5V 50 25 Z = 50 VREF = 1.25V UG012_C2_015_121101 Figure 2-95: Terminated SSTL2_I Table 2-60 lists DC voltage specifications. Table 2-60: SSTL2_I Voltage Specifications Parameter Min Typ Max VCCO 2.3 2.5 2.7 VREF = 0.5 x VCCO 1.15 1.25 1.35 VTT = VREF + N(1) 1.11 1.25 1.39 VIH VREF + 0.18 1.33 1.43 3.0(2) VIL VREF - 0.18 -0.3(3) 1.07 1.17 VOH VREF + 0.61 1.76 1.82 1.96 VOL VREF - 0.61 0.54 0.64 0.74 IOH at VOH (mA) -7.6 - - IOLat VOL (mA) 7.6 - - Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 329 R Chapter 2: Design Considerations SSTL2_II Figure 2-96 shows a sample circuit illustrating a valid termination technique for SSTL2_II. VCCO = 2.5V VTT = 1.25V VTT = 1.25V 50 50 25 Z = 50 VREF = 1.25V UG012_C2_016_121101 Figure 2-96: Terminated SSTL2_II Table 2-61 lists DC voltage specifications. Table 2-61: SSTL2_II Voltage Specifications Parameter Min Typ Max VCCO 2.3 2.5 2.7 VREF = 0.5 x VCCO 1.15 1.25 1.35 VTT = VREF + N(1) 1.11 1.25 1.39 VIH VREF + 0.18 1.33 1.43 3.0(2) VIL VREF - 0.18 -0.3(3) 1.07 1.17 VOH VREF + 0.8 1.95 2.05 - VOL VREF - 0.8 - 0.45 0.55 IOH at VOH (mA) -15.2 - - IOLat VOL (mA) 15.2 - - Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula. 330 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Single-Ended SelectI/O Resources PCI33_3, PCI66_3, and PCIX Table 2-62 lists DC voltage specifications. Table 2-62: PCI33_3, PCI66_3, and PCIX Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.5 VREF - - - VTT - - - VIH = 0.5 x VCCO 1.5 1.65 VCCO + 0.5 VIL = 0.3 x VCCO - 0.5 0.99 1.08 VOH = 0.9 x VCCO 2.7 - - VOL= 0.1 x VCCO - - 0.36 IOH at VOH (mA) Note 1 - - IOLat VOL (mA) Note 1 - - Notes: 1. Tested according to the relevant specification. LVTTL Table 2-63 lists DC voltage specifications. Table 2-63: LVTTL Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF - - - VTT - - - VIH 2.0 - 3.6 VIL -0.5 - 0.8 VOH 2.4 - - VOL - - 0.4 IOH at VOH (mA) -24 - - IOLat VOL (mA) 24 - - Notes: 1. VOLand VOH for lower drive currents are sample tested. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 331 R Chapter 2: Design Considerations LVCMOS15 Table 2-64 lists DC voltage specifications. Table 2-64: LVCMOS15 Voltage Specifications Parameter Min Typ Max VCCO - 1.5 - VREF - - - VTT - - - VIH = 0.7 x VCCO 1.05 - 1.65 VIL = 0.2 x VCCO -0.5 - 0.3 VOH = VCCO - 0.45 - 1.05 - VOL - - 0.4 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - Min Typ Max VCCO 1.7 1.8 1.9 VREF - - - VTT - - - VIH = 0.7 x VCCO 1.19 - 1.95 VIL = 0.2 x VCCO -0.5 - 0.4 VOH = VCCO - 0.4 1.3 - - - - 0.4 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - LVCMOS18 Table 2-65 lists DC voltage specifications. Table 2-65: LVCMOS18 Voltage Specifications Parameter VOL 332 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) LVCMOS25 Table 2-66 lists DC voltage specifications. Table 2-66: LVCMOS25 Voltage Specifications Parameter Min Typ Max VCCO 2.3 2.5 2.7 VREF - - - VTT - - - VIH 1.7 - 2.7 VIL -0.5 - 0.7 VOH 1.9 - - VOL - - 0.4 IOH at VOH (mA) -24 - - IOLat VOL (mA) 24 - - LVCMOS33 Table 2-67 lists DC voltage specifications. Table 2-67: LVCMOS33 Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF - - - VTT - - - VIH 2.0 - 3.6 VIL -0.5 - 0.8 VOH 2.6 - - VOL - - 0.4 IOH at VOH (mA) -24 - - IOLat VOL (mA) 24 - - Digitally Controlled Impedance (DCI) Introduction As FPGAs get bigger and system clock speeds get faster, PC board design and manufacturing becomes more difficult. With ever faster edge rates, maintaining signal integrity becomes a critical issue. Designers must make sure that most PC board traces are terminated properly to avoid reflections or ringing. To terminate a trace, resistors are traditionally added to make the output and/or input match the impedance of the receiver or driver to the impedance of the trace. However, due to the increase in device I/O counts, adding resistors close to the device pins increases the board area and component count, and in some cases might even be physically impossible. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 333 R Chapter 2: Design Considerations To address these issues and to achieve better signal integrity, Xilinx developed a new I/O technology for the Virtex-II and Virtex-II Pro device families, Digitally Controlled Impedance (DCI). DCI adjusts the output impedance or input termination to accurately match the characteristic impedance of the transmission line. DCI actively adjusts the impedance of the I/O to equal an external reference resistance. This compensates for changes in I/O impedance due to process variation. It also continuously adjusts the impedance of the I/O to compensate for variations of temperature and supply voltage fluctuations. In the case of controlled impedance drivers, DCI controls the driver impedance to match two reference resistors, or optionally, to match half the value of these reference resistors. DCI eliminates the need for external termination resistors. DCI provides the termination for transmitters or receivers. This eliminates the need for termination resistors on the board, reduces board routing difficulties and component count, and improves signal integrity by eliminating stub reflection. Stub reflection occurs when termination resistors are located too far from the end of the transmission line. With DCI, the termination resistors are as close as possible to the output driver or the input buffer, thus, eliminating stub reflections. Xilinx DCI DCI uses two multi-purpose reference pins in each bank to control the impedance of the driver or the parallel termination value for all of the I/Os of that bank. The N reference pin (VRN) must be pulled up to VCCO by a reference resistor, and the P reference pin (VRP) must be pulled down to ground by another reference resistor. The value of each reference resistor should be equal to the characteristic impedance of the PC board traces, or should be twice that value (configuration option). When a DCI I/O standard is used on a particular bank, the two multi-purpose reference pins cannot be used as regular I/Os. However, if DCI I/O standards are not used in the bank, these pins are available as regular I/O pins. Check the Virtex-II Pro pinout for detailed pin descriptions. DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or off. The impedance is adjusted to match the external reference resistors. The impedance adjustment process has two phases. The first phase, which compensates for process variations, is done during the device startup sequence. The second phase, which maintains the impedance in response to temperature and supply voltage changes, begins immediately after the first phase and continues indefinitely, even while the part is operating. By default, the DONE pin does not go High until the first phase of the impedance adjustment process has completed. For controlled impedance output drivers, the impedance can be adjusted either to match the reference resistors or half the resistance of the reference resistors. For on-chip termination, the termination is always adjusted to match the reference resistors. DCI can configure output drivers to be the following types: 1. Controlled Impedance Driver (Source Termination) 2. Controlled Impedance Driver with Half Impedance (Source Termination) It can also configure inputs to have he following types of on-chip terminations: 1. Input termination to VCCO (Single Termination) 2. Input termination to VCCO/2 (Split Termination, Thevenin equivalent) For bidirectional operation, both ends of the line can be DCI-terminated permanently: 334 1. Driver with termination to VCCO (Single Termination) 2. Driver with termination to VCCO/2 (Split Termination, Thevenin equivalent) www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) Alternatively, bidirectional point-to-point lines can use controlled-impedance drivers (with 3-state buffers) on both ends. Controlled Impedance Driver (Source Termination) Some I/O standards, such as LVTTL, LVCMOS, etc., must have a drive impedance that matches the characteristic impedance of the driven line. DCI can provide a controlled impedance output drivers that eliminate reflections without an external source termination. The impedance is set by the external reference resistors, whose resistance should be equal to the trace impedance. The DCI I/O standards that support Controlled Impedance Driver are: LVDCI_15, LVDCI_18, LVDCI_25, and LVDCI_33. Figure 2-97 illustrates a controlled impedance driver inside Virtex-II Pro device. IOB R Z0 Virtex-II Pro DCI UG012_C2_047_121101 Figure 2-97: Controlled Impedance Driver Controlled Impedance Driver with Half Impedance (Source Termination) DCI can also provide drivers with one half of the impedance of the reference resistors. The DCI I/O standards that support controlled impedance driver with half-impedance are LVDCI_DV2_15, LVDCI_DV2_18, and LVDCI_DV2_25. Figure 2-98 illustrates a controlled driver with half impedance inside a Virtex-II Pro device. IOB R/2 Z0 Virtex-II Pro DCI UG012_C2_052_121101 Figure 2-98: Controlled Impedance Driver with Half Impedance UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 335 R Chapter 2: Design Considerations Input Termination to VCCO (Single Termination) Some I/O standards, such as HSTL Class III, IV, etc., require an input termination to VCCO. See Figure 2-99. VCCO R Z0 VREF UG012_C2_053_121101 Figure 2-99: Input Termination to VCCO without DCI DCI can provide this termination to VCCO using single termination. The termination resistance is set by the reference resistors. For GTL and HSTL standards, they should be controlled by 50-ohm reference resistors. The DCI I/O standards that support single termination are: GTL_DCI, GTLP_DCI, HSTL_III_DCI, HSTL_III_DCI_18, HSTL_IV_DCI., and HSTL_IV_DCI_18. Figure 2-100 illustrates single termination inside a Virtex-II Pro device. VCCO R Z0 VREF Virtex-II Pro UG012_C2_054_121101 Figure 2-100: 336 Input Termination Using DCI Single Termination www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) Input Termination to VCCO /2 (Split Termination) Some I/O standards, such as HSTL Class I, II, SSTL3 Class I, II, etc., require an input termination voltage of VCCO /2. See Figure 2-101. VCCO /2 R Z0 VREF UG012_C2_055_121101 Figure 2-101: Input Termination to VCCO /2 without DCI This is equivalent to having a split termination composed of two resistors. One terminates to VCCO, the other to ground. The resistor values are 2R. DCI provides termination to VCCO/2 using split termination. The termination resistance is set by the external reference resistors, i.e., the resistors to VCC and ground are each twice the reference resistor value. If users are planning to use HSTL or SSTL standards, the reference resistors should be 50ohms. The DCI I/O standards that support split termination are: HSTL_I_DCI, HSTL_I_DCI_18, HSTL_II_DCI, HSTL_II_DCI_18, SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI. Figure 2-102 illustrates split termination inside a Virtex-II Pro device. VCCO 2R Z0 2R VREF Virtex-II Pro UG012_C2_056_121101 Figure 2-102: Input Termination to VCCO /2 Using DCI Split Termination UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 337 R Chapter 2: Design Considerations Driver with Termination to VCCO (Single Termination) Some I/O standards, such as HSTL Class IV, require an output termination to VCCO. Figure 2-103 illustrates the output termination to VCCO. VCCO R Z0 UG012_C2_057_121101 Figure 2-103: Driver with Termination to VCCO without DCI DCI can provide this termination to VCCO using single termination. In this case, DCI only controls the impedance of the termination, but not the driver. If users are planning to use GTL or HSTL standards, the external reference resistors should be 50-ohms. The DCI I/O standards that support a driver with single termination are: GTL_DCI, GTLP_DCI, HSTL_IV_DCI, and HSTL_IV_DCI_18. Figure 2-104 illustrates a driver with single termination inside a Virtex-II Pro device VCCO R Z0 Virtex-II Pro UG012_C2_058_121101 Figure 2-104: 338 Driver with Termination to VCCO Using DCI Single Termination www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) Driver with Termination to VCCO /2 (Split Termination) Some I/O standards, such as HSTL Class II, require an output termination to VCCO/2. See Figure 2-105. VCCO /2 R Z0 UG012_C2_059_121101 Figure 2-105: Driver with Termination to VCCO /2 without DCI DCI can provide this termination to VCCO/2 using split termination. It only controls the impedance of the termination, but not the driver. For HSTL or SSTL standards, the external reference resistors should be 50-ohms. The DCI I/O standards that support a Driver with split termination are: HSTL_II_DCI, HSTL_II_DCI_18, SSTL2_II_DCI, and SSTL3_II_DCI. Figure 2-106 illustrates a driver with split termination inside a Virtex-II Pro device. VCCO 2R Z0 2R Virtex-II Pro UG012_C2_060_121101 Figure 2-106: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Driver with Termination to VCCO /2 Using DCI Split Termination www.xilinx.com 1-800-255-7778 339 R Chapter 2: Design Considerations Software Support This section lists the valid DCI I/O buffer library components and describes how to use DCI in the Xilinx software. DCI I/O Buffer Library Components The DCI input buffer library components, including global clock buffer, are the following: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 340 IBUFG_GTLP_DCI IBUFG_GTL_DCI IBUFG_HSTL_I_DCI IBUFG_HSTL_II_DCI IBUFG_HSTL_III_DCI IBUFG_HSTL_IV_DCI IBUFG_HSTL_I_DCI_18 IBUFG_HSTL_II_DCI_18 IBUFG_HSTL_III_DCI_18 IBUFG_HSTL_IV_DCI_18 IBUFG_LVDCI_15 IBUFG_LVDCI_18 IBUFG_LVDCI_25 IBUFG_LVDCI_33 IBUFG_LVDCI_DV2_15 IBUFG_LVDCI_DV2_18 IBUFG_LVDCI_DV2_25 IBUFG_SSTL2_I_DCI IBUFG_SSTL2_II_DCI IBUFG_SSTL3_I_DCI IBUFG_SSTL3_II_DCI IBUF_GTLP_DCI IBUF_GTL_DCI IBUF_HSTL_I_DCI IBUF_HSTL_II_DCI IBUF_HSTL_III_DCI IBUF_HSTL_IV_DCI IBUF_LVDCI_15 IBUF_LVDCI_18 IBUF_LVDCI_25 IBUF_LVDCI_33 IBUF_LVDCI_DV2_15 IBUF_LVDCI_DV2_18 IBUF_LVDCI_DV2_25 IBUF_SSTL2_I_DCI IBUF_SSTL2_II_DCI www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) * * IBUF_SSTL3_I_DCI IBUF_SSTL3_II_DCI The following are DCI output buffer library components: * * * * * * * * * * * * * * * * * * * * * OBUF_GTLP_DCI OBUF_GTL_DCI OBUF_HSTL_I_DCI OBUF_HSTL_II_DCI OBUF_HSTL_III_DCI OBUF_HSTL_IV_DCI OBUF_HSTL_I_DCI_18 OBUF_HSTL_II_DCI_18 OBUF_HSTL_III_DCI_18 OBUF_HSTL_IV_DCI_18 OBUF_LVDCI_15 OBUF_LVDCI_18 OBUF_LVDCI_25 OBUF_LVDCI_33 OBUF_LVDCI_DV2_15 OBUF_LVDCI_DV2_18 OBUF_LVDCI_DV2_25 OBUF_SSTL2_I_DCI OBUF_SSTL2_II_DCI OBUF_SSTL3_I_DCI OBUF_SSTL3_II_DCI The following are DCI 3 state output buffer library components: * * * * * * * * * * * * * OBUFT_GTLP_DCI OBUFT_GTL_DCI OBUFT_HSTL_I_DCI OBUFT_HSTL_II_DCI OBUFT_HSTL_III_DCI OBUFT_HSTL_IV_DCI OBUFT_HSTL_I_DCI_18 OBUFT_HSTL_II_DCI_18 OBUFT_HSTL_III_DCI_18 OBUFT_HSTL_IV_DCI_18 OBUFT_LVDCI_15 OBUFT_LVDCI_18 OBUFT_LVDCI_25 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 341 R Chapter 2: Design Considerations * * * * * * * * OBUFT_LVDCI_33 OBUFT_LVDCI_DV2_15 OBUFT_LVDCI_DV2_18 OBUFT_LVDCI_DV2_25 OBUFT_SSTL2_I_DCI OBUFT_SSTL2_II_DCI OBUFT_SSTL3_I_DCI OBUFT_SSTL3_II_DCI The following are DCI I/O buffer library components: * * * * * * * * * * * * * * * IOBUF_GTLP_DCI IOBUF_GTL_DCI IOBUF_HSTL_II_DCI IOBUF_HSTL_IV_DCI IOBUF_SSTL2_II_DCI IOBUF_SSTL3_II_DCI IOBUF_HSTL_II_DCI_18 IOBUF_HSTL_IV_DCI_18 IOBUF_LVDCI_15 IOBUF_LVDCI_18 IOBUF_LVDCI_25 IOBUF_LVDCI_33 IOBUF_LVDCI_DV2_15 IOBUF_LVDCI_DV2_18 IOBUF_LVDCI_DV2_25 How to Use DCI in the Software There are two ways for users to use DCI for Virtex-II Pro devices: 1. Use the IOSTANDARD attribute in the constraint file. 2. Instantiate DCI input or output buffers in the HDL code. IOSTANDARD Attribute The IOSTANDARD attribute can be entered through the NCF or UCF file. The syntax is as follows: NET <net name> IOSTANDARD = LVDCI_25; Where <net name> is the name between the IPAD and IBUF or OPAD or OBUF. For HDL designs, this name is the same as the port name. The following are valid DCI attributes for output drivers: * * * * 342 LVDCI_15 LVDCI_18 LVDCI_25 LVDCI_33 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) * * * LVDCI_DV2_15 LVDCI_DV2_15 LVDCI_DV2_25 The following are valid DCI attributes for terminations: * * * * * * * * * * * * * * GTL_DCI GTLP_DCI HSTL_I_DCI HSTL_II_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 SSTL2_I_DCI SSTL2_II_DCI SSTL3_I_DCI SSTL3_II_DCI VHDL Example Instantiating DCI input and output buffers is the same as instantiating any other I/O buffers. Users must make sure that the correct I/O buffer names are used and follow the standard syntax of instantiation. For example, to instantiate a HSTL Class I output DCI buffer, the following syntax can be used: HSTL_DCI_buffer: OBUF_HSTL_I_DCI port map (I=>data_out, O=>data_out_DCI); Below is an example VHDL code that instantiates four 2.5V LVDCI drivers and four HSTL Class I outputs. -- Module: DCI_TEST --- Description: VHDL example for DCI SelectI/O -- Device: Virtex-II Pro Family --------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dci_test is port (clk, reset, ce, control : in std_logic; A, B : in std_logic_vector (3 downto 0); Dout : out std_logic_vector (3 downto 0); muxout : out std_logic_vector (3 downto 0)); end dci_test; architecture dci_arch of dci_test is --DCI output buffer component declaration component OBUF_LVDCI_25 port (I : in std_logic; O : out std_logic); UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 343 R Chapter 2: Design Considerations end component; attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of OBUF_LVDCI_25 : component is true; attribute black_box_pad_pin of OBUF_LVDCI_25 : component is "O"; --HSTL Class I DCI output buffer component declaration component OBUF_HSTL_I_DCI port (I : in std_logic; O: out std_logic); end component; attribute syn_black_box of OBUF_HSTL_I_DCI : component is true; attribute black_box_pad_pin of OBUF_HSTL_I_DCI : component is "O"; signal muxout_int : std_logic_vector (3 downto 0); signal dout_int : std_logic_vector (3 downto 0); begin process (clk, reset) begin if (reset = '1') then dout_int<="0000"; elsif (clk'event and clk='1') then dout_int<=dout_int+1; end if; end process; process (controls, A, B, DOUT_INT) begin if (control='1') then muxout_int<=A and B; else muxout_int<=Dout_int; end if; end process; U0 : OBUF_LVDCI_25 port map( I=>dout_int(0), O=>dout(0)); U1 : OBUF_LVDCI_25 port map( I=>dout_int(1), O=>dout(1)); U2 : OBUF_LVDCI_25 port map( I=>dout_int(2), O=>dout(2)); U3 : OBUF_LVDCI_25 port map( I=>dout_int(3), O=>dout(3)); K0 : OBUF_HSTL_I_DCI port map( I=>muxout_int(0), O=>muxout(0)); K1 : OBUF_HSTL_I_DCI port map( I=>muxout_int(1), O=>muxout(1)); K2 : OBUF_HSTL_I_DCI port map( I=>muxout_int(2), O=>muxout(2)); K3 : OBUF_HSTL_I_DCI port map( I=>muxout_int(3), 344 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) O=>muxout(3)); end dci_arch; DCI in Virtex-II Pro Hardware DCI only works with certain single-ended I/O standards and does not work with any differential I/O standard. DCI supports the following Virtex-II Pro standards: LVDCI, LVDCI_DV2, GTL_DCI, GTLP_DCI, HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, HSTL_IV_DCI, HSTL_I_DCI_18, HSTL_II_DCI_18, HSTL_III_DCI_18, HSTL_IV_DCI_18, SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI. To correctly use DCI in a Virtex-II Pro device, users must follow the following rules: 1. VCCO pins must be connected to the appropriate VCCO voltage based on the IOSTANDARDs in that bank. 2. Correct DCI I/O buffers must be used in the software either by using IOSTANDARD attributes or instantiations in the HDL code. 3. External reference resistors must be connected to multipurpose pins (VRN and VRP) in the bank. These two multipurpose pins cannot be used as regular user I/Os. Refer to the Virtex-II Pro pinouts for the specific pin locations. Pin VRN must be pulled up to VCCO by its reference resistor. Pin VRP must be pulled down to ground by its reference resistor. 4. The value of the external reference resistors should be selected to give the desired output impedance. If using GTL_DCI, HSTL_DCI, or SSTL_DCI I/O standards, then they should be 50 ohms. 5. The values of the reference resistors must be within the supported range (20 - 100). 6. Follow the DCI I/O banking rules. The DCI I/O banking rules are the following: 1. VREF must be compatible for all of the inputs in the same bank. 2. VCCO must be compatible for all of the inputs and outputs in the same bank. 3. No more than one DCI I/O standard using Single Termination type is allowed per bank. 4. No more than one DCI I/O standard using Split Termination type is allowed per bank. 5. Single Termination and Split Termination, Controlled Impedance Driver, and Controlled Impedance Driver with Half Impedance can co-exist in the same bank. The behavior of DCI 3-state outputs is as follows: If a LVDCI or LVDCI_DV2 driver is in 3-state, the driver is 3-stated. If a Driver with Single or Split Termination is in 3-state, the driver is 3-stated but the termination resistor remains. The following section lists any special care actions that must be taken for each DCI I/O standard. LVDCI_15, LVDCI_18, LVDCI_25, LVDCI_33 Using these buffers configures the outputs as controlled impedance drivers. The number extension at the end indicates the VCCO voltage that should be used. For example, 15 means VCCO=1.5V, etc. There is no slew rate control or drive strength settings for LVDCI drivers. LVDCI_DV2_15, LVDCI_DV2_18, LVDCI_DV2_25 Using these buffers configures the outputs as controlled drivers with half impedance. The number extension at the end indicates the VCCO voltage that should be used. For example, UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 345 R Chapter 2: Design Considerations 15 means VCCO=1.5V, etc. There is no slew rate control or drive strength settings for LVDCI_DV2 drivers. GTL_DCI GTL does not require a VCCO voltage. However, for GTL_DCI, VCCO must be connected to 1.2V. GTL_DCI provides single termination to VCCO for inputs or outputs. GTLP_DCI GTL+ does not require a VCCO voltage. However, for GTLP_DCI, VCCO must be connected to 1.5V. GTLP_DCI provides single termination to VCCO for inputs or outputs. HSTL_ I_DCI, HSTL_ III_DCI, HSTL_ I_DCI_18, HSTL_ III_DCI_18 HSTL_I_DCI provides split termination to VCCO/2 for inputs. HSTL_III_DCI provides single termination to VCCO for inputs. HSTL_ II_DCI, HSTL_ IV_DCI, HSTL_ II_DCI_18, HSTL_ IV_DCI_18 HSTL_II_DCI provides split termination to VCCO/2 for inputs or outputs. HSTL_IV_ DCI provides single termination to VCCO for inputs or outputs. SSTL2_ I_DCI, SSTL3_I_DCI SSTL2_I_DCI and SSTL3_I_DCI provide split termination to VCCO/2 for inputs. These I/O standards provide SSTL compatibility. SSTL2_II_DCI, SSTL3_II_DCI SSTL2_II_DCI and SSTL3_II_DCI provide split termination to VCCO/2 for inputs. These I/O standards provide SSTL compatibility. Figure 2-107 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. 346 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Digitally Controlled Impedance (DCI) HSTL_I HSTL_II VCCO/2 VCCO/2 R Conventional VCCO R Z0 Virtex-II Pro DCI VCCO/2 VCCO Conventional Transmit DCI Receive 2R VCCO R R VCCO VCCO R R Z0 2R 2R Virtex-II Pro DCI Virtex-II Pro DCI VCCO 2R Z0 R Z0 2R 2R 2R Virtex-II Pro DCI R Virtex-II Pro DCI VCCO Virtex-II Pro DCI 2R 2R Reference Resistor Recommended Z0 VCCO R R Z0 N/A Virtex-II Pro DCI Virtex-II Pro DCI Virtex-II Pro DCI VCCO Z0 N/A VCCO R Z0 2R 2R VCCO Z0 Virtex-II Pro DCI VCCO Bidirectional R VCCO 2R Virtex-II Pro DCI VCCO Z0 Z0 Virtex-II Pro DCI VCCO 2R R Z0 Virtex-II Pro DCI 2R Z0 VCCO VCCO VCCO R Virtex-II Pro DCI DCI Transmit DCI Receive VCCO Virtex-II Pro DCI Virtex-II Pro DCI R Z0 Z0 2R VCCO R Z0 R Z0 VCCO R VCCO/2 2R HSTL_IV VCCO R Z0 VCCO/2 DCI Transmit Conventional Receive VCCO/2 R Z0 HSTL_III Virtex-II Pro DCI Virtex-II Pro DCI VRN = VRP = R = Z0 VRN = VRP = R = Z0 VRN = VRP = R = Z0 VRN = VRP = R = Z0 50 50 50 50 UG012_c2_65a_121101 Figure 2-107: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook HSTL DCI Usage Examples www.xilinx.com 1-800-255-7778 347 R Chapter 2: Design Considerations Figure 2-108 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O standards. SSTL2_I SSTL2_II SSTL3_I VCCO/2 VCCO/2 VCCO/2 R VCCO/2 R Conventional R/2 VCCO 25 25 R/2 2R 25 Z0 VCCO/2 Conventional Transmit DCI Receive R/2 2R R/2 VCCO VCCO 2R 25 VCCO VCCO 2R 2R 25 Virtex-II Pro DCI 2R Virtex-II Pro DCI Virtex-II Pro DCI 2R 2R Recommended Z0 2R 2R Virtex-II Pro DCI Virtex-II Pro DCI VCCO VCCO 25 2R 2R Z0 N/A 2R 2R 25 Virtex-II Pro DCI Virtex-II Pro DCI Reference Resistor Virtex-II Pro DCI 2R 2R Z0 N/A Bidirectional 2R 2R Z0 VCCO VCCO 25 VCCO VCCO 25 2R Virtex-II Pro DCI 2R Virtex-II Pro DCI Z0 2R 2R Virtex-II Pro DCI Virtex-II Pro DCI Z0 R/2 2R Virtex-II Pro DCI 2R Z0 2R R Z0 R/2 2R VCCO VCCO/2 Z0 Virtex-II Pro DCI DCI Transmit DCI Receive VCCO 2R 25 2R Virtex-II Pro DCI 2R Z0 Z0 R Z0 VCCO R 2R VCCO/2 R Virtex-II Pro DCI Virtex-II Pro DCI VCCO VCCO 25 2R Z0 2R Virtex-II Pro DCI Z0 R/2 VCCO/2 R R Z0 VCCO/2 Z0 VCCO/2 R Z0 R/2 R VCCO/2 R R Z0 VCCO/2 DCI Transmit Conventional Receive SSTL3_II 25 Virtex-II Pro DCI Virtex-II Pro DCI VRN = VRP = R = Z0 VRN = VRP = R = Z0 VRN = VRP = R = Z0 VRN = VRP = R = Z0 50 50 50 50 UG012_c2_65b_121101 Figure 2-108: SSTL DCI Usage Examples Double-Data-Rate (DDR) I/O Introduction Virtex-II Pro devices have dedicated registers in a single IOB to implement input, output, and output with 3-state control Double-Data-Rate (DDR) registers. Input and output DDR is accomplished with the use of two registers in the IOB. A single clock triggers one register on a Low to High transition and a second register on a High to Low transition. Output DDR with 3-state requires the use of four registers in the IOB clocked in a similar fashion. 348 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O Since the introduction of DLLs, Xilinx devices can generate low-skew clock signals that are 180 degrees out of phase, with a 50/50 duty cycle. These clocks reach the DDR registers in the IOB via dedicated routing resources. Data Flow Input DDR Input DDR is accomplished via a single input signal driving two registers in the IOB. Both registers are clocked on the rising edge of their respective clocks. With proper clock forwarding, alternating bits from the input signal are clocked in on the rising edge of the two clocks, which are 180 degrees out of phase. Figure 2-109 depicts the input DDR registers and the signals involved. D Q Q0 CE CLK0 CK DATA SET/ PRESET RESET/ CLR CE D Q Q1 CE CK CLK1 SET/ PRESET RESET/ CLR SET/PRE RESET/CLR UG002_C2_036_031301 Figure 2-109: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 Input DDR 349 R Chapter 2: Design Considerations CLK0 and CLK1 are 180 degrees out of phase. Both registers share the SET/PRE and RESET/CLR lines. As shown in Figure 2-110, alternating bits on the DATA line are clocked in via Q0 and Q1 while CE is High. The clocks are shifted out of phase by the DCM (CLK0 and CLK180 outputs) or by the inverter available on the CLK1 clock input. CLK0 CLK1 CE DATA OUTPUT Q0 D0A D1A D2A D3A D0A OUTPUT Q1 D4A D5A D7A D4A D2A D1A D6A D3A D8A D6A D5A UG002_C2_037_032201 Figure 2-110: 350 Input DDR Timing Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O Output DDR Output DDR registers are used to clock output from the chip at twice the throughput of a single rising-edge clocking scheme. Clocking for output DDR is the same as input DDR. The clocks driving both registers are 180 degrees out of phase. The DDR MUX selects the register outputs. The output consists of alternating bits from DATA_1 and DATA_2. Figure 2-111 depicts the output DDR registers and the signals involved. DATA2 D Q Q2 CE CLK2 CK SET/ PRESET RESET/ CLR CE DDR MUX DATA1 D Q OUT Q1 CE CLK1 CK SET/ PRESET RESET/ CLR SET/PRE RESET/CLR UG002_C2_038_101300 Figure 2-111: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 Output DDR 351 R Chapter 2: Design Considerations Both registers share the SET/PRE and RESET/CLR line. Both registers share the CE line which must be High for outputs to be seen on Q1 and Q2. Figure 2-112 shows the data flow for the output DDR registers. 1 2 3 4 5 6 CLK1 CLK2 DATA_1 D1A D1B D1C DATA_2 D2A D2B D2C OUT D1A D2A D1B D2B D1C UG002_C2_039_101300 Figure 2-112: Output DDR Timing Diagram 352 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O Output DDR With 3-State Control The 3-state control allows the output to have one of two values, either the output from the DDR MUX or high impedance. The Enable signal is driven by a second DDR MUX (Figure 2-113). This application requires the instantiation of two output DDR primitives. D TRI2 Q Q2 CE CK SET/ PRESET RESET/ CLR DDR MUX CET D TRI1 Q Q1 CE CK SET/ PRESET D DATA1 RESET/ CLR Q Q2 CE CLK1 CK CLK2 SET/ PRESET RESET/ CLR DDR MUX OUT CE D DATA2 Q Q1 CE CK SET/ PRESET RESET/ CLR SET/PRE RESET/CLR UG012_C2_040_121101 Figure 2-113: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Output DDR With 3-State Control www.xilinx.com 1-800-255-7778 353 R Chapter 2: Design Considerations All four registers share the SET/PRESET and RESET/CLEAR lines. Two registers are required to accomplish the DDR task and two registers are required for the 3-state control. There are two Clock Enable signals, one for output DDRs performing the DDR function and another for the output DDRs performing the 3-state control function. Two 180 degree out of phase clocks are used. CLK1 clocks one of the DDR registers and a 3-state register. CLK2 clocks the other DDR register and the other 3-state register. The DDR registers and 3-state registers are associated by the clock that is driving them. Therefore, the DDR register that is clocked by CLK1 is associated to the 3-state register being clocked by CLK1. The remaining two registers are associated by CLK2. If both 3-state registers are driving a logic High, the output sees a high impedance. If both 3-state registers are driving a logic Low, the output sees the values from the DDR MUX see Figure 2-114). CLK1 CLK2 DATA_1 D1A D1B D1C D1D DATA_2 D2A D2B D2C D2D TRI 1 TRI 2 OUT D1A D2A D1B D2B D1C ZZZ UG002_C2_041_101300 Figure 2-114: Timing Diagram for Output DDR With 3-State Control When the 3-state registers are not driving the same logic value, the 3-state register being clocked by CLK1 is called TREG1. The other 3-state register TREG2 is clocked by CLK2. Similarly, the DDR register being clocked by CLK1 is called DREG1, and the other DDR register DREG2 is clocked by CLK2. If TREG1 is driving a logic High and TREG2 is driving a logic Low, the output sees a high impedance when CLK1 is High and the value out of DREG2 when CLK2 is High. If TREG2 is driving a logic High and TREG1 is driving a logic Low, the output sees a high impedance when CLK2 is High and the value out of DREG1 when CLK1 is High. Characteristics 354 * * * * All registers in an IOB share the same SET/PRE and RESET/CLR lines. * When several clocks are used, and when using DDR registers, the floorplan of a design should take into account that the input clock to an IOB is shared with a pair of IOBs. The 3-State and Output DDR registers have common clocks (OTCLK1 & OTCLK2). All signals can be inverted (with no added delay) inside the IOB. DDR MUXing is handled automatically within the IOB. There is no manual control of the MUX-select. This control is generated from the clock. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O Library Primitives Input DDR registers are inferred, and dedicated output DDR registers have been provided as primitives for Virtex-II Pro designs. Input DDR registers consist of two inferred registers that clock in a single data line on each edge. Generating 3-state output with DDR registers is as simple as instantiating a primitive. S FDDRRSE D0 Q D1 CE C0 C1 R UG002_C2_034_032201 Figure 2-115: FDDRRSE Symbol: DDR Flip-Flop With Clock Enable and Synchronous Reset and Set PRE FDDRCPE D0 Q D1 CE C0 C1 CLR UG002_C2_035_101300 Figure 2-116: FDDRCPE Symbol: DDR Flip-Flop With Clock Enable and Asynchronous PRESET and CLR VHDL and Verilog Instantiation Examples are available in VHDL and Verilog Templates, page 357. In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. Constraints file syntax is provided where input registers need to be used. These settings force the input DDR registers into the IOB. The output registers should be instantiated and do not require any constraints file syntax to be pushed into the IOB. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 355 R Chapter 2: Design Considerations Port Signals FDDRRSE Data inputs - D0 and D1 D0 and D1 are the data inputs into the DDR flip-flop. Data on the D0 input is loaded into the flip-flop when R and S are Low and CE is High during a Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when R and S are Low and CE is High during a Low-to-High C1 clock transition. Clock Enable - CE The enable pin affects the loading of data into the DDR flip-flop. When Low, new data is not loaded into the flip-flop. CE must be High to load new data into the flip-flop. Clocks - C0 and C1 These two clocks are phase shifted 180 degrees (via the DLL) and allow selection of two separate data inputs (D0 and D1). Synchronous Set - S and Synchronous Reset - R The Reset (R) input, when High, overrides all other inputs and resets the output Low during any Low-to-High clock transition (C0 or C1). Reset has precedence over Set. When the Set (S) input is High and R is Low, the flip-flop is set, output High, during a Low-toHigh clock transition (C0 or C1). Data Output - Q When power is applied, the flip-flop is asynchronously cleared and the output is Low. During normal operation, The value of Q is either D0 or D1. The Data Inputs description above states how the value of Q is chosen. FDDRCPE Data inputs - D0 and D1 D0 and D1 are the data inputs into the DDR flip-flop. Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE is High during a Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE is High during a Low-to-High C1 clock transition. Clock Enable - CE The enable pin affects the loading of data into the DDR flip-flop. When Low, clock transitions are ignored and new data is not loaded into the flip-flop. CE must be High to load new data into the flip-flop. Clocks - C0 and C1 These two clocks are phase shifted 180 degrees (via the DLL) and allow selection of two separate data inputs (D0 and D1). Asynchronous Preset - PRE and Asynchronous Clear - CLR The Preset (PRE) input, when High, sets the Q output High. When the Clear (CLR) input is High, the output is reset to Low. Data Output - Q When power is applied, the flip-flop is asynchronously cleared and the output is Low. During normal operation, The value of Q is either D0 or D1. The Data Inputs description above states how the value of Q is chosen. 356 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O Initialization in VHDL or Verilog Output DDR primitives can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the attributes are attached to the output DDR instantiation and are copied in the EDIF output file to be compiled by Xilinx tools. The VHDL code simulation uses a generic parameter to pass the attributes. The Verilog code simulation uses the defparam parameter to pass the attributes. The DDR code examples (in VHDL ad Verilog) illustrate the following techniques. Location Constraints DDR instances can have LOC properties attached to them to constrain pin placement. The LOC constraint uses the following form. NET <net_name> LOC=A8; Where "A8" is a valid I/O pin location. Applications DDR SDRAM The DDR SDRAM is an enhancement to the Synchronous DRAM by effectively doubling the data throughput of the memory device. Commands are registered at every positive clock edge. Input data is registered on both edges of the data strobe, and output data is referenced to both edges of the data strobe, as well as both edges of the clock. Clock Forwarding DDR can be used to forward a copy of the clock on the output. This can be useful for propagating a clock along with double-data-rate data that has an identical delay. It is also useful for multiple clock generation, where there is a unique clock driver for every clock load. VHDL and Verilog Templates VHDL and Verilog templates are available for output, output with 3-state enable, and input DDR registers. Input DDR To implement an Input DDR application, paste the following template in your code. DDR_input.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DDR_Input is Port ( clk : in std_logic; d : in std_logic; rst : in std_logic; q1 : out std_logic; q2 : out std_logic ); end DDR_Input; --Describe input DDR registers (behaviorally) to be inferred architecture behavioral of DDR_Input is UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 357 R Chapter 2: Design Considerations begin q1reg : process (clk, d, rst) begin if rst='1' then --asynchronous reset, active high q1 <= '0'; elsif clk'event and clk='1' then --Clock event - posedge q1 <= d; end if; end process; q2reg : process (clk, d, rst) begin if rst='1' then --asynchronous reset, active high q2 <= '0'; elsif clk'event and clk='0' then --Clock event - negedge q2 <= d; end if; end process; end behavioral; ------------ NOTE: You must include the following constraints in the .ucf file when running back-end tools, in order to ensure that IOB DDR registers are used: INST "q2_reg" IOB=TRUE; INST "q1_reg" IOB=TRUE; Depending on the synthesis tools you use, it may be required to check the edif file for modifications to original net names...in this case, Synopsys changed the names: q1 and q2 to q1_reg and q2_reg DDR_input.v module DDR_Input (data_in , q1, q2, clk, rst); input data_in, clk, rst; output q1, q2; reg q1, q2; //Describe input DDR registers (behaviorally) to be inferred always @ (posedge clk or posedge rst) //rising-edge DDR reg. and asynchronous reset begin if (rst) q1 = 1'b0; else q1 = data_in; end always @ (negedge clk or posedge rst) //falling-edge DDR reg. and asynchronous reset 358 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O begin if (rst) q2 = 1'b0; else q2 = data_in; end assign data_out = q1 & q2; endmodule /* NOTE: You must include the following constraints in the .ucf file when running back-end tools, \ in order to ensure that IOB DDR registers are used: INST "q2_reg" IOB=TRUE; INST "q1_reg" IOB=TRUE; Depending on the synthesis tools you use, it may be required to check the edif file for modifications to original net names...in this case, Synopsys changed the names: q1 and q2 to q1_reg and q2_reg */ Output DDR To implement an Output DDR application, paste the following template in your code. DDR_out.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- pragma translate_off LIBRARY UNISIM; use UNISIM.VCOMPONENTS.ALL; --pragma translate_on entity DDR_Output is Port( clk : in std_logic; --clk and clk180 can be outputs from the DCM or clk180 can be the clk180 : in std_logic; --logical inverse of clk (the inverter is located in the IOB and will be inferred. d0 : in std_logic; --data in to fddr d1 : in std_logic; --data in to fddr ce : in std_logic; --clock enable rst : in std_logic; --reset set : in std_logic; --set q : out std_logic --DDR output ); end DDR_Output; architecture behavioral of DDR_Output is component FDDRRSE port( Q : out std_logic; D0 : in std_logic; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 359 R Chapter 2: Design Considerations D1 : in std_logic; C0 : in std_logic; C1 : in std_logic; CE : in std_logic; R : in std_logic; S : in std_logic ); end component; begin U0: FDDRRSE port map ( Q => q, D0 => d0, D1 => d1, C0 => clk, C1 => clk180, CE => ce, R => rst, S => set ); end behavioral; DDR_out.v module DDR_Output (d0 , d1, q, clk, clk180, rst, set, ce); input d0, d1, clk, clk180, rst, set, ce; output q; //Synchronous Output DDR primitive instantiation FDDRRSE U1 ( .D0(d0), .D1(d1), .C0(clk), .C1(clk180), .CE(ce), .R(rst), .S(set), .Q(q) ); endmodule Output DDR With 3-State Enable To implement an Output DDR with 3-state Enable, paste the following template in your code: DDR_3state.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- pragma translate_off LIBRARY UNISIM; use UNISIM.VCOMPONENTS.ALL; --pragma translate_on entity DDR_3state is Port( 360 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Double-Data-Rate (DDR) I/O clk : in std_logic; --clk and clk180 can be outputs from the DCM or clk180 can be the clk180 : in std_logic; --logical inverse of clk (the inverter is located in the IOB and will be inferred. d0 : in std_logic; --data in to fddr d1 : in std_logic; --data in to fddr ce : in std_logic; --clock enable set : in std_logic; --set rst : in std_logic; --reset en0 : in std_logic; --enable signal en1 : in std_logic; --enable signal data_out : out std_logic --data seen at pad ); end DDR_3state; architecture behavioral of DDR_3state is signal ddr_out, tri : std_logic; component FDDRRSE port ( Q : out std_logic; D0 : in std_logic; D1 : in std_logic; C0 : in std_logic; C1 : in std_logic; CE : in std_logic; R : in std_logic; S : in std_logic ); end component; begin --Instantiate Ouput DDR registers U0: FDDRRSE port map(Q => tri, D0 => en0, D1 => en1, C0 => clk, C1 => clk180, CE => ce, R => rst, S => set ); --Instantiate three-state DDR registers U1: FDDRRSE port map( Q => ddr_out, D0 => d0, D1 => d1, C0 => clk, C1 => clk180, CE => ce, R => rst, S => set ); --inferr the 3-State buffer process(tri, ddr_out) begin if tri = '1' then UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 361 R Chapter 2: Design Considerations data_out <= 'Z'; elsif tri = '0' then data_out <= ddr_out; end if; end process; end behavioral; DDR_3state.v module DDR_3state (d0 , d1, data_out, en_0, en_1, clk, clk180, rst, set, ce); input d0, d1, clk, clk180, rst, set, ce, en_0, en_1; output data_out; reg data_out; wire q, q_tri; //Synchronous Output DDR primitive instantiation FDDRRSE U1 ( .D0(d0), .D1(d1), .C0(clk), .C1(clk180), .CE(ce), .R(rst), .S(set), .Q(q) ); //Synchronous 3-State DDR primitive instantiation FDDRRSE U2 ( .D0(en_0), .D1(en_1), .C0(clk), .C1(clk180), .CE(ce), .R(rst), .S(set), .Q(q_tri) ); //3-State buffer description always @ (q_tri or q) begin if (q_tri) data_out = 1'bz; else data_out = q; end endmodule 362 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R LVDS I/O LVDS I/O Introduction Low Voltage Differential Signaling (LVDS) is a very popular and powerful high-speed interface in many system applications. Virtex-II Pro I/Os are designed to comply with the IEEE electrical specifications for LVDS to make system and board design easier. With the addition of an LVDS current-mode driver in the IOBs, which eliminates the need for external source termination in point-to-point applications, and with the choice of an extended mode, Virtex-II Pro devices provide the most flexible solution for doing an LVDS design in an FPGA. Table 2-68 lists all LVDS primitives that are available for Virtex-II Pro devices. Table 2-68: Available Virtex-II Pro LVDS Primitives Input Output 3-State Clock IBUF_LVDS OBUF_LVDS OBUFT_LVDS IBUFG_LVDS IBUFDS_LVDS_25 OBUFDS_LVDS_25 OBUFTDS_LVDS_25 IBUFGDS_LVDS_25 IBUFDS_LVDSEXT_25 OBUFDS_LVDSEXT_25 OBUFTDS_LVDSEXT_25 IBUFGDS_LVDSEXT_25 Bi-Directional IOBUF_LVDS The primitives in bold type are pre-existing LVDS primitives used in Virtex-E and earlier designs. They are not current-mode drivers and are still required for BLVDS (Bus LVDS) applications. *DS_LVDS_25 = 2.5V VCCO LVDS Buffer There are no differences in the AC characteristics of any LVDS I/O. These choices now provide more flexibility for mixed-I/O banking rules: for example, an LVCMOS I/O can coexist with the 2.5V LVDS buffer in the same bank. *DS_LVDSEXT* = Extended mode LVDS buffer This buffer provides a higher drive capability and voltage swing (350 - 750 mV), which makes it ideal for long-distance or cable LVDS links. The output AC characteristics of this LVDS driver are not within the EIA/TIA specifications. This LVDS driver is intended for situations that require higher drive capabilities in order to produce an LVDS signal that is within EIA/TIA specification at the receiver. Creating an LVDS Input/Clock Buffer Figure 2-117 illustrates the LVDS input and clock buffer primitives shown in Table 2-69. The pin names used are the same as those used in the HDL library primitives. Table 2-69: LVDS Input and Clock Buffer Primitives LVDS Inputs LVDS Clocks IBUFDS_LVDS_25 IBUFGDS_LVDS_25 IBUFDS_LVDSEXT_25 IBUFGDS_LVDSEXT_25 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 363 R Chapter 2: Design Considerations IBUFDS_LVDS*/IBUFGDS_LVDS* I + IB - O UG002_C2_031_100200 Figure 2-117: LVDS Input and Clock Primitives To create an LVDS input, instantiate the desired mode (2.5V or Extended) LVDS input buffer. Notice that the P and N channels are included in the primitive (I = P, IB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel. The same applies to LVDS clocks: Use IBUFGDS_LVDS* LVDS Input HDL Examples VHDL Instantiation U1: IBUFDS_LVDS_25 port map ( I => data_in_P, IB => data_in_N O => data_in ); Verilog Instantiation IBUFDS_LVDS_25 U1 ( .I(data_in_P), .IB(data_in_N), .O(data_in) ); Port Signals I = P-channel data input to the LVDS input buffer IB = N-channel data input to the LVDS input buffer O = Non-differential input data from LVDS input buffer Location Constraints NET "data_in_P" LOC= "NS"; LVDS Receiver Termination All LVDS receivers require standard termination. Figure 2-118 is an example of a typical termination for an LVDS receiver on a board with 50 transmission lines. LVDS Line Driver P Z0 = 50 Virtex-II Pro FPGA IN 100 Data out Data in Z 0 = 50 INX N IBUFDS_LVDS UG012_C2_028_121101 Figure 2-118: LVDS Receiver Termination 364 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R LVDS I/O Creating an LVDS Output Buffer Figure 2-119 illustrates the LVDS output buffer primitives: * * OBUFDS_LVDS_25 OBUFDS_LVDSEXT_25 The pin names used are the same as those used in the HDL library primitives. OBUFDS_LVDS* I + O - OB UG002_C2_032_100200 Figure 2-119: LVDS Output Buffer Primitives To create an LVDS output, instantiate the desired mode (2.5 or Extended) LVDS output buffer. Notice that the P and N channels are included in the primitive (O = P, OB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel. LVDS Output HDL Examples VHDL Instantiation U1: OBUFDS_LVDS_25 port map ( I => data_out, O => data_out_P, OB => data_out_N ); Verilog Instantiation OBUFDS_LVDS_25 U1 ( .I(data_out), .O(data_out_P), .OB(data_out_N) ); Port Signals I = data input to the LVDS input buffer O = P-channel data output OB = N-channel data output Location Constraints NET "data_out_P" LOC= "NS"; LVDS Transmitter Termination The Virtex-II Pro LVDS transmitter does not require any termination. Table 2-68 lists primitives that correspond to the Virtex-II Pro LVDS current-mode drivers. Virtex-II Pro LVDS current-mode drivers are a true current source and produce the proper UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 365 R Chapter 2: Design Considerations (IEEE/EIA/TIA compliant) LVDS signal. Figure 2-120 illustrates a Virtex-II Pro LVDS transmitter on a board with 50 transmission lines. Virtex-II Pro FPGA Z0 = 50 P OUT 100 Data out + - Data in Z 0 = 50 OUTX N OBUFDS_LVDS UG012_C2_029_121101 Figure 2-120: LVDS Transmitter Termination Creating an LVDS Output 3-State Buffer Figure 2-121 illustrates the LVDS 3-state buffer primitives: * * OBUFTDS_LVDS_25 OBUFTDS_LVDSEXT_25 The pin names used are the same as those used in the HDL library primitives. OBUFTDS_LVDS* T I + O - OB UG002_C2_033_100200 Figure 2-121: LVDS 3-State Primitives To create an LVDS 3-State output, instantiate the desired mode (2.5V, or Extended) LVDS 3-state buffer. Notice that the P and N channels are included in the primitive (O = P, OB = N). Software automatically uses the appropriate pin from an adjacent IOB for the N channel. LVDS 3-State HDL Example VHDL Instantiation U1: OBUFTDS_LVDS_25 port map ( I => data_out, T => tri, O => data_out_P, OB => data_out_N ); Verilog Instantiation OBUFTDS_LVDS_25 366 U1 ( .I(data_out), .T(tri), www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R LVDS I/O .O(data_out_P), .OB(data_out_N) ); Port Signals I = data input to the 3-state output buffer T = 3-State control signal O = P-channel data output OB = N-channel data output Location Constraints NET "data_out_P" LOC = "NS"; LVDS 3-State Termination The Virtex-II Pro LVDS 3-state buffer does not require any termination. Table 2-68 lists primitives that correspond to Virtex-II Pro LVDS current-mode drivers. These drivers are a true current source, and they produce the proper (IEEE/EIA/TIA compliant) LVDS signal. Figure 2-122 illustrates a simple redundant point-to-point LVDS solution with two LVDS 3-state transmitters sharing a bus with one LVDS receiver and the required termination for the circuit. Virtex-II Pro FPGA Virtex-II Pro FPGA + + - - 100 OBUFTDS_LVDS* + OBUFTDS_LVDS* - LVDS Receiver Figure 2-122: UG012_C2_030_121101 LVDS 3-State Termination Creating a Bidirectional LVDS Buffer Since LVDS is intended for point-to-point applications, BLVDS (Bus-LVDS) is not an IEEE/EIA/TIA standard implementation and requires careful adaptation of I/O and PCB layout design rules. The primitive supplied in the software library for bi-directional LVDS does not use the Virtex-II Pro LVDS current-mode driver. Therefore, source termination is required. Refer to xapp243 for examples of BLVDS termination. The following are VHDL and Verilog instantiation examples of Virtex-II Pro BLVDS primitves. VHDL Instantiation blvds_io: IOBUFDS_BLVDS_25 port map ( I => data_out, O => data_in, T => tri, IO => data_IO_P, IOB => data_IO_N ); UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 367 R Chapter 2: Design Considerations Verilog Instantiation IOBUFDS_BLVDS_25 blvds_io ( .I(data_out), .O(data_in), .T(tri), .IO(data_IO_P), .IOB(data_IO_N) ); Port Signals I = data output: internal logic to LVDS I/O buffer T = 3-State control to LVDS I/O buffer IO = P-channel data I/O to or from BLVDS pins IOB = N-channel data I/O to or from BLVDS pins O = Data input: off-chip data to LVDS I/O buffer Location Constraints Only the P or N channel must be constrained. Software automatically places the corresponding channel of the pair on the appropriate pin. LDT Lightning Data Transport (LDT) is a high speed interface and protocol introduced by Advanced Micro Devices. LDT is a differential signaling based interface that is very similar to LVDS. Virtex-II Pro IOBs are equipped with LDT buffers. These buffers also have corresponding software primitives as follows: IBUFDS_LDT_25 IBUFGDS_LDT_25 OBUFDS_LDT_25 OBUFTDS_LDT_25 LDT Implementation LDT implementation is the same as LVDS with DDR, so follow all of the rules and guidelines set forth earlier in this chapter for LVDS-DDR, and replace the LVDS buffer with the corresponding LDT buffer. For more information on Virtex-II Pro LDT electrical specification, refer to the Virtex-II Pro Data Sheet. Bitstream Encryption Virtex-II Pro devices have an on-chip decryptor that can be enabled to make the configuration bitstream (and thus the whole logic design) secure. The user can encrypt the bitstream in the Xilinx software, and the Virtex-II Pro chip then performs the reverse operation, decrypting the incoming bitstream, and internally recreating the intended configuration. This method provides a very high degree of design security. Without knowledge of the encryption/decryption key or keys, potential pirates cannot use the externally intercepted bitstream to analyze, or even to clone the design. System manufacturers can be sure that their Virtex-II Pro implemented designs cannot be copied and reverse engineered. Also, IP Virtex-II Pro chips that contain the correct decryption key. The Virtex-II Pro devices store the internal decryption keys in a few hundred bits of dedicated RAM, backed up by a small externally connected battery. At <100 nA load, the endurance of the battery is only limited by its shelf life. The method used to encrypt the data is Data Encryption Standard (DES). This is an official standard supported by the National Institute of Standards and Technology (NIST) and the 368 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Bitstream Encryption U. S. Department of Commerce. DES is a symmetric encryption standard that utilizes a 56bit key. Because of the increased sophistication and speed of today's computing hardware, single DES is no longer considered to be secure. However, the Triple Data Encryption Algorithm (TDEA), otherwise known as triple DES, is authorized for use by U. S. federal organizations to protect sensitive data and is used by many financial institutions to protect their transactions. Triple DES has yet to be cracked. Both DES and triple DES are available in Virtex-II Pro devices. What DES Is DES and triple DES are symmetric encryption algorithms. This means that the key to encrypt and the key to decrypt are the same. The security of the data is kept by keeping the key secret. This contrasts to a public key system, like RSA or PGP. One thing to note is that Virtex-II Pro devices use DES in Cipher Block Chaining mode. This means that each block is combined with the previous encrypted block for added security. DES uses a single 56-bit key to encrypt 64-bit blocks one at a time. How Triple DES is Different Triple DES uses three keys (known as a key bundle or key set), and the encryption algorithm is repeated for each of those keys. If EK(I) and DK(I) denote the encryption and decryption of a data block I using key K, the Triple DES encryption algorithm is as follows (known as E-D-E): Outputencrypted = EK3(DK2(EK1(I))) And the decryption algorithm is as follows (known as D-E-D): Outputdecrypted = DK1(EK2(DK3(I))) K1 = K2 = K3 gives the same result as single DES. For a detailed description of the DES standard, refer to: http://www.itl.nist.gov/fipspubs/fip46-2.htm For a popular description of the origin and the basic concept of DES and many other older and newer encryption schemes, see the recent best-seller: The Code Book by Simon Singh, Doubleday 1999, ISBN 0-385-49531-5 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 369 R Chapter 2: Design Considerations Classification and Export Considerations Virtex-II Pro FPGAs have been classified by the U. S. Department of Commerce as an FPLD (3A001.a.7), which is the same classification as current FPGAs. Only the decryptor is onchip and can only be used to decrypt an incoming bitstream, so the classification has not changed and no new paperwork is required. The software has been classified under ECCN#:5D002 and can be exported globally under license exception ENC. No changes to current export practices are necessary. Creating Keys For Virtex-II Pro, DES or triple DES (TDEA) can be used. DES uses a single 56-bit key, where triple-DES always uses three such keys. All of the keys can be chosen by the BitGen program at random, or can be explicitly specified by the user. Virtex-II Pro devices can have six separate keys programmed into the device. A particular Virtex-II Pro device can store two sets of triple-DES keys and can thus accept alternate bitstreams from two competing IP vendors, without providing access to each other's design. However, all of the keys must be programmed at once. An encrypted bitstream is created by the BitGen program. Keys and key options can be chosen in two ways: by command-line arguments to BitGen, or by specifying a KeyFile (with the -g KeyFile command-line option). The BitGen options relevant to encryption are listed in Table 2-70.: Table 2-70: 370 BitGen Encryption Options Option Description Values (default first where appropriate) Encrypt Whether to encrypt the bitstream No, Yes Key0 DES Key 0 pick, <hex string> Key1 DES Key 1 pick, <hex string> Key2 DES Key 2 pick, <hex string> Key3 DES Key 3 pick, <hex string> Key4 DES Key 4 pick, <hex string> Key5 DES Key 5 pick, <hex string> KeyFile Location of separate key definition file <string> Keyseq0 Set the key sequence for key 0 (S = single, F = first, M = middle, L = last) S,F,M,L Keyseq1 Set the key sequence for key 1 S,F,M,L Keyseq2 Set the key sequence for key 2 S,F,M,L Keyseq3 Set the key sequence for key 3 S,F,M,L Keyseq4 Set the key sequence for key 4 S,F,M,L Keyseq5 Set the key sequence for key 5 S,F,M,L StartKey Key number to start decryption 0,3 StartCBC Constant Block Chaining start value pick, <string> www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Bitstream Encryption The key sequence (Keyseq) is set to S for single key encryption, F for first key in multi-key encryption, M for middle key in multi-key encryption, and L for last key in multi-key encryption. When the KeyFile option is specified, BitGen looks in that file for all other DES key options listed above. An example for the input KeyFile using triple DES is: # Comment for key file Key 0 0x9ac28ebeb2d83b; Key 1 pick; Key 2 string for my key; Key 3 0x00000000000000; Key 4 8774eb3ebb4f84; Keyseq 0 F; Keyseq 1 M; Keyseq 2 L; Keyseq 3 F; Keyseq 4 M; Keyseq 5 L; Key StartCBC 503f2f655b1b2f82; StartKey 0; Every key is given in the output key file, with unused key locations set to "0x0000000000000000." The proper key sequence prefix is added for all used keys. The prefix is preserved for unused keys, if the user specified a value. The output key file has the same base file name as the .bit file, but with a .nky file extension. The command line equivalent of the input key file above is as follows: bitgen -g Encrypt:Yes -g Key0: 0x9ac28ebeb2d83b -g Key1:pick -g Key2:" string for my key" -g Key30x00000000000000 -g Key4:8774eb3ebb4f84 -g Keyseq0:F, -g Keyseq1:M, -gKeyseq2:L -g Keyseq3:F -g Keyseq4:M -g Keyseq5:L -g StartCBC:503f2f655b1b2f82 -g StartKey:0 myinput.ncd If the key file is used, the command line is as follows: Bitgen -g Encrypt:Yes -g KeyFile: mykeyfile myinput.ncd The output key file from either of the above inputs looks something like this: Device 2v40CS144; Key 0 0x9ac28ebeb2d83b; Key 1 0xdb1adb5f08b972; Key 2 0x5452032773c286; Key 3 0x00000000000000; Key 4 0x8774eb3ebb4f84; Key 5 0x00000000000000; Keyseq 0 F; Keyseq 1 M; Keyseq 2 L; Keyseq 3 F; Keyseq 4 M; Keyseq 5 L; Key StartCBC 0x503f2f655b1b2f82; StartKey 0; In the case of the string for Key2, if the keyvalue is a character string, BitGen encodes the string into a 56-bit hex string. The same character string gives the same 56-bit hex string every time. This enables passwords or phrases to be used instead of hex strings. The above keys are all specified as 64 bits each. The first 8 bits are used by Xilinx as header information and the following 56 bits as the key. BitGen accepts 64 bit keys, but automatically overrides the header, if necessary. Because of security issues, the -g Compress option cannot be used with bitstream encryption. Also, partial reconfiguration is not allowed. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 371 R Chapter 2: Design Considerations Loading Keys DES keys can only be loaded through JTAG. The JTAG Programmer and iMPACTTM tools have the capability to take a .nky file and program the device with the keys. In order to program the keys, a "key-access mode" is entered. When this mode is entered, all of the FPGA memory, including the keys and configuration data, is cleared. Once the keys are programmed, they cannot be reprogrammed without clearing the entire device. This "key access mode" is completely transparent to most users. Keys are programmed using the ISC_PROGRAM instruction, as detailed in the JTAG 1532 specification. SVF generation is also supported, if keys are to be programmed using a different method, such as a microprocessor or JTAG test software. Loading Encrypted Bitstreams Once the device has been programmed with the correct keys, the device can be configured with an encrypted bitstream. Non-encrypted bitstreams may also be used to configure the device, and the stored keys are ignored. The method of configuration is not at all affected by encryption. Any of the modes may be used, and the signaling does not change (see Chapter 3: Configuration). However, all bitstreams must configure the entire device, since partial reconfiguration is not permitted. Once the device has been configured with an encrypted bitstream, it cannot be reconfigured without toggling the PROG pin, cycling power, or performing the JTAG JSTART instruction. All of these events fully clear the configuration memory, but none of these events reset the keys as long as VBATT or VCCAUX are maintained. VBATT VBATT is a separate battery voltage to allow the keys to remain programmed in the Virtex-II Pro device. VBATT draws very little current (on the order of nA) to keep the keys programmed. A small watch battery is suitable (refer to VBATT DC Characteristics in the Virtex-II Pro Data Sheet and the battery's specifications to estimate its lifetime). While the auxiliary voltage (VCCAUX) is applied, VBATT does not draw any current, and the battery can be removed or exchanged. Platform Generator Xilinx Platform Generator is a tool to help with designing embedded systems on the Virtex-II Pro platform. It presents users with a graphical user interface (GUI) for creating CoreConnect-based embedded systems. * * * Provides memory mapping information Creates FPGA implementation files, software interface file, BSPs, etc. User specifies and configures processors, buses, and peripherals For more details, refer to www.xilinx.com/virtex2pro/. CORE Generator System Introduction This section on the Xilinx CORE GeneratorTM System and the Xilinx Intellectual Property (IP) Core offerings is provided as an overview of products that facilitate the Virtex-II Pro design process. For more detailed and complete information, consult the CORE Generator Guide, which can be accessed online in the Xilinx software installation, as well as at the 372 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm site under the "Design Entry Tools" heading. The CORE Generator System The Xilinx CORE Generator System is the cataloging, customization, and delivery vehicle for IP cores targeted to Xilinx FPGAs. This tool is included with all Xilinx ISE BaseX, ISE Foundation, and ISE Alliance Series software packages. The CORE Generator provides centralized access to a catalog of ready-made IP functions ranging in complexity from simple arithmetic operators, such as adders, accumulators, and multipliers, to systemlevel building blocks, such as filters, transforms, and memories. Cores can be displayed alphabetically, by function, by vendor, or by type. Each core comes with its own data sheet, which documents the core's functionality in detail. The CORE Generator User Interface (see Figure 2-123) has direct links to key Xilinx web support pages, such as the Xilinx IP Center website (www.xilinx.com/ipcenter) and Xilinx Technical Support, making it very easy to access the latest Virtex-II Pro IP releases and get helpful, up-to-date specifications and information on technical issues. Links to partner IP providers are also built into the informational GUIs for the various partner-supplied AllianceCORE products described under AllianceCORE Program, page 377. The use of CORE Generator IP cores in Virtex-II Pro designs enables designers to shorten design time, and it also helps them realize high levels of performance and area efficiency without any special knowledge of the Virtex-II Pro architecture. The IP cores achieve these high levels of performance and logic density by using Xilinx Smart-IPTM technology. ug002_c2_068b_100901 Figure 2-123: Core Generator User Interface Smart-IP Technology Smart-IP technology leverages Xilinx FPGA architectural features, such as look-up tables (LUTs), distributed RAM, segmented routing and floorplanning information, as well as relative location constraints and expert logic mapping to optimize the performance of every core instance in a given Xilinx FPGA design. In the context of Virtex-II Pro cores, Smart-IP technology includes the use of the special high-performance Virtex-II Pro UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 373 R Chapter 2: Design Considerations architectural features, such as embedded 18x18 multipliers, block memory, shift register look-up tables (SRL16's), and special wide mux elements. Smart-IP technology delivers: * * * * * * Physical layouts optimized for high performance Predictable high performance and efficient resource utilization Reduced power requirements through compact design and interconnect minimization Performance independent of device size Ability to use multiple cores without deterioration of performance Reduced compile time over competing architectures CORE Generator Design Flow A block diagram of the CORE Generator design flow is shown in Figure 2-124. Design Entry Design Verification HDL Wrapper Symbol CORE Generator System User Design (HDL or Schematic) HDLTemplate Functional Simulation Synthesis (User design only) CORE Generator Output Files Timing Simulation Netlist Netlist Place & Route Netlist Constraints Design Implementation ug002_c2_069_101001 Figure 2-124: CORE Generator Design Flow Note: 1. The outputs produced by the CORE Generator consist of an implementation Netlist and optional schematic symbol, HDL template files, and HDL simulation model wrapper files. Core Types Parameterized Cores The CORE Generator System supplies a wide assortment of parameterized IP cores that can be customized to meet specific Virtex-II Pro design needs and size constraints. See Figure 2-125. For each parameterized core, the CORE Generator System supplies: 374 * * A customized EDIF implementation netlist (.EDN) * * Verilog or VHDL templates (.VEO, .VHO) A parameterized Verilog or VHDL behavioral simulation model (.V, .VHD) and corresponding wrapper file (also .V, .VHD) An ISE Foundation or Viewlogic(R) schematic symbol www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System The EDIF implementation netlist is used by the Xilinx tools to implement the core. The other design files generated depend on the Design Entry settings specified (target CAE vendor, and design flow type -- schematic or HDL). Schematic symbol files are generated when a schematic design flow is specified for the project. Parameterized HDL simulation models are provided in two separate HDL simulation libraries, one for Verilog functional simulation support, and the other for VHDL functional simulation support. The libraries, which are included as part of the Xilinx installation, are in the following locations: $XILINX/verilog/src/XilinxCoreLib $XILINX/vhdl/src/XilinxCoreLib ug002_c2_070a_100501 Figure 2-125: Core Customization Window for a Parameterized Core If using a compiled simulator, these libraries must be precompiled before performing a functional simulation of the cores. An analyze_order file describing the required compile order of these models is included with each XilinxCoreLib library, one for Verilog (verilog_analyze_order) and one for VHDL (vhdl_analyze_order). For an HDL design flow, Verilog and VHDL templates (.VEO and .VHO files) are also provided to facilitate the integration of the core into the design for the purposes of functional simulation, synthesis, and implementation. The Verilog (.V) and VHDL (.VHD) wrapper files are also generated. The wrapper files for a particular core are compiled like normal simulation models. They convey custom parameter values to the corresponding generic, parameterized behavioral model for that core in the XilinxCoreLib library. The custom parameter values are used to tailor the behavior of the customized core. The following is a sample VHO template: component adder8 port ( a: IN std_logic_VECTOR(7 downto 0); b: IN std_logic_VECTOR(7 downto 0); c: IN std_logic; ce: IN std_logic; UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 375 R Chapter 2: Design Considerations ci: IN std_logic; clr: IN std_logic; s: OUT std_logic_VECTOR(8 downto 0)); end component; -- Synplicity black box declaration attribute black_box : boolean; attribute black_box of test: component is true; -- COMP_TAG_END ------ End COMPONENT Declaration ------------- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : adder8 port map ( a => a, b => b, c => c, ce => ce, ci => ci, clr => clr, s => s); ------ INST_TAG_END ------ End INSTANTIATION Template -----------You must compile the wrapper file test.vhd when simulating the core, test. When compiling the wrapper file, be sure to reference the XilinxCoreLib VHDL simulation library. For detailed instructions, please refer to the "Core Generator Guide". Fixed Netlist Cores The other type of Virtex-II Pro core provided by the CORE Generator is the fixed netlist core. These are preset, non-parameterized designs that are shipped with the following: * * * * A fixed EDIF implementation netlist (as opposed to one that is customized on the fly) .VEO and .VHO templates Non-parameterized .V and .VHD behavioral simulation models Schematic symbol support Examples include the fixed netlist Xilinx FFTs and most AllianceCORE products. Since the HDL behavioral models for fixed netlist cores are not parameterized, the corresponding .VEO and .VHO template files are correspondingly simple. They do not need to pass customizing parameter values to a library behavioral model. Xilinx IP Solutions and the IP Center The CORE Generator works in conjunction with the Xilinx IP Center on the world wide web to provide the latest IP and software upgrades. To make the most of this resource, Xilinx highly recommends that whenever starting a design, first do a quick search of the Xilinx IP Center (www.xilinx.com/ipcenter) to see whether a ready-made core solution is already available. A complete catalog of Xilinx cores and IP tools resides on the IP Center, including: * * * * 376 LogiCORE Products AllianceCORE Products Reference Designs XPERTS Partner Consultants www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System * Design Reuse Tools When installing the CORE Generator software, the designer gains immediate access to dozens of cores supplied by the LogiCORE Program. In addition, data sheets are available for all AllianceCORE products, and additional, separately licensed, advanced function LogiCORE products are also available. New and updated Virtex-II Pro IP for the CORE Generator can be downloaded from the IP Center and added to the CORE Generator catalog. LogiCORE Program LogiCORE products are designed, sold, licensed, and supported by Xilinx. LogiCORE products include a wide selection of generic, parameterized functions, such as muxes, adders, multipliers, and memory cores which are bundled with the Xilinx CORE Generator software at no additional cost to licensed software customers. System-level cores, such as PCI, Reed-Solomon, ADPCM, HDLC, POS-PHY, and Color Space Converters are also available as optional, separately licensed products. Probably, the most common application of the CORE Generator is to use it to quickly generate Virtex-II Pro block and distributed memories. A more detailed listing of available Virtex-II Pro LogiCORE products is available in Table 2-71 and on the Xilinx IP Center website (www.xilinx.com/ipcenter). Types of IP currently offered by the Xilinx LogiCORE program include: * * Basic Elements: logic gates, registers, multiplexers, adders, multipliers * DSP and Video Image Processing: cores ranging from small building blocks (e.g., Time Skew Buffers) to larger system-level functions (e.g., FIR Filters and FFTs) * System Logic: accumulators, adders, subtracters, complementers, multipliers, integrators, pipelined delay elements, single and dual-port distributed and block RAM, ROM, and synchronous and asynchronous FIFOs * Standard Bus Interfaces: PCI 64/66 (64-bit, 66 MHz), 64/33 (64-bit, 33 MHz), and 32/33 (32-bit, 3 3MHz) Interfaces Communications and Networking: ADPCM modules, HDLC controllers, ATM building blocks, forward error correction modules, and POS-PHY Interfaces AllianceCORE Program The AllianceCORE program is a cooperative effort between Xilinx and third-party IP developers to provide additional system-level IP cores optimized for Xilinx FPGAs. To ensure a high level of quality, AllianceCORE products are implemented and verified in a Xilinx device as part of the certification process. Xilinx develops relationships with AllianceCORE partners who can complement the Xilinx LogiCORE product offering. Where Xilinx does not offer a LogiCORE for a particular function, Xilinx partners with an AllianceCORE partner to offer that function. A large percentage of Xilinx AllianceCORE partners focus on data and telecommunication applications, as well as processor and processor peripheral designs. Together, Xilinx and the AllianceCORE partners are able to provide an extensive library of cores to accelerate the design process. AllianceCORE products include customizable cores which can be configured to exact needs, as well as fixed netlist cores targeted toward specific applications. In many cases, partners can provide cores customized to meet the specific design needs if the primary offerings do not fit the requirements. Additionally, source code versions of the cores are often available from the partners at additional cost for those who need maximum flexibility. The library of Xilinx and AllianceCORE IP cores allows designers to leverage the expertise of experienced designers who are well-versed in optimizing designs for Virtex-II Pro and other Xilinx architectures. This enables designers to obtain high performance and density in the target Virtex-II Pro device with a faster time to market. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 377 R Chapter 2: Design Considerations Reference Designs Xilinx offers two types of reference designs; application notes (XAPPs) developed by Xilinx, and reference designs developed through the Xilinx Reference Design Alliance Program. Both types are extremely valuable to customers looking for guidance when designing systems. Reference designs can often be used as starting points for implementing a broad spectrum of functions in Xilinx programmable logic. Application notes developed by Xilinx usually include supporting design files. They are supplied free of charge, without technical support or warranty. To see currently available reference designs, visit the www.xilinx.com/products/logicore/refdes.htm website. Reference designs developed through the Xilinx Reference Design Alliance Program are developed, owned, and controlled by the partners in the program. The goal of the program is to form strategic engineering and marketing partnerships with other semiconductor manufacturers and design houses so as to assist in the development of high quality, multicomponent reference designs that incorporate Xilinx devices and demonstrate how they can operate at the system level with other specialized and general purpose semiconductors. The reference designs in the Xilinx Reference Design Alliance Program are fully functional and applicable to a wide variety of digital electronic systems, including those used for networking, communications, video imaging, and DSP applications. Visit the www.xilinx.com/company/reference_design/referencepartners.htm website to see a list of designs currently available through this program. XPERTS Program Xilinx established the XPERTS Program to provide customers with access to a worldwide network of certified design consultants proficient with Xilinx Platform FPGAs, software, and IP core integration. All XPERT members are certified and have extensive expertise and experience with Xilinx technology in various vertical applications, such as communications and networking, DSP, video and image processing, system I/O interfaces, and home networking. XPERTS partners are an integral part of Xilinx strategy to provide customers with costefficient design solutions, while accelerating time to market. For more information on Xilinx XPERTS Program, visit the www.xilinx.com/company/consultants/index.htm website. Design Reuse Tools To facilitate the archiving and sharing of IP created by different individuals and workgroups within a company, Xilinx offers the IP Capture Tool. The IP Capture Tool helps to package design modules created by individual engineers in a standardized format so that they can be cataloged and distributed using the Xilinx CORE Generator. A core can take the form of synthesizable VHDL or Verilog code, or a fixed function netlist. Once it is packaged by the IP Capture Tool and installed into the CORE Generator, the "captured" core can be shared with other designers within a company through an internal network. The IP Capture Tool is supplied as a separate utility through the Xilinx IP Center. For more information, see the www.xilinx.com/ipcenter/designreuse/ipic.htm website. CORE Generator Summary The CORE Generator delivers a complete catalog of IP including behavioral models, synthesis templates, and netlists with performance guaranteed by Xilinx Smart-IP technology. It is a repository for LogiCORE products from Xilinx, AllianceCORE products from Xilinx partners, and it supports Design Reuse for internally developed IP. In addition, LogiCORE products are continuously updated to add support for new Xilinx architectures, such as Virtex-II Pro. The most current IP updates are available from the Xilinx IP Center. Utilizing the CORE Generator library of parameterizable cores, designed by Xilinx for Xilinx FPGAs, the designer can enjoy the advantages of design reuse, including faster time 378 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System to market and lower cost solutions. For more information, visit the Xilinx IP Center www.xilinx.com/ipcenter website. Virtex-II Pro IP Cores Support Table 2-71 provides a partial listing of cores available for Virtex-II Pro designs. For a complete catalog of Virtex-II Pro IP, visit the Xilinx IP Center www.xilinx.com/ipcenter website. Table 2-71: Virtex-II Pro IP Cores Support Vendor Name IP Type Memory Tests utility Xilinx LogiCORE Used to test Memory Interfaces VxWorks Integration / RTOS Adaptation Layer Xilinx LogiCORE Delivered with each peripheral with the Device Driver Board Support Package (BSP) Xilinx LogiCORE BSP for the Xilinx development board including PPC405 boot code Chip Support Package (CSP) Xilinx LogiCORE Configurable BSP - Delivered through Platform Generator OPB Arbiter Xilinx LogiCORE Device driver included PLB Arbiter Xilinx LogiCORE Device driver included PLB-OPB Bridge Xilinx LogiCORE Device driver included OPB-PLB Bridge Xilinx LogiCORE Device driver included IPIF-Slave Attachment Xilinx LogiCORE Device driver included IPIF-Master Attachment Xilinx LogiCORE Device driver included IPIF-Address Decode Xilinx LogiCORE Device driver included IPIF-Interrupt Control Xilinx LogiCORE Device driver included IPIF-Read Packet FIFOs Xilinx LogiCORE Device driver included IPIF-Write Packet FIFOs Xilinx LogiCORE Device driver included IPIF-DMA Xilinx LogiCORE Device driver included IPIF-Scatter Gather Xilinx LogiCORE Device driver included PLB External Memory Controller Xilinx LogiCORE SRAM & FLASH interface including Flash device driver OPB External Memory Controller Xilinx LogiCORE SRAM & FLASH interface including Flash device driver PLB DDR Controller Xilinx LogiCORE DDR Memory Controller OPB BRAM Controller Xilinx LogiCORE OPB BRAM Controller Function Key Features Application Examples Software-Only IP: Bus Infrastructure: OPB IPIF Modules: Memory Interfaces: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 379 R Table 2-71: Chapter 2: Design Considerations Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type Xilinx LogiCORE ZBT Memory Controller Interrupt Controller Xilinx LogiCORE Device driver included UART-16550 Xilinx LogiCORE Device driver included UART-16450 Xilinx LogiCORE Device driver included IIC Master & Slave Xilinx LogiCORE Device driver included SPI Master & Slave Xilinx LogiCORE Device driver included Ethernet 10/100 MAC Xilinx LogiCORE Device driver included ATM Utopia Level 2 Slave Xilinx LogiCORE Device driver included TimeBase/Watch Dog Timer Xilinx LogiCORE Device driver included Timer/Counter Xilinx LogiCORE Device driver included UART - Lite Xilinx LogiCORE Device driver included GPIO Xilinx LogiCORE Device driver included BUFE-based Multiplexer Slice Xilinx LogiCORE 1-256 bits wide BUFT-based Multiplexer Slice Xilinx LogiCORE 1-256 bits wide Binary Counter Xilinx LogiCORE 2-256 bits output width Binary Decoder Xilinx LogiCORE 2-256 bits output width Bit Bus Gate Xilinx LogiCORE 1-256 bits wide Bit Gate Xilinx LogiCORE 1-256 bits wide Bit Multiplexer Xilinx LogiCORE 1-256 bits wide Bus Gate Xilinx LogiCORE 1-256 bits wide Bus Multiplexer Xilinx LogiCORE IO widths up to 256 bits Comparator Xilinx LogiCORE 1-256 bits wide FD-based Parallel Register Xilinx LogiCORE 1-256 bits wide FD-based Shift Register Xilinx LogiCORE 1-64 bits wide LD-based Parallel Latch Xilinx LogiCORE 1-256 bits wide RAM-based Shift Register Xilinx LogiCORE 1-256 bits wide, 1024 words deep 3G FEC Package Xilinx LogiCORE Viterbi Decoder, Turbo Codec, Convolutional Enc 3G Wireless Infrastructure 3GPP Compliant Turbo Convolutional Decoder Xilinx LogiCORE 3GPP specs, 2 Mb/s, BER=10-6 for 1.5dB SNR 3G Wireless Infrastructure 3GPP Compliant Turbo Convolutional Encoder Xilinx LogiCORE Compliant w/ 3GPP, puncturing 3G Wireless Infrastructure SysOnChip AllianceCORE 3GPP/UMTS compliant, IMT-2000, 2Mb/s data Error correction, wireless Function OPB ZBT Controller Key Features Application Examples Peripherals: Basic Elements: Communication & Networking: 3GPP Turbo Decoder 380 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System Table 2-71: Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type 8b/10b Decoder Xilinx LogiCORE Industry std 8b/10b en/decode for serial data transmission Physical layer of Fiber Channel 8b/10b Encoder Xilinx LogiCORE Industry std 8b/10b en/decode for serial data transmission Physical layer of Fiber Channel ADPCM 1024 Channel Amphion AllianceCORE G.721, 723, 726, 726a, 727, 727a, u-law, a-law DECT, VOIP, cordless telephony ADPCM 256 Channel Amphion AllianceCORE G.721, 723, 726, 726a, 727, 727a, u-law, a-law DECT, VOIP, cordless telephony ADPCM 512 Channel Amphion AllianceCORE ADPCM 768 Channel Amphion AllianceCORE G.721, 723, 726, 726a, 727, 727a, u-law, a-law DECT, VOIP, cordless telephony ADPCM Speech Codec, 32 Channel (DO-DI-ADPCM32) Xilinx LogiCORE G.726, G.727, 32 duplex channels DECT, VOIP, Wireless local loop, DSLAM, PBX ADPCM Speech Codec, 64 Channel (DO-DI-ADPCM64) Xilinx LogiCORE G.726, G.727, 64 duplex channels DECT, VOIP, wireless local loop, DSLAM, PBX BOOST LITE Bluetooth Baseband Processor NewLogic AllianceCORE Compliant to Bluetooth v1.1, BQB qualified software for L2CAP, LHP, HC1, voice support Bluetooth applications BOOST Lite Bluetooth Baseband Processor NewLogic AllianceCORE Compliant to Bluetooth v1.1, BQB qualified software for L2CAP, LHP, HC1, voice support Bluetooth applications Xilinx LogiCORE k from 3 to 9, puncturing from 2/3 to 12/13 3G base stations, broadcast, wireless LAN, cable modem, xDSL, satellite com, uwave iCODING AllianceCORE DVB-RCS compliant, 9 Mb/s data rate, switchable code rates and frame sizes Error correction, wireless, DVB, Satellite data link Flexbus 4 Interface Core, 16-Channel (DO-DI-FLX4C16) Xilinx LogiCORE Line card: terabit routers & optical switches Flexbus 4 Interface Core, 4-Channel (DO-DI-FLX4C4) Xilinx LogiCORE Line card: terabit routers & optical switches Flexbus 4 Interface Core, 1-Channel (DO-DI-FLX4C1) Xilinx LogiCORE Line card: terabit routers & optical switches HDLC Controller Core, 32 Channels Xilinx LogiCORE 32 full duplex, CRC-16/32, 8/16-bit address insertion/deletion X.25, POS, cable modems, frame relay switches, video conferencing over ISDN HDLC Controller Core, Single Channel Xilinx LogiCORE 16/32-bit frame seq, 8/16bit addr insert/delete, flag/zerop insert/detect X.25, POS, cable modems, frame relay switches, video conf. over ISDN Interleaver/De-interleaver Xilinx LogiCORE Convolutional, width up to 256 bits, 256 branches Broadcast, wireless LAN, cable modem, xDSL, satellite com,uwave nets, digital TV Function Convolutional Encoder DVB-RCS Turbo Decoder UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Key Features www.xilinx.com 1-800-255-7778 Application Examples 381 R Table 2-71: Chapter 2: Design Considerations Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type PE-MACMII Dual Speed 10/100 Mb/s Ethernet MAC Alcatel AllianceCORE POS-PHY Level 3 Link Layer Interface Core, 48 Channel (DO-DI-POSL3LINK48A) Xilinx LogiCORE POS-PHY L3 Link Layer Interface, 16-Ch (DO-DIPOSL3LINK16) Xilinx LogiCORE Line card: terabit routers & optical switches POS-PHY L3 Link Layer Interface, 4-Ch (DO-DIPOSL3LINK4) Xilinx LogiCORE Line card: terabit routers & optical switches POS-PHY L3 Link Layer Interface, 2-Ch (DO-DIPOSL3LINK2) Xilinx LogiCORE Line card: terabit routers & optical switches POS-PHY L3 Link Layer Interface, Single Channel Xilinx LogiCORE POS-PHY L4 Multi-Channel Interface (DO-DI-POSL4MC) Xilinx LogiCORE Reed-Solomon Decoder Xilinx LogiCORE Reed-Solomon Decoder TILAB AllianceCORE Reed-Solomon Encoder Xilinx LogiCORE SDLC Controller CAST Function 802.3 compliant, Supports single & multimode fiber optic devices, M11 interfaces, RMON and Etherstate statistics Application Examples Networking, Broadband, NIC, SOHO, Home networking, storage, routers, switches, printers Std or custom coding, 3-12 bit symbol width, up to 4095 symbols Broadcast, wireless LAN, digital TV, cable modem, xDSL, satellite com, uwave nets parameterizable, RTL available Error correction, wireless, DSL Std or cust coding, 3-12 bit width, up to 4095 symbols with 256 check symb. Broadcast, wireless LAN, digital TV, cable modem, xDSL, satellite com, uwave nets AllianceCORE Like Intel 8XC152 Global Serial Channel, Serial Comm., HDLC apps, telecom Embedded systems, professional audio, video IP AllianceCORE Solution requires SPEEDAnalyzer ASIC, 2.5 Gb/s fdx wire speed; net processor (NPV) Networking, edge and access, Switches and routers SysOnChip AllianceCORE 3GPP/UMTS compliant, 2 Mb/s data rate Error correction, wireless Turbo Encoder TILAB AllianceCORE 3GPP/UMTS compliant, upto 4 interleaver laws Error correction, wireless TURBO_DEC Turbo Decoder TILAB AllianceCORE 3GPP/UMTS compliant, >2 Mb/s data rate Error correction, wireless Viterbi Decoder Xilinx LogiCORE Puncturing, serial & parallel architecture, 3G base stations, broadcast, wireless LAN, cable modem, xDSL, satellite com, uwave SPEEDROUTER Network Processor Turbo Decoder - 3GPP 382 Key Features www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System Table 2-71: Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type Xilinx LogiCORE Constraint length(k)=7, G0=171, G1=133 1024-Point Complex FFT IFFT for Virtex-II Xilinx LogiCORE 16 bit complex data, 2's comp, forward and inverse transform 16-Point Complex FFT IFFT for Virtex-II Xilinx LogiCORE 16 bit complex data, 2's comp, forward and inverse transform 256-Point Complex FFT IFFT for Virtex-II Xilinx LogiCORE 16 bit complex data, 2's comp, forward and inverse transform 32 Point Complex FFT/IFFT Xilinx LogiCORE 64-Point Complex FFT IFFT for Virtex-II Xilinx LogiCORE 16 bit complex data, 2's comp, forward and inverse transform Bit Correlator Xilinx LogiCORE 4096 taps, serial/parallel input, 4096 bits width Cascaded Integrator Comb (CIC) Xilinx LogiCORE 32 bits data width, rate change from 8 to 16384 Direct Digital Synthesizer Xilinx LogiCORE 8-65K samples, 32-bits output precision, phase dithering/offset Distributed Arithmetic FIR Filter Xilinx LogiCORE 32-bit input/coeff width, 1024 taps, 1-8 chan, polyphase, online coeff reload GVA-300 Virtex-II DSP Hardware Accelerator GV AllianceCORE LFSR, Linear Feedback Shift Register Xilinx LogiCORE 168 input widths, SRL16/register implementation Accumulator Xilinx LogiCORE 1-256s bit wide Adder Subtracter Xilinx LogiCORE 1-256s bit wide DFP2INT Floating Point to Integer Converter Digital AllianceCORE Full IEEE-754 compliance, 4 pipelines, Single precision real format support DSP, Math, Arithmetic apps DFPADD Floating Point Adder Digital AllianceCORE Full IEEE-754 compliance, 4 pipelines, Single precision real format support DSP, Math, Arithmetic apps DFPCOMP Floating Point Comparator Digital AllianceCORE Full IEEE-754 compliance, 4 pipelines, Single precision real format support DSP, Math, Arithmetic apps Function Viterbi Decoder, IEEE 802-compatible Key Features Application Examples L/MMDS, cable modem, broadcast equip, wireless LAN, xDSL, sat com, uwave nets Digital Signal Processing: 2 Virtex-II, Spartan-II FPGAs, 1 CPLD, Matlab I/F DSP prototyping Math Functions: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 383 R Table 2-71: Chapter 2: Design Considerations Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type DFPDIV Floating Point Divider Digital AllianceCORE Full IEEE-754 compliance, 15 pipelines, Single precision real format support DSP, Math, Arithmetic apps DFPMUL Floating Point Multiplier Digital AllianceCORE Full IEEE-754 compliance, 7 pipelines,32x32 mult, Single precision real format support DSP, Math, Arithmetic apps DFPSQRT Floating Point Square Root Digital AllianceCORE Full IEEE-754 compliance, 4 pipelines, Single precision real format support DSP, Math, Arithmetic apps DINT2FP Integer to Floating Point Converter Digital AllianceCORE Full IEEE-754 compliance, double word input, 2 pipelines, Single precision real output DSP, Math, Arithmetic apps Multiply Accumulator (MAC) Xilinx LogiCORE Input width up to 32 bits, 65-bit accumulator, truncation rounding Multiply Generator Xilinx LogiCORE 64-bit input data width, constant, reloadable or variable inputs, parallel/sequential implementation Pipelined Divider Xilinx LogiCORE 32-bit input data width, multiple clock per output Sine Cosine Look Up Table Xilinx LogiCORE 3-10 bit in, 4-32 bit out, distributed/block ROM Twos Complementer Xilinx LogiCORE Input width up to 256 bits Asynchronous FIFO Xilinx LogiCORE 1-256 bits, 15-65535 words, DRAM or BRAM, independent I/O clock domains Content Addressable Memory (CAM) Xilinx LogiCORE 1-512 bits, 2-10K words, SRL16 Distributed Memory Xilinx LogiCORE 1-1024 bit, 16-65536 word, RAM/ROM/SRL16, opt output regs and pipelining Dual-Port Block Memory Xilinx LogiCORE 1-256 bits, 2-13K words Single-Port Block Memory Xilinx LogiCORE 1-256 bits, 2-128K words Synchronous FIFO Xilinx LogiCORE 1-256 bits, 16-256 words, distributed/block RAM Xilinx LogiCORE Interfaces through OPB to MicroBlazeTM Networking, comm., processor applications Loarant AllianceCORE 44 opcode, 64-K word data, program, Harvard arch. Control functions, State mach, Coprocessor Function Key Features Application Examples Memories & Storage Elements: Microprocessors, Controllers & Peripherals: 10/100 Ethernet MAC AX1610 16-bit RISC Processor 384 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System Table 2-71: Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type C165X MicroController CAST AllianceCORE Microchip 16C5X PIC like Embedded systems, telecom C68000 Microprocessor CAST AllianceCORE MC68000 Compatible Embedded systems, pro audio, video CPU FPGA (Virtex-II) MicroEngine Cards NMI AllianceCORE Hitachi SH-3 CPU Embedded systems CZ80CPU Microprocessor CAST AllianceCORE Zilog Z80 compatible, 8-bit processor Embedded systems, Communications DDR SDRAM Controller Core MemecCore AllianceCORE DDR SDRAM burst length support for 2,4,8 per access, supports data 16,32, 64, 72. Digital video, embedded computing , networking DFPIC125X Fast RISC MicroController Digital AllianceCORE PIC 12c4x like, 2X faster, 12- Embedded systems, bit wide instruction set, 33 telecom, audio and video instructions DFPIC1655X Fast RISC MicroController Digital AllianceCORE S/W compatible with PIC16C55X, 14-bit instruction set, 35 instructions DFPIC165X Fast RISC MicroController Digital AllianceCORE PIC 12c4x like, 2X faster, 12- Embedded systems, bit wide instruction set, 33 telecom, audio and video instructions DI2CM I2C Bus Controller Master Digital AllianceCORE I2C-like, multi master, fast/std. modes Embedded systems DI2CM I2C Bus Controller Slave Digital AllianceCORE I2C-like, Slave Embedded DI2CSB I2C Bus Controller Slave Base Digital AllianceCORE I2C-like, Slave Embedded Systems DR8051 RISC MicroController Digital AllianceCORE 80C31 instruction set, RISC architecture 6.7X faster than standard 8051 Embedded systems, telecom, video DR8051BASE RISC MicroController Digital AllianceCORE 80C31 instruction set, high speed multiplier, RISC architecture 6.7X faster than standard 8051 Embedded systems, telecom, video DR8052EX RISC MicroController Digital AllianceCORE 80C31 instruction set, high speed mult/div ,RISC 6.7X faster than standard 8051 Embedded systems, telecom, video e8254 Programmable Interval Timer/Counter einfochips AllianceCORE Three 8-bit parallel ports, 24 programmable IO lines, 8bit bidi data bus Processor, I/O interface e8255 Peripheral Interface einfochips AllianceCORE Three 8-bit parallel ports, 24 programmable IO lines, 8bit bidi data bus Processor, I/O interface Dolphin AllianceCORE Avg 8X faster & code compatible v. legacy 8051, verification bus monitor, SFR IF, DSP focused DSP, Telecom, industrial, high speed control Xilinx LogiCORE Interfaces through OPB to MicroBlazeTM Networking, com, processor applic Function Flip805x-PS Microprocessor IIC Master and Slave UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Key Features www.xilinx.com 1-800-255-7778 Application Examples Embedded systems, telecom, audio and video 385 R Table 2-71: Chapter 2: Design Considerations Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type Key Features LavaCORE Configurable Java Processor Core Derivation AllianceCORE 32b data/address optional DES Internet appliance, industrial control LavaCORE Configurable Java Processor Core Derivation AllianceCORE 32b data/address optional DES Internet appliance, industrial control Lightfoot 32-bit Java Processor Core Digital AllianceCORE 32bit data, 24 bit address, 3 Stage pipeline, Java/C dev. tools Internet appliance, industrial control, HAVi multimedia, set top boxes MicroBlazeTM Soft RISC Processor Xilinx LogiCORE Soft RISC Processor, small footprint Networking, communications OPB Arbiter Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications OPB GPIO Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications OPB Interrupt Controller Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications OPB Memory Interface (Flash, SRAM) Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications OPB Timer/Counter Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications OPB UART (16450, 16550) Xilinx LogiCORE Interfaces through OPB to MicroBlaze Processor applications OPB UART Lite Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications OPB WDT Xilinx LogiCORE Bundled in the MicroBlaze Development Kit Processor applications Derivation AllianceCORE PC/104 & PC/104+ devlopment board Internet appliance, industrial control Xilinx LogiCORE Interfaces through OPB to MicroBlaze Networking, communications, processor applications MemecCore AllianceCORE UART and baud rate generator Serial data communication PCI32 Virtex Interface Design Kit (DO-DI-PCI32-DKT) Xilinx LogiCORE Includes PCI32 board, drive development kit, and customer education 3-day training class PCI32 Virtex Interface, IP Only (DO-DI-PCI32-IP) Xilinx LogiCORE v2.2 comp, assured PCI timing, 3.3/5-V, 0-waitstate, CPCI hot swap friendly PC add-in boards, CPCI, Embedded PCI64 & PCI32, IP Only (DO-DI-PCI-AL) Xilinx LogiCORE v2.2 comp, assured PCI timing, 3.3/5-V, 0-waitstate, CPCI hot swap friendly PC boards, CPCI, Embedded, hiperf video, gb ethernet PCI64 Virtex Interface Design Kit (DO-DI-PCI64-DKT) Xilinx LogiCORE v2.2 comp, assured PCI timing, 3.3/5-V, 0-waitstate, CPCI hot swap friendly PC boards, CPCI, Embedded, hiperf video, gb ethernet Function PF3100 PC/104-Plus Reconfigurable Module SPI XF-UART Asynchronous Communications Core Application Examples Standard Bus Interfaces: 386 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R CORE Generator System Table 2-71: Virtex-II Pro IP Cores Support (Continued) Vendor Name IP Type Key Features PCI64 Virtex Interface, IP Only (DO-DI-PCI64-IP) Xilinx LogiCORE v2.2 comp, assured PCI timing, 3.3/5-V, 0-waitstate, CPCI hot swap friendly PC boards, CPCI, Embedded, hiperf video, gb ethernet RapidIO 8-bit port LP-LVDS Phy Layer (DO-DI-RIO8-PHY) Xilinx LogiCORE RapidIO Interconnect v1.1 compliant, verified with Motorola's RapidIO bus functional model v1.4 Routers, switches, backplane, control plane, data path, embedded sys, high speed interface to memory and encryption engines, high end video MemecCore AllianceCORE Compliant with USB1.1 spec., Supports VCI bus, Performs CRC, Supports 1.5 Mb/s & 12 Mb/s Scanners, Printers, Handhelds, Mass Storage 1-D Discrete Cosine Transform Xilinx LogiCORE 2-D DCT/IDCT Forward/Inverse Discrete Cosine Transform Xilinx LogiCORE FASTJPEG_BW Decoder BARCOSILEX AllianceCORE Conforms to ISO/IEC Baseline 10918-1, GrayScale Video editing, digital camera, scanners FASTJPEG_C Decoder BARCOSILEX AllianceCORE Conforms to ISO/IEC Baseline 10918-1, color, multi-scan, Gray-Scale Video editing, digital camera, scanners Function USB 1.1 Device Controller Application Examples Video & Image Processing: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook 8-24 bits for coeff & input, 864 pts image, video phone, color laser printers www.xilinx.com 1-800-255-7778 387 R 388 Chapter 2: Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Chapter 3 Configuration Summary This chapter covers the following topics: * * * * * * * * * * Introduction Configuration Solutions Master Serial Programming Mode Slave Serial Programming Mode Master SelectMAP Programming Mode Slave SelectMAP Programming Mode JTAG/ Boundary Scan Programming Mode - Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1149.1 - Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1532 Configuration With MultiLINX Configuration Details Readback Introduction Virtex-II Pro devices are configured by loading application-specific configuration data into internal memory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be reused as general-purpose inputs and outputs after configuration is complete. Depending on the system design, several configuration modes are selectable via mode pins. The mode pins M2, M1, and M0 are dedicated pins. An additional pin, HSWAP_EN, is used in conjunction with the mode pins to select whether user I/O pins have pull-up resistors during configuration. By default, HSWAP_EN is tied High (internal pull-up resistor), which shuts off pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, the pull-up resistors are on and therefore, the user I/Os have pull-up resistors during configuration. Other dedicated pins are: * * * * CCLK - the configuration clock pin DONE - configuration status pin TDI, TDO, TMS, TCK - boundary-scan pins PROG_B - configuration reset pin UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 389 R Chapter 3: Configuration Depending on the configuration mode selected, CCLK can be an output generated by the Virtex-II Pro FPGA or an input accepting externally generated clock data. For correct operation, these pins require a VCCAUX of 2.5V to permit LVCMOS operations. All dual-function configuration pins are contained in banks 4 and 5. Bank 4 contains pins used in serial configuration modes, and banks 4 and 5 contain pins used for SelectMAP modes. A persist option is available, which can be used to force pins to retain their configuration function even after device configuration is complete. If the persist option is not selected, then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used for user I/O in normal operation. The persist option does not apply to boundary-scan related pins. The persist feature is valuable in applications that employ partial reconfiguration, dynamic reconfiguration, or readback. Configuration Modes Virtex-II Pro supports the following configuration modes: * * * * * Master-Serial Slave-Serial (default) Master SelectMAP Slave SelectMAP Boundary-Scan (IEEE 1532 and IEEE 1149) Table 3-1 shows Virtex-II Pro configuration mode pin settings. Table 3-1: Virtex-II Pro Configuration Mode Pin Settings Configuration Mode1 M2 M1 M0 CCLK Direction Data Width Serial Dout2 Master Serial 0 0 0 Out 1 Yes Slave Serial 1 1 1 In 1 Yes Master SelectMAP 0 1 1 Out 8 No Slave SelectMAP 1 1 0 In 8 No Boundary Scan 1 0 1 N/A 1 No Notes: 1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls whether or not the pullups are used. 2. Daisy chaining is possible only in modes where Serial Dout is used. For example, in SelectMAP modes, the first device does NOT support daisy chaining of downstream devices. Table 3-2 lists the total number of bits required to configure each device: Table 3-2: 390 Virtex-II Pro Bitstream Lengths Device Total Number of Configuration Bits XC2VP2 1,305,440 XC2VP4 3,006,560 XC2VP7 4,485,472 XC2VP20 8,214,624 XC2VP50 19,021,408 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Introduction Configuration Process and Flow The configuration process involves loading the configuration bitstream into the FPGA using the selected mode. There are four major phases in the configuration process: * * * * Clearing Configuration Memory Initialization Loading Configuration Data Device Startup Figure 3-1 illustrates the configuration process flow. *Note: If power-up is at room temperature, VCCO-4 > or = 1.5V is acceptable. Power Up VCCINT >1.2V VCCAUX > 1.9V VCCO (Bank 4) > 1.5V* No PROG_b = Low Yes Yes Clear Configuration Memory No INIT_ B = High? Yes Sample Mode Pins Master Serial/ Master SelectMAP CCLK Begins Load Configuration Data Frames CRC Correct? No Pull INIT_B Low Abort Startup Yes Start-Up Sequence Operational ug012_c3_01_111301 Figure 3-1: Configuration Process UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 391 R Chapter 3: Configuration Power Up The VCCINT power pins must be supplied with a 1.5V source. (Refer to the Virtex-II Data Sheet for DC characteristics.) The IOB voltage input for Bank 4 (VCCO_4) and the auxiliary voltage input (VCCAUX) are also used as a logic input to the Power-On-Reset (POR) circuitry. Even if this bank is not being used, VCCO_4 must be connected to a 1.5V or greater source. Clearing Configuration Memory In the memory clear phase, non-configuration I/O pins are 3-stated with optional pull-up resistors. The INIT_B and DONE pins are driven Low by the FPGA, and the memory is cleared. After PROG_B transitions High, memory is cleared twice and initialization can begin. The INIT_B pin transitions High when the clearing of configuration memory is complete. A logic Low on the PROG_B input resets the configuration logic and holds the FPGA in the clear configuration memory state. When PROG_B is released, the FPGA continues to hold INIT_B Low until it has completed clearing all of the configuration memory. The minimum Low pulse time for PROG_B is defined by the TPROGRAM timing parameter. There is no maximum value. The power-up timing of configuration signals is shown in Figure 3-2 and the corresponding timing characteristics are listed in Table 3-3. TPOR Vcc PROG_B TPL INIT_B TICCK CCLK OUTPUT or INPUT M0, M1, (Required) VALID ds022_020_022900 Figure 3-2: Power-Up Timing Configuration Signals Table 3-3: 392 Power-Up Timing Characteristics Description Symbol Program Latency TPL 4 s per frame max Power-on-Reset TPOR ms, max CCLK (output) Delay TICCK Program Pulse Width TPROGRAM www.xilinx.com 1-800-255-7778 Value Units s, min s, max ns, min UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Introduction Initialization For the initialization phase, the INIT_B pin is released, the mode pins are sampled, the appropriate pins become active, and the configuration process begins. It is possible to delay configuration by externally holding INIT_B Low. Delaying Configuration The INIT_B pin can also be held Low externally to delay configuration of the FPGA. The FPGA samples its mode pins on the rising edge of INIT_B. After INIT_B transitions to High, configuration can begin. No additional time-out or waiting periods are required, but configuration does not need to commence immediately after the transition of INIT_B. The configuration logic does not begin processing data until the synchronization word from the bitstream is loaded. Loading Configuration Data Once configuration begins, the target FPGA starts to receive data frames. Cyclic Redundancy Checking (CRC) is performed before and after the last data frame. CRC is also automatically checked after each block write to an internal data register (FDRI). If the CRC checks prove valid, the device start-up phase can begin. If the CRC values do not match, INIT_B is asserted Low to indicate that a CRC error has occurred, startup is aborted, and the FPGA does not become active. To reconfigure the device, the PROG_B pin should be asserted to reset the configuration logic. Recycling power also resets the FPGA for configuration. For more information on CRC calculation, see "Cyclic Redundancy Checking Algorithm" on page 440. The details of loading configuration data in each of the five modes are discussed in the following sections: * * * * * Master Serial Programming Mode, page 403 Master SelectMAP Programming Mode, page 406 Slave Serial Programming Mode, page 404 Slave SelectMAP Programming Mode, page 408 JTAG/ Boundary Scan Programming Mode, page 412 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 393 R Chapter 3: Configuration Device Startup Device startup is a transition phase from the configuration mode to normal programmed device operation. Although the order of the start-up events are user programmable via software, the default sequence of events is as follows: Upon completion of the start-up sequence, the target FPGA is operational. The Start-Up Sequencer is an 8-phase sequential state machine that counts from phase 0 to phase 7. (See Figure 3-3.) The Start-Up Sequencer performs the following tasks: * * * * Release the DONE pin. Negate GTS, activating all of the I/Os. Assert GWE, allowing all RAMs and flip-flops to change state. Assert EOS. The End-Of-Start-Up flag is always set in phase 7. This is an internal flag that is not user accessible. BitGen options control the order of the Start-Up Sequence. The default Start-Up Sequence is the bold line in Figure 3-3. The Start-Up Sequence can also be stalled at any phase until either DONE has been externally forced High, or a specified DCM or DCI has established LOCK. For details, see Appendix A, "BitGen and PROMGen Switches and Options." At the cycle selected for the DONE to be released, the sequencer always waits in that state until the DONE is externally released. However, this does not delay the GTS or GWE if they are selected to be released prior to DONE. Therefore, DONE is selected first in the sequence for default settings. Default Cycles Start-upCLK Phase 0 1 2 3 4 5 6 7 DONE GTS GWE Sync to DONE Start-upCLK Phase 0 1 2 3 4 5 6 7 DONE High DONE GTS GWE x138_01_071100 Figure 3-3: 394 Default Start-Up Sequence www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Introduction Configuration Pins Certain pins in the FPGA are designated for configuration and are listed in Table 3-4. Some pins are dedicated to the configuration function and others are dual-function pins that can be user I/O after configuration. Table 3-4: Configuration Pins Name Direction Driver Type Input/Output Active Description Dedicated Pins CCLK PROG_B DONE Input Input/Output Configuration clock. Output in Master mode. Asynchronous reset to configuration logic. Active/ Open-Drain Configuration status and start-up control. M2, M1, M0 Input Configuration mode selection. HSWAP_EN Input I/O pullups during configuration. TMS Input Boundary Scan Mode Select. TCK Input Boundary Scan Clock. TDI Input Boundary Scan Data Input. TDO Output Active Boundary Scan Data Output. Dual Function Pins DIN (D0) Input/Output Active Bidirectional Serial configuration data input/SelectMAP readback data output. D1:D7 Input/Output Active Bidirectional SelectMAP configuration data input, readback data output. CS_B Input Chip Select (SelectMAP mode only). RDWR_B Input Active Low write select, read select (SelectMAP mode only). BUSY/DOUT INIT_B Output Active Input/Output Open-Drain Serial configuration data output for serial daisy-chains (active). Delay configuration, indicate configuration error. Mixed Voltage Environments Virtex-II Pro devices have separate voltage sources. VCCINT = 1.5V powers the internal circuitry, VCCAUX = 2.5V powers the input buffers and auxiliary circuitry, and VCCO (1.5, 1.8, 2.5, or 3.3V) powers the IOB circuitry. SelectI/O is separated into eight banks of I/O groups. Each bank can be configured with one of several I/O standards. Refer to the Design Considerations section for I/O banking rules and available I/O standards. Before and during configuration, all I/O banks are set for the LVCMOS standard, which requires an output voltage (VCCO) of 2.5V for normal operation. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 395 R Chapter 3: Configuration Table 3-5: Configuration Modes and VCCO Voltages Configuration Mode Pins Used VCCO_4 VCCO_5 JTAG Dedicated Pins not a concern not a concern Serial Dedicated Pins plus DOUT, DIN, and INIT 2.5V not a concern SelectMAP Dedicated Pins plus dual-function pins 2.5V 2.5V All dedicated configuration pins are powered by VCCAUX. All dual-function configuration pins are located within banks 4 and 5. As described under Configuration Process and Flow, the VCCO_4 input voltage is used as a logic input to the power-on-reset (POR) circuitry. For JTAG configuration mode, JTAG inputs are independent of VCCO and work between 2.5V and 3.3V TTL levels. The JTAG output (TDO) is an open-drain output. It needs an external 50 -100 pull-up resistor for 100 MHz JTAG operation. For serial configuration mode, VCCO_4 pins require a 2.5V supply for output configuration pins to operate normally. In serial mode, all of the configuration pins are in bank 4. For SelectMAP configuration mode, VCCO_4 and VCCO_5 pins require a 2.5V supply for output configuration pins to operate normally. In SelectMAP mode, all of the configuration pins are in banks 4 and 5. If the Virtex-II Pro device is being configured in serial or SelectMAP mode, and banks 4 and 5 are being configured for an I/O standard that requires a VCCO other than 2.5V, then VCCO_4 and VCCO_5 (SelectMAP only) must be switched from 2.5V and used during configuration at the same voltage required after configuration. If readback is performed using SelectMAP mode after configuration, then VCCO_4 and VCCO_5 require a 2.5V supply after configuration, as well. Configuration Solutions Several configuration solutions are available to support Virtex-II Pro devices, each targeted to specific application requirements. Guidance and support (application notes, reference designs, and so forth) is also available for designers looking to develop and implement their own configuration solution for Virtex FPGAs. System Advanced Configuration Environment (System ACETM) Series The System ACE series of configuration solutions offers a system-level configuration manager for designers using multiple FPGAs or FPGAs requiring multiple bitstreams. This solution combines standard industry Flash storage with Xilinx-designed configuration control. Features common to the entire System ACE family include: * * * * * * 396 Support for multiple bitstreams Built-in support for embedded processors in FPGAs Support for reconfiguring, updating, or debugging systems over a network Built-in system interface Scalability (density) and re-useability (across many designs) Centralization of configuration control for reduced board space and simpler debugging www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Solutions * Use of excess storage capacity for non-configuration, system storage System ACE CF System ACE CF (CompactFlashTM) solution combines a standard CompactFlash Association (CFA) Type-I or Type-II memory module (CompactFlash or 1" disk drive) with a Xilinx-designed ACE ControllerTM configuration control chip. See Figure 3-4. [Microprocessor] 8/16-bit Bus ACE CompactFlash ATA Bus Configuration 1 TDO TCK TMS ACE TDI Controller INIT_B PROG_B Configuration 2 Configuration 3 Virtex-II Pro Virtex-II Pro TDO TCK TMS TDI TDO TCK TMS TDI INIT_B PROG_B INIT_B PROG_B JTAG Test Port UG012_C3_041_121201 Figure 3-4: System ACE CompactFlash and Controller The CompactFlash card stores an unlimited number of bitstreams and ranges in density from 128 Mb to 3 Gb. This card is capable of storing one large bitstream or several smaller bitstreams. If several bitstreams are used, the system can be set up so that individual bitstreams are callable as needed, allowing for dynamic reconfiguration of the Virtex-II Pro device and other Xilinx FPGAs in the JTAG chain. The ACE Controller drives bits through the FPGA JTAG chain and has three other ports: * * * A port for interfacing with a microprocessor, a network, or a MultiLINX cable A port for interfacing with the CompactFlash card A port that provides access to the FPGA JTAG chain for FPGA testing or configuration via automatic test equipment or via desktop or third-party programmers For further information on any System ACE product, visit the www.xilinx.com/systemace website. System ACE Multi-Package Module (MPM) System ACE MPM is a multi-package module consisting of a packaged standard Flash from AMD, a packaged FPGA, and a packaged configuration PROM, all in a 388-pin BGA package. The Flash stores configuration and other data, while the FPGA acts as an advanced configuration controller and is configured by the PROM. This solution provides high density and high-speed configuration capability in a single package, helping to simplify the design and manufacturing process. It is available in 16 Mb, 32 Mb, and 64 Mb densities. System ACE Soft Controller (SC) System ACE SC is a downloadable version of the configuration controller found in System ACE MPM; versions are provided that support various standard Flash interfaces. System ACE SC provides all of the features of System MPM without the Single Package. It allows UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 397 R Chapter 3: Configuration designers to use the Flash memory already in their system to store configuration data. The System ACE SC controller is available free of charge in the form of a PROM file that can be downloaded from the System ACE website. This pre-engineered solution is implemented by connecting up to four Flash chips on a board to an FPGA that will be used as a configuration controller and then downloading the controller file into a PROM. Figure 3-5 describes the controller for both System ACE MPM and System ACE SC. Up to 4 FPGAs Boundary Scan JTAG Decompressor I/F Configuration Formatter State SelectMAP Machine Flash Flash FPGA Farm SlaveSerial I/F System ACE MPM/SC Controller 1, 2, 4, or 8 Chains of FPGAs AMD Flash TSOP48 XCV50E CS144 Controller XC18V01 Controller Bitstream BG388 Multi-Package Module UG002_C3_031_062901 Figure 3-5: System ACE MPM/SC Controller System ACE MPM and System ACE SC have these unique features: * * * * * 398 High speed configuration up to 154 Mb/s Support for both SelectMAP (8-bit) (see Figure 3-6) and Slave Serial (1-bit) (see Figure 3-7) configuration Configuration of multiple FPGAs in parallel Bitstream compression for increased storage capability Storage of up to 8 different bitstreams www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Solutions VCC 4.7k 330 VCC MPM Virtex-II Pro Virtex-II Pro 4.7k BUSY CFG_DATA[7:0] CFG_MODE[2:0] CFG_CCLK CFG_INIT CFG_DONE CFG_PROG CFG_WRITE CFG_CS[0] CFG_CS[1] CFG_CS[2] CFG_CS[3] BUSY D[7:0] M[2:0] CCLK /INIT_B /DONE /PROG_B /RDWR_B /CS BUSY D[7:0] M[2:0] CCLK /INIT_B /DONE /PROG_B /RDWR_B /CS To SelectMAP FPGAs UG012_C3_033_121201 Figure 3-6: VCC 4.7k VCC 330 VCC System ACE MPM SelectMAP (8-bit) Configuration Virtex-II Pro Virtex-II Pro D0 DOUT M2 M1 M0 CCLK /INIT_B /DONE /PROG_B D0 M2 M1 M0 DOUT CCLK /INIT_B /DONE /PROG_B 4.7k CFG_DATA[0-7] CFG_MODE[2] CFG_MODE[1] CFG_MODE[0] CFG_CCLK CFG_INIT CFG_DONE CFG_PROG CFG_DATA[0] To Cascaded FPGAs CFG_DATA[1-7] To Additional SlaveSerial FPGA Chains Figure 3-7: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook UG012_C3_032_121201 Slave Serial (1-bit) Configuration www.xilinx.com 1-800-255-7778 399 R Chapter 3: Configuration Configuration PROMs Using XC18V00 PROMs The XC18V00 family of Flash in-system programmable (ISP) configuration PROMs offers the flexibility of re-programmability and multiple package offerings, combined with both serial and SelectMAP FPGA configurability. This family is JTAG programmable and ranges in density from 256 Kb to 4 Mb; these PROMs can also be cascaded to support larger bitstreams. The 18V00 family offers data throughput rates of up to 264 Mb/s. It is also capable of triggering FPGA reconfiguration via a JTAG command. The parts can be JTAG programmed via cable, HW-130, or standard third party programmers. The XC18V00 PROMs are available in SO20, PC20, VQ44, and PC44 packages. Refer to Appendix B, XC18V00 Series PROMs for the latest version of the XC18V00 PROMs data sheet and package diagrams for the entire PROM family. See Table 3-8 to determine which PROMs go with which Virtex-II Pro FPGAs. Using XC17V00 PROMs The XC17V00 family of one-time programmable (OTP) PROMs provides a proven, lowcost, compact, and pre-engineered configuration solution. Ranging from 1 Mb to 16 Mb, this family is also the PROM density leader; it can also be daisy-chained to support larger bitstreams. This family supports serial configuration of Virtex-II Pro FPGAs; in addition, the XC17V08 and XC17V16 support SelectMAP configuration modes. The XC17V00 family can be used for stabilized designs that are in a high-volume production flow and/or for designs requiring a low-cost solution. XC17V00 PROMs can be programmed either by using the HW-130 or by using a variety of third-party programmers. The XC17V00 PROMs are available in VO8, SO20, PC20, VQ44, and PC44 packages. Data sheets for PROMs are available at www.xilinx.com. See Table 3-8 to determine which PROMs go with which Virtex-II Pro FPGAs and see Appendix B, XC18V00 Series PROMs for package diagrams. Flash PROMs With a CPLD Configuration Controller Some designers prefer to leverage existing Flash memory in their system to store the configuration bitstreams. A small CPLD-based configuration controller can provide the mechanism to access the bitstreams in the FLASH and deliver them quickly to Virtex-II Pro devices. The following application notes describe the details for a serial or SelectMAP configuration architecture using FLASH memories and CPLDs: * 400 XAPP079: Configuring Xilinx FPGAs Using an XC9500 CPLD and Parallel PROM (www.xilinx.com/apps/xappsumm.htm#xapp079) describes an architecture that configures a chain of Virtex-II Pro devices using Master-Serial mode. See Figure 3-8 for an example of FPGA configuration using a CPLD and a parallel PROM. www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Solutions EPROM VCC FPGA (Master) FPGA (Slave) INIT_B INIT_B CPLD ADDRESS[18:0] INIT_B ADDRESS[18:0] DATAOUT[7:0] DATAIN /CE DOUT DIN DOUT CLKIN CCLK CCLK DONE DONE PROG_B PROG_B DIN /ROM_CS LDC_DONE /OE VCC VCC Control Signal X079_05_111300 Figure 3-8: Configuring Virtex-II Pro Devices Using a CPLD and Parallel PROM * XAPP137: Configuring Virtex FPGAs From Parallel EPROMs With a CPLD (www.xilinx.com/apps/xappsumm.htm#xapp137) describes an architecture that configures one or more Virtex-II Pro devices using the Slave SelectMAP mode. See Figure 3-9 for an example of FPGA configuration using a CPLD and a parallel EPROM. VPU D[0:7] EPROM or FLASH D[0:7] D[0:7] DONE DONE INIT INIT BUSY BUSY Virtex-II Pro Virtex-II Pro CPLD (1M X 8) DONE0 CS0 DONE1 INIT PROGRAM A[0:19] A[0:19] OE/CE OE/CE CS CE1 WRITE BUSY CS CCLK WRITE WRITE PROGRAM PROGRAM CCLK CCLK M2 M1 NC NC M0 M2 M1 NC NC M0 VPU Control Signal Oscillator UG012_C3_005_121201 Figure 3-9: Configuring Virtex-II Pro Devices from Parallel EPROMs UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 401 R Chapter 3: Configuration Embedded Solutions Using an Embedded Microcontroller XAPP058: Xilinx In-System Programming Using an Embedded Microcontroller (www.xilinx.com/apps/xappsumm.htm#xapp058) describes a compact and robust process that (re)configures Virtex-II Pro devices directly from a microprocessor through the JTAG test port of the Virtex-II Pro device. The process additionally supports (re)configuration of XC18V00 ISP PROMs and CPLDs that reside on the JTAG scan chain. Portable, reference Ccode is provided with the application note for rapid implementation. Using IEEE Standard 1532 Systems that implement an IEEE Standard 1532 player are able to configure Virtex-II Pro devices and any other 1532-compliant devices using the device BSDL file and 1532 data file. Using MultiLINX or Other Cables During the development or prototype design stage, designers can program their Virtex-II Pro devices directly in system via the Xilinx Parallel Cable IV or MultiLINX programming cables using the Xilinx JTAG Programmer software or ChipScope Pro software. The operating system (see Table 3-6) and configuration mode (see Table 3-7) determine the appropriate cable selection. Table 3-6: Cable Xilinx Cable Operating System Support Connection Windows 98 Windows NT Windows 2000 Solaris HP-UX Parallel Cable IV Parallel Port Supported Supported Supported N/A N/A MultiLINX USB Supported N/A Supported N/A N/A MultiLINX RS-232 Supported Supported Supported Supported Supported Table 3-7: Xilinx Cable Configuration Mode Support Cable JTAG Slave Serial Slave SelectMAP Parallel Cable IV Supported Supported N/A MultiLINX Supported Supported Supported SelectMAP is the fastest cable configuration mode. JTAG and serial modes provide roughly equivalent configuration speeds but are slower than SelectMAP. 402 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Master Serial Programming Mode PROM Selection Guide Use Table 3-8 to determine which PROMs go with which Virtex-II Pro FPGAs. Table 3-8: Using Virtex-II Pro Devices With PROMs Virtex-II Pro Device Bitstream Length (bits) PROM Family PROM Package 18Vxx 17Vxx V08 SO20 PC20 PC44 VQ44 XCV2VP2 1,305,504 18V02 17V01 x(1) x(1) x(1) x(2) x(2) XCV2VP4 3,006,624 18V04 17V04 x x x XCV2VP7 4,485,536 18V04 + 18V512 17V04 +17V01 x x x XCV2VP20 8,214,688 2 of 18V04 2, 17V04 x(1) x x XCV2VP50 19,021,472 5 of 18V04 5, 17V04 x(1) x x x(1) x Notes: 1. 2. 17Vxx only 18Vxx only Master Serial Programming Mode In serial configuration mode, the FPGA is configured by loading one bit per CCLK cycle. In Master Serial mode, the FPGA drives the CCLK pin. In Slave Serial mode, the FPGAs CCLK pin is driven by an external source. In both serial configuration modes, the MSB of each data byte is always written to the DIN pin first. The Master Serial mode is designed so the FPGA can be configured from a Serial PROM, Figure 3-10. The speed of the CCLK is selectable by BitGen options, see Appendix A, "BitGen and PROMGen Switches and Options." Be sure to select a CCLK speed supported by the PROM. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 403 R Chapter 3: Configuration Figure 3-10 shows a Master Serial FPGA configuring from a PROM. M0 PROM M1 M2 DATA DIN CLK DOUT CCLK CE Virtex-II Pro Master Serial RESET/OE (Low Reset Option Used) Optional Pull-up on DONE(1) PROG_B DONE INIT_B PROG_B UG012_C3_011_121201 Figure 3-10: Master Serial Mode Circuit Diagram Notes: 1. If the Virtex-II Pro device has not selected the DriveDONE option, then an external pull-up resistor of 330 should be added to the DONE pin. This pull-up resistor is not needed if DriveDONE = Yes. PROGRAM INIT Master CLK Begins Here(1) CCLK DIN BIT 0 DOUT BIT 1 BIT n BIT n+1 BIT n-64 BIT n-63 x138_04_022400 Figure 3-11: Master Serial Configuration Cloaking Sequence Notes: 1. For Master configurations, the CCLK does not transition until after initialization as indicated by the arrow. Slave Serial Programming Mode In serial configuration mode, the FPGA is configured by loading one bit per CCLK cycle. In Slave Serial mode, the FPGAs CCLK pin is driven by an external source. In both serial configuration modes, the MSB of each data byte is always written to the DIN pin first. The Slave Serial configuration mode allows for FPGAs to be configured from other logic devices, such as microprocessors, or in a daisy-chain fashion. Figure 3-12 shows a Master Serial FPGA configuring from a PROM with a Slave Serial FPGA in a daisy-chain with the Master. 404 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Slave Serial Programming Mode Daisy-Chain Configuration Virtex-II Pro FPGAs can be used in a daisy-chain configuration only with XC4000X, SpartanXL, Spartan-II or other Virtex FPGAs. There are no restrictions on the order of the chain. However, if a Virtex-II Pro FPGA is placed as the Master and a non-Virtex-II Pro FPGA is placed as a slave, select a configuration CCLK speed supported by all devices in the chain. The separate bitstreams for the FPGAs in a daisy-chain are required to be combined into a single PROM file, by using either the PROM File Formatter or the PROMGen utility (see Appendix A, "BitGen and PROMGen Switches and Options"). Separate PROM files can not be simply concatenated together to form a daisy-chain bitstream. M0 PROM M1 M0 M2 DATA CLK CE RESET/OE (Low Reset Option Used) DIN DOUT DIN CCLK DOUT CCLK Virtex-II Pro Master Serial PROG DONE M1 M2 Note (1) XC4000X, Spartan, Virtex Slave Optional Pull-up on DONE(1) PROG INIT DONE INIT PROGRAM UG012_C3_003_121201 Figure 3-12: Master/Slave Serial Mode Circuit Diagram Notes: 1. If none of the devices have been selected to DriveDONE, then an external pull-up resistor of 330 should be added to the common DONE line. This pull-up resistor is not needed if DriveDONE = Yes. If used, DriveDONE should be selected only for the last device in the configuration chain. The first device in the chain is the first to be configured. No data is passed onto the DOUT pin until all the data frames, start-up command, and CRC check have been loaded. CRC checks only include the data for the current device, not for any others in the chain. After finishing the first stream, data for the next device is loaded. The data for the downstream device appears on DOUT typically about 80 CCLK cycles after being loaded into DIN. This is due to internal packet processing. Each daisy-chained bitstream carries its own synchronization word. Nothing of the first bitstream is passed to the next device in the chain other than the daisy-chained configuration data. The DONE_cycle must be set before GTS, or during the same cycle to guarantee each Virtex-II Pro device to move to the operation state when all the DONE pins have been released. When daisy-chaining multiple devices, either set the last device in the chain to DriveDONE, or add external pull-up resistors to counteract the combined capacitive loading on DONE. If non-Virtex devices are included in the daisy-chain, it is important to UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 405 R Chapter 3: Configuration set their bitstreams to SyncToDONE with BitGen options. For more information on Virtex BitGen options, see Appendix A, "BitGen and PROMGen Switches and Options.". PROG_B INIT_B CCLK DIN BIT 0 BIT 1 BIT n BIT n+1 DOUT BIT n-64 BIT n-63 ug002_c3_028_112900 Figure 3-13: Serial Configuration Clocking Sequence Notes: 1. For Slave configurations, a free running CCLK can be used, as shown in Figure 3-13. . Table 3-9: Master/Slave Serial Mode Programming Switching Description Symbol Values Units TDCC/TCCD 5.0/0.0 ns, min TDSCK/TSCKD 5.0/0.0 ns, min DOUT TCCO 12.0 ns, max High time TCCH 5.0 ns, min Low time TCCL 5.0 ns, min FCC_SERIAL 66 MHz, max DIN setup/hold, slave mode DIN setup/hold, master mode CCLK Maximum Frequency Frequency Tolerance, master mode with respect to nominal +45% -30% Master SelectMAP Programming Mode The SelectMAP mode provides an 8-bit bidirectional data bus interface to the Virtex-II Pro configuration logic that can be used for both configuration and readback. Virtex-II Pro devices can not be serially daisy-chained when the SelectMAP interface is used. However, they can be connected in a parallel-chain as shown in Figure 3-16. The DATA pins (D0:D7), CCLK, RDWR_B, BUSY, PROG_B, DONE, and INIT_B can be connected in common between all of the devices. CS_B inputs should be kept separate so each device can be accessed individually. If all devices are to be configured with the same bitstream, readback 406 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Master SelectMAP Programming Mode is not being used, and CCLK is less than FCC_SelectMAP, the CS_B pins can be connected to a common line so the devices are configured simultaneously. Virtex-II SelectMAP Master 18V00 PROM DATA[0:7] D[0:7] CCLK CCLK CF PROG CE DONE RESET/OE INIT_B RDWR_B CS_B ug002_13_031301 Figure 3-14: Virtex-II Pro Device Interfaced With an 18V00 PROM Notes: 1. If none of the Virtex-II Pro devices have been selected to DriveDONE, add an external 330 pull-up resistor to the common DONE line. This pull-up resistor is not needed if DriveDONE is selected. If used, DriveDONE should be selected only for the last device in the configuration chain. The following pins are involved in Master SelectMAP configuration mode: DATA Pins (D[0:7]) The D0 through D7 pins function as a bidirectional data bus in the SelectMAP mode. Configuration data is written to the bus, and readback data is read from the bus. The bus direction is controlled by the RDWR_B signal. <Link>See "Configuration Details" on page 431. The D0 pin is considered the MSB of each byte. RDWR_B When asserted Low, the RDWR_B signal indicates that data is being written to the data bus. When High, the RDWR_B signal indicates that data is being read from the data bus. CS_B The Chip Select input (CS_B) enables the SelectMAP data bus. To write or read data onto or from the bus, the CS_B signal must be asserted Low. When CS_B is High, Virtex-II Pro devices do not drive onto or read from the bus. CCLK The CCLK pin is a clock output in the Master SelectMAP interface. It synchronizes all loading and reading of the data bus for configuration and readback. The CCLK pin is driven by the FPGA. Data Loading To load data in the Master SelectMAP mode, a data byte is loaded on every rising CCLK edge as shown in Figure 3-15. If the CCLK frequency is less than FCC_SelectMAP, this can be done without handshaking. For frequencies above FCC_SelectMAP, the BUSY signal must be monitored. If BUSY is High, the current byte must be reloaded when BUSY is Low. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 407 R Chapter 3: Configuration The first byte can be loaded on the first rising CCLK edge that INIT_B is High, and when both CS_B and RDWR_B are asserted Low. CS_B and RDWR_B can be asserted anytime before or after INIT_B has gone High. However, the SelectMAP interface is not active until after INIT_B has gone High. The order of CS_B and RDWR_B does not matter, but RDWR_B must be asserted throughout configuration. If RDWR_B is de-asserted before all data has been loaded, the FPGA aborts the operation. To complete configuration, the FPGA must be reset by PROG_B and reconfigured with the entire stream. For applications that need to de-assert RDWR_B between bytes, see "Controlled CCLK" on page 411. PROGRAM INIT CCLK CS WRITE DATA[0:7] Byte 0 BUSY Byte 1 Byte n Byte n Byte n+1 BUSY Device Ready Byte 0 Loaded Byte n Ignored Byte n Loaded x138_06_022400 Figure 3-15: Data Loading in SelectMAP Slave SelectMAP Programming Mode The SelectMAP mode provides an 8-bit bidirectional data bus interface to the Virtex-II Pro configuration logic that can be used for both configuration and readback. Virtex-II Pro devices can not be serially daisy-chained when the SelectMAP interface is used. However, they can be connected in a parallel-chain as shown in Figure 3-16. The DATA pins (D0:D7), CCLK, RDWR_B, BUSY, PROG_B, DONE, and INIT_B can be connected in common between all of the devices. CS_B inputs should be kept separate so each device can be accessed individually. If all devices are to be configured with the same bitstream, readback is not being used, and CCLK is less than FCC_SelectMAP, the CS_B pins can be connected to a common line so the devices are configured simultaneously. 408 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Slave SelectMAP Programming Mode Although Figure 3-16 does not show a control module for the SelectMAP interface, the SelectMAP interface is typically driven by a processor, micro controller, or some other logic device such as an FPGA or a CPLD. DATA[0:7] CCLK RDWR_B BUSY VCC VCC M1 M2 M1 M0 Virtex-II Pro Slave SelectMAP Virtex-II Pro Slave SelectMAP D[0:7] D[0:7] CCLK CCLK RDWR_B RDWR_B BUSY CS_B(0) Optional Pull-up on DONE(1) M2 M0 BUSY CS_B(1) CS_B PROG_B DONE CS_B PROG_B INIT_B DONE INIT_B DONE INIT_B PROG_B UG012_C3_005a_121201 Figure 3-16: Slave SelectMAP Mode Circuit Diagram Notes: 1. If none of the Virtex-II Pro devices have been selected to DriveDONE, add an external 330 pull-up resistor to the common DONE line. This pull-up resistor is not needed if DriveDONE = Yes. If used, DriveDONE should be selected only for the last device in the configuration chain. The following pins are involved in Slave SelectMAP configuration mode: DATA Pins (D[0:7]) The D0 through D7 pins function as a bidirectional data bus in the SelectMAP mode. Configuration data is written to the bus, and readback data is read from the bus. The bus direction is controlled by the RDWR_B signal. <Link>See "Configuration Details" on page 431.. The D0 pin is considered the MSB of each byte. RDWR_B When asserted Low, the RDWR_B signal indicates that data is being written to the data bus. When asserted High, the RDWR_B signal indicates that data is being read from the data bus. CS_B The Chip Select input (CS_B) enables the SelectMAP data bus. To write or read data onto or from the bus, the CS_B signal must be asserted Low. When CS_B is High, Virtex-II Pro devices do not drive onto or read from the bus. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 409 R Chapter 3: Configuration BUSY When CS_B is asserted, the BUSY output indicates when the FPGA can accept another byte. If BUSY is Low, the FPGA reads the data bus on the next rising CCLK edge where both CS_B and RDWR_B are asserted Low. If BUSY is High, the current byte is ignored and must be reloaded on the next rising CCLK edge when BUSY is Low. When CS_B is not asserted, BUSY is 3-stated. BUSY is only necessary for CCLK frequencies above FCC_SelectMAP. For frequencies at or below FCC_SelectMAP, BUSY is ignored, see "Data Loading" on page 407. For parallel chains, as shown in Figure 3-16, where the same bitstream is to be loaded into multiple devices simultaneously, BUSY should not be used. Thus, the maximum CCLK frequency for such an application must be less than FCC_SelectMAP. CCLK Unlike the Master SelectMAP mode of configuration, the CCLK pin is an input in the Slave SelectMAP mode interface. The CCLK signal synchronizes all loading and reading of the data bus for configuration and readback. Additionally, the CCLK drives internal configuration circuitry. The CCLK can be driven either by a free running oscillator or an externally-generated signal. Several scenarios exist when configuring the FPGA in SelectMAP mode, depending on the source of CCLK. Free-Running CCLK A free-running oscillator can be used to drive Virtex-II Pro CCLK pins. For applications that can provide a continuous stream of configuration data, refer to the timing diagram discussed in Data Loading, page 407. For applications that cannot provide a continuous data stream, missing the clock edges, refer to the timing diagram discussed in NonContiguous Data Strobe, page 411. An alternative to a free-running CCLK is discussed in Controlled CCLK, page 411. Express-Style Loading In express-style loading, a data byte is loaded on every rising CCLK edge as shown in Figure 3-17. If the CCLK frequency is less than FCC_SelectMAP, this can be done without handshaking. For frequencies above FCC_SelectMAP, the BUSY signal must be monitored. If BUSY is High, the current byte must be reloaded when BUSY is Low. The first byte can be loaded on the first rising CCLK edge that INIT_B is High, and when both CS_B and RDWR_B are asserted Low. CS_B and RDWR_B can be asserted anytime before or after INIT_B has gone High. However, the SelectMAP interface is not active until after INIT_B has gone High. The order of CS_B and RDWR_B does not matter, but RDWR_B must be asserted throughout configuration. If RDWR_B is de-asserted before all data has been loaded, the FPGA aborts the operation. To complete configuration, the FPGA must be reset by PROG_B and reconfigured with the entire stream. For applications that need to de-assert RDWR_B between bytes, see "Controlled CCLK" on page 411. 410 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Slave SelectMAP Programming Mode PROGRAM INIT CCLK CS WRITE DATA[0:7] Byte 0 Byte 1 Byte n BUSY Byte n Byte n+1 BUSY Device Ready Byte 0 Loaded Byte n Ignored Byte n Loaded x138_06_022400 Figure 3-17: "Express Style" Continuous Data Loading in SelectMAP PROGRAM INIT CCLK CS WRITE DATA[0:7] Byte 0 BUSY Byte 1 High-Z Byte 0 Loaded CCLK and WRITE Ignored Byte n High-Z Byte 1 Loaded High-Z Byte n Loaded X138_07_112999 Figure 3-18: Separating Data Loads by Multiple CCLK Cycles Using CS_B Non-Contiguous Data Strobe In applications where multiple clock cycles might be required to access the configuration data before each byte can be loaded into the SelectMAP interface, data might not be ready for each consecutive CCLK edge. In such a case, the CS_B signal can be de-asserted until the next data byte is valid on the DATA[0:7] pins. This is demonstrated in Figure 3-18. While CS_B is High, the SelectMAP interface does not expect any data and ignores all CCLK transitions. However, RDWR_B must continue to be asserted while CS_B is asserted. If RDWR_B is High during a positive CCLK transition while CS_B is asserted, the FPGA aborts the operation. For applications that need to de-assert the RDWR_B signal without de-asserting CS_B, see "Controlled CCLK". Controlled CCLK Some applications require that RDWR_B be de-asserted between the loading of configuration data bytes asynchronously from the CS_B. Typically, this would be due to the RDWR_B signal being a common connection to other devices on the board, such as UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 411 R Chapter 3: Configuration memory storage elements. In such a case, driving CCLK as a controlled signal instead of a free-running oscillator makes this type of operation possible. In Figure 3-19, the CCLK, CS_B, and RDWR_B are asserted Low while a data byte becomes active. Once the CCLK has gone High, the data is loaded. RDWR_B can be de-asserted and re-asserted as many times as necessary, just as long as it is Low before the next rising CCLK edge. CCLK CS WRITE DATA[0:7] Byte 0 Byte 1 Byte n X138_08_120299 Figure 3-19: Controlling CCLK for RDWR_B De-Assertion Table 3-10: SelectMAP Write Timing Characteristics Description CCLK Symbol Value Units D0-7 Setup/Hold TSMDCC/TSMCCD 5.0/0.0 ns, min CS_B Setup/Hold TSMCSCC/TSMCCCS 7.0/0.0 ns, min RDWR_B Setup/Hold TSMCCW/TSMWCC 7.0/0.0 ns, min TSMCKBY 12.0 ns, max FCC_SelectMAP 66 MHz, max FCCNH 66 MHz, max BUSY Propagation Delay Maximum Frequency Maximum Frequency with no handshake JTAG/ Boundary Scan Programming Mode Introduction Virtex-II Pro devices support the new IEEE 1532 standard for In-System Configuration (ISC), based on the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and BoundaryScan Architecture is commonly referred to as JTAG. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This standard provides a means to assure the integrity of individual components and the interconnections between them at the board level. With increasingly dense multilayer PC boards, and more sophisticated surface mounting techniques, boundary-scan testing is becoming widely used as an important debugging standard. Devices containing boundary-scan logic can send data out on I/O pins in order to test connections between devices at the board level. The circuitry can also be used to send signals internally to test the device specific behavior. These tests are commonly used to detect opens and shorts at both the board and device level. In addition to testing, boundary-scan offers the flexibility for a device to have its own set of user-defined instructions. The added common vendor specific instructions, such as configure and verify, have increased the popularity of boundary-scan testing and functionality. 412 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1149.1 The Virtex-II Pro family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the instruction register, the instruction decoder, the boundary-scan register, and the bypass register. The Virtex-II Pro family also supports some optional instructions; the 32-bit identification register, and a configuration register in full compliance with the standard. Outlined in the following sections are the details of the JTAG architecture for Virtex-II Pro devices. Test Access Port The Virtex-II Pro TAP contains four mandatory dedicated pins as specified by the protocol (Table 3-11). Table 3-11: Virtex-II Pro TAP Controller Pins Pin Description TDI Test Data In TDO Test Data Out TMS Test Mode Select TCK Test Clock There are three input pins and one output pin to control the 1149.1 boundary-scan TAP controller. There are optional control pins, such as TRST (Test Reset) and enable pins, which might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors, because they might need to be driven. The TAP controller is a 16-state state machine shown in Figure 3-20. The four mandatory TAP pins are outlined below. * TMS - This pin determines the sequence of states through the TAP controller on the rising edge of TCK. TMS has an internal resistive pull-up to provide a logic High if the pin is not driven. * TCK - This pin is the JTAG test clock. It sequences the TAP controller and the JTAG registers in the Virtex-II Pro devices. * TDI - This pin is the serial input to all JTAG instruction and data registers. The state of the TAP controller and the current instruction held in the instruction register determine which register is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to provide a logic High to the system if the pin is not driven. TDI is applied into the JTAG registers on the rising edge of TCK. * TDO - This pin is the serial output for all JTAG instruction and data registers. The state of the TAP controller and the current instruction held in the instruction register determine which register (instruction or data) feeds TDO for a specific operation. TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. This pin is 3-stated at all other times. Notes: As specified by the IEEE Standard, the TMS and TDI pins all have internal pull-up resistors. These internal pull-up resistors of 50-150 k are active, regardless of the mode selected. For JTAG configuration mode, JTAG inputs are independent of VCCO and work between 2.5V and 3.3V TTL levels. The JTAG output (TDO) is an open-drain output. It needs an external 50 -100 pull-up resistor for 100 MHz JTAG operation. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 413 R Chapter 3: Configuration TAP Controller Figure 3-20 diagrams a 16-state finite state machine. The four TAP pins control how data is scanned into the various registers. The state of the TMS pin at the rising edge of TCK determines the sequence of state transitions. There are two main sequences, one for shifting data into the data register and the other for shifting an instruction into the instruction register. 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT-DR-SCAN 1 1 0 SELECT-IR-SCAN 1 CAPTURE-DR 0 CAPTURE-IR 0 0 0 SHIFT-DR 1 EXIT1-DR 1 1 EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 0 UPDATE-IR 1 0 NOTE: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. x139_01_112399 Figure 3-20: State Diagram for the TAP Controller 414 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Boundary-Scan Instruction Set To determine the operation to be invoked, an instruction is loaded into the Instruction Register (IR). The length of the IR is device size specific. The IR is 10 bits wide on the XC2VP2, XC2VP4, and XC2VP7; 14 bits wide on the XC2VP20; and 22 bits wide on the XC2VP50. The bottom six bits of the instruction codes are the same for all devices sizes, to support the new IEEE Standard 1532 for In-System Configurable (ISC) devices. The additional IR bits for each instruction are 1's. Table 3-12 lists the available instructions for Virtex-II Pro devices. Table 3-12: Virtex-II Pro Boundary Scan Instructions for XC2VP2 through XC2VP7 Boundary Scan Command Binary Code (9:0) EXTEST 1111000000 Enables boundary-scan EXTEST operation SAMPLE 1111000001 Enables boundary-scan SAMPLE operation USER1 1111000010 Access user-defined register 1 USER2 1111000011 Access user-defined register 2 CFG_OUT 1111000100 Access the configuration bus for readback CFG_IN 1111000101 Access the configuration bus for configuration INTEST 1111000111 Enables boundary-scan INTEST operation USERCODE 1111001000 Enables shifting out user code IDCODE 1111001001 Enables shifting out of ID code HIGHZ 1111001010 3-states output pins while enabling the bypass register JSTART 1111001100 Clocks the start-up sequence when StartClk is TCK JSHUTDOWN 1111001101 Clocks the shutdown sequence BYPASS 1111111111 Enables BYPASS JPROG_B 1111001011 Equivalent to and has the same affect as PROG_B RESERVED All other codes Description Xilinx reserved instructions The mandatory IEEE 1149.1 commands are supported in Virtex-II Pro devices, as well as several Xilinx vendor-specific commands. Virtex-II Pro devices have a powerful command set. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports two internal user-defined registers (USER1 and USER2) and configuration/readback of the device. The Virtex-II Pro boundary-scan operations are independent of mode selection. The boundary-scan mode in Virtex-II Pro devices overrides other mode selections. For this reason, boundary-scan instructions using the boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) must not be performed during configuration. All instructions except USER1 and USER2 are available before a Virtex-II Pro device is configured. After configuration, all instructions are available. JSTART and JSHUTDOWN are instructions specific to the Virtex-II Pro architecture and configuration flow. As described in Table 3-12, the JSTART and JSHUTDOWN instructions clock the startup sequence when the appropriate bitgen option is selected. The instruction does not work correctly without the correct bitgen option selected. bitgen -g startupclk:jtagclk designName.ncd UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 415 R Chapter 3: Configuration For details on the standard boundary-scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard. The user-defined registers (USER1/USER2) are described in USER1, USER2 Registers, page 419. Boundary-Scan Architecture Virtex-II Pro device registers include all registers required by the IEEE 1149.1 Standard. In addition to the standard registers, the family contains optional registers for simplified testing and verification (Table 3-13). Table 3-13: Virtex-II Pro JTAG Registers Register Name Register Length Description Instruction register Device specific Holds current instruction OPCODE and captures internal device status. Boundary scan register 3 bits per I/O Controls and observes input, output, and output enable. Bypass register 1 bit Device bypass. Identification register 32 bits Captures device ID. JTAG configuration register 64 bits Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions. USERCODE register 32 bits Captures user-programmable code Boundary-Scan Register The test primary data register is the boundary-scan register. Boundary-scan operation is independent of individual IOB configurations. Each IOB, bonded or un-bonded, starts as bidirectional with 3-state control. Later, it can be configured to be an input, output, or 3-state only. Therefore, three data register bits are provided per IOB (Figure 3-21). When conducting a data register (DR) operation, the DR captures data in a parallel fashion during the CAPTURE-DR state. The data is then shifted out and replaced by new data during the SHIFT-DR state. For each bit of the DR, an update latch is used to hold the input data stable during the next SHIFT-DR state. The data is then latched during the UPDATEDR state when TCK is Low. The update latch is opened each time the TAP Controller enters the UPDATE-DR state. Care is necessary when exercising an INTEST or EXTEST to ensure that the proper data has been latched before exercising the command. This is typically accomplished by using the SAMPLE/PRELOAD instruction. Consider internal pull-up and pull-down resistors when developing test vectors for testing opens and shorts. The boundary-scan mode determines if the IOB has a pull-up resistor. Figure 3-21 is a representation of Virtex-II Pro Boundary-Scan Architecture. 416 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode DOUT TDO SHIFTDR RESETB EXTEST IB TS IBUF PAD O 0BUF INTEST IB IJTAG I_JTAGB TDI CLOCKDR UPDATEDR UG002_C4_040_112800 Figure 3-21: Virtex Series Boundary Scan Logic Bit Sequence The order in each non-TAP IOB is described in this section. The input is first, then the output, and finally the 3-state IOB control. The 3-state IOB control is closest to the TDO. The input-only pins contribute only the input bit to the boundary-scan I/O data register. The bit sequence of the device is obtainable from the "Boundary-Scan Description Language Files" (BSDL files) for the Virtex family. These files can be obtained from the Xilinx software download area. The bit sequence is independent of the design. It always has the same bit order and the same number of bits. Bypass Register The other standard data register is the single flip-flop BYPASS register. It passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the CAPTURE-DR state. Instruction Register The instruction register loads the OPCODE necessary for the Virtex-II Pro boundary-scan instruction set. This register loads the current OPCODE and captures internal device status. The width of this register is device size specific. Configuration Register (Boundary-Scan) The configuration register is a 64-bit register. This register allows access to the configuration bus and readback operations. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 417 R Chapter 3: Configuration Identification Register Virtex devices have a 32-bit identification register, commonly referred to as the IDCODE register. This register is based upon IEEE Standard 1149.1 and allows easy identification of the part being tested or programmed via boundary scan. Virtex-II Pro Identification Register The Virtex-II Pro JTAG ID Code register has the following format. 3322 2222222 211111111 110000000000 1098 7654321 098765432 109876543210 vvvv:fffffff:aaaaaaaaa:ccccccccccc1 bit positions(00 to 31) where v is the revision code and f is the 7-bit family code = 0001000 0x08 a is the number of array rows in the part expressed in 9 bits. XC2VP2 = x = 0x XC2VP4 = x = 0x XC2VP7 = x = 0x XC2VP20 = x = 0x XC2VP50 = x = 0x c is the company code = 00001001001 = 0x049* *Since the last bit of the JTAG IDCODE is always one, the last three hex digits appear as 0x093. vvvv ffff fff a aaaa aaaa cccc cccc cccc 0001 000 0 0001 1000 0000 1001 0011 v 1 0 1 8 0 9 3 v 1 0 2 0 0 9 3 XC2VPxx XC2VPxx 418 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode ID Codes assigned to Virtex-II Pro FPGAs are shown in Table 3-14. Table 3-14: Virtex-II Pro Device ID Codes FPGA IDCODE XC2VP2 v1226093 XC2VP4 v123E093 XC2VP7 v124A093 XC2VP20 v1266093 XC2VP50 v 129E093 Notes: 1. The "v" in the IDCODE is the revision code field. USERCODE Register USERCODE is supported in the Virtex family as well. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and read back for verification at a later time. The USERCODE is embedded into the bitstream during bitstream generation (bitgen -g UserID option) and is valid only after configuration. USER1, USER2 Registers The USER1 and USER2 registers are only valid after configuration. These two registers must be defined by the user within the design. These registers can be accessed after they are defined by the TAP pins. The BSCAN_VIRTEX2 library macro is required when creating these registers. This symbol is only required for driving internal scan chains (USER1 and USER2). The BSCAN_VIRTEX2 macro provides two user pins (SEL1 and SEL2) for determining usage of USER1 or USER2 instructions respectively. For these instructions, two corresponding pins (TDO1 and TDO2) allow user scan data to be shifted out of TDO. In addition, there are individual clock pins (DRCK1 and DRCK2) for each user register. There is a common input pin (TDI) and shared output pins that represent the state of the TAP controller (RESET, SHIFT, and UPDATE). Unlike earlier FPGA families that required the BSCAN macro to dedicate TAP pins for boundary scan, Virtex-II Pro TAP pins are dedicated and do not require the BSCAN_VIRTEX2 macro for normal boundary-scan instructions or operations. Note that these are user-defined registers. The example (Figure 3-22) is one of many implementations. For HDL, the BSCAN_VIRTEX2 macro needs to be instantiated in the design. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 419 R Chapter 3: Configuration cap0 SHIFT TDI cap1 0 cap2 0 1 0 1 D 1 D Q R D Q R Q TDO1 R DRCK1 RESET D D Q CE D Q CE R Q CE R R SEL1 UPDATE Internal Symbol Logic CLOCKDR DRCK1 SEL1 BSCAN_VIRTEX2 UPDATE SHIFT RESET TDI SEL1 DRCK1 SEL2 DRCK2 CAPTURE TDO1 TDO2 SEL2 DRCK2 Figure 3-22: BSCAN_VIRTEX2 (Example Usage) Using Boundary Scan in Virtex-II Pro Devices Characterization data for some of the most commonly requested timing parameters shown in Figure 3-23 is listed in Table 3-15. TMS TDI TTAPTCK TTCKTAP TCK TTCKTDO TDO Data Valid Data to be captured Data Valid Data to be driven out x139_05_020300 Figure 3-23: 420 Virtex-II Pro Boundary Scan Port Timing Waveforms www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Table 3-15: Symbol Boundary-Scan Port Timing Specifications Parameter Value Units TTAPTCK TMS and TDI setup time before TCK 4.0 ns, min TTCKTAP TMS and TDI hold times after TCK 2.0 ns, min TTCKTDO TCK falling edge to TDO output valid 11.0 ns, min FTCK Maximum TCK clock frequency 33.0 MHz, max For further information on the Startup sequence, bitstream, and internal configuration registers referenced here, refer to Readback, page 441. Configuring Through Boundary-Scan One of the most common boundary-scan vendor-specific instructions is the configure instruction. An individual Virtex-II Pro device is configured via JTAG on power-up using TAP. If the Virtex-II Pro device is configured on power-up, it is advisable to tie the mode pins to the boundary-scan configuration mode settings; 101 (M2 = 1, M1 = 0, M0 = 1). Configuration flow for Virtex-II Pro device configuration with JTAG is shown in Figure 3-24. The sections that follow describe how the Virtex-II Pro device can be configured as a single device via boundary-scan or as part of a multiple-device scan chain. A configured device can be reconfigured by toggling the TAP and entering a CFG_IN instruction after pulsing the PROG_B pin or issuing the shut-down sequence. (Refer to Power Up, page 392). For additional details on power-up or the start-up sequence in Virtex-II Pro devices, see Device Startup, page 394. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 421 R Chapter 3: Configuration For additional detailed information on using Virtex devices in an embedded solution, see Xilinx application note XAPP058. Power Up No VCCI > 1.0 V Yes Keep Clearing Configuration Memory Yes PROG_B Low? Clear Configuration Memory Once More INIT_B = High? No Yes JTAG Available Sample Mode Pins Load JShutdown Instruction Shutdown Sequence Load CFG_IN Instruction Load Bitstream CRC Correct? No Abort Startup Yes Load JSTART Instruction Start-up Sequence Yes Operational Reconfigure? No ug002_c4_37101300 Figure 3-24: Device Configuration Flow Diagram 422 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Single Device Configuration Configure a Virtex-II Pro part as a single device via boundary-scan operations as follows. Ensure that the bitstream is generated with the JTAG clock option. bitgen -g startupclk:jtagclk designName.ncd Also, when using JTAG Programmer software, verify that the most current version is being used. Table 3-16 describes the TAP controller commands required to configure a Virtex-II Pro device. Refer to Figure 3-20 for TAP controller states. These TAP controller commands are issued automatically if configuring the part with the JTAG Programmer software. Table 3-16: Single Device Configuration Sequence Set & Hold # of Clocks TAP Controller Step Description TDI TMS TCK On power-up, place a logic "one" on the TMS and clock the TCK five times. This ensures starting in the TLR (Test-Logic-Reset) state. X 1 5 2 Move into the RTI state. X 0 1 3 Move into the SELECT-IR state. X 1 2 4 Enter the SHIFT-IR state. X 0 2 5 Start loading the CFG_IN instruction. 00101 0 5 6 Load the last bit of CFG_IN instruction when exiting SHIFT-IR. as defined in the IEEE standard. 0 1 1 7 Enter the SELECT-DR state. X 1 2 8 Enter the SHIFT-DR state. X 0 2 9 Shift in the Virtex-II Pro bitstream. Bitn (MSB) is the first bit in the bitstream1. bit1 ...bitn 0 (bits in bitstream) - 1 bit0 1 1 11 Enter UPDATE-DR state. X 1 1 12 Enter the SELECT-IR state. X 1 2 13 Move to the SHIFT-IR state. X 0 2 01100 0 5 15 Load the last bit of the JSTART instruction. 0 1 1 16 Move to RTI and clock the STARTUP sequence by applying a minimum of 12 clock cycles to the TCK. X 0 12 17 Move to the TLR state. The device is now functional. X 1 3 1 10 Shift in the last bit of the bitstream. Bit0 (LSB) shifts on the transition to EXIT1-DR. 14 Start loading the JSTART instruction. The JSTART instruction initializes the startup sequence. Notes: 1. In the Configuration Register, data is shifted in from the right (TDI) to the left (TDO). UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 423 R Chapter 3: Configuration Multiple Device Configuration It is possible to configure multiple Virtex-II Pro devices in a chain. The devices in the JTAG chain are configured one at a time. The multiple device configuration steps are described generally to be applied to any size chain. Ensure the bitstream is generated with the JTAG clock option. bitgen -g startupclk:jtagclk designName.ncd Refer to the State Diagram in Figure 3-20 for the following TAP controller steps. 1. On power-up, place a logic "one" on the TMS and clock the TCK five times. This ensures starting in the TLR (Test-Logic-Reset) state. 2. Load the CFG_IN instruction into the target device (and BYPASS in all other devices).Go through RTI (RUN-TEST/IDLE). Repeat steps 2 through 4 for each successive device. 3. Load the JSTART command into all devices. 4. Go to RTI and clock TCK 12 times. All devices are active at this point. TDO TDI Virtex-II FPGA TDI TDO Virtex-II FPGA TDI TDO Virtex-II FPGA TDI TDO TMS TMS TMS TMS TCK TCK TCK TCK PROG_B PROG_B PROG_B Device 0 Device 1 Device 2 ug002_c3_026101300 Figure 3-25: Boundary Scan Chain of Devices Notes: 1. PROG_B pin should be deasserted during JTAG operation. 424 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Reconfiguring Through Boundary Scan The ability of Virtex-II Pro devices to perform partial reconfiguration is the reason that the configuration memory is not cleared when reconfiguring the device. When reconfiguring a chain of devices, refer to step 3 in Table 3-16. There are two methods to reconfigure Virtex-II Pro devices without possible internal contention. The first method is to pulse the PROG_B pin which resets the internal configuration memory. The alternate method is to perform a shutdown sequence, placing the device in a safe state. The following shutdown sequence includes using internal registers. (For details on internal registers, refer to Readback, page 441.) 1. Load the CFG_IN instruction. 2. In SHIFT-DR state, load the synchronization word followed by the Reset CRC Register (RCRC) command. 1111 1010 0011 0000 0000 0000 1111 1010 0000 0000 0000 0000 1111 1001 0000 0000 0000 0000 1111 1001 0000 0000 0000 0000 1111 0101 1000 0000 0000 0000 1111 0101 0000 0000 0000 0000 1111 0110 0000 0000 0000 0000 1111-> 0110-> 0001-> 0111-> 0000-> 0000-> Dummy word Synchronization word Header: Write to CMD register RCRC command flush pipe flush pipe 3. Load JSHUTDOWN. 4. Go to RTI and clock TCK at least 12 times to clock the shutdown sequence. 5. Proceed to SHIFT-IR state and load the CFG_IN instruction again. 6. Go to SHIFT-DR state and load the configuration bits. Make sure the configuration bits contain AGHIGH command, which asserts the global signal GHIGH_B. This prevents contention while writing configuration data. 0011 0000 0000 0000 1000 0000 0000 0001-> Header: Write to CMD 0000 0000 0000 0000 0000 0000 0000 1000-> AGHIGH command asserts GHIGH_B 7. When all configuration bits have been loaded, go to SHIFT-IR state and load the JSTART instruction. 8. Go to RTI and clock TCK at least 12 times to clock the startup sequence. 9. Go to TLR state to complete the reconfiguration process. Debugging Configuration To verify successful configuration, there are several options. Some of the most helpful verification steps include using TAP pins and the readback command. Using the Virtex-II Pro TAP controller and status pins is discussed first. When using TAP controller pins, TDO is driven only in the SHIFT-DR and SHIFT-IR state. If the output of the TDO can be changed via an external pull-up resistor, the TAP is not in SHIFT-IR or SHIFT-DR. If the TAP can be controlled precisely, use this to test the application. In JTAG configuration, the status pin (DONE) functions the same as in the other configuration modes. The DONE pin can be monitored to determine if a bitstream has been completely loaded into the device. If DONE is Low, the entire bitstream has not been sent or the start-up sequence is not finished. If DONE is High, the entire bitstream has been received correctly. The INIT_B pin functions similar to a normal INIT_B but does not indicate a configuration error in boundary-scan configuration. In addition to external pin monitoring, an internal test can be conducted. The second method includes the following steps to capture the internal device status register contents: 1. Move the TAP to TLR state. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 425 R Chapter 3: Configuration 2. Go to SHIFT-IR state and load in the CFG_IN instruction. 3. Go to SHIFT-DR state and shift in the following 64-bit pattern with the MSB (left-most bit), shifted in first. 1111 1010 0010 0000 0000 0000 1111 1010 1000 0000 0000 0000 1111 1001 0000 0000 0000 0000 1111 1001 0000 0000 0000 0000 1111 0101 1110 0000 0000 0000 1111 0101 0000 0000 0000 0000 1111 0110 0000 0000 0000 0000 1111-> 0110-> 0010-> 0000-> 0000-> 0000-> Dummy word Synchronization word Read STATus Register 1) flush pipe flush pipe flush pipe Notes: 1. Since the JTAG readback shift register is 64-bit long, two 32-bit words are needed to fill the shift register. 4. After shifting in the pattern, load the CFG_OUT instruction in the SHIFT-IR state. 5. Move to SHIFT-DR state and clock TCK 32 times while reading TDO. The data seen on TDO is the content of the status register. The last bit out is a one if a CRC error occurred. If successful, it should read as follows. 0000 0000 0000 0000 0001 1MMM 1110 111011,2) Notes: 1. MMM is the mode pins value. 2. Assuming that the device is in normal operation mode. Since the read status activity causes the crc_error status to be asserted, it is important to clear the crc_error status to ensure normal device operation. This can be done by writing the precalculated CRC value to the CRC register or writing an RCRC command. 6. Go to SHIFT-IR state and load the CFG_IN instruction again. 7. Move to SHIFT-DR state and shift in the following bit pattern: 0011 0000 0000 0000 8. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001-> 0111-> 0000-> 0000-> Header: Write to CMD register RCRC command flush pipe flush pipe Put the TAP in TLR state when finished. The device status register also gives the status of the DONE and INIT_B signals. For information on the status register, refer to Figure 3-30. 426 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Boundary-Scan for Virtex-II Pro Devices Using IEEE Standard 1532 ISC Modal States ISC_ENABLE is executed Unprogrammed (0,0) TLR & ISC_Done is clear Any non-test inst.but ISC_DISABLE loaded and ISC_DONE is clear ISC_Accessed (1,X) TLR and ISC_Done is set ISC_Done is clear Power UP ISC_ENABLE executed ISC_Done is set Any non-test inst. but ISC_ENABLE executed Any non-test inst. but ISC_DISABLE executed Operational (0,1) ISC_DISABLE executed Any non-test inst. but ISC_ENABLE executed ISC Complete (0,X) Any non-test inst.but ISC_DISABLE loaded and ISC_DONE is set ISC_DISABLE loaded (ISC_Enabled, ISC_Done) UG002 01 082600 Figure 3-26: ISC Modal States Once the device is powered up, it goes to an Unprogrammed state. The I/Os are all either 3-stated or pulled up. When ISC_ENABLE is successfully executed, the ISC_Enabled signal is asserted, and the device moves to ISC_Accessed state. When the device moves to ISC_Accessed state from Operational state, the shutdown sequence is executed. The I/Os are all either 3-stated or pulled up. The StartUp sequence is executed when in the ISC_Accessed state. At the end of the StartUp Sequence, ISC_Enabled is cleared and the device moves to ISC_Complete. The minimum clock cycle requirement is the number of clock cycles required to complete the StartUp sequence. At the completion of the minimum required clock cycles, ISC_Enabled is deasserted. Whether the StartUp sequence is successful or not is determined by CRC or configuration error status from the configuration processor. If the startup is completed, ISC_Done is asserted; otherwise, ISC_Done stays Low. The I/Os are either 3-stated or pulled up. When ISC_Done is set in ISC_Complete state, the device moves to the Operational state. Otherwise, if ISC_Done is clear, the device moves to an Unprogrammed state. However, if the TAP controller goes to TLR state while the device is in ISC_Accessed state and if ISC_Done is set, then the device moves to the Operational state. However, the I/O is not active yet because the Startup sequence has not been performed. The Startup sequence has to be performed in the Operational state to bring the I/O active. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 427 R Chapter 3: Configuration Clocking Startup and Shutdown Sequence (JTAG Version) There are three clock sources for Startup and Shutdown sequence, CCLK, UserCLK, and JTAGCLK. Clock selection is set by bitgen. The Startup sequence is executed in ISC_Accessed state. When it is clocked by JTAGCLK, the Startup sequence receives the JTAGCLK in TAP Run/Test Idle state while ISC_DISABLE is the current JTAG instruction. The number of clock cycles in Run/Test Idle state for successful completion of ISC_DISABLE is determined by the number of clock cycles needed to complete the Startup sequence. When UserCLK or CCLK is used to clock the Startup sequence, the user should know how many JTAGCLK cycles should be spent in Run/Test Idle to successfully complete the Startup sequence. The Shutdown sequence is executed when the device transitions from an Operational to ISC_Accessed state. Shutdown is done while executing the ISC_ENABLE instruction. When the Shutdown sequence is clocked using JTAGCLK, the clock is supplied in the Run/Test Idle state of the ISC_ENABLE instruction. The number of clock cycles in Run/Test Idle is determined by the number of clock cycles needed to complete the Shutdown sequence. When the Shutdown sequence is clocked by CCLK or UserCLK, the user is responsible for knowing how many JTAGCLK cycles in Run/Test Idle are needed to complete the Shutdown sequence. Notes: 1. It has been decided that when configuring the device through JTAG, the startup and shutdown clock should come from TCK, regardless of the selection in bitgen. 2. In IEEE 1532 configuration mode, Startup and Shutdown clock source is always TCK. 428 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R JTAG/ Boundary Scan Programming Mode Configuration Flows Using JTAG Power Up PROG_B Vcc > ? A No Load 64 bits of bitstream data Yes PROG_B Yes RTI 1 TCK cycles Keep clearing Configuration memory No No Clear Configuration memory once more End of Data Yes No CRC correct INIT_B = High? Yes No Pull INIT_B Low STOP Yes Sample mode pins Load ISC_DISABLE RTI minimum 12 TCK cycles Load ISC_ENABLE Operational Load 00000 RTI minimum 12 TCK cycles Reconfigure No Yes Load ISC_PROGRAM A UG002_c4_38_101300 Figure 3-27: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook IEEE 1532 Configuration Flow www.xilinx.com 1-800-255-7778 429 R Chapter 3: Configuration TAP Instr. IDCODE ISC_ENABLE Anything but ISC_DISABLE ISC_DISABLE BYPASS ISC_Accessed ISC_Complete Operational ISC_Enabled ISC_Done End of Startup Modal State Unprog. System Output Active Disable (3-stated) Start-up UG002_C3_028_113000 Figure 3-28: Signal Diagram for Successful First Time ISC Configuration TAP Instr. IDCODE ISC_ENABLE Anything but ISC_DISABLE ISC_DISABLE BYPASS ISC_Accessed ISC_Complete Operational ISC_Enabled ISC_Done End of Startup Modal State Operational System Output Active Disabled Start-up UG002_C3_029_113000 Figure 3-29: Signal Diagram for Successful ISC Partial and Full Reconfiguration Software Support and Data Files For Virtex-II Pro devices, the Xilinx tool set includes the JTAG Programmer software to program and get Virtex-II Pro IDCODEs. For test vectors EXTEST or INTEST, or to utilize other JTAG features present in the devices, see www.xilinx.com under Configuration Solutions for third party boundary-scan software tools. 430 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration With MultiLINX IMPORTANT NOTE: To perform any configuration operations through JTAG, the bitgen option should be set for the JTAG clock option. bitgen -g startupclk:jtagclk designName.ncd For Readback operations, this option can be used. bitgen -w -l -m -g readback Readback is not supported in the current version of JTAG Programmer Software. JTAG Programmer JTAG Programmer software is a standard feature of the Alliance SeriesTM and Foundation SeriesTM software packages. JTAG Programmer is a part of Web Pack, which can be downloaded from the following site: http://support.xilinx.com/support/software.htm Configuration With MultiLINX The MultiLINX cable set is a peripheral hardware product. It is used primarily for downloading configuration and programming data from a host computer to Xilinx FPGAs and CPLDs in a target system. The MultiLINX system supports a USB (Universal Serial Bus) interface with communication speeds up to 12 Mb/s, reducing download times by a factor of 120X relative to previous cables. The MultiLINX cable set includes all appropriate flying leads for multiple configuration mode support. In addition, MultiLINX cable sets support readback modes, such as verification and the Virtex-II Pro SelectMAP interface. MultiLINX cable internal hardware is upgraded via software, facilitating the addition of new cable features and simplifying support. Upgrades are completely seamless and invisible to users. For additional information on the MultiLINX cable set and other Xilinx hardware products, refer to the Hardware User Guide on the web, or go to the following site: http://www.xilinx.com/support/programr/cables.htm Configuration Details This section provides a bit-level understanding of the configuration stream. For the purpose of debugging, designing embedded readback operations, or otherwise complex styles of configuring multiple FPGAs, the Virtex-II bitstream, internal configuration logic, and internal processing of configuration data are described here. Data Frames The internal configuration memory is partitioned into segments called "Frames." The portions of the bitstream that actually get written to the configuration memory are "Data Frames." The number and size of frames varies with device size as shown in Table 3-17. The total number of configuration bits for a particular device is calculated by multiplying UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 431 R Chapter 3: Configuration the number of frames by the number of bits per frame, and then adding the total number of bits needed to perform the Configuration Register Writes shown in Table 3-17. Table 3-17: Virtex-II Pro Configuration Data Frames and Programming Times Approx. Total No. of Approx. Serial Approx. JTAG Configuration SelectMAP Bits (including Download Time Download Time Bits Download Time header) (50 MHz) ms (33 MHz) ms (50 MHz) ms Device No. of Frames Frame Length in Bits XC2VP2 884 1,472 1,301,248 1,305,440 3.26 26.11 39.56 XC2VP4 884 3,392 2,998,528 3,006,560 7.52 60.13 91.11 XC2VP7 1,320 3,392 4,477,440 4,485,472 11.21 89.71 135.92 XC2VP20 1,756 4,672 8,204,032 8,214,624 20.54 164.29 248.93 XC2VP50 2,628 7,232 19,005,696 19,021,408 47.55 380.43 576.41 Configuration Registers The Virtex-II Pro configuration logic was designed so that an external source can have complete control over all configuration functions by accessing and loading addressed internal configuration registers over a common configuration bus. The internal configuration registers that are used for configuration and readback are listed in Table 3-18. All configuration data, except the synchronization word and dummy words, is written to internal configuration registers. Table 3-18: Internal Configuration Registers Symbol 432 Register Name Address CRC CRC Register 00000 FAR Frame Address Register 00001 FDRI Frame Data Input Register (Write Configuration Data) 00010 FDRO Frame Data Output Register (Readback Configuration Data) 00011 CMD Command Register 00100 CTL Control Register 00101 MASK Masking Register for CTL 00110 STAT Status Register 00111 LOUT Legacy Output Register (DOUT for daisy chain) 01000 COR Configuration Option Register 01001 MFWR Multiple Frame Write 01010 FLR Frame Length Register 01011 IDCODE Product ID Code Register 01110 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Details Command Register (CMD) Commands shown in Table 3-19 are executed by loading the binary code into the CMD register. Table 3-19: CMD Register Commands Symbol Command Binary Code WCFG Write Configuration Data 0001 MFWR Multi-Frame Write 0010 DGHIGH De-asserts GHIGH 0011 RCFG Read Configuration Data 0100 START Begin STARTUP Sequence 0101 RCAP Reset CAPTURE (after Single-Shot Capture) 0110 RCRC Reset CRC Register 0111 AGHIGH Assert GHIGH 1000 SWITCH Switch CCLK Frequency 1001 GRESTORE Pulse GRESTORE Signal 1010 SHUTDOWN Begin SHUTDOWN Sequence 1011 GCAPTURE Pulse GCAPTURE Signal (one shot) 1100 DESYNCH Forces realignment to 32 bits 1101 Frame Length Register (FLR) The FLR is used to indicate the frame size to the internal configuration logic. This allows the internal configuration logic to be identical for all Virtex-II Pro devices. The value loaded into this register is the number of actual configuration words that get loaded into the configuration memory frames. Configuration Option Register (COR) The COR is loaded with the user selected options from bitstream generation. See Appendix A, "BitGen and PROMGen Switches and Options.". Table 3-20: Configuration Option Register Name Description Bits CRC_BYPASS Does not check against updated CRC value. 29 SHUT_RST_DCI DCI resets if SHUTDOWN and AGHIGH are performed. 27 SHUT_RST_DCM DCM resets if SHUTDOWN and AGHIGH are performed. 26 DONE_PIPE Add pipeline stage to DONEIN. 25 DRIVE_DONE DONE pin is an active driver, not open drain. 24 SINGLE Readback capture is one shot. 23 OSCFSEL Select CCLK frequency in Master Serial Mode. 22:17 SSCLKSRC Select STARTUP block clock source. 16:15 DONE_CYCLE Startup cycle when DONE is asserted/de-asserted. 14:12 MATCH_CYCLE Stall in this Startup cycle until DCI match signals are asserted. 11:9 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 433 R Chapter 3: Configuration Table 3-20: Configuration Option Register Name Description Bits LOCK_CYCLE Stall in this Startup cycle until DCM signals are asserted. 8:6 GTS_CYCLE Startup cycle when GTS_CFG_B is de-asserted. 5:3 GWE_CYCLE Startup cycle when GWE is asserted. 2:0 Control Register (CTL) The CTL controls internal functions such as Security and Port Persistence. Table 3-21: Control Register Name Description Bits SBITS Security level. 4:5 PERSIST Configuration ports remain after configuration. Reserved For internal use. GTS_USR_B Active Low global 3-state I/Os. Turns off pullups if GTS_CFG_B is also asserted. 3 2:1 0 Mask Register (MASK) The MASK is a safety mechanism that controls which bits of the CTL register can be reloaded. Prior to loading new data into the CTL register, each bit must be independently enabled by its corresponding bit in the MASK register. Any CTL bit not selected by the MASK register is ignored when reloading the CTL register. Frame Address Register (FAR) The FAR sets the starting frame address for the next configuration data input write cycle. Frame Data Register Input (FDRI) The FDRI is the input stage for configuration data frames to be stored in the configuration memory. Starting with the frame address specified in the FAR, the FDRI writes its contents to the configuration memory frames. The FDRI automatically increments the frame address after writing each frame for the number of frames specified in the FDRI write command. This is detailed in the next section. CRC Register (CRC) The CRC is loaded with a CRC value that is embedded in the bitstream and compared against an internally calculated CRC value. Resetting the CRC register and circuitry is controlled by the CMD register. Frame Data Register Output (FDRO) FDRO is an output stage for reading frame data from the configuration memory during readback. This works the same as the FDRI but with data flowing in the other direction. Legacy Data Output Register (LOUT) LOUT is pipeline data to be sent out the DOUT pin for serially daisy-chained configuration data output. Status Register (STAT) The STAT register contains bits that indicate the state of the device. Such bits include the status of error pins, global signals, the DCM, and DCI. This register is read-only and can be read using the JTAG or SelectMAP port for debugging purposes. 434 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IN_ERROR DCI_MATCH DCM_LOCK RESERVED CRC_ERROR GHIGH_B GWE GTS_CFG_B MODE RESERVED RESERVED ID_ERROR DONE INIT_B Configuration Details 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Figure 3-30: Table 3-22: Status Register Fields Status Register Name Description Bit Location ID_ERROR IDCODE not validated while trying to write FDRI 13 DONE DONEIN input form DONE pin 12 INIT_B Value of CFG_RDY (INIT_B) 11 MODE Value or MODE pins (M2, M1, M0) GHIGH_B Status of GHIGH 7 GWE Status of GWE 6 GTS_CFG_B Status of GTS_CFG_B 5 IN_ERROR Legacy input error 4 DCI_MATCH DCI matched 3 DCM_LOCK DCM matched 2 Reserved For internal use 1 CRC_ERROR CRC error 0 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 10:8 435 R Chapter 3: Configuration Configuration Data Processing Flow The complete (standard) reconfiguration of a Virtex-II device follows the internal flow shown in Figure 3-31. All associated configuration commands are listed in Table 3-23. Initialize Maximum of three CCLK cycles. Synchronize Define 32-bit word boundaries. Reset CRC Initialize CRC calculation. Set Frame Size Internal use. Set Options Set start-up and ConfigRate. Set Control Parameters Internal use. Set CCLK Frequency Master Serial CCLK changes to optional configuration. Write Frames Invoke Start-up Load CRC Finish Data frames written to configuration memory. Start-up Sequence commences after CRC calculation. If CRC fails, start-up is aborted. Otherwise, Start-up Sequence commences. FPGA is active. X138_09_082599 Figure 3-31: Internal Configuration Processing Flow 436 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Details Table 3-23: Configuration Register Writes Type Number of 32-bit Words Command Set 1 Dummy words 1 Synchronization word 1 Write CMD (RCRC) 2 Write FLR 2 Write COR 2 Write ID 2 Write MASK 2 Write CMD (SWITCH) 2 Command Set 2 Write FAR 2 Write CMD (WCFG) 2 Write FDRI part size dependent Write CMD (DGHIGH) 2 Command Set 3 Write COR 2 Write CMD (START) 2 Write CTL 2 Write CRC 2 Write CMD (DESYNCH) Dummy words 4 TOTAL 40 The first command set prepares the internal configuration logic for the loading of the data frames. The internal configuration logic is first initialized with several CCLK cycles represented by dummy words, then it is synchronized to recognize the 32-bit word boundaries by the synchronization word. The CRC register and circuitry must then be reset by writing the RCRC command to the CMD register. The frame length size for the device being configured is then loaded into the FLR register. The configuration options are loaded into the COR. The CCLK frequency selected is specified in the COR; however, to switch to that frequency the SWITCH command must be loaded into the CMD register. The ID register is written to ensure that the correct bitstream is being used. Now the data frames can be loaded. The second command set loads the configuration data frames. First, a WCFG (Write Configuration) command is loaded into the CMD register activating the circuitry that writes the data loaded into the FDRI into the configuration memory cells. To load a set of data frames, the starting address for the first frame is first loaded to the FAR, followed by a write command, and then by the data frames to the FDRI. The FDRI write command also specifies the amount of data that is to follow in terms of the number of 32-bit words that comprise the data frames being written. When all but the last frame has been loaded, an initial CRC checksum is loaded into the CRC register. The De-assert GHIGH (DGHIGH) is loaded into the CMD register. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 437 R Chapter 3: Configuration The third command set initializes the Start-Up Sequence and finishes CRC checking. After all the data frames have been loaded, the START command is loaded into the CMD register, followed by any internal control data to CTL, the final CRC value into the CRC register, and the DESYNCH command to the CMD register. The four dummy words at the end are flushed through the system to provide the finishing CCLK cycles to activate the FPGA. Standard Bitstream Virtex-II Pro devices have the ability to be only partially re-configured or read back. The standard bitstream, currently generated by BitGen, follows the format shown in Table 3-24, Table 3-25, and Table 3-26. This format assumes D0 is considered the MSB. It is divided into three tables to follow the three command sets described in the previous subsection. Table 3-24 shows the first set of commands in the bitstream that prepare the configuration logic for rewriting the memory frames. All commands are described as 32-bit words, since configuration data is internally processed from a common 32-bit bus. Table 3-24: Bitstream Header and Configuration Options Data Type Dummy word Synchronization word Packet Header: Write to CMD register Packet Data: RCRC Packet Header: Write to FLR register Packet Data: Frame Length Packet Header: Write to COR Packet Data: Configuration options (user defined) Packet Header: Write to ID register Packet Data: IDCODE Packet Header: Write to CMD register Packet Data: SWITCH Packet Header: Write to CMD register Packet Data: WCFG From Table 3-24, the first dummy word pads the front of the bitstream to provide the clock cycles necessary for initialization of the configuration logic. No actual processing takes place until the synchronization word is loaded. Since the Virtex-II Pro configuration logic processes data as 32-bit words, but can be configured from a serial or 8-bit source, the synchronization word is used to define the 32-bit word boundaries. That is, the first bit after the synchronization word is the first bit of the next 32-bit word, and so on. After synchronization, all data (register writes and frame data) are encapsulated in packets. There are two kinds of packets, Header and Data. A header packet has two types: Type 1 and Type 2. Type 1 Packet Headers are used for register writes. A combination of Type 1 and Type Packet Headers are used for frame data writes. A Type 1 Packet Header, shown in Figure 3-32, is always a single 32-bit word that describes the header type, whether it is a read/write function to a specific configuration register address (see Table 3-18) as the destination, and how many 32-bit words are in the following Packet Data portion. A Type 1 Packet Data portion can contain anywhere from 0 to 2,047 32-bit data words. 438 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Configuration Details Packet Header Type Bits[31:0] 31:29 Type 1 001 Operation (Write/Read) Register Address (Destination) Byte Address Word Count (32-bit Words) 28:27 26:13 12:11 10:0 10 / 01 XXXXXXXXXXXXXX XX XXXXXXXXXXXX X138_10_082599 Figure 3-32: Type 1 Packet Header Packet Header Type Operation (Write/Read) Bits[31:0] 31:29 28:27 Word Count (32-bit Words) 26:0 Type 2 010 10 / 01 XXXXXXXXXXXXXXXXXXXXXXXXXX X138_11_082599 Figure 3-33: Type 2 Packet Header The first packet header in Table 3-24 is a Type 1 packet header that specifies writing one data word to the CMD register. The following packet data is a data word specifying a reset of the CRC register (compare the data field of Table 3-24 to the binary codes of Table 3-19). The second packet header in Table 3-24 loads the frame size into the FLR. The third packet header loads the configuration options into the COR register. The binary description of this register is not documented. Following this is a similar write of the SWITCH command to the CMD register which selects the CCLK frequency specified in the COR. Finally, the WCFG command is loaded into the CMD register so that the loading of frame data can commence. The fourth packet header writes to the ID register. This ensures the correct bitstream for the correct Virtex-II Pro family member. Table 3-25 shows the packets that load all of the data frames, starting with a Type 1 packet header to load the starting frame address, which is always 0h. Table 3-25: Bitstream Data Frames and CRC Sequence Data Type Packet Header: Write to FAR register Packet Data: Starting frame address Packet Header: Write to FDRI Packet Header Type 2: Data words Packet Data: Configuration data frames in 32-bit words. Total number of words specified in Type 2 Packet Header Packet Data: CRC value Packet Header: Write to CMD register Packet Data: GRESTORE Packet Header: Write to CMD register Packet Data: DGHIGH Packet Header: NO OP Packet Data: one frame of NO OP The loading of data frames requires a combination of Type 1 and Type 2 packet headers. Type 2 packet headers must always be preceded by a Type 1 packet header. The Type 2 packet data can be up to 67,108,863 data words in size. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 439 R Chapter 3: Configuration The Type 2 packet header, shown in Figure 3-33, differs slightly from a Type 1 packet header in that there is no Register Address or Byte Address fields. To write a set of data frames to the configuration memory, after the starting frame address has been loaded into the FAR, a Type 1 packet header issues a write command to the FDRI, followed by a Type 2 packet header specifying the number of data words to be loaded, and then followed by the actual frame data as Type 2 packet data. Writing data frames might require a Type 1/Type 2 packet header combination, or a Type 1 only. This depends on the amount of data being written. Table 3-26 shows the packets needed to issue the start-up operations and load the final CRC check. The FPGA does not go active until after the final CRC is loaded. The number of clock cycles required to complete the start-up sequence depends on the BitGen options selected. Completion of the configuration process requires 8 to 16 clock cycles after the DESYNCH command. The DESYNCH command forces realignment to 32-bit boundaries and, therefore, a synchronization word is needed. Table 3-26: Bitstream Final CRC and Start-Up Sequence Data Type Packet Header: Write to CMD register Packet Data: START Packet Header: Write to MASK Packet Data: CTL mask Packet Header: Write to CTL Packet Data: Control commands Packet Header: Write to CRC Packet Data: CRC value Packet Header: Write to CMD Packet Data: DESYNCH command Dummy word Dummy word Dummy word Dummy word Typically, DONE is released within the first seven CCLK cycles after the final CRC value is loaded, but the rest of the dummy data at the end of the stream should continue to be loaded. The FPGA needs the additional clock cycles to finish internal processing, but this is not a concern when a free-running oscillator is used for CCLK. In serial mode, this requires only 16 bits (two bytes), but in SelectMAP mode, this requires 16 bytes of dummy words at the end of the bitstream. Since the intended configuration mode to be used is unknown by Bitgen, four 32-bit dummy words (16 bytes) are always placed at the end of the bitstream. Cyclic Redundancy Checking Algorithm Virtex-II Pro configuration uses a standard 16-bit CRC checksum algorithm to verify bitstream integrity during configuration. The 16-bit CRC polynomial is shown below. CRC-16 = X16 + X15 + X2 + 1 The algorithm is implemented by shifting the data stream into a 16-bit shift register, shown in Figure 3-34. Register Bit(0) receives an XOR of the incoming data and the output of Bit(15). Bit(2) receives an XOR of the input to Bit(0) and the output of Bit(1). Bit(15) receives an XOR of the input to Bit(0) and the output of Bit(14). 440 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Readback CRC Calculation Register 15 2 0 3 1 4 5 6 7 9 8 10 11 12 13 14 CRC Data Input Register Address 4 3 2 1 DATA_IN 32-bit Data Word 0 31 30 29 28 27 26 5 4 3 2 1 0 SHIFT 0000 0000 0000 0000 16-bit CRC 31:16 15:0 CRC Register [31:0] x138_12_082300 Figure 3-34: Serial 16-bit CRC Circuitry A CRC Reset resets all the CRC registers to zero. As data is shifted into the CRC circuitry, a CRC calculation accumulates in the registers. When the CRC value is loaded into the CRC calculation register, the ending CRC checksum is loaded into the CRC Register. The value loaded into the CRC Register should be zero; otherwise, the configuration failed CRC check. Not all of the configuration stream is loaded into the CRC circuitry. Only data that is written to one of the registers shown in Table 3-23 is included. For each 32-bit word that is written to one of the registers (Table 3-23), the address code for the register and the 32-bit data word is shifted LSB first into the CRC calculation circuitry, see Figure 3-34. When multiple 32-bit words are written to the same register, the same address is loaded after each word. All other data in the configuration stream is ignored and does not affect the CRC checksum. This description is a model that can be used to generate an identical CRC value. The actual circuitry in the device is a slightly more complex Parallel CRC circuit that produces the same result. Readback Readback is the process of reading all the data in the internal configuration memory. This can be used to verify that the current configuration data is correct and to read the current state of all internal CLB and IOB registers as well as the current LUT RAM and block RAM values. Readback is only available through the SelectMAP and Boundary Scan interfaces. This discussion covers the use of the SelectMAP interface for performing readback. For information on using the Boundary Scan interface for readback see "Readback When Using Boundary Scan" on page 442. Readback Verification and Capture Readback verification is used to verify the validity of the stored configuration data. This is most commonly used in space-based applications where exposure to radiation might alter the data stored in the configuration memory cells. Readback capture is used to list the states of all the internal flip-flops. This can be used for hardware debugging and functional verification. When Capture is initiated, the internal register states are loaded into unused spaces in the configuration memory which can be extracted after a readback of the configuration memory. While both Verify and Capture can be performed in one readback, each require slightly different preparation and post processing. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 441 R Chapter 3: Configuration Preparing for Readback in Design Entry If only a readback verification is to be performed, there are no additional steps at the time of design entry. However, if readback capture is to be used, the Virtex-II Pro library primitive CAPTURE_VIRTEX2 must be instantiated in the user design as shown in Figure 3-35. The CAPTURE_VIRTEX2 component is used in the FPGA design to control when the logic states of all the registers are captured into configuration memory. The CLK pin can be driven by any clock source that would synchronize Capture to the changing logic states of the registers. The CAP pin is an enable control. When CAP is asserted, the register states are captured in memory on the next CLK rising edge. Capture can be performed in two ways: single-shot or continuous. In continuous capture, the CAP line is held High until the desired capture event occurs causing CAP to go Low. See Figure 3-35. Continuous capture does not require a readback operation to reset the CAPTURE block. In single-shot capture, the CAP line is pulsed once, and subsequent pulses are ignored until a readback operation has been performed. Captured data is read using the same process as a normal readback. Trigger with External or Internal Signal. CAPTURE_VIRTEX2 CAP CLK Synchronize to External or Internal Clock. ug002_c4_35_091900 Figure 3-35: Readback CAPTURE_VIRTEX2 Library Primitive Enabling Readback in the Software Since readback is performed through the SelectMAP interface after configuration, the configuration ports must continue to be active by setting the persistence switch in BitGen. Additionally, a readback bit file, which contains the commands to execute a readback and a bitmap for data verification, can optionally be generated by setting the readback option in BitGen. An example of the BitGen command line is shown below. bitgen -w -l -m -g readback -g persist:yes... The -w option overwrites existing output. The -l option generates a Logic Allocation file. The -m option generates a Mask file. The -g readback option generates a readback bit file, and the -g persist:yes option keeps the SelectMAP interface active after configuration. For more information on BitGen options, see Appendix A, "BitGen and PROMGen Switches and Options." Readback When Using Boundary Scan Regular Readback Flow It is highly recommended to perform shutdown before reading back bitstream to ensure normal operation. The Shutdown Sequence can be executed by loading the JSHUTDOWN instruction and spending at least 12 TCK cycles in RTI TAP controller state. CRC_ERROR status and configuration error (CFGERR) must be cleared after readback by issuing Reset CRC bitstream command or writing the correct CRC value to CRC register. 442 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Readback START Load JSHUTDWN Load JSTART RTI minimum 12 TCK cycle RTI minimum 12 TCK cycle Load CFG_IN Go to Test-Logic-Reset Load Readback bitstream command STOP Load CFG_OUT Shift out readback data Load CFG_IN Load Reset CRC bitstream command UG002_c4_36_091900 Figure 3-36: Regular Readback Flow IEEE 1532 Readback Flow In IEEE 1532 readback mode, full chip shutdown is performed when ISC_ENABLE is executed. At the end of readback, CRC Error status must be cleared by issuing Reset CRC command or writing the correct CRC value to CRC register. ISC_DISABLE cannot be executed correctly unless the CRC error status is cleared. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 443 R Chapter 3: Configuration START A Load ISC_ENABLE Load ISC_READ Load 00000? RTI 1 TCK cycles RTI minimum 12 TCK cycles Shift 69 bits of readback data + status Load ISC_PROGRAM No Load 64 bits of bitstream data End of Data Yes Load ISC_PROGRAM RTI 1 TCK cycles Load Reset CRC command No End of bitstream Load ISC_DISABLE Yes A RTI minimum 12 TCK cycles Go to Test-Logic-Reset STOP UG002_c4_39_092100 Figure 3-37: 444 IEEE 1532 Readback Flow www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Readback Using ChipScope Pro The ChipScope Pro on-chip verification tool is sold separately through an authorized Xilinx distributor or over the Xilinx web site. This program uses a combination of PC software and instantiated soft cores to capture states of internal signals. Communication is accomplished via the JTAG USER1 or USER2 scan chain using a Xilinx communication cable. The initial release of ChipScope Pro supports only Virtex-II and Virtex-II Pro devices and allows for internal debug of any internal user logic. ChipScope Pro also allows direct, on-chip debug of the CoreConnect bus in Virtex-II Pro devices. ChipScope Pro supports a high speed USB interface between a host computer and the Virtex-II Pro device using the Xilinx MultiLINX cable on Windows 98/2000 platforms and the RS232 connection using the Xilinx JTAG cable on Windows 98/2000/NT platforms. Solaris 2.7 and 2.8 support is available for core generation and core insertion only. More details are available on the www.xilinx.com/chipscope web site. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 445 R 446 Chapter 3: Configuration www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Chapter 4 PCB Design Considerations Summary This chapter covers the following topics: * * * * * * * * * * Pinout Information Pinout Diagrams Package Specifications Flip-Chip Packages Thermal Data Printed Circuit Board Considerations Board Routability Guidelines XPower IBIS Models BSDL and Boundary Scan Models Pinout Information Introduction This section describes the pinouts for Virtex-II Pro devices in the following packages: * * * FG256 and FG456: wire-bond fine-pitch BGA of 1.00 mm pitch FF672, FF896, FF1152, and FF1517: flip-chip fine-pitch BGA of 1.00 mm pitch BF957: flip-chip BGA of 1.27 mm pitch All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Pins that are not available for the smaller devices are listed in the "No Connects" column. Each device is split into eight I/O banks to allow for flexibility in the choice of I/O standards (see the Virtex-II Pro Data Sheet). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table 4-2 provides definitions for all pin types. The FG256 pinout (Table 4-3, page 451) is included as an example. All Virtex-II Pro pinout tables are available on the distribution CD-ROM, or on the web (at http://www.xilinx.com). Table 4-1 shows the number of 3.3V SelectI/Os in each bank and the total for each device/package combination. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 447 R Table 4-1: Chapter 4: PCB Design Considerations 3.3V SelectI/O Banks Virtex-II Pro Device Package 2VP2 2VP4 2VP7 Bank2 Bank3 FG256 17 18 18 53 FG456 21 18 18 57 FF672 27 24 24 75 FG256 17 17 17 51 FG456 21 40 42 103 FF672 27 60 60 147 FG456 21 40 42 103 FF672 39 60 60 159 FF896 39 60 60 159 2VP20 57 FF896 2VP50 Bank4 Bank5 57 55 Bank6 Bank7 Total 3.3V I/O Bank1 BF957 Bank0 114 84 139 FF1152 57 57 114 BF957 59 59 118 FF1152 69 69 138 FF1517 81 81 162 Pin Definitions Table 4-2 provides a description of each pin type listed in Virtex-II Pro pinout tables. Table 4-2: Virtex-II Pro Pin Definitions Pin Name Direction Description Input/Output All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS, BLVDS, or LDT pairs. Each user I/O is labeled "IO_LXXY_#", where: IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the positive and negative sides of the differential pair. # indicates the bank number (0 through 7) User I/O Pins IO_LXXY_# Dual-Function Pins IO_LXXY_#/ZZZ 448 The dual-function pins are labelled "IO_LXXY_#/ZZZ", where ZZZ can be one of the following pins: Per Bank - VRP, VRN, or VREF Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 - D7, RDWR_B, or CS_B www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Information Table 4-2: Virtex-II Pro Pin Definitions (Continued) Pin Name Direction Description Input/Output In SelectMAP mode, D0 through D7 are configuration data pins. These pins become user I/Os after configuration, unless the SelectMAP port is retained. With /ZZZ: DIN / D0, D1, D2, D3, D4, D5, D6, D7 In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after configuration. CS_B Input In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. RDWR_B Input In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. BUSY/DOUT Output In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The pin becomes a user I/O after configuration, unless the SelectMAP port is retained. In bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. INIT_B Bidirectional (open-drain) When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. The pin becomes a user I/O after configuration. GCLKx (S/P) Input These are clock input pins that connect to Global Clock Buffers. These pins become regular user I/Os when not needed for clocks. VRP Input This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled low with reference resistor). VRN Input This pin is for the DCI voltage reference resistor of N transistor (per bank, to be pulled low with reference resistor). ALT_VRP Input This is the alternative pin for the DCI voltage reference resistor of P transistor. ALT_VRN Input This is the alternative pin for the DCI voltage reference resistor of N transistor. VREF Input These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank). CCLK Input/Output Configuration clock. Output in Master mode or Input in Slave mode. PROG_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor. DONE Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the startup sequence. Dedicated Pins (1) UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 449 R Table 4-2: Chapter 4: PCB Design Considerations Virtex-II Pro Pin Definitions (Continued) Pin Name Direction Description M2, M1, M0 Input Configuration mode selection. HSWAP_EN Input Enable I/O pullups during configuration. TCK Input Boundary Scan Clock. TDI Input Boundary Scan Data Input. TDO Output Boundary Scan Data Output. TMS Input Boundary Scan Mode Select. PWRDWN_B Input Power down pin. DXN, DXP N/A Temperature-sensing diode pins (Anode: DXP, Cathode: DXN). VBATT Input Decryptor key memory backup supply. (Do not connect if battery is not used.) RSVD N/A Reserved pin - do not connect. VCCO Input Power-supply pins for the output drivers (per bank). VCCAUX Input Power-supply pins for auxiliary circuits. VCCINT Input Power-supply pins for the internal core logic. GND Input Ground. AVCCAUXRX# Input Analog power supply for receive circuitry of the multi gigabit transceiver (2.5V). AVCCAUXTX# Input Analog power supply for transmit circuitry of the multi gigabit transceiver (2.5V). VTRXPAD# Input Receive termination supply for the multi gigabit transceiver (1.8V to 2.8V). VTTXPAD# Input Transmit termination supply for the multi gigabit transceiver (1.8V to 2.8V). GNDA# Input Ground for the analog circuitry of the multi gigabit transceiver. RXPPAD# Output Positive differential receive port of the multi gigabit transceiver. RXNPAD# Output Negative differential receive port of the multi gigabit transceiver. TXPPAD# Input Positive differential transmit port of the multi gigabit transceiver. TXNPAD# Input Negitive differential transmit port of the multi gigabit transceiver. Other Pins Notes: 1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage). 450 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Information FG256 Fine-Pitch BGA Package As shown in Table 4-3, XC2VP2 and XC2VP4 Virtex-II Pro devices are available in the FG256 fine-pitch BGA package. The pins in each of these devices are identical. The FG256 pinout information (Table 4-3) is included as an example. All Virtex-II Pro pinout tables are available on the distribution CD-ROM, or on the web (at www.xilinx.com). Table 4-3: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 0 IO_L01N_0/VRP_0 C2 0 IO_L01P_0/VRN_0 C3 0 IO_L02N_0 B3 0 IO_L02P_0 C4 0 IO_L03N_0 A2 0 IO_L03P_0/VREF_0 A3 0 IO_L06N_0 D5 0 IO_L06P_0 C5 0 IO_L07P_0 D6 0 IO_L09N_0 E6 0 IO_L09P_0/VREF_0 E7 0 IO_L69N_0 D7 0 IO_L69P_0/VREF_0 C7 0 IO_L74N_0/GCLK7P D8 0 IO_L74P_0/GCLK6S C8 0 IO_L75N_0/GCLK5P B8 0 IO_L75P_0/GCLK4S A8 1 IO_L75N_1/GCLK3P A9 1 IO_L75P_1/GCLK2S B9 1 IO_L74N_1/GCLK1P C9 1 IO_L74P_1/GCLK0S D9 1 IO_L69N_1/VREF_1 C10 1 IO_L69P_1 D10 1 IO_L09N_1/VREF_1 E10 1 IO_L09P_1 E11 1 IO_L07N_1 D11 1 IO_L06N_1 C12 1 IO_L06P_1 D12 1 IO_L03N_1/VREF_1 A14 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 451 R Table 4-3: 452 Chapter 4: PCB Design Considerations FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 1 IO_L03P_1 A15 1 IO_L02N_1 C13 1 IO_L02P_1 B14 1 IO_L01N_1/VRP_1 C14 1 IO_L01P_1/VRN_1 C15 2 IO_L01N_2/VRP_2 E14 2 IO_L01P_2/VRN_2 E15 2 IO_L02N_2 E13 2 IO_L02P_2 F12 2 IO_L03N_2 F13 2 IO_L03P_2 F14 2 IO_L04N_2/VREF_2 F15 2 IO_L04P_2 F16 2 IO_L06N_2 G13 2 IO_L06P_2 G14 2 IO_L85N_2 G15 2 IO_L85P_2 G16 2 IO_L86N_2 G12 2 IO_L86P_2 H13 2 IO_L88N_2/VREF_2 H14 2 IO_L88P_2 H15 2 IO_L90N_2 H16 2 IO_L90P_2 J16 3 IO_L90N_3 J15 3 IO_L90P_3 J14 3 IO_L89N_3 J13 3 IO_L89P_3 K12 3 IO_L87N_3/VREF_3 K16 3 IO_L87P_3 K15 3 IO_L85N_3 K14 3 IO_L85P_3 K13 3 IO_L06N_3 L16 3 IO_L06P_3 L15 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Information Table 4-3: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 3 IO_L05N_3 L14 3 IO_L05P_3 L13 3 IO_L03N_3/VREF_3 L12 3 IO_L03P_3 M13 3 IO_L02N_3 M16 3 IO_L02P_3 N16 3 IO_L01N_3/VRP_3 M15 3 IO_L01P_3/VRN_3 M14 4 IO_L01N_4/DOUT P15 4 IO_L01P_4/INIT_B P14 4 IO_L02N_4/D0 R14 4 IO_L02P_4/D1 P13 4 IO_L03N_4/D2 T15 4 IO_L03P_4/D3 T14 4 IO_L06N_4/VRP_4 N12 4 IO_L06P_4/VRN_4 P12 4 IO_L07P_4/VREF_4 N11 4 IO_L09N_4 M11 4 IO_L09P_4/VREF_4 M10 4 IO_L69N_4 N10 4 IO_L69P_4/VREF_4 P10 4 IO_L74N_4/GCLK3S N9 4 IO_L74P_4/GCLK2P P9 4 IO_L75N_4/GCLK1S R9 4 IO_L75P_4/GCLK0P T9 5 IO_L75N_5/GCLK7S T8 5 IO_L75P_5/GCLK6P R8 5 IO_L74N_5/GCLK5S P8 5 IO_L74P_5/GCLK4P N8 5 IO_L69N_5/VREF_5 P7 5 IO_L69P_5 N7 5 IO_L09N_5/VREF_5 M7 5 IO_L09P_5 M6 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 453 R Table 4-3: 454 Chapter 4: PCB Design Considerations FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 5 IO_L07N_5/VREF_5 N6 5 IO_L06N_5/VRP_5 P5 5 IO_L06P_5/VRN_5 N5 5 IO_L03N_5/D4 T3 5 IO_L03P_5/D5 T2 5 IO_L02N_5/D6 P4 5 IO_L02P_5/D7 R3 5 IO_L01N_5/RDWR_B P3 5 IO_L01P_5/CS_B P2 6 IO_L01P_6/VRN_6 M3 6 IO_L01N_6/VRP_6 M2 6 IO_L02P_6 N1 6 IO_L02N_6 M1 6 IO_L03P_6 M4 6 IO_L03N_6/VREF_6 L5 6 IO_L05P_6 L4 6 IO_L05N_6 L3 6 IO_L06P_6 L2 6 IO_L06N_6 L1 6 IO_L85P_6 K4 6 IO_L85N_6 K3 6 IO_L87P_6 K2 6 IO_L87N_6/VREF_6 K1 6 IO_L89P_6 K5 6 IO_L89N_6 J4 6 IO_L90P_6 J3 6 IO_L90N_6 J2 7 IO_L90P_7 J1 7 IO_L90N_7 H1 7 IO_L88P_7 H2 7 IO_L88N_7/VREF_7 H3 7 IO_L86P_7 H4 7 IO_L86N_7 G5 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Information Table 4-3: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 7 IO_L85P_7 G1 7 IO_L85N_7 G2 7 IO_L06P_7 G3 7 IO_L06N_7 G4 7 IO_L04P_7 F1 7 IO_L04N_7/VREF_7 F2 7 IO_L03P_7 F3 7 IO_L03N_7 F4 7 IO_L02P_7 F5 7 IO_L02N_7 E4 7 IO_L01P_7/VRN_7 E2 7 IO_L01N_7/VRP_7 E3 0 VCCO_0 F8 0 VCCO_0 F7 0 VCCO_0 E8 1 VCCO_1 F9 1 VCCO_1 F10 1 VCCO_1 E9 2 VCCO_2 H12 2 VCCO_2 H11 2 VCCO_2 G11 3 VCCO_3 K11 3 VCCO_3 J12 3 VCCO_3 J11 4 VCCO_4 M9 4 VCCO_4 L9 4 VCCO_4 L10 5 VCCO_5 M8 5 VCCO_5 L8 5 VCCO_5 L7 6 VCCO_6 K6 6 VCCO_6 J6 6 VCCO_6 J5 7 VCCO_7 H6 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 455 R Table 4-3: 456 Chapter 4: PCB Design Considerations FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number 7 VCCO_7 H5 7 VCCO_7 G6 N/A CCLK N15 N/A PROG_B D1 N/A DONE P16 N/A M0 N3 N/A M1 N2 N/A M2 P1 N/A TCK D16 N/A TDI E1 N/A TDO E16 N/A TMS C16 N/A PWRDWN_B N14 N/A HSWAP_EN C1 N/A RSVD D14 N/A VBATT D15 N/A DXP D2 N/A DXN D3 N/A AVCCAUXTX6 B5 N/A VTTXPAD6 B4 N/A TXNPAD6 A4 N/A TXPPAD6 A5 N/A GNDA6 C6 N/A GNDA6 C6 N/A RXPPAD6 A6 N/A RXNPAD6 A7 N/A VTRXPAD6 B6 N/A AVCCAUXRX6 B7 N/A AVCCAUXTX7 B11 N/A VTTXPAD7 B10 N/A TXNPAD7 A10 N/A TXPPAD7 A11 N/A GNDA7 C11 N/A GNDA7 C11 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Information Table 4-3: FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number N/A RXPPAD7 A12 N/A RXNPAD7 A13 N/A VTRXPAD7 B12 N/A AVCCAUXRX7 B13 N/A AVCCAUXRX18 R13 N/A VTRXPAD18 R12 N/A RXNPAD18 T13 N/A RXPPAD18 T12 N/A GNDA18 P11 N/A GNDA18 P11 N/A TXPPAD18 T11 N/A TXNPAD18 T10 N/A VTTXPAD18 R10 N/A AVCCAUXTX18 R11 N/A AVCCAUXRX19 R7 N/A VTRXPAD19 R6 N/A RXNPAD19 T7 N/A RXPPAD19 T6 N/A GNDA19 P6 N/A GNDA19 P6 N/A TXPPAD19 T5 N/A TXNPAD19 T4 N/A VTTXPAD19 R4 N/A AVCCAUXTX19 R5 N/A VCCINT N4 N/A VCCINT N13 N/A VCCINT M5 N/A VCCINT M12 N/A VCCINT E5 N/A VCCINT E12 N/A VCCINT D4 N/A VCCINT D13 N/A VCCAUX R16 N/A VCCAUX R1 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 457 R Table 4-3: 458 Chapter 4: PCB Design Considerations FG256 -- XC2VP2 and XC2VP4 Bank Pin Description Pin Number N/A VCCAUX B16 N/A VCCAUX B1 N/A GND T16 N/A GND T1 N/A GND R2 N/A GND R15 N/A GND L6 N/A GND L11 N/A GND K9 N/A GND K8 N/A GND K7 N/A GND K10 N/A GND J9 N/A GND J8 N/A GND J7 N/A GND J10 N/A GND H9 N/A GND H8 N/A GND H7 N/A GND H10 N/A GND G9 N/A GND G8 N/A GND G7 N/A GND G10 N/A GND F6 N/A GND F11 N/A GND B2 N/A GND B15 N/A GND A16 N/A GND A1 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams Pinout Diagrams This section contains pinout diagrams for the following Virtex-II Pro packages: * * * * * * * FG256 Fine-Pitch BGA Composite Pinout Diagram, page 461 - FG256 Bank Information - FG256 Dedicated Pins FG456 Fine-Pitch BGA Composite Pinout Diagram, page 465 - FG456 Bank Information - FG456 Dedicated Pins FF672 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram, page 469 - FF672 Bank Information - FF672 Dedicated Pins FF896 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram, page 473 - FF896 Bank Information - FF896 Dedicated Pins FF1152 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram, page 477 - FF1152 Bank Information - FF1152 Dedicated Pins FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram, page 481 - FF1517 Bank Information - FF1517 Dedicated Pins BF957 Flip-Chip BGA Composite Pinout Diagram, page 485 - BF957 Bank Information - BF957 Dedicated Pins UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 459 R 460 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FG256 Fine-Pitch BGA Composite Pinout Diagram FG256 - Top View Bank 0 (17 User I/Os) 1 Bank 7 (18 User I/Os) Bank 6 (18 User I/Os) A B C D E F G H J K L M N P R T 2 3 H P A N I 4 5 6 7 Bank 1 (17 User I/Os) 8 9 Y T X S Z 10 12 13 3 IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 16 M K O WC 4 5 6 7 D Z Y T X S 8 9 10 Bank 5 (17 User I/Os) User I/O Pins 15 R Z Y T X S 2 14 Y T X S Z 1 0 2 1 CS_B 11 11 12 13 14 15 A B Bank 2 C D (18 User I/Os) E F G H J K L Bank 3 M (18 User I/Os) N P R T 16 Bank 4 (17 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B VRN VREF Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_108a_111901 Figure 4-1: FG256 Fine-Pitch BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 461 R Chapter 4: PCB Design Considerations FG256 Bank Information FG256 - Top View Bank 0 (17 User I/Os) 1 Bank 7 (18 User I/Os) Bank 6 (18 User I/Os) 2 3 4 5 6 7 Bank 1 (17 User I/Os) 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T A B Bank 2 C D (18 User I/Os) E F G H J K L Bank 3 M (18 User I/Os) N P R T 1 2 3 4 5 6 7 Bank 5 (17 User I/Os) User I/O Pins 8 9 10 11 12 13 14 15 16 Bank 4 (17 User I/Os) Dedicated Pins Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B RDWR_B BUSY/DOUT VCCO INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF ug012_c4_108b_112001 Figure 4-2: 462 FG256 Bank Information Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FG256 Dedicated Pins FG256 - Top View Bank 0 (17 User I/Os) 1 Bank 7 (18 User I/Os) Bank 6 (18 User I/Os) A B C D E F G H J K L M N P R T 2 4 3 H P A N I 5 6 7 Bank 1 (17 User I/Os) 8 9 Y T X S Z 10 11 12 13 1 3 WC Z Y T X S 4 5 6 7 8 9 10 Bank 5 (17 User I/Os) User I/O Pins 16 M K O R Z Y T X S 2 15 Y T X S Z 1 0 2 14 11 12 13 D 14 15 A B Bank 2 C D (18 User I/Os) E F G H J K L Bank 3 M (18 User I/Os) N P R T 16 Bank 4 (17 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_108c_011402 Figure 4-3: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook FG256 Dedicated Pins Diagram www.xilinx.com 1-800-255-7778 463 R 464 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FG456 Fine-Pitch BGA Composite Pinout Diagram FG456 - Top View Bank 0 (21 User I/Os) 1 Bank 7 (40 User I/Os) Bank 6 (42 User I/Os) A B P C D E F G H J K L M N P R T U V W Y AA AB 1 2 3 4 5 6 7 8 9 Bank 1 (21 User I/Os) 10 11 12 13 14 15 16 17 18 19 20 H Y T X S Y T X S A N Z Z I Y T X S Y T X S Z Z R O 1 C Z Z DW Y T X S Y T X S 0 2 Z Z Y T X S Y T X S 2 3 4 5 6 7 8 9 Bank 5 (21 User I/Os) User I/O Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B 10 11 12 13 14 15 16 17 18 CCLK P PROG_B D DONE 20 21 22 A K B C D E Bank 2 F (40 User I/Os) G H J K L M N P R T Bank 3 U (42 User I/Os) V W Y AA AB 22 Bank 4 (21 User I/Os) Dedicated Pins C 19 21 M 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B VRN VREF No Pair Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_109a_110801 Figure 4-4: FG456 Fine-Pitch BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 465 R Chapter 4: PCB Design Considerations FG456 Bank Information FG456 - Top View Bank 0 (21 User I/Os) 1 Bank 7 (40 User I/Os) Bank 6 (42 User I/Os) 2 3 4 5 6 7 8 9 Bank 1 (21 User I/Os) 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J K L M N P R T U V W Y AA AB 20 21 22 A B C D E Bank 2 F (40 User I/Os) G H J K L M N P R T Bank 3 U (42 User I/Os) V W Y AA AB C 1 2 3 4 5 6 7 8 9 Bank 5 (21 User I/Os) User I/O Pins 10 11 12 13 14 15 16 17 18 19 20 21 22 Bank 4 (21 User I/Os) Dedicated Pins Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B VCCO RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair ug012_c4_109b_111501 Figure 4-5: 466 FG456 Bank Information Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FG456 Dedicated Pins FG456 - Top View Bank 0 (21 User I/Os) 1 Bank 7 (40 User I/Os) Bank 6 (42 User I/Os) 2 3 4 5 6 7 8 9 Bank 1 (21 User I/Os) 10 11 12 13 14 15 16 17 18 19 20 21 M 22 H A Y T X S Y T X S Y T X S Y T X S K B P A N Z Z Z R Z C O I D E F G H J K L M N P R T U V 1 C W 0 2 Z Z Z Z DW Y Y T X S Y T X S Y T X S Y T X S AA AB 2 4 6 8 10 12 14 16 18 20 22 1 3 5 7 9 11 13 15 17 19 21 Bank 5 (21 User I/Os) User I/O Pins A B C D E Bank 2 F (40 User I/Os) G H J K L M N P R T Bank 3 U (42 User I/Os) V W Y AA AB Bank 4 (21 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_109c_111501 Figure 4-6: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook FG456 Dedicated Pins Diagram www.xilinx.com 1-800-255-7778 467 R 468 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF672 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram FF672 - Top View Bank 1 (39 User I/Os) 2 4 6 1 3 5 A S X T B Z C R D E n n n n F G H J Bank 2 K (60 User I/Os) L M N P R T U V W Y Bank 3 n n n n AA (60 User I/Os) AB n n D W AC Z AD S X T AE AF 2 4 6 1 3 5 7 8 9 10 Bank 0 (39 User I/Os) 11 12 13 14 15 16 17 IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 S X T Y Z S X T Y Z 20 21 22 23 24 25 26 S X T Y Z P H n n n n A Bank 5 (39 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B CS_B 19 A B C D E F M G N K O H I J Bank 7 K (60 User I/Os) L M N P R T U V 1 W C Y Bank 6 n n n n AA n n AB (60 User I/Os) 2 0 AC AD Z Z Z AE Y S X T Y S X T Y S X T Y AF 8 10 12 14 16 18 20 22 24 26 7 9 11 13 15 17 19 21 23 25 Y Bank 4 (39 User I/Os) User I/O Pins 18 VRN VREF No_Pair Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_110a_110201 Figure 4-7: FF672 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 469 R Chapter 4: PCB Design Considerations FF672 Bank Information FF672 - Top View Bank 1 (39 User I/Os) 1 2 4 3 5 6 A B C D E F G H J Bank 2 K (60 User I/Os) L M N P R T U V W Y Bank 3 AA (60 User I/Os) AB AC AD AE AF 7 8 9 10 Bank 0 (39 User I/Os) 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J Bank 7 K (60 User I/Os) L M N P R T U V W Y Bank 6 AA AB (60 User I/Os) AC AD AE AF C 1 2 3 4 5 6 7 8 9 10 11 Bank 4 (39 User I/Os) User I/O Pins 12 13 14 15 16 17 18 19 20 21 22 23 Bank 5 (39 User I/Os) Dedicated Pins 24 25 26 Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B VCCO RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No_Pair ug012_c4_110b_110501 Figure 4-8: 470 FF672 Bank Information Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF672 Dedicated Pins FF672 - Top View Bank 1 (39 User I/Os) 2 4 6 1 3 5 A S X T B Z C R D E n n n n F G H J Bank 2 K (60 User I/Os) L M N P R T U V W Y Bank 3 n n n n AA (60 User I/Os) AB n n D W AC Z AD S X T AE AF 2 4 6 1 3 5 7 8 9 10 Bank 0 (39 User I/Os) 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 A B C D E F M G N K O H I J Bank 7 K (60 User I/Os) L M N P R T U V 1 W C Y Bank 6 n n n n AA n n AB (60 User I/Os) 2 0 AC AD Z Z Z AE Y S X T Y S X T Y S X T Y AF 8 10 12 14 16 18 20 22 24 26 7 9 11 13 15 17 19 21 23 25 Y S X T Y Z S X T Y Z Bank 4 (39 User I/Os) User I/O Pins Figure 4-9: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook 18 S X T Y Z P H n n n n A Bank 5 (39 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_110c_111501 FF672 Dedicated Pins Diagram www.xilinx.com 1-800-255-7778 471 R 472 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF896 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram FF896 - Top View Bank 1 (55 User I/Os) 1 2 3 A B C D E F G Bank 2 H (84 User I/Os) J K L M N P R T U V W Y AA Bank 3 (84 User I/Os) AB AC AD AE AF AG AH AJ AK 4 6 5 7 8 9 10 S X T Y Z R Bank 0 (55 User I/Os) 11 12 13 14 15 16 17 S X T Y Z 18 19 20 21 22 23 S X T Y Z 24 25 26 M P H A C D W 2 1 0 Z S X T Y 3 4 5 6 7 Z S X T Y 8 9 10 11 12 13 14 Z S X T Y 15 16 17 18 19 Bank 4 (55 User I/Os) User I/O Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B 30 A B C D E F G Bank 7 H (84 User I/Os) J K L M N P R T U V W Y AA Bank 6 AB (84 User I/Os) AC AD AE AF AG AH AJ AK 20 Z S X T Y 21 22 23 24 25 26 27 28 29 30 Bank 5 (55 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B VRN VREF No_Pair Figure 4-10: 29 I K 2 28 S X T Y Z N O 1 27 Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_111a_110701 FF896 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 473 R Chapter 4: PCB Design Considerations FF896 Bank Information FF896 - Top View Bank 1 (55 User I/Os) 1 2 3 4 A B C D E F G Bank 2 H (84 User I/Os) J K L M N P R T U V W Y AA Bank 3 (84 User I/Os) AB AC AD AE AF AG AH AJ AK 6 5 7 8 9 10 Bank 0 (55 User I/Os) 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G Bank 7 H (84 User I/Os) J K L M N P R T U V W Y AA Bank 6 AB (84 User I/Os) AC AD AE AF AG AH AJ AK O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bank 4 (55 User I/Os) User I/O Pins 20 21 22 23 24 25 26 27 28 29 30 Bank 5 (55 User I/Os) Dedicated Pins Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B VCCO RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No_Pair ug012_c4_111b_011402 Figure 4-11: FF896 Bank Information Diagram 474 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF896 Dedicated Pins FF896 - Top View Bank 1 (55 User I/Os) 1 2 3 A B C D E F G Bank 2 H (84 User I/Os) J K L M N P R T U V W Y AA Bank 3 (84 User I/Os) AB AC AD AE AF AG AH AJ AK 4 5 6 7 8 9 10 S X T Y Z R Bank 0 (55 User I/Os) 11 12 13 14 15 16 17 S X T Y Z 18 19 20 21 22 23 S X T Y Z 24 25 26 27 28 29 30 A B C D E F G Bank 7 H (84 User I/Os) J K L M N P R T U V W Y AA Bank 6 AB (84 User I/Os) AC AD AE AF AG AH AJ AK S X T Y Z N O K M P H A C D W 2 1 0 Z S X T Y 1 2 3 4 5 6 7 Z S X T Y 8 9 10 11 12 13 14 Z S X T Y 15 16 17 18 19 Bank 4 (55 User I/Os) User I/O Pins 20 Z S X T Y 21 22 23 24 25 26 27 28 29 30 Bank 5 (55 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_111c_111501 Figure 4-12: FF896 Dedicated Pins Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 475 R 476 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF1152 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram Bank 1 (69 User I/Os) 1 A B C D E F G H J K Bank 2 (104 User I/Os) L M N P R T U V W Y AA AB AC Bank 3 AD (104 User I/Os) AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 FF1152 - Top View 14 15 16 17 18 19 20 Bank 0 (69 User I/Os) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K Bank 7 L (104 User I/Os) M N P R T U V W Y AA AB AC Bank 6 AD (104 User I/Os) AE AF AG AH AJ AK AL AM AN AP S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y Z Z Z Z Z Z Z Z R N O I K M P HA C D W 2 1 0 Z Z Z Z Z Z Z Z SX T Y S X T Y S XT Y S X T Y S X T Y S X T Y S X T Y S X T Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Bank 4 (69 User I/Os) User I/O Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B 23 24 25 26 27 28 29 30 31 32 33 34 Bank 5 (69 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B VRN VREF No Pair Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_112a_110701 Figure 4-13: FF1152 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 477 R Chapter 4: PCB Design Considerations FF1152 Bank Information Bank 1 (69 User I/Os) 1 2 3 4 5 6 7 8 9 10 11 12 13 FF1152 - Top View 14 15 16 17 18 19 20 Bank 0 (69 User I/Os) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K Bank 2 (104 User I/Os) L M N P R T U V W Y AA AB AC Bank 3 AD (104 User I/Os) AE AF AG AH AJ AK AL AM AN AP A B C D E F G H J K Bank 7 L (104 User I/Os) M N P R T U V W Y AA AB AC Bank 6 AD (104 User I/Os) AE AF AG AH AJ AK AL AM AN AP 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Bank 4 (69 User I/Os) User I/O Pins 22 23 24 25 26 27 28 29 30 31 32 33 34 Bank 5 (69 User I/Os) Dedicated Pins Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B VCCO RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair ug012_c4_112b_110701 Figure 4-14: 478 FF1152 Bank Information Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF1152 Dedicated Pins Bank 1 (69 User I/Os) 1 A B C D E F G H J K Bank 2 (104 User I/Os) L M N P R T U V W Y AA AB AC Bank 3 AD (104 User I/Os) AE AF AG AH AJ AK AL AM AN AP 2 3 4 5 6 7 8 9 10 11 12 13 FF1152 - Top View 14 15 16 17 18 19 20 Bank 0 (69 User I/Os) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G H J K Bank 7 L (104 User I/Os) M N P R T U V W Y AA AB AC Bank 6 AD (104 User I/Os) AE AF AG AH AJ AK AL AM AN AP S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y Z Z Z Z Z Z Z Z R N O I K M P HA C D W 2 1 0 Z Z Z Z Z Z Z Z S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y S X T Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Bank 4 (69 User I/Os) User I/O Pins Figure 4-15: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook 23 24 25 26 27 28 29 30 31 32 33 34 Bank 5 (69 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_112c_011402 FF1152 Dedicated Pins Diagram www.xilinx.com 1-800-255-7778 479 R 480 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram FF1517 - Top View Bank 0 Bank 1 (80 User I/Os) 1 Bank 2 (132 User I/Os) Bank 3 (132 User I/Os) 2 3 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 4 5 6 7 8 9 10 11 12 13 14 15 (80 User I/Os) 16 17 18 19 20 S X T Y S X T Y S X T Y S X T Y Z n Z Z Z MR K O 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J Bank 7 K (132 L User I/Os) M N P R T U V W Y AA AB AC Bank 6 AD (132 AE User I/Os) AF AG AH AJ AK AL AM AN AP AR AT AU AV AW S X T Y S X T Y S X T Y S X T Y n Z Z Z Z N H P I n n A n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n D n 2 n n n 0 1 n Z Z Z Z S X T Y S X T Y S X T Y S X T Y CW Z n Z Z Z S X T Y S X T Y S X T Y S X T Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bank 4 (80 User I/Os) User I/O Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Bank 5 (80 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B VRN VREF No Pair Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_107a_011402 Figure 4-16: FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 481 R Chapter 4: PCB Design Considerations FF1517 Bank Information FF1517 - Top View Bank 0 Bank 1 (80 User I/Os) 1 Bank 2 (132 User I/Os) Bank 3 (132 User I/Os) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (80 User I/Os) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW A B C D E F G H J Bank 7 K (132 L User I/Os) M N P R T U V W Y AA AB Bank 6 AC AD (132 AE User I/Os) AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bank 4 (80 User I/Os) User I/O Pins 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Bank 5 (80 User I/Os) Dedicated Pins Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B VCCO RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair ug012_c4_107b_011402` Figure 4-17: 482 FF1517 Bank Information Diagram www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams FF1517 Dedicated Pins FF1517 - Top View Bank 0 Bank 1 (80 User I/Os) 1 Bank 2 (132 User I/Os) Bank 3 (132 User I/Os) 2 3 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW 4 5 6 7 8 9 10 11 12 13 14 15 (80 User I/Os) 16 17 18 19 20 S X T Y S X T Y S X T Y S X T Y Z n Z Z Z MR K O 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A B C D E F G H J Bank 7 K (132 L User I/Os) M N P R T U V W Y AA AB AC Bank 6 AD (132 AE User I/Os) AF AG AH AJ AK AL AM AN AP AR AT AU AV AW S X T Y S X T Y S X T Y S X T Y n Z Z Z Z N H P I n n A n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n D n 2 n n n 0 1 n Z Z Z Z S X T Y S X T Y S X T Y S X T Y CW Z n Z Z Z S X T Y S X T Y S X T Y S X T Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bank 4 (80 User I/Os) User I/O Pins Figure 4-18: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Bank 5 (80 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_107C_011402 FF1517 Dedicated Pins Diagram www.xilinx.com 1-800-255-7778 483 R 484 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams BF957 Flip-Chip BGA Composite Pinout Diagram BF957 - Top View Bank 1 (59 User I/Os) 1 2 3 A B C D E F G H J Bank 2 (86 User I/Os) K L M N P R T U V W Y AA AB Bank 3 AC (88 User I/Os) AD AE AF AG AH AJ AK AL 4 5 6 7 8 9 10 11 Bank 0 (59 User I/Os) 12 13 14 15 16 17 S X T Y S X T Y S X T Y Z Z Z R 18 19 20 21 22 23 24 3 5 4 P C 1 7 6 27 28 29 30 31 A B C D E F G H J Bank 7 K (86 User I/Os) L M N P R T U V W Y AA AB Bank 6 AC AD (88 User I/Os) AE AF AG AH AJ AK AL H I K 2 0 Z Z Z S X T Y S X T Y S X T Y WD Z Z Z S X T Y S X T Y S X T Y 2 26 S X T Y S X T Y S X T Y Z Z Z N A OM 1 25 9 8 11 10 13 12 15 14 17 16 19 18 21 20 Bank 4 (59 User I/Os) User I/O Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B 23 22 25 24 27 26 29 28 31 30 Bank 5 (59 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 RDWR_B H HSWAP_EN BUSY/DOUT K TCK INIT_B I TDI GCLKx (P) O TDO GCLKx (S) M TMS VRP W PWRDWN_B VRN VREF No Pair Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCO VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_113a_110801 Figure 4-19: BF957 Flip-Chip BGA Composite Pinout Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 485 R Chapter 4: PCB Design Considerations BF957 Bank Information BF957 - Top View Bank 1 (59 User I/Os) 1 2 4 A B C D E F G H J Bank 2 (86 User I/Os) K L M N P R T U V W Y AA AB Bank 3 AC (88 User I/Os) AD AE AF AG AH AJ AK AL 6 8 10 Bank 0 (59 User I/Os) 12 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A B C D E F G H J Bank 7 K (86 User I/Os) L M N P R T U V W Y AA AB Bank 6 AC AD (88 User I/Os) AE AF AG AH AJ AK AL 1 C WD 1 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 Bank 4 (59 User I/Os) User I/O Pins 23 22 25 24 27 26 29 28 31 30 Bank 5 (59 User I/Os) Dedicated Pins Other Pins IO_LXXY_# Dual-Purpose Pins: DIN/D0-D7 CS_B VCCO RDWR_B BUSY/DOUT INIT_B GCLKx (P) GCLKx (S) VRP VRN VREF No Pair ug012_c4_113b_011402 Figure 4-20: BF957 Bank Information Diagram 486 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pinout Diagrams BF957 Dedicated Pins BF957 - Top View Bank 1 (59 User I/Os) 1 2 3 A B C D E F G H J Bank 2 (86 User I/Os) K L M N P R T U V W Y AA AB Bank 3 AC (88 User I/Os) AD AE AF AG AH AJ AK AL 4 5 6 7 8 9 10 11 Bank 0 (59 User I/Os) 12 13 14 15 16 17 S X T Y S X T Y S X T Y Z Z Z R 18 19 20 21 22 23 24 3 5 4 P C 1 7 6 27 28 29 30 31 A B C D E F G H J Bank 7 K (86 User I/Os) L M N P R T U V W Y AA AB Bank 6 AC AD (88 User I/Os) AE AF AG AH AJ AK AL H I K 2 0 Z Z Z S X T Y S X T Y S X T Y WD Z Z Z S X T Y S X T Y S X T Y 2 26 S X T Y S X T Y S X T Y Z Z Z N A OM 1 25 9 8 11 10 13 12 15 14 17 16 19 18 21 20 Bank 4 (59 User I/Os) User I/O Pins 23 22 25 24 27 26 29 28 31 30 Bank 5 (59 User I/Os) Dedicated Pins C CCLK P PROG_B D DONE 2 1 0 M2, M1, M0 H HSWAP_EN K TCK I TDI O TDO M TMS W PWRDWN_B Other Pins N A R n S T X Y Z DXN DXP VBATT RSVD VCCAUX VCCINT GND NO CONNECT AVCCAUXRX AVCCAUXTX VTRXPAD VTTXPAD GNDA RXPPAD RXNPAD TXPPAD TXNPAD ug012_c4_113c_011402 Figure 4-21: BF957 Dedicated Pins Diagram UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 487 R 488 Chapter 4: PCB Design Considerations www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Package Specifications Package Specifications This section contains specifications for the following Virtex-II Pro packages: * FG256 Fine-Pitch BGA Package (1.00 mm Pitch), page 490 * FG456 Fine-Pitch BGA Package (1.00 mm Pitch), page 491 * FF672 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 492 * FF896 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 493 * FF1152 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 494 * FF1517 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch), page 495 * BF957 Flip-Chip BGA Package (1.27 mm Pitch), page 496 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 489 R Chapter 4: PCB Design Considerations FG256 Fine-Pitch BGA Package (1.00 mm Pitch) Figure 4-22: 490 FG256 Fine-Pitch BGA Package www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Package Specifications FG456 Fine-Pitch BGA Package (1.00 mm Pitch) Figure 4-23: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook FG456 Fine-Pitch BGA Package www.xilinx.com 1-800-255-7778 491 R Chapter 4: PCB Design Considerations FF672 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) Figure 4-24: 492 FF672 Flip-Chip Fine-Pitch BGA Package www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Package Specifications FF896 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) Figure 4-25: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook FF896 Flip-Chip Fine-Pitch BGA Package www.xilinx.com 1-800-255-7778 493 R Chapter 4: PCB Design Considerations FF1152 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) Figure 4-26: 494 FF1152 Flip-Chip Fine-Pitch BGA Package www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Package Specifications FF1517 Flip-Chip Fine-Pitch BGA Package (1.00 mm Pitch) Figure 4-27: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook FF1517 Flip-Chip Fine-Pitch BGA Package www.xilinx.com 1-800-255-7778 495 R Chapter 4: PCB Design Considerations BF957 Flip-Chip BGA Package (1.27 mm Pitch) Figure 4-28: 496 BF957 Flip-Chip BGA Package www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Flip-Chip Packages Flip-Chip Packages As silicon devices become more integrated with smaller feature sizes as well as increased functionality and performance, packaging technology is also evolving to take advantage of these silicon advancements. Flip-chip packaging is the latest packaging option introduced by Xilinx to meet the demand for high I/O count and high performance required by today's advanced applications. Flip-chip packaging interconnect technology replaces peripheral bond pads of traditional wire-bond interconnect technology with area array interconnect at the die/substrate interface. The area array pads contain wettable metallization for solders (either eutectic or highlead), where a controlled amount of solder is deposited either by plating or screenprinting. These parts are then reflowed to yield bumped dies with relatively uniform solder bumps spread over the surface of the device. Unlike traditional packaging in which the die is attached to the substrate face up and the connection is made by using wire, the bumped die in a flip-chip package is flipped over and placed face down, with the conductive bumps connecting directly to the matching metal pads on the ceramic or organic laminate substrate. The solder material at molten stage is self-aligning and produces good joints even if the chip is placed offset on the substrate. Flip-chip packages are assembled on high-density, multi-layer ceramic or organic laminate substrates. Since flip-chip bump pads are in area array configuration, very fine lines and geometry on the substrates are required to be able to successfully route the signals from the die to the periphery of the substrates. Multi-layer build-up structures offer this layout flexibility on flip-chip packages, and they provide improvements in power distribution and signal transmission characteristics. Advantages of Flip-Chip Technology Flip-chip interconnections in combination with the advanced multi-layer laminated substrates provide superior performance over traditional wire-bond packaging. Benefits include: * Easy access to core power/ground and shorter interconnects, resulting in better electrical performance * * * * Better noise control since the inductance of flip-chip interconnect is lower Excellent thermal performance due to direct heatsinking to backside of the die Higher I/O density since bond pads are in area array format Smaller size Thermal Data Thermal Considerations The Virtex-II Pro device is a feature-rich FPGA product based on the high-performance Virtex-II architecture. The product incorporates numerous features such as multiple Rocket I/OTM Multi-Gigabit Transceivers (MGTs), one or more embedded IBM PowerPC processors, high-speed SelectI/OTM technology supporting a variety of I/O standards, onboard digitally controlled impedance (DCI) technology, and much more. In fully configured designs that engage all these features at high clock rates, power consumption can add up quickly. Unlike the features of ASICs or even of microprocessors, the combination of Virtex-II Pro features that will be utilized in an application are not known ahead of time. Therefore, as in previous FPGA devices, it remains challenging to predict the power requirements and resulting thermal management needs of a Virtex-II Pro device in a given package. These UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 497 R Chapter 4: PCB Design Considerations devices, therefore, do not come with a preset thermal solution. The end user's conditions will determine what solutions will be most appropriate. In consideration of the high heatgenerating potential of the Virtex-II Pro devices, package offerings are tailored to include medium and high power capable options that allow external thermal management to meet the application's requirements. Table 4-4 shows thermal resistance parameters for Virtex-II Pro packages. Estimated power consumption capability is given, as well. These values were derived using some typical thermal management assumptions as stated in the table. Table 4-4: Thermal Data for Virtex-II Pro Packages Power With Heatsink Max Power, (Watts) Bare Pkg Theta-SA = 1.5 C/Watt (Watts) Theta-CS = 0.1 C/Watt TA = 50 C TJMAX = 100 C TA = 50 C, TJ = 100 C Package Lead Pitch (mm) Junctionto-Ambient Theta-JA Range, in Air (C/Watt) FG256, 2-4L PCB, 17x17 1.0 16 - 22 2.0 - 5.0 13 2.0 FG456, 4L PCB, 23x23 1.0 15 - 28 1.5 - 2.5 9 2.4 FF672, 4L PCB, 27x27 1.0 11 -16 1.0 - 1.5 5 3.7 16 BF957, 40x40 Flip-Chip 1.27 8 - 13 0.7 - 1.1 3 5.0 22 FF896, 31x31 Flip-Chip 1.0 9 - 14 0.8 - 1.1 4 4.5 21 FF1152, 35x35 Flip-Chip 1.0 8 - 13 0.8 - 1.1 4 4.5 21 FF1517, 40x40 Flip-Chip 1.0 8 - 12 0.7 - 1.1 3 5.0 22 Junction-to-Case Junction-to-Board Theta-JC Psi-JB ("Theta-JB") Range, Cold Plate Typical (C/Watt) (C/Watt) : JA (Theta-JA): Thermal resistance, junction-to-ambient (Xilinx-supplied) JC (Theta-JC): Thermal resistance, junction-to-case (use with ratio of heat through the top) JB (Psi-JB, or "Theta-JB"): Thermal resistance in still air, junction-to-board SA (Theta-SA): Thermal resistance, heatsink (manufacturer-supplied) CS (Theta-CS): Thermal resistance, heatsink adhesive (manufacturer-supplied) Virtex-II Pro packages can be grouped into three broad performance categories: low, medium, and high, based on their power handling capabilities. All of the packages can use external thermal enhancements, which can range from simple airflow to schemes that can include passive as well as active heatsinks. This is particularly true for high-performance flip-chip packages where system designers have the option to further enhance the packages to handle in excess of 20 watts, with arrangements that take system physical constraints into consideration. Table 4-5 shows simple but incremental power management schemes that can be brought to bear on flip-chip packages. Table 4-5: Virtex-II Pro Flip-Chip Thermal Management Power Technique Description Low End (1 - 6 watts) Bare package with moderate air 8 - 12 C/Watt Bare package. Package can be used with moderate airflow within a system. Mid Range (4 - 10 watts) Passive heatsink with air 5 - 10 C/Watt Package is used with various forms of passive heatsinks and heat spreader techniques. High End (8 - 25 watts) Active heatsink 2 - 3 C/Watt or better Package is used with active heatsinks, TEC, and boardlevel heat spreader techniques Thermal Management Options The following are thermal management options to consider: 498 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Printed Circuit Board Considerations * For moderate power dissipation (2 to 6 watts), the use of passive heatsinks and heatspreaders attached with thermally conductive double-sided tapes or retainers can offer quick thermal solutions. * The use of lightweight finned external passive heatsinks can be effective for dissipating up to 10 watts. The more efficient external heatsinks tend to be tall and heavy. To help protect component joints from bulky heatsink-induced stresses, the use of spring loaded pins or clips that transfer the mounting stress to a circuit board is advisable. The diagonals of some of these heatsinks can be designed with extensions to allow direct connections to the board. * Flip-chip packages: All flip-chip packages are thermally enhanced BGAs with die facing down. They are offered with exposed metal heatsink at the top. These high-end thermal packages lend themselves to the application of external heatsinks (passive or active) for further heat removal efficiency. Again, precaution should be taken to prevent component damage when a bulky heatsink is attached. * Active heatsinks can include a simple heatsink incorporating a mini fan or even a Peltier Thermoelectric Cooler (TECs) with a fan to blow away any heat generated. Any considerations to apply TEC in heat management should require consultation with experts in using the device, since these devices can be reversed and cause damage to the components. Also, condensation can be an issue. * Outside the package itself, the board on which the package sits can have a significant impact on thermal performance. Board designs can be implemented to take advantage of a board's ability to spread heat. The effect of the board is dependent on its size and how it conducts heat. Board size, the level of copper traces on it, and the number of buried copper planes all lower the junction-to-ambient thermal resistance for packages mounted on the board. The junction-to-board thermal resistance for Virtex-II Pro packages are given in Table 4-4. A standard JEDEC type board was used for obtaining the data. Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources - particularly if the board is not cooled effectively. An otherwise cooler component might be heated by other heat contributing components on the board. Printed Circuit Board Considerations Layout Considerations The PC board is no longer just a means to hold ICs in place. At today's high clock rates and fast signal transitions, the PC board performs a vital function in feeding stable supply voltages to the IC and in maintaining signal integrity between devices. VCC and Ground Planes Since CMOS power consumption is dynamic, it is a non-trivial task to assure stable supply voltages at the device pins and to minimize ground differentials. A multi-layer PC board is a must, with four layers for the simplest circuits, 6 to 12 layers for typical boards. Ground and VCC must each be distributed in complete layers with few holes. Slots in these layers would cause an unacceptable inductive voltage drop, when the supply current changes at a rate of 1 A/ns, or even faster. Besides an uninterrupted ground plane, Virtex-II Pro devices require one plane for VCCINT (1.5V) plus one plane for VCCAUX (2.5V). VCCO can be distributed on wide sections of split plane layers. Note that signal traces on adjacent layers should not be routed across these plane splits. Beyond low resistance and inductance, ground and VCC planes combined can also provide a small degree of VCC decoupling. The capacitance between two planes is ~180 pF/inch2 or ~28 pF/cm2, assuming 5mil (0.125 mm) spacing with FR4 epoxy. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 499 R Chapter 4: PCB Design Considerations VCC Decoupling Fast changing ICC transitions must be supplied by local decoupling capacitors, placed very closely to the VCC device pins or balls. These capacitors must have sufficient capacitance to supply ICC for a few nanoseconds, and must have low intrinsic resistance and inductance. X7R or NPO ceramic surface-mounted capacitors of 0.01 to 0.1 F, one per VCC device pin, are appropriate. 0.1 F can supply 1A for 2 ns with a 20 mV voltage droop. 1A * 2 ns = 2 nanocoulomb = 100 nF * 0.02V Low impedance at >100 MHz is important. Some capacitance variation with temperature is acceptable. A series of values of decoupling capacitors are needed in order to supply transient current to the device over all frequency ranges. The highest frequency capacitors should be in the range of 300 pF to 1 nF. The smallest capacitors are the first-line source for ICC, and they must be placed very close to the VCC pins. An inch of copper plane represents an inductance of several nanohenries, defeating the purpose of the decoupling capacitor. Therefore, the highest frequency (smallest value) capacitors should be mounted within 0.4 inches (1 cm) of the VCC and ground pin pair that it is decoupling. On large full-array BGA packages like the FF1152 abd FF1517, following the decoupling guidelines presents implementation challenges. Note that the power and ground balls on these packages are grouped in banks. A subset of the initial line of high-frequency decoupling capacitors should be mounted directly opposite the component on the reverse side of the board and within the apparent boundary of the component. At least one and typically two 0.1 F chipcaps per bank should be used. The balance of the high-frequency bypass requirements can be implemented outside the periphery on these full-array packages. Backing up this local decoupling is one tantalum capacitor of 10 F to 100 F, able to supply multiple amperes for about 100 ns. Finally, each board needs a power-supply decoupling electrolytic capacitor of 1000 F to 10,000 F, able to supply even more current for a portion of the supply switching period. As described below, larger capacitors inevitably have higher series resistance and inductance, which is the reason for the above-mentioned hierarchy of supply decoupling. As a general rule, multiple capacitors in parallel always offer lower resistance and inductance than any single capacitor. Bypass capacitors must have vias (at least two per pad) abutting the pads, or vias in the pads, to provide the lowest inductance connection. Decoupling Capacitors The ideal decoupling capacitor would present a short circuit to ground for all ac signals. A real capacitor combines a given amount of capacitance with unavoidable parasitics, a small series resistance, and inductance. At low frequencies, the composite impedance is capacitive, i.e., it decreases with increasing frequency. At high frequencies, it is inductive and increases with frequency, making the decoupling ineffective. In-between, there is the LC resonant frequency, where the capacitor looks like a small resistor. This is the range where it is most effective. Different technologies provide different trade-offs between desirable features like small size and high capacitance, and undesirable features like series resistance and inductance. Electrolytic and tantalum capacitors offer the largest capacitance in a given physical size, but also have the highest inductance. This makes them useful for decoupling low frequencies and storing large amounts of charge, but useless for high frequency decoupling. Surface-mount ceramic capacitors, on the other hand, offer the lowest inductance and the best high-frequency performance, but offer only a small amount of capacitance, usually less than a microfarad. Figure 4-29 shows the frequency-dependent impedance and resistance of a typical electrolytic capacitor of 1500 F, while Figure 4-30 and Figure 4-31 show the equivalent data for ceramic bypass capacitors of 33,000 pF and 3,300 pF, respectively. Note that the resonant frequency for the small ceramic bypass capacitor at 100 MHz is 10,000 times 500 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Printed Circuit Board Considerations higher than the resonance frequency of the large electrolytic capacitor at 10 KHz. For more technical information on decoupling capacitors, see the manufacturers' websites. Impendance (Ohms) 100 10 1 0.1 0.01 0.01 0.1 10 1 Frequency kHz 100 1000 UG002_C4_014_111400 Figure 4-29: 1500 F Electrolytic Capacitor Frequency Response Curve 10 Impedence (Ohms) 1 0.1 100 Frequency (MHz) 10 1000 UG002_C5_007_101100 Figure 4-30: 33000 pF X7R Component Frequency Response Curve UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 501 R Chapter 4: PCB Design Considerations 10 Impedence (Ohms) 1 0.1 10 1000 100 Frequency (MHz) UG002_C5_011_101100 Figure 4-31: 3300 pF X7R Component Frequency Response Curve Transmission Line Reflections and Terminations A PC board trace must be analyzed as a transmission line. Its series resistance and parallel conductance can generally be ignored, but series inductance and parallel capacitance per unit length are important parameters. Any signal transition (rising or falling edge) travels along the trace at a speed determined by the incremental inductance and capacitance. For an outer-layer trace (air on one side), the propagation delay is 140 ps/inch, or 55 ps/cm. For an inner-layer trace (FR4 with =4.5 on both sides), the propagation delay is 180 ps/inch, or 70 ps/cm. The voltage-to-current ratio at any point along the transmission line is called the characteristic impedance Z0. A field solver, which is available in most signal integrity simulation software, may be used to determine the impedance of a given trace geometry. As a first order approximation, it is determined by w/d, the ratio of trace width w to the distance d above the ground or VCC plane. For an outer layer trace (microstrip), Z0=50 when w = 2d (e.g., w = 12 mil, d = 6 mil), Z0=75 when w = d (e.g., both 6 mil = 0.15 mm). For an inner layer trace between two ground or VCC planes (stripline), Z0=50 when w = 0.6*d ( e.g., w = 5 mil, d = 8 mil ), Z0=75 when w = 0.25*d ( impractical). Most signal traces fall into the range of 40 to 80 . A slow transition treats a short narrow trace as a lumped capacitance of about 2 pF/inch (0.8 pF/cm). However, if the trace is so long or the signal transition so fast that the potential echo from the far end arrives after the end of the transition, then the trace must be analyzed as a transmission line. In this case, the driver sees the trace not as a lumped capacitance, but rather as a pure resistance of Z0. The signal transition then travels along the trace at the speed mentioned above. At any trace-impedance discontinuity all or part of the signal is reflected back to the origin. If the far end is resistively terminated with R=Z0, then there is no reflection. If, however, the end is open, or loaded with only a CMOS input, then the transition doubles in amplitude, and this new wave travels back to the driver, where it may be reflected again, 502 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Printed Circuit Board Considerations resulting in ringing. Such ringing has a serious impact on signal integrity, reduces noise margins, and can lead to malfunction, especially if an asynchronous signal or a clock signal crosses the input threshold voltage unpredictably. Two alternate ways to avoid reflections and ensure signal integrity are parallel termination and series termination. Parallel Termination Reflections from the far end of the transmission line are avoided if the far end is loaded with a resistor equal to Z0. A popular variation uses two resistors, one to VCC, one to ground, as the Thevenin equivalent of Z0. This reduces the load current for one signal level, while increasing it for the other. Parallel termination inherently has some dc power consumption. DCI on-chip tremination may be used to realizze parallel termination schemes. See Figure 4-32. Vcc R = Z0 Z0 Vcc R= 2 x Z 0 Z0 R= 2 x Z 0 ug002_c4_043_111901 Figure 4-32: Parallel Termination Series Termination While parallel termination eliminates reflections, series termination relies on the reflection from the far end to achieve a full-amplitude signal. For series termination, the driver impedance is adjusted to equal Z0, thus driving a half-amplitude signal onto the transmission line. At the unterminated far end, the reflection creates a full-amplitude signal, which then travels back to the driver where it is absorbed, since the output impedance equals Z0. See Figure 4-33. R = Z0 Z0 ug002_c4_44_111400 Figure 4-33: Series Termination Series termination dissipates no dc power, but the half-amplitude round-trip delay signal means that there must be no additional loads along the line. Series termination is ideal (and only meaningful) for single-source-single-destination interconnects. DCI on=chip termination may beused to realize series termination schemes throught he use of controlled impedance drivers. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 503 R Chapter 4: PCB Design Considerations DCI On-Chip Termination Virtex-II Pro devices offer digitally controlled output impedance drivers and digitallycontrolled input termination, thus eliminating the need for any external termination resistors. This feature is extremely valuable with high pin-count, high density packages. These PC board considerations apply to all modern systems with fast current and voltage transitions, irrespective of the actual clock frequency. The designer of relatively slow systems is more likely caught off-guard by the inherent speed of modern CMOS ICs, where di/dt is measured in A/ns, dV/dt is measured in V/ns, and input flip-flops can react to 1 ns pulses, that are invisible on mid-range oscilloscopes. Powerful tools like HyperLynx and other signal integrity analysis tools can be used to analyze signal integrity on the PC board and can often be amortized by one eliminated board-respin. JTAG Configuration and Test Signals Poor signal integrity and limitations of devices in a JTAG scan chain can reduce the maximum JTAG test clock (TCK) rate and reliability of JTAG-based configuration and test procedures. The JTAG TCK and test mode (TMS) signals must be buffered, distributed, and routed with the same care as any clock signal especially for long JTAG scan chains. The devices in a JTAG scan chain should be ordered such that the connections from the TDO of one device to the TDI of the next device are minimized. When high-speed JTAG-based configuration for the Virtex-II Pro devices is required, devices with lower-specified maximum TCK rates should be placed in a separate JTAG scan chain. Crosstalk Crosstalk can happen when two signals are routed closely together. Current through one of the traces creates a magnetic field that induces current on the neighboring trace, or the voltage on the trace couples capacitively to its neighbor. Crosstalk can be accurately modeled with signal integrity software. Two easy-to-remember rules of thumb are: * * Crosstalk falls off with the square of increasing distance between the traces. Crosstalk also falls off with the square of decreasing distance to a ground plane. DV Peak Crosstalk Voltage = -----------------------------1 + ( D H )2 where DV is the voltage swing D is the distance between traces (center to center) H is the spacing above the ground plane Example: 3.3V swing, and two stripline traces 5 mils apart and 5 mils above the ground plane. Peak Crosstalk Voltage = (3.3V)/(1 + (0.005/0.005)2) = 1.65V This can cause a false transition on the neighboring trace. Separating the trace by an additional 5 mils is significantly better: Peak Crosstalk Voltage = (3.3V)/(1 + (0.01/0.005)2) = 0.66V Decoupling of VREF Pins VREF pins must each have a bypass capacitor to insure that no noise is coupled onto the reference. Signal traces must be kept at least three spaces from the reference trace on either side to prevent crosstalk coupling. Signal Routing to and from Package Pins Signal escaping (traces leaving the pin/ball area) can be quite difficult for the large FG and flip-chip packages. The number of signal layers required to escape all the pins depends on 504 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Board Routability Guidelines the PCB design rules. The thinner the traces, the more signals per layer can be routed, and the fewer layers are needed. The thinner traces have higher characteristic impedance, so choose an impedance plan that makes sense, and then be consistent. Traces from 40 to 80 are common. If only one signal can be escaped between two pads, only two rows of pins can be escaped per layer. For FG packages (1.0mm pitch) one signal of width 5 mils (0.13mm) can be escaped between two pads, assuming a space constraint equal to the trace width. For a discussion of signal routing specific to Virtex-II Pro devices, see www.xilinx.com for currently available application notes. As packages are able to handle more I/Os with a minimum increase in size, the signal integrity of those signals must be considered, regardless of clock frequency. Especially with the largest packages, precise PCB layer stackup is required. Parameters such as board material, trace width, pad type, and stackup must be defined based on simulation, and the fabrication drawings must be marked with "precise layer stackup" and the stackup specified. A number of board-level signal integrity simulators exist. Careful attention to PCB design rules creates a robust design with low EMI and high signal reliability. Board Routability Guidelines Board-Level BGA Routing Challenges Xilinx ball grid array (BGA) wire-bond and flip-chip packages contain a matrix of solder balls (see Figure 4-34). These packages are made of multilayer BT substrates. Signal balls are in a perimeter format. Power and ground pins are grouped together appropriately. Power Ground Figure 4-34: Fine-Pitch BGA Pin Assignments The number of layers required for effective routing of these packages is dictated by the layout of balls in each package. If several other technologies and components are already present on the board, the system cost is factored with every added board layer. The intent of a board designer is to optimize the number of layers required to route these packages, considering both cost and performance. This section provides guidelines for minimizing required board layers for routing BGA products using standard PCB technologies (5 mil wide lines and spaces or 6 mil wide lines and spaces). For high performance and other system needs, designers can use premium technologies with finer lines/spaces on the board. The pin assignment and pin grouping scheme in BGA packages enables efficient routing of the board with an optimum number of required board layers. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 505 R Chapter 4: PCB Design Considerations Board Routing Strategy The diameter of a land pad on the component side is provided by Xilinx. This information is required prior to the start of board layout when designing the board pads to match component-side land geometry. Typical values for these land pads are described in Figure 4-35 and summarized in Table 4-6. VL VH W D L M Mask Opening Outside of Land e Non-Solder-Mask-Defined Land Patterns or Land-Defined Land Patterns are recommended for all packages. x157_02_120500 Figure 4-35: Suggested Board Layout of Soldered Pads for BGA Packages Table 4-6: Summary of Typical Land Pad Values (mm) Land Pad Characteristics FG256 FG456 FF672 FF896 FF1152 FF1517 BF957 Component Land Pad Diameter (SMD) (4) 0.45 0.45 0.48 0.48 0.48 0.48 0.61 Solder Land (L) Diameter 0.40 0.40 0.45 0.45 0.45 0.45 0.56 Opening in Solder Mask (M) Diameter 0.50 0.50 0.55 0.55 0.55 0.55 0.66 Solder (Ball) Land Pitch (e) 1.00 1.00 1.00 1.00 1.00 1.00 1.27 Line Width Between Via and Land (w) 0.130 0.130 0.130 0.130 0.130 0.130 0.203 Distance Between Via and Land (D) 0.70 0.70 0.70 0.70 0.70 0.70 0.90 Via Land (VL) Diameter 0.61 0.61 0.61 0.61 0.61 0.61 0.65 Through Hole (VH), Diameter 0.300 0.300 0.300 0.300 0.300 0.300 0.356 Pad Array Full Full Full Full Full Full Full 16 x 16 22 x 22 26 x 26 30 x 30 34 x 34 39 x 39 31 x 31 - - - - - Matrix or External Row Periphery Rows - 7 (3) Notes: 1. Dimensions in millimeters. 2. 3 x 3 matrix for illustration only, one land pad shown with via connection. 3. FG456 package has solder balls in the center in addition to the periphery rows of balls. 4. Component land pad diameter refers to the pad opening on the component side (solder-mask defined). 506 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Board Routability Guidelines For Xilinx BGA packages, NSMD (Non Solder Mask Defined) pads on the board are suggested. This allows a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in Figure 4-35. The space between the NSMD pad and the solder mask, and the actual signal trace widths depends on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller. Selection of the pad types and pad sizes determines the available space between adjacent balls for signal escape. Based on PCB capability, the number of lines that can share the available space is described in Figure 4-36. Based on geometrical considerations, if one signal escapes between adjacent balls, then two signal rows can be routed on a single metal layer. This is illustrated in Figure 4-36, as routing with one line/channel, either at 6 mil lines and spaces or 5 mil lines and spaces. The blocked nature of multi-gigabit transceiver (MGT) at the top edge prevents a direct implementation of one line/channel arrangement in layer 1. Using this suggested routing scheme, a minimum of eight PCB layers are required to route up to 10 signal rows in a package. These Virtex-II Pro BGA packages may incorporate up to 16 MGT channels per package. The balls that make up these channels are grouped within the two outer rows of top and bottom edges. This outer row arrangement allows easy escape and pairing of signals. Accomodation of any filtering schemes off the chip can be accomplished in close proximity as well. A slightly lower trace width than that employed on the top and bottom external or exposed traces can be used by the inner signal rows routed in internal layers. Depending on the signal being handled, the practice of "necking down" a trace in the critical space between the BGA balls is allowable. Changes in width over very short distances can cause small impedance changes. Validate these issues with the board vendor and signal integrity engineers responsible for design. It is also suggested to implement the MGT signals in stripline arrangement. MGT Signal (Top Edge) (L4) 1 2 3 4 5 6 7 PCB DESIGN RULE (1.0 mm BALL PITCH) 8 9 10 11 12 Trace Width/Spacing (mils) I/O Rows Lines Per Channel PCB Layer Ball Pad Via Pad 5/5 8 1 8 .018" .024" A MGT Signal (L4) B 1.0 mm C D Detail "A" E 9.3 mils >5 mils 1.0 mm 5 mils 6 mils 8.8 mils >5 mils F G H J K L M Signal (L1) Signal (L3, L6, L8) 0.30 mm (0.012) PWR Plane GND Plane Legend: 0.61 mm (0.024) I/O GND Detail "A" 1 Line/Channel 5 mils Line / 5 mils Spacing (Standard Technology) PWR VCCINT 0.55 mm (0.022) 1 Line/Channel 6 mils Line / 6 mils Spacing (Standard Technology) 27 x 27 mm, 1.0 mm Fine Pitch BGA V INT 0.45 mm (0.018) UG012_C4_120_011002 Figure 4-36: FF672 PC Board Layout/Land Pattern UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 507 R Chapter 4: PCB Design Considerations Figure 4-36 describes a board-level layout strategy for a Xilinx 1.0 mm pitch FF672 package, which incorporates four MGT channels at the top edge. Detail A in Figure 4-36 describes the opening geometry for the land pad and the solder mask. Routing with 5 mil lines/trace allows one signal per channel (between the balls). For successful routing, eight-row-deep signal traces require six to eight PCB layers. Figure 4-37 shows the suggested schematic of layers for the eight-layer routing scheme. By using a premium board technology such as Microvia Technology--allowing up to 4 mil lines and spaces--efficient routing with a reduced number of board layers is made possible. A grouping scheme for power, ground, control, and I/O pins may also enable efficient routing. Signal (S1) L-1 Power/Gnd L-2 Signal (S2) L-3 Signal (S3 - MGT) L-4 Power/Gnd L-5 Signal (S4) L-6 Power/Gnd L-7 Signal (S5) L-8 ug012_c4_119_010302 Figure 4-37: Eight-Layer Routing Scheme Figure 4-38 and Figure 4-39 show examples of suggested layer-by-layer board escape strategy routing used to implement MGT and LVDS pairs for some of the Virtex-II Pro packages, including flip-chip package FF672. Complete suggested layer-by-layer board escape routing for each Virtex-II Pro package can be found in the Virtex-II Pro section of the www.xilinx.com website. These drawings assume a standard PCB technology of 5 mil wide lines and spaces. More details are contained in XAPP157, which is available on the web at www.xilinx.com/xapp/xapp157.pdf, as is a full-color (PDF) version of this document. 508 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R UG012_C4_122_011002 Board Routability Guidelines Figure 4-38: FG456 Routing with LVDS Pairs UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 509 R UG012_C4_121_011002 Chapter 4: PCB Design Considerations Figure 4-39: FF672 Routing with LVDS Pairs 510 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R XPower XPower XPower is the first graphic power-analysis software available for programmable logic design. Earlier than ever in the design flow you can analyze total device power, power per net, routed, or partially routed or unrouted designs. You can also receive graphical or ASCII-based reports, all driven from a comprehensive graphic interface, or use a command-line driven batch-mode execution. XPower supports Virtex-II Pro and Virtex-II advanced FPGA devices and the XPLA3 family of CPLD devices, offering the broadest device support available in programmable power estimation. XPower also supports the importing of simulation data from ModelSimTM VCD files, greatly reducing the time spent setting up net activity, and increasing overall estimation accuracy. XPower uses device knowledge and design data to project device power and by-net power utilization. This is a significant advance from the static estimation pages most logic providers offer their customers, and it is a leap forward in providing logic designers with accurate power dissipation information. Features include: * * * * * * * * * Support for Virtex-II Pro, Virtex-II, Virtex-E, Virtex, and Spartan-II FPGAs in ISE 4.1i XPLA3 device support through ISE WebPACK 4.1i VCD simulation file import for ModelSimTM Windows 98 and NT, Windows ME and Windows 2000, and Solaris support Graphic and/or ASCII report formats Menu-driven or batch-mode execution Device data read directly from Xilinx layout files Save and recall setup data Recognize small voltage variations on VCC More details are available under the Xpower link on the www.xilinx.com website. IBIS Models The need for higher system performance leads to faster output transitions. Signals with fast transitions cannot be considered purely digital. It is therefore important to understand their analog behavior by signal integrity analysis. To simulate the signal integrity of printed circuit boards (PCB) accurately and solve design problems before the PCB is fabricated, models of the I/O characteristics are required. SPICE models were traditionally used for this purpose, however, a manufacturer's SPICE models contain proprietary circuit-level information. Therefore, there was a need for a model type which does not give details of the circuit topology, or process parameters. One such standard is the I/O Buffer Information Specification (IBIS) format originally suggested by Intel. In the early 1990's, the IBIS Open Forum was formed and the first IBIS specification was written to promote tool independent I/O models for system signal integrity analysis. IBIS is now the ANSI/EIA-656 and IEC 62014-1 standard. IBIS accurately describes the signal behavior of the interconnections without disclosing the actual technology and circuitry used to implement the I/O. The standard is basically a black-box approach to protect proprietary information. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 511 R Chapter 4: PCB Design Considerations Using IBIS Models IBIS models can be used by designers for system-level analysis of signal integrity issues, such as ringing, ground bounce, cross talk, and predicting RFI/EMI. Complete designs can be simulated and evaluated before going through the expensive and time consuming process of producing prototype PCBs. This type of pre-layout simulation can considerably reduce the development cost and time to market, while increasing the reliability of the I/O operation. IBIS models consist of look-up tables that predict the I/V characteristics and dV/dt of integrated circuit inputs and outputs when combined with PCB traces, cables and passive components. The data is extracted for the typical case, minimum case (weak transistors, low VCC, hot temperatures) and maximum case (strong transistors, high VCC, cold temperatures). IBIS models have a limitation in that they do not contain internal delays. IBIS models contain package parasitic information for simulation of ground bounce. However, not all simulators are able to use this data to simulate ground bounce. Simulation results may not agree with measurement results due to package, die, PCB trace and ground plane modeling inaccuracies. Similarly, because simultaneous switching outputs (SSOs) are also difficult to model, only a first approximation is provided to the designer. IBIS Generation IBIS models are generated either from SPICE simulations or from actual device measurements. A SPICE netlist of the I/O buffer is required to produce V/I and dV/dt simulation curve data. The SPICE simulation data is then converted to an IBIS format/syntax file. IBIS models that are derived from measurement data do not have process corner information, unlike IBIS models that are derived from SPICE simulation data. It is only practical to measure a few parts, and it is therefore impossible to represent the extremes of production by such a method. Advantages of IBIS Using IBIS models has a great advantage to the user in that simulation speed is significantly increased over SPICE, while accuracy is only slightly decreased. Nonconvergence, which can be a problem with SPICE models and simulators, is eliminated in IBIS simulation. Virtually all EDA vendors presently support IBIS models and ease of use of these IBIS simulators is generally very good. IBIS models for most devices are freely available over the Internet, making it easy to simulate several different manufacturers devices on the same board. IBIS File Structure An IBIS file contains two sections, the header and the model data for each component. One IBIS file can describe several devices. The following is the contents list in a typical IBIS file: * * * * * * * * 512 IBIS Version File Name File Revision Component Package R/L/C Pin name, model, R/L/C Model (i.e., 3-state) Temperature Range (typical, minimum, and maximum) www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IBIS Models * * * * * * * * Voltage Range (typical, minimum, and maximum) Pull-Up Reference Pull-Down Reference Power Clamp Reference Ground Clamp Reference I/V Tables for: - Pull-Up - Pull-Down - Power Clamp - Ground Clamp Rise and Fall dV/dt for minimum, typical, and maximum conditions (driving 50) Package Model (optional) <package_number>.pkg with RLC sections. IBIS I/V and dV/dt Curves A digital buffer can be measured in receive (3-state) mode and drive mode. IBIS I/V curves are based on the data of both these modes. The transition between modes is achieved by phasing in/out the difference between the driver and the receiver models, while keeping the receiver model constantly in the circuit. The I/V curve range required by the IBIS specification is -VCC to (2xVCC). This wide voltage range exists because the theoretical maximum overshoot due to a full reflection is twice the signal swing. The ground clamp I/V curve must be specified over the range - VCC to VCC, and the power clamp I/V curve must be specified from VCC to (2xVCC). The three supported conditions for the IBIS buffer models are typical values (required), minimum values (optional), and maximum values (optional). For CMOS buffers, the minimum condition is defined as high temperature and low supply voltage, and the maximum condition is defined as low temperature and high supply voltage. An IBIS model of a digital buffer has four I/V curves: * The pull-down I/V curve contains the mode data for the driver driving low. The origin of the curve is at 0V for CMOS buffers. * The pull-up I/V curve contains the mode data for the driver driving high. The origin of the curve is at the supply voltage (VCC or VDD). * The ground clamp I/V curve contains receive (3-state) mode data, with the origin of the curve at 0V for CMOS buffers. * The power clamp I/V curve contains receive (3-state) mode data, with the origin of the curve at the supply voltage (VCC or VDD). For 3.3V buffers that are 5V tolerant, the power clamp is referenced to 5V while the pull-up is referenced to 3.3V. Ramp and dV/dt Curves The Ramp keyword contains information on how fast the pull-up and pull-down transistors turn on/off. The dV/dt curves give the same information, while including the effects of die capacitance (C_comp). C_comp is the total die capacitance as seen at the die pad, excluding the package capacitance. dV/dt curves describe the transient characteristics of a buffer more accurately than ramps. A minimum of four dV/dt curves are required to describe a CMOS buffer: pull-down ON, pull-up OFF, pull-down OFF, and pull-up ON. dV/dt curves incorporate the clock-to-out delay, and the length of the dV/dt curve corresponds to the clock speed at which the buffer is used. Each dV/dt curve has t = 0, where the pulse crosses the input threshold. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 513 R Chapter 4: PCB Design Considerations Xilinx IBIS Package Parasitic Modelling Xilinx IBIS modeling previously used a simple RCL model for the pin and bond wire parasitics. Due to the fast rise and fall times of many of the supported I/O standards, it was deemed necessary to improve the package parasitic modeling. The latest IBIS 3.2 specification has a complex parasitic package model, which incorporates a transmission line and lumped RCL model. Unfortunately, IBIS 3.2 is still not widely supported by simulators. For these reasons, the old lumped package parasitic parameters have been removed from the latest models, and the user should now manually add an external transmission line. A 65 ideal transmission line, with the delay set at 25 ps to 100 ps, is recommended. This works in conjunction with a revised lumped model (included inside the IBIS model). For critical applications, both extremes (25 ps and 100 ps) should be checked. However, for most I/O applications this difference is very small. IBIS Simulations The circuit shown in Figure 4-40 models a Virtex-II Pro LVCMOS_18F driver and receiver, connected by a 6-inch 50 circuit board trace. The rise and fall simulation results show that there is a large amount of overshoot and undershoot, which is actually limited by the IOB clamp diodes. UG012_c4_114_111301 Figure 4-40: Unterminated Example 514 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R IBIS Models By adding a series termination resistor to the driver output, the overshoot and undershoot can be effectively controlled. The simulation results in Figure 4-41 show that by adding a 25 termination there is minimal overshoot and undershoot. UG012_c4_115_111901 Figure 4-41: Series Termination Example An alternative is to use a DCI source impedance controlled driver. The results shown in Figure 4-42 show the waveforms from an LVDCI_18 driver, which has virtually no overshoot or undershoot. UG012_c4_116_111901 Figure 4-42: DCI Driver Example IBIS Simulators Several different IBIS simulators are available today, and each simulator provides different results. An overshoot or undershoot of 10% of the measured result is tolerable. Differences between the model and measurements occur because not all parameters are modeled. Simulators for IBIS models are provided by the following vendors: * * Cadence Avanti Corporation UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 515 R Chapter 4: PCB Design Considerations * * * * * * Hyperlynx Mentor Microsim Intusoft Veribest Viewlogic Xilinx IBIS Advantages Xilinx provides preliminary IBIS files before working silicon has been verified (before tape out), as well as updated versions of IBIS files after the ICs are verified. Preliminary IBIS files are generated from SPICE models before working silicon has been verified. After the IC (device) is verified, appropriate changes are made to the existing IBIS files. These IBIS files are available at the following web site: http://www.xilinx.com/support/sw_ibis.htm IBIS Reference Web Site http://www.eia.org/eig/ibis/ibis.htm BSDL and Boundary Scan Models Boundary scan is a technique that is used to improve the testability of ICs. With Virtex-II Pro devices, registers are placed on I/Os that are connected together as a long shift register. Each register can be used to either save or force the state of the I/O. There are additional registers for accessing test modes. The most common application for boundary scan is testing for continuity of the IC to the board. Some packages make visual inspection of solder joints impossible, e.g. BGA. The large number of I/Os available requires the use of such packages, and also increases the importance of testing. A large number of I/Os also means a long scan chain. Test software is available to support testing with boundary scan. The software requires a description of the boundary scan implementation of the IC. The IEEE 1149.1 specification provides a language description for Boundary Scan Description Language (BSDL). Boundary scan test software accepts BSDL descriptions. The IEEE 1149.1 spec also defines a 4 to 5 pin interface known as the JTAG interface. IEEE 1532 is a capability extension of IEEE 1149.1. BSDL Files Preliminary BSDL files are provided from the IC Design Process. Final BSDL files have been verified by an external third party test and verification vendor. The following are Virtex-II Pro BSDL file names. Virtex-II Pro BSDL File Names 516 XC2VP2_FG256.BSD XC2VP4_FF672.BSD XC2VP20_FF1152.BSD XC2VP2_FG456.BSD XC2VP7_FG456.BSD XC2VP20_BF957.BSD XC2VP2_FF672.BSD XC2VP7_FF672.BSD XC2VP50_FF1152.BSD XC2VP4_FG256.BSD XC2VP7_FF896.BSD XC2VP50_FF1517.BSD XC2VP4_FG456.BSD XC2VP20_FF896.BSD XC2VP50_BF957.BSD www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Appendix A BitGen and PROMGen Switches and Options Using BitGen BitGen produces a bitstream for Xilinx device configuration. After the design has been completely routed, it is necessary to configure the device so that it can execute the desired function. The Xilinx bitstream necessary to configure the device is generated with BitGen. BitGen takes a fully routed NCD (Circuit Description) file as its input and produces a configuration bitstream--a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA memory cells, or it can be used to create a PROM file (see Figure A-1). NCD Circuit Description (Placed/Routed) LL (Optional) BGN BitGen MSK (Optional) DRC BIT RBT PROMGen Hardware Debugger X9227 Figure A-1: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 BitGen 517 R Appendix A: BitGen and PROMGen Switches and Options BitGen Syntax The following syntax creates a bitstream from your NCD file. bitgen [options] infile[.ncd] [outfile] [pcf_file] options is one or more of the options listed in BitGen Options, page 519. Infile is the name of the NCD design for which you want to create the bitstream. You can specify only one design file, and it must be the first file specified on the command line. You do not have to use an extension. If you do not, .ncd is assumed. If you do use an extension, it must be .ncd. Outfile is the name of the output file. If you do not specify an output file name, BitGen creates one in the same directory as the input file. If you specify -l on the command line, the extension is .ll (see -l command line option). If you specify -m (see -m command line option), the extension is .msk. If you specify -b, the extension is .rbt. Otherwise the extension is .bit. If you do not specify an extension, BitGen appends one according to the aforementioned rules. If you do include an extension, it must also conform to the rules. Pcf_file is the name of a physical constraints (PCF) file. BitGen uses this file to determine which nets in the design are critical for tiedown, which is not available for Virtex families. BitGen automatically reads the .pcf file by default. If the physical constraints file is the second file specified on the command line, it must have a .pcf extension. If it is the third file specified, the extension is optional; .pcf is assumed. If a .pcf file name is specified, it must exist, otherwise the input design name with a .pcf extension is read if that file exists. A report file containing all BitGen's output is automatically created under the same directory as the output file. The report file has the same root name as the output file with a .bgn extension. BitGen Files This section describes input files that BitGen requires and output files that BitGen generates. Input Files Input to BitGen consists of the following files. * NCD file--a physical description of the design mapped, placed and routed in the target device. The NCD file must be fully routed. * PCF--an optional user-modifiable ASCII Physical Constraints File. If you specify a PCF file on the BitGen command line, BitGen uses this file to determine which nets in the design are critical for tiedown (not used for Virtex families). Output Files Output from BitGen consists of the following files. 518 * BIT file--a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA memory cells, or it can be used to create a PROM file (see Using PROMGen, page 523). * RBT file--an optional "rawbits" file with an .rbt extension. The rawbits file is ASCII ones and zeros representing the data in the bitstream file. If you enter a -b option on the BitGen command line, an RBT file is produced in addition to the binary BIT file (see -b (Create Rawbits File), page 519). * LL file--an optional ASCII logic allocation file with a .ll extension. The logic allocation file indicates the bitstream position of latches, flip-flops, and IOB inputs and outputs. A .ll file is produced if you enter a -l option on the BitGen command line (-l (Create a www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Using BitGen Logic Allocation File), page 523). * MSK file--an optional mask file with an .msk extension. This file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA. A MSK file is produced if you enter a -m option on the BitGen command line (see -m (Generate a Mask File), page 523). * * BGN file--a report file containing information about the BitGen run. DRC file--a Design Rule Check (DRC) file for the design. A DRC runs and the DRC file is produced unless you enter a -d option on the BitGen command line (see -d (Do Not Run DRC), page 519). BitGen Options Following is a description of command line options and how they affect BitGen behavior. -b (Create Rawbits File) Create a "rawbits" (file_name.rbt) file. The rawbits file consists of ASCII ones and zeros representing the data in the bitstream file. If you are using a microprocessor to configure a single FPGA, you can include the rawbits file in the source code as a text file to represent the configuration data. The sequence of characters in the rawbits file is the same as the sequence of bits written into the FPGA. -d (Do Not Run DRC) Do not run DRC (Design Rule Check). Without the -d option, BitGen runs a DRC and saves the DRC results in two output files: the BitGen report file (file_name.bgn) and the DRC file (file_name.drc). If you enter the -d option, no DRC information appears in the report file and no DRC file is produced. Running DRC before a bitstream is produced detects any errors that could cause the FPGA to malfunction. If DRC does not detect any errors, BitGen produces a bitstream file (unless you use the -j option described in the -j (No BIT File), page 523). -f (Execute Commands File) -f command_file The -f option executes the command line arguments in the specified command_file. -g (Set Configuration) -g option:setting The -g option specifies the startup timing and other bitstream options for Xilinx FPGAs. The settings for the -g option depend on the design's architecture. These options have the following syntax. Compress Enable bitstream compression using multiple frame writes (MFW). Readback This allows the user to perform Readback by the creating the necessary bitstream (.rbb file). CRC Virtex-II allows the user to enable or disable the CRC checking. If CRC checking is disabled, a CBC (Constant Bit Check) is used instead. Settings: Enable, Disable Default: Enable UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 519 R Appendix A: BitGen and PROMGen Switches and Options DebugBitstream This option creates a modified bitstream which loads each frame individually, and places an LOUT write after each, for debugging purposes. This option should be used only in Master or Slave Serial downloads. Settings: Yes, No Default: No ConfigRate Virtex-II devices use an internal oscillator to generate CCLK when configuring in Master SelectMAP or Master Serial modes. This option sets the CCLK rate in MHz. Settings: 4,5,6,7,8,10,13,15,20,26,30,34,41,45,51,55,60,130 Default: 4 StartupClk The last few cycles of configuration is called the startup sequence. The startup sequence can be clocked by CCLK signal, a User clock (connected to the STARTUP block), or TCK (the JTAG clock). Settings: CCLK, UserClk, JTAGClk Default: CCLK PowerdownStatus This options allows the user to choose whether the DONE pin is used as the PowerDown pin after configuration. Settings: Enable, Disable Default: Enable DCMShutdown If the DCMShutdown option is enabled, the DCM resets if the SHUTDOWN and AGHIGH commands are performed. Settings: Enable, Disable Default: Enable CclkPin This option selects an internal pullup on the CCLK pin. Settings: Pullnone, Pullup Default: Pullup DonePin This option selects an internal pullup on the DONE pin. Settings: Pullnone, Pullup Default: Pullup M0Pin This option selects an internal pullup or pulldown on the M0 (Mode 0) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullup M1Pin This option selects an internal pullup or pulldown on the M1 (Mode 1) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullup 520 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Using BitGen M2Pin This option selects an internal pullup or pulldown on the M2 (Mode 2) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullup ProgPin This options selects an internal pullup on the PROGRAM pin. Settings: Pullnone, Pullup Default: Pullup TckPin This option selects an internal pullup or pulldown on the TCK (JTAG Clock) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullup TdiPin This option selects an internal pullup or pulldown on the TDI (JTAG Input) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullup TdoPin This option selects an internal pullup or pulldown on the TDO (JTAG Output) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullnone TmsPin This option selects an internal pullup or pulldown on the TMS (JTAG Mode Select) pin. Settings: Pullnone, Pullup, Pulldown Default: Pullup UnusedPin This option selects an internal pullup or pulldown on all unused I/Os. Settings: Pullnone, Pullup, Pulldown Default: Pulldown GWE_cycle Selects the startup phase that asserts the internal write enable to flip-flops, LUT RAMs, shift registers, and BRAMs. Before the startup phase both BRAM writing and reading are disabled. The Done setting asserts GWE when the DoneIn signal is high. DoneIn is either the value of the DONE pin or a delayed version if DonePipe=Yes. The Keep setting is used to keep the current value of the GWE signal. Settings: 1, 2, 3, 4, 5, 6, Done, Keep Default: 6 GTS_cycle Selects the startup phase that releases the internal 3-state control to the I/O buffers. The Done setting releases GTSA when the DoneIn signal is high. DoneIn is either the value of the DONE pin or a delayed version if DonePipe=Yes. The Keep setting is used to keep the current value of the GTS signal. Settings: 1, 2, 3, 4, 5, 6, Done, Keep Default: 5 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 521 R Appendix A: BitGen and PROMGen Switches and Options LCK_cycle Selects the startup phase to wait until DCM locks are asserted. Settings: 0, 1, 2, 3, 4, 5, 6, NoWait Default: NoWait MATCH_cycle Selects the startup phase to wait until DCI locks are asserted. Settings: 0, 1, 2, 3, 4, 5, 6, NoWait, Auto Default: Auto DONE_cycle Selects the startup phase that activates the FPGA DONE signal. DONE is delayed when DonePipe=Yes. Settings: 1, 2, 3, 4, 5, 6 Default: 4 Persist This option is needed for Readback and Partial Reconfiguration using the configuration pins. If Persist=Yes, all the configuration pins used retain their function. Which configuration pins are persisted is determined by the mode pin settings. If a serial mode is chosen, the persisted pins would be INIT, DOUT, and DIN. If a SelectMAP mode is chosen, the persisted pins would be INIT, BUSY, D0-D7, CS, and WRITE. Settings: Yes, No Default: No DriveDone This option actively drives the DONE pin high as opposed to an open-drain driver. Take care when setting DriveDone=Yes in daisy chain applications. Settings: Yes, No Default: No DonePipe This option is intended for use with FPGAs being set up in a high-speed daisy chain configuration. When set to Yes, the FPGA waits on the DONE pin, and waits for the first StartupClk edge before moving to the Done state. Settings: Yes, No Default: No Security This options selects the level of bitstream security. Selecting Level 1 disables Readback, and selecting Level 2 disables Readback and reconfiguration. Settings: Level1, Level2, None Default: None UserID The user can enter up to an 8-digit hexadecimal code (32-bit value) in the UserID register. You can use the register to identify implementation or design revisions. Settings: <any 8-digit hex string> Default: 0xFFFFFFFF 522 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Using PROMGen -h or -help (Command Usage) -h architecture Displays a usage message for BitGen. The usage message displays all available options for BitGen operating on the specified architecture. -j (No BIT File) Do not create a bitstream file (.bit file). This option is generally used when you want to generate a report without producing a bitstream. For example, if you wanted to run DRC without producing a bitstream file, you would use the -j option. Note: The .msk or .rbt files might still be created. -l (Create a Logic Allocation File) This option creates an ASCII logic allocation file (design.ll) for the selected design. The logic allocation file indicates the bitstream position of latches, flip-flops, and IOB inputs and outputs. In some applications, you may want to observe the contents of the FPGA internal registers at different times. The file created by the -l option helps you identify which bits in the current bitstream represent outputs of flip-flops and latches. Bits are referenced by frame and bit number within the frame. The Hardware Debugger uses the design.ll file to locate signal values inside a readback bitstream. -m (Generate a Mask File) Creates a mask file. This file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA. -w (Overwrite Existing Output File) Enables you to overwrite an existing BIT, LL, MSK, or RBT output file. Using PROMGen The PROMGen program is compatible with the following families. * Virtex/Virtex-E/Virtex-II/Virtex-II Pro PROMGen formats a BitGen-generated configuration bitstream (BIT) file into a PROM format file (Figure A-2). The PROM file contains configuration data for the FPGA device. PROMGen converts a BIT file into one of three PROM formats: MCS-86 (Intel), EXORMAX (Motorola), or TEKHEX (Tektronix). It can also generate a Hex file format. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 523 R Appendix A: BitGen and PROMGen Switches and Options BIT PRM Memory Map PROMGen EXO PROM File MCS PROM File TEK PROM File HEX Device Configuration X9226 Figure A-2: PROMGen There are two functionally equivalent versions of PROMGen. There is a stand-alone version you can access from an operating system prompt. You can also access an interactive version, called the PROM File Formatter, from inside the Design Manager for Alliance or the Project Manager in Foundation. This chapter describes the stand-alone version; the interactive version is described in the PROM File Formatter Guide. You can also use PROMGen to concatenate bitstream files to daisy-chain FPGAs. Note: If the destination PROM is one of the Xilinx Serial PROMs, you are using a Xilinx PROM Programmer, and the FPGAs are not being daisy-chained, it is not necessary to make a PROM file. See the Hardware User Guide for more information about daisy-chained designs PROMGen Syntax Use the following syntax to start PROMGen from the operating system prompt: promgen [options] Options can be any number of the options listed in PROMGen Options, page 525. Separate multiple options with spaces. PROMGen Files This section describes the PROMGen input and output files. Input Files The input to PROMGEN consists of BIT files-- one or more bitstream files. BIT files contain configuration data for an FPGA design. Output Files Output from PROMGEN consists of the following files. 524 * PROM files--The file or files containing the PROM configuration information. Depending on the PROM file format used by the PROM programmer, you can output a TEK, MCS, or EXO file. If you are using a microprocessor to configure your devices, you can output a HEX file, containing a hexadecimal representation of the bitstream. * PRM file--The PRM file is a PROM image file. It contains a memory map of the www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Using PROMGen output PROM file. The file has a .prm extension. Bit Swapping in PROM Files PROMGen produces a PROM file in which the bits within a byte are swapped compared to the bits in the input BIT file. Bit swapping (also called "bit mirroring") reverses the bits within each byte, as shown in Figure A-3. Original Data Data in PROM File or HEX File 8 1000 A 1010 0101 5 0001 1 X8074 Figure A-3: Bit Swapping In a bitstream contained in a BIT file, the Least Significant Bit (LSB) is always on the left side of a byte. But when a PROM programmer or a microprocessor reads a data byte, it identifies the LSB on the right side of the byte. In order for the PROM programmer or microprocessor to read the bitstream correctly, the bits in each byte must first be swapped so they are read in the correct order. In this release of the Xilinx Development System, the bits are swapped for all of the PROM formats: MCS, EXO, and TEK. For a HEX file output, bit swapping is on by default, but it can be turned off by entering a -b PROMGen option that is available only for HEX file format. PROMGen Options This section describes the options that are available for the PROMGen command. -b (Disable Bit Swapping--HEX Format Only) This option only applies if the -p option specifies a HEX file for the output of PROMGen. By default (no -b option), bits in the HEX file are swapped compared to bits in the input BIT files. If you enter a -b option, the bits are not swapped. Bit swapping is described in Bit Swapping in PROM Files, page 525. -c (Checksum) promgen -c The -c option generates a checksum value appearing in the .prm file. This value should match the checksum in the prom programmer. Use this option to verify that correct data was programmed into the prom. -d (Load Downward) promgen -d hexaddress0 filename filename... This option loads one or more BIT files from the starting address in a downward direction. Specifying several files after this option causes the files to be concatenated in a daisy chain. You can specify multiple -d options to load files at different addresses. You must specify this option immediately before the input bitstream file. The multiple file syntax is as follows: UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 525 R Appendix A: BitGen and PROMGen Switches and Options promgen -d hexaddress0 filename filename... The multiple -d options syntax is as follows: promgen -d hexaddress1 filename -d hexaddress2 filename... -f (Execute Commands File) -f command_file The -f option executes the command line arguments in the specified command_file. -help (Command Help) This option displays help that describes the PROMGen options. -l option (Disable Length Count) promgen -l The -l option disables the length counter in the FPGA bitstream. It is valid only for 4000EX, 4000XL, 4000XLA, 4000XV, and SpartanXL Devices. Use this option when chaining together bitstreams exceeding the 24 bit limit imposed by the length counter. -n (Add BIT FIles) -n file1[.bit] file2[.bit]... This option loads one or more BIT files up or down from the next available address following the previous load. The first -n option must follow a -u or -d option because -n does not establish a direction. Files specified with this option are not daisy-chained to previous files. Files are loaded in the direction established by the nearest prior -u, -d, or -n option. The following syntax shows how to specify multiple files. When you specify multiple files, PROMGen daisy-chains the files. promgen -d hexaddress file0 -n file1 file2... The following syntax when using multiple -n options prevents the files from being daisychained: promgen -d hexaddress file0 -n file1 -n file2... -o (Output File Name) -o file1[.ext] file2[.ext]... This option specifies the output file name of a PROM if it is different from the default. If you do not specify an output file name, the PROM file has the same name as the first BIT file loaded. ext is the extension for the applicable PROM format. Multiple file names may be specified to split the information into multiple files. If only one name is supplied for split PROM files (by you or by default), the output PROM files are named file_#.ext, where file is the base name, # is 0, 1, etc., and ext is the extension for the applicable PROM format. promgen -d hexaddress file0 -o filename -p (PROM Format) -p {mcs | exo | tek | hex} This option sets the PROM format to one of the following: MCS (Intel MCS86), EXO (Motorola EXORMAX), TEK (Tektronix TEKHEX). The option may also produce a HEX file, which is a hexadecimal representation of the configuration bitstream used for microprocessor downloads. If specified, the -p option must precede any -u, -d, or -n options. The default format is MCS. 526 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Using PROMGen -r (Load PROM File) -r promfile This option reads an existing PROM file as input instead of a BIT file. All of the PROMGen output options may be used, so the -r option can be used for splitting an existing PROM file into multiple PROM files or for converting an existing PROM file to another format. -s (PROM Size) -s promsize1 promsize2... This option sets the PROM size in kilobytes. The PROM size must be a power of 2. The default value is 64 kilobytes. The -s option must precede any -u, -d, or -n options. Multiple promsize entries for the -s option indicates the PROM will be split into multiple PROM files. Note: PROMGen PROM sizes are specified in bytes. The Programmable Logic Data Book specifies PROM sizes in bits for Xilinx serial PROMs (see -x option). -u (Load Upward) -u hexaddress0 filename1 filename2... This option loads one or more BIT files from the starting address in an upward direction. When you specify several files after this option, PROMGen concatenates the files in a daisy chain. You can load files at different addresses by specifying multiple -u options. This option must be specified immediately before the input bitstream file. -x (Specify Xilinx PROM) -x xilinx_prom1 xilinx_prom2... The -x option specifies one or more Xilinx serial PROMs for which the PROM files are targeted. Use this option instead of the -s option if you know the Xilinx PROMs to use. Multiple xilinx_prom entries for the -x option indicates the PROM will be split into multiple PROM files. Examples To load the file test.bit up from address 0x0000 in MCS format, enter the following information at the command line. promgen -u 0 test To daisy-chain the files test1.bit and test2.bit up from address 0x0000 and the files test3.bit and test4.bit from address 0x4000 while using a 32K PROM and the Motorola EXORmax format, enter the following information at the command line. promgen -s 32 -p exo -u 00 test1 test2 -u 4000 test3 test4 To load the file test.bit into the PROM programmer in a downward direction starting at address 0x400, using a Xilinx XC1718D PROM, enter the following information at the command line. promgen -x xc1718d -d 0x400 test To specify a PROM file name that is different from the default file name enter the following information at the command line. promgen options filename -o newfilename UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 527 R 528 Appendix A: BitGen and PROMGen Switches and Options www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Appendix B XC18V00 Series PROMs This appendix contains package specifications for the XC18V00 Series of In-System Programmable Configuration PROMs, as well as the XC18V00 Series product specification (DS026). The latest version of this information is available online (at www.xilinx.com). PROM Package Specifications This section contains specifications for the following Virtex-II packages: * PC20-84 Specification * SO20 Specification * VQ44 Specification UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 529 R Appendix B: XC18V00 Series PROMs PC20-84 Specification UG002_app_01_111600 Figure B-1: 530 PC20-84 Specification www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R PROM Package Specifications SO20 Specification UG002_app_02_111600 Figure B-2: SO20 Specification UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 531 R Appendix B: XC18V00 Series PROMs VQ44 Specification UG002_app_04_111600 Figure B-3: VQ44 Specification 532 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook 0 XC18V00 Series of In-System Programmable Configuration PROMs R DS026 (v3.0) November 12, 2001 0 0 Features * Product Specification * In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Dual configuration modes - Serial Slow/Fast configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) Endurance of 20,000 program/erase cycles * 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals Program/erase over full commercial/industrial voltage and temperature range * 3.3V or 2.5V output capability * Available in PC20, SO20, PC44 and VQ44 packages * Design support using the Xilinx Alliance and Foundation series software packages. * JTAG command initiation of standard FPGA configuration * IEEE Std 1149.1 boundary-scan (JTAG) support * Simple interface to the FPGA * Cascadable for storing longer or multiple bitstreams * Low-power advanced CMOS FLASH process Description Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Initial devices in this 3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a 512-Kbit, and a 256-Kbit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA or CPLD configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. TMS TDI Control and JTAG Interface TDO Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable Serial PROM family. OE/Reset CLK CE TCK When the FPGA is in Slave-Parallel or SelectMAP Mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data is clocked into the FPGA on the following rising edge of the CCLK. Neither Slave-Parallel nor SelectMAP utilize a Length Count, so a free-running oscillator can be used. Data Memory Address Data CEO Serial or Parallel Interface 7 D0 DATA (Serial or Parallel [Slave-Parallel/SelectMAP] Mode) D[1:7] Slave-Parallel and SelectMAP Interface CF DS026_01_111201 Figure 1: XC18V00 Series Block Diagram (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 533 R XC18V00 Series of In-System Programmable Configuration PROMs Pinout and Pin Description Table 1: Pin Names and Descriptions (pins not listed are "no connect") 20-pin Pin Name Boundary Scan Order Function D0 4 DATA OUT 3 OUTPUT ENABLE 6 DATA OUT 5 OUTPUT ENABLE 2 DATA OUT 1 OUTPUT ENABLE 8 DATA OUT 7 OUTPUT ENABLE 24 DATA OUT 23 OUTPUT ENABLE 10 DATA OUT 9 OUTPUT ENABLE 17 DATA OUT 16 OUTPUT ENABLE 14 DATA OUT 13 OUTPUT ENABLE CLK 0 DATA IN OE/ RESET 20 DATA IN 19 DATA OUT 18 OUTPUT ENABLE 15 DATA IN D1 D2 D3 D4 D5 D6 D7 CE 534 44-pin 44-pin VQFP PLCC SOIC and PLCC D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. 40 2 1 D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Slave-Parallel/SelectMap mode. 29 35 16 42 4 2 27 33 15 9 15 7(1) 25 31 14 14 20 9 19 25 12 Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. 43 5 3 When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. 13 19 8 When CE is High, this pin puts the device into standby mode and resets the address counter. The DATA output pin is in a high-impedance state, and the device is in low power standby mode. 15 21 10 Pin Description www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Table 1: Pin Names and Descriptions (pins not listed are "no connect") (Continued) 20-pin Pin Name Boundary Scan Order Function CF 22 DATA OUT 21 OUTPUT ENABLE 11 DATA OUT 12 OUTPUT ENABLE CEO GND 44-pin 44-pin Pin Description VQFP PLCC SOIC and PLCC Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. 10 16 7(1) Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. 21 27 13 6, 18, 28 & 41 3, 12, 24 & 34 11 GND is the ground connection. TMS MODE SELECT The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. 5 11 5 TCK CLOCK This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. 7 13 6 TDI DATA IN This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 3 9 4 TDO DATA OUT This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K ohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 31 37 17 VCC Positive 3.3V supply voltage for internal logic and input buffers. 17, 35 & 38 23, 41 & 44 18 & 20 VCCO Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers. 8, 16, 26 & 36 14, 22, 32 & 42 19 Notes: 1. Pin 7 is CF in Serial Mode, D4 in Slave-Parallel Mode for 20-pin packages. DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 535 R XC18V00 Series of In-System Programmable Configuration PROMs Xilinx FPGAs and Compatible PROMs Table 2 provides a list of Xilinx FPGAs and compatible PROMs. Table 2: Xilinx FPGAs and Compatible PROMs Table 2: Xilinx FPGAs and Compatible PROMs 536 Device Configuration Bits XC18V00 Solution XCV1000E 6,587,520 2 of XC18V04 XCV1600E 8,308,992 2 of XC18V04 XCV2000E 10,159,648 3 of XC18V04 XCV2600E 12,922,336 4 of XC18V04 XCV3200E 16,283,712 4 of XC18V04 XC2S15 197,696 XC18V256 XC2S30 336,768 XC18V512 XC2S50 559,200 XC18V01 XC2S100 781,216 XC18V01 XC2S150 1,040,096 XC18V01 XC2S200 1,335,840 XC18V02 Device Configuration Bits XC18V00 Solution XC2V40 360,160 XC18V512 XC2V80 635,360 XC18V01 XC2V250 1,697,248 XC18V02 XC2V500 2,761,952 XC18V04 XC2V1000 4,082,656 XC18V04 XC2V1500 5,659,360 XC18V04 + XC18V02 XC2V2000 7,492,064 2 of XC18V04 XC2V3000 10,494,432 3 of XC18V04 XC2V4000 15,660,000 4 of XC18V04 XC2V6000 21,849,568 5 of XC18V04 + XC18V02 XC2S50E 630,048 XC18V01 XC2S100E 863,840 XC18V01 XC2V8000 29,063,136 7 of XC18V04 XC2S150E 1,134,528 XC18V02 XCV50 559,200 XC18V01 XC2S200E 1,442,016 XC18V02 XCV100 781,216 XC18V01 XC2S300E 1,875,648 XC18V02 XCV150 1,040,096 XC18V01 XCV200 1,335,840 XC18V02 XCV300 1,751,808 XC18V02 XCV400 2,546,048 XC18V04 XCV600 3,607,968 XC18V04 XCV800 4,715,616 XC18V04 + XC18V512 XCV1000 6,127,744 XC18V04 + XC18V02 XCV50E 630,048 XC18V01 XCV100E 863,840 XC18V01 XCV200E 1,442,106 XC18V02 XCV300E 1,875,648 XC18V02 XCV400E 2,693,440 XC18V04 XCV405E 3,430,400 XC18V04 XCV600E 3,961,632 XC18V04 XCV812E 6,519,648 2 of XC18V04 Capacity Devices Configuration Bits XC18V04 4,194,304 XC18V02 2,097,152 XC18V01 1,048,576 XC18V512 524,288 XC18V256 262,144 In-System Programming In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx JTAG Programmer software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The JTAG Programmer software also outputs www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-impedance state or held at clamp levels during in-system programming. OE/RESET The ISP programming algorithm requires issuance of a reset that causes OE to go Low. External Programming Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 device programmer. This provides the added flexibility of using pre-programmed devices in board design and boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes. Reliability and Endurance cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit. Design Security The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 3 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 3: Data Security Options Default = Reset Set Read Allowed Program/Erase Allowed Read Inhibited via JTAG Erase Allowed Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase V CC GND (a) (b) DS026_02_011100 Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable IEEE 1149.1 Boundary-Scan (JTAG) The XC18V00 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system pro- DS026 (v3.0) November 12, 2001 Product Specification gramming (ISP) to facilitate configuration, erasure, and verification operations on the XC18V00 device. Table 4 lists the required and optional boundary-scan instructions supported in the XC18V00. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. www.xilinx.com 1-800-255-7778 537 R XC18V00 Series of In-System Programmable Configuration PROMs on the XC18V00 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. Table 4: Boundary Scan Instructions Boundary-Scan Command Binary Code [7:0] Description Required Instructions BYPASS 11111111 Enables BYPASS SAMPLE/ PRELOAD 00000001 Enables boundary-scan SAMPLE/PRELOAD operation EXTEST 00000000 Enables boundary-scan EXTEST operation CLAMP 11111010 Enables boundary-scan CLAMP operation HIGHZ 11111100 all outputs in high-impedance state simultaneously IDCODE 11111110 Enables shifting out 32-bit IDCODE USERCODE 11111101 Enables shifting out 32-bit USERCODE The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where XC18V00 Specific Instructions 11101110 For each input pin, the register stage controls and observes the input state of the pin. Identification Registers Optional Instructions CONFIG For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the pin. Initiates FPGA configuration by pulsing CF pin Low v = the die version number f = the family code (50h for XC18V00 family) Instruction Register a = the ISP PROM product ID (26h for the XC18V04) The Instruction Register (IR) for the XC18V00 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 3. c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1 Table 5 lists the IDCODE register values for the XC18V00 devices. Table 5: IDCODES Assigned to XC18V00 Devices The ISP Status field, IR(4), contains logic "1" if the device is currently in ISP mode; otherwise, it contains logic "0". The Security field, IR(3), contains logic "1" if the device has been programmed with the security option turned on; otherwise, it contains logic "0". TDI-> IR[7:5] IR[4] IR[3] IR[2] IR[1:0] 000 ISP Status Security 0 01 ->TD O Notes: 1. IR(1:0) = 01 is specified by IEEE Std. 1149.1 Figure 3: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence Boundary Scan Register The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin 538 ISP-PROM IDCODE XC18V01 05024093h XC18V02 05025093h XC18V04 05026093h XC18V256 05022093h XC18V512 05023093h The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XC18V00 device. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh. www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs XC18V00 TAP Characteristics TAP Timing The XC18V00 family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XC18V00 TAP are described as follows. Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations. TCKMIN TCK TMSS TMSH TMS TDIS TDIH TDI TDOV TDO DS026_04_020300 Figure 4: Test Access Port Timing TAP AC Parameters Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4 Table 6: Test Access Port Timing Parameters Symbol Parameter Min Max Units TCKMIN1 TCK minimum clock period 100 - ns TCKMIN2 TCK minimum clock period, Bypass Mode 50 - ns TMSS TMS setup time 10 - ns TMSH TMS hold time 25 - ns TDIS TDI setup time 10 - ns TDIH TDI hold time 25 - ns TDOV TDO valid delay - 25 ns Connecting Configuration PROMs Connecting the FPGA device with the configuration PROM (see Figure 6). * * * * The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) (in Master Serial mode only). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even DS026 (v3.0) November 12, 2001 Product Specification when a reconfiguration is initiated by a VCC glitch. * * The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of the first FPGA device, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Slave-Parallel/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements. www.xilinx.com 1-800-255-7778 539 R XC18V00 Series of In-System Programmable Configuration PROMs Initiating FPGA Configuration The XC18V00 devices incorporate a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses the CF low for 300-500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. The JTAG Programmer software can also issue a JTAG CONFIG command to initiate FPGA configuration through the "Load FPGA" setting. Selecting Configuration Modes The XC18V00 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XC18V00 device. This control register is accessible through JTAG, and is set using the "Parallel mode" setting on the Xilinx JTAG Programmer software. Serial output is the default programming mode. Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs are designed to accommodate the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated by the FPGA during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configu- 540 ration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip pull-up resistor. Cascading Configuration PROMs For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (Figure 5). Multiple XC18V00 devices can be concatenated by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all XC18V00 devices in the chain are interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 6. After configuration is complete, address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low. www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Vcc Vcco Vcc Vcco Vcc 4.7K Vcc MODE PINS* Vcc DOUT DIN DIN Vcc D0 Vcco J1 TDI TMS TCK TDO 1 2 3 4 D0 Vcc Xilinx FPGA Vcco XC18V00 XC18V00 Cascaded PROM First PROM Vcc MODE PINS* Xilinx FPGA 4.7K Master Serial Slave Serial ** CLK CCLK CCLK TMS CE TMS CE DONE DONE TCK CEO TCK CEO TDI GND CLK TDI OE/RESET OE/RESET CF CF TDO GND TDO INIT INIT PROGRAM PROGRAM TDI TDI TMS TCK TMS TDO * For Mode pin connections, refer to appropriate FPGA data sheet. ** Virtex, Virtex-E is 300 ohms, all others are 4.7K. TCK TDO DS026_08_011501 Figure 5: JTAG Chain for Configuring Devices in Master Serial Mode DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 541 R XC18V00 Series of In-System Programmable Configuration PROMs OPTIONAL Daisy-chained FPGAs with different configurations DOUT FPGA OPTIONAL Slave FPGAs with identical configurations Vcco Vcc VCC 4.7K Modes (1) VCC (2) ** VCC 4.7K VCC VCCO DATA First CLK PROM CEO CE DIN CCLK DONE INIT DATA Cascaded PROM CLK CE OE/RESET OE/RESET CF CF PROGRAM (Low Resets the Address Pointer) (1) For Mode pin connections, refer to the appropriate FPGA data sheet. (2) Virtex is 300 ohms. Master Serial Mode I/O(1) I/O (1) WRITE 1K VIRTEX Select MAP NC External Osc (4) CS Modes VCC VCCO VCC VCCO VCC VCCO VCC VCCO 1K 3.3V VCC BUSY VCC XC18Vxx (2) 8 PROGRAM D[0:7] D[0:7] CE DONE OE/RESET INIT XC18Vxx 4.7K CLK CCLK CLK CEO CEO D[0:7] CE CF OE/RESET CF (1) CS and WRITE must be pulled down to be used as I/O. One option is shown. (2) Virtex, Virtex-E is 300 ohms, all others are 4.7K. (3) For Mode pin connections, refer to the appropriate FPGA data sheet. (4) External oscillator required for Virtex/E SelectMAP or Virtex-II Slave SelectMAP modes. Virtex SelectMAP Mode VCC VCC CS(0) To Additional Optional Daisy-chained Devices CS(1) VCC VCC VCC M0 VCCO VCC 3.3K 3.3K VCC 3.3K VCCO D[0:7] 8 M1 CS Spartan-II, Spartan- IIE D[0:7] CEO XC18Vxx CE CF OE/RESET CLK M0 M1 CS PROGRAM DONE INIT DOUT Optional Daisy-chained Spartan-II, Spartan-IIE D[0:7] PROGRAM DONE INIT CCLK CCLK To Additional Optional Daisy-chained Devices External Osc Spartan-II/IIE Slave-Parallel Mode DS026_05_111201 Figure 6: (a) Master Serial Mode (b) Virtex SelectMAP Mode (c) Spartan-II/IIE Slave-Parallel Mode (dotted lines indicate optional connection) 542 www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs 5V Tolerant I/Os The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) can have power applied in any order. This makes the PROM devices immune to power supply sequencing issues. Reset Activation low until the XC18V00 voltage reaches the operating voltage range. If the power drops below 2.0V, the PROM resets. OE/RESET polarity is NOT programmable. Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. JTAG pins TMS, TDI and TDO can be in a high-impedance state or High. Customer Control Pins On power up, OE/RESET is held low until the XC18V00 is active (1 ms) and able to supply data after receiving a CCLK pulse from the FPGA. OE/RESET is connected to an external resistor to pull OE/RESET HIGH releasing the FPGA INIT and allowing configuration to begin. OE/RESET is held The XC18V00 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using "Skip User Array" in Xilinx JTAG Programmer Software. Table 7: Truth Table for PROM Control Inputs Control Inputs Outputs OE/RESET CE Internal Address DATA CEO ICC High Low If address < TC(1): increment If address > TC(1): don't change Active High-Z High Low Active Reduced Low Low Held reset High-Z High Active High High Held reset High-Z High Standby Low High Held reset High-Z High Standby Notes: 1. TC = Terminal Count = highest address value. TC + 1 = address 0. DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 543 R XC18V00 Series of In-System Programmable Configuration PROMs Absolute Maximum Ratings Symbol Description Value Units VCC Supply voltage relative to GND -0.5 to +4.0 V VIN Input voltage with respect to GND -0.5 to +5.5 V VTS Voltage applied to High-Z output -0.5 to +5.5 V TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10s @ 1/16 in.) +260 C Junction temperature +150 C TJ Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to -2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Recommended Operating Conditions Symbol Parameter VCCINT Internal voltage supply (TA = 0C to +70C) Internal voltage supply (TA = -40C to +85C) VCCO Min Max Units Commercial 3.0 3.6 V Industrial 3.0 3.6 V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCCO V 1 50 ms TVCC VCC rise time from 0V to nominal voltage(1) Notes: 1. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. Quality and Reliability Characteristics Symbol 544 Description Min Max Units 20 - Years TDR Data retention NPE Program/erase cycles (Endurance) 20,000 - Cycles VESD Electrostatic discharge (ESD) 2,000 - Volts www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs DC Characteristics Over Operating Conditions Symbol Parameter Test Conditions Min Max Units 2.4 - V 90% VCCO - V High-level output voltage for 3.3V outputs IOH = -4 mA High-level output voltage for 2.5V outputs IOH = -500 A Low-level output voltage for 3.3V outputs IOL = 8 mA - 0.4 V Low-level output voltage for 2.5V outputs IOL = 500 A - 0.4 V ICC Supply current, active mode 25 MHz - 25 mA ICCS Supply current, standby mode - 10 mA IILJ JTAG pins TMS, TDI, and TDO VCC = MAX VIN = GND -100 - A IIL Input leakage current VCC = Max VIN = GND or VCC -10 10 A IIH Input and output High-Z leakage current VCC = Max VIN = GND or VCC -10 10 A Input and output capacitance VIN = GND f = 1.0 MHz - 10 pF VOH VOL CIN and COUT Notes: 1. 18V01/18V512/18V256 only, cascadable. 2. 18V01/18V512/18V256 only, non-cascadable, no brown-out protection. DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 545 R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions for XC18V04 and XC18V02 CE TSCE THCE OE/RESET THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS026_06_012000 Symbol Description Min Max Units TOE OE/RESET to data delay - 10 ns TCE CE to data delay - 20 ns TCAC CLK to data delay - 20 ns TOH Data hold from CE, OE/RESET, or CLK 0 - ns TDF CE or OE/RESET to data float delay(2) - 25 ns Clock periods 50 - ns TLC CLK Low time(3) 10 - ns THC CLK High time(3) 10 - ns TSCE CE setup time to CLK (to guarantee proper counting)(3) 25 - ns THCE CE High time (to guarantee proper counting) 2 - s THOE OE/RESET hold time (guarantees counters are reset) 25 - ns TCYC Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 s, TCE = 2 s. 546 www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and XC18V256 CE TSCE THCE OE/RESET THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS026_06_012000 Symbol Description Min Max Units TOE OE/RESET to data delay - 10 ns TCE CE to data delay - 15 ns TCAC CLK to data delay - 15 ns TOH Data hold from CE, OE/RESET, or CLK 0 - ns TDF CE or OE/RESET to data float delay(2) - 25 ns Clock periods 30 - ns TLC CLK Low time(3) 10 - ns THC CLK High time(3) 10 - ns TSCE CE setup time to CLK (to guarantee proper counting)(3) 20 - ns THCE CE hold time to CLK (to guarantee proper counting) 2 - s THOE OE/RESET hold time (guarantees counters are reset) 20 - ns TCYC Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 s, TCE = 2 s. DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 547 R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions When Cascading for XC18V04 and XC18V02 OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 25 ns TOCK CLK to CEO delay(3) - 20 ns TOCE CE to CEO delay(3) - 20 ns TOOE OE/RESET to CEO delay(3) - 20 ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 548 www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions When Cascading for XC18V01, XC18V512, and XC18V256 OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 25 ns TOCK CLK to CEO delay(3) - 20 ns TOCE CE to CEO delay(3) - 20 ns TOOE OE/RESET to CEO delay(3) - 20 ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS026 (v3.0) November 12, 2001 Product Specification www.xilinx.com 1-800-255-7778 549 R XC18V00 Series of In-System Programmable Configuration PROMs Ordering Information XC18V04 VQ44 C Device Number XC18V04 XC18V02 XC18V01 XC18V512 XC18V256 Operating Range/Processing Package Type VQ44 = 44-pin Plastic Quad Flat Package PC44 = 44-pin Plastic Chip Carrier(1) SO20 = 20-pin Small-Outline Package(2) PC20 = 20-pin Plastic Leaded Chip Carrier(2) C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C) Notes: 1. XC18V04 and XC18V02 only. 2. XC18V01, XC18V512, and XC18V256 only. Valid Ordering Combinations XC18V04VQ44C XC18V02VQ44C XC18V01VQ44C XC18V512VQ44C XC18V256VQ44C XC18V04PC44C XC18V02PC44C XC18V01PC20C XC18V512PC20C XC18V256PC20C XC18V01SO20C XC18V512SO20C XC18V256SO20C XC18V04VQ44I XC18V02VQ44I XC18V01VQ44I XC18V512VQ44I XC18V256VQ44I XC18V04PC44I XC18V02PC44I XC18V01PC20I XC18V512PC20I XC18V256PC20I XC18V01SO20I XC18V512SO20I XC18V256SO20I Marking Information 44-pin Package XC18V04 VQ44 C Device Number XC18V04 XC18V02 XC18V01 XC18V512 XC18V256 Operating Range/Processing Package Type VQ44 = 44-pin Plastic Quad Flat Package PC44 = 44-pin Plastic Leaded Chip Carrier(1) C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C) Notes: 1. XC18V02 and XC18V04 Only. 20-pin Package(1) Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows: 18V01 S C Device Number 18V01 18V512 18V256 Operating Range/Processing Package Type S20 = 20-pin Small-Outline Package J20 = 20-pin Plastic Leaded Chip Carrier C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C) Notes: 1. XC18V01, XC18V512, and XC18V256 only. 550 www.xilinx.com 1-800-255-7778 DS026 (v3.0) November 12, 2001 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Revision History The following table shows the revision history for this document. Date Version 2/9/99 1.0 First publication of this early access specification 8/23/99 1.1 Edited text, changed marking, added CF and parallel load 9/1/99 1.2 Corrected JTAG order, Security and Endurance data. 9/16/99 1.3 Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF description, 256 Kbit and 128 Kbit devices. 01/20/00 2.0 Added Q44 Package, changed XC18xx to XC18Vxx 02/18/00 2.1 Updated JTAG configuration, AC and DC characteristics 04/04/00 2.2 Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to FPGA table. 06/29/00 2.3 Removed XC18V128 and updated format. Added AC characteristics for XC18V01, XC18V512, and XC18V256 densities. 11/13/00 2.4 Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: TSCE units to ns, THCE CE High time units to s. Removed Standby Mode statement: "The lower power standby modes available on some XC18V00 devices are set by the user in the programming software". Changed 10,000 cycles endurance to 20,000 cycles. 01/15/01 2.5 Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP PROM product ID from 06h to 26h. 04/04/01 2.6 Updated Figure 6, Virtex SelectMAP mode; added XC2V products to Compatible PROM table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years; 04/30/01 2.7 Updated Figure 6: removed Virtex-E in Note 2, fixed SelectMAP mode connections. Under AC Characteristics Over Operating Conditions for XC18V04 and XC18V02, changed TSCE from 25 ms to 25 ns. 06/11/01 2.8 AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and XC18V256 Changed Min values for TSCE from 20 ms to 20 ns and for THCE from 2 ms to 2 s. 09/28/01 2.9 Changed the boundary scan order for the CEO pin in Table 1, updated the configuration bits values in the table under Xilinx FPGAs and Compatible PROMs, and added information to the Recommended Operating Conditions table. 11/12/01 3.0 Updated for Spartan-IIE FPGA family. DS026 (v3.0) November 12, 2001 Product Specification Revision www.xilinx.com 1-800-255-7778 551 XC18V00 Series of In-System Programmable Configuration PROMs 552 www.xilinx.com 1-800-255-7778 R DS026 (v3.0) November 12, 2001 Product Specification R Glossary AC Coupling Method of interfacing drivers and receivers through a series capacitor. Often used when the differential swing between drivers and receivers is compatible, but common mode voltages of driver and receiver are not. Requires that a minimum data frequency be established based on the RC time constant, necessitating a run length limit. Addressing Modes Techniques used by software or hardware in calculating an address. ALU (Arithmetic and Logic Unit) The part of a processor that performs integer addition, subtraction, multiplication, division and other Boolean logic instructions. AQL (Acceptable Quality Level) The relative number of devices, expressed in parts-per-million (ppm), that might not meet specification or might be defective. Typical values are around 10 ppm. ASIC (Application-Specific Integrated Circuit) An integrated circuit designed to perform a particular function by defining the interconnection of a set of basic circuit building blocks drawn from a library provided by the circuit manufacturer. Assembler A software development tool that translates assembly language programs into machine instructions that the processor can decode and execute. Assembly Language A human-readable form of a processor's instruction set. Most processor-specific functions are written in assembly language. Asynchronous Logic that is not synchronized by a clock. Asynchronous designs can be faster than synchronous ones, but are more sensitive to parametric changes, and are thus less robust. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 553 R Glossary ATM (Asynchronous Transfer Mode) A very-high-speed (megahertz to gigahertz) connection-oriented bit-serial protocol for transmitting data and real-time voice and video in fixed-length packets (48-byte payload, 5-byte header). Attenuation Reduction in amplitude of a signal. Back Annotation Automatically attaching timing values to the entered design format after the design has been placed and routed in a field-programmable gate array (FPGA). BER (Bit Error Rate) A measurement of the number of errors detected at a receiver in a given length of time, sometimes specified as a percentage of received bits; sometimes specified in exponential form (10E-8 to indicate 1 bit error in 10E-8 bits). BERT (Bit Error Rate Test, Bit Error Rate Tester) A test or an instrument used to determine the Bit Error Rate (BER) of a device or system under test. It is generally made up of a test pattern generator, receiver, and analyzer. Big Endian A representation of a multi-byte value that has the most significant byte of any multi-byte data field stored at the lowest memory address. Also see Little Endian. BIST (Built-In Self Test) The technique of designing circuits with additional logic that can be used to test proper operation of the primary (functional) logic. Bitstream The bitstream is a binary representation of an implemented FPGA design. The bitstream is generated by Xilinx bit generation tools (BitGen and Makebits) and is denoted with the .bit extension. For information on creating BIT files, refer to the Hardware Debugger Reference/User Guide. Block RAM An 18 Kb block of random access memory (RAM) inside the Virtex-II Pro device. Dual-port and synchronous operation are desirable. Block SelectRAM Fully-synchronous, dual-port memories in the Virtex-II Pro FPGAs. Each of these memories contain 18 x 1024 (18,432) bits. The organization of each memory is configurable. Block SelectRAM resources complement smaller, distributed, LUT-based SelectRAM resources. Book "E" A Motorola and IBM jointly written architectural definition and instruction set for embedded PowerPC implementations. 554 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Boot ROMs The program used to bring up a computer or system that is stored in Read Only Memory Boundary Scan Interface One of the configuration interfaces on the Virtex device. This is a bit-serial interface. The Boundary Scan interface is also known as the JTAG port. Also see SelectMAP Interface. Breakpoint A location in a program at which execution is to be stopped and control of the processor switched to the debugger. Mechanisms for creating and removing breakpoints are provided by most debugging tools. BSP (Board Support Package) The purpose of the BSP is to isolate the user design from hardware making it easier to write new applications and to port applications from other environments. BSP consists of a set of software modules that offer interface to peripheral devices and lowlevel processor core functions for user software or C library. For example, these functions include hardware initialization, boot monitor access, drivers for all the available resources and features on board. Cache A small block of high-speed memory located between the processor and main memory. Cache stores frequently used data and instructions. Cache improves system performance by reducing the need to access the system's slower main memory. Cache Block See Cache Line. Cache Line A portion of a cache array that contains a copy of contiguous system-memory addresses. Cache lines in PPC405 are 32 bytes long and aligned on a 32 byte address. Cache Set See Congruence Class. Capture Data The flip-flop and pad data saved from the logic cells and I/O blocks into the bitstream for readback. Use the CAPTURE_VIRTEX primitive in your HDL code to specify the trigger and clock for the capture operation. CCLK (Configuration Clock) During configuration, the configuration clock (CCLK) is an output in Master modes or in the Asynchronous Peripheral mode but is an input in Slave, Synchronous Peripheral, Express, and SelectMAP/Slave Serial modes. After configuration, CCLK has a weak pullup and can be selected as the readback clock. CDR (Clock/Data Recovery) Feature of most high-speed serial transcievers. At the receiver, a clock is generated based on the timing of data transitions. In this way, a clock signal is derived from the data. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 555 R Glossary Channel Bonding Feature of multi-channel high-speed transcievers. Allows multiple channels to be sued together, offering a greater aggregate bandwidth. Chirp Bit sequence which is transmitted by a high-speed transciever when it is not in use. The chirp is usually a repeating pattern of IDLE characters. The purpose of the chirp is to keep clock recovery circuits aligned and active while the link is not transmitting data. CISC (Complex Instruction Set Computer) The architecture of a processor family. CISC processors generally feature variable-length instructions, multiple addressing formats, and contain only a small number of generalpurpose registers. Intel's 80x86 family is the quintessential example of CISC. CLB (Configurable Logic Block) Xilinx-specific name for a block of logic surrounded by routing resources. The functional elements for constructing logic circuits. The Virtex-II Pro CLB is made up of four slices, and each slice contains two Logic Cells. CML (Current Mode Logic) A differential I/O standard used in high-speed serial channels. Voltage swing is typically from 450 mV to 1200 mV. Coherency Coherency describes the ordering of reads from and writes to a single memory location. A memory system is coherent when the value read from a memory address is always the last value written to the address. In a system where all devices read and write from a single, shared system memory, memory is always coherent. Comma A comma is a "K" character used by the transceiver to align the serial data on a byte/halfword boundary (depending on the protocol used), so that the serial data is correctly decoded into parallel data. Common Mode The DC component of a signal. In differential channels, it is the average voltage of the differential pair. Compiler Software that converts a higher-language description into a lower-level representation. For FPGAs, the complete partition, place, and process. Configuration Bitstream Configuration commands with configuration data. Configuration Commands Instructions for the Virtex-II Pro device. There are two classes of Configuration Command -- Major and Minor. The Major Commands read and write data to configuration registers 556 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R in the Virtex-II Pro device. The Minor commands instruct the Virtex-II Pro configuration logic to perform specific functions. Configuration Data Bits that directly define the state of programmable logic. These are written to a Virtex-II Pro device in a configuration bitstream, and read as readback data from a Virtex-II Pro device. Configuration File The internally stored file that controls the FPGA sot hat it performs the desired logic function. Also, the act of loading an FPGA with that file. That is, the process of programming Xilinx SRAM-based FPGAs with a bitstream. Configuration Frame The configuration bits in a Virtex-II Pro device are organized in columns. A column of CLBs with the I/O blocks above and below the CLBs contain 48 frames of configuration bits. The smallest number of bits that can be read or written through the configuration interfaces is one frame. Configuration Interface A logical interface on the Virtex-II Pro device through which configuration commands and data can be read and written. A interface consists of one or more physical device pins. Configuration Readback The operation of reading configuration data (also known as readback data) from a Virtex-II Pro device. Congruence Class A collection of cache lines with the same index. Constraints Performance requirements imposed on the design, usually in the form of maximum allowable delay, or the required operating frequency. Context Switch The process of switching from one task to another in a multitasking operating system. A context switch involves saving the context of the running task and restoring the previously-saved context of the other. CoreConnectTM Bus Architecture An interconnection internal bus developed by IBM. It eases the integration and reuse of processor, system, and peripheral cores Elements of CoreConnect architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register (DCR) bus. Cross Compiler A compiler that runs on a particular processor architecture and produces code for a different architecture. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 557 R Glossary Crosstalk Undesirable signal coupling from noisy aggressor nets to victim nets. May be eliminated by increasing the spacing between the nets or reducing signal amplitude of the aggressor net. CS Pin The CS pin is the Chip Enable pin for Virtex-II Pro devices. It is used only in SelectMAP mode. When CS is asserted (Low) the device examines data on the Data bus. When CS is de-asserted (High), all CCLK transitions are ignored. DataFrame A DataFrame is a block of configuration data. A configuration bit-stream contains many such frames, each with a start bit and stop bits. Also see Configuration Frame. DC Balanced A channel is said to be DC Balanced if it has an equal number of 1's and 0's transmitted across it. Encoding schemes like 8B10B are designed to ensure this. DC Coupling Method of interfacing drivers and receivers without the use of series capacitors. A direct connection (through PCB trace) from driver to receiver. DCR (Device Control Register) A CoreConnect bus. DCR is designed to transfer data between the CPU's general purpose registers (GPRs) and the DCR slave logic's device control registers (DCRs). Debug Monitor A piece of embedded software that has been designed specifically for use as a debugging tool. It usually resides in ROM and communicates with a debugger via a serial port or network connection. The debug monitor provides a set of primitive commands to view and modify memory locations and registers, create and remove breakpoints, and execute your program. The debugger combines these primitives to fulfill higher-level requests like program download and single-step. Debugger A software development tool used to test and debug embedded software. The debugger runs on a host computer and connects to the target through a serial port or network connection. Using a debugger you can download software to the target for immediate execution. You can also set breakpoints and examine the contents of specific memory locations and registers. Deterministic Jitter The component of jitter attributable to the data pattern in the channel. Different digital patterns have different spectral contents. These differing spectral contents give rise to varying amounts of signal jitter. Device Pin One of the electrical connections on the package containing the Virtex-II Pro device. 558 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Dhrystone MIPS Dhrystone is a benchmark program for testing a system's integer performance. The objective is to compare the performance of a machine against the performance of a reference machine. The industry has adopted the VAX 11/780 as the reference 1 MIPS (Million Instruction Per Second) machine. Differential Signaling A signaling scheme which uses two complementary signals to transmit data. Differential signaling offers faster data rates at reduced signal swing with higher signal-to-noise ratio. DIN Pin During serial configuration, the DIN pin is the serial configuration data input receiving data on the rising edge of CCLK. During parallel configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O pin. Dirty Bit A bit in a memory cache or virtual memory page that has been modified by the CPU but not yet written back to storage. Dispersion "Smearing" of a signal or waveform as a result of transmission through a non-ideal transmission line. Through a non-ideal medium, signals travel at different velocities according to their frequency. Dispersion of the signal is the result. All cables and PCB transmission lines are non-ideal. DONE Pin The DONE pin on a Xilinx FPGA is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a low level on DONE can be configured to delay the global logic initialization and the enabling of outputs. Double Word Eight bytes or 64 bits. DOUT Pin During configuration in any mode except Express and SelectMAP, the DOUT pin is the serial configuration data output that can drive the DIN pin of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it is received at the DIN pin (in Master Serial Mode only). DOUT/BUSY Pin For Virtex-II Pro devices, the DOUT/BUSY pin has a dual purpose, depending on device mode. When the device is in Serial mode, this pin functions as DOUT. When the device is in SelectMAP/Slave Parallel mode, this pin functions as a handshaking signal. If BUSY is asserted (High) on a rising edge of CCLK, the data is not seen on the data bus, and should be held until the data is accepted. DRAM (Dynamic Random Access Memory) A low-cost read-write memory where data is stored on capacitors and must be refreshed periodically. DRAMs are usually addressed by a sequence of two addresses, row address, UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 559 R Glossary and column address, which makes them slower and more difficult to use than SRAMs. Also see SRAM. DSL (Digital Subscriber Line) Sometimes referred to as a "last-mile technology" because it is used only for connections from a telephone switching station to a home or office, not between switching stations. DSL uses sophisticated modulation schemes to pack data onto POTS (ordinary analog telephone) wires. Downstream data rates of up to 32 Mb/s can be achieved. The physical distance between the subscriber and the switching station must be kept short, however, to attain the higher speeds. DSOCM (Data-Side On Chip Memory) See OCM (On-Chip Memory). DSP (Digital Signal Processing) The manipulation of analog data that has been sampled and converted into a digital representation. Examples are filtering, convolution, Fast-Fourier-Transform, and so on. EDIF (Electronic Data Interchange Format) Industry standard for specifying a logic design in text (ASCII) form. EEMBC (Embedded Microprocessor Benchmark Consortium) It develops and certifies real-world benchmarks and benchmark scores to help designers select embedded processors. Effective Address The un-translated memory address as seen by a program. Emulator Short for ICE (In-Circuit Emulator). Endianness See Big Endian and Little Endian. Equalization Amplification or attenuation of certain frequency components of a signal. Used to counteract the effects of a non-ideal transmission medium. ESD (Electrostatic Discharge) High-voltage discharge can rupture the input transistor gate oxide. ESD-protection diodes divert the current to the supply leads. Exception An abnormal event or condition that requires the processor's attention. They can be caused by instruction execution or an external device. The processor records the occurrence of an exception and they often cause an interrupt to occur. 560 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Eye Diagram An eye diagram of a signal overlays the signal's waveform over many cycles. Each cycle's waveform is aligned to a common timing reference, typically a clock. An eye diagram provides a visual indication of the voltage and timing uncertainty associated with the signal. It can be generated by synchronizing an oscilloscope to a timing reference. The vertical thickness of the line bunches in an eye diagram indicate the magnitude of AC voltage noise, whereas the horizontal thickness of the bunches where they cross over is an indication of the AC timing noise or jitter. Fixed DC voltage and timing offsets are indicated by the position of the eye on the screen. Eye Mask The size of the eye opening in the center of an eye diagram indicates the amount of voltage and timing margin available to sample this signal. Thus, for a particular electrical interface, a fixed reticule or window could be placed over the eye diagram showing how the actual signal compares to minimum criteria window, know as the eye mask. If a margin rectangle with width equal to the required timing margin and height equal to the required voltage margin fits into the opening, then the signal has adequate margins. Voltage margin can often be traded of for timing margin. Fall Time The time it takes for a waveform to transition from the high logic state to the low logic state. Fall time is usually measured from 90% of the total signal swing to 10% of the signal swing. FIFO (First-In First-Out) FIFO memory where data is stored in the incoming sequence and is read out in the same sequence. Input and output can be asynchronous to each other. A FIFO needs no external addresses, although all modern FIFOs are implemented internally with RAMs driven by circular read and write counters. FIT (Failure In Time) Describes the number of device failures statistically expected for a certain number of device-hours. Expressed as failures per one billion (109) device hours. Device temperature must be specified. Mean time between failure (MTBF) can be calculated from FIT. 10 FITs are good; 100 FITs are bad. FIT (Fixed Interval Timer) One of several user-accessible timers available in the Virtex-II Pro FPGA's PowerPC 405 core. The FIT provides timer interrupts having a repeatable period. The FIT is functionally similar to an auto-reload Programmable Interval Timer (PIT), except that only a smaller fixed selection of interrupt periods is available. Flash Non-volatile programmable technology, and alternative to electrically-erasable programmable read-only memory (EEPROM) technology. The memory content can be erased by an electrical signal. This allows in-system programmability and eliminates the need for ultraviolet light and quartz windows in the package. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 561 R Glossary Flip-Flop Single-bit storage cell that samples its data input at the active (rising or falling) clock edge, and then presents the new state on its Q output after that clock edge, holding it there until after the next active clock edge. Flush A cache or TLB operation that involves writing back a modified entry to memory, followed by an invalidation of the entry. FPGA (Field Programmable Gate Array) An integrated circuit that contains configurable (programmable) logic blocks and configurable interconnect between these blocks. Xilinx FPGAs are SRAM- based programmable logic devices (PLDs). FPU (Floating Point Unit) Floating-point operations include any operations that involve fractional numbers. Frame See Configuration Frame. Function Generator Also called a look-up table (LUT), with N inputs and one output. Can implement any logic function of its N inputs. N can be between 3 and 6; 4-input function generators are most popular. Gate Smallest logic element with several inputs and one output. The AND gate output is High when all inputs are High. The OR gate output is High when at least one input is High. The NAND gate output is Low when all inputs are High. A 2-input NAND gate is used as the measurement unit for gate array complexity. Gate Array An ASIC where transistors are predefined, and only the interconnect pattern is customized for the individual application. GNU A recursive acronym "GNU Not Unix" (pronounced "guh-NEW"). The Free Software Foundation's GNU project was launched in 1984 to develop a complete Unix-like operating system that is freely distributed. GUI (Graphical User Interface ) The way of representing the computer output on the screen as graphics, pictures, icons, and windows. Pioneered by Xerox and the Apple Macintosh, now universally adopted, e.g., by Windows95 and others. Halfword Two bytes, or 16 bits. 562 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R HardWire Xilinx name for a low-cost derivative of an FPGA, where the configuration is fixed, but functionality and footprint are identical with the original FPGA-based design. Harvard Architecture Harvard architecture has separate data bus and an instruction bus. This allows instruction and data access in parallel making faster execution than a Von-Neuman architecture possible. PPC405 core is built on Harvard architecture. HDC Pin The High during configuration (HDC) pin is driven High until the I/Os become active in the Startup sequence. It is available as a control output indicating that configuration is not yet complete. After configuration, HDC is a user-programmable I/O pin. HDL (Hardware Description Language) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. Hierarchical Design Design description in multiple layers, from the highest (overview) tot he lowest (circuit details). An alternative is flat design, where everything is described at the same level of detail. Hit An indication that requested information exists in the accessed cache array, the associated fill buffer, or on the corresponding OCM interface. HyperTransportTM A high-performance bus solution developed by Advanced Micro Devices and several partners to break the I/O bottleneck in 32- and 64-bit systems. HyperTransport provides a scalable architecture that provides better than an order of magnitude increase in bus transaction throughput over existing I/O bus architectures such as PCI, PCI-X and AGP. Formerly called Lightning Data Transport (LDT). ICE (In-Circuit Emulator) A debugging tool that takes the place of (emulates) the processor on the target board. Emulators frequently incorporate a special "bond-out" version of the target processor that allows the user to observe and record its internal state as the program is executing. Idle Pattern A data sequence transmitted by a high-speed transciever as a placeholder or for link maintenance. The particular sequence of an IDLE pattern is determined by the communication protocol, and is usually a control character like K28.5. Impedance (Characteristic Impedance) Electrical characteristic of a transmission line, derived from the capacitance and inductance per unit length. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 563 R Glossary Index Register A special purpose register used by a processor when performing indexed addressing. The value in the index register is usually the reference location to which a displacement will be added. INIT Pin The INIT pin is a quadruple function signal. Before and during configuration, INIT is a bidirectional signal. A 1 - 10 k external pull-up resistor is recommended. As an activeLow open-drain output, INIT is held Low during power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O become active in the Startup sequence, INIT becomes a user-programmable I/O. Instruction Set Is referred to the set of instructions that the microprocessor can execute. The instruction set specifies the types of instructions (such as load/store, integer arithmetic, and branch instructions), the specific instructions, and the encoding used for the instructions. The instruction set definition also specifies the addressing modes used for accessing memory. Interrupt Latency The amount of time between the assertion of an interrupt and the start of the associated interrupt service routine. Interrupt Service Routine A section of code written to handle the tasks associated with an interrupt request. Interrupt Vector A special code that identifies the circuit requesting an interrupt. IP (Intellectual Property) In the legal sense, patents, copyrights, and trade secrets. In integrated circuits (ICs), predefined large functions, called "cores," that help the user complete a large design faster. ISA (Instruction Set Architecture) A term referring to a family of microprocessors with similar basic design, for example the PowerPC architecture includes Motorolas PowerQUICC, PPC7440, 7410, IBM's PPC 405, 440, and Xilinx Virtex-II Pro. ISI (Inter-Symbol Interference) A form of data corruption or noise due to the effect that data has on data-dependent channel characteristics. ISOCM (Instruction-Side On Chip Memory) See OCM (On-Chip Memory). 564 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Jitter The jitter of a periodic signal is the delay between the expected transition of the signal and the actual transition. Jitter is a zero mean random variable. When worst case analysis is undertaken the maximum value of this random variable is used. Jitter Tolerance Jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input that causes a predefined, acceptable loss at the output. For example jitter applied to the input of an OC-N equipment interface that causes an equivalent 1dB optical power penalty. Jitter Transfer Jitter transfer is defined as the ratio of jitter on the output of a device to the jitter applied on the input of the device, versus frequency. Jitter transfer is important in applications where the system is utilized in a loop-timed mode, where the recovered clock is used as the source of the transmit clock. JTAG (Joint Test Action Group) Earlier name for IEEE 1149.1 boundary scan, a method for testing boards and integrated circuits. Also see Parallel Cable IV. Kernel An essential part of any multitasking operating system software which controls how the rest of the system can operate. The kernel is to software what the CPU is to hardware. LAN (Local Area Network) A computer network that spans a relatively small area. Most LANs are confined to a single building or group of buildings. However, one LAN can be connected to other LANs over any distance via telephone lines and radio waves. A system of LANs connected in this way is called a WAN (Wide Area Network). Latency The time between when something happens and when its response is generated. This is often critical in real-time applications LC (Logic Cell) Metric for FPGA density. The basic building block of the Virtex-II Pro CLB. An LC includes a 4-input function generator, carry logic, and a storage element. LDC Pin Low during configuration (LDC) is driven Low until the I/Os become active in the Startup sequence. It is available as a control output indicating that configuration isn't complete. After configuration, LDC is a user-programmable I/O pin. LDT (Lightning Data Transport) See HyperTransportTM. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 565 R Glossary Linker A software development tool that accepts one or more object files as input and outputs a relocatable program. The linker is thus run after all of the source files have been compiled or assembled. Little Endian A representation of a multi-byte value that has the least significant byte of any multi-byte data field stored at the lowest memory address. Also see Big Endian. LogiBLOX Library of logic modules, often with user-definable parameters, like data width. Similar to LPM. Logical Address Synonym for effective address. Loopback Path in a high-speed transceiver which connects the output to the input, on either the PMA or PCS side, for testing purposes. LPM (Library of Parametrized Modules) Library of logic modules, often with user-definable parameters, like data width. Similar to LogiBLOX. LUT (Look-Up Table) Also called a function generator with N inputs and one output. Can implement any logic function of its N inputs. N is between 3 and 6; most popular are 4-input LUTs. LUT SelectRAM Shallow RAM structure implemented in CLB look-up tables (LUTs). Also see Block SelectRAM. LVDS (Low Voltage Differential Signaling) A differential I/O standard commonly used for high-speed, low-swing signals. Machine Language A computer language that is directly executable by a computer without the need for translation by a compiler or an assembler. Although the computer works on binary patterns, the program can usually be entered in octal or hexadecimal. MAN (Metropolitan Area Network) A data network designed for a town or city. In terms of geographic breadth, a MAN is larger than a LAN (Local Area Network), but smaller than a WAN (Wide Area Network). Mapping Process of assigning portions of the logic design to the physical chip resources (CLBs). With FPGAs, mapping is more demanding and more important a process than with gate arrays. Also see Synthesis. 566 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Masking A process in which an operation can be performed on a single bit. Memory Map Documentation that lists or shows the function of each location in memory. Memory-Mapped I/O A system of I/O in which each I/O location is treated as if it were memory. MicroBlaze A 32-bit soft processor developed by Xilinx Miss An indication that requested information does not exist in the accessed cache array, the associated fill buffer, or on the corresponding OCM interface. MMU (Memory Management Unit) Performs address translation (logical to physical) and protection functions. The MMU divides logical storage into pages. Mnemonic A easy to remember string representing a processor instruction. For example, EIEIO is the mnemonic of the PPC405 instruction `Enforce In Order Execution of I/O'. MTBF (Mean Time Between Failures) The statistically relevant up-time between equipment failures. Also see FIT (Failure In Time). Multilevel Signaling System where multiple logic levels are utilized instead of just two (high and low). This enables the tranmission of multiple bits in a single waveform. See http://www.signalintegrity.com/articles/misc/mls.htm MultiLINX Cable The MultiLINX cable provides many complex functions and can be loaded with new firmware as it becomes available. It can be connected to the host computer in two ways: via a Serial port or a USB port. The MultiLINX cable is supported by the Hardware Debugger software for Slave Serial and SelectMAP/Slave Parallel programming (as appropriate), as well as readback/verify. It is also supported by the JTAG programmer software for JTAG programming of both CPLDs and FPGAs. Multiprocessing The use of more than one processor in a single computer system. So-called "multiprocessor systems" usually have a common memory space through which the processors can communicate and share data. In addition, some multiprocessor systems support parallel processing. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 567 R Glossary Netlist Textual description of logic and interconnects. Also see XNF File and EDIF (Electronic Data Interchange Format). Non-maskable Interrupt (NMI) An interrupt that cannot be turned off. NRE (Non-Recurring Engineering) Charges Start-up cost for the creation of an ASIC, gate array, or HardWire. Pays for layout, masks, and test development. FPGAs and CPLD do not require NRE. Object Code The form of software after it has been translated (compiled) from the source code format a programmer writes into the machine format a microprocessor can understand. A set of processor-readable opcodes and data. The output of compilers, assemblers, linkers, and locators are files containing object code. OCM (On-Chip Memory) Interface that supports the attachment of additional memory to the instruction and data caches, and that can be accessed at performance levels matching the cache arrays. On-Chip Debugger It can be considered as advanced on-chip debug monitor. It usually allows code download, memory/resource access, single stepping, reset, status, etc. OPB (On-chip Peripheral Bus) A CoreConnect bus. OPB is architected to alleviate system performance bottlenecks by reducing capacitive loading on the Processor Local Bus (PLB). OPB is designed to support lower-performance/speed peripherals such as IIC, UART, GPIO, USB, External Bus Controller, etc Optimization Design change to improve performance. Also see Synthesis. Overshoot Phenomenon where a signal rises to a level greater than its steady-state voltage before settling to its steady-state voltage. Pad Pad bits are extra bits used to make the total number of bits in a frame an integral multiple of 32, the number of bits in a configuration word. A pad word is an extra word used at the end of a configuration frame for pipelining. A pad frame is an extra configuration frame used at the beginning of a configuration readback and at the end of a configuration write for pipelining. Parallel Cable IV Xilinx Parallel Cable IV (PC IV) is a high-speed download cable that configures or programs all Xilinx FPGA, CPLD, ISP PROM, and System ACE MPM devices. The cable 568 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R takes advantage of the IEEE 1284 ECP protocol and Xilinx iMPACT software to increase download speeds over eight times faster than existing solutions. Partitioning In FPGAs, the process of dividing the logic into subfunctions that can later be placed into individual CLBs. Partitioning precedes placement. PCMCIA Personal Computer Memory Card Interface Association. Physical and electrical standard for small plug-in boards for portable computers. PCS (Physical Coding Sublayer) Part of the physical layer of the ISO/OSI reference stack model for Gigabit Ethernet. The PCS encodes 8-bit data octets into 10-bit code groups, which it passes down to the PMA (Physical Media Attachment). In reverse direction, it also decodes 10-bit code groups passed up from the PMA. Peak-to-Peak In the case of peak-to-peak voltage, a measure of a signal's total amplitude. In the case of peak-to-peak jitter, a measure of the extremes of excursion of the bit transition times. PECL (Positive Emitter-Coupled Logic) A differential I/O standard based on the ECL standard, but which operates with a positive supply voltage. (ECL uses a negative supply voltage.) PECL is used in clocking and highspeed data applications. Peripheral Component Interface (PCI) Synchronous bus standard characterized by short range, light loading, low cost, and high performance. 66 MHz PCI can support data byte transfers up to 528 megabytes per second (MB/s) on 64 parallel data lines. Physical Address The actual address that is placed on the address bus when accessing a physically implemented memory location or register. This address can be translated from the effective address. When address translation is not used, this address is equal to the effective address. Pin-Locking Rigidly defining and maintaining the functionality and timing requirements of device pins while the internal logic is still being designed or modified. Pin-locking has become important, since circuit board fabrication times are longer than PLD design implementation times. PIP (Programmable Interconnect Point) In Xilinx FPGAs, a point where two signal lines can be connected, as determined by the device configuration. Placement In FPGAs, the process of assigning specific parts of the design to specific locations (CLBs) on the chip. Usually done automatically. Also see Partitioning. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 569 R Glossary PLB (Processor Local Bus) A CoreConnect bus. PLB interconnects high-bandwidth devices such as processor cores, external memory interfaces, PCI, and DMA controllers. PLB offers 64- and 128-bit implementations PLD (Programmable Logic Device) Generic name for all programmable logic: PALs, CPLDs, and FPGAs. PLL (Phase-Locked Loop) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. PMA (Physical Media Attachment) Part of the physical layer of the ISO/OSI reference stack model for Gigabit Ethernet. Serializes code-grouped data passed to it from the PCS (Physical Coding Sublayer), and deserializes data to be passed up to the PCS. Polling A process in which the status of devices attached to a bus system is periodically sampled. PowerPC A RISC-based computer architecture developed jointly by IBM, Apple Computer, and Motorola corporation. The name PowerPC is derived from IBM's name for the POWER (Performance Optimization With Enhanced RISC) architecture. PRBS (Pseudo-Random Bit Sequence) A pattern that appears to be random, but is actually a predictable and repeatable sequence with a very long interval (i.e., billions of bits before repeating), depending on the pattern. Preamble The Preamble is a 4-bit binary sentinel ("0010"b) used to indicate the beginning of the LengthCount in the Header portion of the bitstream. At the beginning of configuration, FPGAs ignore all data prior to the preamble but counts the number of data bits preceding the preamble, and the LengthCount counter increments for every rising CCLK edge, even the ones proceeding the preamble. Pre-emphasis Pre-emphasis is magnitude boosting of high frequency spectral components before launching the signal (wave) onto the Transmission Line. Transmission Lines embedded in most standard PCB materials (FR4, Rogers 43xx, Nelco and Rogers) suffer varying degrees of dispersion and loss in the 1 gigahertz spectrum. This is mostly due to conductance losses (leakage from the copper trace to any other conducting structure) and Skin Effect. Dispersion is a phenomenon whereby spectral components travel at different velocities. The waveform looks smeared when it arrives at the receiver. Both of these "characteristics" play into a diminished and poorly received signal. By boosting the high freq. spectral components, the magnitude of these components can be diminished as the wave travels through the Transmission Line, but since it starts out larger than the lower frequency components, the composite signal arrives at the receiver looking the way it was intended. 570 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Pre-emphasis is done by simply increasing the maximum amplitude of the signal for one bit period. If the signal is 1 bit in duration, the amplitude is allowed to rise to a value which is some percentage greater in magnitude. At this point, if the signal is to stay at the same logic state, the driver sends a decreased magnitude signal, or nominal logic level. Every time a transition occurrs, the greater magnitude level is used. For all times after this that the same level is to be transmitted, the nominal magnitude is used. Priority the level of importance of an event. Most often, interrupts are assigned priorities. Privileged (or Supervisor) Mode Privileged mode allows programs to access all registers and execute all instructions supported by the processor. Normally, the operating system and low-level device drivers operate in this mode. Program Counter A register that places addresses on the bus to retrieve information stored within a program. PROGRAM Pin The PROGRAM pin is an active-Low input that forces clearing of the FPGA configuration memory and is used to initiate a configuration cycle. While PROGRAM is held Low, the FPGA drives INIT Low and continues to clear the configuration memory. When PROGRAM goes High, the FPGA finishes the current clear cycle, executes another complete clear cycle, goes into a WAIT state, and releases INIT. Random Jitter Jitter caused by Power Supply noise, temperature variations and crosstalk. Readback Initiating a readback causes the configuration memory to become accessible to be serially clocked out and read from the device, or (byte-wide in SelectMAP/Slave Parallel modes). The configuration memory contains the configuration data, facilitating a Read-Verification of the data. The configuration memory can also contain the CLB output logic states facilitating a Read-Capture of the internal logic states.Read-Verification and Read-Capture are used by the Hardware Debugger for hardware verification. For information on the readback specification and timing, refer to The Programmable Logic Data Book. For information on using the readback component in a design, refer to the Libraries Guide. For information on enabling the readback function in the Implementation Software, refer to the Development System Reference Guide. For information on using the Hardware Debugger refer to the Hardware Debugger Reference/User Guide. For information on connecting the XChecker cable for readback, refer to the Hardware Users Guide. Readback Data Configuration data read from a Virtex-II Pro device. The data is organized as configuration frames. Real Address Synonym for physical address. Real Mode In real mode, programs address physical memory directly. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 571 R Glossary Register A memory location that is part of a processor or an I/O device. In other words, it's not normal memory. Generally, each bit or set of bits within the register controls some behavior of the larger device. Relative Addressing An addressing mode that calculates a new address based on the position of an instruction within a program. Ringing Common name for the characterisitic waveform seen when a transmission line ends at a high impedance discontinuity. The signal first overshoots the target voltage, then sags below, then overshoots again--and continues this oscillating pattern with decreasing swing amplitude until finally settling at the target voltage. RISC (Reduced Instruction Set Computer) A type of microprocessor architecture that runs very fast by simplifying the number of its commands. PPC405 is a RISC microprocessor Rise Time The time it takes for a signal to rise from 10% of its total logic swing to 90% of its total logic swing. ROM Emulator A debugging tool that takes the place of-or emulates-the ROM on the target board. A ROM emulator acts very much like a debug monitor, except that it includes its own serial or network connection to the host. ROM Monitor A piece of debugging code which usually communicates via a serial connection to a host computer or terminal. Also see Debug Monitor. Routing The interconnection or the process of creating the desired interconnection of logic cells to make them perform the desired function. Routing follows after partitioning and placement. RTOS (Real Time Operating System) Also called real-time multitasking kernel. Software which ensures that time critical events are processed simultaneously and efficiently within a predictable response time. In general, the use of an RTOS simplifies the design process of a system by allowing the application to be divided into multiple independent tasks. SAN (Storage Area Network) A high-speed subnetwork of shared storage devices. A storage device is a machine that contains nothing but a disk or disks for storing data. A SAN's architecture works in a way that makes all storage devices available to all servers on a LAN (Local Area Network) or WAN (Wide Area Network). 572 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Schematic Graphic representation of a logic design in the form of interconnected gates, flip-flops, and larger blocks. Older and more visually intuitive alternative to the increasingly more popular equation-based or high-level language textual description of a logic design. SelectMAP Interface One of the configuration interfaces on the Virtex-II Pro device. This is a byte-serial interface. The pins in the SelectMAP interface can be used as user I/O after configuration has been completed or remain configured as a configuration interface. SelectRAM Xilinx-specific name for RAM implemented in CLBs. SERDES (Serializer/Deserializer) A common name for a high-speed transciever that performs both parallel-to-serial and serial-to-parallel conversion. Simulation Computer modeling of logic and (sometimes) timing behavior of logic driven by simulation inputs (stimuli or vectors). Single-Ended Method of signaling which, unlike differential signaling, only transmits signals over one net. Skin Effect Loss Electrical loss in a non-ideal medium due to skin effect. Skin effect is the tendancy for highfrequency signal components to travel close to the surface of the medium. Slice A subdivision of the Virtex-II Pro CLB. There are four vertical slices in each Virtex-II Pro CLB. Each slice contains two Logic Cells. SNR (Signal-to-Noise Ratio) A measure of signal strength relative to background noise. The ratio is usually measured in decibels (dB). If the incoming signal strength in microvolts is VS, and the noise level, also in microvolts, is VN, then the signal-to-noise ratio, SNR, in decibels, is given by the formula: SNR = 20 log10 ( V S V N ) Soft IP A synthesizable Intellectual Property which can be readily incorporated into an FPGA. Soft IP solves many of the time-to-market issues and also can simplify verification if a proper test bench is included. Software Interrupt An interruption of a program that is initiated by a software instruction. Software interrupts are commonly used to implement breakpoints and operating system entry points. Unlike true interrupts, they occur synchronously with respect to program execution. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 573 R Glossary SONET (Synchronous Optical NETwork) A standard for connecting fiber-optic transmission systems. SONET was proposed by Bellcore in the mid-1980s and is now an ANSI standard. SPECint95 and SPECfp95 Acronym for Standard Performance Evaluation Corporation, a nonprofit corporation set up by many computer and microprocessor vendors to create a standard set of benchmark tests. The most widely used set of tests, known as SPEC95, results in two sets of measurements, one for integer operations (SPECint95) and one for floating-point operations (SPECfp95). The SPEC95 benchmark tests are also called CPU95 tests. SRAM Static random access memory. Read-Write memory with data stored in latches. Faster than DRAM and with simpler timing requirements, but smaller in size and about four times more expensive than DRAM of the same capacity. Stack An area of memory used to implement a data structure that follows the last in, first out method of access. The stack is usually used by the processor to keep track of subroutine calls and returns. Stack Pointer A special purpose register that tracks the location of the last entry in the stack. Static Timing Detailed description of on-chip logic and interconnect delays. Submicron The smallest feature size is usually expressed in microns ( = one millionth of a meter, or a thousandth of a millimeter). The state of the art is moving from 0.35 to 0.25, and soon may reach 0.18. For comparison purposes, the wavelength of visible light is 0.4 to 0.8. One thousandth of an inch, or 1 mil, is 25.4. Sync Word A 32-bit word with a value that is used to synchronize the configuration logic. Synchronous Circuitry that changes state only in response to a common clock, as opposed to asynchronous circuitry that responds to a multitude of derived signals. Synchronous circuits are easier to design, debug, modify, and better tolerate parameter changes and speed upgrades than asynchronous circuits. Synthesis Optimization process of adapting a logic design to the logic resources available on the chip, like look-up tables, Longline, and dedicated carry. Synthesis precedes mapping. 574 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R TBUFs Buffers with a 3-state option, where the output can be made inactive. Used for multiplexing different data sources onto a common bus. The pulldown-only option can use the bus as a "wired AND" function. Termination Usually implemented with passive components, termination is used to interface drivers, receivers, and traces that have differing impedance values. Typically, device drivers and receivers do not match the impedance of the PCB trace that connects them. Termination resistors are employed to match the impedances of these components, maximizing signal transmission and reducing noise. Timing Relating to delays, performance, or speed. Timing Driven A design or layout method that takes performance requirements into consideration. TLB (Translation Lookaside Buffer) TLB is part of an MMU. It has a table used in a virtual memory system keeping track of the physical address page number associated with each virtual address page number. A TLB is used in conjunction with a cache whose tags are based on virtual addresses. Trace A PPC405 feature which supports tracing of the instruction stream being executed out of the instruction cache in real time. Trap 1. A program interrupt, usually an interrupt caused by some exceptional situation in the user program. In most cases, the OS performs some action, then returns control to the program. 2. Internally generated exceptions that deal with such instances as arithmetic overflow, divide by zero, and bound check failure. UART (Universal Asynchronous Receiver/Transmitter) An 8-bit parallel-to-serial and serial-to-parallel converter, combined with parity and startdetect circuitry, and sometimes even FIFO buffers. Used widely in asynchronous serial communications interfaces, such as modems. UI (Unit Interval) Unit of time corresponding to one bit period. A unit interval is the time it takes to send one bit. USB (Universal Serial Bus) A low-cost, low-speed, self-clocking bit-serial bus (1.5 MHz and 12 MHz) using four wires (VCC, ground, differential data) to daisy-chain up to 128 devices. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 575 R Glossary User Mode User mode restricts access to some registers and instructions. Normally, application programs operate in this mode. Virtual Address An intermediate address used to translate an effective address into a physical address. It consists of a process ID and the effective address. It is only used when address translation is enabled. Virtual Mode In virtual mode, programs address virtual memory and virtual-memory addresses are translated by the processor into physical-memory addresses. This allows programs to access much larger address spaces than might be implemented in the system. VME Older bus standard, popular with MC68000-based industrial computers. Von-Neuman Architecture Von-Neuman architecture has a shared bus for instruction and data access. Therefore simultaneous instruction and data transfer is not possible. WAN (Wide Area Network) A computer network that spans a relatively large geographical area. Typically, a WAN consists of two or more local-area networks (LANs). Watchdog Timer A hardware timer that is periodically reset by software. If the software crashes or hangs, the watchdog timer will expire, and the entire system will be reset automatically WDM (Wavelength Division Multiplexing) A type of multiplexing developed for use on optical fiber. WDM modulates each of several data streams onto a different part of the light spectrum. Word Four bytes, or 32 bits. Write Back A Cache write policy in which data written into the cache by the CPU is not written into main memory until that data line in the cache is to be replaced. WRITE Pin The WRITE pin is an input to Virtex-II Pro devices in the SelectMAP/Slave Parallel mode, indicating to the device which direction data is flowing on the Data bus. When WRITE is asserted (Low), data is entering the device (configuration). When WRITE is de-asserted (High), data is leaving the device (readback). If WRITE changes state when the device isn't expecting it, an abort occurs. For more information on the WRITE pin, refer to The Programmable Logic Data Book, and in this Handbook, Design Considerations, page 161. 576 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Write Through A Cache write policy. A technique for writing data from the CPU simultaneously into the cache and into main memory to assure coherency XChecker Cable The Xilinx XChecker Cable (model DLC4) is a serial download cable. The XChecker uses a serial 9-pin interface to the communication port of a host computer and two 8-pin headers for flying-wire connectors to a target board. The XChecker cable is supported by the Hardware Debugger software for performing Slave Serial configuration and readback of FPGAs. The XChecker cable is also supported by the JTAG Programmer software for performing Slave Serial and Boundary Scan configuration of FPGAs, and Boundary Scan programming of CPLDs. For more information on using the XChecker cable refer to the Hardware Users Guide and the Hardware Debugger Reference/Users Guide. XNF File Xilinx-proprietary description format for a logic design. Alternative is EDIF. UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 577 R 578 Glossary www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook Index Numerics 3-state buffers, 55 3-state driver (TBUF), 55 3-state output buffer, 310 8B/10B decoder, 30 8B/10B encoder, 29 A AC characteristics, 71 AC coupling defined, 553 of transmitter/receiver, 72 address mapping, 251 addressing modes, 33 defined, 553 addressing scheme, 251 ALU, 37 defined, 553 arithmetic logic, 53 ASIC defined, 553 Virtex-II Pro compared with, 11-15, 497 aspect ratios, 57 asynchronous defined, 553 clocks, 62 interrupt inputs, 38 reads in SelectRAM, 50 set/reset in register or latch, 41, 49 ATM defined, 554 IP core for, 24, 377, 380 available products Virtex-II Pro, 19 XC1700D Config PROM, 550 B ball grid array (BGA), 24 BER, 380 defined, 554 receiver switching, 84 REFCLK, 83 BF957 bank information diagram, 486 composite pinout diagram, 485 dedicated pins diagram, 487 flip-chip BGA package, 496 BGN files, 519 bidirectional LVDS, 367 bidirectional signals, 312 big endian, 39 defined, 554 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook instruction cache, 39 bit error rate See BER BIT files description, 518 disabling, 523 loading downward, 525 loading up or down, 526 loading upward, 527 bit swapping description, 525 disabling, 525 BitGen -b option, 519 -d option, 519 description, 517 disabling DRC, 519 DRC file, 519 encryption options, 370 -g option, 519-522 -h option, 523 input files, 518 -j option, 523 -l option, 523 -m option, 523 options, 519 output files, 518 PCF files, 518 persistence switch, 442 readback option, 442 standard bitstream, 438 syntax, 518 -w option, 523 bitstream defined, 554 configuration, 438 data frames, 439 encryption, 68, 368-372 loading encrypted, 372 standard, 438 block SelectRAM, 22, 56, 243-260 defined, 554 switching characteristics, 100 timing model, 135 timing parameters, 136 total available, 58 board routability, 505 board support package SeeBSP, 555 boundary scan instruction set, 415 mode, 67, 390 models, 516 Boundary Scan Description Language (BSDL), 516 boundary scan interface defined, 555 www.xilinx.com 1-800-255-7778 and readback, 441 BSDL files, 516 BSP, 379 defined, 555 and Platform Generator, 372 buffers, 60 3-state, 55 3-state output, 310 bidirectional LVDS, 367 global clock, 203 LDT, 368 output, 308 SelectI/O, 45 BUFG, 61 BUFGCE, 61, 215 BUFGMUX, 62 C cache defined, 555 and MMU, 37 controllers and PLB, 34 data write-through register, 37 data (PPC405 core), 19, 21, 36 instruction and debug logic, 39 big endian, 39 instruction (PPC405 core), 19, 21, 36 cache line, 21, 22 defined, 555 cache pollution and OCM, 33 capacitors decoupling, 500 carry chains, 52, 65 in one CLB, 55 logic, 52 multiplexer (MUXCY), 52 cascadable shift registers, 270 CCLK, 66, 389 defined, 555 and configuration, 395 and configuration mode, 390 and master serial programming mode, 403 timing, 392 CDR, 12, 19, 21, 29 defined, 555 channel bonding, 31 defined, 556 characteristic impedance See impedance 579 R characteristics AC, 71 DC, 71 electrical, 71 IOB input switching, 88 IOB output adjustments, 91 IOB output switching, 90 land pads, 506 performance, 77 PPC405 switching, 80 Rocket I/O switching, 83 switching, 79 checksum, 525 ChipScope Pro, 445 and CoreConnect, 445 classification and export considerations, 370 CLB, 22, 47 defined, 556 switching characteristics, 97 distributed RAM, 98 CLB/slice timing model, 126 clearing configuration memory, 392 CLK, 234 CLK2X, 229 CLKDV, 230 CLKFB, 225 CLKIN, 225 clock enable signal (CE), 49 clock nets, 65 clock networks, 202-221 clocks, 64, 202 buffer input, 205 de-skewing, 63, 222 distribution, 60, 202 forwarding, 357 frequency ranges, 64 frequency synthesis, 62 global buffers, 61, 203 global multiplexer buffer, 60 global networks, 202 input clock tolerances, 156 multiplexer waveform, 62, 214, 215 multiplexers, 202 output clock precision, 157 phase shifting, 63, 232 resources, 203 skew, 63 coherency, 37 defined, 556 combinatorial logic functions, 54 comma defined, 556 detection, 19, 21, 30 command register (CMD), 433 commands file, executing, 526 compiler defined, 556 memory, 267 580 configuration, 23, 66, 389 bitstream, 431 defined, 556 bitstream header, 438 block SelectRAM, 56 Boundary Scan mode, 390 clearing memory, 392 data frames, 431 data processing flow, 436 distributed SelectRAM, 49 dual-port, 50 -g option, 519-522 internal processing, 431 JTAG, 504 logic, 431 Master SelectMAP mode, 390 Master Serial mode, 390 mode, 67 mode pins, 389 modes, 66, 389, 390 multipliers, 59 of latches, 41 of registers, 41 option register (COR), 433 pin settings, 67 process, 391 register writes, 437 SelectI/O, 42 sequence, 68 single-port, 50 Slave SelectMAP mode, 390 Slave Serial mode, 390 with MultiLINX, 431 configuration registers, 432 CMD, 433 COR, 433 CRC, 434 CTL, 434 FAR, 434 FDRI, 434 FDRO, 434 FLR, 433 LOUT, 434 MASK, 434 STAT, 434 writes, 437 conflict resolution, 247 constraining placement, 275 content-addressable memory (CAM), 269 control pins, 58 control register (CTL), 434 control signals, 222 controlled impedance, 45 controlled output impedance, 45 conventions typographical, 8 CORE Generator system, 372-387 CoreConnectTM bus architecture, 35 defined, 557 and ChipScope Pro, 445 and Platform Generator, 372 www.xilinx.com 1-800-255-7778 CPM interface, 34 CRC, 28, 32 16-bit polynomial, 440 and transmit latency, 85 register, 434 sequence, 439 crosstalk, 504 defined, 558 CS pin, 522 defined, 558 cyclic redundancy check See CRC D data cache write-through register, 37 Data Encryption Standard (DES), 68, 368 data frames, 439 data sheets Virtex-II Pro, 19 XC18V00 Series PROMs, 529 DC characteristics, 71, 72 DC coupling defined, 558 of transmitter/receiver, 72 DC input and output levels, 74 DCI, 44, 333-348 I/O buffer library, 340 I/O standards, 46 software support, 340 DCM, 20, 23, 62, 222, 222-243 clock de-skew, 222, 223 control signals, 222 frequency ranges, 64 frequency synthesis, 62, 222, 228 legacy support, 226 location, 65 miscellaneous timing parameters, 158 operating frequency ranges, 155 overview, 222 phase shifting, 63, 222, 232 port signals, 225 timing model, 154 timing parameters, 104, 155 waveforms, 241 DCR defined, 558 and processor block timing model, 114 bus interface, 34 DDR I/O, 40, 348-362 input, 349 output, 351 output with 3-state control, 353 SDRAM, 357 debug interface, 35 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R debug logic, 38 debugger defined, 558 hardware, 523 JTAG interface extensions, 35 debugging, 23, 68 using ChipScope Pro, 445 decoupling capacitors, 500 decryptor, 68 dedicated AND (MULT_AND), 53 dedicated OR gate (ORCY), 54 dedicated pins, 389 diagrams, 463, 467, 471, 475, 479, 483, 487 delays, 88 input, 88 IOB, 77 output, 90 DES, 68, 369 deserializer, 30 de-skew, 63 de-skew circuit, 224 DESYNCH command, 440 deterministic jitter defined, 84 device control register See DCR device/package combinations, 24 differential signaling, 368 defined, 559 Digital Clock Manager See DCM Digitally Controlled Impedance See DCI DIN pin defined, 559 direct connect lines, 65 disparity control, 29 distributed SelectRAM, 49, 260-269 DLLs characteristics, 224 source clock input, 225 DONE pin defined, 559 double data rate I/O See DDR I/O DOUT pin defined, 559 DOUT/BUSY pin defined, 559 DRC disabling for BitGen, 519 DRC file, 519 DSOCM defined, 560 See OCM: data side DSP, 14, 20, 22, 34, 59, 377, 378, 383 defined, 560 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook dual-port RAM, 49, 56 dynamic read operations, 271 E EDIF, 253, 254, 265, 267, 274, 357, 374, 375, 376 defined, 560 effective address, 37 defined, 560 EIC interface, 34 electrical characteristics, 71 electrostatic discharge See ESD embedded multipliers, 296 timing model, 139 timing parameters, 139 encryption, 68 BitGen options, 370 bitstream, 368-372 endianness See big endian and little endian ESD, 43 defined, 560 export considerations, 370 F fall time defined, 561 REFCLK, 83 fast slew rate, 91, 101 FDDRCPE, 356 FDDRRSE, 356 FF1152 bank information diagram, 478 composite pinout diagram, 477 dedicated pins diagram, 479 flip-chip fine-pitch BGA package, 494 FF1517 bank information diagram, 482 composite pinout diagram, 481 dedicated pins diagram, 483 flip-chip fine-pitch BGA package, 495 FF672 bank information diagram, 470 composite pinout diagram, 469 dedicated pins diagram, 471 fine-pitch BGA package, 492 FF896 bank information diagram, 474 composite pinout diagram, 473 dedicated pins diagram, 475 fine-pitch BGA package, 493 FG256 bank information diagram, 462 composite pinout diagram, 461 dedicated pins diagram, 463 fine-pitch BGA package, 490 www.xilinx.com 1-800-255-7778 pinouts, 451 FG456 bank information diagram, 466 composite pinout diagram, 465 dedicated pins diagram, 467 fine-pitch BGA package, 491 FIFO, 32, 377 defined, 561 application notes, 254 generating async, 243 in block RAM, 78 in SRL, 78 sync and async using CORE Generator, 260 transmit, 29 fine phase adjustment, 63, 232 flip-chip advantages, 497 flip-chip packages, 24, 497 flip-flop, 22, 40, 43, 49 flip-flops in one CLB, 55 frame address register (FAR), 434 Frame Data Register Input (FDRI), 434 Frame Data Register Output (FDRO), 434 frame length register (FLR), 433 frequency ranges, 64 frequency synthesis, 62, 222 fully synchronous shift registers, 276 function generators, 52 G global clock buffers, 61, 203 global clock multiplexer buffer, 60 global clock nets, 65, 202 global clocks, 23 input to output delay, 101 input to output timing parameters, 152 setup and hold, 103 setup and hold timing parameters, 153 global routing matrix, 23 global routing resources, 65 GTL, 321 GTL+, 322 H Hardware Debugger, 523 Harvard architecture, 19, 36 defined, 563 HDC pin defined, 563 581 R hierarchical routing resources, 65 horizontal routing, 65 HSTL_I, 322, 325 HSTL_II, 323, 326 HSTL_III, 324, 326 HSTL_IV, 324, 327 HSWAP_EN pin, 43, 66 HyperTransportTM defined, 563 See LDT I I/O banks, 43, 44, 447 I/O Buffer Information Specification See IBIS I/O standards DCI, 46 differential signaling, 22 single-ended, 22, 304 supported, 39 I/Os user, 24 IBIS, 511, 512 advantages, 512 file structure, 512 generation, 512 I/V and dV/dt curves, 513 ramp keyword, 513 simulations, 514 simulators, 515 IEEE 1149.1, 516 IEEE 1149.1 - 1993, 23 IEEE 1532, 23, 67, 443, 516 impedance, 45 defined, 563 controlled, 45 receiver termination, 30 INIT pin defined, 564 input clock tolerances, 106 timing parameters, 156 input DDR, 349 input delays, 88 input files BitGen, 518 PROMGen, 524 Instruction Set, 21, 33 instruction set, 36, 37 defined, 564 boundary scan, 415 interrupts ansynchronous, 38 IOBs, 22, 39 3-state timing parameters, 148 delays, 77 input switching characteristics, 88 input timing parameters, 143 output switching characteristics, 90, 91 output timing parameters, 145 timing model, 141 582 IOBUF, 312 IOSTANDARD attribute, 342 ISOCM defined, 564 See OCM: instruction side J jitter, 107 defined, 565 deterministic receive, 84 serial data out, 85 random defined, 571 serial data out, 85 JTAG, 504 defined, 565 instruction, 68 mode, 67 test access port, 100 junction temperature specifications, 71 K keys, 372 creating, 370 L land pad characteristics, 506 land pads, 506 latch set/reset, 49 latches, 49 configuration, 41 latency receive, max, 84 transmit, max, 85 LDC pin defined, 565 LDT, 368 defined, 565 buffers, 368 DC specifications, 75 implementation, 368 software primitives, 368 See also HyperTransport legacy data output register (LOUT), 434 legacy support, 226 library primitives and submodules, 213 Lightning Data Transport See LDT little endian, 39 defined, 566 www.xilinx.com 1-800-255-7778 LL files, 518, 523 loading, 372 locked output, 225 logic allocation file, 523 logic resources in one CLB, 55 logical address See effective address long lines, 65 look-up table See LUT loopback See Rocket I/O transceiver loopback low voltage differential signaling (LVDS), 363 LUTs, 269 defined, 566 as shift registers, 269-279 in one CLB, 55 LVCMOS, 42 LVCMOS 2.5V, 88 LVCMOS15, 332 LVCMOS18, 332 LVCMOS25, 333 LVCMOS33, 333 LVDS, 363-368 defined, 566 3-state buffer termination, 367 bidirectional, 367 DC specifications, 75 extended DC specifications, 75 primitives, 363 receiver termination, 364 transmitter termination, 365 LVTTL, 43, 331 M mask file, 523 MASK register (MASK), 434 Master SelectMAP mode, 390 Master Serial mode, 67, 390 memory clearing, 392 memory compiler program, 267 memory management unit See MMU MGT (multi-gigabit transceiver) See Rocket I/O transceiver MicroBlazeTM, 384, 385, 386 defined, 567 MMU, 37-38 defined, 567 mode pins, 66 modes boundary scan, 67 configuration, 390 boundary scan, 390 master SelectMAP, 390 master serial, 67, 390, 403 slave SelectMAP, 390 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R slave serial, 66, 390, 404 JTAG, 67 NO_CHANGE, 246 operating, 64 programming See modes: configuration READ_FIRST, 245 WRITE_FIRST, 245 MSK files, 519 MULT_ANDs in one CLB, 55 MultiLINX cable, 431 defined, 567 Multiplexers, 279-289 multiplexers, 52, 279 clocks, 202 large, 279 primary/secondary global, 206 wide-input, 284 multipliers, 59 blocks, 60 configuration, 59 embedded, 296 location, 59 switching characteristics, 99 Multipliers, embedded, 296-303 N National Institute of Standards and Technology (NIST), 368 NO_CHANGE mode, 246 NO_CHANGE option, 58 O OBUF, 308 OBUFT, 310 OCM, 33 defined, 568 and processor block timing model, 114 cache pollution reduction, 33 data side, 34 instruction side, 34 interfaces, 34 thrashing reduction, 33 See also PowerPC 405 processor block on-chip buses, 55 on-chip decryptor, 68 on-chip memory See OCM on-chip peripheral bus See OPB on-chip termination, 45 OPB defined, 568 and MicroBlazeTM, 384 IP cores for, 379 IP for, 386 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook operating conditions recommended, 72 operating frequency ranges, 155 operating modes, 64 optimization defined, 568 ORCY, 54 ordering information, 25 XC1700D, 550 output buffer (OBUF), 308 output clock jitter, 107 phase alignment, 107 output clock precision timing parameters, 157 output DDR, 351 with 3-state control, 353 output delays, 90 output drive strength, 314 output files BitGen, 518 name, PROMGen, 526 overwriting, 523 PROMGen, 524 output power/ground pairs, 316 overshoot defined, 568 overview of user guide, 7 P package specifications, 489 BF957, 496 FF1152, 494 FF1517, 495 FF672, 492 FF896, 493 FG256, 490 FG456, 491 package/device combinations, 24 packages, 24 flip-chip, 24, 497 thermal considerations, 497 wire-bond, 24 packets, 438 data, 440 headers, 440 pads, 506 defined, 568 Parallel Cable IV, 402 defined, 568 parallel termination, 503 parallel terminations, 45 parameters miscellaneous timing, 108 pin-to-pin output, 101 timing, 104 partial reconfiguration, 68 PC20-84 specification, 530 PCB layout considerations, 499 PCF files BitGen, 518 www.xilinx.com 1-800-255-7778 PCI defined, 569 PCI33_3, 331 PCI66_3, 331 PCIX, 331 performance characteristics, 77 persist option, 390 phase shifting, 63, 222, 232 physical address defined, 569 pin-locking defined, 569 pinout diagrams, 459 pinout information, 447 pins, 389 chip enable See CS Pin, 558 control, 58 CS, 522 defined, 558 dedicated, 389 DIN defined, 559 DONE defined, 559 DOUT defined, 559 DOUT/BUSY defined, 559 dual-function, 390 HDC defined, 563 HSWAP_EN, 43, 66 INIT defined, 564 LDC defined, 565 mode, 66 power, 392 PROGRAM defined, 571 types, 448 VBATT, 68 WRITE defined, 576 pin-to-pin input parameters, 103 pin-to-pin output parameters, 101 pin-to-pin timing model, 151 place-and-route software, 65 placement constraints, 275 defined, 569 Platform Generator, 372 and CoreConnect, 372 PLB defined, 570 interfaces, 34 583 R port addressing scheme, 251 port aspect ratios, 57 port signals, 225 power analysis software, 511 power consumption, 61 power pins, 392 power supply requirements, 73 power-on ramp rate, 73 PowerPC 405 processor block, 21, 180-202 cache data, 19, 21, 36 instruction, 19, 21, 36 debug resources, 22 features summary, 19 instantiation template, Verilog, 193 instantiation template, VHDL, 185 interface signals, 180 MMU (Memory Management Unit), 22 OCM (On-Chip Memory), 22 overview, 33 PPC405 CPU, 21 storage control, 21 switching characteristics, 80 timers, 22 timing model, 114 pre-emphasis, 19, 21 defined, 570 primitives LVDS, 363 PRM files, 524 PROGRAM pin defined, 571 PROMGen -b option, 525 -c option, 525 -d option, 525 description, 523, 524 examples, 527 flow diagram, 523 -help option, 526 input files, 524 -l option, 526 -n option, 526 -o option, 526 options, 525 output file name, 526 output files, 524 -p option, 526 -r option, 527 -s option, 527 supported families, 523 -u option, 527 -x option, 527 PROMs bit swapping, 525 data sheet, 529 files, description, 524 formats, 526 loading files, 527 multiple files, 527 584 package specifications, 529 sizes, 527 R RAM dual-port, 49 single-port, 49 rawbits file, 519 RBT files, 518, 519 read operations, 57 dynamic, 271 static, 271 READ_FIRST mode, 245 READ_FIRST option, 58 readback, 23, 68, 441 defined, 571 capture, 441 enabling in software, 442 IEEE 1532 flow, 443 regular flow, 442 verification, 441 with Boundary Scan, 442 recommended operating conditions, 72 reconfiguration partial, 68 REFCLK timing (waveform), 83 reference clock timing See REFCLK timing register defined, 572 set/reset, 49 registers configuration, 41, 432 DDR, 40 shift, 51 reset interface, 34 revision history data sheet, 25, 69, 109 ringing defined, 572 on PC board signals, 502 rise time defined, 572 REFCLK, 83 Rocket I/O transceiver, 162-180 available ports, 162 block diagram, 28, 122 byte mapping, 175 CDR (clock/data recovery), 29 channel bonding, 31 clock correction, 31 clock synthesizer, 29 clocking, 175 2-byte, VHDL template, 177 clock ratio, 176 using DCM, 176 configuration, 32 CRC, 32 features summary, 19, 21 www.xilinx.com 1-800-255-7778 functional description, 27-32 I/O standards supported, 27 loopback, 30 defined, 566 modifiable primitives, 171 number of per FPGA, 19 power down, 32 power sequencing, 32 primitive attributes, 166 receiver, 30 receiver buffer, 30 reset, 32 switching characteristics, 83 timing model, 121 transmitter, 29 transmitter buffer, 32 routability guidelines, 505 routing, 65 defined, 572 challenges, 505 matrix, 23 resources, 65 strategy, 506 RST, 225 S segmented routing, 65 SelectI/O buffers, 45 configuration, 42 single-ended resources, 303-333 SelectI/O Ultra technology, 20 SelectMAP See configuration modes SelectRAM, 20 block, 56 distributed, 49 in one CLB, 55 reads and writes in, 50 total available, 58 SERDES, 19, 21 defined, 573 serial transceiver See Rocket I/O transceiver serializer, 29 series termination, 503 set/reset asynchronous, in register or latch, 41 in register or latch, 49 synchronous, in register or latch, 41 set/reset (SR), 49 shift registers, 51 cascadable, 270 cascading, 51 fully synchronous, 276 in one CLB, 55 operation, 270 static length, 277 signals bidirectional, 312 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R simulation, 14, 79, 96, 241, 249 defined, 573 simultaneous switching output (SSO), 316 single event upset (SEU), 43 single-ended defined, 573 I/O standards, 22, 304 SelectI/O resources, 303-333 single-port RAM, 49 Slave SelectMAP mode, 390 Slave Serial mode, 66, 390 slew rate, 314 slices, 289 defined, 573 description, 47 in one CLB, 55 SO20 specification, 531 software place-and-route, 65 solder balls, 505 SOP chains, 54, 65 in one CLB, 55 specifications PC20-84, 530 PROM packages, 529 SO20, 531 VQ44, 532 SRL16, 270 SRLC16, 270 SSTL2_I, 329 SSTL2_II, 330 SSTL3_I, 328 SSTL3_II, 328 standard adjustments, 89, 91 standard bitstream, 438 standards supported I/O, 39 start-up sequence, 440 STARTUP_WAIT attribute, 225 static length shift registers, 277 static read operations, 271 status register (STAT), 434 Sum of Products (SOP), 54, 289-296 summary of Virtex-II Pro features, 19 supply voltage specifications, 71 switching characteristics, 79 synchronous defined, 574 set/reset in register or latch, 41, 49 synchronous DRAM, 357 series, 503 techniques, 315 terminations on-chip, 45 parallel, 45 Test Access Port (TAP), 23 thermal considerations, 497 thermal management, 498 thrashing and OCM, 33 Timing Analyzer, 79, 113 timing models, 113 block SelectRAM, 135 CLB / slice, 126 DCM, 154 embedded multiplier, 139 IOB, 141 pin-to-pin, 151 PPC405, 114 Rocket I/O MGT, 121 timing parameters, 104 block SelectRAM, 136 DCM, 155 embedded multiplier, 139 general slice, 128 global clock input to output, 152 global clock setup and hold, 153 input clock tolerances, 156 IOB 3-state, 148 IOB input, 143 IOB output, 145 miscellaneous, 108 miscellaneous DCM, 158 output clock precision, 157 PPC405, 115 Rocket I/O transceiver, 122 slice distributed RAM, 131 slice SRL, 134 TMULT, 139 transceiver See Rocket I/O transceiver transmission line effects, 315, 502 TRCE, 113 Triple Data Encryption Algorithm (TDEA), 369 Triple DES, 369 typographical conventions, 8 vertical routing, 65 VHDL and Verilog templates, 217, U X user I/Os, 24 XC18V00 Series PROMs, 529 T V TBUF switching characteristics, 100 TBUFs defined, 575 in one CLB, 55 termination defined, 575 parallel, 503 VBATT, 372 VBATT pin, 68 VCC decoupling, 500 VCCO, 43, 315 verification using ChipScope Pro, 445 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook www.xilinx.com 1-800-255-7778 238, 254, 263, 267, 278, 286, 292, 302, 357 Virtex-II Pro and Virtex-II compared, 27 architectural overview, 21 available products, 19 compared with ASIC, 11-15, 497 Data Sheet DC and switching characteristics, 71-109 functional description, 27-69 introduction and overview, 19-?? DCI, 44, 333-348 DES, 368 device/package combinations, 24 features summary, 19 I/O banks, 44 IP core support, 24 LUTs, 269 maximum number of I/Os, 24 multiplexers, 279 ordering information, 25 package specifications, 489 pinout diagrams, 459 pinouts, 447 platform FPGA technology, 20 slices, 289 VQ44 specification, 532 VREF, 43, 315 VRN, 45 VRP, 45 W weak-keeper circuits, 42 wide logic functions, 52 wide-input multiplexers, 284 wire-bond packages, 24 Write Enable (WE), 49 write operations, 57 WRITE pin defined, 576 WRITE_FIRST mode, 245 WRITE_FIRST option, 57 585 R 586 www.xilinx.com 1-800-255-7778 UG012 (v1.0) January 31, 2002 Virtex-II Pro Platform FPGA Handbook R Xilinx Sales Offices Headquarters Ledgewood, NJ Tel: (973) 584-7199 Fax: (973) 584-1390 2100 Logic Drive San Jose, CA 95124 Raleigh, NC Tel: (919) 846-3922 Fax: (919) 846-8316 Tel: (408) 559-7778 Fax: (408) 559-7114 TWX: (510) 600-8750 Brecksfield, OH Tel: (330) 659-3131 Fax: (330) 659-9254 North America Madison, AL Tel: (256) 722-4050 Fax: (256) 722-9912 Portland, OR Tel: (503) 293-9016 Fax: (503) 293-3858 Phoenix, AZ Tel: (480) 753-4503 Fax: (480) 753-4504 West Chester, PA Tel: (610) 430-3300 Fax: (610) 430-0470 Irvine, CA Tel: (949) 727-0780 Fax: (949) 727-3128 Dallas, TX Tel: (972) 960-1043 Fax: (972) 960-0927 San Diego, CA Tel: (858) 558-5974 Fax: (858) 558-6418 Salt Lake City, UT Tel: (801) 268-3434 Fax: (801) 266-9021 Sunnyvale, CA Tel: (408) 245-9850 Fax: (408) 245-9865 Bellevue, WA Tel: (425) 451-7000 Fax: (425) 990-8989 Greenwood Village, CO Tel: (303) 220-7541 Fax: (303) 220-8641 Winter Park, FL Tel: (407) 673-8661 Fax: (407) 673-8663 Schaumburg, IL Tel: (847) 605-1972 Fax: (847) 605-1976 Deephaven, MN Tel: (612) 473-4816 Fax: (612) 473-5060 Marriottsville, MD Tel: (410) 442-9748 Fax: (410) 442-9749 Nashua, NH Tel: (603) 891-1098 Fax: (603) 891-0890 Oakville, Ontario Canada Tel: (905) 337-0894 Fax: (905) 337-3554 Kanata, Ontario Canada Tel: (613) 271-5264 Fax: (613) 592-4256 European Headquarters Benchmark House, 203 Brooklands Rd. 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