Advance v0.7 IGLOO nano Low-Power Flash FPGAs (R) with Flash*Freeze Technology Features and Benefits Advanced I/Os * 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--up to 4 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V * I/O Registers on Input, Output, and Enable Paths * Selectable Schmitt Trigger Inputs * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the IGLOO Family Low Power * * * * * nanoPower Consumption--Industry's Lowest Power 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content * Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode Small Footprint Packages * As Small as 3x3 mm in Size Wide Range of Features * 10 k to 250 k System Gates * Up to 36 kbits of True Dual-Port SRAM * Up to 71 User I/Os Clock Conditioning Circuit (CCC) and PLL Reprogrammable Flash Technology * * * * * Up to Six CCC Blocks, One with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 250 MHz) 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off Embedded Memory In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x 18 organization) Enhanced Commercial Temperature Range * -20C to +70C * Segmented, Hierarchical Routing and Clock Structure Table 1 * IGLOO nano Devices AGLN010 AGLN015 AGLN020 AGLN030 1 AGLN060 AGLN125 AGLN250 10 k 15 k 20 k 30 k 60 k 125 k 250 k Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048 VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144 2 4 4 5 10 16 24 - - - - 18 36 36 - - - - 4 8 8 1k 1k 1k 1k 1k 1k 1k - - - - Yes Yes Yes IGLOO nano Devices System Gates Flash*Freeze Mode (typical, W) RAM kbits (1,024 bits) 2 4,608-Bit Blocks 2 FlashROM Bits Secure (AES) ISP 2 Integrated PLL in CCCs 2,3 VersaNet Globals - - - - 1 1 1 4 4 4 6 18 18 18 I/O Banks 2 3 3 2 2 2 4 Maximum User I/Os (packaged device) 34 49 52 77 71 71 68 Maximum User I/Os (Known Good Die) 34 - 52 83 71 71 68 UC36 QN48 CS81 CS81 CS81 QN68 VQ100 VQ100 VQ100 Package Pins UC/CS QFN VQFP UC81, CS81 UC81, CS81 QN68 QN48, QN68 VQ100 Notes: 1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer to "IGLOO nano Ordering Information" on page III. 2. AGLN030 and smaller devices do not support this feature. 3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. 4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe handbooks. AGLN030 and smaller devices do not support this feature. April 2009 (c) 2009 Actel Corporation I IGLOO nano Low-Power Flash FPGAs I/Os Per Package AGLN010 AGLN015 AGLN020 AGLN030 1 AGLN060 AGLN125 AGLN250 Known Good Die 34 - 52 83 71 71 68 UC36 23 QN48 34 IGLOO nano Devices 34 QN68 49 49 49 UC81 52 66 CS81 52 66 60 60 60 77 71 71 68 VQ100 Notes: 1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer to "IGLOO nano Ordering Information" on page III. 2. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO Handbook to ensure compliance with design and board migration requirements. 3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of singleended user I/Os available is reduced by one. 4. "G" indicates RoHS-compliant packages. Refer to "IGLOO nano Ordering Information" on page III for the location of the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only. Table 2 * IGLOO FPGAs Package Sizes Dimensions Packages UC36 UC81 CS81 QN48 QN68 VQ100 Length x Width (mm\mm) 3x3 4x4 5x5 6x6 8x8 14 x 14 9 16 36 36 64 196 Pitch (mm) 0.4 0.4 0.5 0.4 0.4 0.5 Height (mm) 0.80 0.80 0.80 0.90 0.90 1.20 Nominal Area (mm2) II A d v a n c e v 0 .7 IGLOO nano Low-Power Flash FPGAs IGLOO nano Ordering Information AGLN250 V2 _ Z VQ G 100 I Application (Temperature Range) Blank = Commercial (-20C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type UC = Micro Chip Scale Package (0.4 mm pitch) CS = Chip Scale Package (0.5 mm pitch) QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) DIELOT = Known Good Die Z = nano devices without enhanced features1 Blank = Standard Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOO nano Devices AGLN010 = 10,000 System Gates AGLN015 = 15,000 System Gates AGLN020 = 20,000 System Gates AGLN030 = 30,000 System Gates AGLN060 = 60,000 System Gates AGLN125 = 125,000 System Gates AGLN250 = 250,000 System Gates Notes: 1. For the AGLN060, AGLN125, and AGLN250, the Z feature grade does not support the enhanced nano features of Schmitt trigger input, bus hold, cold-sparing, and hot-swap I/O capability. The AGLN030 Z feature grade does not support Schmitt trigger input and bus hold. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the device. 2. Marking Information: IGLOO nano V2 devices do not have V2 marking, but IGLOO nano V5 devices are marked with a V5 designator. Device Marking Actel normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of the device marking will be used that includes the required legal information and as much of the part number as allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples. Advance v0.7 III IGLOO nano Low-Power Flash FPGAs Figure 1 shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the device/package combination ordered. Device Name (six characters) Package Wafer Lot # Figure 1 * ACTELXXX AGL030YWW UCG81XXXX XXXXXXXX Country of Origin Date Code Customer Mark (if applicable) Example of Device Marking for Small Form Factor Packages IGLOO nano Product Available in the Z Feature Grade Devices Packages AGLN030 AGLN060 AGLN125 AGLN250 QN48 - - - QN68 - - - UC81 - - - CS81 CS81 CS81 CS81 VQ100 VQ100 VQ100 VQ100 Temperature Grade Offerings Package AGLN010 AGLN015 AGLN020 AGLN030 AGLN060 AGLN125 AGLN250 UC36 C, I - - - - - - QN48 C, I - - C, I - - - QN68 - C, I C, I C, I - - - UC81 - - C, I C, I - - - CS81 - - C, I C, I C, I C, I C, I VQ100 - - - C, I C, I C, I C, I Notes: 1. C = Commercial temperature range: -20C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. IV A d v a n c e v 0 .7 1 - IGLOO nano Device Overview General Description The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultralow-power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low-power consumption while the IGLOO nano device is completely functional in the system. This allows the IGLOO nano device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, lowpower, single-chip solution that is live at power-up (LAPU). The IGLOO nano device is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os. IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. Features such as smaller footprint packages designed with two-layer PCBs in mind, power consumption measured in nanoPower, Schmitt trigger, and bus hold functionality make these devices ideal for deployment in applications that require high levels of flexibility and low cost. Flash*Freeze Technology The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode. IGLOO nano devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state, tristate, HIGH, or LOW. The availability of low-power modes, combined with reprogrammability, a single-chip and singlevoltage solution, and small-footprint packages make IGLOO nano devices the best fit for portable electronics. A dv a n c e v 0. 7 1-1 IGLOO nano Device Overview Flash Advantages Low Power Flash-based IGLOO nano devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO nano devices also have low dynamic power consumption to further maximize power savings; power is reduced even further by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO nano device the lowest total system power offered by any FPGA. Security Nonvolatile, flash-based IGLOO nano devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO nano devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO nano devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO nano devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO nano devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO nano devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO nano device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of IGLOO nano devices. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. IGLOO nano devices, with FlashLock and AES security, are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOO nano device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO nano FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Actel flash-based IGLOO nano devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO nano devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO nano devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO nano flash FPGAs enable the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 s) and the device retains configuration and data in registers and RAM. 1 -2 A dv a n c e v 0. 7 IGLOO nano Device Overview Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from external memory components; instead it retains all necessary information to resume operation immediately. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based IGLOO nano devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes IGLOO nano devices cost-effective ASIC replacement solutions, especially for applications in the consumer, networking/communications, computing, and avionics markets. With a variety of devices under $1, Actel IGLOO nano FPGAs enable cost-effective implementation of programmable logic and quick time to market. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO nano flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO nano FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO nano device offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO nano FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO nano architecture provides granularity comparable to standard-cell ASICs. The IGLOO nano device consists of five distinct and programmable architectural features (Figure 1-3 on page 1-5 to Figure 1-4 on page 1-5): * Flash*Freeze technology * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO nano core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC(R) family of third-generation- The AGLN030 and smaller devices do not support PLL or SRAM. A dv a n c e v 0. 7 1-3 IGLOO nano Device Overview architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V) programming of IGLOO nano devices via an IEEE 1532 JTAG interface. Bank 1* I/Os Bank 1 Bank 0 VersaTile User Nonvolatile FlashROM Flash*Freeze Technology Charge Pumps CCC-GL Bank 1 Note: *Bank 0 for the AGLN030 device Figure 1-1 * IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030) Bank 1 I/Os Bank 2 Bank 0 VersaTile User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps CCC-GL Bank 1 Figure 1-2 * IGLOO Device Architecture Overview with Three I/O Banks and No RAM (AGLN015 and AGLN020) 1 -4 A dv a n c e v 0. 7 IGLOO nano Device Overview . Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 0 Bank 1 VersaTile Bank 1 Figure 1-3 * IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125) Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 1 Bank 3 I/Os ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology VersaTile Charge Pumps Bank 2 Figure 1-4 * IGLOO Device Architecture Overview with Four I/O Banks (AGLN250) A dv a n c e v 0. 7 1-5 IGLOO nano Device Overview Flash*Freeze Technology The IGLOO nano device has an ultra-low-power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks can still be driven and can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 2 W in this mode. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned. Actel IGLOO Nano FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-5 * IGLOO nano Flash*Freeze Mode VersaTiles The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOO nano VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-6 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR Figure 1-6 * VersaTile Configurations 1 -6 A dv a n c e v 0. 7 Y D-FF IGLOO nano Device Overview User Nonvolatile FlashROM Actel IGLOO nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard IGLOO nano IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the AGLN030 and smaller devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOO nano development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature enables the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOO nano devices (except the AGLN030 and smaller devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the AGLN030 and smaller devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC Higher density IGLOO nano devices using either the two I/O bank or four I/O bank architectures provide designers with very flexible clock conditioning capabilities. AGLN060, AGLN125, and AGLN250 contain six CCCs. One CCC (center west side) has a PLL. The AGLN030 and smaller devices use different CCCs in their architecture (CCC-GL). These CCC-GLs contain a global MUX but do not have any PLLs or programmable delays. A dv a n c e v 0. 7 1-7 IGLOO nano Device Overview For devices using the six CCC block architecture, these are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections to the CCC block, which are located near the CCC. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis (for PLL only) Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) * Maximum acquisition time is 300 s (for PLL only) * Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns (for PLL only) * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC (for PLL only) Global Clocking IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). The I/Os are organized into banks with two, three, or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of various single-data-rate applications for all versions of nano devices and double-data-rate applications for the AGLN060, AGLN125, and AGLN250 devices. IGLOO nano devices support LVTLL and LVCMOS I/O standards, are hot-swappable, and support cold-sparing and Schmitt trigger. Wide Range I/O Support Actel nano devices support JEDEC-defined wide range I/O operation. IGLOO nano devices support both the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. 1 -8 A dv a n c e v 0. 7 IGLOO nano Device Overview Part Number and Revision Date Part Number 51700110-001-6 Revised April 2009 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (Advance v0.7) Page Advance v0.6 (February 2009) The -F speed grade is no longer offered for IGLOO PLUS devices. The speed grade column and note regarding -F speed grade were removed from "IGLOO nano Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. III, IV Advance v0.5 (February 2009) The QN100 package was removed for all devices. Advance v0.4 (December 2008) N/A Table 1 * IGLOO nano Devices was updated to change the maximum user I/Os for AGLN030 from 81 to 77. I The "Device Marking" section is new. III The following table note was removed from Table 1 * IGLOO nano Devices: "Six chip (main) and three quadrant global networks are available for AGLN060 and above." I The CS81 package was added for AGLN250 in the "IGLOO nano Product Available in the Z Feature Grade" table. IV Advance v0.3 The second table note in Table 1 * IGLOO nano Devices was revised to state, (November 2008) "AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. AGLN030 and smaller devices do not support this feature." I The I/Os per package for CS81 were revised to 60 for AGLN060, AGLN125, and AGLN250 in the "I/Os Per Package"table. II The "Advanced I/Os" section was updated to include wide power supply voltage support for 1.14 V to 1.575 V. I The AGLN030 device was added to product tables and replaces AGL030 entries that were formerly in the tables. I to IV The "I/Os Per Package"table was updated for the CS81 package to change the number of I/Os for AGLN060, AGLN125, and AGLN250 from 66 to 64. II Advance v0.2 (October 2008) Advance v0.1 (October 2008) The "Wide Range I/O Support" section is new. 1-8 The following tables and sections were updated to add the UC81 and CS81 packages for AGL030: N/A "IGLOO nano Devices" "I/Os Per Package" "IGLOO nano Product Available in the Z Feature Grade" "Temperature Grade Offerings" The "I/Os Per Package" table was updated to add the following information to table note 4: "For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only." II The "IGLOO nano Product Available in the Z Feature Grade" section was updated to remove QN100 for AGLN250. IV The device architecture figures, Figure 1-3 * IGLOO Device Architecture Overview 1-4 with Two I/O Banks (AGLN060, AGLN125) through Figure 1-4 * IGLOO Device through Architecture Overview with Four I/O Banks (AGLN250), were revised. 1-5 Figure 1-1 * IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030) is new. A dv a n c e v 0. 7 1-9 IGLOO nano Device Overview Previous Version Advance v0.1 (continued) 1 -1 0 Changes in Current Version (Advance v0.7) Page The "PLL and CCC" section was revised to include information about CCC-GLs in AGLN020 and smaller devices. 1-7 The "I/Os with Advanced I/O Standards" section was revised to add information about IGLOO nano devices supporting double-data-rate applications. 1-8 A d v a n c e v 0. 7 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. 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