PFE600-12-054RA - POWER-ONE

BCD.00036_AG Sep-11-2013 1 www.power-one.com

DATA SHEET

The PFE600-12-054xA is a 600 Watt, AC to DC power-factor-corrected

(PFC) power supply that converts standard AC mains power into a

main output of 12 VDC for powering intermediate bus architectures

(IBA) in high performance and reliability servers, routers, and network

switches. The PFE600-12-054xA meets international safety standards

and displays the CE-Mark for the European Low Voltage Directive

(LVD).

o HIGH PERFORMANCE SERVERS

o ROUTERS

o SWITCHES

PFE600-12-054xA

 Best-in-class, 80 PLUS certified “Platinum” efficiency

 Wide input voltage range: 90-264 VAC

 AC input with power factor correction

 Always-On 16.5 W programmable standby output (3.3/5V)

 Hot-plug capable

 Parallel operation with active digital current sharing

 Full digital controls for improved performance

 High density design: 14.0 W/in3

 Small form factor: 54.5 x 40.0 x 321.5 mm

 I2C communication interface for control, programming and

monitoring with PSMI and PMBus™ protocol

 Overtemperature, output overvoltage and overcurrent

protection

 256 Bytes of EEPROM for user information

 2 Status LEDs: AC OK and DC OK with fault signaling

FEATURES

DESCRIPTION

APPLICATIONS

PFE600-12-054xA 2 www.power-one.com

DATA SHEET

1 ORDERING INFORMATION

PFE

600

054

Product Family

PFE Front-Ends

Power Level

600 W

Dash

V1 Output

12 V

Dash

Width

54 mm

Airflow

N: Normal

R: Reversed

Input

A: AC

2 OVERVIEW

The PFE600-12-054xA AC-DC power supply is a mainly DSP controlled, highly efficient front-end. It incorporates resonance-

soft-switching technology and interleaved power trains to reduce component stresses, providing increased system reliability

and very high efficiency. With a wide input operating voltage range and no derating of output power with input voltage and

temperature, the PFE600-12-054xA maximizes power availability in demanding server, switch, and router applications. The

front-end is fan cooled and ideally suited for server integration with a matching airflow path.

The PFC stage is controlled using a state-of-the-art integrated control-IC to guarantee best efficiency and unity power factor

over a wide operating range.

The DC-DC stage uses soft switching resonant techniques in conjunction with synchronous rectification. An active OR-ing

device on the output ensures no reverse load current and renders the supply ideally suited for operation in redundant power

systems.

The always-on standby output with selectable voltage level (3.3/5 V) provides power to external power distribution and man-

agement controllers. Its protection with an active OR-ing device provides for maximum reliability.

Status information is provided with front-panel LEDs. In addition, the power supply can be controlled and the fan speed set

via the I2C bus. It allows full monitoring of the supply, including input and output voltage, current, power, and inside tempera-

tures.

Cooling is managed by a fan controlled by the DSP controller. The fan speed is adjusted automatically depending on the

actual power demand and supply temperature and can be overridden through the I2C bus.

Figure 1 – PFE600-12-054xA Block Diagram

3 ABSOLUTE MAXIMUM RATINGS

Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-term reliabil-

ity and cause permanent damage to the supply.

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Vi maxc

Maximum Input

Continuous

264

VAC

Logic Signals

V1Sense+

Buck

Aux

Converter

VsbSense+

VsbSense-

GND

Vsb

PFC

Digital

Prim

Controls

V1Sense-

I2C

PWM

Filter

PWM

Communication Bus APS

Digital

Sec

Controls

EEPROM

FAN

BCD.00036_AG Sep-11-2013 3 www.power-one.com

DATA SHEET

4 INPUT

General Condition: TA = 0… 45 °C unless otherwise noted.

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Vi nom

Nominal Input Voltage

100

230

VAC

Input Voltage Ranges

Normal operating (Vi min to Vi max)

264

VAC

Ii max

Max Input Current

8.5

Arms

Ii p

Inrush Current Limitation

Vi min to Vi max, 90°, TNTC = 25 °C (see Figure 4 )

Input Frequency

50/60

Power Factor

Vi nom, 50 Hz, > 0.2 I1 nom

0.9

W/VA

Vi on

Turn-on Input Voltage1)

Ramping up

VAC

Vi off

Turn-off Input Voltage1)

Ramping down

VAC

Efficiency without Fan

Vi nom, 0.1∙Ix nom, Vx nom, TA = 25 °C

85.4

Vi nom, 0.2∙Ix nom, Vx nom, TA = 25 °C

92.8

Vi nom, 0.5∙Ix nom, Vx nom, TA = 25 °C

94.5

Vi nom, Ix nom, Vx nom, TA = 25 °C

94.0

Thold

Hold-up Time

After last AC zero point, V1 > 10.8 V,

VSB within regulation, Vi = 230 VAC, Px nom

1) The Front-End is provided with a minimum hysteresis of 3 V during turn-on and turn-off within the ranges.

4.1 INPUT FUSE

Quick-acting 12.5 A input fuses (5 x 20 mm) in series with both the L- and N-line inside the power supply protect against

severe defects. The fuses are not accessible from the outside and are therefore not serviceable parts.

4.2 INRUSH CURRENT

The AC-DC power supply exhibits an X-capacitance of only 3.2 μ, resulting in a low and short peak current, when the supply

is connected to the mains. The internal bulk capacitor will be charged through an NTC which will limit the inrush current.

NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in-rush current limiting device (NTC)

may not sufficiently cool down and excessive inrush current or component failure(s) may result.

4.3 INPUT UNDER-VOLTAGE

If the input voltage exceeds Vi maxC, the power supply remains on and may get damaged if the voltage exceeds a tolerable

level. If the sinusoidal input voltage stays below the input undervoltage lockout threshold Vi on, the supply will be inhibited.

Once the input voltage returns within the normal operating range, the supply will return to normal operation again.

4.4 POWER FACTOR CORRECTION

Power factor correction (PFC) is achieved by controlling the input current waveform synchronously with the input voltage. A

linear IC is used giving good PFC results over wide input voltage and load ranges. The input current will follow the shape of

the input voltage. If for instance the input voltage has a trapezoidal waveform, then the current will also show a trapezoidal

waveform.

4.5 EFFICIENCY

High efficiency (see Figure 2) is achieved by using state-of-the-art silicon power devices in conjunction with soft-transition

topologies minimizing switching losses and a full digital control scheme. Synchronous rectifiers on the output reduce the

losses in the high current output path. The speed of the fan is digitally controlled to keep all components at an optimal oper-

ating temperature regardless of the ambient temperature and load conditions.

PFE600-12-054xA 4 www.power-one.com

DATA SHEET

Figure 2 - Efficiency vs. Load current (ratio metric loading)

Figure 3 - Power factor vs. Load current

Figure 4 - Inrush current, Vin = 230Vac, 90°

CH4: Vin (200V/div), CH2: Iin (5 A/div)

5 OUTPUT

General Condition: Ta = 0 … +45 °C unless otherwise noted.

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Main Output V1

V1 nom

Nominal Output Voltage

0.5 ∙I1 nom, Tamb = 25 °C

12.0

VDC

V1 set

Output Setpoint Accuracy

-0.5

+0.5

% V1nom

dV1 tot

Total Regulation

Vi min to Vi max, 0 to 100% I1 nom, Ta min to Ta max

-1

% V1nom

P1 nom

Nominal Output Power

V1 = 12 VDC

600

I1 nom

Nominal Output Current

V1 = 12 VDC

50.0

ADC

V1 pp

Output Ripple Voltage

V1 nom, I1 nom, 20 MHz BW (See chapter 5.1)

150

mVpp

dV1 Load

Load Regulation

Vi = Vi nom, 0 - 100 % I1 nom

dV1 Line

Line Regulation

Vi =Vi min…Vi max

I1 max

Current Limitation

PFE600-12-054NA

Ta < 45 °C

Vi > 110 VAC, Ta < 45 °C

Vi > 90 VAC, Ta < 45 °C

52.5

ADC

Current Limitation

PFE600-12-054RA

dIshare

Current Sharing

Deviation from I1 tot / N, I1 > 10 A

-3

dVdyn

Dynamic Load Regulation

ΔI1 = 50% I1 nom, I1 = 5 … 100% I1 nom,

dI1/dt = 1 A/μs, recovery within 1% of V1 nom

-0.6

0.6

Trec

Recovery Time

tAC V1

Start-up Time from AC

V1 = 10.8 VDC (see Figure 6)

sec

tV1 rise

Rise Time

V1 = 10…90% V1 nom (see Figure 7)

CLoad

Capacitive Loading V1

Ta = 25 °C

30000

μF

0.8

0.82

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

0100 200 300 400 500 600

Po [W]

Power Factor

230VAC

115VAC

BCD.00036_AG Sep-11-2013 5 www.power-one.com

DATA SHEET

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Standby Output VSB

VSB nom

Nominal Output Voltage

0.5 ∙ISB nom, Tamb = 25°C

VSB_SEL = 1

3.3

VDC

VSB set

Output Setpoint Accuracy

VSB_SEL = 0

5.0

VDC

VSB_SEL = 0 / 1

-0.5

+0.5

%V1nom

dVSB tot

Total Regulation

Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max

-1

%VSBnom

PSB nom

Nominal Output Power

VSB_SEL = 0 / 1

16.5

ISB nom

Nominal Output Current

VSB = 3.3 VDC

ADC

VSB = 5.0 VDC

3.3

VSB pp

Output Ripple Voltage

VSB nom, ISB nom, 20 MHz BW (See chapter 5.1)

mVpp

dVSB

Droop

0 - 100 % ISB nom

VSB_SEL = 1

dVSB

VSB_SEL = 0

ISB max

Current Limitation

VSB_SEL = 1

5.25

ADC

VSB_SEL = 0

3.45

4.3

dVSBdyn

Dynamic Load Regulation

ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom,

dIo/dt = 0.5 A/μs, recovery within 1% of V1 nom

-3

%VSBnom

Trec

Recovery Time

250

μs

tAC VSB

Start-up Time from AC

VSB = 90% VSB nom (see Figure 6)

sec

tVSB rise

Rise Time

VSB = 10…90% VSB nom (see Figure 7)

CLoad

Capacitive Loading

Tamb = 25 °C

10000

μF

5.1 OUTPUT VOLTAGE RIPPLE

The internal output capacitance at the power supply output (behind OR ring element) is minimized to prevent disturbances

during hot plug. In order to provide low output ripple voltage in the application, external capacitors should be added close to

the power supply output.

The setup of Figure 6 has been used to evaluate suitable capacitor types. The capacitor combinations of Table 1 and Table 2

and Table 2 should be used to reduce the output ripple voltage. The ripple voltage is measured with 20 MHz BWL, close to

the external capacitors.

Figure 5 - Output ripple test setup

PGND

VSB

PFExxxx-12-054NA

Connection board

NOTE: Care must be taken when using ceramic capacitors with a total capacitance of 1 µF to 50 µF on output V1, due to

their high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects.

Table 1 - Suitable capacitors for V1

External capacitor V1

dV1max

Unit

2Pcs 47 µF/16 V/X5R/1210

150

mVpp

1Pcs 1000 µF/16 V/Low ESR Aluminum/ø10x20

mVpp

1Pcs 270 µF/16 V/Conductive Polymer/ø8x12

mVpp

2Pcs 47 µF/16 V/X5R/1210 plus

1Pcs 270 µF Conductive Polymer OR

1Pcs 1000 µF Low ESR AlCap

mVpp

Table 2 - Suitable capacitors for VSB

External capacitor VSB

dV1max

Unit

1Pcs 10 µF/16 V/X5R/1206

mVpp

2Pcs 10 µF/16 V/X5R/1206

mVpp

1Pcs 47 µF/16 V/X5R/1210

mVpp

2Pcs 100 µF/6.3 V/X5R/1206

mVpp

The output ripple voltage on VSB is influenced by the main output V1. Evaluating VSB output ripple must be done when maxi-

mum load is applied to V1.

PFE600-12-054xA 6 www.power-one.com

DATA SHEET

Figure 6 - Turn-On AC Line 230VAC, full load (200ms/div)

CH1: V1 (2V/div) CH2: VSB (1V/div) CH3: Vin (200V/div)

Figure 7 - Turn-On AC Line 230VAC, full load (5ms/div)

CH1: V1 (2V/div) CH2: VSB (1V/div) CH3: Vin (200V/div)

Figure 8 - Turn-Off AC Line 230 VAC, full load (20 ms/div)

CH1: V1 (2 V/div) CH2: VSB (1 V/div) CH3: Vin (200 V/div)

Figure 9 - Short circuit on V1 (500 μs/div)

CH1: V1 (2 V/div) CH2: VSB (1 V/div) CH3: I1 (200 A/div)

Figure 10 - Short circuit on V1 (50 ms/div)

CH1: V1 (2 V/div) CH2: VSB (1 V/div) CH4: I1 (200 A/div)

Figure 11 - AC drop out 10 ms (10 ms/div)

CH1: V1 (2 V/div) CH2: VSB (1 V/div) CH3: Vin (200 V/div)

Figure 12 - AC drop out 30 ms (20 ms/div)

CH1: V1 (2 V/div) CH2: VSB (1 V/div) CH3: Vin (200 V/div)

Figure 13 - AC drop out 30ms (200 ms/div), V1 restart after 1s

CH1: V1 (2 V/div) CH2: VSB (1 V/div) CH3: I1 (200 V/div)

Figure 14 - Load transient V1, 5 to 30 A (500 μs/div)

BCD.00036_AG Sep-11-2013 7 www.power-one.com

DATA SHEET

CH1: V1 (200 mV/div) CH4: I1 (10 A/div)

Figure 15 - Load transient V1, 30 to 5 A (500 μs/div)

CH1: V1 (200 mV/div) CH4: I1 (10 A/div)

Figure 16 - Load transient V1, 20 to 45 A (500 μs/div)

CH1: V1 (200 mV/div) CH4: I1 (10 A/div)

Figure 17 - Load transient V1, 45 to 20 A (500 μs/div)

CH1: V1 (200 mV/div) CH4: I1 (10 A/div)

6 PROTECTION

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Input Fuses (L+N)

Not user accessible, quick-acting (F)

12.5

V1 OV

OV Threshold V1

13.3

14.5

VDC

tOV V1

OV Latch OFF Time V1

VSB OV

OV Threshold VSB

115

125

% VSB

tOV VSB

OV Latch OFF Time VSB

IV1 lim

Current Limit V1

PFE600-12-054NA

Ta < 45 °C

52.5

Current Limit V1

PFE600-12-054RA

Vi > 110 VAC, Ta < 45 °C

Vi > 90 VAC, Ta < 45 °C

IV1 SC

Max Short Circuit Current V1

V1 < 3 V

tV1 SC

Short Circuit Regulation Time

V1 < 3 V, time until IV1 is limited to < IV1 sc

tV1 SC off

Short Circuit Latch OFF Time

Time to latch off when in short circuit

200

TSD

Over Temperature on Heat Sinks

Automatic shut-down

115

°C

6.1 OVERVOLTAGE PROTECTION

The PFE front-ends provide a fixed threshold overvoltage (OV) protection implemented with a HW comparator. Once an OV

condition has been triggered, the supply will shut down and latch the fault condition. The latch can be unlocked by discon-

necting the supply from the AC mains, or by toggling the PSON_L input.

6.2 VSB UNDERVOLTAGE DETECTION

Both main and standby outputs are monitored. LED and PWOK_H pin signal if the output voltage exceeds ±5% of its nomi-

nal voltage. Output undervoltage protection is provided on the standby output only. When VSB falls below 75% of its nominal

voltage, the main output V1 is inhibited.

PFE600-12-054xA 8 www.power-one.com

DATA SHEET

6.3 CURRENT LIMITATION

MAIN OUTPUT

The main output exhibits a substantially rectangular output characteristic controlled by a software feedback loop. If it runs in

current limitation and its voltage drops below ~10.0 VDC for more than 200 ms, the output will latch off (standby remains on).

Figure 18 - Current Limitation on V1 (Vi = 230 VAC)

A second current limitation circuit on V1 will immediately switch off the main output if the output current increases beyond the

peak current trip point. The supply will re-start 4 ms later with a soft start, if the short circuit persists (V1<10.0 V for >200 ms)

the output will latch off; otherwise it continuous to operate (hardware current limit triggers).

The latch can be unlocked by disconnecting the supply from the AC mains or by toggling the PSON_L input.

The main output current limitation will decrease if the ambient (inlet) temperature increases beyond 45°C (see Figure 20 and

Figure 21). Note that the actual current limitation on V1 will kick in at a current level approximately 4 A higher than what is

shown in Figure 20.

STANDBY OUTPUT

The standby output exhibits a substantially rectangular output characteristic down to 0 V (no hiccup mode / latch off) If it runs

in current limitation and its output voltage drops below the UV threshold, then the main output will be inhibited (standby re-

mains on). The current limitation of the standby output is independent of the AC input voltage, but is derated with the ambient

temperature (only for reverse airflow).

Figure 19 - Derating on V1 vs. Vi and Ta

for PFE600-12-054NA

Figure 20 - Derating on V1 vs. Vi and Ta

for PFE600-12-054RA

010 20 30 40 50 60

Main Output Current [A]

Main Output Voltage [V]

90 115 140 165 190 215 240 265

Input AC Voltage [VAC]

Main Output Nominal Current [A]

Ta < 45°C

Ta < 55°C

Ta < 65°C

90 115 140 165 190 215 240 265

Input AC Voltage [VAC]

Main Output Nominal Current [A]

Ta < 45°C

Ta < 55°C

Ta < 65°C

BCD.00036_AG Sep-11-2013 9 www.power-one.com

DATA SHEET

Figure 21 - Current limitation on VSB

Figure 22 - Temperature derating on VSB

7 MONITORING

See chapter 8.12 to 8.17 and PFE Programming Manual BCA.00006 for further information on communication interface.

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Vi mon

Input RMS Voltage

Vi min ≤ Vi ≤ Vi max

-2.5

+2.5

Ii mon

Input RMS Current

Ii > 4 Arms

-5

Ii ≤ 4 Arms

-0.2

+0.2

Arms

Pi mon

True Input Power

Pi > 100 W

-5

Pi ≤ 100 W

-5

V1 mon

V1 Voltage

-2

I1 mon

V1 Current

I1 > 10 A

-2

I1 ≤ 10 A

-0.2

+0.2

Po nom

Total Output Power

Po > 120 W

-4

Po ≤ 120 W

-4.5

+4.5

VSB mon

Standby Voltage

-0.1

+0.1

ISB mon

Standby Current

ISB ≤ ISB nom

-0.2

+0.2

8 SIGNALING AND CONTROL

8.1 ELECTRICAL CHARACTERISTICS

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

PSKILL_H / PSON_L / VSB_SEL / HOTSTANDBYEN_H Inputs

VIL

Input Low Level Voltage

-0.2

0.8

VIH

Input High Level Voltage

2.4

3.5

IIL, H

Maximum Input Sink or Source Current

RpuPSKILL_H

Internal Pull up Resistor on PSKILL_H

100

kΩ

RpuPSON_L

Internal Pull up Resistor on PSON_L

kΩ

RpuVSB_SEL

Internal Pull up Resistor on VSB_SEL

kΩ

RpuHOTSTANDBYEN_H

Internal Pull up Resistor on

HOTSTANDBYEN_H

kΩ

RLOW

Resistance Pin to SGND for Low Level

kΩ

RHIGH

Resistance Pin to SGND for High Level

kΩ

PWOK_H Output

VOL

Output Low Level Voltage

Isink < 4 mA

0.4

VOH

Output High Level Voltage

Isource < 0.5 mA

2.6

3.5

RpuPWOK_H

Internal Pull up Resistor on PWOK_H

kΩ

0 2 4 6 8

Standby Output Current [A]

Standby Output Voltage [V]

VSB=3.3V

VSB=5V

010 20 30 40 50 60 70

Ambient Temperature [°C]

Standby Output Nominal Current [A]

Vsb = 3.3V, RA

Vsb = 3.3V, NA

Vsb = 5V, NA & RA

PFE600-12-054xA 10 www.power-one.com

DATA SHEET

ACOK_H Output

VOL

Output Low Level Voltage

Isink < 2 mA

0.4

VOH

Output High Level Voltage

Isource < 50 µA

2.6

3.5

RpuACOK_H

Internal Pull up Resistor on ACOK_H

kΩ

SMB_ALERT_L Output

Vext

Maximum External Pull up Voltage

VOL

Output Low Level Voltage

Isource < 4 mA

0.4

IOH

Maximum High Level Leakage Current

µA

RpuSMB_ALERT_L

Internal Pull up Resistor on

SMB_ALERT_L

None

kΩ

8.2 INTERFACING WITH SIGNALS

All signal pins have protection diodes implemented to protect internal circuits. When the power supply is not powered, the

protection devices start clamping at signal pin voltages exceeding ±0.5 V. Therefore all input signals should be driven only

by an open collector/drain to prevent back feeding inputs when the power supply is switched off.

If interconnecting of signal pins of several power supplies is required, then this should be done by decoupling with small sig-

nal schottky diodes as shown in examples in Figure 23 (except for SMB_ALERT_L, ISHARE and I2C pins). This will ensure

the pin voltage is not affected by an unpowered power supply.

SMB_ALERT_L pins can be interconnected without decoupling diodes, since these pins have no internal pull up resistor and

use a 15 V zener diode as protection device against positive voltage on pins.

ISHARE pins must be interconnected without any additional components. This in-/output also has a 15 V zener diode as a

protection device and is disconnected from internal circuits when the power supply is switched off.

Figure 23 - Interconnection of Signal Pins

PSU 1 PDU

PSU 2

VSB_SEL

PSU 1 PDU

PSU 2

3.3V

VSB_SEL

3.3V

PWOK

3.3V

PWOK

8.3 FRONT LEDS

The front-end has 2 front LEDs showing the status of the supply. LED number one is green and indicates AC power is on or

off, while LED number two is bi-colored: green and yellow, and indicates DC power presence or fault situations. For the posi-

tion of the LEDs see Table 3 lists the different LED status.

Table 3 - LED Status

OPERATING CONDITION

LED SIGNALING

AC LED

AC Line within range

Solid Green

AC Line UV condition

Off

DC LED 1)

PSON_L High

Blinking Yellow (1:1)

Hot-Standby Mode

Blinking Yellow/Green (1:2)

V1 or VSB out of regulation

Solid Yellow

Over temperature shutdown

Output over voltage shutdown (V1 or VSB)

Output over current shutdown (V1 or VSB)

Fan error (>15%)

Over temperature warning

Blinking Yellow/Green (2:1)

Minor fan regulation error (>5%, <15%)

Blinking Yellow/Green (1:1)

1) The order of the criteria in the table corresponds to the testing precedence in the controller.

BCD.00036_AG Sep-11-2013 11 www.power-one.com

DATA SHEET

8.4 PRESENT_L

This signaling pin is recessed within the connector and will contact only once all other connector contacts are closed. This

active-low pin is used to indicate to a power distribution unit controller that a supply is plugged in. The maximum current on

PRESENT_L pin should not exceed 10 mA.

Figure 24 - PRESENT_L signal pin

VSB

PRESENT_L

PFE PDU

8.5 PSKILL_H INPUT

The PSKILL_H input is active-high and is located on a recessed pin on the connector and is used to disconnect the main

output as soon as the power supply is being plugged out. This pin should be connected to SGND in the power distribution

unit. The standby output will remain on regardless of the PSKILL_H input state.

8.6 AC TURN-ON / DROP-OUTS / ACOK_H

The power supply will automatically turn-on when connected to the AC line under the condition that the PSON_L signal is

pulled low and the AC line is within range. The ACOK_H signal is active-high. The timing diagram is shown in

Figure 25 and referenced in Table 4.

Table 4 - AC Turn-on / Dip Timing

OPERATING CONDITION

MIN

MAX

UNIT

tAC VSB

AC Line to 90% VVSB

sec

tAC V1

AC Line to 90% V1

sec

tACOK_H on1

ACOK_H signal on delay (start-up)

2000

tACOK_H on2

ACOK_H signal on delay (dips)

100

tACOK_H off

ACOK_H signal off delay

tVSB V1 del

VSB to V1 delay

500

tV1 holdup

Effective V1 holdup time

tVSB holdup

Effective VSB holdup time

tACOK_H V1

ACOK_H to V1 holdup

tACOK_H VSB

ACOK_H to VSB holdup

tV1 off

Minimum V1 off time

1000

1200

tVSB off

Minimum VSB off time

1000

1200

Figure 25 - AC turn-on timing

Input

VSB

PSON_L

ACOK_H

PWOK_H

tAC VSB tVSB rise

tV1 rise

tAC V1

tPWOK_H del

tACOK_H on1

tVSB V1 del

Figure 26 - AC short dips

Input

VSB

PSON_L

ACOK_H

PWOK_H

tV1 holdup

tACOK_H off

tV1 off

tPWOK_H warn

tACOK_H on2

Figure 27 - AC long dips

Input

VSB

PSON_L

ACOK_H

PWOK_H

tVSB holdup

tACOK_H VSB

tACOK_H off

tV1 holdup

tACOK_H V1

tV1 off

tVSB off

tPWOK_H warn

PFE600-12-054xA 12 www.power-one.com

DATA SHEET

8.7 PSON_L INPUT

The PSON_L is an internally pulled-up (3.3 V) input signal to enable/disable the main output V1 of the front-end. This active-

low pin is also used to clear any latched fault condition. The timing diagram is given in Figure 28 and the parameters in

Table 5.

Table 5 - PSON_L timing

OPERATING CONDITION

MIN

MAX

UNIT

tPSON_L V1on

PSON_L to V1 delay (on)

tPSON_L V1off

PSON_L to V1 delay (off)

tPSON_L H min

PSON_L minimum High time

8.8 PWOK_H SIGNAL

The PWOK_H is an open drain output with an internal pull-up to 3.3 V indicating whether both VSB and V1 outputs are within

regulation. This pin is active-low. The timing diagram is shown in

Figure 25 / Figure 28 and referenced in the Table 6.

Figure 28 - PSON_L turn-on/off timing

VSB

Input

PSON_L

ACOK_H

PWOK_H

tPSON_L V1on tV1 rise

tPWOK_H del

tPSON_L V1off

tPWOK_H warn

tPSON_L H min

Table 6 - PWOK_H timing

OPERATING CONDITION

MIN

MAX

UNIT

tPWOK_H del

PWOK_H to V1 delay (on)

100

500

tPWOK_H warn*)

PWOK_H to V1 delay (off)

caused by:

PSKILL_H

PSON_L, ACOK_H, OT, Fan

Failure

2.5

UV and OV on VSB

OC on V1 (Software trigger)

-11

OC on V1 (Hardware trigger)

-1

OV on V1

-3

*) A positive value means a warning time, a negative value a

delay (after fact).

8.9 CURRENT SHARE

The PFE front-ends have an active current share scheme implemented for V1. All the ISHARE current share pins need to be

interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will disconnect

its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases.

The current share function uses a digital bi-directional data exchange on a recessive bus configuration to transmit and re-

ceive current share information. The controller implements a Master/Slave current share function. The power supply provid-

ing the largest current among the group is automatically the Master. The other supplies will operate as Slaves and increase

their output current to a value close to the Master by slightly increasing their output voltage. The voltage increase is limited to

+250 mV.

The standby output uses a passive current share method (droop output voltage characteristic).

8.10 SENSE INPUTS

Both main and standby outputs have sense lines implemented to compensate for voltage drop on load wires. The maximum

allowed voltage drop is 200 mV on the positive rail and 100 mV on the PGND rail.

With open sense inputs the main output voltage will rise by 270 mV and the standby output by 50 mV. Therefore if not used,

these inputs should be connected to the power output and PGND close to the power supply connector. The sense inputs are

protected against short circuit. In this case the power supply will shut down.

8.11 HOT-STANDBY OPERATION

The hot-standby operation is an operating mode allowing to further increase efficiency at light load conditions in a redundant

power supply system. Under specific conditions one of the power supplies is allowed to disable its DC/DC stage. This will

save the power losses associated with this power supply and at the same time the other power supply will operate in a load

range having a better efficiency. In order to enable the hot standby operation, the HOTSTANDBYEN_H and the ISHARE pins

need to be interconnected. A power supply will only be allowed to enter the hot-standby mode, when the HOT-

STANDBYEN_H pin is high, the load current is low (see Figure 29) and the supply was allowed to enter the hot-standby

BCD.00036_AG Sep-11-2013 13 www.power-one.com

DATA SHEET

mode by the system controller via the appropriate I2C command (by default disabled). The system controller needs to ensure

that only one of the power supplies is allowed to enter the hot-standby mode.

If a power supply is in a fault condition, it will pull low its active-high HOTSTANDBYEN_H pin which indicates to the other

power supply that it is not allowed to enter the hot-standby mode or that it needs to return to normal operation should it al-

ready have been in the hot-standby mode.

NOTE: The system controller needs to ensure that only one of the power supplies is allowed to enter the hot-standby model.

Figure 30 shows the achievable power loss savings when using the hot-standby mode operation. A total power loss reduc-

tion of 45% is achievable.

Figure 29 - Hot-standby enable/disable current thresholds

1 PSU on

2 PSU on

25A10A 50A

Total

System

Current

Figure 30 - PSU power losses with/without hot-standby mode

Figure 31 - Recommended hot-standby configuration

In order to prevent voltage dips when the active power supply is unplugged while the other is in hot-standby mode, it is

strongly recommended to add the external circuit as shown in Figure 31. If the PRESENT_L pin status needs also to be read

by the system controller, it is recommended to exchange the bipolar transistors with small signal MOS transistors or with

digital transistors.

8.12 I2C / SMBUS COMMUNICATION

The interface driver in the PFE supply is referenced to the V1 Return. The PFE supply is a communication Slave device only;

it never initiates messages on the I2C / SMBus by itself. The communication bus voltage and timing is defined in Table 7

further characterized through:

 There are no internal pull-up resistors

 The SDA/SCL IOs are 3.3/5 V tolerant

 Full SMBus clock speed of 100 kbps

 Clock stretching limited to 1 ms

 SCL low time-out of >25 ms with recovery

within 10 ms

 Recognizes any time Start/Stop bus conditions

Figure 32 - Physical layer of communication interface

050 100 150 200 250 300 350 400 450

Po [W]

Total Power Loss [W]

Hot-Standby Disabled

Hot-Standby Enabled

PSU 1 PSU 2

VSB

HOTSTANDBYEN

PRESENT_L

VSB

HOTSTANDBYEN

PRESENT_L

3 x 3k3

3.3/5V

Rpull-up

SDA/SCL

PFE600-12-054xA 14 www.power-one.com

DATA SHEET

The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investi-

gate. This is a logical OR of the Shutdown and Warning events. The power supply responds to a read command on the gen-

eral SMB_ALERT_L call address 25(0x19) by sending its status register.

Communication to the DSP or the EEPROM will be possible as long as the input AC voltage is provided. If no AC is present,

communication to the unit is possible as long as it is connected to a life V1 output (provided e.g. by the redundant unit). If

only VSB is provided, communication is not possible.

Table 7 - I2C / SMBus Specification

PARAMETER

DESCRIPTION

CONDITION

MIN

MAX

UNIT

ViL

Input low voltage

-0.5

1.0

ViH

Input high voltage

2.3

5.5

Vhys

Input hysteresis

0.15

VoL

Output low voltage

3 mA sink current

0.4

Rise time for SDA and SCL

20+0.1Cb1

300

tof

Output fall time ViHmin  ViLmax

10 pF < Cb1 < 400 pF

20+0.1Cb1

250

Input current SCL/SDA

0.1 VDD < Vi < 0.9 VDD

-10

μA

Internal Capacitance for each SCL/SDA

fSCL

SCL clock frequency

100

kHz

Rpu

External pull-up resistor

fSCL ≤ 100 kHz

1000ns / Cb1

Ω

tHDSTA

Hold time (repeated) START

fSCL ≤ 100 kHz

4.0

μs

tLOW

Low period of the SCL clock

fSCL ≤ 100 kHz

4.7

μs

tHIGH

High period of the SCL clock

fSCL ≤ 100 kHz

4.0

μs

tSUSTA

Setup time for a repeated START

fSCL ≤ 100 kHz

4.7

μs

tHDDAT

Data hold time

fSCL ≤ 100 kHz

3.45

μs

tSUDAT

Data setup time

fSCL ≤ 100 kHz

250

tSUSTO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

μs

tBUF

Bus free time between STOP and START

fSCL ≤ 100 kHz

1 Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF

Figure 33 - I2C / SMBus Timing

8.13 ADDRESS/PROTOCOL SELECTION (APS)

The APS pin provides the possibility to select the communication protocol and address by connecting a resistor to V1 return

(0 V). A fixed addressing offset exists between the Controller and the EEPROM.

NOTE

- If the APS pin is left open, the supply will operate with the PSMI protocol at controller / EEPROM addresses 0xB6 / 0xA6.

- The ASP pin is only read at start-up of the power supply. Therefore it is not possible to change the communication protocol

and address dynamically.

tLOW

tHIGH

tLOW

tHDSTA

tSUSTA tHDDAT tSUDAT tSUSTO tBUF

tof

SDA

SCL

BCD.00036_AG Sep-11-2013 15 www.power-one.com

DATA SHEET

Table 8 - Address and protocol encoding

RAPS (Ω) 1)

Protocol

I2C Address 2)

Controller

EEPROM

820

PMBus™

0xB0

0xA0

2700

0xB2

0xA2

5600

0xB4

0xA4

8200

0xB6

0xA6

15000

PSMI

0xB0

0xA0

27000

0xB2

0xA2

56000

0xB4

0xA4

180000

0xB6

0xA6

1) E12 resistor values, use max 5% resistors, see also Figure 35.

2) The LSB of the address byte is the R/W bit.

Figure 34 - I2C address and protocol setting

8.14 CONTROLLER AND EEPROM ACCESS

The controller and the EEPROM in the power supply share the same I2C bus physical layer, Figure 35. An I2C driver device

assures logic level shifting (3.3/5 V) and a glitch-free clock stretching. The driver also pulls the SDA/SCL line to nearly 0 V

when driven low by the DSP or the EEPROM providing maximum flexibility when additional external bus repeaters are need-

ed. Such repeaters usually encode the low state with different voltage levels depending on the transmission direction.

The DSP will automatically set the I2C address of the EEPROM with the necessary offset when its own address is changed /

set. In order to write to the EEPROM, first the write protection needs to be disabled by sending the appropriate command to

the DSP. By default the write protection is on.

The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply.

Figure 35 - I2C Bus to DSP and EEPROM

8.15 EEPROM PROTOCOL

The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read

commands are defined, it is recommended to use the single byte write / read commands.

WRITE

The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte

with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the

bus should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory.

READ

The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data

address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with

the data byte at the specified location.

ADC APS

RAPS

3.3V

12k

DSP

EEPROM

Driver

SDA

SCL

APS

Addr

SCLi

SDAi

Protection

Address & Protocol Selection

S Address W A Data Address A Data A P

Data nA P

S Address W A Data Address A

S Address R A

PFE600-12-054xA 16 www.power-one.com

DATA SHEET

8.16 PSMI PROTOCOL

New power management features in computer systems require the system to communicate with the power supply to access

current, voltage, fan speed, and temperature information. Current measurements provide data to the system for determining

potential system configuration limitations and provide actual system power consumption for facility planning. Temperature

and fan monitoring allow the system to better manage fan speeds and temperatures for optimizing system acoustics. Voltage

monitoring allows the system to calculate input wattage and warning of system voltage regulation problems. The Power Sup-

ply Management Interface (PSMI) supports diagnostic capabilities and allows managing of redundant power supplies. The

communication method is SMBus. The current design guideline is version 2.12.

The communication protocol is register based and defines a read and write communication protocol to read / write to a single

WRITE

The write protocol used is the SMBus 2.0 Write Word protocol. All writes are 16-bit words; byte reads are not supported nor

allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming

Manual for further information.

READ

The read protocol used is the SMBus 2.0 Read Word protocol. All reads are 16-bit words; byte reads are not supported nor

allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming

Manual for further information.

8.17 PMBus™ PROTOCOL

The Power Management Bus (PMBus™) is an open standard protocol that defines means of communicating with power

conversion and other devices. For more information, please see the System Management Interface Forum web site at:

www.powerSIG.org.

PMBus™ command codes are not register addresses. They describe a specific command to be executed. The

PFE1100-12-054xA supply supports the following basic command structures:

 Clock stretching limited to 1 ms

 SCL low time-out of >25 ms with recovery within 10 ms

 Recognized any time Start/Stop bus conditions

WRITE

The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte

or after the first data byte (Byte command) or then after sending 2 data bytes (Word command).

In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual

for further information.

S Address W A Register ID A

Data Low Byte A Data High Byte A P

S Address W A Register ID A

Data Low Byte AS Address R A Data High Byte nA P

S Address W A Command A

Data Low Byte1) A Data High Byte1) A P

1) Optional

S Address W A Command A

Byte 1 A Byte N A P

Byte Count A

BCD.00036_AG Sep-11-2013 17 www.power-one.com

DATA SHEET

READ

The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word.

In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual

BCA.00006 for further information.

8.18 GRAPHICAL USER INTERFACE

Power-One provides with its “Power-One I2C Utility” a Windows® XP/Vista/Win7 compatible graphical user interface allowing

the programming and monitoring of the PFE600-12-054xA Front-End. The utility can be downloaded on www.power-one.com

and supports both the PSMI and PMBus™ protocols.

The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation

tree. In the monitoring view the power supply can be controlled and monitored.

If the GUI is used in conjunction with the PFE600-12-054xA Evaluation Kit it is also possible to control the PSON_L pin(s) of

the power supply.

Further there is a button to disable the internal fan for approximately 10 seconds. This allows the user to take input power

measurements without fan consumptions to check efficiency compliance to the Climate Saver Computing Platinum specifica-

tion.

The monitoring screen also allows to enable the hot-standby mode on the power supply. The mode status is monitored and

by changing the load current it can be monitored when the power supply is being disabled for further energy savings. This

obviously requires 2 power supplies being operated as a redundant system (like the evaluation kit).

NOTE: The user of the GUI needs to ensure that only one of the power supplies have the hot-standby mode enabled.

Figure 36 - Monitoring dialog of the I2C Utility

S Address W A Command A

Data (Low) Byte AS Address R A Data High Byte1) nA P

1) Optional

S Address W A Command A

Byte 1 A

S Address R A

Byte N nA PByte Count A

PFE600-12-054xA 18 www.power-one.com

DATA SHEET

9 TEMPERATURE AND FAN CONTROL

To achieve best cooling results sufficient airflow through the supply must be ensured. Do not block or obstruct the airflow at

the rear of the supply by placing large objects directly at the output connector. The PFE600-12-054NA is provided with a

normal airflow, which means the air enters through the rear of the supply and leaves at the front. The PFE600-12-054RA is

provided with a reverse airflow, which means the air enters through the front of the supply and leaves at the rear. PFE sup-

plies have been designed for horizontal operation.

The fan inside of the supply is controlled by a microprocessor. The rpm of the fan is adjusted to ensure optimal supply cool-

ing and is a function of output power and the inlet temperature.

For the normal airflow version additional constraints apply because of the AC-connector. In a normal airflow unit, the hot air

is exiting the power supply unit at the AC-inlet.

The IEC connector on the unit is rated 105°C. If 70°C mating connector is used then end user must derate the input power to

meet a maximum 70°C temperature at the front, see Figure 39.

NOTE: It is the responsibility of the user to check the front temperature in such cases. The unit is not limiting its power auto-

matically to meet such a temperature limitation.

Figure 37 - Airflow direction

Figure 38 - Fan speed vs. main output load

Figure 39 - Thermal derating for PFE600-12-054NA

Figure 40 - Thermal derating for PFE600-12-054RA

All rights strictly reserved. Reproduction or issue to third parties in any form is not permitted without written authority from Power-One.

Drawing No.

Title

Material Finish

Dim. in mm Revision

Modified

Mech. Eng. approved

Elec. Eng. approved

Mfg. approved

>120-400: ±0.2

Tolerances unless otherwise stated:

0.5-30: ±0.1 >30-120: ±0.15

Supersedes:

5/5

www.power-one.com

Issued

Scale

SizeSheet

2009-09-17 WH

2009-11-10 -

SNP Family Product GA

SNP1100-12G_GA 003

All materials used, and finished product, must meet the requirements of the current RoHS directive 2002/95/EC.

For additional information use other data files, or ask.

010 20 30 40 50

Main Output Current [A]

Fan Speed [1000 x rpm]

fan speed

min speed at Vsb = 3.3V; Isb > 3A

min speed at Vsb = 5V; Isb > 2A

100

200

300

400

500

600

010 20 30 40 50 60

Ambient Temperature [°C]

Main Output Power [W]

T Outlet < 70°C

T Outlet < 80°C

100

200

300

400

500

600

700

010 20 30 40 50 60

Ambient Temperature [°C]

Main Output Power [W]

Vi > 90VAC

Vi > 110VAC

Normal Airflow

Reverse Airflow

BCD.00036_AG Sep-11-2013 19 www.power-one.com

DATA SHEET

10 ELECTROMAGNETIC COMPATIBILITY

10.1 IMMUNITY

NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003.

PARAMETER

DESCRIPTION / CONDITION

CRITERION

ESD Contact Discharge

IEC / EN 61000-4-2, ±8 kV, 25+25 discharges per test point

(metallic case, LEDs, connector body)

ESD Air Discharge

IEC / EN 61000-4-2, ±15 kV, 25+25 discharges per test point

(non-metallic user accessible surfaces)

Radiated Electromagnetic Field

IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation,

1 µs Pulse Modulation, 10 kHz…2 GHz

Burst

IEC / EN 61000-4-4, level 3

AC port ±2 kV, 1 minute

DC port ±1 kV, 1 minute

Surge

IEC / EN 61000-4-5

Line to earth: level 3, ±2 kV

Line to line: level 2, ±1 kV

VSB: A,V1: B1

RF Conducted Immunity

IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 … 80 MHz

Voltage Dips and Interruptions

IEC/EN 61000-4-11

1: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 10 ms

2: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 20 ms

3: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration >20 ms

1 V1 drops to 90 … 97% V1 nom for 3 ms

10.2 EMISSION

PARAMETER

DESCRIPTION / CONDITION

CRITERION

Conducted Emission

EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG,

single unit

Class A

6 dB margin

EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG,

2 units in rack system

Class A

6 dB margin

Radiated Emission

EN55022 / CISPR 22: 30 MHz … 1 GHz, QP,

single unit

Class A

6 dB margin

EN55022 / CISPR 22: 30 MHz … 1 GHz, QP,

2 units in rack system

Class A

6 dB margin

Harmonic Emissions

IEC61000-3-2, Vin = 100 VAC/ 60 Hz, 100% Load

Class A

IEC61000-3-2, Vin = 120 VAC/ 60 Hz, 100% Load

Class A

IEC61000-3-2, Vin = 200 VAC/ 60 Hz, 100% Load

Class A

IEC61000-3-2, Vin = 230 VAC/ 50 Hz, 100% Load

Class A

IEC61000-3-2, Vin = 240 VAC/ 50 Hz, 100% Load

Class A

Acoustical Noise

Sound power statistical declaration (ISO 9296, ISO 7779, IS9295)

@ 50% load

42 dBA

11 SAFETY / APPROVALS

Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to-output

electric strength tests should not be repeated in the field. Power-One will not honor any warranty claims resulting from elec-

tric strength field tests.

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Agency Approvals

UL 60950-1 Second Edition

CAN/CSA-C22.2 No. 60950-1-07 Second Edition

IEC 60950-1:2005

EN 60950-1:2006

Approved by

independent body

(see CE Declaration)

Isolation Strength

Input (L/N) to case (PE)

Basic

Input (L/N) to output

Reinforced

Output to case (PE)

Functional

Creepage / Clearance

Primary (L/N) to protective earth (PE)

According to

safety standard

Primary to secondary

PFE600-12-054xA 20 www.power-one.com

DATA SHEET

Electrical Strength Test

Input to case

kVAC

Input to output

Output and Signals to case

12 ENVIRONMENTAL

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Ambient Temperature

Vi min to Vi max, I1 nom, ISB nom

+45

°C

TAext

Extended Temp. Range

Derated output (see Figure 19 and Figure 39)

+45

+65

°C

Storage Temperature

Non-operational

-20

+70

°C

Altitude

Operational, above Sea Level

10,000

Feet

Audible Noise

Vi nom, 50% Io nom, TA = 25°C

dBA

13 MECHANICAL

PARAMETER

DESCRIPTION / CONDITION

MIN

NOM

MAX

UNIT

Dimensions

Width

54.5

Height

40.0

Depth

321.5

Weight

950

Figure 41 - Side View 1

Figure 42 - Top View

Figure 43 - Side View 2

Reverse Air Flow Direction

Normal Air Flow Direction

NOTE: A 3D step file of the power supply casing is available on request.

BCD.00036_AG Sep-11-2013 21 www.power-one.com

DATA SHEET

Figure 44 - Front and Rear View

14 CONNECTIONS

Power Supply Connector: Tyco Electronics P/N 2-1926736-3 (NOTE: Column 5 is recessed (short pins))

Mating Connector: Tyco Electronics P/N 2-1926739-5 or FCI 10108888-R10253SLF

NAME

DESCRIPTION

Output

6, 7, 8, 9, 10

+12 VDC main output

1, 2, 3, 4, 5

PGND

Power ground (return)

Control Pins

VSB