1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package. This product is designed and qualified for use in computing, communications,
consumer and industrial applications only.
1.2 Features
1.3 Applications
1.4 Quick reference data
PMN38EN
N-channel TrenchMOS logic level FET
Rev. 02 — 3 October 2007 Product data sheet
Logic level threshold Low threshold voltage
Surface-mounted package Very fast switching
Battery powered motor control Driver FET in DC-to-DC converters
High speed switch in set top box power
supplies
Load switch in notebook computers
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj25 °C; Tj150 °C --30V
IDdrain current Tsp =25°C; VGS =10V;
see Figure 1 and 3--5.4A
Ptot total power dissipation Tsp =25°C; see Figure 2 --1.75W
Static characteristics
RDSon drain-source on-state
resistance VGS =4.5V; I
D=2.8A;
Tj=25°C; see Figure 8 and 9- 3846mΩ
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 2 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
2. Pinning information
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Symbol Description Simplified outline Graphic Sy mbol
1 D drain
SOT457 (TSOP6)
2 D drain
3 G gate
4 S source
5 D drain
6 D drain
132
4
56
S
D
G
m
bb076
Table 3. Orderi ng information
Type number Package
Name Description Version
PMN38EN TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj25 °C; Tj150 °C-30V
VGS gate-source voltage -20 20 V
IDdrain current Tsp =100°C; VGS = 10 V; see Figure 1 -3.4A
Tsp =25°C; VGS = 10 V; see Figure 1 and 3-5.4A
IDM peak drain current Tsp =25°C; tp10 μs; pulsed; see Figure 3 - 21.6 A
Ptot total power dissipation Tsp =25°C; see Figure 2 -1.75W
Tstg storage temperature -55 150 °C
Tjjunction temperature -55 150 °C
Source-drain diode
ISsource current Tsp =25°C - 1.45 A
ISM peak source current Tsp =25°C; tp=10μs; pulsed - 5.8 A
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 3 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
Fig 1. Normalized co ntinuous drain current as a
function of solder point temperature Fig 2. Normalized total power dissipation as a
function of solder point temperature
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
03aa25
0
40
80
120
0 50 100 150 200
Tsp (°C)
Ider
(%)
03aa17
0
40
80
120
0 50 100 150 200
Tsp (°C)
Pder
(%)
Ider =ID
ID(25°C)× 100 %
Pder =Ptot
Ptot(25°C)× 100 %
003aab227
10-2
10-1
1
10
102
10-1 1 10 102
VDS (V)
ID
(A)
DC 10 ms
Limit RDSon = VDS / ID
1 ms
tp = 10 μs
100 ms
100 μs
Tsp=25°C;IDM is single pulse
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 4 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
5. Thermal characteristics
[1] Mounted on a metal clad board
6. Characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-sp) thermal resistance
from junction to solder
point
see Figure 4 [1] --70K/W
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
03aj69
1
10
102
10-4 10-3 10-2 10-1 1 10 102
tp (s)
Zth(j-sp)
(K/W)
single pulse
δ = 0.5
0.2
0.1
0.05
0.02
tp
T
P
t
tp
T
δ =
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=250μA; VGS =0V;
Tj=-55°C27 - - V
ID=250μA; VGS =0V;
Tj=25°C30 - - V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS = VGS;
Tj= 150 °C0.6 - - V
ID=1 mA; VDS = VGS; Tj=-55°C- - 2.2 V
ID=1mA; V
DS = VGS; Tj=25°C;
see Figure 7 11.52V
IDSS drain leakage current VDS =30V; V
GS =0V; T
j=25°C - 0.01 0.1 μA
VDS =30V; V
GS =0V;
Tj= 150 °C--10μA
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 5 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
IGSS gate leakage current VGS =+20V; V
DS =0V;
Tj=25°C- 10 100 nA
VGS =-20V; V
DS =0V;
Tj=25°C- 10 100 nA
RDSon drain-source on-state
resistance VGS =10V; I
D=3A; T
j=150°C- 49.6 60.9 mΩ
VGS =4.5V; I
D=2.8A;
Tj=25°C; see Figure 8 and 9-3846mΩ
VGS =10V; I
D=3A; T
j=25°C;
see Figure 8 and 9-3138mΩ
Dynamic characteristics
QG(tot) total gate charge ID=5A; V
DS =15V;
VGS =4.5V; T
j=25°C;
see Figure 10 and 11
-6.1-nC
QGS gate-source charge ID=5A; V
DS =15V;
VGS =4.5V; T
j=25°C;
see Figure 10 and 11
-1.7-nC
QGD gate-drain charge ID=5A; V
DS =15V;
VGS =4.5V; T
j=25°C;
see Figure 10 and 11
-2.35-nC
Ciss input capacitance VDS =25V; V
GS =0V;
f=1MHz; T
j=25°C;
see Figure 12
-495-pF
Coss output capacitance VGS =0V; V
DS =25V;
f=1MHz; T
j=25°C;
see Figure 12
-100-pF
Crss reverse transfer
capacitance VDS =25V; V
GS =0V;
f=1MHz; T
j=25°C;
see Figure 12
-70-pF
td(on) turn-on delay time RG(ext) =6Ω; RL=12Ω;
VDS =15V; V
GS =4.5V;
Tj=25°C
-14-ns
trrise time RG(ext) =6Ω; RL=12Ω;
VDS =15V; V
GS =4.5V;
Tj=25°C
-19-ns
td(off) turn-off delay time VDS =15V; R
L=12Ω;
VGS =4.5V; R
G(ext) =6Ω;
Tj=25°C
-28-ns
tffall time RG(ext) =6Ω; RL=12Ω;
VDS =15V; V
GS =4.5V;
Tj=25°C
-16-ns
Source-drain diode
VSD source-drain voltage IS= 1.7 A; VGS =0V; T
j=25°C;
see Figure 13 -0.751.2V
trr reverse recovery time IS= 2.3 A; dIS/dt = 100 A/μs;
VGS =0V; V
DS =30V; T
j=25°C-22-ns
Table 6. Characteristics …continued
Symbol Parameter Conditions Min Typ Max Unit
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 6 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
Fig 5. Output ch aracteristics: drain current as a
function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 7. Sub-threshold drai n cu rre nt as a function of
gate-source voltage Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
003aab228
0
5
10
15
20
0 0.2 0.4 0.6 0.8 1
V
DS
(V)
I
D
(A)
10
2.7
2.5
4.5 3.96
3.5
3.1
2.9
2.3
V
GS
(V) = 2.1
03aj73
0
5
10
15
20
01234
V
GS
(V)
I
D
(A)
T
j
= 150 °C
25 °C
Tj=25°C
VDS >ID×RDSon
03aa36
10-6
10-5
10-4
10-3
10-2
10-1
0123
VGS (V)
ID
(A)
maxtypmin
003aab229
0
20
40
60
0 5 10 15 20
I
D
(A)
R
DSon
(mΩ)
T
j
= 25 °C3.5
4.5
6
10
3.9
V
GS
(V) = 3.1
Tj=25°C;VDS =VGS
Tj=25°C
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 7 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature Fig 10. Gate-sour c e voltage as a function of gate
charge; typical values
Fig 11. Gate charge waveform definitions Fig 12. Input, output and reverse transfer capacit ances
as a function of drain- source voltage; typical
values
03af18
0
0.5
1
1.5
2
-60 0 60 120 180
T
j
(°C)
a
03aj76
0
2
4
6
8
10
0 5 10 15
Q
G
(nC)
V
GS
(V)
a=RDSon
RDSon(25°C)
ID=5A;Tj=25°C;VDS =15V
003aaa50
8
VGS
VGS(th)
QGS1 QGS2
QGD
VDS
QG(tot)
ID
QGS
VGS(pl)
03aj75
10
10
2
10
3
10
-1
1 10 10
2
V
DS
(V)
C
(pF)
C
iss
C
oss
C
rss
VGS =0V;f=1MHz
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 8 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
Fig 13. Source current as a function of source-d rain voltage; typical values
03aj74
0
5
10
15
20
00.511.5
V
SD
(V)
I
S
(A)
T
j
= 25 °C
150 °C
VGS =0V
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 9 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
7. Package outline
Fig 14. Package outline SOT457 (TSOP6)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT457 SC-74
wBM
bp
D
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
scale
c
X
132
4
56
0 1 2 mm
Plastic surface-mounted package (TSOP6); 6 leads SOT457
UNIT A1bpcDEHELpQywv
mm 0.1
0.013
0.40
0.25
3.1
2.7
0.26
0.10
1.7
1.3
e
0.95 3.0
2.5 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2
0.33
0.23
A
1.1
0.9
05-11-07
06-03-16
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 10 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PMN38EN_2 20071003 Product data sheet - PMN38EN_1
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the company name where appropriate.
PMN38EN_1 20060113 Product data sheet - -
PMN38EN_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 3 October 2007 11 of 12
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
9.3 Disclaimers
General — In formation in this document is believed to be accurate and
reliable. However, NXP Semiconductors does no t give any represent ations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are no t designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconducto rs product can reasonably b e expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ra tings System of IEC 60134) may cause permane nt
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PMN38EN
N-channel TrenchMOS logic level FET
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 October 2007
Document identifier: PMN38EN_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Contact information. . . . . . . . . . . . . . . . . . . . . 11
11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12