INA116UAG4 - Texas Instruments

Difet

®; Burr-Brown Corporation

FEATURES

●LOW INPUT BIAS CURRENT: 3fA typ

●BUFFERED GUARD DRIVE PINS

●LOW OFFSET VOLTAGE: 2mV max

●HIGH COMMON-MODE REJECTION:

84dB (G = 10)

●LOW QUIESCENT CURRENT: 1mA

●INPUT OVER-VOLTAGE PROTECTION: ±40V

APPLICATIONS

●LABORATORY INSTRUMENTATION

●pH MEASUREMENT

●ION–SPECIFIC PROBES

●LEAKAGE CURRENT MEASUREMENT

Ultra Low Input Bias Current

INSTRUMENTATION AMPLIFIER

INA116

60kΩ60kΩ

V+

V–

INA116

Ref

G = 1 + 50kΩ

–

25kΩ

Guard

Over-Voltage

Protection

Over-Voltage

Protection

DESCRIPTION

The INA116 is a complete monolithic FET-input instru-

mentation amplifier with extremely low input bias

current.

Difet

® inputs and special guarding techniques

yield input bias currents of 3fA at 25°C, and only 25fA

at 85°C. Its 3-op amp topology allows gains to be set

from 1 to 1000 by connecting a single external resistor.

Guard pins adjacent to both input connections can be

used to drive circuit board and input cable guards to

maintain extremely low input bias current.

The INA116 is available in 16-pin plastic DIP and SOL-16

surface-mount packages, specified for the –40°C to +85°C

temperature range.

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

SBOS034

INA116 2

SPECIFICATIONS

AT TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.

INA116P, U INA116PA, UA

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

INPUT

Offset Voltage, RTI

Initial TA = +25°C±0.5 ±0.5/G ±2 ±2/G ✻±5 ±5/G mV

vs Temperature TA = TMIN to TMAX See Typical Curve ✻

vs Power Supply VS = ±4.5V to ±18V ±10 ±15/G ±50 ±100/G ✻±100 ±200/G µV/V

Long-Term Stability ±1 ±5/G ✻µV/mo

Bias Current ±3±25 ✻±100 fA

vs Temperature See Typical Curve ✻

Offset Current ±1±25 ✻±100 fA

vs Temperature See Typical Curve ✻

Impedance, Differential >1015/0.2 ✻Ω/pF

Common-Mode >1015/7 ✻Ω/pF

Common-Mode Voltage Range

(V+)–4 (V+)–2 ✻✻ V

(V–)+4 (V–)+2.4 ✻✻ V

Safe Input Voltage ±40 ✻V

Common-Mode Rejection VCM = ±11V, ∆RS = 1kΩ

G = 1 80 89 73 ✻dB

G = 10 84 92 78 ✻dB

G = 100 86 94 80 ✻dB

VCM = ±5V, G = 1000 86 94 80 ✻dB

NOISE

Voltage Noise, RTI G = 1000, RS = 0Ω

f = 1kHz 28 ✻nV/√Hz

fB = 0.1Hz to 10Hz 2 ✻µVp-p

Current Noise

f = 1kHz 0.1 ✻fA/√Hz

GAIN

Gain Equation 1+(50kΩ/RG)✻V/V

Range of Gain 1 1000 ✻✻V/V

Gain Error G = 1 ±0.01 ±0.05 ✻0.1 %

G = 10 ±0.25 ±0.4 ✻±0.5 %

G = 100 ±0.35 ±0.5 ✻±0.7 %

G = 1000 ±1.25 ✻%

Gain vs Temperature(1) G = 1 ±5±10 ✻±20 ppm/°C

50kΩ Resistance(1)(2) ±25 ±100 ✻±100 ppm/°C

Nonlinearity G = 1 ±0.0005 ±0.005 ✻±0.01 % of FSR

G = 10 ±0.001 ±0.005 ✻±0.01 % of FSR

G = 100 ±0.001 ±0.005 ✻±0.01 % of FSR

G = 1000 ±0.005 ✻% of FSR

GUARD OUTPUTS

Offset Voltage ±15 ±50 ✻✻mV

Output Impedance 650 ✻Ω

Current Drive +2/–0.05 ✻mA

OUTPUT

Voltage Positive RL = 10kΩ(V+) –1 (V+) –0.7 ✻✻ V

Negative RL = 10kΩ(V–) +0.35 (V–) +0.2 ✻✻ V

Load Capacitance Stability 1000 ✻pF

Short-Circuit Current +5/–12 ✻mA

FREQUENCY RESPONSE

Bandwidth, –3dB G = 1 800 ✻kHz

G = 10 500 ✻kHz

G = 100 70 ✻kHz

G = 1000 7 ✻kHz

Slew Rate G = 10 to 200 0.8 ✻V/µs

Settling Time, 0.01% 10V Step, G = 1 22 ✻µs

G = 10 25 ✻µs

G = 100 145 ✻µs

G = 1000 400 ✻µs

Output Overload Recovery 50% Overdrive 20 ✻µs

POWER SUPPLY

Voltage Range ±4.5 ±15 ±18 ✻✻✻V

Current VIN = 0V ±1±1.4 ✻✻mA

TEMPERATURE RANGE

Specification –40 85 ✻✻°C

Operating –40 125 ✻✻°C

JA 80 ✻°C/W

✻ Specification same as INA116P

NOTE: (1) Guaranteed by wafer test. (2) Temperature coefficient of the “50kΩ” term in the gain equation.

3INA116

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

Top View DIP

SOL-16

Supply Voltage .................................................................................. ±18V

Input Voltage Range.......................................................................... ±40V

Output Short-Circuit (to ground).............................................. Continuous

Operating Temperature ................................................. –40°C to +125°C

Storage Temperature ..................................................... –40°C to +125°C

Junction Temperature.................................................................... +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

ABSOLUTE MAXIMUM RATINGS

Guard –

NC: No Internal Connection.

V+

Guard +

V–

Ref

–

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE INFORMATION

PACKAGE DRAWING

PRODUCT PACKAGE NUMBER(1)

INA116PA 16-Pin Plastic DIP 180

INA116P 16-Pin Plastic DIP 180

INA116UA SOL-16 Surface-Mount 211

INA116U SOL-16 Surface-Mount 211

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

PIN CONFIGURATION

INA116 4

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.

GAIN vs FREQUENCY

–10

–20

Gain (dB)

Frequency (Hz)

1k 10k 100k 1M 10M

G = 100

G = 10

G = 1

G = 1000

COMMON-MODE REJECTION vs FREQUENCY

100

Common-Mode Rejection (dB)

Frequency (Hz)

10 100 1k 10k 100k

G = 1000V/V

G = 100V/V

G = 10V/V

G = 1V/V

POSITIVE POWER SUPPLY REJECTION

vs FREQUENCY

Frequency (Hz)

Power Supply Rejection (dB)

120

100

01 10 100 1k 10k 100k

G = 1000V/V

G = 100V/V

G = 1V/V

G = 10V/V

NEGATIVE POWER SUPPLY REJECTION

vs FREQUENCY

Frequency (Hz)

Power Supply Rejection (dB)

120

100

01 10 100 1k 10k 100k

G = 1

G = 1k

G = 10 < 100

INPUT BIAS CURRENT vs INPUT VOLTAGE

Input Voltage (V)

Input Bias Current (fA)

–5

–10

–15–15 –10 –5 0 5 10 15

INPUT BIAS CURRENT vs TEMPERATURE

Input Bias Current (fA)

1000

100

1–75 –50 –25 0 25 50 75 100 125

Measurement Limit

5INA116

INPUT OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION

Production Distribution (%)

Offset Voltage Drift (µV/°C)

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.

INPUT OVER-VOLTAGE V/I CHARACTERISTICS

–1

–2

–3

–4

Input Current (mA)

Input Voltage (V)

–40 –30 –20 –10 0 10 20 30 40

G = 1000V/V

G = 1V/V

INPUT REFERRED NOISE vs FREQUENCY

Frequency (Hz)

Voltage Noise Density (nV/√ Hz)

110 1k100

10k

100

10 10k

G = 1V/V

G = 10V/V

G = 1000V/V

Bandwidth Limit

INPUT COMMON-MODE RANGE

vs OUTPUT VOLTAGE

Output Voltage (V)

Common-Mode Voltage (V)

–15 –10 0 5 15–5

–5

–10

–15 10

G ≥ 10 G ≥ 10

G = 1

D/2

–

VCM

D/2

INA116Ref

–15V

+15V G = 1G = 1

OFFSET VOLTAGE WARM-UP

–5

–10

–15

G = 1

Offset Voltage Change (µV)

Time After Power Supply Turn-On (s)

0 5 10 15 20 25

G ≥ 10

QUIESCENT CURRENT AND SLEW RATE

vs TEMPERATURE

Temperature (°C)

Quiescent Current (µA)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

Slew Rate (V/µs)

1.4

1.2

1.0

0.8

0.6

0.4

–75 –50 –25

0 25 50 75 100 125

0.5 6

17 18

G = 100

G = 10

G = 1

0 20406080

920

0.5 3

15 14 0.5

0.5

–80 –60 –40 –20

INA116 6

G=1

G=10

G=100

G=1000

G=1

G=10

G=100

G=1000

20mV/div

100µs/div

20mV/div

10µs/div

5V/div

100µs/div

5V/div

100µs/div

LARGE SIGNAL RESPONSE LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

0100 1k 10k 100k 1M

Frequency (Hz)

Peak-to-Peak Output Voltage (V)

G = 10, 100

G = 1

G = 1000

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.

1s/div

VOLTAGE NOISE, 0.1 TO 10Hz

INPUT-REFERRED, G ≥ 100

500nV/div

7INA116

APPLICATIONS INFORMATION

Figure 1 shows the connections required for basic operation

of the INA116. Applications with noisy or high impedance

power supplies may require decoupling capacitors close to

the supply pins as shown.

The output is referred to the output reference (Ref) terminal

which is normally grounded. This must be a low impedance

connection to assure good common-mode rejection. A resis-

tance of 30Ω in series with this connection will cause a

typical device to degrade to approximately 72dB CMR at

G = 1.

SETTING THE GAIN

Gain of the INA116 is set by connecting a single external

resistor, RG, as shown. The gain is—

Commonly used gains and resistor values are shown in

Figure 1.

The 50kΩ term in equation 1 is the sum of the two feedback

resistors of A1 and A2. These on-chip metal film resistors are

laser trimmed to accurate absolute values. The accuracy and

temperature coefficient of these resistors are included in the

gain accuracy and drift specifications of the INA116.

The stability and temperature drift of RG also affect gain.

RG’s contribution to gain accuracy and drift can be directly

inferred from the gain equation (1). Low resistor values

required for high gain make wiring resistance important.

Sockets add to the wiring resistance that will contribute

additional gain error in gains of approximately 100 or

greater.

OFFSET TRIMMING

The INA116 is laser trimmed for low offset voltage and

offset voltage drift; most applications require no external

offset adjustment. Figure 2 shows an optional circuit for

trimming the output offset voltage. A voltage applied to the

Ref terminal is summed at the output. Op amp A1 provides

a low source impedance for the Ref terminal, assuring good

common-mode rejection.

G=1+50kΩ

(1)

FIGURE 1. Basic Connections.

INA116

Also drawn in simplified form:

Ref

–

60kΩ

V–

INA116

Ref

G = 1 + 50kΩ

–

25kΩ

Over-Voltage

Protection

Over-Voltage

Protection

Input Guards

See Text.

0.1µF

V+ 0.1µF

DESIRED

GAIN

100

200

500

1000

2000

5000

10000

NC: No Connection.

(Ω)

50.00k

12.50k

5.556k

2.632k

1.02k

505.1

251.3

100.2

50.05

25.01

10.00

5.001

NEAREST 1% R

(Ω)

49.9k

12.4k

5.62k

2.61k

1.02k

511

249

100

49.9

24.9

4.99

INA116 8

FIGURE 2. Optional Trimming of Output Offset Voltage.

INPUT BIAS CURRENT RETURN PATH

Input circuitry must provide an input bias current path for

proper operation. Figure 3 shows resistors R1 and R2 to

provide an input current path. Without these resistors, the

inputs would eventually float to a potential that exceeds the

common-mode range of the INA116 and the input amplifiers

would saturate. Because of its exceedingly low input bias

current, improperly biased inputs may operate normally for

a period of time after power is first applied, or operate

intermittently.

CIRCUIT BOARD LAYOUT AND ASSEMBLY

Careful circuit board layout and assembly techniques are

required to achieve the exceptionally low input bias current

performance of the INA116. Guard terminals adjacent to

both inputs make it easy to properly guard the critical input

terminal layout. Since traces are not required to run between

device pins, this layout is easily accomplished, even with the

surface mount package. The guards should completely en-

circle their respective input connections—see Figure 4. Both

sides of the circuit board should be guarded, even if only one

side has an input terminal conductor. Route any time-

varying signals away from the input terminals. Solder mask

should not cover the input and guard traces since this can

increase leakage.

FIGURE 3. Providing An Input Bias Current Path.

FIGURE 4. Circuit Board Guard Layout.

After assembly, the circuit board should be cleaned. Com-

mercial solvents should be chosen according to the soldering

method and flux used. Solvents should be cleaned and

replaced often. Solvent cleaning should be followed by a de-

ionized water rinse and 85°C bake out.

Sockets can be used, but select and evaluate them carefully

for best results. Use caution when installing the INA116 in

a socket. Careless handling can contaminate the plastic near

the input pins, dramatically increasing leakage current.

A proven low leakage current assembly method is to bend

the input pins outward so they do not contact the circuit

board. Input connections are made in air and soldered

directly to the input pin. This technique is often not practical

or production-worthy. It is, however, a useful technique for

evaluation and testing and provides a benchmark with which

to compare other wiring techniques. The circuit board guard-

ing techniques discussed normally reduce leakage to accept-

able levels.

A solid mechanical assembly is required for good results.

Nearby plastic parts can be especially troublesome since a

static charge can develop and the slightest motion or vibra-

tion will couple charge to the inputs. Place a Faraday shield

around the whole amplifier and input connection assembly

to eliminate stray fields.

INA116

100MΩ

INA116

100MΩ

Polarizing

Voltage

Capacitive

Sensor

Crystal or

Ceramic

Transducer

Guard Top and

Bottom of Circuit Board.

INA116

–

10kΩ

(1)

OPA131

Ref

±10mV

Adjustment Range

100Ω

(1)

100Ω

(1)

100µA

1/2 REF200

100µA

1/2 REF200

V+

V–

NOTE: (1) For wider trim range required

in high gains, scale resistor values larger

9INA116

INPUT CONNECTIONS

Some applications must make high impedance input connec-

tions to external sensors or input connectors. To assure low

leakage, the input should be guarded all the way to the signal

source—see Figure 5. Coaxial cable can be used with the

shield driven by the guard. A separate connection is required

to provide a ground reference at the signal source. Triaxial

cable may reduce noise pickup and provides the ground

reference at the source. Drive the inner shield at guard

potential and ground the outer shield. Two separate guarded

lines are required if both the inverting and non-inverting

inputs are brought to the source.

The guard drive output current is limited to approximately

+2mA/–50µA. For slow input signals the internal guard

output can directly drive a cable shield. With fast input

signals, however, the guard may not provide sufficient

output current to rapidly charge the cable capacitance. An op

amp buffer may be required as shown in Figure 6.

FIGURE 7. pH or Ion Measurement System.

FIGURE 6. Buffered Guard Drive.

1MΩ

–

Two coaxial cables and ground

Two triaxial cables

High-Z

Source

1MΩ

High-Z

Source

–

FIGURE 5. Input Cable Guarding Circuits.

OPA131

Cable

Op amp buffer helps

guard cables with

fast input signals—

see text.

Circuit Board

Guard

150Ω

INA116

5.62kΩ

8911 V

G = 10

+15

–15

Solution

Ground

Sample

Electrode

Reference

Electrode

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

INA116PA ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

INA116PAG4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

INA116UA ACTIVE SOIC DW 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

INA116UAG4 ACTIVE SOIC DW 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Feb-2009

Addendum-Page 1

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