74HC08D-Q100,118 - NXP SEMICONDUCTORS

Important notice

Dear Customer,

On 7 February 2017 the former NXP Standard Product business became a new company with the

tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS

semiconductors with its focus on the automotive, industrial, computing, consumer and wearable

application markets

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use

the references to Nexperia, as shown below.

Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,

use http://www.nexperia.com

Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use

salesaddresses@nexperia.com (email)

Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on

the version, as shown below:

reserved

Should be replaced with:

If you have any questions related to the data sheet, please contact our nearest sales office via e-mail

or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and

understanding,

Kind regards,

Team Nexperia

1. General description

The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp

diodes. This enables the use of current limiting resistors to interface inputs to voltages in

excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from 40 C to +85 C and from 40 C to +125 C

Complies with JEDEC standard JESD7A

Complies with JEDEC standard JESD8-1A

Input levels:

For 74HC08-Q100: CMOS level

For 74HCT08-Q100: TTL level

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

Multiple package options

3. Ordering information

74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

Rev. 1 — 16 July 2012 Product data sheet

Table 1. Ordering information

Type number Package

Tempe rature range Name Description Version

74HC08D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm SOT108-1

74HCT08D-Q100

74HC08PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74HCT08PW-Q100

74HC08BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 14 terminals;

body 2.5 30.85 mm

SOT762-1

74HCT08BQ-Q100

Product data sheet Rev. 1 — 16 July 2012 2 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

mna222

1B 1Y

2B 2Y

3B 3Y

4B 4Y

12 11

mna223

mna221

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configura tion DHVQFN14

$ 9&&

% %

<$

$<

%%

<$

*1'<













 













+&4

+&74

DDD

*1'



7UDQVSDUHQWWRSYLHZ

$

%

<

$

%

$

 

















WHUPLQDO

LQGH[DUHD

+&4

+&74

DDD

<

%

$

<

%

*1'

<

Product data sheet Rev. 1 — 16 July 2012 3 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

Table 2. Pin description

Symbol Pin Description

1A to 4A 1, 4, 9, 12 data input

1B to 4B 2, 5, 10,13 data input

1Y to 4Y 3, 6, 8, 11 data output

GND 7 ground (0 V)

VCC 14 supply voltage

Table 3. Function table[1]

Input Output

nA nB nY

LLL

LHL

HLL

HHH

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7 V

IIK input clamping current VI < 0.5 V or VI>V

CC + 0.5 V [1] -20 mA

IOK output clamping current VO<0.5 V or VO>V

CC +0.5V [1] -20 mA

IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA

ICC supply current - 50 mA

IGND ground current 50 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation [2] - 500 mW

Product data sheet Rev. 1 — 16 July 2012 4 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating con ditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC08-Q100 74HCT08-Q100 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0- V

CC V

VOoutput voltage 0 - VCC 0- V

CC V

Tamb ambient temperature 40 - +125 40 - +125 C

t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - n s/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V--83---ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

74HC08-!00

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VOH HIGH-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0 .1 V

IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0 .1 V

IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0 .1 V

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =6.0V --0.1 - 1-1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =6.0V --2.0- 20 - 40A

Product data sheet Rev. 1 — 16 July 2012 5 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

10. Dynamic characteristics

CIinput

capacitance -3.5- - - - -pF

74HCT08-Q100

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2 .0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V

IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI = VIH or VIL; VCC = 4.5 V

IO = 20 A - 0 0.1 - 0.1 - 0.1 V

IO = 5.2 mA - 0.15 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI = VCC or GND;

VCC =5.5V --±0.1- ±1 - ±1A

ICC supply current VI = VCC or GND; IO=0A;

VCC =5.5V --2.0- 20 - 40A

ICC additional

supply current per input pin;

VI=V

CC 2.1 V; IO=0A;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V

- 60 216 - 270 - 294 A

CIinput

capacitance -3.5- - - - -pF

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit

Min Typ Max Min Max Min Max

Table 7. Dynam ic characteristics

GND = 0 V; CL= 50 pF; for load circui t see Figure 7.

Symbol Parameter Conditions 25 C40 C to +125 CUnit

Min Typ Max Max

(85 C) Max

(125 C)

74HC08-Q100

tpd propagation delay nA, nB to nY; see Figure 6 [1]

VCC = 2.0 V - 25 90 115 135 ns

VCC = 4.5 V - 9 18 23 27 ns

VCC = 5.0 V; CL=15pF - 7 - - - ns

VCC = 6.0 V - 7 15 20 23 ns

tttransition time see Figure 6 [2]

VCC = 2.0 V - 19 75 95 110 ns

VCC = 4.5 V - 7 15 19 22 ns

VCC = 6.0 V - 6 13 16 19 ns

Product data sheet Rev. 1 — 16 July 2012 6 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in W):

PD=C

PD VCC2fiN+ (CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

11. Waveforms

CPD power dissipation

capacitance per package; VI=GNDtoV

CC [3] -10- - -pF

74HCT08-Q100

tpd propagation delay nA, nB to nY; see Figure 6 [1]

VCC = 4.5 V - 14 24 30 36 ns

VCC = 5.0 V; CL=15pF - 11 - - - ns

tttransition time VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns

CPD power dissipation

capacitance per package;

VI=GNDtoV

CC 1.5 V [3] -20- - -pF

Table 7. Dynam ic characteristics

GND = 0 V; CL= 50 pF; for load circui t see Figure 7.

Symbol Parameter Conditions 25 C40 C to +125 CUnit

Min Typ Max Max

(85 C) Max

(125 C)

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. Input to output propagation delays

*1'

Q<RXWSXW

DDD

3+/

7+/

7/+

3/+

;

Q$Q%LQSXW

Table 8. Measurement points

Type Input Output

VMVMVXVY

74HC08-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC

74HCT08-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC

Product data sheet Rev. 1 — 16 July 2012 7 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

Test data is given in Table 9.

Definitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig 7. Load circuitry for measuring switching times

001aah768

negative

pulse

GND

positive

pulse

GND

10 %

90 %

10 % VMVM

VCC

DUT

VIVO

Table 9. Test data

Type Input Load Test

VItr, tfCL

74HC08-Q100 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL

74HCT08-Q100 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL

Product data sheet Rev. 1 — 16 July 2012 8 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

12. Package outline

Fig 8. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 1 — 16 July 2012 9 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

Fig 9. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 1 — 16 July 2012 10 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

Fig 10. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 1 — 16 July 2012 11 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

LSTTL Low-power Schottky Transistor-Transistor Logic

MM Machine Model

TTL Transistor-Transistor Logic

MIL Military

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT08_Q100 v.1 20120716 Product data sheet - -

Product data sheet Rev. 1 — 16 July 2012 12 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — T his NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specif ication for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 1 — 16 July 2012 13 of 14

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) versio n of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 July 2012

Document identifier: 74HC_ HCT08_Q100

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in sectio n ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16 Contact information. . . . . . . . . . . . . . . . . . . . . 13

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14