1
Description
The configurator in-system programming cable (ISP cable) is a PC-only based cable
that attaches to the parallel port of a computer. This cable can be used to download
and verify configuration data cascading up to 8 devices. This cable allows designers to
quickly and economically program Atmel’s family of AT17 configuration memories. It
also provides support for new devices in the AT17 family prior to third-party program-
mer support being available. Therefore, it is a truly portable solution that allows
engineers to work from their lab bench or office.
Supported Devices
The AT17 series configurators can interface with many SRAM-based FPGA families.
This document is limited to example implementations for the following families:
• Atmel – AT94K(FPSLIC), AT40K, AT6K
• Xilinx – XC4000, XC5200, Spartan®, Spartan2, Virtex®, VirtexE
• Altera – EPF6K, EPF8K, EPF10K
• Cypress – Delta39K15, 39K30, 39K50, 39K100, 39K165, 39K200
Software Support
Make sure to use the latest CPS software (http://www.atmel.com/atmel/prod-
ucts/prod185.htm). CPS is used to program configurators and supports both the
ATDH2200E programming board and this ISP cable. CPS also includes a conversion
utility which supports Cypress, Xilinx and Altera file formats. The software, in conjunc-
tion with Atmel ISP cable, can be used to download an Atmel, Cypress, Xilinx or Altera
programming file directly to Atmel’s configurator(s).
• CPS – Configurator Programming System
• GUI Bbased Interface
• Supports Windows® 95/98/2000 and Windows NT®
• Supports up to 8 devices
• Supports programming reset polarity
• Verification routines to validate programming
• Accepts HEX, MCS, POF, RBF, HXU and BST file formats
• Online help
• Ability to enable or disable internal oscillator
For specific information on using the CPS software, refer to the ATDH2200E Program-
ming Kit User Guide.
Rev. 2288A–05/01
In-System
Programming
Cable
ATDH2225
FPGA
Configuration
EEPROM
Memory
2ATDH2225 FPGA
Connecting Cable to
Target System
The cable draws its power from the target system through VCC and GND. Therefore,
power to the cable, as well as to the target FPGA, must be stable. Do not connect any
signals before connecting VCC and GND. Connect the programming dongle to your
printer parallel port. Connect the other end with 10-pin header to your target system
(Figure 1). Your target system should have the 10-pin header pin layout as follow in
order to match the download cable (Figure 2). The pin 9 of the 10-pin header on the tar-
get system is a key pin; therefore, it is cut off. The control signals generated by the
software are fed to the header. The programming algorithms written by Atmel can be
used to program an AT17 device in-system.
Figure 1. In-System Programming Application
Figure 2. In-System Programming Header
Parallel Port
PC
Target System
FPGA FPGA
ATDH2225
Configurator In-System
Programming Cable
(Direct connects to PC)
In-System Programming
Connector Header AT17C/LVXXX
Configurator
1
3
5
7
9
2
4
6
8
10
DATA
SCLK
NC
GND
NC
CE
RESET/OE
NC
VCC
(SER_EN)GND
3
ATDH2225 FPGA
Notes: 1. Pin 10 activates "SER_EN" on target board.
2. Pin 9 is the polarizing pin (cut off).
3. The 10-pin header is 0.1' spacing
Pin 5 and Pin 6 of the 10-pin header are the two signals which able to decode for cas-
cading up to 8 devices. The latest CPS software has the ability to control the 2 signals
SW1, SW2 and by using the A2 pin of the device, you can select up to 8 devices. There-
fore, you could use a 2-to-4 decoder to cascade 8 devices using our existing ISP circuit
(see Figure 3).
Figure 3. ISP of Cascaded AT17C/LV002s in AT40K FPGA Applications
Table 1. 10-pin Header Pin Location on Target Board
1(DATA) 2(CE)
3(SCLK) 4(RESET/OE)
5(SW1) 6(SW2)
7(GND) 8(VCC)
9(NC) 10(SER_EN/GND)
GND
DATA
SCLK
2
34
1
6
7
5
8
910
GND
Vcc Vcc
Vcc
RESET
M1
M2
M0
INIT
DIN
CCLK
CON
FPGA
DATA
SER_EN
#5 AT17C/LV002
CE
RESET/OE
READY
RESET
Vcc
READY
CLK
CEO(A2)
#1 AT17C/LV002
CEO(A2)
SER_EN
CLK
CE
RESET/OE
DATA
Vcc
#7 AT17C/LV002 #3 AT17C/LV002
DATA
RESET/OE
CE
CLK
SER_EN
CEO(A2)
READY
DATA
RESET/OE
SER_EN
CLK
CE
READY
CLK
0
1
2
3
SW1 SW2
VccVccVcc
SW1 SW2
2-to-4
decoder
DATA
SER_EN
#6 AT17C/LV002
CE
RESET/OE
READY READY
CLK
CEO(A2)
#2 AT17C/LV002
CEO(A2)
SER_EN
CLK
CE
RESET/OE
DATA
#8 AT17C/LV002 #4 AT17C/LV002
DATA
RESET/OE
CE
CLK
SER_EN
CEO(A2)
READY
DATA
RESET/OE
SER_EN
CLK
CE
CEO(A2)
READY
VCC
CLK
CEO(A2)
Reset/OE
CE
VCC
VCC
4ATDH2225 FPGA
Note: No additional logic required, SW1 and SW2 not used.
Note: SW1 and some additional logic required for selecting up to 4 devices.
Note: SW1, SW2 and some additional logic required for selecting up to 8 devices.
Note: 2 to 4 devices and some additional logic required for selecting up to 4 devices.
The AT17C/LV020 device is implemented using two 1-Mb Configurator EEPROMs in a
multi-chip module. The A2 pin of the first internal 1Mb is set to Low by the internal pull-
down circuitry. An external 4.7 kΩ pull-up must be connected to the A2 pin of the second
internal 1Mb in order to program the second device. To work with the AT17C/LV020
devices, A2 should always have a pull up on the target system. The CPS software will
implement the correct A2 value to program both internal devices. In fact, to program an
AT17C/LV020 is just like programming two 1-Mb Configurator EEPROMs in casacade
configuration.
Table 2. 2 Devices
Device A2
Device #1 pull down
Device #2 pull up
Table 3. 4 Devices
Device SW1 A2
Device #1 0 pull down
Device #2 1 pull down
Device #3 0 pull up
Device #4 1 pull up
Table 4. 8 Devices
Device SW1 SW2 A2
Device #1 0 0 pull down
Device #2 0 1 pull down
Device #3 1 0 pull down
Device #4 1 1 pull down
Device #5 0 0 pull up
Device #6 0 1 pull up
Device #7 1 0 pull up
Device #8 1 1 pull up
Table 5. For 020 Max. is 4 Devices
Device SW2 SW1
Device #1 0 0
Device #2 0 1
Device #3 1 0
Device #4 1 1
5
ATDH2225 FPGA
Due to the fact that the AT17C/LV002 device is a single-die solution, an external pull-up
or pull-down resistor can be connected to the A2 pin in order to program the data to the
device. As long as the software A2 setting is matched with the hardware A2 pin setting,
the data can be programmed to the device.
The tables on page 4 allow you to select any device out of the 8 devices, which can
work with the ISP download cable. The circuit is limited to example implementation for
the Atmel vendor only. It is the same idea for Xilinx and Altera applications. In addition,
user can still use the existing ISP circuit, which from the 2-megabit cascade document
with the same ISP download cable.
Related Documents ATDH2200E Programming Kit User Guide
AT17C/LV device datasheet
Programming Specification for Atmel’s FPGA Serial Configuration Memories
Technical Support Use the ATDH2200E Programming Kit User Guide
Review the Configurator FAQ at www.atmel.com
Contact your local Atmel representative or distributor who provided the ISP download
cable for technical support
Contact your local Atmel FAE (available at most sales offices)
Contact the Atmel configurator technical support hotline:
(408) 436-4119 (9:00 AM - 6:00 PM PST)
E-mail Atmel configurator technical support: configurator@atmel.com
Fax your inquires to “Configurator Tech Support” at:
(408) 487-2637
6ATDH2225 FPGA
Schematic This cable would perform ISP without the use of the ATDH2200 board. The software
used would be CPS.
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
VCC
4.7K
2
4
6
8
11
13
15
17
1
19
3
5
7
9
12
14
16
18
TriState
BiDir Data
Harris CD74LPT244
ATMEL CORPORATION
Size: Document Number: Rev:
ACHW5450 (ATDH2200) 9
Sheet: 1 OF 1Date: September 22, 1999
Title:
FPGA Configurator Programmer
1
14 2
15 3
16 4
17 5
18 6
19 7
20 8
21 9
22 10
23 11
25 13
24 12
1
3
5
7
9
2
4
6
8
10
DI
CLK
DO
GND
NC
CE
RESET/OE
ERR
VCC
GND
VCC
VCC
GND
20
10
VCC
DATA_IN
CE_IN
RESET/OE_IN
CLK_IN
ACK
RESET/OE_IN
CLK_IN
CE_IN
D0
DATA
ACK
RESET/OE
CE
.1uF
22 ohms
CLK
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Atmel Headquarters Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
Atmel SarL
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex
France
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
Atmel Smart Card ICs
Scottish Enterprise Technology Park
East Kilbride, Scotland G75 0QR
TEL (44) 1355-357-000
FAX (44) 1355-242-743
Atmel Grenoble
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex
France
TEL (33) 4-7658-3000
FAX (33) 4-7658-3480
Atmel Configurator Hotline
1-(408) 436-4119
Atmel Configurator e-mail
configurator@atmel.com
FAQ
Available on web site
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
Printed on recycled paper.
2288A–05/01/xM
Spartan and Virtex are the registered trademarks of Xilinx Corporation.
Windows® 95/98/2000 and Windows NT® are the registered trademarks of Microsoft Corporation.
Other terms and product names may be trademarks of others.
