PD - 96058 IRLR7843CPbF IRLU7843CPbF HEXFET(R) Power MOSFET Applications l l l High Frequency Synchronous Buck Converters for Computer Processor Power High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Lead-Free VDSS 30V RDS(on) max 3.3m: Qg 34nC Benefits l l l Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current D-Pak I-Pak IRLR7843CPbF IRLU7843CPbF Absolute Maximum Ratings Parameter Max. Units 30 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V 20 161 113 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current PD @TC = 25C Maximum Power Dissipation PD @TC = 100C Maximum Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range ID @ TC = 25C ID @ TC = 100C c f f A 620 g g 140 W 71 0.95 -55 to + 175 Soldering Temperature, for 10 seconds W/C C 300 (1.6mm from case) Thermal Resistance Parameter RJC RJA Junction-to-Case Junction-to-Ambient (PCB Mount) RJA Junction-to-Ambient Notes through www.irf.com g Typ. Max. --- 1.05 --- 50 --- 110 Units C/W are on page 11 1 05/31/06 IRLR/U7843CPbF Static @ TJ = 25C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions BVDSS VDSS/TJ RDS(on) Drain-to-Source Breakdown Voltage 30 --- --- Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance --- --- 19 2.6 --- 3.3 VGS(th) VGS(th)/TJ IDSS Gate Threshold Voltage --- 1.5 3.2 --- 4.0 2.3 Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current --- --- -5.4 --- --- 1.0 IGSS Gate-to-Source Forward Leakage --- --- --- --- 150 100 nA VDS = 24V, VGS = 0V, TJ = 125C VGS = 20V Gate-to-Source Reverse Leakage Forward Transconductance --- 37 --- --- -100 --- S VGS = -20V VDS = 15V, ID = 12A Total Gate Charge Pre-Vth Gate-to-Source Charge --- --- 34 9.1 50 --- Post-Vth Gate-to-Source Charge Gate-to-Drain Charge --- --- 2.5 12 --- --- Qgodr Qsw Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) --- --- 10 15 --- --- Qoss td(on) Output Charge Turn-On Delay Time --- --- 21 25 --- --- tr td(off) Rise Time Turn-Off Delay Time --- --- 42 34 --- --- tf Ciss Fall Time Input Capacitance --- --- 19 4380 --- --- Coss Crss Output Capacitance Reverse Transfer Capacitance --- --- 940 430 --- --- gfs Qg Qgs1 Qgs2 Qgd V VGS = 0V, ID = 250A mV/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 15A e = 12A e V VGS = 4.5V, ID VDS = VGS, ID = 250A mV/C A VDS = 24V, VGS = 0V VDS = 15V nC VGS = 4.5V ID = 12A See Fig. 16 nC ns VDS = 15V, VGS = 0V VDD = 15V, VGS = 4.5V e ID = 12A Clamped Inductive Load VGS = 0V pF VDS = 15V = 1.0MHz Avalanche Characteristics EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current EAR Repetitive Avalanche Energy c d c Typ. --- --- Max. 1440 12 Units mJ A --- 14 mJ Diode Characteristics Parameter Min. Typ. Max. Units 161 f Conditions IS Continuous Source Current --- --- ISM (Body Diode) Pulsed Source Current --- --- 620 VSD (Body Diode) Diode Forward Voltage --- --- 1.0 V p-n junction diode. TJ = 25C, IS = 12A, VGS = 0V trr Qrr Reverse Recovery Time Reverse Recovery Charge --- --- 39 36 59 54 ns nC TJ = 25C, IF = 12A, VDD = 15V di/dt = 100A/s ton Forward Turn-On Time 2 c MOSFET symbol A showing the integral reverse e e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRLR/U7843CPbF 1000 1000 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP 100 10 2.5V 1 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 1 0.1 1 10 2.5V 10 20s PULSE WIDTH Tj = 175C 20s PULSE WIDTH Tj = 25C 0.1 100 0.1 100 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 T J = 175C T J = 25C 10 VDS = 15V 20s PULSE WIDTH 1 2.0 3.0 4.0 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com ID = 30A VGS = 10V 1.5 (Normalized) 100 RDS(on) , Drain-to-Source On Resistance 1000 ID, Drain-to-Source Current () 1 1.0 0.5 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRLR/U7843CPbF 12 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds Crss = C gd ID= 12A SHORTED VGS, Gate-to-Source Voltage (V) 100000 C, Capacitance (pF) Coss = Cds + Cgd 10000 Ciss Coss 1000 Crss VDS= 24V VDS= 15V 10 8 6 4 2 0 100 1 10 0 100 20 80 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 1000.0 10000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 60 Q G Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) 100.0 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 T J = 175C 10.0 1.0 T J = 25C 100 100sec 10 1msec Tc = 25C Tj = 175C Single Pulse VGS = 0V 10msec 1 0.1 0.0 0.5 1.0 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 40 1.5 0.1 1.0 10.0 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U7843CPbF 160 2.5 VGS(th) Gate threshold Voltage (V) ID , Drain Current (A) LIMITED BY PACKAGE 120 80 40 2.0 ID = 250A 1.5 1.0 0.5 0 25 50 75 100 125 150 0.0 175 -75 -50 -25 T C , Case Temperature (C) 0 25 50 75 100 125 150 175 T J , Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.1 J 0.05 0.02 0.01 0.01 R1 R1 J 1 R2 R2 C 2 1 2 Ri (C/W) 0.5084 i (sec) 0.000392 0.5423 0.011108 Ci= i/Ri Ci= i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U7843CPbF 15V D.U.T RG + V - DD IAS 20V VGS A 0.01 tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS, Single Pulse Avalanche Energy (mJ) DRIVER L VDS 6000 ID 8.6A 9.6A BOTTOM 12A TOP 5000 4000 3000 2000 1000 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature (C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1s Duty Factor < 0.1% 50K 12V .2F .3F D.U.T. + V - DS Fig 14a. Switching Time Test Circuit VDS 90% VGS 3mA IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 10% VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms 6 www.irf.com IRLR/U7843CPbF D.U.T Driver Gate Drive P.W. + + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer D= Period V DD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRLR/U7843CPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms x Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg x Vg x f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput Q + oss x Vin x f + (Qrr x Vin x f ) 2 This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 x Rds(on ) ) Qgd +I x x Vin x ig Qgs 2 f + I x x Vin x f ig + (Qg x Vg x f ) + Qoss x Vin x f 2 This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U7843CPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information (;$03/( 7+,6,6$1,5)5 3$57180%(5 :,7+$66(0%/< ,17(51$7,21$/ /27&2'( ,5)5 $ 5(&7,),(5 $66(0%/('21:: /2*2 ,17+($66(0%/</,1($ '$7(&2'( <($5 :((. /,1($ 1RWH3LQDVVHPEO\OLQHSRVLWLRQ $66(0%/< LQGLFDWHV/HDG)UHH /27&2'( 3LQDVVHPEO\OLQHSRVLWLRQLQGLFDWHV /HDG)UHHTXDOLILFDWLRQWRWKH&RQVXPHUOHYHO 25 3$57180%(5 ,17(51$7,21$/ 5(&7,),(5 ,5)5 /2*2 '$7(&2'( 3 '(6,*1$7(6/($')5(( 3 '(6,*1$7(6/($')5(( 352'8&7 237,21$/ 352'8&748$/,),('72 $66(0%/< /27&2'( &21680(5/(9(/ 237,21$/ <($5 :((. $ www.irf.com $66(0%/<6,7(&2'( 9 IRLR/U7843CPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information (;$03/( 7+,6,6$1,5)8 :,7+$66(0%/< /27&2'( $66(0%/('21:: ,17+($66(0%/</,1($ 1RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH ,17(51$7,21$/ 5(&7,),(5 /2*2 3$57180%(5 ,5)8 $ $66(0%/< /27&2'( '$7(&2'( <($5 :((. /,1($ 25 ,17(51$7,21$/ 5(&7,),(5 /2*2 3$57180%(5 ,5)8 $66(0%/< /27&2'( 10 '$7(&2'( 3 '(6,*1$7(6/($')5(( 352'8&7 237,21$/ <($5 :((. $ $66(0%/<6,7(&2'( www.irf.com IRLR/U7843CPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 20mH, RG = 25, IAS = 12A. Pulse width 400s; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 05/2006 www.irf.com 11 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/