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05/31/06
IRLR7843CPbF
IRLU7843CPbF
HEXFET® Power MOSFET
Notes through are on page 11
Applications
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
lHigh Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
lLead-Free
Absolute Maximum Ratings
Parameter Units
V
DS Dr ain- to-Sourc e Voltage V
VGS Gat e- to-Source Vo lt age
I
D
@ T
C
= 25°C
Co ntin uo us D r ai n C ur rent , V
GS
@ 10V
ID @ TC = 10 0°C
Co ntin uo us D r ai n C ur rent , V
GS
@ 10V
A
I
DM
Pulsed D rai n C urrent
c
PD @TC = 25°C
g
W
P
D
@T
C
= 100°C
g
Linear Derating F actor W/°C
T
J Operatin g Junction and °C
TSTG Stor ag e Tempe r ature Range
Soldering Temperature, for 10 seconds
Thermal Resist ance
Parameter Typ. Max. Units
R
θJC Junction-to-Case ––– 1.05
R
θJA
Junctio n-to-Ambient ( P CB Mount)
g
––– 50 °C/W
R
θJA Junction-to-Ambient ––– 110
140
Max.
161
f
113
f
620
± 20
30
0.95
71
300 ( 1.6mm f rom ca s e)
-55 to + 17 5
V
DSS
R
DS(on)
max
Qg
30V
3.3m
:
34nC
D-Pak
IRLR7843CPbF I-Pak
IRLU7843CPbF
PD - 96058
IRLR/U7843CPbF
2www.irf.com
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min.
Typ.
Max.
Units
BV
DSS Dr ai n- to-Sour c e Br eakd ow n V oltage 30 ––– ––– V
∆Β
V
DSS
/
∆
T
J Br eakdown Voltage Temp. Co effi cient ––– 19 –– – mV/°C
R
DS(on) Static D rain-to-S ourc e On- R e s i s tance ––– 2. 6 3.3
m
Ω
––– 3.2 4.0
V
GS(th) Gate Threshold Voltage 1.5 ––– 2.3 V
∆
V
GS(th)
/
∆
T
JGate Thr es h old Vo ltage C oe f ficient ––– -5 .4 ––– mV/° C
I
DSS Dr ai n- to-Sour c e Le akage Cu r rent ––– ––– 1. 0 µA
––– ––– 150
I
GSS Gate-to-S ourc e Fo r war d Leakag e ––– ––– 100 nA
Gate-t o- Sour c e R ev ers e Le ak age ––– ––– -10 0
gfs For ward Tra nsconductance 37 ––– ––– S
Q
gTotal Gate Charge ––– 34 50
Q
gs1 Pre-Vth Gat e-to-Source Charge ––– 9.1 –––
Q
gs2 Post-Vth G ate-to-Source Cha rge ––– 2.5 ––– nC
Q
gd Gate - to- D rai n Charge ––– 12 –– –
Q
godr G ate Cha r ge Ov e r drive ––– 10 ––– Se e Fi g. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
––– 15 –––
Q
oss Output Charge ––– 21 ––– nC
t
d(on) Turn-On Delay Time ––– 25 –––
t
rRise Time ––– 42 –––
t
d(off) Turn-Of f Delay Time ––– 34 ––– ns
t
fFall Time ––– 19 –––
C
iss Input Capacitance ––– 4380 –––
C
oss Out pu t Capacita nc e ––– 940 ––– pF
C
rss Reve r s e Tr a ns fer Capacitance ––– 430 –––
Avalanche Characteristics
Parameter Units
E
AS
Si ngle P ul se Avala nc h e E n er g y
d
mJ
I
AR
Avalanche Current
c
A
E
AR
Repetiti ve Avala nche Energy
c
mJ
Diode Charac teristi cs
Parameter
Min.
Typ.
Max.
Units
I
SCont inuous Source Cur ren t ––– –––
161
f
(Body Diode) A
I
SM Pulsed Source Current ––– ––– 620
(Body Diode)
c
V
SD Diode Fo rw ar d V olta g e –– – ––– 1.0 V
t
rr Reverse Recovery Time ––– 39 59 n s
Q
rr Reverse Recovery Charge ––– 36 54 nC
t
on Forward Turn-On Time
VDS = VGS, ID = 250µ A
VDS = 24V , V GS = 0V
VDS = 24V , V GS = 0V, TJ = 125° C
Conditions
14
Max.
1440
12
ƒ = 1. 0M H z
ID = 12A
VDS = 15V
Conditions
VGS = 0V, ID = 25 0µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 15A
e
VGS = 4.5V , ID = 12A
e
VGS = 20V
VGS = -20V
VDS = 15V , I D = 12A
VDS = 15V , V GS = 0V
VDD = 15V, VGS = 4.5V
e
Cla m ped In du cti v e Lo ad
TJ = 25°C, IF = 12 A, VDD = 15V
di /dt = 100A/µ s
e
TJ = 25°C, IS = 12A, V GS = 0V
e
showing t he
integra l revers e
p-n ju nctio n diode.
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
MOSFET symbol
–––
VGS = 4.5V
Typ.
–––
–––
ID = 12A
VGS = 0V
VDS = 15V
IRLR/U7843CPbF
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Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
2.0 3.0 4.0 5.0
VGS, Gate-to-Sour ce Vol tage (V)
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25° C
TJ = 175° C
VDS = 15V
20µs PU LSE WIDT H
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (° C)
0.5
1.0
1.5
2.0
RDS(on)
,
Drain-to-Source On Resistanc
e
(Normalized)
ID = 30A
VGS = 10V
0.1 110 100
VDS, Dr ain-to-Source Volt age (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PU LSE WIDT H
Tj = 25° C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
0.1 110 100
VDS, Dr ain-to-Source Volt age (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PU LSE WIDT H
Tj = 175° C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
IRLR/U7843CPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Dr ain-to-Sour ce Vol tage (V)
100
1000
10000
100000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds S HORTED
Crss = Cgd
Coss = Cds + Cgd
0 20406080
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 12A
0.0 0.5 1.0 1.5
VSD, Source-t oDrain Volt age (V )
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0.1 1.0 10.0 100.0 1000.0
VDS , Dr ain- toS ource Voltage (V )
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175° C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMI TED BY RDS(on)
100µsec
IRLR/U7843CPbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150 175
TC , Case T em perature (°C)
0
40
80
120
160
ID , Drain Current (A)
LIMI TED BY PACKAGE
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temper ature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular P ulse D urat ion ( sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0. 50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zt hjc + Tc
Ri (°C/W) τi (sec)
0.5084 0.000392
0.5423 0.011108
τJ
τJ
τ1
τ1τ2
τ2
R1
R1R2
R2
τ
τ
C
Ci= i/Ri
Ci= τi/Ri
IRLR/U7843CPbF
6www.irf.com
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starting TJ, Juncti on Temperature (°C)
0
1000
2000
3000
4000
5000
6000
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 8.6A
9.6A
BOTTOM 12A
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
IRLR/U7843CPbF
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRLR/U7843CPbF
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on)
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs2
ig
×Vin ×
f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRLR/U7843CPbF
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D-Pak (TO-252AA) Part Marking Information
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D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
IRLR/U7843CPbF
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I-Pak (TO-251AA) Part Marking Information

/,1($
/2*2
,17(51$7,21$/
5(&7,),(5
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352'8&7237,21$/
3 '(6,*1$7(6/($')5((
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
IRLR/U7843CPbF
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Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 20mH, RG = 25Ω,
IAS = 12A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes:
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FE ED DIRE CT ION
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OT ES :
1
. CONTROLLING DIMENSION : MILLIMETER.
2
. ALL DIMENSION S ARE SHOWN IN MILLIMETERS ( INCHES ).
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTL INE CO NFORMS TO EIA-481.
16 mm
13 INCH
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/2006
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/