1. General description
The 74HC165-Q100; 74HCT165-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC165-Q100; 74HCT165-Q100 are 8-bit parallel-load or serial-in shift registers
with complementary serial outputs (Q7 and Q7) available from the last st age. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Parallel-to-serial data conversion
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Rev. 1 — 17 July 2012 Product data sheet
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 2 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC165D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HCT165D-Q100
74HC165PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT165PW-Q100
74HC165BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT165BQ-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna985
D0
D1
D2
D3
D4
D5
D6
D7
CP CE
DS
Q7
Q7
10
15
2
7
9
6
PL
1
5
4
3
14
13
12
11
mna986
59
10
11
12
13
14
3
4
67
2
15
1
≥ 11C3/
C2[LOAD]
G1[SHIFT]
3D
2D
2D
SRG8
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 3 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
6. Pinning information
6.1 Pinning
Fig 3. Functional diagram
mna992
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
9
7
PL
11
1
DS
10
CP
2Q7
D0 D1 D2 D3 D4 D5 D6 D7
Q7
12 13 14 3 4 5 6
CE
15
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration SO16 and TSSOP16 Fig 5. Pin configuration DHVQFN16
74HC165-Q100
74HCT165-Q100
PL VCC
CP CE
D4 D3
D5 D2
D6 D1
D7 D0
Q7 DS
GND Q7
aaa-003155
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-003156
74HC165-Q100
74HCT165-Q100
Q7 DS
GND(1)
D7 D0
D6 D1
D5 D2
D4 D3
CP CE
GND
Q7
PL
VCC
Transparent top view
710
611
512
413
314
215
8
9
1
16
terminal 1
index area
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 4 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 2. Pin description
Symbol Pin Description
PL 1 asynchronous parallel load input (active LOW)
CP 2 clock input (LOW-to-HIGH edge-triggered)
Q7 7 complementary output from the last stage
GND 8 ground (0 V)
Q7 9 serial output from the last stage
DS 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)
CE 15 clock enable input (active LOW)
VCC 16 positive supply voltage
Table 3. Function table[1]
Operating modes Inputs Qn registers Outputs
PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7
parallel load L X X X L L L to L L H
L X X X H H H to H H L
serial shift H L l X L q0 to q5 q6 q6
HLh X H q0 to q5 q6 q6
HL l X L q0 to q5 q6 q6
HL h X H q0 to q5 q6 q6
hold “do noth i n g” H H X X X q0 q1 to q6 q7 q7
HXHXXq0q1 to q6q7q
7
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 5 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Fig 6. Timing diag ram
CE
CP
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
mna993
inhibit serial shift
load
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current V I < 0.5 V or VI>V
CC +0.5V [1] -20 mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[2] - 500 mW
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 6 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC165-Q100 74HCT165-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.6 7 139 - 1.67 139 ns/V
VCC = 6.0 V--83---ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC165-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4. 5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6. 0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1- 1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --8.0- 80 - 160A
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 7 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
CIinput
capacitance -3.5-- - - - pF
74HCT165-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6. 0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1- ±1 A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --8.0- 80 - 160A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs - 35 126 - 157.5 - 171.5 A
CP CE, and PL inputs - 65 234 - 292.5 - 318.5 A
CIinput
capacitance -3.5-- - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 8 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7. Dynam ic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC165-Q100
tpd propagation
delay CP or CE to Q7, Q7;
see Figure 7 [1]
VCC = 2.0 V - 52 165 - 205 - 250 ns
VCC = 4.5 V - 19 33 - 41 - 50 ns
VCC = 6.0 V - 15 28 - 35 - 43 ns
VCC = 5.0 V; CL=15pF-16---- - ns
PL to Q7, Q7; see Figure 8
VCC = 2.0 V - 50 165 - 205 - 250 ns
VCC = 4.5 V - 18 33 - 41 - 50 ns
VCC = 6.0 V - 14 28 - 35 - 43 ns
VCC = 5.0 V; CL=15pF-15---- - ns
D7 to Q7, Q7; see Figure 9
VCC = 2.0 V - 36 120 - 150 - 180 ns
VCC = 4.5 V - 13 24 - 30 - 36 ns
VCC = 6.0 V - 10 20 - 26 - 31 ns
VCC = 5.0 V; CL=15pF-11---- - ns
tttransition
time Q7, Q7 output; see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
PL input LOW; see Figure 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
trec recovery time PL to CP, CE; see Figure 8
VCC = 2.0 V 100 22 - 125 - 150 - ns
VCC = 4.5 V 20 8 - 25 - 30 - ns
VCC = 6.0 V 17 6 - 21 - 26 - ns
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 9 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
tsu set-up time DS to CP, CE; see Figure 10
VCC = 2.0 V 80 11 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
CE to CP and CP to C E;
see Figure 10
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
Dn to PL; see Figure 11
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
thhold time DS to CP, CE and Dn to PL;
see Figure 10
VCC = 2.0 V 5 6 - 5 - 5 - ns
VCC = 4.5 V 5 2 - 5 - 5 - ns
VCC = 6.0 V 5 2 - 5 - 5 - ns
CE to CP and CP to C E;
see Figure 10
VCC = 2.0 V 5 17 - 5 - 5 - ns
VCC = 4.5 V 5 6- 5 - 5 - ns
VCC = 6.0 V 5 5- 5 - 5 - ns
fmax maximum
frequency CP input; see Figure 7
VCC = 2.0 V 6 17 - 5 - 4 - MHz
VCC = 4.5 V 30 51 - 24 - 20 - MHz
VCC = 6.0 V 35 61 - 28 - 24 - MHz
VCC = 5.0 V; CL=15pF-56---- - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -35---- - pF
Table 7. Dynam ic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 10 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
74HCT165-Q100
tpd propagation
delay CE, CP to Q7, Q 7;
see Figure 7 [1]
VCC = 4.5 V - 17 34 - 43 - 51 ns
VCC = 5.0 V; CL=15pF-14---- - ns
PL to Q7, Q7; see Figure 8
VCC = 4.5 V - 20 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF-17---- - ns
D7 to Q7, Q7; see Figure 9
VCC = 4.5 V - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL=15pF-11---- - ns
tttransition
time Q7, Q7 output; see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP input; see Figure 7
VCC = 4.5 V 16 6 - 20 - 24 - ns
PL input; see Figure 8
VCC = 4.5 V 20 9 - 25 - 30 - ns
trec recovery time PL to CP, CE; see Figure 8
VCC = 4.5 V 20 8 - 25 - 30 - ns
tsu set-up time DS to CP, CE; see Figure 10
VCC = 4.5 V 20 2 - 25 - 30 - ns
CE to CP and CP to C E;
see Figure 10
VCC = 4.5 V 20 7 - 25 - 30 - ns
Dn to PL; see Figure 11
VCC = 4.5 V 20 10 - 25 - 30 - ns
thhold time DS to CP, CE and Dn to PL;
see Figure 10
VCC = 4.5 V 7 1- 9 - 11 - ns
CE to CP and CP to C E;
see Figure 10
VCC = 4.5 V 0 7- 0 - 0 - ns
fmax maximum
frequency CP input; see Figure 7
VCC = 4.5 V 26 44 - 21 - 17 - MHz
VCC = 5.0 V; CL=15pF-48---- - MHz
Table 7. Dynam ic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 11 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC 1.5 V [3] -35---- - pF
Table 7. Dynam ic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width, maximum
clock frequency and output transition times
mna987
CP or CE input
Q7 or Q7 output 90 %
10 % 10 %
90 %
t
PHL
t
THL
t
TLH
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 12 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Para llel load (PL ) pulse wid th , p arallel load to outpu t (Q7 or Q7) propagation delays, p arallel load to clock
(CP) and clock enable (CE) recovery time
mna988
PL input
CE, CP input
Q7 or Q7 output
tPHL
tWtrec
VM
VOH
VI
GND
VI
GND
VOL
VM
VM
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
mna989
D7 input
Q7 output
Q7 output
tPHL
tPHL
VM
VOH
VI
GND
VOH
VOL
VOL
VM
tPLH
tPLH
VM
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 13 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
(1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1.
Fig 10. Waveforms showing set-up and hold times
th
tsu tsu
th
tW
VM
VM
GND
VI
GND
VI
DS input
tsu
VM
mna990
GND
VI
CP, CE input
CP, CE input
(1)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
mna991
Dn input
PL input
t
su
t
h
V
I
GND
V
I
GND
V
M
V
M
t
su
t
h
V
M
V
M
Table 8. Measurement points
Type Input Output
VIVMVM
74HC165-Q100 VCC 0.5VCC 0.5VCC
74HCT165-Q100 3 V 1.3 V 1.3 V
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 14 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC165-Q100 VCC 6ns 15pF, 50 pF 1kopen
74HCT165-Q100 3 V 6 ns 15 pF, 50 pF 1 kopen
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 15 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
13. Package outline
Fig 13. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 16 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Fig 14. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 17 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
Fig 15. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 18 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
14. Abbreviations
15. Revision history
Table 10. Ab br eviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
MIL Military
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT165_Q10 0 v.1 20120717 Product data sheet - -
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 19 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors her eby exp ressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qua lification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT165_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 17 July 2012 20 of 21
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
© NXP B.V. 2012. All r ights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 July 2012
Document identi fier: 74HC_HCT165_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
17 Contact information. . . . . . . . . . . . . . . . . . . . . 20
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
