ADC124S101CIMM/NOPB - NATIONAL SEMICONDUCTOR

CS SCLK

DOUT

DIN

IN1

GND

IN4

IN3 IN2

ADC124S101

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ADC124S101 4 Channel, 500 ksps to 1 Msps, 12-Bit A/D Converter

Check for Samples: ADC124S101

1FEATURES DESCRIPTION

The ADC124S101 is a low-power, four-channel

2• Specified Over a Range of Sample Rates CMOS 12-bit analog-to-digital converter with a high-

• Four Input Channels speed serial interface. Unlike the conventional

• Variable Power Management practice of specifying performance at a single sample

rate only, the ADC124S101 is fully specified over a

• Single Power Supply with 2.7V - 5.25V range sample rate range of 500 ksps to 1 Msps. The

converter is based on a successive-approximation

APPLICATIONS register architecture with an internal track-and-hold

• Portable Systems circuit. It can be configured to accept up to four input

signals at inputs IN1 through IN4.

• Remote Data Acquisition

• Instrumentation and Control Systems The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

KEY SPECIFICATIONS serial interfaces.

• DNL: +0.9/−0.6 LSB (typ) The ADC124S101 operates with a single supply that

• INL: ± 0.64 LSB (typ) can range from +2.7V to +5.25V. Normal power

• SNR: 72.4 dB (typ) consumption using a +3V or +5V supply is 4.3 mW

• Power Consumption and 13.1 mW, respectively. The power-down feature

reduces the power consumption to just 0.14 µW using

– 3V Supply: 4.3 mW (typ) a +3V supply, or 0.32 µW using a +5V supply.

– 5V Supply: 13.1 mW (typ) The ADC124S101 is available in a 10-lead VSSOP

package. Operation over the industrial temperature

range of −40°C to +85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. PIN-COMPATIBLE ALTERNATIVES BY RESOLUTION AND SPEED(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC124S021 ADC124S051 ADC124S101

10-bit ADC104S021 ADC104S051 ADC104S101

8-bit ADC084S021 ADC084S051 ADC084S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Figure 1. 10-Lead VSSOP

See DGS Package

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

IN1

IN4

MUX T/H

SCLK

GND

DIN

DOUT

CONTROL

LOGIC

12-Bit

SUCCESSIVE

APPROXIMATION

ADC

GND

ADC124S101

SNAS283D –MARCH 2005–REVISED MARCH 2013

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Block Diagram

Figure 2.

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No. Symbol Description

ANALOG I/O

4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA.

DIGITAL I/O

10 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

9 DOUT Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.

Digital data input. The ADC124S101's Control Register is loaded through this pin on rising edges of

8 DIN the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long

1 CS as CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed

2 VAto GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power

pin.

3 GND The ground return for the supply and signals.

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Absolute Maximum Ratings(1)(2)(3)

Supply Voltage VA−0.3V to 6.5V

Voltage on Any Pin to GND −0.3V to VA+0.3V

Input Current at Any Pin (4) ±10 mA

Package Input Current(4) ±20 mA

Power Consumption at TA= 25°C See (5)

ESD Susceptibility (6)

Human Body Model 2500V

Machine Model 250V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to

10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an

input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VApin. The current into the VApin is

limited by the Analog Supply Voltage specification.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax −TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through zero ohms.

Operating Ratings(1)(2)

Operating Temperature Range −40°C ≤TA≤+85°C

VASupply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range −0.3V to VA

Clock Frequency 50 kHz to 16 MHz

Analog Input Voltage 0V to VA

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

Package Thermal Resistance(1)(2)

Package θJA

10-lead VSSOP 190°C / W

(1) Soldering process must comply with TI's Reflow Temperature Profile specifications.

(2) Reflow temperature profiles are different for lead-free and non-lead-free packages.

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ADC124S101

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ADC124S101 Converter Electrical Characteristics(1)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 8 to 16 MHz, fSAMPLE = 500 ksps to 1 Msps,

CL= 35 pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits(2) Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

+0.64 +1.6 LSB (max)

INL Integral Non-Linearity −0.64 −1.2 LSB (min)

+0.9 +1.6 LSB (max)

DNL Differential Non-Linearity −0.6 −1.0 LSB (min)

VOFF Offset Error 0.44 ±1.3 LSB (max)

OEM Channel to Channel Offset Error Match ±0.1 ±1.0 LSB (max)

FSE Full Scale Error −0.34 ±1.5 LSB (max)

Channel to Channel Full-Scale Error

FSEM ±0.1 ±1.0 LSB (max)

Match

DYNAMIC CONVERTER CHARACTERISTICS

VA= +2.7V to 5.25V

SINAD Signal-to-Noise Plus Distortion Ratio 72 69.2 dB (min)

fIN = 40.3 kHz, −0.02 dBFS

VA= +2.7V to 5.25V

SNR Signal-to-Noise Ratio 72.4 70.6 dB (min)

fIN = 40.3 kHz, −0.02 dBFS

VA= +2.7V to 5.25V

THD Total Harmonic Distortion −82 −75 dB (max)

fIN = 40.3 kHz, −0.02 dBFS

VA= +2.7V to 5.25V

SFDR Spurious-Free Dynamic Range 83 76 dB (min)

fIN = 40.3 kHz, −0.02 dBFS

ENOB Effective Number of Bits VA= +2.7V to 5.25V 11.7 11.2 Bits (min)

VA= +5.25V

Channel-to-Channel Crosstalk −86 dB

fIN = 40.3 kHz

Intermodulation Distortion, Second VA= +5.25V −87 dB

Order Terms fa= 40.161 kHz, fb= 41.015 kHz

IMD Intermodulation Distortion, Third Order VA= +5.25V −88 dB

Terms fa= 40.161 kHz, fb= 41.015 kHz

VA= +5V 11 MHz

FPBW -3 dB Full Power Bandwidth VA= +3V 8 MHz

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±0.02 ±1 µA (max)

Track Mode 33 pF

CINA Input Capacitance Hold Mode 3 pF

DIGITAL INPUT CHARACTERISTICS

VA= +5.25V 2.4 V (min)

VIH Input High Voltage VA= +3.6V 2.1 V (min)

VIL Input Low Voltage 0.8 V (max)

IIN Input Current VIN = 0V or VA±0.1 ±10 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

ISOURCE = 200 µA VA−0.03 VA−0.5 V (min)

VOH Output High Voltage ISOURCE = 1 mA VA−0.10

ISINK = 200 µA 0.02 0.4 V (max)

VOL Output Low Voltage ISINK = 1 mA 0.1

IOZH, IOZL TRI-STATE Leakage Current ±1 µA (max)

(1) Min/max specification limits are specified by design, test, or statistical analysis.

(2) Tested limits are specified to AOQL (Average Outgoing Quality Level).

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ADC124S101 Converter Electrical Characteristics(1) (continued)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 8 to 16 MHz, fSAMPLE = 500 ksps to 1 Msps,

CL= 35 pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits(2) Units

COUT TRI-STATE Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (CL= 10 pF)

2.7 V (min)

VASupply Voltage 5.25 V (max)

VA= +5.25V, 2.5 3.0 mA (max)

fSAMPLE = 1 Msps, fIN = 40 kHz

Supply Current, Normal Mode

(Operational, CS low) VA= +3.6V, 1.2 1.6 mA (max)

fSAMPLE = 1 Msps, fIN = 40 kHz

IAVA= +5.25V, 60 nA

fSAMPLE = 0 ksps

Supply Current, Shutdown (CS high) VA= +3.6V, 38 nA

fSAMPLE = 0 ksps

VA= +5.25V 13.1 15.8 mW (max)

Power Consumption, Normal Mode

(Operational, CS low) VA= +3.6V 4.3 5.8 mW (max)

PDVA= +5.25V 0.32 µW

Power Consumption, Shutdown (CS

high) VA= +3.6V 0.14 µW

AC ELECTRICAL CHARACTERISTICS

8MHz (min)

fSCLK Maximum Clock Frequency See(3) 16 MHz (max)

500 ksps (min)

fSSample Rate See(3) 1Msps (max)

tCONV Conversion Time 13 SCLK cycles

30 % (min)

DC SCLK Duty Cycle fSCLK = 16 MHz 50 70 % (max)

tACQ Track/Hold Acquisition Time Full-Scale Step Input 3SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

(3) This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is

specified under Operating Ratings.

ADC124S101 Timing Specifications

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to

1 Msps, CL= 35 pF, Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits(1) Units

VA= +3.0V −3.5

tCSU Setup Time SCLK High to CS Falling Edge See(2) 10 ns (min)

VA= +5.0V −0.5

VA= +3.0V +4.5

tCLH Hold time SCLK Low to CS Falling Edge See(2) 10 ns (min)

VA= +5.0V +1.5

VA= +3.0V +4

tEN Delay from CS Until DOUT active 30 ns (max)

VA= +5.0V +2

VA= +3.0V +14.5

tACC Data Access Time after SCLK Falling Edge 30 ns (max)

VA= +5.0V +13

tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)

tHData Valid SCLK Hold Time +3 10 ns (min)

tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min)

(1) Tested limits are specified to AOQL (Average Outgoing Quality Level).

(2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

Product Folder Links: ADC124S101

IOL

200 PA

IOH

200 PA

1.6V

To Output Pin

35 pF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8

Track Hold

Power Up

Track Hold

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

9 10

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 DB8 DB7

DIN

DOUT

Power Up

SCLK

Power Down

Control register Control register

ADC124S101

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ADC124S101 Timing Specifications (continued)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 ksps to

1 Msps, CL= 35 pF, Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits(1) Units

tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min)

VA= +3.0V 1.8

Output Falling VA= +5.0V 1.3

tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max)

VA= +3.0V 1.0

Output Rising VA= +5.0V 1.0

Timing Diagrams

Figure 3. ADC124S101 Timing Diagram

Figure 4. Timing Test Circuit

Product Folder Links: ADC124S101

tCSU

tCLH

SCLK

tCONVERT

tACQ

Z3 Z2 Z1 Z0 DB10

DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

DB11 DB9 DB8 DB1

1687654321

DB0

DIN

DOUT

SCLK

tEN tCL tACC tDIS

tCH

tSU

ADC124S101

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Figure 5. ADC124S101 Serial Timing Diagram

Figure 6. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold

capacitor to charge up to the input voltage.

APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the

input signal is acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy

from one analog input that appears at the measured analog input.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below

VREF+and is defined as:

VFSE = Vmax + 1.5 LSB – VREF+(1)

where Vmax is the voltage at which the transition to the maximum code occurs. FSE can be

expressed in Volts, LSB or percent of full scale range.

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF −1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last

code transition). The deviation of any given code from this straight line is measured from the center of that

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log20=THD 

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code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the

power in the second and third order intermodulation products to the power in one of the original

frequencies. IMD is usually expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be

reached with any input value. The ADC124S101 is ensured not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

d.c. or the harmonics included in THD.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of

the input signal to the rms value of all of the other spectral components below half the clock frequency,

including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal

amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral

component is any signal present in the output spectrum that is not present at the input and may or may

not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five

harmonic components at the output to the rms level of the input signal frequency as seen at the output.

THD is calculated as

(2)

where Af1is the RMS power of the input frequency at the output and Af2through Af6are the

RMS power in the first 5 harmonic frequencies.

THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the

acquisition time plus the conversion and read out times. In the case of the ADC124S101, this is 16 SCLK

periods.

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Typical Performance Characteristics

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

DNL - VA= 3.0V INL - VA= 3.0V

Figure 7. Figure 8.

DNL - VA= 5.0V INL - VA= 5.0V

Figure 9. Figure 10.

DNL vs. Supply INL vs. Supply

Figure 11. Figure 12.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

DNL vs. Clock Frequency INL vs. Clock Frequency

Figure 13. Figure 14.

DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle

Figure 15. Figure 16.

DNL vs. Temperature INL vs. Temperature

Figure 17. Figure 18.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

SNR vs. Supply THD vs. Supply

Figure 19. Figure 20.

SNR vs. Clock Frequency THD vs. Clock Frequency

Figure 21. Figure 22.

SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle

Figure 23. Figure 24.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

SNR vs. Input Frequency THD vs. Input Frequency

Figure 25. Figure 26.

SNR vs. Temperature THD vs. Temperature

Figure 27. Figure 28.

SFDR vs. Supply SINAD vs. Supply

Figure 29. Figure 30.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

SFDR vs. Clock Frequency SINAD vs. Clock Frequency

Figure 31. Figure 32.

SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle

Figure 33. Figure 34.

SFDR vs. Input Frequency SINAD vs. Input Frequency

Figure 35. Figure 36.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

SFDR vs. Temperature SINAD vs. Temperature

Figure 37. Figure 38.

ENOB vs. Supply ENOB vs. Clock Frequency

Figure 39. Figure 40.

ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency

Figure 41. Figure 42.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps, fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

ENOB vs. Temperature Spectral Response - 3V, 500 ksps

Figure 43. Figure 44.

Spectral Response - 5V, 500 ksps Spectral Response - 3V, 1.0 Msps

Figure 45. Figure 46.

Spectral Response - 5V, 1.0 Msps Power Consumption vs. Throughput

Figure 47. Figure 48.

Product Folder Links: ADC124S101

IN1

MUX

AGND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN4

IN1

MUX

AGND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN4

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APPLICATIONS INFORMATION

ADC124S101 OPERATION

The ADC124S101 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter. Simplified schematics of the ADC124S101 in both track and hold modes

are shown in Figure 49 and Figure 50, respectively. In Figure 49, the ADC124S101 is in track mode: switch SW1

connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances

the comparator inputs. The ADC124S101 is in this state for the first three SCLK cycles after CS is brought low.

Figure 50 shows the ADC124S101 in hold mode: switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The ADC124S101 is in this state for the fourth through sixteenth SCLK cycles after CS

is brought low.

The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of

16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is

clocked into the DIN pin to indicate the multiplexer address for the next conversion.

Figure 49. ADC124S101 in Track Mode

Figure 50. ADC124S101 in Hold Mode

USING THE ADC124S101

A ADC124S101 timing diagram and a serial interface timing diagram for the ADC124S101 are shown in the

Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers.

SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data

output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the

ADC124S101's Control Register is placed on DIN, the serial data input pin. New data is written to the ADC at

DIN with each conversion.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain

an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when

CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a

power down state when CS is high, and also between continuous conversion cycles.

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During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13

SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock. If

there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK

after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK,

where "N" is an integer.

When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the

subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track

mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC

enters the track mode on the first falling edge of SCLK after the falling edge of CS.

During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS.

For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion

after the current one. See Table 2,Table 3, and Table 4.

If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking

data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum

tCSU and tCLH times given in the Timing Specifications..

There are no power-up delays or dummy conversions required with the ADC124S101. The ADC is able to

sample and convert an input to full conversion immediately following power up. The first conversion result after

power-up will be that of IN1.

Table 2. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

Table 3. Control Register Bit Descriptions

Bit #: Symbol: Description

7 - 6, 2 - 0 DONTC Don't care. The value of these bits do not affect device operation.

5 ADD2 These three bits determine which input channel will be sampled and converted in the next

track/hold cycle. The mapping between codes and channels is shown in Table 4.

4 ADD1

3 ADD0

Table 4. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

x 0 0 IN1 (Default)

x 0 1 IN2

x 1 0 IN3

x 1 1 IN4

Product Folder Links: ADC124S101

IN1

IN2 MICROPROCESSOR

DSP

SCLK

DIN

DOUT

GND

ADC124S101

LP2950 5V

1 PF

TANT 0.1 PF 0.1 PF1 PF

IN3

IN4

0V +VA - 1.5LSB

0.5LSB ANALOG INPUT

1LSB = VA/4096

ADC CODE

111...111

111...110

111...000

011...111

000...010

000...001

000...000

ADC124S101

SNAS283D –MARCH 2005–REVISED MARCH 2013

www.ti.com

ADC124S101 TRANSFER FUNCTION

The output format of the ADC124S101 is straight binary. Code transitions occur midway between successive

integer LSB values. The LSB width for the ADC124S101 is VA/4096. The ideal transfer characteristic is shown in

Figure 51. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a

voltage of VA/8192. Other code transitions occur at steps of one LSB.

Figure 51. Ideal Transfer Characteristic

TYPICAL APPLICATION CIRCUIT

A typical application of the ADC124S101 is shown in Figure 52. Power is provided in this example by the LP2950

low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin

is bypassed with a capacitor network located close to the ADC124S101.

Because the reference for the ADC124S101 is the supply voltage, any noise on the supply will degrade device

noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide

sufficient decoupling from other circuitry to keep noise off the ADC124S101 supply pin. Because of the

ADC124S101's low power requirements, it is also possible to use a precision reference as a power supply to

maximize performance. The four-wire interface is also shown connected to a microprocessor or DSP.

Figure 52. Typical Application Circuit

ANALOG INPUTS

An equivalent circuit for one of the ADC124S101's input channels is shown in Figure 53. Diodes D1 and D2

provide ESD protection for the analog inputs. At no time should any input go beyond (VA+ 300 mV) or (GND −

300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason,

these ESD diodes should NOT be used to clamp the input signal.

Product Folder Links: ADC124S101

VIN

30 pF

3 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

ADC124S101

www.ti.com

SNAS283D –MARCH 2005–REVISED MARCH 2013

The capacitor C1 in Figure 53 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor

R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the

ADC124S101 sampling capacitor, and is typically 30 pF. The ADC124S101 will deliver best performance when

driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.

This is especially important when using the ADC124S101 to sample AC signals. Also important when sampling

dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic

performance.

Figure 53. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC124S101's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital

input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted

before VAwithout any latch-up risk.

POWER SUPPLY CONSIDERATIONS

The ADC124S101 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with

one exception: the ADC124S101 automatically enters power-down mode between the 16th falling edge of a

conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams).

The ADC124S101 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles.

The ADC124S101 will perform conversions continuously as long as CS is held low.

The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.

The Power Consumption vs. Sample Rate curve in the Typical Performance Characteristics section shows the

typical power consumption of the ADC124S101 versus throughput. To calculate the power consumption, simply

multiply the fraction of time spent in the normal mode by the normal mode power consumption, and add the

fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation.

Power Management

When the ADC124S101 is operated continuously in normal mode, the maximum throughput is fSCLK/16.

Throughput may be traded for power consumption by running fSCLK at its maximum 16 MHz and performing fewer

conversions per unit time, putting the ADC124S101 into shutdown mode between conversions. A plot of typical

power consumption versus throughput is shown in the Typical Performance Characteristics section. To calculate

the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the

normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the

shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part

back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is

because the power consumption in the shutdown mode is so small that it can be ignored for all practical

purposes.

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the power supply, VA. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the supply. If these

variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the

substrate that will degrade noise performance if that current is large enough. The larger is the output

capacitance, the more current flows through the die substrate and the greater is the noise coupled into the

analog channel, degrading noise performance.

Product Folder Links: ADC124S101

ADC124S101

SNAS283D –MARCH 2005–REVISED MARCH 2013

www.ti.com

To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load

capacitance is greater than 35 pF, use a 100 Ωseries resistor at the ADC output, located as close to the ADC

output pin as practical. This will limit the charge and discharge current of the output capacitance and improve

noise performance.

Product Folder Links: ADC124S101

ADC124S101

www.ti.com

SNAS283D –MARCH 2005–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision C (March 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 20

Product Folder Links: ADC124S101

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC124S101CIMM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 X27C

ADC124S101CIMMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 X27C

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC124S101CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

ADC124S101CIMMX/NOP

BVSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC124S101CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0

ADC124S101CIMMX/NOP

BVSSOP DGS 10 3500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

5.05

4.75

1.1 MAX

8X 0.5

10X 0.27

0.17

0.15

0.05

TYP

0.23

0.13

0 - 8

0.25

GAGE PLANE

0.7

0.4

NOTE 3

3.1

2.9

NOTE 4

3.1

2.9

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

110

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 3.200

www.ti.com

EXAMPLE BOARD LAYOUT

(4.4)

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

10X (1.45)

10X (0.3)

8X (0.5)

(R )

TYP

0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:10X

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(4.4)

8X (0.5)

10X (0.3)

10X (1.45)

(R ) TYP0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

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