RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM S E M I C O N D U C T O R 50A, 60V, ESD Rated, Avalanche Rated, Logic Level N-Channel Enhancement-Mode Power MOSFETs July 1996 Features * * * * * * * Packages JEDEC STYLE TO-247 50A, 60V rDS(ON) = 0.022 2kV ESD Protected Temperature Compensating PSPICE Model Peak Current vs Pulse Width Curve UIS Rating Curve +175oC Operating Temperature SOURCE DRAIN GATE DRAIN (FLANGE) Description The RFG50N06LE, RFP50N06LE, RF1S50N06LE, and RF1S50N06LESM are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) PACKAGE AVAILABILITY PACKAGE BRAND RFG50N06LE TO-247 FG50N06L RFP50N06LE TO-220AB FP50N06L RF1S50N06LE TO-262AA F50N06LE RF1S50N06LESM TO-263AB F50N06LE JEDEC TO-262AA Note: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, i.e. RF1S50N06LESM9A. Formerly developmental type TA49164. Symbol SOURCE DRAIN GATE DRAIN (FLANGE) A PART NUMBER D JEDEC TO-263AB G M A A DRAIN (FLANGE) GATE SOURCE S Absolute Maximum Ratings TC = +25oC Drain-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain-Gate Voltage (RGS = 1M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate-Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TSTG, TJ Soldering Temperature of Leads for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . ESD RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM 60 60 10 50 Refer to Peak Current Curve Refer to UIS Curve A 142 0.95 -55 to +175 260 2 W W/oC oC oC kV CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright (c) Harris Corporation 1996 1 UNITS V V V File Number 4072.1 Specifications RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM Electrical Specifications TC = +25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain-Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V 60 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 1 - 2 V TC = +25oC - - 1 A TC = +150oC - - 50 A VGS = 10V - - 10 A ID = 50A, VGS = 5V - - 0.022 VDD = 30V, ID = 50A, RL = 0.6, VGS = 5V, RGS = 2.5 - - 230 ns - 20 - ns tR - 170 - ns tD(OFF) - 48 - ns tF - 90 - ns tOFF - - 165 ns - 96 120 nC - 57 70 nC Zero Gate Voltage Drain Current IDSS Gate-Source Leakage Current IGSS On Resistance rDS(ON) Turn-On Time tON Turn-On Delay Time tD(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDS = 60V, VGS = 0V Total Gate Charge QG(TOT) VGS = 0V to 10V Gate Charge at 5V QG(5) VGS = 0V to 5V QG(TH) VGS = 0V to 1V - 2.2 2.7 nC VDS = 25V, VGS = 0V, f = 1MHz - 2100 - pF Threshold Gate Charge VDD = 48V, ID = 50A, RL = 0.96 Input Capacitance CISS Output Capacitance COSS - 600 - pF Reverse Transfer Capacitance CRSS - 230 - pF Thermal Resistance Junction-to-Case RJC - - 1.05 oC/W Thermal Resistance Junction-to-Ambient RJA TO-247 - - 30 oC/W TO-220, TO-262, and TO-263 - - 80 oC/W MIN TYP MAX UNITS Source-Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS Forward Voltage VSD ISD = 50A - - 1.5 V Reverse Recovery Time tRR ISD = 50A, dISD/dt = 100A/s - - 130 ns 2 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM Typical Performance Curves TC = +25oC 10 ZJC, NORMALIZED THERMAL RESPONSE ID, DRAIN CURRENT (A) 500 100 100s 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10ms 100ms DC 100 1 PDM 0.1 t1 t2 SINGLE PULSE VDSS MAX = 60V 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC DUTY CYCLE 0.5 0.2 0.1 0.05 0.02 0.01 0.01 10-5 200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 10-4 10-3 10-2 10-1 FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TC = +25oC IDM, PEAK CURRENT CAPABILITY (A) 60 ID, DRAIN CURRENT (A) 50 40 30 20 10 0 50 75 100 125 150 1000 VGS = 10V VGS = 5V 100 THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 175 TC, CASE TEMPERATURE (oC) 10-4 10-3 FOR TEMPERATURES ABOVE +25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 10-2 10-1 100 FIGURE 4. PEAK CURRENT CAPABILITY PULSE DURATION = 250s, TC = +25oC VDD = 15V ID(ON), ON-STATE DRAIN CURRENT (A) 100 VGS = 10V ID, DRAIN CURRENT (A) VGS = 5V VGS = 4V 50 VGS = 3V 25 VGS = 2.5V 1.5 3.0 4.5 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 100 6.0 FIGURE 5. TYPICAL SATURATION CHARACTERISTICS -55oC +25oC +175oC 75 50 25 PULSE TEST PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX 0 0.0 0 0 101 t, PULSE WIDTH (s) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE 75 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 1. SAFE OPERATING AREA CURVE 25 100 1.5 3.0 4.5 VGS, GATE-TO-SOURCE VOLTAGE (V) FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS 3 6.0 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM (Continued) VGS = VDS, ID = 250A ID = 250A 2.0 1.2 VGS(TH), NORMALIZED GATE THRESHOLD VOLTAGE 1.1 1.0 0.9 0.8 -80 -40 1.5 1.0 0.5 0.0 -80 200 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE PULSE DURATION = 250s, VDD = 15V rDS(ON), ON-STATE RESISTANCE (m) rDS(ON), NORMALIZED ON RESISTANCE PULSE DURATION = 250s, VGS = 5V, ID = 50A 2.5 2.0 1.5 1.0 0.5 -80 -40 0 40 80 120 160 80 ID = 12.5A ID = 25A 20 0 2.0 2.5 3.0 4.0 3.5 5.00 VDS , DRAIN-SOURCE VOLTAGE (V) 60 tR 400 tD(OFF) 300 tF 200 tD(ON) VDD = BVDSS VDD = BVDSS 45 3.75 30 RL =1.2 IG(REF) = 1.2mA VGS = 5V 2.50 15 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 1.25 0 0 10 20 30 5.0 FIGURE 10. rDS(ON) FOR VARYING CONDITIONS OF GATE VOLTAGE AND DRAIN CURRENT VDD = 30V, ID = 50A, RL= 0.6 0 4.5 VGS, GATE-TO-SOURCE VOLTAGE (V) 500 SWITCHING TIME (ns) ID = 100A 40 200 FIGURE 9. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE 100 ID = 50A 60 TJ, JUNCTION TEMPERATURE (oC) 600 200 40 0 I G ( REF ) 50 20 ------------------I G ( ACT ) RGS, GATE-TO-SOURCE RESISTANCE () FIGURE 11. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE VGS , GATE-SOURCE VOLTAGE (V) BVDSS, NORMALIZED DRAIN-TO-SOURCE BREAKDOWN VOLTAGE Typical Performance Curves t, TIME (s) I G ( REF ) 80 ------------------I G ( ACT ) FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT. REFER TO HARRIS APPLICATION NOTES AN7254 AND AN7260 4 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM Typical Performance Curves (Continued) VGS = 0V, FREQUENCY (f) = 1MHz 300 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) IAS, AVALANCHE CURRENT (A) 2500 1500 1000 COSS 500 CRSS 0 5 10 15 20 VDS, DRAIN-TO-SOURCE VOLTAGE (V) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = +25oC 10 STARTING TJ = +150oC 1 0.01 0 25 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 100 FIGURE 14. UNCLAMPED INDUCTIVE SWITCHING. REFER TO HARRIS APPLICATION NOTES AN9321 AND AN9322 FIGURE 13. TYPICAL CAPACITANCE vs VOLTAGE POWER DISSIPATION MULTIPLIER C, CAPACITANCE (pF) CISS 2000 75 100 TC , CASE TEMPERATURE 125 150 175 (oC) FIGURE 15. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING CURVE 5 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM Test Circuits and Waveforms VDS BVDSS tP VDS L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS DUT RG - VGS 0V VDD + VDD tP IL 0.01 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS VDD tON tOFF tD(ON) RDS tD(OFF) tF tR VDS VDS 90% 90% VGS 10% DUT 10% 0V 90% RGS VGS 50% 10% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT 6 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM Temperature Compensated PSPICE Model for the RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM SUBCKT 50N06LE 2 1 3 ; rev 8/11/95 CA 12 8 7.0e-9 CB 15 14 7.0e-9 CIN 6 8 1.85e-9 LDRAIN DPLCAP 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD RLDRAIN RSLC1 51 + 5 51 ESLC RSLC2 EBREAK 11 7 17 18 65.3 LDRAIN 2 5 1e-9 LGATE 1 9 7.29e-9 LSOURCE 3 7 6.16e-9 LGATE GATE 1 RLGATE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.95e-3 RGATE 9 20 1.18 RLDRAIN 2 5 10 RLGATE 1 9 72.9 RLSOURCE 3 7 61.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 8.0e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 6 8 + 20 RDRAIN 16 EBREAK 21 MWEAK EVTHRES + 19 8 EVTEMP RGATE + 18 9 11 50 ESG MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A S1B S2A S2B DBREAK - EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 DRAIN 2 5 6 + - DBODY 17 18 MMED 22 MSTRO DESD1 91 DESD2 LSOURCE RIN CIN RSOURCE 8 SOURCE 3 7 RLSOURCE S1A 12 13 8 S2A 14 13 RBREAK 15 17 18 S2B S1B RVTEMP 13 CB CA + 6 8 EGS + EDS 5 8 - IT 14 - 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD 19 - VBAT + 8 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*185),4.2))} .MODEL DBODYMOD D (IS = 1.98e-12 RS = 4.90e-3 TRS1 = 2.75e-3 TRS2 = -4.08e-6 CJO = 1.90e-9 TT = 7.15e-8 M = 0.49) .MODEL DBREAKMOD D (RS = 1.26e-1 TRS1 = 2.75e-3 TRS2 = -1.17e-5) .MODEL DESD1MOD D (BV = 12.75 TBV1 = 0 TBV2 = 0 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 12.75 TBV1 = 0 TBV2 = 0 RS = 54 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 1.36e-9 IS = 1e-30 N = 10 M = 0.56) .MODEL MMEDMOD NMOS (VTO = 1.56 KP = 3.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.18) .MODEL MSTROMOD NMOS (VTO = 1.88 KP = 50.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.34 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 11.8 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.02e-4 TC2 = 9.18e-7) .MODEL RDRAINMOD RES (TC1 = 1.41e-2 TC2 = 7.94e-5) .MODEL RSLCMOD RES (TC1 = 3.0e-3 TC2 = 2.0e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -9.50e-4 TC2 = -9.53e-6) .MODEL RVTEMPMOD RES (TC1 = -1.54e-3 TC2 = 1.21e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.95 VOFF = -1.95) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.95 VOFF = -4.95) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.43 VOFF = 1.57) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.57 VOFF = -1.43) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records; authors William J. Hepp and C. Frank Wheatley, 1991. 7 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM TO-247 3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE A E TERM. 4 OS INCHES OP SYMBOL Q OR D L1 MAX NOTES A 0.180 0.190 4.58 4.82 - b 0.046 0.051 1.17 1.29 2, 3 b1 0.060 0.070 1.53 1.77 1, 2 b2 0.095 0.105 2.42 2.66 1, 2 0.020 0.026 0.51 0.66 1, 2, 3 0.800 0.820 20.32 20.82 - b1 E 0.605 0.625 15.37 15.87 b2 e c e MILLIMETERS MIN c e1 b 2 MAX D L 1 MIN 3 3 J1 0.219 TYP 0.438 BSC - 5.56 TYP 4 11.12 BSC 4 J1 0.090 0.105 2.29 2.66 1 L 0.620 0.640 15.75 16.25 - BACK VIEW L1 0.145 0.155 3.69 3.93 1 2 e1 5 OP 0.138 0.144 3.51 3.65 - Q 0.210 0.220 5.34 5.58 - OR 0.195 0.205 4.96 5.20 - OS 0.260 0.270 6.61 6.85 - NOTES: 1. Lead dimension and finish uncontrolled in L1. 2. Lead dimension (without solder). 3. Add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93. 8 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM TO-220AB 3 LEAD JEDEC TO-220AB PLASTIC PACKAGE A INCHES E OP A1 Q H1 TERM. 4 D 45o E1 D1 L1 b1 L b c MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 - b 0.030 0.034 0.77 0.86 3, 4 b1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 D 0.590 0.610 14.99 15.49 - D1 - 0.160 E 0.395 0.410 E1 - 0.030 e 60o 1 2 e e1 3 J1 e1 MILLIMETERS SYMBOL 0.100 TYP 0.200 BSC H1 0.235 0.255 J1 0.100 0.110 L 0.530 0.550 10.04 - 4.06 - 10.41 - 0.76 - 2.54 TYP 5 5.08 BSC 5 5.97 6.47 - 2.54 2.79 6 13.47 13.97 - L1 0.130 0.150 3.31 3.81 2 OP 0.149 0.153 3.79 3.88 - Q 0.102 0.112 2.60 2.84 - NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 1 dated 1-93. 9 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM TO-262AA 3 LEAD JEDEC TO-262AA PLASTIC PACKAGE E INCHES A 15o A1 H1 TERM. 4 D L1 b1 MIN MAX MIN MAX c A 0.170 0.180 4.32 4.57 - 0.048 0.052 1.22 1.32 3, 4 b 0.030 0.034 0.77 0.86 3, 4 b1 0.045 0.055 1.15 1.39 3, 4 c 0.018 0.022 0.46 0.55 3, 4 D 0.405 0.425 10.29 10.79 - E 0.395 0.405 10.04 10.28 e1 L 60o 1 2 e 3 J1 NOTES A1 e b MILLIMETERS SYMBOL 0.100 TYP 0.200 BSC - 2.54 TYP 5 5.08 BSC 5 H1 0.045 0.055 1.15 1.39 - J1 0.095 0.105 L 0.530 0.550 2.42 2.66 6 13.47 13.97 - L1 0.110 0.130 2.80 3.30 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. A of JEDEC TO-262AA outline dated 6-90. 2. Solder finish uncontrolled in this area. 3. Dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder plating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 4 dated 10-95. e1 10 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM TO-263AB SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE E INCHES A A1 H1 TERM. 4 D L2 L1 L 1 3 b b1 e c e1 J1 .450 (11.43) TERM. 4 L3 .350 (8.89) b2 .700 (17.78) 3 MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 4, 5 b 0.030 0.034 0.77 0.86 4, 5 b1 0.045 0.055 1.15 1.39 4, 5 b2 0.310 - 7.88 - 2 c 0.018 0.022 0.46 0.55 4, 5 D 0.405 0.425 10.29 10.79 - E 0.395 0.405 10.04 10.28 - e 0.100 TYP 2.54 TYP 7 e1 0.200 BSC 5.08 BSC 7 H1 0.045 0.055 1.15 1.39 - J1 0.095 0.105 2.42 2.66 - L 0.175 0.195 4.45 4.95 - L1 0.090 0.110 2.29 2.79 4, 6 L2 0.050 0.070 1.27 1.77 3 L3 0.315 - 8.01 - 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-263AB outline dated 2-92. 2. L3 and b2 dimensions established a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.120 inches (3.05mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 7 dated 10-95. 1 .150 (3.81) .080(2.03) MILLIMETERS SYMBOL .080(2.03) .062(1.58) .062(1.58) MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS 11 RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM TO-263AB 24mm TAPE AND REEL 40mm MIN. ACCESS HOLE 4.0mm 1.5mm DIA. HOLE 2.0mm 30.4mm 13mm 330mm 1.75mm C L 24mm 100mm 16mm 24.4mm USER DIRECTION OF FEED COVER TAPE GENERAL INFORMATION 1. USE "9A" SUFFIX ON PART NUMBER. 2. 800 PIECES PER REEL. 3. ORDER IN MULTIPLES OF FULL REELS ONLY. 4. MEETS EIA-481 REVISION "A" SPECIFICATIONS. Revision 7 dated 10-95 All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries. Sales Office Headquarters For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS UNITED STATES Harris Semiconductor P. O. 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