SEMICONDUCTOR
1
July 1996
File Number 4072.1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
Copyright © Harris Corporation 1996
RFG50N06LE, RFP50N06LE,
RF1S50N06LE, RF1S50N06LESM
50A, 60V, ESD Rated, Avalanche Rated, Logic Level
N-Channel Enhancement-Mode Power MOSFETs
Features
• 50A, 60V
•r
DS(ON) = 0.022Ω
• 2kV ESD Protected
•
Temperature Compensating
PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• +175oC Operating Temperature
Description
The RFG50N06LE, RFP50N06LE, RF1S50N06LE, and
RF1S50N06LESM are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization of silicon,
resulting in outstanding performance. They were designed for use in
applications such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated directly from
integrated circuits .
Note: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in tape and reel, i.e.
RF1S50N06LESM9A.
Formerly developmental type TA49164.
Symbol
PACKAGE AVAILABILITY
PART NUMBER PACKAGE BRAND
RFG50N06LE TO-247 FG50N06L
RFP50N06LE TO-220AB FP50N06L
RF1S50N06LE TO-262AA F50N06LE
RF1S50N06LESM TO-263AB F50N06LE
G
D
S
Packages
JEDEC STYLE TO-247
JEDEC TO-220AB
JEDEC TO-262AA
JEDEC TO-263AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
A
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
A
A
M
DRAIN
(FLANGE)
GATE
SOURCE
Absolute Maximum Ratings TC= +25oCRFG50N06LE, RFP50N06LE,
RF1S50N06LE, RF1S50N06LESM UNITS
Drain-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V
Drain-Gate Voltage (RGS = 1MΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V
Gate-Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V
Drain Current
Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
50
Refer to Peak Current Curve A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Power Dissipation
TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate above +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
0.95 W
W/oC
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TSTG, TJ-55 to +175 oC
Soldering Temperature of Leads for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL260 oC
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . .ESD 2 kV
2
Specifications RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
Electrical Specifications TC = +25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain-Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 60 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA1-2V
Zero Gate Voltage Drain Current IDSS VDS = 60V,
VGS = 0V TC = +25oC--1µA
T
C
= +150oC--50µA
Gate-Source Leakage Current IGSS VGS = ±10V - - 10 µA
On Resistance rDS(ON) ID = 50A, VGS = 5V - - 0.022 Ω
Turn-On Time tON VDD = 30V, ID = 50A,
RL = 0.6Ω, VGS = 5V,
RGS = 2.5Ω
- - 230 ns
Turn-On Delay Time tD(ON) -20-ns
Rise Time tR- 170 - ns
Turn-Off Delay Time tD(OFF) -48-ns
Fall Time tF-90-ns
Turn-Off Time tOFF - - 165 ns
Total Gate Charge QG(TOT) VGS = 0V to 10V VDD = 48V,
ID = 50A,
RL = 0.96Ω
- 96 120 nC
Gate Charge at 5V QG(5) VGS = 0V to 5V - 57 70 nC
Threshold Gate Charge QG(TH) VGS = 0V to 1V - 2.2 2.7 nC
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz - 2100 - pF
Output Capacitance COSS - 600 - pF
Reverse Transfer Capacitance CRSS - 230 - pF
Thermal Resistance Junction-to-Case RθJC - - 1.05 oC/W
Thermal Resistance Junction-to-Ambient RθJA TO-247 - - 30 oC/W
TO-220, TO-262, and TO-263 - - 80 oC/W
Source-Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage VSD ISD = 50A - - 1.5 V
Reverse Recovery Time tRR ISD = 50A, dISD/dt = 100A/µs - - 130 ns
3
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
Typical Performance Curves
FIGURE 1. SAFE OPERATING AREA CURVE FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL
IMPEDANCE
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. TYPICAL SATURATION CHARACTERISTICS FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
1 10 100
1
100
10
ID, DRAIN CURRENT (A)
TC = +25oC
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS DC
100µs
10ms
100ms
1ms
500
200
VDSS MAX = 60V
t, RECTANGULAR PULSE DURATION (s)
10-5 10-3 10-2 10-1 100
0.01
10
0.1
1
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE
10-4 101
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
PDM
t1
t2
SINGLE PULSE
ZθJC, NORMALIZED
THERMAL RESPONSE
20
10
025 50 75 100 125 150
30
50
40
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC) 175
60
t, PULSE WIDTH (s)
1000
10
10-5 10-4 10-3 10-2 10-1 100101
TC = +25oC
100
IDM, PEAK CURRENT CAPABILITY (A)
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE +25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
0
25
75
0 1.5 3.0 4.5 6.0
50
100
ID, DRAIN CURRENT (A)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
PULSE DURATION = 250µs, TC = +25oC
VGS = 3V
VGS = 5V
VGS = 10V
VGS = 2.5V
VGS = 4V
0.0 3.0 4.5 6.01.5
0
25
50
75
100
+175oC
VDD = 15V
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE-TO-SOURCE VOLTAGE (V)
-55oC+25oC
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
4
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
FIGURE 7. NORMALIZED DRAIN-SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED rDS(ON) vs JUNCTION
TEMPERATURE FIGURE 10. rDS(ON) FOR VARYING CONDITIONS OF GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 11. SWITCHING TIME AS A FUNCTION OF GATE
RESISTANCE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT. REFER TO HARRIS
APPLICATION NOTES AN7254 AND AN7260
Typical Performance Curves
(Continued)
ID = 250µA
1.2
1.0
0.9
0.8
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
BVDSS, NORMALIZED DRAIN-TO-SOURCE
BREAKDOWN VOLTAGE
200
1.1
-80 -40 0 40 80 120 160
VGS = VDS,ID = 250µA
VGS(TH), NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC) 200
2.0
1.0
0.5
0.0
1.5
PULSE DURATION = 250µs, VGS = 5V, ID = 50A
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
rDS(ON), NORMALIZED ON RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
2.5
200
20
40
60
80
03.0
VGS, GATE-TO-SOURCE VOLTAGE (V)
rDS(ON), ON-STATE RESISTANCE (mΩ)
2.0
PULSE DURATION = 250µs, VDD = 15V
ID = 100A
3.5 4.5 5.0
ID = 50A
ID = 12.5A
ID = 25A
4.02.5
200
20 30 40 500
500
400
300
100
010
SWITCHING TIME (ns)
RGS, GATE-TO-SOURCE RESISTANCE (Ω)
VDD = 30V, ID = 50A, RL= 0.6Ω
600
tR
tD(OFF)
tF
tD(ON)
60
45
30
15
0
20IG REF()
I
G ACT()
------------------- t, TIME (µs) 80IG REF()
I
GACT()
-------------------
5.00
3.75
2.50
1.25
0
VDS, DRAIN-SOURCE VOLTAGE (V)
VGS, GATE-SOURCE VOLTAGE (V)
RL =1.2Ω
IG(REF) = 1.2mA
VGS = 5V
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS VDD = BVDSS
5
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
FIGURE 13. TYPICAL CAPACITANCE vs VOLTAGE FIGURE 14. UNCLAMPED INDUCTIVE SWITCHING. REFER TO
HARRIS APPLICATION NOTES AN9321 AND
AN9322
FIGURE 15. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING CURVE
Typical Performance Curves
(Continued)
VGS = 0V, FREQUENCY (f) = 1MHz
2500
2000
1000
00 5 10 15 20 25
C, CAPACITANCE (pF)
CRSS
1500
CISS
COSS
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
500
10
100
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = +150oC
STARTING TJ = +25oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
1 10 1000.01 0.1
300
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.0 0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
6
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IL
-
+
VDS
VDD
RGDUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
VDD
VDS
VGS
0V
RGS
DUT
RDS
tON
tD(ON)
tR
90%
10%
VDS 90%
10%
tF
tD(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
7
Temperature Compensated PSPICE Model for the RFG50N06LE, RFP50N06LE,
RF1S50N06LE, RF1S50N06LESM
SUBCKT 50N06LE 2 1 3 ; rev 8/11/95
CA 12 8 7.0e-9
CB 15 14 7.0e-9
CIN 6 8 1.85e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 65.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 7.29e-9
LSOURCE 3 7 6.16e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.95e-3
RGATE 9 20 1.18
RLDRAIN 2 5 10
RLGATE 1 9 72.9
RLSOURCE 3 7 61.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 8.0e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*185),4.2))}
.MODEL DBODYMOD D (IS = 1.98e-12 RS = 4.90e-3 TRS1 = 2.75e-3 TRS2 = -4.08e-6 CJO = 1.90e-9 TT = 7.15e-8 M = 0.49)
.MODEL DBREAKMOD D (RS = 1.26e-1 TRS1 = 2.75e-3 TRS2 = -1.17e-5)
.MODEL DESD1MOD D (BV = 12.75 TBV1 = 0 TBV2 = 0 RS = 0 TRS1 = 0 TRS2 = 0)
.MODEL DESD2MOD D (BV = 12.75 TBV1 = 0 TBV2 = 0 RS = 54 TRS1 = 0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 1.36e-9 IS = 1e-30 N = 10 M = 0.56)
.MODEL MMEDMOD NMOS (VTO = 1.56 KP = 3.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.18)
.MODEL MSTROMOD NMOS (VTO = 1.88 KP = 50.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.34 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 11.8 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.02e-4 TC2 = 9.18e-7)
.MODEL RDRAINMOD RES (TC1 = 1.41e-2 TC2 = 7.94e-5)
.MODEL RSLCMOD RES (TC1 = 3.0e-3 TC2 = 2.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -9.50e-4 TC2 = -9.53e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.54e-3 TC2 = 1.21e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.95 VOFF = -1.95)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.95 VOFF = -4.95)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.43 VOFF = 1.57)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.57 VOFF = -1.43)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records; authors William J. Hepp and C. Frank Wheatley, 1991.
+
-
GATE
1
LGATE
RLGATE
RGATE
DESD1
DESD2
91
12S1A
920
+-
EVTEMP
18
22 6
RIN CIN
MSTRO
EVTHRES
13
8
S2A
14
13 15
8
RDRAIN
ESG 16
+
MMED
MWEAK
EBREAK
RSOURCE
21
-
RBREAK
17 18
50
RVTEMP
RLSOURCE
LSOURCE
DBODY
RSLC1
51
+
RSLC2
ESLC
DBREAK
RLDRAIN
SOURCE
3
11
7
DRAIN
2
LDRAIN
DPLCAP
10
RVTHRES
VBAT
22
19
IT
14
+
-
EGS
8
S1B S2B
13
-
+
19
8
-
+17
18
-
5
51
5
6
8
-
+
EDS 5
8
8
6
CB
CA
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
8
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
TO-247
3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE
A
b
b1
c
D
E
L
L1
ØR
12
e1
31
J1
ØS
Q
ØP
BACK VIEW
TERM. 4
3
e
b2
2
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.180 0.190 4.58 4.82 -
b 0.046 0.051 1.17 1.29 2, 3
b10.060 0.070 1.53 1.77 1, 2
b20.095 0.105 2.42 2.66 1, 2
c 0.020 0.026 0.51 0.66 1, 2, 3
D 0.800 0.820 20.32 20.82 -
E 0.605 0.625 15.37 15.87 -
e 0.219 TYP 5.56 TYP 4
e10.438 BSC 11.12 BSC 4
J10.090 0.105 2.29 2.66 5
L 0.620 0.640 15.75 16.25 -
L10.145 0.155 3.69 3.93 1
ØP 0.138 0.144 3.51 3.65 -
Q 0.210 0.220 5.34 5.58 -
ØR 0.195 0.205 4.96 5.20 -
ØS 0.260 0.270 6.61 6.85 -
NOTES:
1. Lead dimension and finish uncontrolled in L1.
2. Lead dimension (without solder).
3. Add typically 0.002 inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.250 inches (6.35mm) from bottom
of dimension D.
5. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of dimension D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
9
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
E
ØP
Q
D
H1
E1
L
L1
60o
b1
b
123
e
e1
A
c
J1
45o
D1
A1
TERM. 4
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
A10.048 0.052 1.22 1.32 -
b 0.030 0.034 0.77 0.86 3, 4
b10.045 0.055 1.15 1.39 2, 3
c 0.014 0.019 0.36 0.48 2, 3 , 4
D 0.590 0.610 14.99 15.49 -
D1- 0.160 - 4.06 -
E 0.395 0.410 10.04 10.41 -
E1- 0.030 - 0.76 -
e 0.100 TYP 2.54 TYP 5
e10.200 BSC 5.08 BSC 5
H10.235 0.255 5.97 6.47 -
J10.100 0.110 2.54 2.79 6
L 0.530 0.550 13.47 13.97 -
L10.130 0.150 3.31 3.81 2
ØP 0.149 0.153 3.79 3.88 -
Q 0.102 0.112 2.60 2.84 -
NOTES:
1. These dimensions are within allowab le dimensions of Re v. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 1 dated 1-93.
10
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
TO-262AA
3 LEAD JEDEC TO-262AA PLASTIC PACKAGE
H1
D
L1
L
1e
e1
b
b1
A1
A
c
J1
E15o
23
TERM. 4
60o
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
A10.048 0.052 1.22 1.32 3, 4
b 0.030 0.034 0.77 0.86 3, 4
b10.045 0.055 1.15 1.39 3, 4
c 0.018 0.022 0.46 0.55 3, 4
D 0.405 0.425 10.29 10.79 -
E 0.395 0.405 10.04 10.28 -
e 0.100 TYP 2.54 TYP 5
e10.200 BSC 5.08 BSC 5
H10.045 0.055 1.15 1.39 -
J10.095 0.105 2.42 2.66 6
L 0.530 0.550 13.47 13.97 -
L10.110 0.130 2.80 3.30 2
NOTES:
1. These dimensions are within allowable dimensions of Rev. A of
JEDEC TO-262AA outline dated 6-90.
2. Solder finish uncontrolled in this area.
3. Dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder plating.
5. P osition of lead to be measured 0.250 inches (6.35mm) from bottom
of dimension D.
6. P osition of lead to be measured 0.100 inches (2.54mm) from bottom
of dimension D.
7. Controlling dimension: Inch.
8. Revision 4 dated 10-95.
11
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
TO-263AB
SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
EA1
A
H1
D
L
be
e1
L2
b1
L1
c
J
TERM. 4
13
1
13
L
3
b
2
TERM. 4 .450
.350
.150
(3.81)
.080(2.03).080(2.03)
.700
(11.43)
(8.89)
(17.78)
.062(1.58) .062(1.58)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
A10.048 0.052 1.22 1.32 4, 5
b 0.030 0.034 0.77 0.86 4, 5
b10.045 0.055 1.15 1.39 4, 5
b20.310 - 7.88 - 2
c 0.018 0.022 0.46 0.55 4, 5
D 0.405 0.425 10.29 10.79 -
E 0.395 0.405 10.04 10.28 -
e 0.100 TYP 2.54 TYP 7
e10.200 BSC 5.08 BSC 7
H10.045 0.055 1.15 1.39 -
J10.095 0.105 2.42 2.66 -
L 0.175 0.195 4.45 4.95 -
L10.090 0.110 2.29 2.79 4, 6
L20.050 0.070 1.27 1.77 3
L30.315 - 8.01 - 2
NOTES:
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-263AB outline dated 2-92.
2. L3 and b2 dimensions established a minimum mounting surface
for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. P osition of lead to be measured 0.120 inches (3.05mm) from bottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 7 dated 10-95.
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reser ves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which ma y result from its use . No license is g ranted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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(407) 729-4984
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ASIA
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TEL: (65) 748-4200
FAX: (65) 748-0400
SEMICONDUCTOR
12
RFG50N06LE, RFP50N06LE, RF1S50N06LE, RF1S50N06LESM
TO-263AB
24mm TAPE AND REEL
330mm 100mm
13mm
30.4mm
24.4mm
2.0mm
4.0mm 1.75mm
1.5mm
DIA. HOLE C
L
COVER TAPE
USER DIRECTION OF FEED
GENERAL INFORMATION
1. USE "9A" SUFFIX ON PART NUMBER.
2. 800 PIECES PER REEL.
3. ORDER IN MULTIPLES OF FULL REELS ONLY.
4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
16mm
24mm
ACCESS HOLE
40mm MIN.
Revision 7 dated 10-95
