AT49F002(N)(T)(NT) - N/A

Features

•Single-volt age Operation

–5V Read

– 5V Reprogramming

•Fast Read Access Time - 55 ns

•Internal Program Control and Timer

•Sector A rchi tecture

–One 16K Byte Boot Block with Programming Lockout

–Two 8K Byte Parameter Blocks

–Two Main Memory Blocks (96K, 128K Bytes)

•Fast Erase Cycle Time - 10 seconds

•Byte-by-byte Programming - 10 µs/Byte Typical

•Hardware Data Protection

•DATA Polling for End of Program Detection

•Low Power Dissipation

–50 mA A ctive Current

–100 µA CMOS Standby Current

•Typical 10,000 Write Cycles

Description

The AT49F002(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its 2

megabits of memory is organized as 262,144 words by 8 bits. Man ufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55

ns with power dissipation of just 275 mW over the commercial temperature range.

Rev. 1017D–10/99

2-megabit

(256K x 8)

5-volt Only

Flash Memory

AT49F002

AT49F002N

AT49F002T

AT49F002NT

Pin Configurations

Pin Name Function

A0 - A17 Addresses

CE Chip Enable

OE Output Enable

WE Write Enab l e

RESET RESET

I/O0 - I/O7 Data Inputs/Outputs

DC Don’t Connect

DIP Top View

* RESET

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A17

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PLCC Top View

I/O0

A14

A13

A11

A10

I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

A16

RESET *

VCC

A17

(continued)

VSOP Top View (8 x 14 mm) or

TSOP Top View (8 x 20 mm)

Type 1

A11

A13

A14

A17

VCC

* RESET

A16

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

*Note: This pin is a DC on the AT49F002(N)(T).

AT49F002(N)(T)

When th e device i s dese lecte d, the CMO S standby curren t

is less than 100 µA. For the AT 49F002N(T) pin 1 for the

DIP and PLCC packages and pin 9 for the TSOP package

are don’t connect pins.

To allow for simple in-system reprogrammability, the

AT49F002(N)(T) does not require high input voltages for

programming. Five-volt-only commands determine the read

and programmi ng operation of the device. Readin g data

out of the device is similar to reading from an EPROM; it

has stan dard CE, OE, an d WE inputs to avoid bus co nten-

tion. Reprogramming the AT49F002(N)(T) is performed by

erasing a block of data and then programming on a byte by

byte basi s . The by te progr am min g ti me i s a fast 50 µ s. T h e

end of a program cycle can be optionally detected by the

DATA polling feature. Once the end of a byte program

cycle has been detected, a new access for a read or pro-

gram ca n begin. Th e typica l number of program and eras e

cycles is in excess of 10,000 cycles.

The device is erased by executing the erase command

sequence; the device internally controls the erase opera-

tions. Ther e are two 8K byte par ameter bl ock sect ions and

two main memory blocks.

The device has the capability to protect the data in the boot

block; this feature is enabled by a command sequence.

The 16K-byte boot block section includes a reprogramming

lock ou t fea t ure to pr ov ide data in tegr it y. Th e bo ot s ec tor is

design ed to contain us er secure co de, and when the fea-

ture is enabled, the boot sector is protected from being

reprogrammed.

In the AT49F002(N)(T), once the boot block programming

lockout feature is enabled, the contents of the boot block

are permanent and cannot be changed. In the

AT49F002( T), once the boot block programm ing lockout

feature is enabled, the contents of the boot block cannot be

changed with input voltage levels of 5.5 volts or less.

Block Diag ram

CONTROL

LOGIC

Y DECODER

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

RESET

ADDRESS

INPUTS

VCC

GND

AT49F002(N)

DATA INPUTS/OUTPUTS

I/O7 - I/O0

X DECODER

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(96K BYTES)

MAIN MEMORY

BLOCK 2

(128K BYTES)

PROGRAM

DATA LATCHES

Y-GATING

INPUT/OUTPUT

BUFFERS

3FFFF

20000

1FFFF

08000

07FFF

06000

05FFF

04000

03FFF

00000

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

AT49F002(N)T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(96K BYTES)

MAIN MEMORY

BLOCK 2

(128K BYTES)

PROGRAM

DATA LATCHES

Y-GATING

INPUT/OUTPUT

BUFFERS

3FFFF

3C000

3BFFF

3A000

39FFF

38000

37FFF

20000

1FFFF

00000

AT49F002(N)(T)

Device Operation

READ: The AT49F002(N)(T) is accessed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

COMMAND SEQUEN CES: When the de vice is first p ow-

ered on it will be reset to the read or standby mode

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table.

The command sequences are written by applying a low

pulse on th e WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling

edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard

microprocess or write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

RESET: A RESET input pin is provide d to ease some sy s-

tem appl icati ons. When RE SET is at a logic high level, the

device is in i ts sta nda rd operating mod e. A low l ev el on th e

RESET input halts the prese nt device op eration and puts

the outputs of the device in a high impedance state. If the

RESET pin makes a high to low transition during a program

or erase operation, the operation may not be successfully

comple ted and the op eratio n will have to be repeate d after

a high level is app lied to the RESET pin. W hen a high level

is reasse rted on the RESET pin, the device r eturns to the

read or standby mode, depending upon the state of the

control input s. By apply ing a 12V ± 0.5V in put signa l t o the

RESET pin, the boot block array can be reprogrammed

even if the boot block lockou t feature has been enabled

(see Boot Bl ock Pr ogrammi ng Loc kout Ov erride s ection ).

The RESET feature is not available for the AT49F002N(T).

ERASURE: Befor e a byte can b e reprogr amme d, the mai n

memory block or parameter block which contains the byte

must be erased . The erased state of th e memory bits is a

logical “1”. The entire device can be erased at one time by

using a 6-byte software code. The software chip erase

code consists of 6-byte load commands to specific address

locations with a specific data pattern (please refer to the

Chip Erase Cycle Waveforms).

After th e so ftwar e c hi p e rase h as b een i niti ate d, the d evi c e

will internal ly time the erase opera tion so that no external

clocks are required. The maximum time needed to erase

the whole chip is tEC. If the boot bl ock lockout feature has

been enabled, the data in the boot sector will not be

erased.

CHIP E RAS E: If the boot block lockout has been enabled,

the Chip Erase function will erase Parameter Block 1,

Parame ter Bloc k 2, M ain Me mory B lock 1, a nd Mai n Mem-

ory Block 2 but not the boot block. If the Boot Block Lockout

has not been enabled, the Chip Erase function will erase

the entire chip. After the full chip erase the device will

return ba ck to re ad mo de. A ny c omm and dur ing chip er ase

will be ignored.

SECTOR ERASE: As an alternative to a full chip erase, the

device is organized into sectors that can be individually

erased. There are two 8K-byte parameter block s ections

and two main memory blocks. The 8K-byte parameter

block sections can be independently erased and repro-

grammed. The two main memory sections are designed to

be used as alternative memory sectors. That is, whenever

one of the blocks h as bee n eras ed and r eprog ra mme d, th e

other bl ock should be erased and rep rogrammed be fore

the fir st bloc k i s ag ain e ra sed. T he Se ct or E ra se c om man d

is a six bus cycle operation. The sector address is latched

on the falling WE edge of the sixth cycle while the 30H data

input command is latched at the rising edge of WE. The

sector erase starts after the rising edge of WE of the sixth

cycle. The erase operation is internally controlled ; it will

automatically time to completion.

BYTE PROGRAMMING: Once the memory array is

erased, the device is programmed (to a logical “0”) on a

byte- by-byte basis . Please not e that a data “0” cannot be

progra mmed ba ck to a “1”; only erase operations can con-

vert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle

operation (please refer to the Command Definitions table).

The devi ce wil l au toma tic al ly gen er ate th e re quir ed in ter na l

program pulses.

The program cycle has add resses latched on the falling

edge of WE or CE, whichever occurs last, and the data

latched on the rising edge of WE or CE, whichever occurs

first. Programming is completed after the specified tBP cycle

time. The D ATA polling feature may also be used to indicate

the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device

has one designated block that has a programming lockout

feature. This feature prev ents programm ing of data in th e

designated block once the feature has been enabled. The

size of the block is 16K bytes. This block, referred to as the

boot block, can contain secure code that is used to bring up

the sys tem. En ablin g the l ockou t feature w ill al low the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boo t blo ck ’s u sag e as a wr i te protected r eg io n is

optional to the user. The address range of the boot block is

00000 to 03FFF for the AT49F002(N) while the address

AT49F002(N)(T)

range of the boot block is 3C000 to 3FFFF for the

AT49F002(N)T.

Once the fe ature is en abled, the data in th e boot blo ck can

no longer be er ased or prog rammed wi th inpu t voltage lev-

els of 5.5V or less . Data in the ma in memo ry blo ck ca n still

be changed through the regular programming method. To

activ ate the lockout featu re, a series of si x program co m-

mands to specific addresses with specific data must be

performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine if programming of the boot

block section is locked out. When the device is in the soft-

ware product i dentificati on mode (see Sof tware Produ ct

Identification Entry and Exit sections) a read from address

loca tion 0000 2H will show i f progr ammin g the boot bl ock is

locked out for the AT49F002(N), and a read from address

location 3C002H will show if programming the boot block is

locked out for AT49F002(N)T. If the data on I/O0 is low, the

boot bloc k can be pro grammed; i f the data on I/O0 i s high,

the program lo ckout feature has be en activated and the

block c annot be progra mmed. The softw are produ ct identi-

fication exit code should be used to return to standard

operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The use r can overri de the boot blo ck progra mming lo ckout

by taking the RESET pin to 12 volts. By doing this, pro-

tected boot block data can be altered through a chip erase,

sector erase or word programming. When the RESET pin is

brought back to TTL levels the boot block programming

lockou t featur e is agai n acti ve. Thi s feat ure is n ot ava ilabl e

on the AT49F002N(T).

PRODUCT IDENTIFICATION: The product identific ation

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

For d etails, see Ope rating Mo des (f or hardw are ope ratio n)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING: The AT49F002(N)(T) features D ATA poll-

ing to indicate the end of a program c ycle. During a pro-

gram cycle an attempted read of the last byte loaded will

result in the complement of the loaded data on I/O7. Once

the program cycle has been completed, true data is valid

on all o utputs and the next cy cle may begi n. DATA polling

may begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA polling the

AT49F002(N)(T) provides another method for determining

the end of a program or erase cycle. During a program or

erase ope ratio n, s ucces siv e atte mpt s to read data from the

device will result in I/O6 toggling between one and zer o.

Once the program cycle has completed, I/O6 will stop tog-

gling and valid data will be read. Ex amining the to ggle bit

may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the

AT49F002(N)(T) in the following ways: (a) VCC se nse: if

VCC is below 3.8V (typical), the program function is inhib-

ited. (b) Program inhibit : holding any one of OE low, CE

high or WE high inhibits program cycles . (c) Noise filter:

pulses of less than 15 ns (typical) on the WE or CE inputs

will not initiate a program cycle.

AT49F002(N)(T)

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)

2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F002(N) and 3C000H to 3FFFFH for the

AT49F002(N)T

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses:

For the AT49F002(N):

SA = 00000 to 03FFF for BOOT BLOCK

Nothing will happen and the device goes back to the read mode in 100 ns

SA = 04000 to 05FFF for PARAMETER BLOCK 1

SA = 06000 to 07FFF for PARAMETER BLOCK 2

SA = 08000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 1

This command will erase - PB1, PB2 and MMB1

SA = 20000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 2

For the AT49F002(N)T:

SA = 3C000 to 3FFFF for BOOT BLOCK

Nothing will happen and the device goes back to the read mode in 100 ns

SA = 3A000 to 3BFFF for PARAMETER BLOCK 1

SA = 38000 to 39FFF for PARAMETER BLOCK 2

SA = 20000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1

This command will erase - PB1, PB2 and MMB1

SA = 00000 to IFFFF for MAIN MEMORY ARRAY BLOCK 2

Command Definition (in He x)(1)

Command

Sequence Bus

Cycles

1st Bus

Cycle 2nd Bus

Cycle 3rd Bus

Cycle 4th Bu s

Cycle 5th Bus

Cycle 6th Bu s

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr DOUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA(4) 30

Byte Progr am 4 5555 AA 2AAA 55 5555 A0 Add r DIN

Boot Block Lockout(2) 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID Entr y 3 5555 AA 2AAA 55 5555 90

Product ID Exit(3) 3 5555 AA 2AAA 55 5555 F0

Product ID Exit(3) 1 XXXX F0

Absolute Maxim u m Ratings*

Temperature Under Bias................................ -55°C to +125°C*NOTICE: Stre ss es be yond those lis ted under “Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions beyond those indicated in the operational sec-

tions of this specification is not implied. Exposure to

absolute maximu m rating conditions for extended

periods may affe ct device rel iab ili ty.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to VCC + 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F002(N)(T)
6
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 07H - AT49F002(N), 08H - AT49F002(N)T
5. See details under Software Product Identification Entry/Exit.
6. This pin  is not availa ble on the AT49F00 2N (T).
Note: 1. In the era s e mode, ICC is 90 mA.
DC and AC Operating Rang e
AT49F002(N)(T)-55 AT49F002(N)(T)-70 AT49F002(N)(T)-90 AT49F002(N)(T)-12
Operating 
Temperature (Case) Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
Operating Modes
Mode CE OE WE RESET(6) Ai I/O 
Read VIL VIL VIH VIH Ai DOUT
Program/Erase(2) VIL VIH VIL VIH Ai DIN
Standby/Write Inhibit VIH  X(1) XV
IH X High Z
Program Inhibit XXV
IH VIH
XV
IL XV
IH
Output Disable X VIH XV
IH High Z
Reset XXX V
IL X High Z
Product Identification
Hardware VIL VIL VIH A1 - A17 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4)
A1 - A17 = VIL, A9 = VH,(3) A0 = VIH Device Code(4)
Software(5) A0 = VIL, A1 - A17=VIL Manufacturer Code(4)
A0 = VIH, A1 - A17=VIL Device Code(4)
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V  to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC Com. 100 µA
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3mA
ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

AT49F002(N)(T)
7
AC Read Waveforms (1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change  
without impact on tACC.
3. tDF is specifie d from OE  or CE whicheve r occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveform and 
Measurement Level
tR, tF < 5 ns
Output Load Test
Note: 1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49F002(N)(T)
Units
-55-70-90-12
Min Max Min Max Min Max Min Max
tACC Address to Output Delay 55 70 90 120 ns
tCE(1) CE to Output Delay 55 70 90 120 ns
tOE(2) OE to Output Delay 0 30 0 35 0 40 0 50 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 25 0 30 ns
tOH
Output Hold from OE, CE 
or Address, whichever
occurred first 0000ns
ADDRESS
OUTPUT
HIGH Z
OUTPUT
OE
CE
t
ACC
t
OE
t
DF
t
OH
t
CE
VALID
ADDRESS   VALID
5.0V
1.8K
100 pF
30 pF 1.3K
5.0V
1.8K
OUTPUT
PIN
1.3K
OUTPUT
PIN
50 ns 70/90/120 n s
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN = 0V
COUT 812pFV
OUT = 0V

AT49F002(N)(T)

AC Byte Load Waveforms

WE Controlled

CE Controlled

AC Byte Load Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Set-up Time 0 ns

tAH Address H old Time 50 ns

tCS Chip Select Set-up Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE)90ns

tDS Data Set-up Time 50 ns

tDH, tOEH Data, OE Hold Time 0 ns

tWPH Write Pulse Width High 90 ns

ADDRESS

DATA IN

OE t

OES

OEH

WE t

WPH

tDH

tDS

tAS tAH

tWP

ADDRESS

DATA IN

OE tOES tOEH

CE tCS

tCH

tWPH

AT49F002(N)(T)

Program Cycle Waveforms

Sector or Chip Erase Cycle Waveforms

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.

(See note 4 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

tBP Byte Progr am mi ng Time 10 50 µs

tAS Address Set-u p Time 0 ns

tAH Address H old Time 50 ns

tDS Data Set-up Time 50 ns

tDH Data Hold Time 0 ns

tWP Write Pulse Widt h 90 ns

tWPH Write Pulse Width High 90 ns

tEC Erase Cyc le Tim e 10 seconds

AT49F002(N)(T)

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec i n AC Read C haracteristics.

Data Polling Wa veforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec i n AC Read C haracteristics.

Tog gle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0 ns

Tog gle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 ns

HIGH Z

An An An An An

I/O7

A0-A17

OEH

I/O6

tOEH

HIGH Z

tDH tOE

tWR

tOEHP

AT49F002(N)(T)

Software Product Identification Entry(1)

Software Product Identification Exit(1)

Notes for software product identification

1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. A1 - A17 = VIL.

Manufacture Code is read for A0 = VIL;

Device Code is read for A0 = VIH.

3. The device does not remain in identification mode if

power ed down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH

Device Code: 07H - AT49F002(N)

08H - AT49F002(N)T

Boot Block Lockout Feature Enable

Algorithm(1)

Notes for boot block lockout feature enable:

1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Boot block lock out feature enabled.

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 90

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

MODE(2)(3)(5)

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA F0

ADDRESS 5555

EXIT PRODUCT

IDENTIFICATION

MODE(4)

LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE(4)

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 80

ADDRESS 5555

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 40

ADDRESS 5555

PAUSE 1 second(2)

AT49F002(N)(T)

AT 49F002 Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 50 0.1 AT49F002-55JC

AT49F002-55PC

AT49F002-55TC

AT49F002-55VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002-55JI

AT49F002-55PI

AT49F002-55TI

AT49F002-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

70 50 0.1 AT49F002-70JC

AT49F002-70PC

AT49F002-70TC

AT49F002-70VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002-70JI

AT49F002-70PI

AT49F002-70TI

AT49F002-70VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

90 50 0.1 AT49F002-90JC

AT49F002-90PC

AT49F002-90TC

AT49F002-90VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002-90JI

AT49F002-90PI

AT49F002-90TI

AT49F002-90VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

120 50 0.1 AT49F002-12JC

AT49F002-12PC

AT49F002-12TC

AT49F002-12VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002-12JI

AT49F002-12PI

AT49F002-12TI

AT49F002-12VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32P6 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)

AT49F002(N)(T)

AT49F002N Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 50 0.1 AT49F002N-55JC

AT49F002N-55PC

AT49F002N-55TC

AT49F002N-55VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002N-55JI

AT49F002N-55PI

AT49F002N-55TI

AT49F002N-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

70 50 0.1 AT49F002N-70JC

AT49F002N-70PC

AT49F002N-70TC

AT49F002N-70VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002N-70JI

AT49F002N-70PI

AT49F002N-70TI

AT49F002N-70VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

90 50 0.1 AT49F002N-90JC

AT49F002N-90PC

AT49F002N-90TC

AT49F002N-90VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002N-90JI

AT49F002N-90PI

AT49F002N-90TI

AT49F002N-90VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

120 50 0.1 AT49F002N-12JC

AT49F002N-12PC

AT49F002N-12TC

AT49F002N-12VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002N-12JI

AT49F002N-12PI

AT49F002N-12TI

AT49F002N-12VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32P6 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)

AT49F002(N)(T)

AT 49F002T Ordering Info rmation

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 50 0.1 AT49F002T-55JC

AT49F002T-55PC

AT49F002T-55TC

AT49F002T-55VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002T-55JI

AT49F002T-55PI

AT49F002T-55TI

AT49F002T-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

70 50 0.1 AT49F002T-70JC

AT49F002T-70PC

AT49F002T-70TC

AT49F002T-70VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002T-70JI

AT49F002T-70PI

AT49F002T-70TI

AT49F002T-70VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

90 50 0.1 AT49F002T-90JC

AT49F002T-90PC

AT49F002T-90TC

AT49F002T-90VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002T-90JI

AT49F002T-90PI

AT49F002T-90TI

AT49F002T-90VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

120 50 0.1 AT49F002T-12JC

AT49F002T-12PC

AT49F002T-12TC

AT49F002T-12VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002T-12JI

AT49F002T-12PI

AT49F002T-12TI

AT49F002T-12VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32P6 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)

AT49F002(N)(T)

AT49F002NT Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 50 0.1 AT49F002NT-55JC

AT49F002NT-55PC

AT49F002NT-55TC

AT49F002NT-55VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002NT-55JI

AT49F002NT-55PI

AT49F002NT-55TI

AT49F002NT-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

70 50 0.1 AT49F002NT-70JC

AT49F002NT-70PC

AT49F002NT-70TC

AT49F002NT-70VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002NT-70JI

AT49F002NT-70PI

AT49F002NT-70TI

AT49F002NT-70VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

90 50 0.1 AT49F002NT-90JC

AT49F002NT-90PC

AT49F002NT-90TC

AT49F002NT-90VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002NT-90JI

AT49F002NT-90PI

AT49F002NT-90TI

AT49F002NT-90VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

120 50 0.1 AT49F002NT-12JC

AT49F002NT-12PC

AT49F002NT-12TC

AT49F002NT-12VC

32J

32P6

32T

32V

Commercial

(0° to 70°C)

50 0.3 AT49F002NT-12JI

AT49F002NT-12PI

AT49F002NT-12TI

AT49F002NT-12VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32P6 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)

AT49F002(N)(T)

Packaging Information

.045(1.14) X 45˚ PIN NO. 1

IDENTIFY .025(.635) X 30˚ - 45˚

.012(.305)

.008(.203)

.021(.533)

.013(.330)

.530(13.5)

.490(12.4)

.030(.762)

.015(.381)

.095(2.41)

.060(1.52)

.140(3.56)

.120(3.05)

.032(.813)

.026(.660)

.050(1.27) TYP

.553(14.0)

.547(13.9)

.595(15.1)

.585(14.9)

.300(7.62) REF

.430(10.9)

.390(9.90)

AT CONTACT

POINTS

.022(.559) X 45˚ MAX (3X)

.453(11.5)

.447(11.4)

.495(12.6)

.485(12.3)

1.67(42.4)

1.64(41.7) PIN

.566(14.4)

.530(13.5)

.090(2.29)

MAX

.005(.127)

MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

.630(16.0)

.590(15.0) 0

15 REF

.690(17.5)

.610(15.5)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATING

PLANE

.220(5.59)

MAX

1.500(38.10) REF

*Controlling dimension: millimeters

INDEX

MARK

18.5(.728)

18.3(.720) 20.2(.795)

19.8(.780)

0.25(.010)

0.15(.006)

0.50(.020)

BSC 7.50(.295)

REF

8.20(.323)

7.80(.307) 1.20(.047) MAX

0.15(.006)

0.05(.002)

5REF

0.70(.028)

0.50(.020)

0.20(.008)

0.10(.004)

INDEX

MARK

12.5(.492)

12.3(.484) 14.2(.559)

13.8(.543)

0.25(.010)

0.15(.006)

0.50(.020)

BSC 7.50(.295)

REF

8.10(.319)

7.90(.311) 1.20(.047) MAX

0.15(.006)

0.05(.002)

5REF

0.70(.028)

0.50(.020)

0.20(.008)

0.10(.004)

32J, 32-lead, Plastic J-lea ded Chi p Carr i er (PLC C)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-016 AE

32P6, 32-pi n, 0.60 0" Wi de,

Plastic Dual Inline P ackage (PDIP)

Dimensions in Inches and (Millimeters)

32T, 32-lead, Plastic Thin Small Outline Package

(TSOP)

Dimensions in Millimeters and (Inches)*

32V, 32-lead, Plastic Thin Small Outline Package

(TSOP)

Dimensions in Millimeters and (Inches)

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life suppor t devices or systems.

Mar ks b eari ng ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

Ter ms and product names in this document may be trademarks of others.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441- 0311

FAX (408) 487-2600

Europe

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721 -9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24 -8 Shinka wa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Indu strie lle

13106 Rousset Cedex

France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

1017D–10/99/xM