ORCA

July 2008 Data Sheet DS1027

© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand

(GbE, 10 GbE) applications.

XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be

used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and

protection links between a line card and switch fabric.

The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board

which implements four channels of SERDES with SONET scrambling and cell processing.

Table 1. ORCA ORT42G5 and ORT82G5 Family – Available FPGA Logic

Device PFU Rows

Columns Total PFUs

FPGA Max.

FPGA System

Gates (K)

ORT42G5 36 36 1296 204 10,368 12 111 333-643

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

Table of Contents

Table of Contents......................................................... 2

Embedded Function Features...................................... 4

Programmable Features .............................................. 5

Programmable Logic System Features........................ 6

System-Level Features ................................................ 9

ORT42G5/ORT82G5 Overview ................................. 11

Backplane Transceiver Core Detailed Description .... 13

Multi-channel Alignment Configuration ...................... 30

Reference Clocks and Internal Clock Distribution...... 37

for the ORT82G5 ....................................45

Strategies for the ORT82G5 ................... 47

Boundary, Excluding SERDES ............... 55

(ORT82G5 Only)..................................... 55

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

Embedded Function Features

• High-speed SERDES with programmable serial data rates over the range 0.6 to 3.7 Gbps. Operation has been

• Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control

• IEEE 802.3ae compliant XAUI transceiver. Includes embedded IEEE 802.3ae-based XAUI link state machine.

• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external

• SERDES characterization pins available to control/monitor the internal interface to one SERDES block

• Built-in boundary scan (IEEE

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

Programmable Features

• High-performance programmable logic:

– 0.16 µm 7-level metal technology.

– Internal performance of >250 MHz.

– Over 400K usable system gates.

– Meets multiple I/O interface standards.

– 1.5V operation (30% less power than 1.8V operation) translates to greater performance.

• New programmable high-speed I/O:

– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.

– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

• New local clock routing structures allow creation of localized clock trees.

• Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved

• New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-

• New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

What is an FPSC?

FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or

mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the

FPGA functionality is changed—all of the Series 4 FPGA capability is retained including: the Embedded Block

RAMs, MicroProcessor Interface (MPI), boundary scan, etc. The columns of programmable logic are replaced at

the right of the device, allowing pins from the replaced columns to be used as I/O pins for the embedded core. The

remainder of the device pins retain their FPGA functionality.

FPSC Gate Counting

a much larger gate count.

32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-

tions including the Embedded Block RAMs and the microprocessor interface.

Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking

between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global

set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the

FPGA as a system.

For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This

allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embed-

ded core configurations may be designed into a single device with user-programmable control over which configu-

rations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.

iting the Lattice

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

FPGA Logic Overview

with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce

logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhance-

ments and are offered in a variety of packages and speed grades.

The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge

of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with

true plug-and-play design implementation.

formed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs

multiplexing, uplink and downlink functions, and other functions on two output signals.

MPI, PLLs, and the Embedded System Bus (ESB).

PLC Logic

may be used independently or with arithmetic functions.

The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidi-

rectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional

INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU

outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-

world system performance.

Programmable I/O

The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements.

I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which

allow the user the flexibility to select new I/O types that support High-Speed Interfaces.

Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

and other functions of two output signals.

state signal can be registered or nonregistered.

The new programmable I/O cell allows designers to select I/Os which meet many new communication standards

permitting the device to hook up directly without any external interface translation. They support traditional FPGA

standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-ori-

ented I/O ring architecture, designs can be implemented using 3.3V, 2.5V, 1.8V, and 1.5V referenced output levels.

The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses

with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One

high connectivity with fast software routing times and high-speed system performance.

locked to specific pins.

System-Level Features

The Series 4 also provides system-level functionality by means of its microprocessor interface, Embedded System

Bus, block-port Embedded Block RAMs, universal programmable Phase-Locked Loops, and the addition of highly

tuned networking specific Phase-locked Loops. These functional blocks allow for easy glueless system interfacing

and the capability to adjust to varying conditions in today’s high-speed networking systems.

Microprocessor Interface

The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-, 16,

and 32-bit interfaces with optional parity to the Motorola

bytes), or 16-beat (16 x 1 bytes).

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

Transmit Path (FPGA to Backplane) Logic

The transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel

interface to the FPGA logic. It also uses the reference clock, REFCLK[P:N]_[A:B] to synthesize an internal high-

speed serial bit clock. The serialized transmitted data are available at the differential CML output pins to drive either

an optical transmitters, coaxial media or a circuit board backplane.

• 10:1 Multiplexer

• CML Output Buffer

Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock dis-

tribution, including the transmit PLL are given in later sections of this data sheet.

Figure 3. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)

Encoder

(with

Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet

or [AC, AD, BC, BD]). The control bits are TCOMMAx[3:0] which define whether the input byte is to be interpreted

Figure 4. Transmit MUX Block Timing - Single Channel

Within the definition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission charac-

ters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. Bit a corresponds to STBDxx[0], bit b to STBDxx[1], bit

c to STBDxx[2], bit d to STBDxx[3], bit e to STBDxx[4], bit i to STBDxx[5], bit f to STBDxx[6], bit g to STBDxx[7], bit

h to STBDxx[8], and bit j to STBDxx[9].

CML output buffer and are transmitted serially with STBDxx[0] transmitted first and STBDxx[9] transmitted last.

CML Output Buffer

The transmitter’s CML output buffer is terminated on-chip in 86 ohms to optimize the data eye as well as to reduce

the number of discrete components required. The differential output swing reaches a maximum of 1.2 VPP in the

normal amplitude mode. A half amplitude mode can be selected via configuration register bit HAMP_xx. Half ampli-

symbol interface which results in the closing of the data eye opening at the receiver.

Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also

degrade the data eye opening at the receiver. In the ORT42G5 and ORT82G5 the degree of transmit preemphasis

can be programmed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass

transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in

to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks

are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit decoded or a

10-bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters,

detects code violations and aligns the bit stream to the proper word boundary.

As shown in Figure 6, the basic blocks in the receive path include:

Receive SERDES Block

• CML input buffer

• Receive PLL

• 1:10 demultiplexer (DEMUX)

8b/10b bypass mode.

nel alignment. Each step is described functionally in the following paragraphs. The details of the logical implemen-

tations are described in subsequent sections.

Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi-

tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL

is unable to lock to the serial data stream, it instead locks to REFCLK[A:B] to stabilize the voltage-controlled oscil-

lator (VCO), and periodically switches back to the serial data stream to again attempt synchronization. This pro-

cess continues until a valid input data stream is detected and lock is achieved. The CDR can maintain lock on data

as long as the input data stream contains an adequate data “eye” (i.e., jitter is within specification) and the maxi-

mum data stream run length is not exceeded.

Logic Common to Block

From other channel

or channels

From Control

FPGA

Align Character Detect

4 bits k-control

32-bit data

78.125 MHz

4 bits k-ctrl Synchronization

Status bits

Fibre Channel State

FPGA

and phase. The time required for re-acquisition to the data’s frequency is minimized by logic that periodically

switches the PLL to lock to the REFCLK[A:B] when it fails to lock on the serial data stream, thus limiting the VCO’s

frequency wander. Second, there is the time spent while the PLL is locking to REFCLK[A:B], which can be from

Word (32-bit) alignment can occur after the Fibre Channel (XAUI_MODE_xx = 0) or XAUI (XAUI_MODE_xx = 1)

comma is in the most significant byte position. It is important that the comma is in the most significant byte position

since the multi-channel aligner looks for comma in the most significant byte only.

In Fibre Channel mode, the default setting (NOWDALGN_xx = 0) causes the word boundary to be set as soon as

the SERDES SWDSYNC_xx output is a 1 and a comma character has been detected. The character that is the

is indicated by the status of WDSYNC_xx output which now transitions from 1 to 0. At this point the machine

attempts to establish the link yet again. Figure 9 shows the state diagram for the Fibre Channel link state machine.

LOS is also indicated by DEMUXWAS_xx status register bit. This bit is set to 0 during loss of synchronization.

zation and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled

sync_complete Indication that alignment code-group alignment has been established at the boundary indicated by the

cg_comma Indication that a valid code-group, with correct running disparity, containing a comma has been received.

cg_good Indication that a valid code-group with the correct running disparity has been received.

cg_bad Indication that an invalid code-group has been received.

no_comma Indication that comma timer has expired. The timer is initialized upon receipt of a comma.

• FMPU_RESYNC4B for quad channel B[A:D]

• FMPU_RESYNC2B1 for twin channel B[A:B]

• FMPU_RESYNC2B2 for twin channel B[C:D]

ORT42G5 Alignment Sequence

2. Initiate a SERDES software reset by setting the SWRST bit to 1 and then to 0. Note that, any changes to the

SERDES configuration bits should be followed by a software reset.

3. Wait for 3 ms. REFCLK should be toggling by this time. During this time, configure the following registers.

Set the following bits in registers 30820, 30920:

• XAUI_MODE_xx-set to 1 for XAUI mode or keep the default value of 0 if the Fibre Channel state machine was

• Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811, 30911.

• Monitor the following status bits in registers 30804, 30904

• XAUISTAT_xx - In XAUI mode, they should be 10.

Monitor the following status bits in registers 30805, 30905

• DEMUXWAS_xx - They should be 1 indicating word alignment is achieved.

• CH24_SYNCxx - They should be 1 indicating channel alignment. This is cleared by resync.

value of the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the

resync bits: write a 0 and then write a 1. It is highly recommended to precede a resync with a word alignment,

especially in situations where a disturbance in the receive SERDES path can cause misalignment of data and

OOS indications without bringing the FC/XAUI state machine to a loss of synch state. A word alignment is

achieved by writing a 0 and then a 1 to the appropriate DOWDALIGNxx bits in registers 30810/30910.

Check out-of-sync and FIFO overflow status in registers 30814 (Bank A).

• SYNC2_A_OOS, SYNC2_A_OVFL - by 2 alignment.

Check out-of-sync status in registers 30914 (Bank B).

• SYNC2_B_OOS, SYNC2_B_OVFL - by 2 alignment.

Check out-of-sync status in registers 30A03.

• SYNC4_OOS, SYNC4_OVFL - by 4 alignment.

• If out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the OOS bit again.

• If Out of Synchronization (OOS) bit is 0 but OVFL bit is 1, then check if the RX_FIFO_MIN value has been pro-

If OOS and OVFL are 1, then rewrite a 1 to the appropriate resync registers. The resync operation requires a rising

edge. Two writes are required to the resync bits: write a 0 and then write a 1.

• XAUI_MODE_xx-set to 1 for XAUI mode or keep the default value of 0 if the Fibre Channel state machine was

• Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811, 30911.

• FMPU_SYNMODE_xx. Set to appropriate values for 2, 4, or 8 alignment based on Table 7.

• Set RCLKSEL[A:B] and TCKSEL[A:B] bits in registers 30A00.

• RCKSEL[A:B] – Choose clock source for 78 MHz RCK78x (Table 18).

• TCKSEL[A:B] – Choose clock source for 78 MHz TCK78x (Table 17). Send data on serial links.

Monitor the following status/alarm bits:

• Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130.

• LKI-PLL_xx lock indicator. A 1 indicates that PLL has achieved lock.

Monitor the following status bits in registers 30804, 30904:

• XAUISTAT_xx - In XAUI mode, they should be 10.

• DEMUXWAS_xx-They should be 1 indicating word alignment is achieved.

• CH248_SYNCxx-They should be 1 indicating channel alignment. This is cleared by resync.

• SYNC2_A2_OOS, SYNC_A2_OVFL or SYNC2_A1_OOS, SYNC2_A1_OVFL-by 2 alignment.

• Check out-of-sync status in registers 30914 (Bank B).

• SYNC4_B_OOS, SYNC4_B_OVFL-by 4 alignment.

• SYNC_B2_OOS, SYNC2_B2_OVFL or SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 alignment.

• Check out-of-sync status in register 30A03

• SYNC8_OOS, SYNC8_OVFL-by 8 alignment.

• If out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the OOS bit again. If Out of

groups of decoded information depending on setting of 8b10bR_xx control register bits.

bits 29 and 19, are also described in Table 9 and Table 10.

03 bit 3 of 10-bit data 0 bit 3 of byte 0 bit 3 of byte 0

02 bit 2 of 10-bit data 0 bit 2 of byte 0 bit 2 of byte 0

01 bit 1 of 10-bit data 0 bit 1 of byte 0 bit 1 of byte 0

00 bit 0 of 10-bit data 0 bit 0 of byte 0 bit 0 of byte 0

Reference Clock Requirements

distributed to all channels in a block. Each channel has a differential buffer to isolate the clock from the other chan-

The input reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jit-

ter components in the DC to 5 MHz range should be minimized. The required electrical characteristics for the refer-

ence clock are given in Table 38.

Note: In sections of this data sheet, the differential clocks are simply referred to as the reference clock as

REFCLK_[A:B].

Synthesized and Recovered Clocks

and its frequency can drift outside of the nominal ±350 ppm range. Under this condition, the receive PLL will lock to

lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per

channel to force the receive PLL to always lock to the reference clock.

The high-speed transmit and receive serial data links can run at 0.6 to 3.7 Gbps, depending on the frequency of the

reference clock and the state of the control bits from the internal transmit control register. The interface to the seri-

alizer/deserializer block runs at 1/10th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts the

Interface Signal Name

Input (I) to or

TSYS_CLK_xx I Transmit low-speed clock to the FPGA – channel xx

MRWDxx[39:0] O Receive data – Channel xx (see Table 8 and Table ).

RWCKxx O Low-speed receive clock—Channel xx.

RCK78[A:B] O Receive low-speed clock to FPGA—SERDES Quad [A:B].

RSYS_CLK_A1 I Low-speed receive FIFO clock for channels AA, AB

RSYS_CLK_A2 I Low-speed receive FIFO clock for channels AC, AD

RSYS_CLK_B1 I Low-speed receive FIFO clock for channels BA, BB

RSYS_CLK_B2 I Low-speed receive FIFO clock for channels BC, BD

CV_SELxx I Enable detection of code violations in the incoming data

Internal Clock Signals at the FPGA/Core Interface for the ORT42G5

will be at a frequency of 156.25 MHz.

RWCK[AC, AD, BC, BD]:

these clocks operate at 78.125 MHz.

RCK78[A:B]:

156.25 MHz, these clocks operate at 78.125 MHz.

Common Logic, Block A

TSYS_CLK[AC, AD, BC, BD]:

nel to control the timing of the Transmit Data Path. To guarantee correct transmit operation theses clocks must be

frequency locked within 0 ppm to TCK78[A:B].

Besides taking in a TSYS_CLK_xx from the FPGA logic for each channel, the transmit path logic sends back a

clock of the same frequency, but arbitrary phase. This clock, TCK78[A:B], is derived from the MUX block of one of

the 2 channels in its SERDES block. The MUX blocks provide the potential source for TCK78[A:B] by a divide-by-4

of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311xx clock domain.

The STBC311xx clocks are internal to the core and are not brought across the core/FPGA interface

Transmit Clock Source Selection

trolled by this bit as shown in Table 14.

Table 14. TCK78[A:B] Source Selection

Recommended Transmit Clock Distribution for the ORT42G5

used for Block B.

0.6 Gbps 60 MHz 15 MHz Half

1.0 Gbps 100 MHz 25 MHz Half

2.0 Gbps 100 MHz 50 MHz Full

2.5 Gbps 125 MHz 62.5 MHz Full

3.7 Gbps 185 MHz 92.5 MHz Full

register bits RCKSEL[A:B] is used to select the clock source for these clocks. The selection of the source for

RCK78[A:B] is controlled by this bit as shown in Table 15.

Table 15. RCK78[A:B] Source Selection

In the receive channel alignment bypass mode the data and recovered clocks for the four channels are indepen-

dent. The data for each channel are synchronized to the recovered clock from that channel.

Figure 21 shows the recommended receive clocking for a single block.

Common Logic, Block A