Standard Power
Data Sheet
Rev. 1.0, 2011-02-07
IFX80471
Step-Down DC/DC Controller
IFX80471SKV
IFX80471SKV50
Data Sheet 2 Rev. 1.0, 2011-02-07
IFX80471
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Detailed Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 PFM/PWM Step-down regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Battery voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Undervoltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Output voltage at adjustable version - feedback divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 SI_Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3.1 Battery sense comparator - voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.4 Undervoltage reset - delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5 100% duty-cycle operation and dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6 SYNC Input and Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7 Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8 Buck converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8.1 Buck inductance (L1) selection in terms of ripple current: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8.2 Determining the current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8.3 PFM and PWM thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8.4 Buck output capacitor (COUT) selection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8.5 Input capacitor (CIN1) selection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.6 Freewheeling diode / catch diode (D1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.7 Buck driver supply capacitor (CBDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.8 Input pi-filter components for reduced EME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.9 Frequency compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.9 Components recommendation - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.10 Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table of Contents
PG-DSO-14
Type Package Marking
IFX80471SKV PG-DSO-14 I80471V
IFX80471SKV50 PG-DSO-14 I80471V50
Data Sheet 3 Rev. 1.0, 2011-02-07
Step-Down DC/DC Controller
IFX80471
1Overview
Features
• Input voltage range from 5V up to 60V
• Output voltage: 5V fixed or adjustable
• Output voltage accuracy: 3%
• Output current up to 2.3A
• 100% maximum duty cycle
• Less than 120µA quiescent current at low loads1)
• 2µA max. shutdown current at device off (IFX80471SKV)
• Fixed 360kHz switching frequency
• Frequency synchronization input for external clocks
• Current Mode control scheme
• Integrated output undervoltage reset circuit2)
• On chip low battery detector (on chip comparator)
• Temperature range -40°C to 125 °C
• Green Product (RoHS compliant)
1) dependent on external component
2) for the adjustable version IFX80471SKV the reset functionality is available for output voltages > 7V
For automotive and transportation applications, please refer to the Infineon TLE and TLF voltage regulator series.
Description
The IFX80471 step-down DC-DC switching controllers provide high efficiency over loads ranging from 1mA up to
2.3A. A unique PWM/PFM control scheme operates with a duty cycle up to 100% resulting in a very low dropout
voltage. This control scheme eliminates minimum load requirements and reduces the supply current under light
loads to 120µA, depending on dimensioning of external components. In addition the adjustable version
IFX80471SKV can be shut down via the Enable input reducing the input current to <2µA. The IFX80471 step-down
controllers drive an external P-channel MOSFET, allowing design flexibility for applications up to 11.5W of output
power at 5V output voltage. The IFX80471 offers high switching frequency of up to 360kHz as well as operation
in continuous-conduction mode and allows the usage of tiny surface-mount inductors. Output capacitor
requirements are also reduced, minimizing PC board area and system costs. The output voltage of the
IFX80471SKV50 is preset to 5V and is adjustable for the IFX80471SKV. The IFX80471SKV50 features a reset
function with a threshold between 4.5V and 4.8V, including a small hysteresis of typ. 50mV. Input voltages of both
IFX80471 versions can be up to 60V.
Data Sheet 4 Rev. 1.0, 2011-02-07
IFX80471
Block Diagram
2 Block Diagram
Figure 1 Block Diagram
Internal Power
Supply and
Biasing
Battery Sense and
Undervoltage Reset
Voltage
Reference
Block
PWM / PFM
Regulator
Clock generator
SO
RO
VOUT
G
DRV
SYNC
SI
ENA
BLE
SI-
GND
GND
VS
IFX80471SKV
Driver
COMP
CS
FB
BDS
IFX80471
Pin Configuration
Data Sheet 5 Rev. 1.0, 2011-02-07
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol Function
1 ENABLE Active-High enable input (only adjustable version, IFX80471SKV) for the
device.
The device is shut down when ENABLE is driven low. In this shut down-mode the
reference, the output and the external MOSFET are turned off. Connect to logic high
for normal operation.
1 SI_ENABLE Active-High enable input (only 5V version, IFX80471SKV50) for SI_GND input.
SI_GND is switched to high impedance when SI_ENABLE is low. High level at
SI_ENABLE connects SI_GND to GND with low impedance. SO is undefined when
SI_ENABLE is low.
2FB Feedback input.
1. For adjustable version (IFX80471SKV) connect this pin to an external voltage
divider from the output to GND (see Chapter 7.2).
2. For the 5V fixed output voltage version (IFX80471SKV50) the FB is connected to
an on-chip voltage divider supplied internally by VOUT. It does not have to be
connected externally to the output.
3VOUT Buck output voltage input.
Input for the internal supply. Connect always to the output of the buck converter
(output capacitor).
8
9
10
11
12
7
6
5
4
3
2 13
1 14
ENABLE /
SI_ENABLE
FB
VOUT
GND
SYNC
SI_GND
SI
CS
VS
GDRV
BDS
RO
SO
COMP
Data Sheet 6 Rev. 1.0, 2011-02-07
IFX80471
Pin Configuration
4GND Ground connection. Analog signal ground.
5 SYNC Input for external frequency synchronization.
An external clock signal connected to this pin allows switching frequency
synchronization of the device. The internal oscillator is clocked then by the
frequency applied at the SYNC input.
6 SI_GND SI-Ground input.
Ground connection for SI comparator resistor divider. Depending on SI_ENABLE
this input is switched to high impedance or low ohmic to GND.
7SI Sense comparator input.
Input of the low-battery comparator. This input is compared to an internal 1.25V
reference where SO gives the result of the comparison. Can be used for any
comparison, not necessarily as battery sense.
8 COMP Compensation input.
Connect via RC-compensation network to GND.
9SO Sense comparator output.
Open drain output from SI comparator at the adjustable version (IFX80471SKV),
Pull down structure with an internal 20kΩ pull up resistor to VOUT at the 5V version
(IFX80471SKV50).
10 RO Reset output.
Open drain output from undervoltage reset comparator at the adjustable version
(IFX80471SKV),
Pull down structure with an internal 20kΩ pull up resistor to VOUT at the 5V version
(IFX80471SKV50).
11 BDS Buck driver supply input.
Connect a ceramic capacitor between BDS and VS to generate clamped gate-
source voltage to supply the driver of the PMOS power stage.
12 GDRV Gate drive output.
Connect to the gate of the external P-Channel MOSFET. The voltage at GDRV
swings between the levels of VS and BDS.
13 VS Device supply input.
Connect a 220nF ceramic cap close to the pin in addition to the low ESR tantalum
input capacitance.
14 CS Current-sense input.
Connect current-sense resistor between VS and CS. The voltage drop over the
sense-resistor determines the peak current flowing in the buck circuit. The external
MOSFET is turned off when the peak current is exceeded.
Pin Symbol Function
IFX80471
General Product Characteristics
Data Sheet 7 Rev. 1.0, 2011-02-07
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Absolute Maximum Ratings 1)
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Device supply input VS
4.1.1 Voltage VVS -0.3 61 V –
4.1.2 Current IVS ––––
Current sense input CS
4.1.3 Voltage VCS -0.3 61 V |VVS - VCS| < 0.3V
4.1.4 Current ICS ––––
Gate drive output GDRV
4.1.5 Voltage VGDRV – 0.3 61 V -0.3V < |VVS -VGDRV|
< 6.8V;
-0.3V < |VBDS - VGDRV|
< 6.8V
4.1.6 Current IGDRV – – – limited internally
Buck driver supply input BDS
4.1.7 Voltage VBDS – 0.3 61 V -0.3V < |VVS - VBDS|
< 6.8V
4.1.8 Current IBDS ––––
Feedback input FB
4.1.9 Voltage VFB – 0.3 6.8 V –
4.1.10 Current IFB ––––
Enable input SI_ENABLE
4.1.11 Voltage VSI_ENABLE – 0.3 61 V IFX80471SKV50
4.1.12 Current ISI_ENABLE ––––
SI-Ground input SI_GND
4.1.13 Voltage VSI_GND – 0.3 61 V –
4.1.14 Current ISI_GND ––––
Enable input ENABLE
4.1.15 Voltage VENABLE – 0.3 61 V IFX80471SKV
4.1.16 Current IENABLE – – V –
Sense comparator input SI
4.1.17 Voltage VSI – 0.3 61 V –
4.1.18 Current ISI – – V –
Sense comparator output SO
4.1.19 Voltage VSO – 0.3 6.8 V –
4.1.20 Current ISO – – V limited internally
Data Sheet 8 Rev. 1.0, 2011-02-07
IFX80471
General Product Characteristics
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Buck output voltage input VOUT
4.1.21 Voltage VVOUT – 0.3 15 V IFX80471SKV
4.1.22 Voltage VVOUT – 0.3 6.8 V IFX80471SKV50
4.1.23 Current IVOUT – – V –
Compensation input COMP
4.1.24 Voltage VCOMP – 0.3 6.8 V –
4.1.25 Current ICOMP – – V –
Reset output RO
4.1.26 Voltage VRO – 0.3 6.8 V –
4.1.27 Current IRO – – V limited internally
Frequency synchronization input SYNC
4.1.28 Voltage VSYNC – 0.3 6.8 V –
4.1.29 Current ISYNC – – V –
Temperatures
4.1.30 Junction Temperature TJ-40 150 °C –
4.1.31 Storage temperature TSTG -50 150 °C –
ESD Susceptibility
4.1.32 ESD Resistivity Pin VOUT VESD_VOUT -1.5 1.5 kV HBM2)
4.1.33 ESD Resistivity all Pins except VOUT VESD -2 2 kV HBM2)
4.1.34 ESD Resistivity to GND VESD -500 500 V CDM3)
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to EIA/JESD 22-A114B
3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Absolute Maximum Ratings (cont’d)1)
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
IFX80471
General Product Characteristics
Data Sheet 9 Rev. 1.0, 2011-02-07
4.2 Functional Range
[
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
Table 1
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Supply Voltage Range VVS 560V–
4.2.2 Output voltage adjust range
IFX80471SKV
VOUT 7 15 V IFX80471SKV
4.2.3 Sense Resistor RSENSE 10 47 mΩCalculation see
Chapter 7
4.2.4 PMOS, on+off delay ton+off delay –tmin-300 1)
1) A too high PMOS on+off delay might cause an instable output voltage
ns tmin=
VVOUT /(VVS*fSW)
4.2.5 Buck driver supply capacitor CBDS 220 – nF –
4.2.6 Buck inductance L122 100 µH –2)
2) a recommended minimum value for L1 is 47µH
4.2.7 Buck output capacitor COUT 100 – µF –
4.2.8 Junction Temperature Tj-40 125 °C–
Data Sheet 10 Rev. 1.0, 2011-02-07
IFX80471
General Product Characteristics
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Soldering Point1)
1) Not subject to production test, specified by design.
RthJSP –50–K/W–
4.3.2 Junction to Ambient1) RthJA – 140 – K/W Footprint only
Data Sheet 10 Rev. 1.0, 2011-02-07
IFX80471
Electrical Characteristics
5 Electrical Characteristics
5.1 Electrical Characteristics
Electrical Characteristics: Power
5V < VVS < 48V; Tj = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Current Consumption1) IFX80471SKV50
5.1.1 Current consumption of VS IVS –80 150 µA VVS = 48V;
PFM mode
–70 85 µA VVS = 13.5V;
PFM mode;
Tj = 25 °C
5.1.2 Current consumption of
SI_ENABLE
ISI_ENABLE –930µAVVS = 48V;
VSI_ENABLE = 48V;
PFM mode
5.1.3 Current consumption of
VOUT
IVOUT –95 130 µA VSI_ENABLE = L;
VVOUT = 5.5V;
VVS=13.5V;
PFM mode;
Tj = 25°C
–140 220 µA VSI_ENABLE = H;
VVOUT = 5.5V;
VVS = 13.5V;
VSI > VSI, high;
PFM mode
5.1.4 Current consumption of SI ISI –0.2 0.5 µA VSI_ENABLE = H;
VVS = 13.5V;
VSI = 10V;
PFM mode
Current Consumption1) IFX80471SKV (variable)
5.1.5 Current consumption of VS IVS –80 150 µA VVS = 48V;
VENABLE = H;
PFM mode;
VOUT > 7V
–70 85 µA VVS = 13.5V;
VENABLE = H;
PFM mode;
Tj = 25 °C;
VOUT > 7V
5.1.6 Current consumption of VS –2µAVENABLE = 0V;
Tj < 105°C
5.1.7 Current consumption of
ENABLE
IEN –930µAVVS = 48V;
VENABLE = H;
PFM mode
IFX80471
Electrical Characteristics
Data Sheet 11 Rev. 1.0, 2011-02-07
5.1.8 Current consumption of
VOUT
IVOUT –140 220 µA VOUT = 8V;
VVS = 13.5V;
VENABLE = H;
VSI > VSI, high;
PFM mode
5.1.9 Current consumption of SI ISI –0.2 0.5 µA VVS = 13.5V;
VENABLE = H;
VSI = 10V;
PFM mode;
Tj = 25°C
5.1.10 Current consumption of FB IFB –0.2 0.5 µA VVS = 13.5V;
VFB = 1.25V;
VENABLE = H;
PFM mode;
Tj = 25°C
Buck Controller
5.1.11 Output voltage VVOUT 4.85 5.00 5.15 V IFX80471SKV50;
VVS=13.5V& 48V;
PWM mode
IOUT = 0.5 to 2A;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω
4.75 5.00 5.25 V IFX80471SKV50;
VVS = 24V; PFM mode;
IOUT = 15mA;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;
5.1.12 FB threshold voltage VFB, th
1.225
1.25
1.275
V IFX80471SKV
5.1.13 Output voltage VVOUT 9.7 10.0 10.3 V IFX80471SKV;
Calibrated divider, see
Chapter 7.2;
VVS = 13.5V & 48V;
IOUT = 0.5 to 2A;
PWM mode;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;
9.5 10.0 10.5 V IFX80471SKV;
Calibrated divider, see
Chapter 7.2;
VVS = 24V;
IOUT = 15mA;
PFM mode;
RSENSE = 22mΩ;
RM1 = 0.25Ω;
RL1 = 0.1Ω;
Electrical Characteristics: Power (cont’d)
5V < VVS < 48V; Tj = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Data Sheet 12 Rev. 1.0, 2011-02-07
IFX80471
Electrical Characteristics
5.1.14 Buck output voltage adjust range VVOUT VFB, th –7V IFX80471SKV, supplied by
VS only, complete current to
supply the IC drawn from VS,
no reset function 2)
7–15 V IFX80471SKV, current to
supply the IC drawn from VS
and VOUT, as specified 2)
5.1.15 Buck output voltage accuracy VVOUT 0.97 *
VOUT_nom
–1.03 *
VOUT_nom
IFX80471SKV;
PWM mode 2)
5.1.16 Buck output voltage accuracy VVOUT 0.95 *
VOUT_nom
–1.05 *
VOUT_nom
IFX80471SKV,
PFM mode 2)
5.1.17 Line regulation |
Δ
V VOUT |––35 mV IFX80471SKV50,
VVS = 9V to 16V;
IOUT = 1A;
RSENSE = 22mΩ;
PWM mode
––50 mV IFX80471SKV50,
VVS = 16V to 32V;
IOUT = 1A;
RSENSE = 22mΩ;
PWM mode
5.1.18 Line regulation
Δ
V VOUT
/
VVOUT
––2.5 % IFX80471SKV,
VVS = 12V to 36V;
VVOUT=10V
IOUT = 1A;
RSENSE = 22mΩ;
PWM mode
5.1.19 Load regulation
Δ
V VOUT
/
Δ
ILOAD
–40 –mV/
A
IFX80471SKV50;
IOUT = 0.5A to 2A; VVS = 5.8V
& 48V;
RSENSE = 22mΩ
–8*
VOUT_nom
/ V
–mV/
A
IFX80471SKV;
IOUT = 0.5 to 2A;
VVS= 13.5V & 48V;
RSENSE = 22mΩ
5.1.20 Gate driver,
PMOS off
VVS –
VGDRV
0–0.2VVENABLE/SI_ENABLE = 5 V;
CBDS = 220 nF;
CGDRV = 4.7nF
5.1.21 Gate driver,
PMOS on
VVS –
VGDRV
6–8.2VVENABLE/SI_ENABLE = 5 V;
CBDS = 220 nF;
CGDRV = 4.7nF3)
5.1.22 Gate driver,
UV lockout
VVS – VBDS 2.75 – 4 V Decreasing (VVS-VBDS) until
GDRV is permanently at VS
level
5.1.23 Gate driver,
peak charging current
IGDRV – 1 – A PMOS dependent; 2)
5.1.24 Gate driver,
peak discharging current
IGDRV – 1 – A PMOS dependent; 2)
Electrical Characteristics: Power (cont’d)
5V < VVS < 48V; Tj = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
IFX80471
Electrical Characteristics
Data Sheet 13 Rev. 1.0, 2011-02-07
5.1.25 Gate driver,
gate voltage, rise time
tr–4560nsVENABLE/SI_ENABLE = 5 V;
CBDS = 220 nF;
CGDRV = 4.7nF
5.1.26 Gate driver,
gate voltage, fall time
tf–5065nsVENABLE/SI_ENABLE = 5 V;
CBDS = 220 nF;
CGDRV = 4.7nF
5.1.27 Peak current limit threshold
voltage
VLIM =
VVS - VCS
50 70 90 mV
5.1.28 Oscillator frequency fOSC 290 360 420 kHz PWM mode only
5.1.29 Maximum duty cycle dMAX 100 ––%PWM mode only
5.1.30 Minimum on time tMIN –220 400 ns PWM mode only
5.1.31 SYNC capture range
Δ
fsync 250 –530 kHz PWM mode only
5.1.32 SYNC trigger level high VSYNC,h 4.0 ––V
2)
5.1.33 SYNC trigger level low VSYNC,l ––0.8 V2)
Reset Generator
5.1.34 Reset headroom VRT,HEAD 80 ––mVIFX80471SKV50;
VOUT (VS=6V,
ILOAD=1A)
-VVOUT,RT
5.1.35 Reset threshold VVOUT, RT 4.5 4.65 4.8 VIFX80471SKV50;
VVOUT increasing/decreasing
5.1.36 Reset threshold hysteresis ΔVVOUT, RT –50 –mVIFX80471SKV50 2)
5.1.37 Reset threshold VFB, RT –1.12 –VIFX80471SKV;
VVOUT decreasing
–1.17 –VIFX80471SKV;
VVOUT increasing
5.1.38 Reset output pull up resistor RRO 10 20 40 kΩIFX80471SKV50; Internally
connected to VOUT
5.1.39 Reset output High voltage VRO, H
0.8 *
V
VOUT
––VIFX80471SKV50;
IRO = 0mA
5.1.40 Reset output Low voltage VRO,L –0.20.4VIRO, L = 1mA;
2.5V < VVOUT < VRT
–0.2 0.4 V IRO, L = 0.2mA;
1V < VVOUT < 2.5V
5.1.41 Reset delay time trd 17 21 25 ms IFX80471SKV
70 82 100 ms IFX80471SKV50
5.1.42 Reset reaction time trr ––10µs
2)
Overvoltage Lockout
5.1.43 Overvoltage threshold VVOUT, OV –VOUT_nom
+ 100
–mVIFX80471SKV50;
VVOUT increasing
5.1.44 Overvoltage threshold VFB, OV –VFB,th,nom
+ 20
–mVIFX80471SKV;
VVOUT increasing
Electrical Characteristics: Power (cont’d)
5V < VVS < 48V; Tj = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Data Sheet 14 Rev. 1.0, 2011-02-07
IFX80471
Electrical Characteristics
ENABLE Input
5.1.45 Enable ON-threshold Venable,ON 4.5 – – V
5.1.46 Enable OFF-threshold Venable,OFF ––0.8V
SI_ENABLE Input
5.1.47 Enable ON-threshold Venable,ON 4.5 – – V
5.1.48 Enable OFF-threshold Venable,OFF ––0.8V
SI_GND Input
5.1.49 Switch ON resistance RSW 50 100 230 ΩVSI_ENABLE = 5V;
ISI_GND = 3mA
Battery Voltage Sense
5.1.50 Sense threshold VSI, low 1.22 1.25 1.28 V VVS decreasing
5.1.51 Sense threshold VSI, high –1.33–VV
VS increasing
5.1.52 Sense threshold hysteresis VSI, hys 30 80 120 mV
5.1.53 Sense output pull up resistor RSO 10 20 40 kΩIFX80471SKV50;
Internally connected to
VVOUT
5.1.54 Sense out output High voltage VSO,H 0.8 *
VVOUT
VISO,H =0mA
5.1.55 Sense out output Low voltage VSO,L 0.2 0.4 V ISO,L = 1mA;
2.5V < VVOUT; VSI <1.13V
0.4 VVOUT VISOL=0.2mA;
1V < VVOUT < 2.5V;
VSI <1.13V
Thermal Shutdown
5.1.56 Thermal shutdown junction
temperature
TjSD 150 175 200 °C2)
5.1.57 Temperature hysteresis ΔT30K
2)
1) The device current measurements for IVS and IFB exclude MOSFET driver currents.
2) Not subject to production test - specified by design
3) For 4V < VVS < 6V: VGDRV ≈ 0V.
Electrical Characteristics: Power (cont’d)
5V < VVS < 48V; Tj = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
IFX80471
Electrical Characteristics
Data Sheet 15 Rev. 1.0, 2011-02-07
5.2 Typical Performance Characteristics
Typical Performance Characteristics
Current Consumption IVS versus
Junction Temperature TJ (INH = ON), VVS = 13.5 V
Current Consumption IVOUT versus
Junction Temperature TJ (INH = ON), VVOUT = 5.5 V
Current Consumption IVS versus Junction
Temperature TJ (INH = ON), VVOUT = 48 V
Current Consumption IVOUT vs. Junction Tempera-
ture TJ (INH = ON), VOUT = 10 V (IFX80471SKV)
-50 -20 10 40 70 100 130 160
T
j
°C
I
VS
µA
20
30
40
50
60
70
80
90
-50 -20 10 40 70 100 130 160
T
j
°C
I
VOUT
µA
110
120
130
140
150
160
170
180
-50 -20 10 40 70 100 130 160
T
j
°C
I
VS
µA
40
50
60
70
80
90
100
110
-50 -20 10 40 70 100 130 160
T
j
°C
I
VOUT
µA
90
100
110
120
130
140
150
160
Data Sheet 16 Rev. 1.0, 2011-02-07
IFX80471
Electrical Characteristics
Internal oscillator frequency fOSC
versus Junction Temperature Tj)
Peak current limit threshold voltage VLIM versus
Junction Temperature Tj
Minimum on time tMIN (blanking)
versus Junction Temperature Tj
Gate driver supply VVS - VBDS
versus Junction Temperature Tj
-50 -20 10 40 70 100 130 160
T
j
°C
f
OSC
kHz
310
320
380
330
340
350
360
370
-50 -20 10 40 70 100 130 160
T
j
°C
V
LIM
mV
40
50
60
70
80
90
100
110
-50 -20 10 40 70 100 130 160
T
j
°C
t
MIN
ns
175
200
350
225
250
275
300
325
-50 -20 10 40 70 100 130 160
T
j
°C
V
VS
-V
BDS
V
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
IFX80471
Electrical Characteristics
Data Sheet 17 Rev. 1.0, 2011-02-07
Lower Reset threshold VFB,RT
versus Junction Temperature Tj (IFX80471SKV)
Lower Sense threshold VSI, low
versus Junction Temperature Tj
On resistance of SI_GND switch RSW
versus Junction Temperature Tj
Output Voltage versus Load Current
(IFX80471SKV50)
-50 -20 10 40 70 100 130 160
T
j
°C
V
FB,RT
V
1.07
1.08
1.14
1.09
1.10
1.11
1.12
1.13
-50 -20 10 40 70 100 130 160
T
j
°C
V
SI,low
V
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
-50 -20 10 40 70 100 130 160
T
j
°C
R
SW
Ω
0
40
280
80
120
160
200
240
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75
I
LOAD
A
V
OUT
V
0
1
2
3
4
5
6
7
IFX80471SKV50
R
SENSE
= 50mΩ
V
VS
= 13.5V
App. Circuit Fig. 6
Data Sheet 18 Rev. 1.0, 2011-02-07
IFX80471
Electrical Characteristics
Output voltage vs. Load Current
(IFX80471SKV)
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75
ILOAD
A
VOUT
VOUT,nom
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
IFX80471SKV
RSENSE = 50mΩ
VVS = 13.5V
App. Circuit Fig. 5
IFX80471
Detailed Circuit Description
Data Sheet 19 Rev. 1.0, 2011-02-07
6 Detailed Circuit Description
In the following, the internal blocks of the IFX80471 are described in more detail. For selecting external
components please refer to the section “Application Information” on Page 21.
6.1 PFM/PWM Step-down regulator
To meet also high requirements in terms of current consumption a special PFM (Pulse Frequency Modulation) -
PWM (Pulse Width Modulation) control scheme for highest efficiency is implemented in the IFX80471 regulators.
Under light load conditions the output voltage is able to increase slightly and at a certain threshold the controller
jumps into PFM mode. In this PFM operation the PMOS is triggered with a certain on time (depending on input
voltage, output voltage, inductance- and sense resistor value) whenever the buck output voltage decreases to the
so called WAKE-threshold. The switching frequency of the step down regulator is determined in the PFM mode by
the load current. It increases with increasing load current and turns finally to the fixed PWM frequency at a certain
load current depending on the input voltage, current sense resistor and inductance. The diagram below shows the
buck regulation circuit of the IFX80471.
Figure 3 Buck control scheme
The IFX80471 uses a slope-compensated peak current mode PWM control scheme in which the feedback or
output voltage of the step down circuit and the peak current of the current through the PMOS are compared to
form the OFF signal for the external PMOS. The ON-trigger is set periodically by the internal oscillator when acting
in PWM mode and is given by the output of the WAKE-comparator when operating in PFM mode. The Multiplexer
(MUX) is switched by the output of the MODE-detector which distinguishes between PFM and PWM by tracking
the output voltage (go to PFM) and by tracking the gate trigger frequency (goto PWM). In PFM mode the peak
current limit is reduced to prevent overshoots at the output of the buck regulator. In order to avoid a gate turn off
signal due to the current peak caused by the parasitic capacitance of the catch diode the blanking filter is
necessary. The blanking time is set internally to 200ns and determines (together with the PMOS turn on and turn
off delay) the minimum duty cycle of the device. In addition to the PFM/PWM regulation scheme an overvoltage
lockout and thermal protection are implemented to guarantee safe operation of the device and of the supplied
application circuit.
VREF
VFB
VS
BDS
GDRV
Current-
sense
Amplifier
+
MUX
CSVS
Error
Amplifier
PWM
Comparator
Slope-
compensation
Blanking
R
S Q
+-
+
-
>1
&
+- +-
Over-
Voltage
Lockout
Over-
Temp.
Shutdown
VREFVFB, OV VREF VDIODE
-
+
Wake-
Comparator
VREF
VFB, WK
Oscillator
SYNC
MODE
Level-
shift
PFM
PWM
Data Sheet 20 Rev. 1.0, 2011-02-07
IFX80471
Detailed Circuit Description
6.2 Battery voltage sense
To detect undervoltage conditions at the battery a sense comparator block is available within the IFX80471. The
voltage at the SI input is compared to an internal reference of typ. 1.25V. The output of the comparator drives a
NMOS structure giving a low signal at SO as soon as the voltage at SI decreases below this threshold. In the 5V
fixed version an internal pull up resistor is connected from the drain of the NMOS to the output of the buck
converter, in the variable version SO is open drain.
The sense in voltage divider can be switched to high impedance by a low signal at the SI_ENABLE to avoid high
current consumption to GND (IFX80471SKV50 only).
Of course the sense comparator can be used for any input voltage and does not have to be used for the battery
voltage sense only.
6.3 Undervoltage Reset
The output voltage is monitored continuously by the internal undervoltage reset comparator. As soon as the output
voltage decreases below the thresholds given in the characteristics the NPN structure pulls RO low (latched). In
the 5V fixed version an internal pull up resistor is connected from the collector of the NPN to the output of the buck
converter, in the variable version RO is open collector.
At power up RO is kept low until the output voltage has reached its reset threshold and stayed above this threshold
for the power on reset delay time.
IFX80471
Application Information
Data Sheet 21 Rev. 1.0, 2011-02-07
7 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
7.1 General
The IFX80471 step-down DC-DC controllers are designed primarily for use in industrial applications and offer a
large flexibility in the input voltage range they can handle. Using an external P-MOSFET and current-sense
resistor allows design flexibility and the improved efficiencies associated with high-performance P-channel
MOSFETs. The unique, peak current-limited, PWM/PFM control scheme gives these devices excellent efficiency
over wide load ranges, while drawing around 100µA current from the battery under no load condition. This wide
dynamic range optimizes the IFX80471 for applications, where load currents can vary considerably as individual
circuit blocks are turned on and off to conserve energy. Operation to a 100% duty cycle allows the lowest possible
dropout voltage, maintaining operation during cold cranking. High switching frequencies and a simple circuit
topology minimize PC board area and component costs.
7.2 Output voltage at adjustable version - feedback divider
The output voltage is sensed either by an internal voltage divider connected to the VOUT pin (IFX80471SKV50,
fixed 5V version) or an external divider from the Buck output voltage to the FB pin (IFX80471SKV, adjustable
version). The Vout pin has to be connected always to the Buck converter output regardless which output voltage
for the adjustable version is desired.
To determine the resistors of the feedback divider for the desired output voltage VOUT at the IFX80471SKV select
RFB2 between 5kΩ and 500kΩ and obtain RFB1 with the following formula:
VFB is the threshold of the error amplifier with its value of typical 1.25V which shows that the output voltage can
be adjusted in a range from 1.25V to 15V. However the integrated Reset function will only be operational if the
output voltage level is adjusted to >7V.
Also the current consumption will be increased in PFM mode in the range between
1.25V and 7V.
7.3 SI_Enable
Connecting SI_ENABLE to 5V causes SI_GND to have low impedance. Thus the SI comparator is in operation
and can be used to monitor the battery voltage. SO output signal is valid. Connecting SI_ENABLE to GND causes
SI_GND to have high impedance. Thus the SI comparator is not able to monitor the battery voltage. SO output
signal is invalid.
RFB1 RFB2
VOUT
VFB th,
---------------- 1–
⎝⎠
⎛⎞
⋅=
Data Sheet 22 Rev. 1.0, 2011-02-07
IFX80471
Application Information
7.3.1 Battery sense comparator - voltage divider
The formula to calculate the resistor divider for the sense comparator is basically the same as for the feedback
divider in section before. With the selected resistor RSI2, the desired threshold of the input voltage VIN, UV and the
lower sense threshold VSI, low the resistor RSI1 is given to:
For high accuracy and low ohmic resistor divider values the on-resistance of the SI_GND NMOS (typ. 100Ω) has
to be added to RSI2.
7.4 Undervoltage reset - delay time
The diagram below shows the typical behavior of the reset output in dependency on the input voltage VIN, the
output voltage VVOUT or VFB.
Figure 4 Reset timing
7.5 100% duty-cycle operation and dropout
The IFX80471 operates with a duty cycle up to 100%. This feature allows to operate with the lowest possible drop
voltage at low battery voltage as it occurs at cold cranking. The MOSFET is turned on continuously when the
supply voltage approaches the output voltage level, conventional switching regulators with less than 100% duty
cycle would fail in that case.
RSI1 RSI2
VIN UV,
VSI low,
-------------------1–
⎝⎠
⎛⎞
⋅=
IFX80471
Application Information
Data Sheet 23 Rev. 1.0, 2011-02-07
The drop- or dropout voltage is defined as the difference between the input and output voltage levels when the
input is low enough to drop the output out of regulation. Dropout depends on the MOSFET drain-to-source on-
resistance, the current-sense resistor and the inductor series resistance. It is proportional to the load current:
7.6 SYNC Input and Frequency Control
The IFX80471’s internal oscillator is set for a fixed PWM switching frequency of 360kHz or can be synchronized
to an external clock at the SYNC pin. When the internal clock is used SYNC has to be connected to GND. SYNC
is a negative-edge triggered input that allows synchronization to an external frequency ranging between 270kHz
and 530kHz. When SYNC is clocked by an external signal, the converter operates in PWM mode until the load
current drops below the PWM to PFM threshold. Thereafter the converter continues operation in PFM mode.
7.7 Shutdown Mode
Connecting ENABLE to GND places the IFX80471SKV in shutdown mode. In shutdown, the reference, control
circuitry, external switching MOSFET, and the oscillator are turned off and the output falls to 0V. Connect ENABLE
to voltages higher than 4.5V for normal operation. As this input operates analogue way the voltage applied at this
pin should have a slope of 0.5V/3µs as a minimum requirement to avoid undefined states within the device.
7.8 Buck converter circuit
A typical choice of external components for the buck converter circuit is given in Figure 5 and Figure 6. For basic
operation of the buck converter the input capacitors CIN1, CIN2, the driver supply capacitor CBDS, the sense resistor
RSENSE, the PMOS device, the catch diode D1, the inductance L1 and the output capacitor COUT are necessary. In
addition for low electromagnetic emission a Pi-filter at the input and/or a small resistor in the path between GDRV
and the gate of the PMOS may be necessary.
7.8.1 Buck inductance (L1) selection in terms of ripple current
The internal PWM/PFM control loop includes a slope compensation for stable operation in PWM mode. This slope
compensation is optimized for inductance values of 47µH and Sense resistor values of 47mΩ for the 5V output
voltage versions. When choosing an inductance different from 47µH the Sense resistor has to be changed also:
Increasing this ratio above 1000 Ω/H may result in sub harmonic oscillations as well-known for peak current mode
regulators without integrated slope compensation.
To achieve the same effect of slope compensation in the adjustable voltage version also the inductance in µH is
given by
Vdrop ILOAD RDS ON()PMOS RSENSE RINDUCTANCE
++()⋅=
RSENSE
L1
------------------- ( 0 , 5 . . . 1 , 0 )3
×10 Ω
H
----
=
Data Sheet 24 Rev. 1.0, 2011-02-07
IFX80471
Application Information
The inductance value determines together with the input voltage, the output voltage and the switching frequency
the current ripple which occurs during normal operation of the step down converter. This current ripple is important
for the all over ripple at the output of the switching converter.
In this equation fsw is the actual switching frequency of the device, given either by the internal oscillator or by an
external source connected to the SYNC pin. When picking finally the inductance of a certain supplier (Epcos,
Coilcraft etc.) the saturation current has to be considered. The saturation current value of the desired inductance
has to be higher than the maximum peak current which can appear in the actual application.
7.8.2 Determining the current limit
The peak current which the buck converter is able to provide is determined by the peak current limit threshold
voltage VLIM and the sense resistor RSENSE. With a maximum peak current given by the application (IPEAK,
PWM=ILOAD+0.5ΔI) the sense resistor is calculated to
The equation above takes account for the foldback characteristic of the current limit as shown in the figures ’Output
Voltage versus Load Current’ on page 17/18 by introducing a factor of 2. It must be assured by correct
dimensioning of RSENSE that the load current doesn’t reach the foldback part of the characteristic curve.
7.8.3 PFM and PWM thresholds
The crossover thresholds PFM to PWM and vice versa strongly depend on the input voltage VIN, the Buck
converter inductance L1, the sense resistor value RSENSE and the turn on and turn off delays of the external PMOS.
7.8.4 Buck output capacitor (COUT) selection:
The choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of
the buck converter. In continuous conduction mode the ripple of the output voltage can be estimated by the
following equation:
2,0 10 4–
×H
VΩ
---------VOUT RSENSE
⋅⋅ ⋅
⎝⎠
⎛⎞
L1 4,0 10 4–
×H
VΩ
---------V⋅OUT RSENSE
⋅⋅
⎝⎠
⎛⎞
<<
ΔIVIN VOUT
–()VOUT
⋅
fSW VIN L1⋅⋅
------------------------------------------------------=
RSENSE
VLIM
2I⋅PEAK PWM,
-------------------------------------=
VRipple ΔIR
ESRCOUT
1
8f
SW COUT
⋅⋅
------------------------------------+
⎝⎠
⎛⎞
⋅=
IFX80471
Application Information
Data Sheet 25 Rev. 1.0, 2011-02-07
From the formula it is recognized that the ESR has a big influence in the total ripple at the output, so low ESR
tantalum or ceramic capacitors are recommended for the application (recommended range: 50mOhm to
150mOhm).
One other important thing to note are the requirements for the resonant frequency of the output LC-combination.
The choice of the components L and C have to meet also the specified range given in Chapter 4.2 otherwise
instabilities of the regulation loop might occur.
7.8.5 Input capacitor (CIN1) selection:
At high load currents, where the current through the inductance flows continuously, the input capacitor is exposed
to a square wave current with its duty cycle VOUT/VI. To prevent a high ripple to the battery line a capacitor with
low ESR should be used. The maximum RMS current which the capacitor has to withstand is calculated to:
For low ESR an e.g. Al-electrolytic capacitance in parallel to an ceramic capacitance could be used.
7.8.6 Freewheeling diode / catch diode (D1)
For lowest power loss in the freewheeling path Schottky diodes are recommended. With those types the reverse
recovery charge is negligible and a fast hand over from freewheeling to forward conduction mode is possible.
Depending on the application (12V battery systems) 40V types could be also used instead of the 60V diodes. Also
for high temperature operation select a Schottky-diode with low reverse leakage.
A fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance
values (smaller spikes) are desired.
7.8.7 Buck driver supply capacitor (CBDS)
The voltage at the ceramic capacitor is clamped internally to 7V, a ceramic type with a minimum of 220nF and
voltage class 16V would be sufficient.
7.8.8 Input pi-filter components for reduced EME
At the input of Buck converters a square wave current is observed causing electromagnetic interference on the
battery line. The emission to the battery line consists on one hand of components of the switching frequency
(fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the
current slope. For proper attenuation of those interferers a π-type input filter structure is recommended which is
built up with inductive and capacitive components in addition to the Input caps CIN1 and CIN2. The inductance can
be chosen up to the value of the Buck converter inductance, higher values might not be necessary, the additional
capacitance should be a ceramic type in the range up to 100nF.
Inexpensive input filters show due to their parasitics a notch filter characteristic, which means basically that the
low pass filter acts from a certain frequency as a high pass filter and means further that the high frequency
components are not attenuated properly. To slower down the slopes at the gate of the PMOS switch and get down
the emission in the high frequency range a small gate resistor can be put between GDRV and the PMOS gate.
7.8.9 Frequency compensation
The external frequency compensation pin should be connected via a 22nF (>10V) ceramic capacitor and a 430 Ω
(1/8W) resistor to GND. This node should be kept free from switching noise.
IRMS ILOAD
VOUT
VIN
-------------- 1 1
3
---ΔI
2I
LOAD
⋅
-----------------------
⎝⎠
⎛⎞
2
⋅+⋅⋅=
Data Sheet 26 Rev. 1.0, 2011-02-07
IFX80471
Application Information
7.9 Components recommendation - Overview
7.10 Layout recommendation
The most sensitive points for Buck converters - when considering the layout - are the nodes at the input, output
and the gate of the PMOS transistor and the feedback path.
For proper operation and to avoid stray inductance paths the external catch diode, the Buck inductance and the
input capacitor CIN1 have to be connected as close as possible to the PMOS device. Also the GDRV path from the
controller to the MOSFET has to be as short as possible. Best suitable for the connection of the cathode of the
catch diode and one terminal of the inductance would be a small plain located next to the drain of the PMOS.
The GND connection of the catch diode must be also as short as possible. In general the GND level should be
implemented as surface area over the whole PCB as second layer, if necessary as third layer. The feedback path
has to be well grounded also, a ceramic capacitance might help in addition to the output cap to avoid spikes.
To obtain the optimum filter capability of the input pi-filter it has to be located also as close as possible to the input.
To filter the supply input of the device (VS) the ceramic cap should be connected directly to the pin.
As a guideline an EMC optimized application board / layout is available.
Device Values / Remarks
CIN1 100μF, 60V
CIN2 220nF, 60V
L1 47μH, 1.6A, 145mΩ
47μH, 3.5A, 47mΩ
47μH, 3.8A, 110mΩ
68μH, 3.5A, 130mΩ
47μH, 4.0A, 97mΩ
M1 60V, 3.44A, 130mΩ, NL
60V, 2.9A, 130mΩ, NL
60V, 9A, 250mΩ, LL
CBDS 220nF, 16V
D1 Schottky, 60V, 3A
Schottky, 40V, 3A
Schottky, 40V, 3A
COUT Low ESR Tantalum, 100μF, 10V
CCOMP see 7.8.9.
IFX80471
Application Information
Data Sheet 27 Rev. 1.0, 2011-02-07
Figure 5 Application Diagram circuit IFX80471SKV
Figure 6 Application Diagram circuit IFX80471SKV50
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
M1
D1
C
OUT
=
100 μF
V
OUT
C
BDS
=
220 nF
V
IN
L
1
= 47 μH
IFX80471SKV
GDRV
BDS VOUT
GND ENABLE
C
IN1
=
100 μF
ON OFF
CS
R
SEN SE
=
47mΩ
M1: Infineon BSO 613SPV
or Infineon BSP 613P
R
SI 1
=
400kΩ
C
IN2
=
220nF
R
SI 2
=
100kΩ
FB
SO
RO
SYNC
COMP
R
FB2
=
47kΩ
11
13
7SI
VS
14 12 3
9
2
8
10451
SI_GND
6
to e.g. 5V rail
R
SO
=
R
RO
=
20kΩ
to µC
to µC
R
FB1
=
330kΩ
430Ω
22nF
M1
D1
C
OUT
=
100 μF
V
OUT
C
BD S
=
220 nF
V
IN
L
1
= 47 μH
GDRVBDS FB
GNDSI_ENABLE
VS
C
IN1
=
100 μF
ON OFF
CS
R
SENSE
=
47mΩ
M1: Infineon BSO 613SPV
or Infineon BSP 613P
SI_GND
SI
R
SI 1
=
400kΩ
C
IN2
=
220nF
R
SI 2
=
100kΩ
COMP
SO
RO
SYNC
V
OUT
I
OUT
IFX80471SKV50
11 14 12 2
3
9
8
10451
7
13
6
VOUT
430Ω22nF
Data Sheet 28 Rev. 1.0, 2011-02-07
IFX80471
Package Outlines
8 Package Outlines
Figure 7 PG-DSO-14
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
-0.2
8.75
1)
0.64
0.19
+0.06
Index Marking
1.27
+0.10
0.41
0.1
1
14
2)
7
14x
8
0.175
(1.47)
±
0.07
±0.2
6
0.35 x 45˚
-0.2
1.75 MAX.
4
1)
±0.25
8˚MAX.
-0.06
0.2 MAB
M
0.2 C
C
B
A
GPS01230
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
IFX80471
Revision History
Data Sheet 29 Rev. 1.0, 2011-02-07
9 Revision History
Revision Date Changes
1.0 2011-02-07 Data Sheet - Initial Release
Edition 2011-02-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
The Infineon Technologies component described in this Data Sheet may be used in life-support devices or
systems and/or automotive, aviation and aerospace applications or systems only with the express written approval
of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that
life-support automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that
device or system. Life support devices or systems are intended to be implanted in the human body or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the
user or other persons may be endangered.