CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 3-128
SEMICONDUCTOR
80C286/883
High Performance Microprocessor with Memory
Management and Protection
Description
The Harris 80C286/883 is a static CMOS version of the
NMOS 80286 microprocessor. The 80C286/883 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. The 80C286/883 has built-in memory protection that
suppor ts operating system and task isolation as well as pro-
gram and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 224
bytes (16 megabytes) of physical memory.
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a super-
set of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code com-
patible with e xisting 80C86 and 80C88 softw are. In protected
vir tual address mode, the 80C286/883 is source code com-
patible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883’s integrated memory management and protec-
tion mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
The 80C286/883 provides special operations to support the
efficient implementation and e xecution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present excep-
tion and restartable instructions.
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Compatible with NMOS 80286/883
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
• Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
• Compatible with 80287 Numeric Data Co-Processor
March 1997
Ordering Information
PACKAGE TEMP. RANGE 10MHz 12.5MHz 16MHz 20MHz 25MHz PKG. NO.
68 Pin PGA 0oC to +70oC - CG80C286-12 CG80C286-16 CG80C286-20 - G68.B
-40oC to +85oC IG80C286-10 IG80C286-12 - - - G68.B
-55oC to +125oC MG80C286-10/883 MG80C286-12/883 - - - G68.B
5962-9067801MXC 5962-9067802MXC - - - G68.B
File Number 2948.1
3-129
80C286/883
Pinout
68 LEAD PGA, COMPONENT PAD VIEW
As viewed from underside of the component when mounted on the board.
P.C. BOARD VIEW
As viewed from the component side of the P.C. board.
68
66
64
62
60
58
56
54
5253
51
55
57
59
61
63
65
67
2
13
579
10 4
6812
1113
1416
1517
1918
2120
22
24
26
28
30
32
34
23
25
27
29
31
33
36
35 37
38 40
39 41
42 44
43 45
46 48
47 49
50
ERROR
D7
D6
D5
D4
D3
D2
D1
D0
NC
S1
PEACK
A22
A21
A19
A17
A15
A12
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/IO
NC
NC
BUSY
NC
NC
VSS
VCC
HOLD
COD/INTA
LOCK
D15
D14
D13
D12
D11
D10
D9
D8
VSS
BHE
NC
S0
A23
VSS
A20
A18
A16
A14
A0
A2
VCC
A3
A5
A7
A9
A11
A13
PIN 1 INDICATOR
68
66
64
62
60
58
56
54
52 53
51
55
57
59
61
63
65
67
2
13579
10
468 12
11 13
14 16
15 17
19 18
21 20
22
24
26
28
30
32
34
23
25
27
29
31
33
36
3537
3840
3941
4244
4345
4648
4749
50
ERROR
D7
D6
D5
D4
D3
D2
D1
D0
NC
S1
PEACK
A22
A21
A19
A17
A15
A12
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/IO
NC
NC
BUSY
NC
NC
VSS
VCC
HOLD
COD/INTA
LOCK
D15
D14
D13
D12
D11
D10
D9
D8
VSS
BHE
NC
S0
A23
VSS
A20
A18
A16
A14
A0
A2
VCC
A3
A5
A7
A9
A11
A13
PIN 1 INDICATOR
3-130
80C286/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage Applied. . . . . .GND -1.0V to VCC +1.0V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical) θJA θJC
PGA Package . . . . . . . . . . . . . . . . . . . . . 35oC/W 6oC/W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max)
System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max)
Input RISE and FALL Time (From 0.8V to 2.0V
80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL CONDITIONS
GROUP A
SUB-
GROUPS TEMPERATURE
LIMITS
UNITS MIN MAX
Input LOW Voltage VIL VCC = 4.5V 1, 2, 3 -55oC≤ TA≤ +125oC -0.5 0.8 V
Input HIGH Voltage VIH VCC = 5.5V 1, 2, 3 -55oC≤ TA≤ +125oC 2.0 VCC +0.5 V
CLK Input LOW Voltage VILC VCC = 4.5V 1, 2, 3 -55oC≤ TA≤ +125oC -0.5 1.0 V
CLK Input HIGH Voltage VIHC VCC = 5.5V 1, 2, 3 -55oC≤ TA≤ +125oC 3.6 VCC +0.5 V
Output LOW Voltage VOL IOL = 2.0mA, VCC = 4.5V 1, 2, 3 -55oC≤ TA≤ +125oC - 0.4 V
Output HIGH Voltage VOH IOH = -2.0mA, VCC = 4.5V 1, 2, 3 -55oC≤ TA≤ +125oC 3.0 - V
IOH = -100µA, VCC = 4.5V VCC -0.4 - V
Input Leakage Current IIVIN = GND or VCC,
VCC = 5.5V,
Pins 29, 31, 57, 59, 61,
63-64
1, 2, 3 -55oC≤ TA≤ +125oC -10 10 µA
Input Sustaining Current
LOW IBHL VCC = 4.5V and 5.5V,
VIN = 1.0V, Note 1 1, 2, 3 -55oC≤ TA≤ +125oC 38 200 µA
Input Sustaining Current
HIGH IBHH VCC = 4.5V and 5.5V,
VIN = 3.0V, Note 2 1, 2, 3 -55oC≤ TA≤ +125oC -50 -400 µA
Input Sustaining Current
on BUSY and ERROR
Pins
ISH VCC = 4.5V and 5.5V
VIN = GND, Note 5 1, 2, 3 -55oC≤ TA≤ +125oC -30 -500 µA
Output Leakage Current IOVO = GND or VCC
VCC = 5.5V,
Pins 1, 7-8, 10-28, 32-34
1, 2, 3 -55oC≤ TA≤ +125oC -10 10 µA
Active Power Supply
Current ICCOP 80C286-10/883, Note 4 1, 2, 3 -55oC≤ TA≤ +125oC - 185 mA
80C286-12/883, Note 4 - 220 mA
Standby Power
Supply Current ICCSB VCC = 5.5V, Note 3 1, 2, 3 -55oC≤ TA≤ +125oC- 5 mA
NOTES:
2. IBHL should be measured after lowering VIN to GND and then raising to 1.0V on the following pins: 36-51, 66, 67.
3. IBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.
4. ICCSB should be tested with the clock stopped in phase two of the processor clock cycle. VIN = VCC or GND, VCC = 5.5V, outputs unloaded.
5. ICCOP measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. VIN = 2.4V or 0.4V, VCC = 5.5V, outputsunloaded.
6. ISH should be measured after raising VIN to VCC and then lowering to 0V on pins 53 and 54.
3-131
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
80C286/883
UNITS
10MHz 12.5MHz
MIN MAX MIN MAX
System Clock
(CLK) Period 1V
CC = 4.5V and 5.5V 9, 10, 11 -55 oC≤TA≤ +125oC 50 - 40 - ns
System Clock
(CLK) Low Time 2V
CC = 4.5V and 5.5V
at 1.0V 9, 10, 11 -55oC≤TA≤+125oC 12 - 11 - ns
System Clock (CLK)
High Time 3V
CC = 4.5V and 5.5V
at 3.6V 9, 10, 11 -55oC≤TA≤ +125oC 16 - 13 - ns
Asynchronous Inputs
SETUP Time
(Note 1)
4V
CC = 4.5V
and 5.5V 9, 10, 11 -55oC≤TA≤ +125oC 20 - 15 - ns
Asynchronous Inputs
HOLD Time
(Note 1)
5V
CC = 4.5V
and 5.5V 9, 10, 11 -55oC≤ T A≤ +125oC 20 - 15 - ns
RESET SETUP Time 6 VCC = 4.5V
and 5.5V 9, 10, 11 -55oC≤ T A≤ +125oC 19 - 10 - ns
RESET HOLD Time 7 VCC = 4.5V
and 5.5V 9, 10, 11 -55oC≤ T A≤ +125oC0 - 0 - ns
Read Data
SETUP Time 8V
CC = 4.5V
and 5.5V 9, 10, 11 -55oC≤ T A≤ +125oC8 - 5 - ns
Read Data
HOLD Time 9V
CC = 4.5V
and 5.5V 9, 10, 11 -55oC≤ T A≤ +125oC4 - 4 - ns
READY SETUP Time 10 VCC = 4.5V
and 5.5V 9, 10, 11 -55oC≤ T A≤ +125oC 26 - 20 - ns
READY HOLD Time 11 VCC = 4.5V
and 5.5V 9, 10, 11 -55oC≤TA≤ +125oC 25 - 20 - ns
Status/PEACK Active
Delay, (Note 4) 12A VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
9, 10, 11 -55oC≤ T A≤ +125oC 1 22 1 21 ns
Status/PEACK
Inactive Delay
(Note 3)
12B VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
9, 10, 11 -55oC≤ T A≤ +125oC 1 30 1 24 ns
Address Valid
Delay (Note 2) 13 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
9, 10, 11 -55oC≤ T A≤ +125oC 1 35 1 32 ns
Write Data
Valid Delay, (Note 2) 14 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
9, 10, 11 -55oC≤ T A≤ +125oC 0 40 0 31 ns
3-132
80C286/883
HLDA Valid Delay
(Note 5) 15 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
9, 10, 11 -55oC≤ T A≤ +125oC 0 47 0 25 ns
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD , PEREQ, ERROR, and BUSY. This specification is given only f or testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
80C286/883
UNITS
10MHz 12.5MHz
MIN MAX MIN MAX
CLK Input Capacitance CCLK FREQ = 1MHz 5 TA = +25oC - 10 - 10 pF
Other Input Capacitance CIN FREQ = 1MH 5 TA = +25oC - 10 - 10 pF
I/O Capacitance CI/O FREQ = 1MH 5 TA = +25oC - 10 - 10 pF
Address/Status/Data
Float Delay 15 1, 3, 4, 5 -55oC≤ TA≤ +125oC 0 47 0 32 ns
Address Valid to Status
SETUP Time 19 IL = |2.0mA| 1, 2, 5 -55oC≤ TA≤ +125oC 27 - 20 - ns
NOTES:
1. Output Load: CL = 100pF.
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. IL = -6mA (VOH to Float), IL = 8mA (VOL to Float).
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS METHOD SUBGROUPS
Initial Test 100%/5004 -
Interim Test 100%/5004 1, 7, 9
PDA 100% 1
Final Test 100% 2, 3, 8A, 8B, 10, 11
Group A - 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group C & D Samples/5005 1, 7, 9
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
80C286/883
UNITS
10MHz 12.5MHz
MIN MAX MIN MAX
3-133
80C286/883
AC Electrical Specifications 82C284 and 82C288 Timing Specifications Are Given For Reference Only, And No Guarantee is
Implied.
82C284 Timing
SYMBOL PARAMETER
10MHz 12.5MHz
UNIT TEST CONDITIONMIN MAX MIN MAX
TIMING REQUIREMENTS
11 SRDY/SRDYEN Setup Time 15 - 15 - ns
12 SRDY/SRDYEN Hold Time 2 - 2 - ns
13 ARDY/ARDYEN Setup Time 5 - 5 - ns (Note 1)
14 ARDY/ARDYEN Hold Time 30 - 25 - ns (Note 1)
TIMING RESPONSES
19 PCLK Delay 0 20 0 16 ns CL = 75pF, IOL = 5mA,
IOH = -1mA
NOTE:
1. These times are given for testing purposes to ensure a predetermined action.
82C288 Timing
SYMBOL PARAMETER
10MHz 12.5MHz
UNIT TEST CONDITIONMIN MAX MIN MAX
TIMING REQUIREMENTS
12 CMDLY Setup Time 15 - 15 - ns
13 CMDLY Hold Time 1 - 1 - ns
TIMING RESPONSES
16 ALE Active Delay 1 16 1 16 ns
17 ALE Inactive Delay - 19 - 19 ns
19 DT/R Read Active Delay - 23 - 23 ns CL = 150pF
20 DEN Read Active Delay 0 21 0 21 ns IOL = 16mA Max
21 DEN Read Inactive Delay 3 23 3 21 ns IOH = -1mA Max
22 DT/R Read Inactive Delay 5 24 5 18 ns
23 DEN Write Active Delay - 23 - 23 ns
24 DEN Write Inactive Delay 3 23 3 23 ns
29 Command Active Delay from CLK 3 21 3 21 ns CL = 300pF
30 Command Inactive Delay from CLK 3 20 3 20 ns IOL = 32mA Max
3-134
80C286/883
AC Specifications
NOTE:
1. For AC testing, input rise and fall times are driven at 1ns per volt.
FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT
CLK INPUT
4.0V
0.45V
3.6V 3.6V
1.0V1.0V
1.0V 1.0V
3.6V3.6V
4.0V
2.0V
0.8V 0.8V
2.0V
0.8V
2.0V
tDELAY (MAX)
tDELAY (MIN)
tHOLD
tSETUP
CLK INPUT
0.45V
2.4V
OTHER
0.4V
DEVICE
DEVICE
INPUT
OUTPUT
3-135
80C286/883
Waveforms
NOTES:
1. The modified timing is due to the CMDLY signal being active.
2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.
FIGURE 2. MAJOR CYCLE TIMING
3 1
2 12A 12B
φ2φ2φ1φ2φ1φ2φ1φ2φ1φ2φ1
CLK
VOL
VOH
TITSTCTSTCTC
S1 • S0
19
13
19
13
M/IO,
A23 - A0
BHE, LOCK
VALID ADDRESS VALID ADDRESS VALID IF TS
13 13
VALID CONTROL VALID CONTROL
VALID WRITE DATA
9
814
11
10
15
D15 - D0
11
10
11
12
19 14
13
1919 20
16 17
12
13
13
12 12 13
29 30
(SEE NOTE 1)
29 30
19
20 21 22
23
24
READ
(TI OR TS)
READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES
WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE
READY
SRDY +
ARDY +
PCLK
ALF
CMDLY
MWTC
MRDC
DT/R
ARDYEN
SRDYEN
COD INTA
80C286/88382C284 (SEE NOTE 2)82C288 (SEE NOTE 2)
BUS CYCLE TYPE
DEN
VALID READ DATA
3-136
80C286/883
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK ma y not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat φ1 of a processor cycle.
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
NOTES:
1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
2. The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC.
3. The 80C286/883 puts its status pins in a high impedance logic one state during TH.
4. For HOLD request set up to HLDA, refer to Figure 8.
5. BHE and LOCK are driven at this time but will not become valid until TS.
6. The data bus will remain in a high impedance state if a read cycle is performed.
FIGURE 5. EXITING AND ENTERING HOLD
Waveforms
(Continued)
φ2
BUS CYCLE TYPE VCH
VCL
CLK
φ1
PCLK
(SEE NOTE 1)
TX
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
ERROR, BUSY
(SEE NOTE 2)
19 19
45
5
4
φ2
7
RESET
φ1φ1φ2
6
VCH
VCL
CLK
(SEE NOTE 1)
TX
VCH
CLK
VCL
RESET
TXφ2φ2φ1
76(SEE NOTE 1)
16
φ2φ1φ2φ1φ2φ1φ2φ1
THTITH
THOR TI
BUS CYCLE TYPE
VCH
CLK
HILDA
VCL 16
(SEE NOTE 4)
12A (NOTE 3) 15 (SEE NOTE 3)
12B
15
IF TS
S1 • S0
PEACK
BHE, LOCK
A23 - A0,
M/IO,
COD/INTA
(SEE NOTE 5) 13
(SEE NOTE 1)
15
VALID
14
(SEE NOTE 6)
(SEE NOTE 2)
15
VALID IF WRITE
D15 - D0
PCLK
80C286/88380C284
IF NPX TRANSFER
3-137
80C286/883
NOTES:
1. PEACK alw ays goes active during the first bus operation of a processor extension data operand transfer sequence . The first bus operation
will be either a memory read at operand address or I/O read at port address 00FA(H).
2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x - 12AMAX -(4)MIN
The actual, configuration dependent, maximum time is: 3 x - 12AMAX - (4)MIN +N x 2 x (1). N is the number of extra TC states added
to either the first or second bus operation of the processor extension data operand transfer sequence.
FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
NOTES:
1. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
3. The data bus is only guaranteed to be in a high impedance state at the time shown.
FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET
Waveforms
(Continued)
1
12A
φ2
CLK
φ1φ2φ2φ1φ2φ1φ1φ2
TITSTCTSTCTI
VCH
VCL
CLK
S1 • S0
PEACK
M/IO,
A23 -A0
COD INTA
PEREQ
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O
PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
12B
5
4
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
BUS CYCLE TYPE
(SEE NOTE 1)
(SEE NO TE 2)
I/0 READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
1
1
12B
TX
S1 • S0
BUS CYCLE TYPE
φ2φ2φ2φ2φ2φ1φ1φ1φ1TXTXTI
CLK
VCH
VCL 676
(SEE NOTE 1)
PEACK
A23 - A0
BHE
M/IO
COD/INTA
AT LEAST
16 CLK PERIODS
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
13
13
13
15 (SEE NOTE 3)
LOCK
DATA
HILDA
16
(SEE NOTE 2)
RESET
3-138
80C286/883
NOTES:
1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
2. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in φ2 of TC.
3. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to ex-
ternal HOLD. The float starts in φ1 of TC.
4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
Waveforms
(Continued)
VALID
VALID
VALID
(SEE NOTE 3)
(SEE NOTE 2)
(SEE NOTE 1)
(SEE NOTE 6)
(SEE NOTE 5)
NOT READY NOT READY
NOT READY NOT READY
(SEE NOTE 7)
READY
(SEE NOTE 7)DELAY ENABLE
VOH
THφ2φ1
THφ2φ1
THφ2φ1
BUS HOLD ACKNOWLEDGE
TSφ2φ1
TCφ2φ1
TCφ2φ1
TCφ2φ1
TIφ2φ1
THφ2φ1
BUS HOLD
ACKNOWLEDGE
WRITE CYCLE
BUS CYCLE TYPE
CLK
HOLD (SEE NOTE 4)
HLDA
S1 •S0
A23 - A0
M/IO,
D15 - D0
SRDY +
ARDY +
CMDLY
MWTC
DT/R
ALE
COD/INTA
BHE, LOCK
SRDYEN
ARDYEN
DEN
80C28680C28480C288
TS - STATUS CYCLE
CT - COMMAND CYCLE
(SEE NOTE 1)
3-139
80C286/883
Burn-In Circuit
NOTES:
8. Supply Voltage: VDD = 5.5V, VSS = 0.0V.
9. Input Voltage Limits: VIL (Maximum) = 0.8V, VIH (Minimum) = 2.0V
10. Component Values: RC = 1kΩ±5%, RI = 10kΩ±5%, RO = Two Series 2.7kΩ±5%
11. Capacitor Values: C1 = 0.1 Microfarads
12. Oven Type and Frequency Requirements: Wakefield Oven Board f0 = 100kHz, f3 = 12.5kHz,
f4 = 6.25kHz, f5 = 3.125kHz, f7 = 781.25Hz.
13. Special Requirements: (a) ELECTROSTATIC DISCHARGE SENSITIVE. Proper Precautions Must be Used When Handling Units. (b) All Power Supplies
Must be at Zero Volts When the Boards are Inserted into the Ovens. (c) When Powering Up, the Inputs Must be Held Below the VDD Voltage. (d) If an
Excessive Current is Indicated at Final Inspection, Chec k to See if a Part is Inserted Backw ards or is Latched Up.
RI RI RI RIRI RI RI RI RI RI RI RI RIRI RI RI
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 3536 34
VSS
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
RI
RI
RI
RI
RI
RI
RI
RI
RO
RO
RO
RO
RO
RO
GND
5.5V
C1
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RC
RI
F0
F7
VSS
VDD
VDD
F5
F4
F3
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
80C286/883 PGA
3-140
80C286/883
Die Characteristics
DIE DIMENSIONS:
286 x 283 x 19 ±1mils
METALLIZATION:
Type: Si-Al
Thickness: 8kÅ
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ
WORST CASE CURRENT DENSITY: 2 X 105A/cm2
LEAD TEMPERATURE: (10s Soldering): ≤300oC
Metallization Mask Layout
80C286/883
