PHK13N03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 17 March 2009 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industria l applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Simple gate drive required due to low
gate charge
Suitable for high frequency
applicat ion s du e to fast swit ch ing
characteristics
1.3 Applications
DC-to-DC convertors
Lithium-ion batt er y applica tio n s
Notebook computers
Porta ble equipment
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - - 30 V
IDdrain current Tsp =25°C; V
GS =10V;
see Figure 1; see Fi gure 3 - - 13.8 A
Ptot total power
dissipation Tsp =25°C; see Figure 2 --6.25W
Dynamic characteristics
QGD gate-drain charge VGS =5V; I
D=8A;
VDS =15V; T
j=25°C;
see Figure 11
-3.9-nC
Static characteristics
RDSon drain-source
on-state resistance VGS =10V; I
D=8A;
Tj= 25 °C; see Figure 9;
see Figure 10
- 1720mΩ
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 2 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
2. Pinning information
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1S source
SOT96-1
(SO8)
2S source
3S source
4G gate
5D drain
6D drain
7D drain
8D drain
4
5
1
8
S
D
G
mbb076
Table 3. Orderi ng informatio n
Type number Package
Name Description Version
PHK13N03LT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - 30 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤150 °C; RGS =20kΩ-30V
VGS gate-source voltage -20 20 V
IDdrain current Tsp =25°C; V
GS = 10 V; see Figure 1; see Figure 3 -13.8A
Tsp = 100 °C; VGS =10V; see Figure 1 -8.7A
IDM peak drain current Tsp =25°C; t
p≤10 µs; pulsed; see Figure 3 -55A
Ptot total power dissipation Tsp =25°C; see Figure 2 -6.25W
Tstg storage temperature -55 150 °C
Tjjunction temperature -55 150 °C
Source-drain diode
ISsource current Tsp =25°C - 5.7 A
ISM peak source current Tsp =25°C; t
p≤10 µs; pulsed - 55 A
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 3 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
Fig 1. Normalized continuous drain current as a
function of solde r point temperature Fig 2. Normalized total power dissipation as a
function of solder point temperature
Fig 3. Safe operating area; continuous and peak drain curren ts as a function of drain-source voltage
Tsp (°C)
0 20015050 100
03aa25
40
80
120
Ider
(%)
0
Tsp (°C)
0 20015050 100
03aa17
40
80
120
Pder
(%)
0
003aaa487
VDS (V)
10−1102
101
10
1
102
ID
(A)
10−1
Limit RDSon = VDS / ID
tp = 10 μs
1 ms
10 ms
100 ms
DC
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 4 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-sp) thermal resistance from
junction to solder point see Figure 4 --20K/W
Rth(j-a) thermal resistance from
junction to ambient minimum footprint; moun ted on a
printed-circuit board -70-K/W
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration
003aaa324
10−4
tp (s)
11010−1
10−310−2
10
1
102
Zth(j-sp)
(K/W)
10−1
δ = 0.5
0.2
0.1
0.05
0.02
single pulse
tp
tp
T
P
t
T
δ =
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 5 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=250µA; V
GS =0V; T
j=25°C 30 - - V
ID=250µA; V
GS =0V; T
j=-55°C 27 - - V
VGS(th) gate-source threshold
voltage ID=250µA; V
DS = VGS; Tj= 150 °C;
see Figure 8 0.5 - - V
ID=250µA; V
DS = VGS; Tj=-55°C;
see Figure 8 --2.2V
ID=250µA; V
DS = VGS; Tj=25°C;
see Figure 8 11.52V
IDSS drain leakage current VDS =24V; V
GS =0V; T
j=25°C --1µA
VDS =24V; V
GS =0V; T
j= 100 °C - - 5 µA
IGSS gate leakage current VGS =20V; V
DS =0V; T
j= 25 °C - - 100 nA
VGS =-20V; V
DS =0V; T
j= 25 °C - - 100 nA
RDSon drain-source on-state
resistance VGS =4.5V; I
D=7A; T
j=25°C;
see Figure 9 -2126mΩ
VGS =10V; I
D=8A; T
j=150°C;
see Figure 10 ; see Figure 9 --33mΩ
VGS =10V; I
D=8A; T
j=25°C;
see Figure 9; see Figure 10 -1720mΩ
Dynamic characteristi cs
QG(tot) total gate charge ID=8A; V
DS =15V; V
GS =5V;
Tj=25°C; see Figure 11 - 10.7 - nC
QGS gate-source charge - 2.7 - nC
QGD gate-drain charge - 3.9 - nC
Ciss input capacitance VDS =15V; V
GS = 0 V; f = 1 MHz;
Tj=25°C; see Figure 12 - 752 - pF
Coss output capacitance - 200 - pF
Crss reverse transfer
capacitance - 130 - pF
td(on) turn-on delay time VDS =15V; R
L=10Ω; VGS =10V;
RG(ext) =6Ω; Tj=25°C; I
D=1.5A -6-ns
trrise time VDS =15V; R
L=10Ω; VGS =10V;
RG(ext) =6Ω; ID= 1.5 A; Tj=25°C -7-ns
td(off) turn-off delay time VDS =15V; R
L=10Ω; VGS =10V;
RG(ext) =6Ω; Tj=25°C; I
D=1.5A -23-ns
tffall time - 11 - ns
Source-drain diode
VSD source-drain voltage IS=7A; V
GS =0V; T
j=25°C;
see Figure 13 - 0.86 1.1 V
trr reverse recovery time IS=7A; dI
S/dt = -100 A/µs; VGS =0V;
VDS =30V; T
j=25°C -25-ns
Qrrecovered charge - 5 - nC
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 6 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a
function of gate-source vo ltage; typical values
Fig 7. Sub-threshold drain current as a function of
gate-source voltage Fig 8. Gate-source threshold voltage as a function of
junction temperature
VDS (V)
010.80.4 0.60.2
003aaa325
4
6
2
8
10
ID
(A)
0
10 V 5 V 3 V VGS (V) =
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
003aaa326
VGS (V)
0321
4
6
2
8
10
ID
(A)
0
VDS > ID × RDSon
Tj = 150 °C 25 °C
003aaa426
VGS (V)
0321
10−4
10−5
10−2
10−3
10−1
ID
(A)
10−6
min typ max
03aa33
0
0.5
1
1.5
2
2.5
-60 0 60 120 180
Tj (°C)
VGS(th)
(V)
max
typ
min
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 7 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
Fig 9. Drain-source on-state resistance as a function
of drain current; typical values Fig 10. Normalized drain-source on-state resistance
factor as a functio n of junction temperature
Fig 11. Gate-source voltage as a function of gate
charge; typical values Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
ID (A)
0108462
003aaa327
40
20
60
80
RDSon
(mΩ)
0
VGS (V) =
2.5 V 2.6 V 2.8 V
3 V
4 V
5 V
10 V
03aa27
0
0.5
1
1.5
2
-60 0 60 120 180
Tj (°C)
a
003aaa330
QG (nC)
015105
2
3
1
4
5
VGS
(V)
0
VDS (V)
10−1102101
003aaa328
103
102
104
C
(pF)
10
Ciss
Coss
Crss
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 8 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
Fig 13. Source current as a function of source-drain voltage; typica l values
VSD (V)
0.2 10.80.4 0.6
003aaa329
2
3
1
4
5
IS
(A)
0
150 °CTj = 25 °C
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 9 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
7. Package outline
Fig 14. Package outline SOT96-1 (SO8)
UNIT A
max. A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
1.0
0.4
SOT96-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15 0.05 0.244
0.228
0.028
0.024
0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
99-12-27
03-02-18
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 10 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PHK13N03LT_2 20090317 Product data sheet - PHK13N03LT-01
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate .
PHK13N03LT -01 20030623 Product data sheet - -
© Nexperia B.V. 2017. All rights reserved
PHK13N03LT_2
Product data sheet Rev. 02 — 17 March 2009 11 of 12
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nexperia.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Nexperia does not give any representations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environment al
damage. Nexperia accepts no liability for inclusion and/or use of
Nexperia products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Rati ngs System of I EC 60134) may cause perman ent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — Nexperia products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nexperia.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by Nexperia. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the it em(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
10. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Document status [1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for prod uct development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
Nexperia PHK13N03LT
N-channel TrenchMOS logic level FET
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
10 Contact information. . . . . . . . . . . . . . . . . . . . . .11
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
17 March 2009
