AN-080E Rev.1.0
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
Fuji Power MOSFET
PowerMOSFET
Application Note
’11-4
Fuji Electric Co.,Ltd.
AN-080E Rev.1.0
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
1. This Catalog contains the product specifications, characteristics, data, materials, and structures as of April 2011.
The contents are subject to change without notice for specification changes or other reasons. When using a product listed in this
Catalog, be sure to obtain the latest specifications.
2. All applications described in this Catalog exemplify the use of Fuji's products for your reference only. No right or license, either
express or implied, under any patent, copyright, trade secret or other intellectual property right owned by Fuji Electric Co.,
Ltd.is (or shall be deemed) granted. Fuji Electric Co., Ltd. makes no representation or warranty, whether express or implied,
relating to the infringement or alleged infringement of other's intellectual property rights which may arise from the use of the
applications described herein.
3. Although Fuji Electric Co., Ltd. is enhancing product quality and reliability, a small percentage of semiconductor products
may become faulty. When using Fuji Electric semiconductor products in your equipment, you are requested to take adequate safety
measures to prevent the equipment from causing a physical injury, fire, or other problem if any of the product become faulty. It is
recommended to make your design fail-safe, flame retardant, and free of malfunction.
4. The products introduced in this Catalog are intended for use in the following electronic and electrical equipment which has normal
reliability requirements.
• Computers • OA equipment • Communications equipment (terminal devices) • Measurement equipment
• Machine tools • Audiovisual equipment • Electrical home appliances • Personal equipment • Industrial robots etc.
5. If you need to use a product in this Catalog for equipment requiring higher reliability than normal, such as for the equipment listed
below, it is imperative to contact Fuji Electric Systems Co., Ltd. to obtain prior approval. When using these products for such
equipment, take adequate measures such as a backup system to prevent the equipment from malfunctioning even if a Fuji's product
incorporated in the equipment becomes faulty.
• Transportation equipment (mounted on cars and ships) • Trunk communications equipment
• Traffic-signal control equipment • Gas leakage detectors with an auto-shut-off feature
• Emergency equipment for responding to disasters and anti-burglary devices • Safety devices
• Medical equipment
6. Do not use products in this Catalog for the equipment requiring strict reliability such as the following and equivalents to strategic
equipment (without limitation).
• Space equipment • Aeronautic equipment • Nuclear control equipment
• Submarine repeater equipment
7. Copyright ©1996-2008 by Fuji Electric Systems Co., Ltd. All rights reserved.
No part of this Catalog may be reproduced in any form or by any means without the express permission of Fuji Electric Co.,
Ltd.
8. If you have any question about any portion in this Catalog, ask Fuji Electric Co., Ltd. or its sales agents before using the product.
Neither Fuji Electric Co., Ltd. nor its agents shall be liable for any injury caused by any use of the products not in accordance
with instructions set forth herein.
WARNING
AN-080E Rev.1.0
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Contents
1. Structure and features of the device ...... 4
2. Terms and characteristics ...... 7
3. Circuit design and device characteristics ...... 11
4. Circuit design and mechanism of breakdown ...... 19
5. Thermal design ...... 25
6. Cautions in mounting and handling ...... 31
7. Application to switching power supply ...... 36
Note:
• The contents of this document are subject to change without prior notice because of product improvement, etc.
• The applications and the parts constants listed in this document is for assisting the design, and does not take the
variation of parts and operating conditions into consideration. When integrating our products into your design, take the
variation of these parts and operating conditions into consideration.
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1. Structure and features of the device
1-1. Structure and features of the device
Just as the name suggests, a Power MOSFET is a semiconductor device in a metal-oxide semiconductor
(MOS) structure operating due to the field effect. Of the two types of Power MOSFET (vertical and horizontal
types), the vertical type has a feature that current is fed over the entire chip and the resistance per unit chip
area (ON resistance, which is the most important characteristics of the MOSFET) can be minimized.
Compared with conventional bipolar transistors, the Power MOSFET has the following advantages:
1) Since it is a voltage-controlled device, drive power is low.
2) Since it is a unipolar device, high-speed switching is allowed.
3) Since the temperature coefficient of the current is negative, no secondary breakdown occurs, which
facilitates parallel operation.
Figure 1-2 shows the cross-sectional view of a SuperFAP series chip, whereas Fig. 1-3 shows that of a
conventional chip. The SuperFAP series feature the following:
1) Reduced turnoff power dissipation
2) Reduced gate charge
3) Low RonA
The SuperFAP series contributes to the reduction of power dissipation, improvement of efficiency, and
downsizing.
Fig.1-1 Basic structure of the Power MOSFET
Drain
SourceGate
CGD
Drain
SourceGate
CGD
Gate Source
Drain
SourceGate
CGD
Drain
SourceGate
CGD
Drain
Gate Source
Drain
Fig.1-2 Cross-sectional view of a SuperFAP series chip Fig.1-3 Cross-sectional view of a conventional chip
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1-2. Power MOSFET of Fuji Electric Systems Co., Ltd.
Since 1982, Fuji Electric Systems Co., Ltd. has been importing Power MOSFET elements from Siemens AG in
the Federal Republic of Germany, assembling them, and providing the assemblies to the market. Fuji has also
established an integrated production system ranging from wafer process to assembly through technical
partnership with Siemens entered in 1986, and started mass-producing Power MOSFETs. We then focused on
improving the properties to achieve ultrahigh-speed switching and high avalanche capacity, and are now
providing our products mainly in the field of switching power supplies. Figure 1-4 shows the Power MOSFET
series developed by us.
High-voltage Power MOSFET Low-voltage Power MOSFET
1980
1990
1995
2000
2010
Fig.1-4 Fuji Power MOSFET series
SIPMOS
(F-0)
F-Ⅰ
F-Ⅱ
FAP-Ⅱ
FAP-ⅡA
FAP-ⅡS
series
SuperFAP-G
series
SuperFAP-E3
series
Super
Junction
MOSFET
F-Ⅰ
F-Ⅲ
FAP-Ⅲ
FAP-ⅢA
series
FAP-ⅢB
series
SuperFAP-G
series
Trench
FT-1
series
Trench
FT-2
series
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1-3. Code symbols of Fuji Power MOSFET
2SK 3686 -01
(1)Code of Device type
2SK: N-Channnel MOSFET
2SJ: P-Channnel MOSFET
(1) (2) (3)
(2)JEITA registration number
Serial number
(3)Avalanche Proof
-01: Avalanche Proven product
FM V06 N60 ES
(1)Code of Device type
F: Fuji Electric
M: MOSFET
(1) (2) (3) (4) (5) (6)
(2)Code of Package Outline
(3)Current rating range
Drain current I
D
[A]
(4)Code of Polarity
N: N-Channnel MOSFET
P: P-Channnel MOSFET
(5)Drain-Source Voltage rating range
1/10 of drain-source withstand voltage V
DSS
[V]
(6)Code of Series category
Code Series
Blank Conventional series product
GSuperFAP-G
GF SuperFAP-G (FRED)
T2 Trench MOSFET (2G)
ESuperFAP-E3
ES Supe rFAP-E3S
S1 SJ-MOSFET (1G)
Code Package
A TO-220F
BD2-Pack
C T-Pack(S)
DK-Pack(S)
H TO-3P(Q)
IT-Pack(L)
KTO-3PL
LTFP
PTO-220AB
RTO-3PF
UK-Pack(L)
V TO-220F(SLS)
WTO-247
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2. Terms and characteristics
2-1. Description of terms (Absolute maximum rating, electrical characteristics)
2-1-1. Absolute maximum rating
(Reference example) Excerpt from the specification of the FMV06N60ES
Term Symbol Definition and description
Drain-Source Voltage VDSS Maximum voltage value permitted between the drain and the source in a state where the
gate and the source are short-circuited.
Continuous Drain current ID
Maximum DC current value permitted to the drain terminal determined based on the
maximum power dissipation and the maximum ON resistance (Tch=150deg.) .
(including forward current rating of parasitic diodes)
Pulsed Drain Current ID pulse
Maximum peak value of the drain current permitted at the time of pulse operation at pulse
width and duty ratio specified in the “area of safe operation” of the characteristic curve.
Specified as 4 times the continuous drain current.
Gate-Source Voltage VGS Maximum voltage value permitted between the gate and the source. Maximum permitted
voltage value of the gate oxide film.
Repetitive and Non-Repetitive
Maximum Avalanche Current IAR Maximum permitted current at the occurrence of an avalanche. Forward current value of
the avalanche parasitic diode.
Maximum Avalanche Energy
Non-Repetitive
Repetitive
EAS
EAR
Maximum permissible power at the occurrence of an avalanche.
Peak Diode Recovery dV/dt dv/dt Rate of change of the maximum permissible D-S voltage during reverse recovery
operation of the parasitic diode
Peak Diode Recovery –di/dt -di/dt Rate of change of the maximum permissible D-S current during reverse recovery
operation of the parasitic diode
Maximum Power Dissipation
Independent use state
(Ta=25deg.)
Infinite heat dissipated state
(Tc=25deg.)
PD Maximum power dissipation value permitted to the MOSFET.
Channel temperature Tch Chip temperature range in which MOSFET operation is permitted
Storage temperature Tstg Temperature range allowing storage or transportation of the MOSFET without being
subjected to electric load
Isolation Voltage VISO Applicable to full-mold packages only
* Derating is required for some absolute maximum rating items depending on conditions such as case temperature.
5.Absolute Maximum Ratings at Tc=25C (unless otherwise specified)
Description Symbol Characteristics Unit Remarks
V
DS
600 V
V
DSX
600 V V
GS
=-30V
Continuous Drain Current I
D
6A
Pulsed Drain Current I
DP
24 A
Gate-Source Voltage V
GS
30 V
Repetitive and Non-Repetitive
Maximum Avalanche Current
Non-Repetitive
Maximum Avalanche Energy
Repetitive
Maximum Avalanche Energy
Peak Diode Recovery dV/dt dV/dt kV/μs
Peak Diode Recovery -di/dt -di/dt A/μs
Ta=25℃
37 Tc=25℃
Operating and Storage T
ch
150 ℃
Temperature range T
stg
-55 to +150 ℃
Isolation Voltage V
ISO
2 kVrms t=60sec,f=60Hz
Drain-Source Voltage
3.8 Note *4
Note *2
E
AR
3.7 mJ Note *3
I
AR
6 A Note *1
E
AS
313.7 mJ
100 Note *5
Maximum Power Dissipation P
D
2.16 W
Note *1 : Tch
150℃, See Fig.1 and Fig.2
Note *2 : Stating Tch=25℃, I
AS
=2.4A, L=99.8mH, Vcc=60V, R
G
=50Ω, See Fig.1 and Fig.2
E
AS
limited by maximum channel temperature and avalanche current.
See to 'Avalanche Energy' graph of page 9/15.
Note *3 : Repetitive rating : Pulse width limited by maximum channel temperature.
See to the 'Transient Themal impeadance' graph of page 9/15.
Note *4 : I
F
-I
D
, -di/dt=100A/μs, VccBV
DSS
, Tch150℃.
Note *5 : I
F
-I
D
, dv/dt=3.8kV/μs, VccBV
DSS
, Tch150℃.
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2-1-2. Electrical characteristics (Static Ratings)
(Reference example) Excerpt from the specification of the FMV06N60ES
Term Symbol Definition and description
Drain-Source
Breakdown Voltage BVDSS
Breakdown voltage between the drain and the source (= Reverse voltage of the parasitic diode).
Voltage value between the drain and the source measured with specified drain current fed, in a
state where the gate and the source are short-circuited.
Gate Threshold Voltage VGS(th) Gate voltage value allowing the drain current to start flowing. Gate source voltage value
measured by feeding specified drain current and applying specified drain source voltage.
Zero Gate Voltage
Drain Current IDSS
Current between the drain and the source when the gate voltage is 0V (= Drain leakage current).
Drain current value measured by applying specified drain-source voltage in a state where the
gate and the source are short-circuited.
Gate-Source
Leakage Current IGSS Gate leakage current value measured by applying specified gate-source voltage in a state where
the drain and the source are short-circuited.
Drain-Source
On-State Resistance RDS(on) Resistance between the drain and the source measured by applying specified gate-source
voltage and feeding specified drain current.
* Unless otherwise specified, the above characteristics are exhibited when at Tc=25deg.
6.Electrical Characteristics at Tc=25C (unless otherwise specified)
Static Ratings
Description Symbol Conditions min. typ. max. Unit
Drain-Source I
D
=250μA
Breakdown Voltage BV
DSS
V
GS
=0V 600 - - V
Gate Threshold I
D
=250μA
Voltage V
GS
(th) V
DS
=V
GS
3.2 3.7 4.2 V
Zero Gate Voltage V
DS
=600V
V
GS
=0V T
ch
=25℃--25
Drain Current I
DSS
V
DS
=480V
V
GS
=0V T
ch
=125℃- - 250
Gate-Source V
GS
=
30V
Leakage Current I
GSS
V
DS
=0V - 10 100 nA
Drain-Source I
D
=3A
On-State Resistance R
DS
(on) V
GS
=10V - 1.03 1.20 Ω
μA
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2-1-3. Electrical characteristics (Dynamic Ratings)
(Reference example) Excerpt from the specification of the FMV06N60ES
Term Symbol Definition and description
Forward
Transconductance gfs
Rate of change of the drain current against the specified change in gate-source voltage measured
by applying specified drain-source voltage and feeding specified drain current. Represents the
degree of ease of feeding current. Equivalent to hFE of bipolar transistors.
Input Capacitance Ciss
Characteristic value of the parasitic capacitance measured between gate and source terminals at
specified gate-source and drain-source voltage and measuring frequency, in a state where the drain
and the source are alternately short-circuited.
Output Capacitance Coss
Characteristic value of the parasitic capacitance measured between drain and source terminals at
specified gate-source and drain-source voltage and measuring frequency, in a state where the gate
and the source are alternately short-circuited.
Reverse Transfer
Capacitance Crss
Characteristic value of the parasitic capacitance measured between the drain and the gate at
specified gate-source voltage and measuring frequency in a state where source terminal is
grounded.
Turn-On Delay Time td(on) Delay time of drain voltage with respect to the gate voltage measured between 10% value of
gate-source voltage and 90% value of drain-source voltage.
Turn-On Time tr Time required for drain voltage measured between 90% value and 10% value of the drain-source
voltage to decrease.
Turn-Off Delay Time td(off) Delay time of drain voltage with respect to the gate voltage measured between 90% value of
gate-source voltage and 10% value of drain-source voltage.
Turn-Off Time tf Time required for the drain voltage measured between 10% value and 90% value of drain-source
voltage to increase.
Total Gate Charge QG Gate charge required to turn on the MOSFET
Gate-Source Charge QGS
Gate-Drain Charge QGD
Gate-Drain
Crossover Charge QSW
Q
GS
VDS
V
GS
ID
Q
SW
V
GS(th)
V
GS(on)
Q
GD
Q
G
Dynamic Ratings
Description Symbol Conditions min. typ. max. Unit
Forward I
D
=3.0A
Transconductance g
fs
V
DS
=25V 2.5 5 - S
Input Capacitance Ciss V
DS
=25V - 950 1425
Output Capacitance Coss V
GS
=0V - 100 150
Reverse Transfer f=1MHz - 7.5 11 pF
Capacitance Crss
td(on) V
cc
=300V I
D
=3.0A - 29 43.5
Turn-On Time tr V
GS
=10V R
GS
=27Ω- 15 22.5
td(off) See Fig.3 and Fig.4 - 75 113 ns
Turn-Off Time tf - 16 24
Total Gate Charge Q
G
V
cc
=300V I
D
=6A - 31 46.5
Gate-Source Charge Q
GS
V
GS
=10V - 10.5 15.8 nC
Gate-Drain Charge Q
GD
See Fig.5 - 8 12
Gate-Drain
Crossover Charge Q
SW
- 4.5 6.75
ID starts to flow at VGS(th)
Mirror effect area
(=QGD)
Period where VDS and ID
are crossing (=QSW)
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2-1-4. Electrical characteristics (Parasitic diode)
(Reference example) Excerpt from the specification of the FMV06N60ES
Term Symbol Definition and description
Avalanche Capability IAV
Drain current value resistant to the switching of unclamped inductance. Since the current is fed
at the parasitic pn contact (parasitic diode structure), the avalanche capacity is displayed as
parasitic diode characteristics. Same as avalanche current at absolute maximum rating.
Diode Forward On-Voltage VSD
Forward voltage between the source and the drain measured by feeding forward current IF to the
parasitic diode at gate voltage VGS=0V and chip temperature Tch=25deg. When forward bias
voltage is applied to the gate terminal, current is fed to the parasitic diode and the MOSFET.
Consequently, this value decreases (Synchronous rectification).
Reverse Recovery Time trr
Reverse Recovery Charge Qrr
Time required for reverse recovery current of
parasitic diode to vanish under specified
measurement conditions. The same switching
characteristics as diodes for input bridge.
Slow compared with fast recovery diodes.
FRED type is high-speed parasitic diode.
2-1-5. Electrical characteristics (Thermal resistance)
(Reference example) Excerpt from the specification of the FMV06N60ES
Term Symbol Definition and description
Thermal Resistance
(Channel to Case) Rth(ch-c)
Thermal resistance from the channel to the surface of the case of the device (heat sink mounting
surface). The characteristics depend on package and chip sizes. The larger the chip size, the
smaller the thermal resistance. Use this value to calculate thermal resistance at the time of
mounting the heat sink.
Thermal Resistance
(Channel to Ambient) Rth(ch-a)
Thermal resistance from the channel to the ambient. Thermal resistance from the chip to the
ambient not affected by temperature increase measured in an independent state where heat
sink, etc. are not mounted. The characteristics become a unique value depending on packages.
Thermal resistance in a state mounted to specified substrate may be adopted for SDM
packages, etc.
Rev erse Diode
Description Symbol Conditions min. typ. max. Unit
Avalanche Capability L=6.39mH Tch=25℃
I
AV
See Fig.1 and Fig.2 6 - - A
Diode Forward I
F
=6A
On-Voltage V
SD
V
GS
=0V T
ch
=25℃- 0.90 1.35 V
Reverse Recovery I
F
=6A V
GS
=0V
Time trr -di/dt=100A/μs, Tch=25℃ -0.4-
μs
Reverse Recovery See Fig.6
Charge Qrr - 3.3 - μC
7.Thermal Resistance
Description Symbol min. typ. max. Unit
Channel to Case Rth(ch-c) 3.38 ℃/W
Channel to Ambient Rth(ch-a) 58.0 ℃/W
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3. Circuit design and device characteristics
3-1. Drain-Source Breakdown Voltage : BVDSS
The drain-source breakdown voltage BVDSS for guaranteeing rated voltage is specified in min. value. To ensure
safety in circuit operation with respect to this guaranteed value, a margin is allowed for actual value. However,
since the drain-source breakdown voltage and ON resistance is in a trade-off relation, by decreasing the
margin as far as possible, the ON resistance is decreased.
The dependence of the drain-source breakdown voltage on temperature exhibits positive temperature
dependence, and generally increases at the rate of 10%/100deg.
3-2. Gate Threshold Voltage : VGS(th)
The gate threshold voltage is the gate-source voltage VGS allowing the MOSFET to start feeding current.
Figure 3-1 is a temperature characteristics chart of the gate-source threshold voltage VGS(th). The gate-source
threshold voltage has different negative temperature coefficient (-5mV to -7mV/deg.) depending on products,
and decreases under the high-temperature condition, namely the actual operating conditions. Consequently,
when designing a drive circuit, it is necessary to check the temperature characteristics chart of the gate-source
threshold value listed in the data sheet to prevent malfunction from occurring due to external noise, etc.
Figure 3-2 is a chart demonstrating the transmission characteristics of the gate voltage VGS and the drain
current ID. In the MOSFET, the current fed by the gate voltage is limited. Consequently, when designing a drive
circuit, it is necessary to check the transmission characteristics chart of the gate voltage and drain voltage
listed in the data sheet to set a gate voltage that can feed sufficient drain current. If the gate voltage is set low
to minimize drive power dissipation, required drain current cannot be fed, and consequently required output
cannot be obtained. In addition, increase in ON dissipation may result in a breakdown.
3-3. Zero Gate Voltage Drain Current (Drain Leakage Current) : IDSS
The zero gate voltage drain current is a leakage current between the drain and the source. The drain leakage
current has positive temperature characteristics. The dissipation from IDSS is expressed by P(IDSS)=VDS IDSS
when the MOSFET remains OFF. However, within normal operating range, the value is negligibly small
compared with the ON dissipation (dissipation generated by RDS(on)).
012345678910
0.1
1
10
100
ID[A]
VGS[V]
Typical Transfer Characteristic
ID=f(VGS):80 s pulse test,VDS=25V,Tch=25 C
Fig.3-1 VGS
(
th
)
temperature characteristics chart Fig.3-2 VGS-ID transmission characteristics chart
When drain current ID=5A is fed,
g
ate volta
g
e VGS=5.9V or hi
g
her is re
q
uired.
-50 -25 0 25 50 75 100 125 150
0
1
2
3
4
5
6
7
8
typ.
max.
min.
Gate Threshold Voltage vs. Tch
VGS(th)=f(Tch):VDS=VGS,ID=250
A
VGS(th) [V]
Tch [
C]
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3-4. Maximum Power Dissipation : PD
Figure 3-3 is a chart showing the reduction curve of the maximum power dissipation PD at the case
temperature Tc under the condition of absolute maximum rating of the channel temperature Tch=150deg.
In designing, it is essential not to allow the power dissipation PD to be exceeded at the assumed maximum
case temperature Tc.
Note that the power dissipation PD listed in the brochure and the data sheet is the value calculated from the
heat resistance between the channel and the case Rth(ch-c) in a state where the device is mounted to an infinite
radiator plate.
The power dissipation in actual operation is calculated from the thermal resistance and ambient temperature,
with the thermal resistance of the heat sink to be mounted and contact thermal resistance taken into
consideration.
Power dissipation on the data sheet:
Infinite heat dissipated state
Power dissipation in actual operation:
(Example) State in which a heat sink is mounted
Rth(c-f) : Contact thermal resistance with the heat sink
Rth(f-a) : Thermal resistance of the heat sink
Ta : Ambient temperature
Tc : Case temperature
3-5. Thermal Resistance (Channel to Case) : Rth(ch-c)
The thermal resistance value listed in the brochure or the data sheet is the thermal resistance in steady state.
When preparing thermal design of devices that perform pulse operation such as switching power supply, or
calculating the temperature increase due to pulse surge, it is necessary to find the thermal resistance at any
given time from the transient thermal impedance characteristics chart (Fig.3-4) listed in the data sheet, or to
use a calculated value.
][
)(
(max) W
cchRth
TcTch
P
D
][
)()()(
(max) W
afRthfcRthcchRth
TaTch
P
D
Fig.3-3 Power dissipation PD temperature
characteristics chart
0 25 50 75 100 125 150
0
5
10
15
20
25
30
35
40
Allowable Power Dissipation
PD=f(Tc)
PD [W]
Tc [
C]
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
-3
10
-2
10
-1
10
0
10
1
Maximum Transient Thermal Impedance
Zth(ch-c)=f(t):D=0
Zth(ch-c) [
C/W]
t [sec]
Transient region Constant region
Fig.3-4 Transient resistance characteristics chart
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3-6. Area of safe operation (ASO)
Figure 3-5 shows the area of safe operation of the FMV06N60ES.
The area of safe operation, which is used to judge the feasibility of use of a Power MOSFET in an application
circuit, is divided into the following 4 areas, each of which is restricted by different conditions.
Area [1]: Area restricted by drain current ID, and pulse drain current IDP
Area [2]: Area (1) restricted by the maximum power dissipation PD
Area [3]: Area (2) restricted by the maximum power dissipation PD (at t=1ms to DC only)
Normally, the ASO breakdown tolerance is determined by power dissipation and thermal resistance, and
when t=1ms or longer, the breakdown tolerance decreases in high-voltage region due to local current
crowding phenomenon. Consequently, a phenomenon similar to secondary breakdown in bipolar transistors
occurs.
Area [4]: Area restricted by drain-source voltage VDSS (withstand voltage)
The ASO chart listed in the data sheet applies to an ideal condition in which the case temperature Tc=25deg.
and Duty=0 (Single pulse), and does not exhibit the operation condition of actual switching power supply
circuits, etc. Consequently, the chart cannot be used for the review of feasibility of use without making
modifications. The chart must be derated according to the actual operating conditions (case temperature Tc,
operating frequency f, ON width t, etc.)
Fig.3-5 ASO chart of the FMV06N60ES (Condition: Duty=0, Tc=25deg.)
10
0
10
1
10
2
10
3
10
-3
10
-2
10
-1
10
0
10
1
DC
100ms
10ms
t
P
D
Power loss waveform :
Square waveform
t
P
D
t
P
D
Power loss waveform :
Square waveform
ID [A]
VDS [V]
Safe Operating Area
I
D
=f(V
DS
):Duty=0(Single pulse),Tc=25 c
t=
1
s
10
s
1ms
100
s
Area[1]
Area[2]
Area[3]
Area[4]
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3-7. Drain-Source On-state Resistance : RDS(on)
Figure 3-6 is a temperature characteristics chart of ON resistance RDS(on) of the FMV06N60ES.
The ON resistance is the most important characteristics for determining the ON dissipation, and is determined
by the typ. value and the max. value at the case temperature Tc=25deg. in the characteristics table. The ON
resistance has positive temperature characteristics, and in the power dissipation calculation/design in actual
operation, the max. value of RDS(on) at the channel temperature Tch=150deg. is read from Fig.3-6 and used as
the worst condition. The MOSFET has self-stabilizing function when connected in parallel. When two of more
devices are connected in parallel, even if current is fed concentrated on a device having low resistance value
due to variation of ON resistance, the device temperature increases due to heat loss, and the resistance value
of the device heated due to positive temperature characteristics of the variation of the ON resistance increases,
thus decreasing current. Consequently the balance of the current fed through each device is maintained
without causing thermal runaway to occur.
Figure 3-7 is a ON resistance RDS(on) - drain current ID characteristics chart. The ON resistance depends on
drain current and gate-source voltage, and the higher the gate-source voltage, the smaller the ON resistance.
We therefore recommend the use under the condition where the gate-source voltage is 10V or higher.
Fig.3-6 ON resistance - channel temperature Fig.3-7 ON resistance - drain current (standard value)
-50 -25 0 25 50 75 100 125 150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RDS(on) [ ]
Tch [C]
typ.
max.
Drain-Source On-state Resistance
RDS(on)=f(Tch):ID=3A,VGS=10V
0 2 4 6 8 10 12 14
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
6.5V
RDS(on) [ ]
ID [A]
Typical Drain-Source on-state Resistance
RDS(on)=f(ID):80 s pulse test,Tch=25 C
10V
8V
20V
7V
VGS=6.0V
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3-8. Capacitance characteristics Ciss, Crss, Coss
Figure 3-9 illustrates a simplified equivalent circuit of an N-channel MOSFET. The gate-drain capacitance,
namely mirror capacitance, greatly affects the switching characteristics. If the drain-source voltage becomes
equal to or smaller than the gate-source voltage, the mirror capacitance surges to approximately 10 times the
value of the time when it is larger than the gate-source voltage, as shown in Fig.3-10.
Figure 3-11 is a chart showing the capacitance
characteristics of the FMV06N60ES. Each capacitance
of the Power MOSFET has the relations shown below:
Input capacitance:
Reverse transfer capacitance:
Output capacitance:
The reverse transfer capacitance of the SuperFAP
series is designed to remain small to ensure
significantly improved switching characteristics.
C
GS
Reverse
diode
C
DS
C
GD
(C
mi
)
R
D
R
S
R
G
G
G
D
D
S
S(Source)
(Drain)
(Gate)
Fig.3-10 Capacitance and
drain-source voltage
Fig.3-9 Symbols and equivalent circuit of an N-channel MOSFET
GS
CCmiCiss
CmiCrss
DS
CCmiCoss
Fig.3-11 Capacitance and drain-source voltage
(standard value)
0 1020304050
C
mi
(= C
GD
)V
GS
= 5V
C
DS
C
GS
C
V
DS
[V]
10
-2
10
-1
10
0
10
1
10
2
10
0
10
1
10
2
10
3
10
4
C [pF]
VDS [V]
Typical Capacitance
C=f(VDS):VGS=0V,f=1MHz
Crss
Coss
Ciss
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3-9. Total Gate Charge : Qg
Figure 3-12 illustrates a gate charge Qg measurement circuit, and Fig. 3-13 illustrates the input gate charge
characteristics of the FMV06N60ES. In this measurement, the gate is charged with constant current (ig), and
the temporal change of the drain-source voltage (VDS) and gate-source voltage (VGS) is observed.
By charging the gate with constant current (ig), the time axis can be read as the quantity of electric charge Qg
only by multiplying time by ig.
3-10. Switching characteristics
Since the MOSFET is a voltage-controlled device, drive current is not required when ON or OFF state is
maintained. Meanwhile, each time switching operation is performed, charging/discharging current of the input
capacitance is fed.
(1) Resistance load switching characteristics
Figure 3-14 illustrates the switching operation waveforms against resistance load.
(1-1) Turn ON process
Period t0-t1:
The MOSFET is driven at time t0. The gate-source voltage increases with the progress of charging of
input capacitance Ciss from the internal resistance Ri of the drive circuit. The gate path resistance Rg is
compared with Ri and ignored.
Period t1-t2:
When threshold voltage value is reached at time t2, the MOSFET starts conducting. The drain-source
voltage decreases with the increase of the load resistance voltage drop. The drain current increases in
the period t1-t2. The mirror capacitance, which is still small at this time, is discharged due to the change in
drain-source voltage. The gate-source voltage increases along the transmission characteristics curve.
Period t2-t3:
At time t2, the drain-source voltage VDS becomes equal to the gate-source voltage VGS. The effect of
mirror capacitance that has grown very large appears here. In period t2-t3, the MOSFET operates as a
mirror integration circuit. Namely, the gate-source voltage remains the same, whereas the gate charging
current is fed via the mirror capacitance to further decrease the drain-source voltage.
Period t3-t4:
At time t3, the drain-source voltage reaches the final point of the analog area (mirror effect region) of the
output characteristics curve. In period t3-t4, the input capacitance Ciss is charged up to the level of the
drive voltage. The channel resistance further decreases. At timed t4, the ON resistance RDS(on) (value
obtained by dividing the drain-source voltage by the drain current) of the MOSFET reaches the lowest
value.
D.U.T
ig
Fig.3-12 Gate charge measurement circuit
0 5 10 15 20 25 30 35 40 45 50 55 60
0
2
4
6
8
10
12
14
Qg [nC]
Typical Gate Charge Characteristics
VGS=f(Qg):ID=6A,Tch=25
C
VGS [V]
480V
300V
Vcc= 120V
Fig.3-13 Input gate charge (standard)
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(1-2) Turn OFF process
Period t5-t6:
The turn off process is started by switching the drive voltage to 0 at time t5. The charge accumulated in
the input capacitance Ciss, which is at the maximum value at this time, is discharged via the internal
resistance Ri of the drive circuit, and the gate-source voltage decreases to the value that allows the drain
current to pass through the resistance area of the output characteristics curve.
Period t6-t7:
When time t6 is reached, the ON resistance increases slightly.
The MOSFET operates again as a mirror integrator during the period t6-t7. Namely, the gate drive current
is fed via the mirror capacitance, which is still large, with the gate-source voltage maintained at a constant
level, and the drain-source voltage increases.
Period t7-t8:
At time t7, the gate-source voltage becomes equal to the drain-source voltage. The mirror capacitance
decreases to a small value. The mirror capacitance, which has decreased, is charged, and the
drain-source voltage surges during period t7-t8. The drain current decreases in response to the voltage
drop of the load resistance, and the gate-source voltage also decreases.
Period t8-t9:
The threshold voltage is reached at time t8, and the MOSFET is interrupted completely. Finally, during the
period t8-t9, the input capacitance is discharged down to the level of the drive voltage.
Since the MOSFET does not have accumulation time, its switching time is determined only by the charging
and discharging of the input capacitance. Since the internal resistance Ri of the drive circuit can be selected
freely, the switching time of the MOSFET can be adjusted within a wide range.
(2) Switching characteristics of the induction load with a flywheel diode
Assume that in the initial state, the MOSFET is interrupted and current is fed to the induction load and the
flywheel diode. (See Fig. 3-15.)
(2-1) Turn ON process
Period t0-t1:
At time t0, the MOSFET is driven via rectangular wave voltage. (See Fig. 3-16.) The gate-source voltage
increases with the progress of the charging process of the input capacitance Ciss by the internal
resistance Ri of the drive circuit.
Period t1-t2:
At time t1, the threshold voltage is reached. During period t1-t2, the drain current increases in proportion
to the gate-source voltage, whereas the drain-source voltage is maintained at the operation voltage level
due to characteristics of the diode.
Period t2-t3:
At time t2, the transistor carries the entire load current. Since the reverse recovery current of the diode is
added to the load current in the subsequent period t2-t3, the drain current further increases.
0 t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
V
GS(th)
V
GS
I
D
V
DS
V
GS
I
D
V
DS
Fig.3-14 Switching characteristics against resistance load
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Period t3-t4:
At time t3, namely at the polarity reversing point of the reverse recovery current of the diode, the drain
current reaches the maximum value. Up to that time, the drain-source voltage remains at the same level
as the operating voltage. The gate-source voltage reaches a value capable of conducting the peak current
generated in the transistor.
In the period t3-t4, the drain-source voltage decreases, and the reverse voltage of the diode increases by
the same amount. In normal cases, the drain-source voltage decreases at the same rate as the mirror
capacitance is discharged depending on the gate drive voltage, and the gate-source voltage must be
maintained at a constant level as in the following period t4-t5 (mirror integrator).
However, in the period t3-t4, the change in drain current resulting from the decrease in reverse recovery
current of the diode affects the switching process. If the drain current decreases, the gate source
capacitance is discharged via the mirror capacitance. The gate-source voltage decreases to the value
sufficient to conduct the drain current. Consequently, sharp drain-source voltage waveforms are
generated during this period.
Due attention should be paid to the process in which a change is caused in the drain-source voltage in the
period t3-t4. If the MOSFET is driven at low resistance, the drain current increase rate is high, and the
change in commutation current of the flywheel diode also increases. Consequently, high reverse recovery
current of the diode is generated, which reaches the maximum value and then decreases suddenly. Note
that the sharp change in the reverse recovery current of the diode resulting in dissipation may cause
excessive voltage increase within the circuit, thus resulting in an overvoltage breakdown.
(2-2) Turn OFF process
Period t8-t9:
The turn OFF process is started at time t8. At time t9, the gate-source voltage decreases to the value
allowing the drain current to pass through the resistance area of the output characteristics curve.
Period t9-t10:
In the period t9-t10, the transistor operates as a mirror integrator having a large mirror capacitance.
Period t10-t11:
After the drain-source voltage exceeds the gate-source voltage at time t10, the transistor operates as a
mirror integrator having a small mirror capacitance.
Period t11-t12:
The flywheel diode is conducted at time t11, and the drain-source
voltage is maintained at a constant level. The drain current
decreases in proportion to the gate-source voltage.
Period t12-t13:
When the gate-source voltage is decreases to the threshold
voltage at time t12, the drain-source voltage reaches 0.
In the period t12-t13, the input capacitance is discharged to 0.
Fig.3-15 Current characteristics
at the time of induction load switching
iD
iL
iF
Fig.3-16 Switching characteristics
of induction load with flywheel diode
0 t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
V
GS(th)
V
GS
I
D
V
DS
V
GS
I
D
V
DS
t
t
t
iL
iF
iD
Load current
Diode current
MOSFET current
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4. Circuit design and mechanism of breakdown
4-1. Avalanche breakdown
4-1-1. What is avalanche breakdown?
When an inductance load such as transformer is subjected to high-speed switching using a Power MOSFET,
excessive surge voltage may be applied, the withstand voltage of the Power MOSFET may be exceeded, and
the breakdown area may be entered. The avalanche breakdown is defined as a mode in which due to
avalanche operation the channel temperature Tch and avalanche current IAR exceed the absolute maximum
rating, resulting in breakdown.
(1) Mechanism of avalanche breakdown.
Figure 4-1 shows the cross-sectional structure of the MOSFET.
A bipolar transistor exists parasitically within the MOSFET.
If overvoltage is applied to the MOSFET, and the withstand
voltage of the device is exceeded, avalanche current is fed.
The major flows of the avalanche current is as follows:
[1] Drain - Rzd - Vzd – Source
[2] Drain - Rzb - Vzb - Rb - Source
First of all, the avalanche current flows by the route of [1] when
the avalanche happens. The avalanche voltage increase by
generation of heat because of the avalanche current, and the
avalanche current begins to flow to the route of [2]. The potential
difference is caused by this current in Rb and heat is generated.
The resistance of Rb increase by generation of heat, and VBE of
a parasitic bipolar transistor decrease. The current that flows in
Vzb divides into Rb and VBE when the potential difference in Rb
higher than VBE of a parasitic bipolar transistor, and a parasitic bipolar transistor malfunctions. Therefore, the
current crowding happens in the part where the avalanche was caused, and MOSFET breakdown.
(2) Technology for increasing the resistance to avalanche breakdown
Generally, to improve the resistance to avalanche breakdown of the MOSFET, the base Rb of the parasitic
bipolar transistor is decreased, and a cell structure not allowing concentration of electric field is adopted. The
SuperFAP series adopts the following techniques to increase the avalanche capacity.
[1] Adopting a structure where by arranging a simple spherical p diffusion layer carefully, concentration of
electric field is loosened to eliminate local concentration of avalanche current
[2] Adopting a structure where by arranging a simple spherical p diffusion layer carefully, the entire area of pn
diode is increased, and avalanche permissible current per unit area is increased
[3] Adopting a structure where by forming a high-concentration p+ diffusion layer inside the channel p diffusion
layer, the base resistance Rb of the parasitic bipolar transistor is decreased and the operation of the
parasitic bipolar transistor is suppressed
(3) Measurement of the avalanche capacity
Figure 4-2 illustrates a circuit for measuring the avalanche capacity of the MOSFET, and Fig.4-3 illustrates the
measured waveform. If a voltage exceeding VGS(th) is biased to the gate of the MOSFET, drain current ID starts
to flow within the MOSFET via an inductance L. At this time, the drain current ID flows within the channel area.
If the gate voltage of the MOSFET decreases to VGS(th) or lower, the drain current ID decreases, whereas the
drain voltage VDS surges. The drain voltage VDS increases until it reaches the withstand voltage of the device,
and is cramped. The residual energy accumulated in the inductance L continues flowing as drain current ID. At
this time, since the channel area is interrupted, the drain current flows as avalanche current. The capacity of
the MOSFET of consuming the energy accumulated in the inductance L is defined as the avalanche capacity.
Fig.4-1 Cross-sectional structure of
the MOSFET
Metal (Drain electrode)
Al-Si (Source electrode)
PSG (Insulation film)
Poly-Si (Gate electrode)
SiO
2
(Oxide film)
Source
Drain
Rz d
Vzd
Paras tic
Bipola Transistor
Rb
Vzb
Rz b
n
+
n
+
n
-
[2][1]
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(4) How to guarantee the avalanche capacity
The SuperFAP series defines the avalanche capacity using the following items:
[1] Avalanche current IAR
Permissible current at occurrence of an avalanche.
Generally, permissible avalanche current decreases with the increase of temperature, which is why
temperature derating is provided in some cases. The SuperFAP series do not provide temperature derating,
and guarantee is made in the same temperature range.
[2] Avalanche energy EAS
The permissible avalanche energy at single pulse at the specified power voltage and under inductance
condition. Since it is restricted by channel temperature, the permissible energy varies depending on the
operating temperature conditions.
(5) Feasibility of use under avalanche condition
The following must be satisfied when using the MOSFET for actual avalanche operation:
[1] The current value at the time of avalanche is the lower than the guaranteed avalanche current.
[2] The channel temperature falls within the guarantee range (normally Tch150deg.).
The channel temperature in [2] must be considered even when avalanche operation is not performed. Since
power dissipation increases under avalanche operation, more attention should be paid.
Figure 4-4 illustrates the waveform at turn OFF in actual avalanche operation. There may be a case in which
even if the voltage at turn OFF exceeds the maximum rated withstand voltage VDS, avalanche current may not
be fed due to high withstand voltage of the device. In such cases, power dissipation calculation should be
made assuming that avalanche is occurring during the period in which the maximum rated withstand voltage
VDS of the device is exceeded.
Fig.4-2 Avalanche capacity measurement circuit
Fig.4-3 Avalanche waveform
Fig.4-4 Typical waveform at avalanche operation
BV
DSS
I
D
= I
AV
V
DS
Actual current
waveform
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4-2. ASO breakdown
ASO breakdown is classified into overcurrent, overpower, and overvoltage breakdowns.
4-2-1. Overcurrent breakdown
Due to short circuit of loads, etc., current exceeding the area restricted by the drain current ID and pulsed drain
current IDP in ASO is fed, causing the device to heat up and resulting in breakdown or melting of the internal
wiring of the package, which is defined as overcurrent breakdown.
4-2-2. Overpower breakdown
If the drain current ID and the drain-source voltage VDS are simultaneously applied, power dissipation
exceeding the area restricted by the maximum power dissipation PD in ASO is generated, thus causing the
device to heat up excessively, which is defined as overpower breakdown.
4-2-3. Overvoltage breakdown
If a large surge voltage exceeding the area restricted by the drain-source voltage VDSS (withstand voltage) in
ASO is applied due to high-speed switching of an inductance load such as transformer, and thus the
breakdown area is entered, the device is heated abnormally, resulting in breakdown or avalanche breakdown,
which is defined as overvoltage breakdown.
4-3. Diode breakdown
4-3-1. What is diode breakdown?
In a bridging circuit using a drain-source parasitic diode, sharp change in voltage (dv/dt) and/or current (di/dt)
during reverse recovery operation of the parasitic diode causes the parasitic bipolar transistor of the MOSFET
to arc and large current to be fed, thus resulting in uncontrollable state and breakdown, which is defined as
diode breakdown.
4-3-2. Mechanism of diode breakdown
If voltage is applied in reverse direction in a state in which
current is fed to the parasitic diode (voltage is applied between
D and S), the parasitic diode performs reverse recovery operation.
A part of this recovery current is fed through the Rb of the parasitic
bipolar transistor via route [2] in Fig.4-5 as in the case of an
avalanche. In this case, the charging current to the parasitic
capacitance Cds (=Cvzd+Cvzb) via the recovery dv/dt is also fed
to the Rb of the parasitic bipolar transistor. Due to the
composite effect of these two currents, potential difference is
generated in the Rb, and consequently parasitic bipolar transistor
(between B and E) is biased. When current starts to flow from the
drain through the parasitic bipolar transistor to the source, the
temperature of the parasitic bipolar transistor increases, causing
the resistance value of the Rb to increase and parasitic bipolar
transistor threshold voltage VEB to decrease, which further causes
the parasitic bipolar transistor to be biased, current is concentrated,
thus resulting in a breakdown of the MOSFET. To prevent this from
occurring, restrictions are imposed on the recovery di/dt affecting the
recovery current and the recovery dv/dt affecting the charging current.
Metal (Drain electrode)
Al-Si (Source electrode)
PSG (Insulation film)
Poly-Si (Gate electrode)
SiO
2
(Oxide film)
Source
Drain
Rz d
Vzd
Paras tic
Bipola Transistor
Rb
Vzb
Rz b
n
+
n
+
n
-
[2][1]
Fig.4-5 Current route
at avalanche breakdown
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4-4. Breakdown due to parasitic oscillation
As a result of directly connecting gate terminals (without inserting gate resistance Rg in between) when
connecting devices in parallel, or sudden change in the drain-source voltage or current at the time of turn
ON/OFF, parasitic oscillation occurs at the gate. Due to this parasitic oscillation, the gate-source voltage VGS
may exceed the rated voltage VGS, or the device may malfunction due to the parasitic oscillation of the gate,
thus resulting in thermal breakdown, which is called a breakdown due to parasitic oscillation.
The gate breakdown that occurs due to static electricity or parasitic oscillation is in two modes: One is
thorough breakdown, namely short circuit between the gate and the source or between the drain and the
source [1], and the other is halfway operation in which the impedance between the gate and the source
decreases whereas the leakage current between the drain and the source increases [2]. Under normal
operating conditions, the trace of breakdown increases due to short circuit between the drain and the source in
mode [1], and in mode [2] the operation by voltage whose VGS is lower than prescribed causes malfunction to
occur and leakage current to increase, thus resulting in ASO breakdown. It is therefore difficult to judge the
occurrence of gate breakdown from the trace of the breakdown.
Figure 4-6 shows parasitic oscillation waveform when the gates of the MOSFET are directly connected in
parallel. This oscillation occurs when the drive voltage reaches the threshold voltage of the MOSFET and the
drain current starts to flow.
This oscillation occurs because of extremely high forward transconductance of the MOSFET. The resonance
circuit consists of an external circuit, inductance of each MOSFET itself, and the parasitic capacitance. The
voltage generated due to this oscillation exceeds the maximum gate-source voltage value in many cases, thus
breaking the device. It is therefore recommended to connect a resistance of 4.7 or higher to each gate of the
MOSFET connected in parallel.
Fig.4-6 Change in gate-source voltage at parallel switching
Top: Each gate is connected directly.
Center: A 10 resistance is connected to each gate in series.
Bottom: A ferrite bead is connected to each gate in series.
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4-5. Electrostatic breakdown
4-5-1. What is electrostatic breakdown?
If static electricity or surge voltage is applied to the gate terminal of the MOSFET through human body or
experimental devices, the resistance to static electricity at the gate terminal is exceeded, thus resulting in a
breakdown, which is defined as electrostatic breakdown.
4-5-2. Prevention of electrostatic breakdown of the Power MOSFET (measures)
Compared with small-signal MOSFET and MOS IC, the Power MOSFET has significantly higher oxide film
resistance. However, since damage may occur due to static electricity as in the case of these MOS products,
pay special attention when handling the Power MOSFET.
(1) How to discharge static electricity from an electrostatic body
When making a workbench protected against static electricity, proper use of an electrically conductive table
mat, wrist strap, and floor mat allows static electricity built up to be removed. The speed of removing the
charge is determined based on the resistance on the capacitance route of the conductive body. Figure 4-8
shows an equivalent circuit in which the conductive body has capacitance C and the route resistance of R.
The voltage of the conductive body is expressed by the following formula as the function of time t:
V = Voltage [V] of the charged body at time t
V0 = Initial voltage [V] of the charged body
t = Second
C = Capacitance [F] of the charged body
R = Route resistance []
electrically conductive mats
electrically conductive floor
GND GND
TESTER
wrist strap
RC
t
VV exp0
Fig.4-7 Example of measures against
breakdown by static electricity
Fig.4-8 Equivalent circuit for static electricity discharge
Route
Resistance
R
Capacitance of
conductive body
C
t=0
Initial
Voltage
V0
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<Example>
Assume that the static electricity level of a worker is decreased to 100V or lower within one second according
to technical material TB57-1 of the Electric Industries Association of Japan (EIAJ). Substitute the following into
the above formula:
V = 100V (safe voltage)
V0 = 10kV (Initial voltage of the human body or charged body)
t = 1sec. (Longest permissible time for achieving the safe voltage of 100V)
C = 200pF (Average of human capacitance 100pF to 400pF)
R = Maximum permissible resistance [] to the ground
R 1.09 109 = 1090 M
can thus be obtained. From this calculation, it is found that if the resistance from the table mat, floor mat, or
wrist strap to the ground is 109 or lower, discharge to obtain safe voltage, 100V, can be performed within one
second, and the parts can thus be protected against electrostatic breakdown.
- About the breakdown value of a device due to electrostatic discharge
Table 4-1 lists the voltage range in which various devices may result in breakdown due to electrostatic
discharge from workers.
Table 4-1 Breakdown voltage by device
Type Voltage range [V]
MOSFET 100 ~ 200
Junction FET 140 ~ 10000
C MOS 250 ~ 2000
R・
・2
4
10200
1
exp101100
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5. Thermal design
5-1. Concept of heat dissipation
(1) Transient thermal impedance and steady thermal resistance
The heat dissipation treatment of power dissipation that occurs at the channel of a Power MOSFET is
performed by mounting the MOSFET to a cooling body, or by the device itself. Figure 5-1 simulates the heat
radiation route in the former case in an electrically equivalent circuit.
In the equivalent circuit in Fig.5-1, the transient thermal impedance is the thermal resistance within the time
range affected by the thermal capacitances C1 to 4, and is the function of time. As the transient thermal
impedance characteristics of each device, the maximum value is displayed on the data sheet, which is
equivalent to D 0. The transient thermal impedance of the cooling body is found by the following formula:
where,
Fig.5-1 Electric equivalent circuit showing thermal behavior
f
t
af
RtRf τ
1)(
CVRf af ・γ・・τ
冷却体
絶縁シート金属ベース
チップ
MOSFET
PDch R1R2R3R4R5
C4
C3
C2
C1
PD 発生損失
C1,R 1 MOSFETチップ、半田層
C2,R 2 金属ベース
R3 接触熱抵抗
C3,R 4 絶縁シート（接触熱抵抗を一部含む）
C4,R 5 冷却体
Chip
Metal b ase Insulation sheet Cooling body
PD Power dissipation
C1,R1 MOSFET chip, soldered layer
C2,R2 Metal base
R3 Contact thermal resistance
C3,R4 Insulation sheet
(including a part of contact thermal resistance)
C4,R5 Cooling body
Rf-a : Cooling body steady thermal resistance [deg./W]
t : Time [S]
f : Thermal time constant of the cooling body [S]
V : Cooling volume [cm3]
: Specific gravity [g/cm3]
C : Specific heat [W• S/g• deg.]
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Table 5-1 lists the specific gravity of materials required for this calculation, and Fig.5-2 illustrates the steady
thermal resistance of an aluminum cooling plate (coated in black).
Table 5-1 Specific gravity and specific heat of
each material
Material Specific
gravity
[g/cm3]
Specific heat
[W• S/g• deg.]
Aluminum 2.71 0.895
Copper 8.96 0.383
Meanwhile, since the steady thermal resistance is not affected by thermal capacitance at all, the channel
temperature can be found easily.
Tch : Channel temperature
Ta : Ambient temperature
Rch-c : Thermal resistance between channel and case (MOSFET thermal resistance)
Ri : Insulation sheet
Rc-i, Ri-f : Contact thermal resistance
Rf-a : Thermal resistance of cooling body
PD : Generated power dissipation
5-2. Transient thermal impedance characteristics of the device
The specification of the MOSFET lists the transient thermal impedance characteristics of the device to assist
thermal designing. Figure 5-3 illustrates the transient thermal impedance characteristics of the FMV06N60ES.
For example, assume a single pulse having pulse width of 1 ms, and the permissible power dissipation PD in
the case in which the device is mounted to a cooling body of 5deg./W under Ta=40deg. condition can be
calculated by using the following formula:
21.4 [W]
msRthaRthf
TaTch
P
D
1
max
WW /0.15/5
40150
℃℃
℃℃
Fig.5-3 Transient thermal impedance
characteristics of the FMV06N60ES
D
PaRffRiRiiRccRchTaTch ・
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
-3
10
-2
10
-1
10
0
10
1
Maximum Transient Thermal Impedance
Zth(ch-c)=f(t):D=0
Zth(ch-c) [
C/W]
t [sec]
Thermal resistance of an aluminum plate
Thermal resistance (deg./W)
Area of a radiator plate (cm
2
)
Fig.5-2 Steady thermal resistance of the aluminum cooling plate
AN-080E Rev.1.0
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
5-2. Calculation of channel temperature
When using a MOSFET, it is essential that the channel temperature fall within the maximum rating under the
operating condition. It is therefore necessary to find the channel temperature based on the operating
waveforms, thus verifying whether the MOSFET can be used or not.
(1) Calculation of channel temperature for rectangular wave power dissipation
Table 5-2 lists the channel temperature calculation formulae for continuous load, single pulse load, continuous
pulse load, and irregular pulse load following the continuous pulse load.
Table 5-2. Channel temperature calculation formula
Load Channel temperature calculation formula
単一パルス負荷
Tch
P
0t
1
Single pulse load
連続パルス負荷に続く
不規則パルス負荷 Tch
P1
t1
t2
P2
P3
t3t4t5t6
Irregular pulse load following
continuous pulse load
連続パルス負荷
Tch
P
t
1
t
2
Continuous pulse load
連続負荷
Tch
P
0
Continuous load
aRthchPTaTch
･
)1(tRthPTaTch ･
･･
2
1
2
11t
t
aRthch
t
t
PTaTch
1221 tRthtRthttRth
･･･
2
1
2
1
11t
t
aRthch
t
t
PTaTch
46362 ttRthttRthP
･
221 tRthttRth
563 ttRthP
･
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
(2) Calculation of channel temperature for complicated power dissipation waveforms
If the MOSFET has a complicated power dissipation waveform, the channel temperature can be calculated by
converting the waveform into a rectangular wave as shown in the dotted line in Fig.5-4, and based on the
concept of superposition.
(3) Specific channel temperature calculation
To calculate the channel temperature of the MOSFET, the following are required:
(a) Waveform for one cycle (VDS, ID, and cycle T must be clear.)
(b) Expansion of turn ON/OFF waveform
(c) Operating condition (case temperature Tc, etc.)
The steps for calculating channel temperature are shown below.
[1] Obtaining operation waveform
Fig.5-4 Channel temperature in complicated
power dissipation waveforms
* If turn ON dissipation and turn OFF dissipation can be ignored, the waveform need not be obtained.
Po Po Po Po Po
Po Po
P
AV
P
AV
Po Po
-P
AV
-Po
Tch
(peak)
Tch
(AV)
T
t
(a) Power dissipation waveform
(b) Power dissipation approximation
(averaging)
(c) Application of concept of
superposition (power dissipation)
(d) Application of concept of
superposition (temperature increase)
V
DS
I
D
V
DS
I
D
V
DS
I
D
ON period
OFF period
Entire waveform
(The cycle must be clear.)
Enlarged waveform at turn ON Enlarged waveform at turn OFF
50~100ns/div 50~100ns/div
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[2] Approximation of operation waveform
[3] Calculation of transient thermal impedance
The transient thermal impedance value at each
time can be read from the transient thermal
impedance chart in Fig.5-5. Note, however, that
if the pulse width is 1 ms or shorter, the value
can be found by using the following formula:
Example: In the case of pulse width of (Ta)
Rth(ch-c)(1ms) : Duty=0, Transient thermal
impedance value at 1ms
ｔｔ２
ｔ
1
ｔ
3
ｔ
T
Average power
dissipation:
Pav
Average power
dissipation at ON:
Pav(on)
Turn ON dissipation:
Pt-on
Turn OFF dissipation:
Pt-off
ON dissipation:
Pon
Fig.5-5 Transient thermal impedance chart
001.0
)1)(())((
Ta
RthRth mscchTacch
t
II
0
t
VV
0
dtVtItP t
S0
00
t
P
PS
Power dissipation is calculated by the following formula:
T
tP
Pav onav
)(
t
tPtPtP
Pofftonont
onav
321
)(
* If the turn ON dissipation and turn OFF dissipation can be ignored, they need not be taken into consideration.
If the power dissipation for the turn ON period is calculated using the
above formula, the result of the calculation “P” is expressed as “Pt-on.”
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
-3
10
-2
10
-1
10
0
10
1
Maximum Transient Thermal Impedance
Zth(ch-c)=f(t):D=0
Zth(ch-c) [
C/W]
t [sec]
t
I
D
V
DS
I
0
I
V
0
V
Pt-on
Pon
Approximated
dissipation
Operation waveform at turn ON
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
[4] Calculation of channel temperature
)()()()()( TonavtTavonavcchavcch RthPRthPPRthPT
)3()32()( tonofftttontontont RthPPRthPPRthP
Channel temperature increase calculation formula :
* If turn ON dissipation and turn OFF dissipation can be ignored, they need not be taken into consideration.
Pav
Pav(on)
Pt-on
Pon
Pt-off
Power dissipation
approximation model
Temperature increase model
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Fuji Power MOSFET
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6. Cautions in mounting and handling
To ensure safe operation over a long period of time, follow the precautions on handling shown below.
(1) Soldering
When a semiconductor device is soldered, the temperature of the lead exceeds the maximum rated storage
temperature. Since quality assurance regarding the resistance against soldering is applicable to the level
shown below, perform soldering within the listed range.
(a) Recommended mounting condition
Methods
Categories Packages Wave Soldering
(Full dipping)
Wave Soldering
(Only terminal) Infrared Reflow Air Reflow Soldering iron
(Re-work)
TO-3PL Unable Possible Unable Unable Limited to 1time
TO-3P Unable Possible Unable Unable Limited to 1time
TO-247 Unable Possible Unable Unable Limited to 1time
TO-3PF Unable Possible Unable Unable Limited to 1time
TO-220 Unable Possible Unable Unable Limited to 1time
TO-220F Unable Possible Unable Unable Limited to 1time
T-Pack(L) Unable Possible Unable Unable Limited to 1time
Through-Hole
K-Pack(L) Unable Possible Unable Unable 1time
T-Pack(S) Unable Unable Possible Possible Unable
T-Pack(SJ) Unable Unable Possible Possible Unable
K-Pack(S) Unable Unable Possible Possible Unable
Surface Mount
TFP Unable Unable Possible Possible Unable
- Through-Hole Package
Soldering temp. Immersion time
260±5 deg. 10±1 sec
350±10 deg. 3.5±0.5 sec
- Surface Mount Package
Number of times(Reflow) Twice
Soldering Temp. & Time ≥230 deg., 50sec
Package surface Peak Temp. & Time 260 deg., 10sec
(b) The immersion depth of the lead should be up to 1 to 1.5 mm from the device main unit.
(c) Be careful not to let the device main unit be immersed in soldering liquid when mounting the device by
the solder flow method.
(d) When using a flux, it is desirable to use rosin series flux, and not chlorine series flux.
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(e) Recommended reflow
Fig.6-1 Recommended reflow profile (through hole/Pb-free solder specification)
Fig.6-2 Recommended reflow profile (SMD/Pb-free solder specification)
Pre-heat
Post Cooling
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(2) Processing and mounting of through hole terminal
Handling of lead wire of resin-sealed power transistor
(a) Stress to the lead wire
If stress of more than necessary is applied to the electrode lead of a semiconductor device, the internal chips
and external package may be damaged. To prevent this from occurring, keep the load applied in the direction
shown in Fig.6-3 to 1kg or lower.
(b) Caution in molding a lead
If there is no other choice but to mold a lead for convenience of parts layout, pay attention to the following:
•Provide an exclusive jig that does not allow stress shown in Fig.6-4 to be applied.
•When bending the lead in the horizontal direction, bend it at the thin portion or at the part 4 mm or more away
from the transistor main unit, and keep the bending angle within 30.
•When bending the lead at the right angle against the type displaying surface, bend it at the portion 4 mm or
more away from the transistor main unit.
•Molding should be performed only once at a place, and do not perform re-molding or restore the original
shape.
(c) Insertion into the printed board
When inserting a lead to the printed board, coincide the interval of lead wires and that of insertion holes to
prevent excessive stress from being applied to the root portion of the leads.
To prevent the lead soldered to the printed board from being forcibly bent to mount it to a radiator plate,
perform mounting work first and then perform soldering.
Fig.6-3 Stress to the lead wire
Fig.6-4 Cautions in molding a lead
すべて力は1kg以下
1kg or lower
30°以内
細い部分
4mm以上
4mm以上
4mm or more
thin portion
within 30°
4mm or more
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
(3) Washing (Common to through hole and SMD)
When soldering is performed using a flux, washing with solvent is required in general. In this case, pay
attention to the following:
(a) Solvent
•Do not use flammable, toxic, or corrosive solvents.
•Never use a trichloroethylene series solvent because it contains chlorine.
(b) Washing method
It is desirable to perform washing by immersing the portion to be washed. If ultrasonic washing is to be
performed, set the frequency, avoiding the resonance point (several tens of kHz), and pay attention not to let
the device or printed board to directly contact the oscillation source.
(4) Mounting to a radiator plate
(a) If the fastening torque of the screw for mounting is too low, the thermal resistance increases. On the
contrary, if it is too high, the device may be deformed, thus resulting in a failure.
Consequently, it is recommended to fasten the screws at the torque listed in Table 6-1.
Table 6-1. Semiconductor device fastening torque
Package Diameter of
mounting hole Screws used Optimum fastening
torque (N•cm)
TO-220AB φ3.6 M3 30-50
TO-220F φ3.2 M3 30-50
TO-3P φ3.2 M3 40-60
TO-247 φ3.2 M3 40-60
TO-3PF φ3.2 M3 40-60
TO-3PL φ3.2 M3 60-80
(b) It is recommended to apply a compound thinly and uniformly to improve the thermal conductivity between
the semiconductor device main unit and the radiation plate, thus improving heat dissipation effect.
(c) Application of thermal compound
As a method for allowing a thermal compound to exist between the device and a cooling body, a compound is
applied uniformly to the device, which is then mounted to the cooling body. However, in the case of small
products such as the TO220 package, the application work is cumbersome. As a method for filling the gap
between the device and the cooling body with a compound, apply an appropriate amount of compound to the
case immediately below the semiconductor device chip-mounting portion in a shape of a point, and fasten the
device to the cooling body with screws, and the compound expands, filling the gap, and a compound layer
containing few air bubbles can thus be formed easily.
(d) When fastening one device with screws at 2 positions, pay special attention to fasten the screws uniformly.
(e) Surface flatness 30 m
(f) Surface roughness 10 m
(g) Do not taper threaded holes.
コンパウンド
Compound
<Small package such as TO3P>
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(5) Cautions in storage and transportation
(a) Storage
(i) It is desirable that semiconductor devices be stored in a place of normal temperature and humidity. Avoid
storing the devices in a place of temperature and humidity far away from the normal values, which are
approximately 5 to 35deg. and 45 to 75% respectively. When storing molded type power transistors in an area
that becomes extremely dry in winter, humidification by a humidifier is required. If tap water is used for
humidification, chlorine contained in it may cause corrosion of the leads of the device. To prevent this from
occurring, use pure water or boiled water for humidification.
(ii) Avoid storing semiconductor devices in a place where corrosive gas is generated or subjected to much
dust.
(iii) Avoid storing semiconductor devices in a place subjected to sharp temperature change. Otherwise
condensation may occur to the devices. Store the devices in a place having minimum temperature change.
(iv) Pay attention not to apply load to semiconductor devices during storage. In particular, if they are stored,
stacked on top of each other, unexpected load may be applied.
(v) Store the semiconductor devices with each terminal kept unprocessed to avoid occurrence of corrosion,
which may result in insufficient soldering at the time of processing.
(vi) Contain the devices in a container that does not take static electricity easily, or the one used for the
delivery of the product.
(vii) All the shelves for storage should be made of a metal. Be sure to ground them.
(b) Transportation
(i) Be careful not to have impact on the devices by dropping them, etc.
(ii) When transporting large number of devices in boxes, place the devices by inserting a soft spacer to prevent
the contact electrode surface, etc. from being damaged.
(iii) When transporting Fuji Power MOSFET, take measures against static electricity using a conductive bag or
aluminum foil to prevent static electricity to build up between the gate and the source.
(c) Work environment
(i) The person who handles the Power MOSFET should use a body earth. As a body earth, wear a wrist strap,
copper ring, etc., mount a resistance of approximately 1M, and ground it to prevent electric shock.
(ii) Spread a conductive floor mat, tablemat, etc. in a place for handling the Power MOSFET, and be sure to
perform grounding.
(iii) When using a measuring device such as curve tracer, also ground the measuring device.
(iv) Before performing soldering, ground the soldering bath to prevent the leak voltage from the soldering iron
or bath from being applied to the Power MOSFET.
Be sure to follow the cautions described above to prevent an electrostatic breakdown of the device.
Fig.6-5 Conductive bag (left) and conductive foam (right)
AN-080E Rev.1.0
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
7. Application to switching power supply
7-1. Advantages of Power MOSFET
Advantage Disadvantage
Feature
For users For users
Power-
controlled
devaice
• Small drive power
• Simple drive circuit
•Saved energy and improved
efficiency
•Compact and reduced cost
•Lower number of parts
•High drive voltage • Difficulty in applying to
low-voltage driving
Majority
carrier
device
•High switching speed
•Excellent radiofrequency
characteristics
•High resistance to
breakdown
•Resistant to thermal
runaway
•Higher device performance
allowed
(high-accuracy control etc.)
•Downsizing of peripheral
devices resulting from
higher frequency
(transformer, capacitance)
•Saved energy and improved
efficiency
•Improved device reliability
•Facilitated heat dissipation
design
•Larger ON resistance
of high-voltage devices
than that of bipolar
transistors
•Increased ON
resistance resulting
from temperature
increase
• Large power dissipation in
low-frequency application
(A large radiator plate is
required.)
•Consideration required for
heat dissipation design
Major advantages of the MOSFET include not only high switching speed but also excellent radiofrequency
characteristics and independence of switching time of the temperature. By achieving higher frequency of the
switching frequency using these advantages, downsizing of radiofrequency transformers and the LC on the
secondary side is allowed.
In addition, with the increase of operation frequency, the switching loss (OFF dissipation in particular)
becomes dominant, and the effect of the defect of large ON resistance decreases, which is an essential point
for selecting devices.
Other features are summarized in the following table:
Item Feature Advantage in application
Area of safe operation
(ASO)
•Independent of gate reverse bias voltage •No need of considering reverse bias ASO
Voltage-controlled type
•Low drive power
•Simple drive circuit
•No consideration is needed in designing a drive circuit
when a large load current range is required for the
power supply as in the case of pulse load such as
motors
Positive ON resistance
temperature characteristics
•Easy parallel connection
7-2. Points to keep in mind when designing a gate drive circuit
(1) Drive circuit
(a) The drive power dissipation is calculated from Ciss based on the gate charge amount Qg.
Generally, in designing a Power MOSFET drive circuit, the drive power dissipation can be found using the
following formula:
Drive power dissipation:
where,
f : Operation frequency
VGS : Gate-source voltage
t : Switching time
2
GS
VCissfPd
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Fuji Electric Co., Ltd.
The input capacitance Ciss in this formula in the data sheet is the value obtained with VDS fixed, and the value
obtained by substituting this value into the formula deviates from the actual power dissipation. The reason for
this is that a gate-drain capacitance CGD, which is a mirror capacitance, exists in the Ciss, CGD is the function of
the drain-source voltage VDS, and the gate-source capacitance CGS is the function of VGS. If the Ciss in the
above formula is regarded as the function of VDS and VGS in actual designing of a drive circuit, the calculation
becomes extremely complicated and cumbersome. Therefore, specifying the gate charge amount Qg as the
function of VGS and VDS is the optimum method.
Figure 7-1 illustrates the input charge of the FMV06N60ES (600 V/6 A).
The drive power dissipation of the drive circuit can be found based on the gate charge Qg, using the following
formula.
Drive power dissipation:
(Example) When driven at VGS = 10 V and f = 200 kHz
•When the drive power dissipation is calculated using the Ciss defined in the specification:
Ciss=2280 ㎊ , Pd=0.05W
•When the drive power dissipation is calculated using the gate charge Qg:
Qg=54nC , Pd=0.11W
The drive power dissipation calculated using Qg is approximately twice as large as the drive power
dissipation calculated using the Ciss defined in the specification.
(b) Other points
Item Caution
Switching loss •To decrease the switching loss, measures should be taken to discharge the gate charge in a short time.
Drive circuit
voltage
•The voltage should be maintained at least 8V or higher. To achieve this, measures such as stopping the oscillation
before VGS decreases to 8V or lower should be taken.
•Measures should be taken not to allow VGS to exceed the gate threshold voltage VGS(th) at the time of turning OFF.
Fig.7-1 Typical Input Charge
0 5 10 15 20 25 30 35 40 45 50 55 60
0
2
4
6
8
10
12
14
Qg [nC]
Typical Gate Charge Characteristics
VGS=f(Qg):ID=6A,Tch=25
C
VGS [V]
480V
300V
Vcc= 120V
GS
VQgfPd
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<Typical drive circuit>
(2) SuperFAP series and gate resistance Rg
Compared with conventional products, high-speed
switching is allowed with the SuperFAP series by
reduced the gate charge. Conventionally, the gate
resistance was decreased to increase the speed, thus
decreasing the switching loss. Meanwhile, with the
SuperFAP series, high-speed switching is allowed with
a larger gate resistance than that of the conventional
one, and the switching loss can be reduced.
Figure 7-2, 7-3, and 7-4 are the charts illustrating the
turn OFF dissipation, temperature increase, and power
efficiency obtained with the conventional product and
the SuperFAP series mounted to the MOSFET for
main switching of AC adaptor for 90W worldwide input
laptop PCs.
Fig.7-2 Gate resistance and standardized
power efficiency
Fig.7-3 Gate resistance and standardized
turn OFF dissipation
Fig.7-4 Gate resistance and standardized
temperature increase
Q2
Q1
ｵﾌ
ﾊﾟﾙｽ
ｵﾝ
ﾊﾟﾙｽ
E
Q2
Q1
E
E
Q2
Q1
C
R
T
直接駆動
パルストランス駆動
T
Q1
EQ2
Direct drive
ON
p
ulse
OFF
p
ulse
Pulse trans drive
10 20 30 40 50 60 70
0.970
0.975
0.980
0.985
0.990
0.995
1.000
規格化 効率（Rg=10ohmを1とする)
Rg (ohm)
2SK3502
従来品レベル
Standardized efficiency
(Rg=10ohm regarded as 1)
Conventional product
2SK3502
10 20 30 40 50 60 70
1
2
3
4
5
6
規格化 Poff （Rg=10ohmを 1 とする）
Rg (ohm)
2SK3502
従来品レベル
Standardized Poff
(Rg=10ohm regarded as 1)
Conventional product
2SK3502
10 20 30 40 50 60 70
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
規格化 温度上昇ΔT(Rg=10ohmを1とする）
Rg (ohm)
2SK3502
従来品レベル
Standardized temperature increse ΔT
(Rg=10ohm regarded as 1)
Conventional product
2SK3502
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Fuji Power MOSFET
Fuji Electric Co., Ltd.
7-3. Cautions for parallel connection
To increase the output capacitance of electronic devices, power devices to be used for the main circuit of the
electronic device are connected in parallel in many cases. Generally, the Power MOSFET is easier to be
connected in parallel than bipolar transistors. The reason for this is that the operation resistance of the Power
MOSFET has a positive temperature coefficient, and that even if unbalance should occur between the current
fed through each device connected in series, the positive temperature coefficient offsets the current unbalance.
However, if the wiring connecting each MOSFET in parallel is unbalanced, unbalance in current occurs during
the transient period of the ON and OFF switching operation, thus resulting in non uniform channel temperature.
Cautions in connecting the Power MOSFET in parallel are described below.
(1) Gate parasitic oscillation
If the gate of the MOSFET is directly connected in parallel, parasitic oscillation may occur to the gate and thus
resulting in the breakdown of the device. (See 4-4. Breakdown due to parasitic oscillation)
To prevent this from occurring, connect a resistance of 4.7 or higher to each gate of the MOSFET connected
in parallel.
(2) Circuit wiring
It is desirable that the gate drive and main circuit wiring connecting two or more MOSFETs in parallel be
uniform. In particular, the counter electromotive force,
Vls = ls•di/dt ,
generated due to the inductance Is contained in the wiring between the main circuit and the source electrode
affects the voltage close to the gate-source electrodes of the MOSFET, thus having a large impact on the
current balance at the time of turning ON and OFF of the MOSFET.
l
D1
l
D2
l
S2
l
S1
l
G1
l
G2
R
g1
R
g2
Fig.7-6 Wiring inductance equivalent circuit
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Fuji Electric Co., Ltd.
Figures 7-7 and 7-8 illustrate the current balance waveforms at the time of turn ON and OFF generated due to
the difference between the drain and the source wiring inductance ID and IS of the main circuit (two
SuperFAP-Gs rated at 500 V/10 A are used).
Turn ON current balance Turn OFF current balance
ΔLd=6nH
ΔLd=45nH
Turn ON current balance Turn OFF current balance
ΔLs=2nH
ΔLs=6nH
ΔLs=21nH
Fig.7-7 When there is a difference in the inductance of the drain electrode wiring of the main circuit
Fig.7-8 When there is a difference in the inductance of
the source electrode wiring of the main circuit
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As shown above, the current balance at the time of turn ON in parallel operation depends largely on the wiring
of the source of the main circuit. Consequently, the wiring between the source and the ground should be kept
as short and thick as possible to minimize the inductance.
(3) Improving the current unbalance
(a) Characteristics of the MOSFET and current balance
The positive temperature coefficient of the operation resistance of the MOSFET affects the current unbalance
generated in parallel operation to be improved at all times.
However, if the MOSFET is used at radiofrequency as in the case of an application to a switching power supply,
the unbalance in power dissipation, which may be generated due to the unbalance in transient current at turn
ON and OFF, cannot be ignored. As the method for improving this current unbalance, Fuji Power MOSFETs
classified into various standard threshold voltage VGS(th) classes are available.
Table 7-1 Standard VGS(th) classification of the SuperFAP series
SuperFAP series
(logic series)
SuperFAP series
(nonlogic series)
Series
Rank symbol Range Range
C 0.95 V ~ 1.30 V -
D 1.25 V ~ 1.60 V -
E 1.55 V ~ 1.90 V -
F 1.85 V ~ 2.20 V -
G 2.15 V ~ 2.50 V -
L - 2.95 V ~ 3.35 V
M - 3.30 V ~ 3.70 V
N - 3.65 V ~ 4.05 V
P - 4.00 V ~ 4.40 V
R - 4.35 V ~ 4.75 V
S - 4.70 V ~ 5.00 V
Note: Ranks cannot be specified.
(b) Drive condition and current balance
As a method for improving the current unbalance at turn OFF, in particular, measures should be taken to keep
the switching time as short as possible. Figure 7-9 illustrates the current unbalance at turn ON and turn OFF
due to increase/decrease of gate series resistance (500V/10A MOSFET is used).
Turn ON current balance Turn OFF current balance
Rg=10Ω
Rg=200Ω
Fig.7-9 Current balance waveform due to the difference in series gate resistance
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Fuji Electric Co., Ltd.
7-4. Example of applications
* The values in the above table are guidelines. Select your MOSFET after due consideration.
○:Planer / ●:SJ-MOS
MOSFET On-state Resistance RDS(on) [ohm]
Power range [W]
Application Circuit type
MOSFET
Breakdown
Voltage
BVDSS [V] ~30 50 100 150 200 300 500 1k 2k
Recommended
IC
CRM-PFC 600V
○
0.85
○
0.52
○
0.52
○
0.38
○
0.27
FA5590series
CCM-PFC 600V
●
0.19
●
0.19x2
●
0.11x2
FA5502
FA5610series
Single
Forward
900V
○
2.5
○
2.0
○
1.4
○
1.0
○
1.4x2
○
1.0x2
FA5504/10/14
FA5604
Double
Forward
500V
○
0.27
●
0.19
-
Standard
Power Supply
Phase-shift
Full-Bridge
600V
●
0.38
●
0.19
-
CRM-PFC
CCM-PFC
500V /
600V
○
0.52
○
0.38
○
0.31
●
0.19
●
0.19x2
FA5590series
FA5610series
Current Resonant 500V
○
1.5
○
0.85
○
0.52
○
0.38
M-Power
LCD-TV
PDP-TV
QR 800V
○
2.0
○
1.5
FA5571series
Boost-
Chopper
600V
●
0.05x2
- Photovoltaic
Power
Conditioner Full-Bridge 500V
●
0.05x2
-
100V /
110V
600V
○
2.3
-
Adapter
(Low Power)
Ringing
choke 200V /
220V
900V
○
4.6
-
CCM-PFC 600V
○
0.4
○
0.4
●
0.19
●
0.19x2
●
0.19x2
FA5502
FA5610series
Single
Forward
900V
○
2.0
○
1.4
○
1.0
FA5504/10/14
FA5604
Desktop PC /
PC server
Double
Forward
500V
○
0.52
○
0.27
●
0.19
-
CRM-PFC 600V
○
0.52
●
0.38
FA5590series
Flybuck-PWM 600V
○
2.3
○
1.2
○
0.75
●
0.38
FA5528series
FA5592series
Note PC-
Adapter /
IJP /
LBP
Flybuck-QR 600V
○
2.3
○
1.2
○
0.75
●
0.38
FA5571series
Single
Forward
200V
○
170m
○
66m
○
66m
○
66mx2
○
66mx2
○
66mx2
-
Bus
converter Phase-shift
Full-Bridge
100V
○
10mx8
○
10mx8
-
