SHAP4-B
ATM Traffic Shaper
(Generator/Receiver)
SHAP4-B
Title: ATM Traffic Shaper SHAP4-B
Version: 1.1
Last update: November 9, 2000
Originator: M. Guth, T. Mense
Purpose: Specify SHAP4-B implementation
Keywords: ATM, UPC, Shaping, Measurement
Features:
Shaping on a per class or per group basis
Supports 32 classes or 10 groups
Single or Dual Leaky Bucket Shaping function
Allows control of PCR, SCR, MBS and CDV traffic parameters
Allows 32 output rates per class per LB
Select different parameter sets by HW or SW
Up to 2M cells per class
Uses low cost Dynamic RAM EDO/Fastpage Mode
Up to 320 Mbit/sec data rate with 50 ns EDO
Multiplexed utopia level 1 and SAI compatible interfaces
Output can be halted while arriving cells are stored
Supports 53 and 56 byte cell size
Cell size conversion 53
56 bytes
Cell drop and insert via microprocessor interface
Repeated cell sequence transmission at specified rate
Can work as traffic generator and traffic analyzer
Can copy one cell or part of a cell from the data stream
24 bit time stamp for cell arrival timing
November 9, 2000
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Revision History
Version Date Comment
1.0 24-7-2000 Initial version (preliminary)
1.1 9-11-2000 Changes after prototype testing
- up to 40 MHz sys-clk
- new feature to handle Utopia output FIFO, see section 2.2.6
Page 2 of 82
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November 9, 2000
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Contents
1 General description 8
1.1 Shapingfunction .................................................... 8
1.2 Dataflow ........................................................ 9
2 ATM ports 9
2.1 Inputport ........................................................ 9
2.1.1 Multi Physical Utopia Level-1 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Cell alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 Idlecells .................................................... 12
2.1.4 HECcheck................................................... 12
2.1.5 Cellformat................................................... 13
2.1.6 Timestamp................................................... 14
2.1.7 Inputstatus................................................... 14
2.2 Outputport ....................................................... 15
2.2.1 Multi Physical Utopia Level-1 output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Idle cell production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 Output cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.4 Idle cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.5 Circularmode.................................................. 18
2.2.6 Utopia output FIFO control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Shaping function 18
3.1 Rateparameters..................................................... 19
3.2 Specialrates....................................................... 19
3.2.1 Full data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Stopdatastream ................................................ 20
3.3 Single Leaky Bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1 Ratecontrol................................................... 20
3.3.2 Examples.................................................... 21
3.4 DualLeakyBucket ................................................... 22
3.4.1 Ratecontrol................................................... 22
3.4.2 Examples.................................................... 23
3.5 Output burst control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Cell Delay Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Multiple classes 25
4.1 Priorities setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 Independent priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.2 Group priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Queue output conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
November 9, 2000
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
5 Class data 28
5.1 Queue control RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.1 Queue base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.2 Queuesize ................................................... 29
5.1.3 Indication level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.4 Discarded cells counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.5 Queuelevel................................................... 29
5.1.6 Queue status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.7 Read/Write queue control RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Leaky Bucket select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Read/Write Shaping settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.1 Write parameter or level RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.2 Read parameter or level RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.3 Read/write static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 CLP bit handling 32
7 Class assignment 32
7.1 Headermask ...................................................... 32
7.2 Lookuptable ...................................................... 33
7.3 General memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Class Rate Adaptation 34
8.1 Parameter set select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2 Software rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3 Hardware rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.4 Parametercurves .................................................... 36
8.5 Asymmetric change (ABR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9 Local cell transfer 37
9.1 CPUcellhandling.................................................... 38
9.2 DMAcellhandling................................................... 38
9.3 Read cell from data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4 Insert cell in data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.5 Cell interface transfer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 Special cell copy 40
11 Queue status indication 41
12 Traffic receiver & generator 43
12.1Trafficreceiver ..................................................... 43
12.2Trafficgenerator..................................................... 43
Page 4 of 82
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November 9, 2000
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
13 External memory 45
13.1Dynamicmemory.................................................... 45
13.1.1Memorytype.................................................. 45
13.1.2Refreshrate................................................... 46
13.1.3 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.2Staticmemory...................................................... 46
14 Register summary 49
14.1 Dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.1.1 Header mask register (HDM) [Address 0..4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.1.2 Cell copy header value register (CCHV) [Address 5..8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.1.3 Cell copy nibble mask register (CCNM) [Address 9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1.4 Cell copy low index (CCLI) [Address 10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1.5 Cell copy high index (CCHI) [Address 11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1.6 DRAM CAS additional delay register (DCAD) [Address 12] . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1.7 DRAM RAS additional delay register (DRAD) [Address 13] . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1.8 Dynamic ram control register 1 (DRC1) [Address 14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1.9 Revision number/Utopia output FIFO register (RN/UOF) [Address 15] . . . . . . . . . . . . . . . . . . . 51
14.1.10Input control register (IOC) [Address 16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14.1.11Interrupt control register (IC) [Address 17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14.1.12Dynamic ram control register 2 (DRC2) [Address 18] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
14.1.13Class select register (CLA) [Address 19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
14.1.14Leaky Bucket parameter select register (CSL) [Address 20..23] . . . . . . . . . . . . . . . . . . . . . . . 52
14.1.15Leaky Bucket control register 1 (LBC1) [Address 24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.1.16Leaky Bucket 2/RxEnb control register (LBC2) [Address 25] . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.1.17Parameter set control register (PSC) [Address 26] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.1.18Cell out control register (COLB) [Address 27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.1.19Transfer control register (TRC) [Address 48] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.1.20Input status register (IS) [Address 49] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.2 All purpose data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.2.1 Transferring from or to class lookup table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.2.2 Transferring from/to memory using class lookup table transfer command: . . . . . . . . . . . . . . . . . . 55
14.2.3 Transferring from or to on chip Leaky Bucket Level RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.2.4 Transferring from/to Leaky Bucket Parameter set in internal or external RAM . . . . . . . . . . . . . . . . 56
14.2.5 Transferring from/to Leaky Bucket Parameter set pointer table in external RAM . . . . . . . . . . . . . . . 56
14.2.6 Transferring from/to on chip queue control RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.2.7 Transferring from/to the cell interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.2.8 Transferring from/to the output port table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
November 9, 2000
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
15 Signal description 59
15.1ATMinputport..................................................... 59
15.2ATMoutputports.................................................... 59
15.3 Dynamic memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.4 Static memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.5 Microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.6 Parameter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.7Statusport........................................................ 60
15.8Extracellport...................................................... 61
15.9Systemsignals ..................................................... 61
15.10JTAGsignals ...................................................... 61
16 Pin Configuration 62
16.1 Pin Diagram: 208 Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
16.2PinDescription..................................................... 62
17 Mechanical Information 67
18 Timing diagrams 68
18.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
18.1.1 Read Cycle - Motorola and Intel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
18.1.2 Write Cycle - Motorola Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
18.1.3 Write Cycle - Intel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
18.2 DRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
19 Electrical Characteristics 75
19.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
19.2 Recommended Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
19.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
20 Thermal data 76
21 Application notes 76
21.1 Connecting the power and ground pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
22 Addendum 77
22.1 Connecting the SHAP4-B to the standard Utopia interface level 1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 77
22.1.1 Single port PHY input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
22.1.2 Utopia level-2 PHY input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
22.1.3 Multi level-1 PHY inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
23 Migration of the SHAP4 into the SHAP4-B 81
23.1Majorchanges...................................................... 81
23.2Listofitems....................................................... 81
23.3 SW change when using the SHAP4-B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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November 9, 2000
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
List of Figures
1Block diagram SHAP4-B ................................................ 8
2Data flow through the SHAP4-B ............................................ 9
3Input interface timing single port mode ......................................... 10
4Input interface timing multiple port mode example 1 .................................. 11
5Input interface timing multiple port mode example 2 .................................. 12
653 Byte cell format ................................................... 13
753 Byte + 3 routing tag bytes cell format ........................................ 13
856 Byte cell format ................................................... 14
9Output interface timing single port mode ........................................ 15
10 Output interface timing multiple port mode example 1 ................................. 16
11 Output interface timing multiple port mode example 2 ................................. 17
12 Single Leaky Bucket with CDV of zero ......................................... 21
13 Single Leaky Bucket with a CDV of three cell times .................................. 21
14 Single Leaky Bucket with a CDV of two cell times ................................... 22
15 Typical level behavior .................................................. 22
16 Single Leaky Bucket with burst ............................................. 24
17 Dual Leaky Bucket without CDV ............................................ 24
18 Dual Leaky Bucket with CDV .............................................. 25
19 Collision without CDV ................................................. 28
20 Collision with CDV of one ............................................... 28
21 Header extraction mask plus port id .......................................... 32
22 Par_inc, Par_dec signal timing ............................................. 36
23 Linear rate change ................................................... 37
24 Logarithmic rate change ................................................ 38
25 Pi–Curve rate change .................................................. 39
26 Faster access to SHAP4-B data ............................................. 39
27 Cell copy interface timing, copy 4 bytes ........................................ 41
28 Cell copy interface timing, copy single byte ...................................... 41
29 Status interface timing ................................................. 42
30 Memory configuration with one bank .......................................... 47
31 Memory configuration with two banks ......................................... 47
32 Static RAM connected to SHAP4-B ........................................... 48
33 Pin Diagram SHAP4-B ................................................. 62
34 208 Pin Copper Leadframe Short Plastic Quad Flat Pack ............................... 67
35 Microprocessor read timing ............................................... 68
36 Microprocessor write timing - Motorola Mode ..................................... 69
37 Microprocessor write timing - Intel Mode ....................................... 70
38 Timing diagram read cell of the DRAM ......................................... 70
39 Timing diagram write cell of the DRAM ........................................ 71
40 Microprocessor word read from dram memory ..................................... 71
41 Microprocessor word write to dram memory ...................................... 72
42 Timing diagram refresh of the DRAM .......................................... 72
43 Timing diagram System Clock and Reset ........................................ 73
44 Timing diagram JTAG Port ............................................... 74
45 Decoupling the power and ground pads ........................................ 76
46 Single port PHY TX interface ............................................. 77
47 Multiple port PHY TX interface, example 1 ...................................... 78
48 Multiple port PHY TX interface, (The clock line is drawn dashed to make it easier to follow all the signals in the
picture.) ......................................................... 80
November 9, 2000
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Page 7 of 82
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
1 General description
The idea of traffic shaping in ATM is well known. However there are numerous ways to perform traffic shaping. This document
describes how traffic shaping is done by the ATecoM SHAP4-B device.
Figure 1 depicts the block diagram of the SHAP4-B:
ATM
input
DRAM
1M-128M
Memory
controller output
ATM
Queue
controller
header extract
Assign to
class
Special cell Processor register queue
statusoutput
(optional)
SRAM
32Kx8
Priority
control
Shaping
function
Figure 1: Block diagram SHAP4-B
1.1 Shaping function
The SHAP4-B is a device that allows an incoming ATM cell stream to be output with a pre-defined rate. To do so the cell stream is
split into 32 traffic classes. For each class the following parameters can be set:
Peak Cell Rate output (PCR)
Sustainable Cell Rate output (SCR)
Maximum Burst size at PCR output (MBS)
CLP bit handling
Amount of memory used by the class
Priority within the classes
The output rate is controlled according to one of two Shaper functions both based on the Leaky Bucket algorithm namely the Single
Leaky Bucket and the Dual Leaky Bucket.
The SHAP4-B operates using a number of classes. Up to 24 bits of the arriving cell header are extracted and presented to a lookup
table in the main memory. The class to which the cell belongs is extracted from the table. The cells of each class are stored in a
queue that is also held in the external memory. Arriving cells are stored until the queue is full. If a queue is full and more cells
arrive they are discarded. A counter keeps track of the number of discarded cells. Each class has a Shaper function assigned to it.
The Shaper function determines when a cell is allowed to leave the queue. Each class has one of the four outputs assigned to it.
Thus the SHAP4-B can be seen as a (limited) 4x4 switch with 200 Mbit/sec (with special DRAMs 320 Mbit/sec) throughput.
Page 8 of 82
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November 9, 2000
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
The SHAP4-B has several queues thus it can happen that multiple Shaper functions signal that a cell should be output. If multiple
requests to output a cell are made, a priority function decides which request is honored. The device supports static priorities, round
robin priorities and a special group shaping mode.
To support flow control the device allows the rate at which data is output to be changed under hardware or software control by
selecting one of 32 pre-defined rates per class.
Beside shaping an ATM stream passing through the device, it is also possible to start or terminate a stream at the device. This allows
the SHAP4-B to be used as Traffic Generator, Traffic analyzer or low speed AAL0.
1.2 Data flow
The SHAP4-B supports up to four input streams and four output streams. However at any time only one input stream or output
stream is active. Also the throughput of the device is maximum 200 (320) Mbit/sec.
A cell is read from an input stream. Next it is determined to which class the cell belongs. To do this up to 24 bits can be extracted
from the cell header. To these bits the number of the input port at which the cell arrived can be added (programmable). This gives a
value from 0 to 26 bits. This value is used to address an entry in the lookup table where the related class number is stored. If there
is room for the cell it is stored in the queue of that class.
Each class has an output port assigned at which the cells are output. Thus once a cell is assigned to a class it will also arrive at the
output port for that class and it can no longer be re-routed to a different output port. The output port can be set by the user for each
class independently. Figure 2 gives a schematic overview of the data flow.
look-up
table
number
class
output
use as
address
number
input
port
header
extract
class has
one output port
Four
ports
Four
ports
Figure 2: Data flow through the SHAP4-B
2 ATM ports
The SHAP4-B supports the SAI- and the Utopia interface. The input port is decoupled from the rest of the chip through a four cell
FIFO. Cells will first be completely stored in the FIFO before they are handled by the device. The output of the SHAP4-B can be
stopped in which case new arriving cells are stored in the queues. The SHAP4-B can work with a 53 or 56 byte cell stream. In the
56 byte mode the first 3 bytes may be used for a routing tag. It is also possible to convert 56 byte cells to 53 byte cells and vice
versa.
2.1 Input port
The input port of the SHAP4-B has the following properties:
Supports up to four Utopia level-1 interfaces
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Can work on a continuous or discontinuous cell stream
Can be enabled or disabled
Can check or ignore an incoming HEC
Can pass or remove incoming idle cells
Can work on 53 or 56 byte cells
Can insert a three byte time stamp at the end of the cell when running in 53 byte cell mode
Can convert from 56 to 53 byte cell format
Bit 0 of the
IOC register
enables or disables the input port.
If bit 0 of the
IOC register
is cleared all incoming cells are discarded.
If bit 0 of the
IOC register
is set the input port is enabled.
The input port of the device is decoupled through a four cell on chip FIFO. The FIFO is used for clock decoupling only and not for
rate adaptation.
2.1.1 Multi Physical Utopia Level-1 input interface
Up to four devices can be connected to the input interface of the SHAP4-B. The input interface supports gaps of arbitrary length.
Single Port Mode In single port mode only the signals concerning port 0 (RX(0)) are used. RxClav(3..1) must be connected to
GND. RxClav(0) is set from the external device to indicate that a whole cell can be sent. RxEnb*(0) set by SHAP4-B indicates that
a whole cell can be received. After asserting RxEnb*(0) SHAP4-B expects the Start Of Cell-signal (RxSOC).
Example:
Figure 3: At clock cycle 2 the SHAP4-B detects that the connected device can sent a cell (RxClav(0) is set). In cycle (4) RxEnb*(0)
deassertion is recognized by the external device. After RxEnb*(0) is received the external device has to sent the first data byte and
the RxSOC signal.
Figure 3: Input interface timing single port mode
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Multiple Port Mode Up to four devices connected to the input interface are supported. RxClav(x) indicates that the corresponding
device can transmit a whole cell towards the SHAP4-B. In the case of there is only one RxClav(x) signal asserted at the same time
the input interface works similar to the single port mode. The only difference is that the data can be received from the different
connected devices. The SHAP4-B indicates by setting the RxEnb*(x)-signal that transmission can be started. One clock cycle after
a device is selected by asserting its corresponding RxEnb*(x)-signal SHAP4-B expects the assertion of RxSOC.
Example:
Figure 4: Consider two devices connected to the input ports of SHAP4-B. At clock cycle 2 SHAP4-B detects the valid RxClav(0)
signal. RxEnb*(0) is asserted while RxEnb*(1) is deasserted. Device0 asserts its RxSOC(0) signal and starts transmitting a cell
(clock cycle 4). While device0 is sending the RxSOC(1) and RxData(1) ports must be tristate. At clock cycle 55 device0 signals by
its deasserted RxClav-signal that it can not sent an additional cell. But device1 is ready to send a cell (indicated through its RxClav-
signal set). At clock cycle 56 device0 is de-selected and device1 is selected (setting respectively resetting their corresponding
RxEnb*(x) signals. With rising edge of clock cycle 57 device1 starts transmitting data. The RxData(0) and RxSOC(0) signals are
tristate.
Figure 4: Input interface timing multiple port mode example 1
In the case of different input devices are able to transfer a whole cell towards SHAP4-B at the same time (indicated by their
RxClav(x)-signal set) one device must be polled. This is done by asserting its corresponding RxEnb*(x)-signal using the Round
Robin algorithm.
Example:
Figure 5: Two devices (device0 and device1) are connected to SHAP4-B. At clock cycle 1 device1 is sending. At clock cycle 2
SHAP4-B detects that both devices are able to transmit a cell( indicated due their RxClav signals set). As device1 was last selected
the next cell is received from device0. At clock cycle 55 SHAP4-B recognizes that both devices are still able to sent. Because
device0 was polled last time this time device1 is selected by asserting its RxEnb*(1)-signal.
2.1.2 Cell alignment
In ATM two different cell streams are possible:
systems where a continuous cell stream is present and all space between cells containing valid data is filled with idle cells.
systems with a discontinuous cell stream where the cell stream will contain gaps of arbitrary length.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 5: Input interface timing multiple port mode example 2
The input port works correctly on both types of data streams. In all cases the start of a cell is marked with the so called Start Of Cell
signal that is active during the arrival of the first byte of a cell. When the first byte has entered the device the following 52 (or 55)
bytes are assumed to belong to the same cell and are stored accordingly. If another cell sync arrives during the loading of these 52
(or 55) bytes, this signal is ignored. The event is registered in the
input status register
and can provide an interrupt, signaling that
an early sync has been detected.
The input port can also notice if there is no cell sync immediately following the last loaded cell byte: Late Sync Detection. This is
an error when a continuous cell stream should be present. This event can also be registered in the
input status register
and can also
provide an interrupt signal. Systems working with a discontinuous cell stream should simply ignore this status bit.
2.1.3 Idle cells
The input port can remove incoming idle cells or pass them on. If idle cell detection is switched on, the device checks whether an
incoming cell has an idle cell header (first four octets) or not. Idle cells are discarded and are not passed through the device. If idle
cell detection is switched off all cells are handled by the device.
Bit 2 of the
IOC register
controls the storage of idle cells.
If bit 2 of the
IOC register
is cleared idle cells are treated as normal data cells.
If bit 2 of the
IOC register
is set idle cells are removed from the data stream.
2.1.4 HEC check
The input port can check the cell HEC field and discard the cell if an HEC error occurs. It is not possible to correct the HEC field.
This HEC check option can be disabled, allowing the HEC position to contain arbitrary data.
Bit 1 of the
IOC register
controls the check of the cell header.
If bit 1 of the
IOC register
is cleared the HEC byte is ignored.
If bit 1 of the
IOC register
is set the HEC is checked against the HEC-byte. If a HEC error occurs the cell is discarded.
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2.1.5 Cell format
The input controller supports three different cell formats:
53 byte cells
53 byte cells with 3 leading tag bytes
56 byte cells
It can also perform cell format conversion from 56 to 53 bytes. In this mode the first three octets of each cell are removed and the
system clock must fulfill the following condition:
!
"
Bits 5 and 6 of the
IOC register
control the type of cells coming into the device:
IOC [6:5] Input cell type Write to RAM
00 53 bytes 53 bytes + 24 bit time stamp
01 53 bytes + 3 tag bytes 53 bytes + 24 bit time stamp
10 56 bytes 56 bytes
11 53 bytes + 3 tag bytes 53 bytes + 3 tag bytes
The three different cell formats are shown below:
Figure 6: 53 Byte cell format
Figure 7: 53 Byte + 3 routing tag bytes cell format
The difference between a 56-byte cell and a 53+3 tag bytes cell is the location of the header in the cell stream. This is important as
the SHAP4-B uses the information in the header to assign cells to a certain queue.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 8: 56 Byte cell format
2.1.6 Time stamp
As described above the controller can write a 24 bit time stamp indicating the arrival time of the cell in the memory. For this time
stamp two different resolutions are available:
If bit 4 of the
IOC register
is cleared the time stamp counter is incremented each RxClk.
If bit 4 of the
IOC register
is set the time stamp counter is incremented once every 53 or every 56 RxClk cycles depending on
the selected input cell format.
An incrementeveryRxClk cycles provides the best accuracy. However the time stampcounter will roll over after sometime. Before
this happens a cell must have arrived. Thus the minimum distance between cells must be
RxClk cycles. This is about one cell
every second. An increment every cell time allows a longer period of non-arriving cells: 53 or 56 seconds.
2.1.7 Input status
The device has a register that reflects the status of the input port. The following events can be noticed:
Early cell sync
Late cell sync
Missing RxClk
Discarded cell counter rollover
FIFO level high
FIFO overflow
Early cell sync and late cell sync have been explained in the chapter about cell alignment.
Missing RxClk The incoming RxClk clock is checked against the system clock. If the incoming RxClk clock is not present for
32 system clock cycles the missing RxClk clock bit will be set.
Discarded cell counter overflow Each queue has a counter counting the number of discarded cells. This counter can be pro-
grammed to stay at it’s maximum value or roll over and set a status bit. There is only a single status bit for all counters.
FIFO level high A FIFO level high occurs when more than two cells are in the input FIFO. The reason may be that the input cell
rate is higher than the output cell rate.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
FIFO overflow A FIFO overflow occurs when the input data rate is higher than the output data rate. When this bit is set at least
one cell has been discarded due to the fact that the queue is full. The device has a four cell FIFO which is under normal conditions
large enough to handle clock variations and flow control between input and output. Although the device is not meant for rate
decoupling 1it can be used for that under certain conditions. It can always perform rate decoupling from a low rate towards a high
rate. If the input port removes incoming idle cells and the rate of incoming data cells is sufficient low some rate decoupling from
high to low rate can be performed.
Cells discarded due to a FIFO overflow are not counted in the class error counters.
Clearing of status bits The input status bits will remain set until cleared by a write from the microprocessor. Clearing a status
bit is done by writing a “1” to the corresponding position in the
input status register
. This “1” is not stored. It is only used to clear
the status bit. Each
input status register
has a related
interrupt control register
. When a bit in the
interrupt control register
is set the
corresponding bit in the
input status register
will cause an interrupt to occur.
2.2 Output port
The output port is 8 bits wide. It works on the system clock. As with the input port, the output port can work in continuous or
discontinuous mode. The output port has no separate cell-clock signal, the system clock can be used as the cell-clock signal instead.
2.2.1 Multi Physical Utopia Level-1 output interface
Up to four devices can be supported. The cells for each output Port (Tx(x)) are stored in a separate FIFO according to that port. The
output interface supports only gaps of multiple cell lengths.
Single port mode In single port mode only the signals concerning port 0 (Tx(0)) are used. The TxClav(1..3) signals must be
connected to GND. TxClav(0) is set from the external device to indicate that a whole cell can be received. If a complete cell can be
transmitted one clock cycle after detection of TxClav(0) SHAP4-B sends the Start Of Cell-signal (TxSOC(0)). TxEnb*(0) set by
SHAP4-B indicates that valid data is transmitted. SHAP4-B can be forced to stop sending by deasserting TxClav(0) before the last
octet of the current output cell is transmitted. One clock cycle after detecting TxClav (0) deasserted, TxEnb*(0) is deasserted by
SHAP4-B. An idle cell is transmitted or a gap of one cell cycle is produced.
Example:
Figure 9: One clock cycle after TxClav(0) is asserted, the SHAP4-B starts transmitting a cell.
Figure 9: Output interface timing single port mode
1For real rate decoupling much larger FIFOs are needed.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Multiple port mode In multiple port mode two conditions must be fulfilled to transmit a cell towards an output port.
1. A cell must be stored in the internal FIFO of that output.
2. The according TxClav(x)-signal of the output port must be set.
If both conditions are true, transmission starts with sending the corresponding TxSOC(x)-signal of that output and asserting the
corresponding TxEnb*(x)-signal. SHAP4-B can be forced to stop sending by deasserting TxClav(x) before the last byte of the
current output cell is transmitted. One clock cycle after detecting deassertion of TxClav, TxEnb*(x) is deasserted by SHAP4-B. If
the above conditions are not fulfilled for another output port an idle cell is transmitted or a gap of one cell is produced.
Example:
Figure 10: Two devices are connected to output port0 and output port1 respectively. Cells are only stored in FIFO1. Although both
device are able to receive cells (cycle 3) data can only be forwarded to port1 because only this FIFO contains a valid cell. At clock
cycle 56 SHAP4-B detects that device1 is unable to continue receiving. This leads to deassertion of TxEnb*(1) and production of a
gap of one cell.
Figure 10: Output interface timing multiple port mode example 1
Since the cells concerning the four output ports are stored internally into FIFOs it is possible that at the same time more than one
output port fulfills the above conditions. In that case the sending output port is selected by using the Round Robin algorithm.
Example:
Figure 11: Beginning with rising edge of clock cycle 4 device 1 is selected for receiving a cell. During this cell cycle a cell is
stored in FIFO 0 but the correspondingdevice is not able to receive a cell (indicated by TxClav(0)keeping deasserted). As result no
transmission starts a clock cycle 57. A gap of one cell is produced. The next cell cycle one cell is stored in FIFO 1. At clock cycle
110 both devices are able to receive a cell (indicated by assertion of TxClav(1) and TxClav(0)) and both internal FIFOs are filled.
In the following clock cycle (110) device0 is selected to receive a cell (through assertion of its TxEnb*(0) signal), because device1
has received the last transmitted valid cell.
2.2.2 Idle cell production
In continuous mode the output generates idle cells if no cell is allowed to leave the SHAP4-B or all the queues are empty. In
discontinuous mode the device outputs no data if no cell is available. In that case there will be gaps between the cells. The gaps
will always be 53 (or 56) bytes long as the SHAP4-B works on cell slot basis. This means that the SHAP4-B aligns all cells on 53
(or 56) system clock cycle intervals. In one interval either a cell will leave the SHAP4-B or not.
Bit 0 of the
COLB register
controls the generation of idle cells.
If bit 0 of the
COLB register
is cleared idle cells are not producedat the output and there will be gaps between cells if no data
cell is output
If bit 0 of the
COLB register
is set an idle cell is generated at the output port if no data cell is output
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 11: Output interface timing multiple port mode example 2
2.2.3 Output cell format
The
output control register
determines the output cell format of the SHAP4-B.
Bit 1 of the
COLB register
controls the type of cells leaving the device:
If bit 1 of the
COLB register
is cleared cells of 53 bytes leave the SHAP4-B.
If bit 1 of the
COLB register
is set cells of 56 bytes leave the SHAP4-B.
This bit also influences the rate of the SHAP4-B related to the system clock. The Leaky Bucket calculations are performedonce per
cell time. For an outgoing cell format of 53 bytes a cell time equals 53 system clock cycles. For an outgoing cell format of 56 bytes
a cell time equals 56 system clock cycles.
This bit should only be changed during initialization of the SHAP4-B. It is not allowed
to change this bit while the cell stream is running
.
Note that the outgoing cell format is independent of the incoming cell format.
The cell type of the
IOC register
specifies the cell format stored in the memory. Bit 1 of the
COLB register
specifies the format of
the outgoing cell. These two functions are completely independentalthough some combinations give strange results like:
Input cell size is 56 bytes but output format is 53 bytes. In this case the last 3 bytes of a cell are lost.
Input format is 53 bytes, output format is 56 bytes. The cell will contain 3 extra bytes at the end which hold the 24 bit time
stamp.
(Note that to operate in this mode the following condition must be fulfilled:
"
!
"
)
As the SHAP4-B can work with two differentcell sizes throughout this document the description53 (or 56) is found. If the cell size
programmed in the ATM
output control register
is 53 the system works in a cadence of 53 clock cycles. Thus storing and reading a
cell takes 53 clock cycles, a refresh is performed every
clock cycles, a class increment or decrement can be performed once
every 53 clock cycles, etc. If the programmed cell size in the ATM
output control register
is 56 the system works in a cadence of
56 clock cycles.
Note that the input stage of the SHAP4-B works on the RxClk and thus runs independent from the rest of the chip.
2.2.4 Idle cell format
As the 56 byte cell is non-standard there is no idle cell format defined for such cell sizes. The SHAP4-B provides two different cell
formats for idle cells:
If bit 2 of the
COLB register
is cleared an idle cell consists of 3 routing tag bytes all zero followed by a normal 53 byte idle
cell pattern.
If bit 2 of the
COLB register
is set an idle cell starts as a normal idle cell but with 51 bytes of idle cell payload.
If the cell size is 53 bytes (bit 1 of the
COLB register
is cleared) bit 2 is don’t care. Otherwise bit 2 specifies the 56 byte idle cell
format.
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Page 17 of 82
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
2.2.5 Circular mode
Circular mode is provided to use the SHAP4-B as a continuous traffic generator device. The device supports beside the normal
operation mode three circular modes. In normal mode cells are read from a queue as long as the queue holds data. This guarantees
that the SHAP4-B will not output any cells if the queue is empty. In circular mode this protection is disabled for some, or all the
queues. As a consequence the SHAP4-B will output all cells from a queue and then start reading at the beginning again. In this
mode the SHAP4-B will transmit the complete queue contents over and over again. No other aspect of the SHAP4-B is changed.
Those queues which are not in circular mode function normally.
Bits 5 and 6 of the
COLB register
control the circular modes:
COLB [6:5] Operation mode
00 Normal operation, All queues in normal mode.
01 Queue 0 in circular mode, Queue 1..31 in normal mode.
10 Queue 8..23 in circular mode, Queue 0..7 and 24..31 in normal mode.
11 All queues in circular mode.
2.2.6 Utopia output FIFO control
Each Utopia output port has a FIFO where one cell can be temporarily be stored. The cell coming from the external dram is stored
in this FIFO first. When the Utopia handshake signals allow to send a cell, this cell is sent to the output port. These fifos are
directly controlled by the ATM output block which can be seen in figure 1. If one of the four Utopia ports are stopped by the
Utopia handshake it may happen that one cell is remaining in this Utopia output FIFO. There is a special register called Revision
number/Utopia FIFO out register where the status of these fifos can be checked.
If bit 4..7 of the
RN/UOF register
is set a cell is stored in the corresponding Utopia output port FIFO 0..3.
If bit 4..7 of the
RN/UOF register
is cleared no cell is stored in the correspondingUtopia output port FIFO 0..3.
So it may happen that a cell is stored in the FIFO and the port is not needed any more. In this case it is possible to clear the cell in
this FIFO by writing a one to the
RN/UOF register
.
Writing a one to bit 4..7 of the
RN/UOF register
will clear the cell stored in the corresponding Utopia output port FIFO 0..3.
Writing a zero will have no effect.
Please keep in mind that it is only useful to clear the Utopia output port FIFO when no cells are transmitted via this port. Setting bit
4..7 of the
RN/UOF register
while the corresponding port is active may result in a cell loss.
3 Shaping function
The shaper function determines the characteristic of the outgoing data stream. Two operation modes are available: Dual Leaky
Bucket or single Leaky Bucket mode. The Leaky Bucket mode is determined by bit 7 of the
Leaky Bucket control register
. In dual
Leaky Bucket mode each class has one dual Leaky Bucket parameter (if the external SRAM is used up to 32 dual Leaky Bucket
parameter per class). In single Leaky Bucket mode each class has two single Leaky Bucket parameters (if the external SRAM is
used up to 64 single Leaky Bucket parameter per class). This mode allows output control with two different single Leaky Bucket
parameters without the need of the external parameter RAM.
In single Leaky Bucket the output rate is controlled with a single Leaky Bucket. This allows a user to set the Peak Cell Rate (PCR)
and the Cell Delay Variation (CDV) of the outgoing cell stream.
In dual Leaky Bucket mode the output rate is controlled with two Leaky Buckets in parallel. A cell is output if both Leaky Buckets
give their OK. This allows cells to be output at a specified Peak Cell rate, Sustainable Cell Rate, Maximum Burst Size at PCR and
CDV. This gives a three stage rate control.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
3.1 Rate parameters
The output rate is based on the system clock together with the cell size. The Leaky Bucket calculations are performed once per cell
time. For a 53 byte outgoing cell size a cell time equals 53 system clock cycles. For a 56 byte outgoing cell size a cell time equals
56 system clock cycles.
Example 1:
System clock = 19.44 MHz
Cell size = 53 bytes
System rate is 19.44 106 Hz/53 bytes = 366792 cells/sec (=155.52 Mbit/sec)
Example 2:
System clock = 23 MHz
Cell size = 53 bytes
System rate is 23 106Hz/53 bytes = 433962 cells /sec (=184 Mbit/sec)
Based on that, the rate is further determined by the following parameters:
Limit:
The bucket limit together with the splash determines the maximum burst size that can be output (
). The bucket limit
value is 24 bits wide. As long as the level is below or equal to the limit a cell is allowed to leave the queue.
Splash:
This value together with the leak determines the output rate. This value is 8 bits wide. The splash is the amount added to the level
for each cell allowed to leave the queue. The splash is only added if a cell is actually leaving the queue. Not if a cell-request is
made.
Leak:
The leak is the amount with which the level is decreased per cell time. The leak parameter is often taken to be 1 and therefore not
explicitly mentioned in numerous descriptions of the Leaky Bucket algorithm. This register together with the splash determines the
output rate. The leak value is stored in a coded 4 bit format. The table below shows how the leak rate is coded.
Leak Leak
Code rate Code rate
0x0 128 0x8 1/2
0x1 64 0x9 1/4
0x2 32 0xA 1/8
0x3 16 0xB 1/16
0x4 8 0xC 1/32
0x5 4 0xD 1/64
0x6 2 0xE 1/128
0x7 1 0xF 0
Level:
The level is changing depending on the cell flow and the other three parameters Limit, Splash and Leak. This value is 31 bits
wide where 7 bits are fraction bits (because the minimum Leak is 1/128) The Level can be preset by the user when setting up a
connection. This can be used to avoid that the first cells of this connection are output back to back (if CDV is allowed).
3.2 Special rates
3.2.1 Full data stream
The SHAP4-B can be programmed to pass all cells of a dedicated class. No shaping is performed. The Leaky Bucket parameter for
that class would be:
Bucket limit = 0xFFFFFF
Splash = 0x0
Leak code = 0xF (no leaking)
Level = don’t care
So the Level is always lower than or equal to the Limit. In dual Leaky Bucket mode both parameters should be programmed this
way.
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Page 19 of 82
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
3.2.2 Stop data stream
The SHAP4-B can be programmed to stop the data stream of a dedicated class. The Leaky Bucket parameter would be:
Bucket limit = 0x0
Splash = 0x0
Leak code = 0xF (no leaking)
Level = 0xFFFFFF
So the Level is always higher than the Limit. In dual Leaky Bucket mode only one parameter need to be programmed this way.
3.3 Single Leaky Bucket
3.3.1 Rate control
The Peak Cell Rate (PCR) is set with the leak and splash parameters according to:
The splash is normally chosen in the range 128..255 because this gives the best accuracy. A rate change is then possible in steps of
(accuracy 0.78
) to
(accuracy
).
The minimum PCR can then be calculated from the minimum leak and maximum splash:
.
With a link rate of 155 Mbit/sec this gives a minimum rate of 4.8 Kbits/sec. It is also possible to select a splash from a different
range e.g. 64..127 or 32..63. The accuracy is then
or
. Several accuracy values are available between
and
.
For example: With an accuracy
we have the following parameters:
Minimum rate 38 Kbit/sec
Maximum rate 155 Mbit/sec
Maximum number of consecutive cells: 256K
The maximum number of consecutive cells is determined by:
! "
#
#
%$
"
&
('
*),+
.-
&
/)0+
132
4
At all rates a number of 64K consecutive cells can be obtained. If the limit is set to zero the number of consecutive cells is one. In
this case the SHAP4-B tries to output all cells equidistant (spacer 2). It is still possible that due to a higher priority class, cells will
leave the SHAP4-B not equidistant. This is not the case for class zero in absolute priority mode as there is no class with a higher
priority.
The CDV generated by the Leaky Bucket is determined by:
65879
&
"
()
;:
"
3<=
"
6587
?>
2
+
4
6587
The CDV is defined to be a positive integer in cell time units.
Note that CDV and the maximum number of consecutive can not be set independently.
The minimum CDV is zero (limit = 0). The maximum CDV depends on the leak rate and the limit. From the formula it can be seen
that the largest CDV is reached with low leak rates or a high limit.
If the leak rate and the CDV are given the necessary limit can be calculated by the formula:
A@
+
CB
+ED
6587GF
The single Leaky Bucket controls PCR and CDV. The Leaky Bucket implementation of ATecoM outputs a cell from the SHAP4-B
if the level is below or equal to the limit. Thus if the limit is set to zero cells are still allowed to leave the SHAP4-B.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 12: Single Leaky Bucket with CDV of zero
Figure 13: Single Leaky Bucket with a CDV of three cell times
3.3.2 Examples
With a limit set to zero the CDV is zero (See formulas above). Thus all cells will leave the SHAP4-B equidistant. Figure 12 shows
how the level changes as function of the parameters with a limit of zero.
With a limit of three we get a CDV of three cell times (two consecutive cells). Figure 13 shows this case.
If we have Leak=1, Splash=4, Limit=2 we get a CDV of two cell times and a number of consecutive cells of one (Figure 14).
Consecutive cells could be sent only if the level is dropped far enough below the limit to allow one or more cells. This happens if
no cells are output for some time.
There are three cases when no cell is output although the shaper function requests one:
1. There are no more cells in the queue.
2. Cells are output from another class.
3. The output from the SHAP4-B is halted (TxClav signal is low).
The first case happens if the queue is empty, which can only happen if no new cells arrive for the class. Thus an output burst will
appear if several cells arrive at the input of the class after a period of rest. The second case can happen at all times except for the
class with the highest priority. The third case depends on the hardware configuration in which the device is used. Figure 15 shows
a typical figure of the SHAP4-B output when a large burst of cells arrive. At the moment the burst arrives the bucket level is zero.
This is the case if the class has been enabled recently or the queue has been empty for some time.
2Note that a cell shaper is more powerful than a spacer.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 14: Single Leaky Bucket with a CDV of two cell times
Figure 15: Typical level behavior
The level is far belowthe limit thus a large bursts of cells is output while the level rises to the limit. When the limit has been reached
the PCR of 1:4 is active unless one of the three cases described above occurs. If no cells are sent for some period the level drops
as the bucket is leaking continuously. When cells can be output again, a burst of cells is sent until the limit has been reached again.
The setting of a certain CDV can also be used to output a more regular cell flow when more than one class is active. In chapter 4.2
an example is given.
In case of large CDV values generatedby the single Leaky Bucket algorithm a lot of cells are output consecutively. The disadvantage
is that all these cells are output with the full link rate. This is often intolerable.
3.4 Dual Leaky Bucket
With a single Leaky Bucket the Peak Cell Rate (PCR) and the CDV can be controlled. However the Maximum Burst Size (MBS) at
PCR and the Sustainable Cell Rate can not be controlled. To control all four parameters a dual Leaky Bucket shaper is needed.
3.4.1 Rate control
The Peak Cell Rate (PCR) is set with the leak2 and splash2 (of Leaky Bucket2) parameters according to:
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The Sustainable Cell Rate (SCR) is set with the leak1 and splash1 (of Leaky Bucket1) parameters according to:
The splash is normally chosen in the range 128..255 because this gives the best accuracy. A rate change is then possible in steps of
(accuracy
) to
(accuracy
).
The minimum PCR and SCR can then be calculated from the minimum leak and maximum splash:
.
With a link rate of 155 Mbit/sec this gives a minimum rate of 4.7Kbit/sec.
The Maximum Burst Size (MBS) at PCR cells is determined by:
'
"
+
The CDV generated by the Leaky Bucket is determined by:
65879
&
)
;:
3<=
6587
>
2
+
4
6587
The CDV is defined to be a positive integer in cell time units.
The minimum CDV is zero (limit = 0). The maximum CDV depends on the leak2 rate and the limit2. From the formula it can be
seen that the largest CDV is reached with low leak2 rates or a high limit2.
If the leak rate and the CDV are given the necessary limit2 can be calculated by the formula:
@
+
CB
+ED
65876F
Setting a CDV results in a maximum number of consecutive cells:
! "
#
%$
&
'
"
),+
.-
&
),+
132
4
Note that CDV and the maximum number of consecutive can not be set independently.
The dual LeakyBucket mode is specially used to controlthe MBS at PCR. As discussed abovethe burst froma single Leaky Bucket
consists of consecutive cells. Thus the data is send at the full link rate. In most cases this is not tolerable. To allow not only control
of the PCR, but also of the MBS at PCR and the SCR, a second Leaky Bucket is used.
3.4.2 Examples
Assume Leaky bucket one has Splash1 = 10, Leak1 = 1, Limit1 = 9000. Thus it allows cells output at 1/10 of the link rate and
outputs 1001 consecutive cells if possible. The output is shown in Figure 16.
Assume Leaky bucket two has Splash2 = 5, leak2 = 1, Limit2 = 0. Thus it allows cells output at 1/5 of the link rate and has a
CDV of zero. The dual Leaky Bucket function outputs a cell only if both Leaky Buckets say that it is OK. Under normal operating
conditions bucket one will control the Sustainable Cell Rate (SCR) and Bucket two the Peak Cell Rate (PCR). However if the level
of bucket one is zero it allows the output of 1001 consecutive cells. This is blocked by bucket two which allows a maximum rate of
1/5 of the link rate (PCR = 1/5). Thus instead of 1001 consecutive cells, the SHAP4-B will output 1801 cells at a fifth of the link
rate (MBS = 1801) and then output all other cells at a tenth of the link rate (SCR = 1/10). This is shown in Figure 17.
An even more complicated outputfunction can be built by allowing a certain CDV. In such a case the SHAP4-B will output number
of consecutive cells at the full link rate, then go down for (MBS - number of consecutive cells) at a fifth of the link rate (PCR) and
finally settle at a tenth of the link rate (SCR). This gives an output flow in three stages from which the height of stage two and three
can be controlled. This is shown in Figure 18:
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 16: Single Leaky Bucket with burst
Figure 17: Dual Leaky Bucket without CDV
3.5 Output burst control
It is not always possible to set the two values output rate and CDV independently, namely in the case that the output rate should
be higher than 50%. For example if an output rate of 90% is programmed this would mean that one in ten cells is not a user cell.
However this also implies 9 consecutive cells. This again means a possible CDV of 0.875 cell times. Thus programming an output
rate of 90% also requires a CDV 0.875 cell times.
3.6 Cell Delay Variation
When setting the SHAP4-B parameters a user should keep in mind that the network can change the distance between cells. This is
called the cell delay variation (CDV). Thus even if the SHAP4-B outputs all the cells with equal distance, it is not guaranteed that
they also keep this distance throughout the network. Especially if the cells arrive at the UPC in the network cells can be removed
because the ’logic’ between the SHAP4-B and the UPC block in the network has changed the inter-cell distance.
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Figure 18: Dual Leaky Bucket with CDV
4 Multiple classes
4.1 Priorities setting
All the Leaky Bucket calculations for the SHAP4-B work independent from each other. As a result it can happen that at one
time several classes want to output a cell. However one cell must be selected to leave the SHAP4-B and thus an arbiter is needed to
assign the output to one of the classes. The SHAP4-B has a priority unit that solves multiple requests to output a cell. The SHAP4-B
supports a number of priority mechanisms:
Independent priority
In this mode all classes are treated separately.
Group priority
In this mode most classes are serviced in groups of three.
4.1.1 Independent priority
Static priority Using Static priority gives a known behavior of the SHAP4-B towards cell-requests. The class with the lowest
number has the highest priority. Thus class zero has priority over class one which has priority over class two, etc. Normally at least
two classes are working in static priority because time-critical cells (For example from AAL1 type traffic) must be transported over
the network with minimal delay.
Round Robin priority In round robin priority the classes are polled one after the other if a cell-request is pending. If this is the
case the selected class is allowed to send the cell. The next time the requests are started with the class followingthe one just served.
After reaching class 31 class 0 is polled again. This mechanism allows multiple classes equal access to the output port. Of course
the polling of the 32 classes is all done in one cell time.
Mixed priorities In independent priority all 32 classes are treated separately. However it is still possible to set different priorities
among the 32 classes. The following priority schemes are possible:
All static
Class 0 has highest priority. Class 31 has lowest priority.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
All round robin
All classes have equal priority and are serviced on a round-robin basis.
The classes 0..X have static priority, all other classes X..31 are round robin, but classes 0..X have priority over classes X..31.
Priority Static Round – Robin Priority Static Round – Robin
code classes classes code classes classes
0
'
0..31 17 0..16 17..31
1 0 1..31 18 0..17 18..31
2 0..1 2..31 19 0..18 19..31
3 0..2 3..31 20 0..19 20..31
4 0..3 4..31 21 0..20 21..31
5 0..4 5..31 22 0..21 22..31
6 0..5 6..31 23 0..22 23..31
7 0..6 7..31 24 0..23 24..31
8 0..7 8..31 25 0..24 25..31
9 0..8 9..31 26 0..25 26..31
10 0..9 10..31 27 0..26 27..31
11 0..10 11..31 28 0..27 28..31
12 0..11 12..31 29 0..28 29..31
13 0..12 13..31 30 0..29 30..31
14 0..13 14..31 31 0..30 31
15 0..14 15..31 32 0..31
'
16 0..15 16..31
4.1.2 Group priority
In group priority mode the 32 classes are arranged in 10 groups each consisting of 3 classes and two groups consisting of 1 class.
In group mode only 22 shaping functions are active. The classes 0 and 1 are exceptions as they work in independent priority mode.
You could see it as two special ’groups’ consisting of a single class. The other classes form 10 groups each consisting of 3 classes.
This leads to the following set of groups:
Static priority :
Group Queues Shaping
parameter
0 0 0
1 1 1
Round Robin priority :
Group Queue Group shaping Medium shaping
Qa, Qb, Qc parameter parameter (Qb)
(Qa & Qb & Qc)
2 2+3+22 2 3
3 4+5+23 4 5
4 6+7+24 6 7
5 8+9+25 8 9
6 10+11+26 10 11
7 12+13+27 12 13
8 14+15+28 14 15
9 16+17+29 16 17
10 18+19+30 18 19
11 20+21+31 20 21
As can be seen from the table the groups 2-11 each have two shaping functions:
A group shaper
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A medium shaper
The group shaper determines the output rate of the cells for an entire group. Within a group the classes are serviced with static
priority. The class with the lowest number has the highest priority and is serviced first. If this class with the lowest number is empty
the medium class is serviced.
The medium class has an additional shaping function that controls the output rate for the medium class. The output rate for this
class is thus determined by the rate of both the group shaper and the medium shaper. For sensible functioning the output rate set by
the medium shaping function should be lower than (or maximum equal to) the rate of the group shaping function.
The class with the highest number has the lowest priority and is serviced last. Thus for a cell to leave this class the following
conditions must be true:
The high priority class must be empty
The medium priority class must be either empty or
the medium shaping function specifies that no cell is allowed to leave
Of course a cell is only allowed to leave any of the three classes if the output for that class is enabled. The truth table below shows
when a cell is allowed to leave the queue. The table has 6 conditions that we specify as:
Qa, Qb, Qc If a queue has data in it (Qa is highest, Qc is lowest priority).
Out If the output can accept a cell. (Depends on the output port assigned to the class).
GSF If the group shaping function gives an OK to output a cell.
MSF If the medium shaper function gives an OK to output a cell.
GSF MSF Out Qa Qb Qc Output
0 x x x x x
'
x x 0 x x x
'
1 x 1 1 x x Qa
x x x 0 0 0
'
1 0 1 0 1 0
'
1 x 1 0 0 1 Qc
1 0 1 0 x 1 Qc
1 1 1 0 1 x Qb
Note that the medium class has two shaping functions each having the dual Leaky Bucket algorithm. For Qb the group shaping
function and the medium shaping function must both allow to output a cell. Thus if the other two classes (Qa, Qc) of the group are
not used this allows a user to set up a class controlled by four Leaky Buckets. Figure 18 shows how a dual Leaky Bucket allows a
three-step output rate. A quad Leaky Bucket function allows the output rate to be controlled in five steps.
4.2 Queue output conflicts
The SHAP4-B is normally used with more than one active class. As described above the classes will influence each other when
cells should be output. If no measurements are taken some nasty side-effects can occur. Below we give an example of two classes
where one is heavily distorted by the other.
We have one class sending cells at a ratio 1:4 (One cell in 4 time frames), CDV 0 which has a high priority and a second class
sending cells at a ratio 1:3, CDV 0 with a lower priority. At some moment both want to output a cell at the same time however only
one of them is allowed to do so. As the one with ratio 1:4 has the highest priority the other has to wait for one cell time. The result
is shown in Figure 19.
Once a collision occurs the class with the lowest priority must wait before a cell can be output. In Figure 19 this is indicated with
an arrow showing that the cell was shifted for one time slot. From this moment on every cell gives a collision as the ratio 1:3 with
a time delay of one cell (due to the higher priority of the 1:4 class) also gives a ratio of 1:4. The net effect is that the lower priority
class is sending at a ratio of 1:4 instead of 1:3. If the round robin priority mechanism is used it gives the same result and does not
help here.
A solution to the problem is to set a very small CDV one for the low priority class. This is shown in Figure 20.
Here the Leaky Bucket has a kind of ’memory’ when a collision occurs and the cell had to be output with a small delay. Therefore
the next cell is output a cell slot earlier (CDV of one).
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Figure 19: Collision without CDV
Figure 20: Collision with CDV of one
5 Class data
Each class has a number of configuration and status values stored in three internal RAMs (Queue control RAM, Leaky Bucket
parameter RAM and Leaky Bucket level RAM). The internal RAMs can not be accessed directly by the microprocessor. To write to
these RAMs the microprocessor must first write the
all purpose data register
with the data and set the number of the class to write
to. Then it must give a command to transfer this
all purpose data register
to the specified internal RAM. The opposite is valid for
reading the class data. The microprocessor must first specify which class should be read and then give a command to transfer the
RAM data to the
all purpose data register
.
All configuration data in all three RAMs should be initialized after reset!
5.1 Queue control RAM
5.1.1 Queue base address
The base address determines where the queue starts in the main memory. The start position is in blocks from the memory begin.
One block holds 4096 words of 32 bits and can store up to 288 cells. This value is 13 bits wide. The first words in the main
memory are used for the class lookup table. This table can be as small as 1 byte or as big as half the total memory size (maximum
64 Mbytes). Even if a single byte is used this byte may not be overwritten by data. So at least one block must be reserved for the
lookup table. The minimum queue start value is then 1. For a lookup table of 64Kbytes blocks 0..3 are used and the first free block
is number 4.
Note:
A cell containing 53 or 56 bytes is stored in 14 words each 32 bits wide. One block of 4096 words can hold
cells.
However a complete cell is stored and read back in page mode 3. As a consequence we can not utilize the memory for the full
and thus only 288 cells are stored in a space that could hold 292 cells. This gives an efficiency of almost
.
3Page mode is a special means of operation of a dynamic RAM. It means a single RAS cycle followed by multiple CAS cycles. For more details see the data
sheet of a dynamic RAM that can work in page mode. In page mode all CAS addresses are remaining in a single RAS page.
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5.1.2 Queue size
The queue size determines the size of the queue in cells. This value is 21 bits wide. This allows classes holding a maximum of 2M
cells to be defined. Although the start addresses of the queues are 288 cells apart, the queue-size parameter allows smaller queues
to be defined. As this is a loss of memory utilization a minimum queue size of 288 cells is proposed. The minimum queue size is 2
cells. Setting a smaller queue size will result in unpredictable behavior of the SHAP4-B.
5.1.3 Indication level
The value of the indication level is compared with the queue level. If the queue level is above the indication level this is used for
two purposes:
The queue status interface shows that a high level is present.
Incoming cells with the CLP bit set can be discarded if CLP discard is enabled.
To enable the CLP discard feature the CLP cell discard enable bit in the
COLB register
must be set. Bit 4 of the
COLB register
controls the type of cells leaving the device:
If bit 4 of the
COLB register
is cleared all cells are treated equal.
If bit 4 of the
COLB register
is set cells with incoming CLP = 1 are discarded if level
indication level.
If this bit is set the SHAP4-B looks at the queue level for each incoming cell with the CLP bit set (CLP = 1). If the CLP bit is set
AND the queue level is higher than the indication level the cell will not be stored in the queue. By setting the indication level equal
to or larger than the queue size the indication level becomes inactive. The indication level value is 21 bits wide. The discarded cell
counter can be programmed to count these discarded cells as lost or ignore these discarded cells. See also the next chapter.
5.1.4 Discarded cells counter
This value shows how many cells were discarded for this queue. If the maximum value has been reached this value can be hold or
it can set the interrupt bit and start counting from zero again.
If bit 5 of the
all purpose data register
1 is cleared when initializingthe queue control RAM the counter countsto the maximum
value and stays there.
If bit 5 of the
all purpose data register
1 is set when initializing the queue control RAM the counter rolls over when reaching
the maximum value and sets a status bit.
The counter can also be programmed to count the discarded cells with CLP = 1.
If bit 6 of the
all purpose data register
1 is cleared it is also incrementedwhen a cell arrives which has the CLP bit set and the
queue level is above the indication level.
If bit 6 of the
all purpose data register
1 is set when initializing the queue control RAM it is only incremented when the queue
is full (queue overflow).
When cells are discarded due to an erroneous HEC or a FIFO full status, the counter is not incremented. The cell counter can not
be written independent of the rest of the queue data. Thus it is not possible to reset the counters.
5.1.5 Queue level
The level is a read only value. It shows how many cells are stored for that class. The queue level value is 21 bits wide and is
automatically updated when a parameter is read from the on chip queue control RAM.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
5.1.6 Queue status bits
There are three status bits of the queue, the empty, full and indication level status bit. These bits are automatically updated when
a parameter is read from the on chip queue control RAM. The indication level status bit is set if the queue level is larger than the
indication level. The level status can also be read from the queue status interface.
5.1.7 Read/Write queue control RAM
The queue base address, queue size, indication level, discarded cells counter, read pointer, write pointer and the three configuration
bits (
all purpose data register
1 bit 5..7) are stored in the queue control RAM. It is not possible to access the queue control RAM
directly from the microprocessor. Instead the
all purpose data register
is used for intermediate data storage. Under all conditions it
is possible to address the queue control RAM.
Write queue control RAM To write to the queue control RAM first the
all purpose data register
0..16 must be written. It is
important that the read pointer, write pointer and bit 7 of the
all purpose data register
1 used by the queue control algorithm are
cleared when setting up a queue control entry. Then the
class select register
must be set with the number of the class to write to.
Finally the command
transfer to queue control RAM
(code 0x03) must be written to the
transfer control register
. The SHAP4-B
will then update the queue control RAM in such a way that it does not interfere with the normal operations. Bit 7 of the
transfer
control register
shows the status of the transfer:
If bit 7 of the
transfer control register
is cleared the transfer is still pending. No new data may be written to the
all purpose
data register
while a transfer is pending.
If bit 7 of the
transfer control register
is set the transfer is ready.
Read queue control RAM To read the data from the queue control RAM, the first task of the microprocessor is to set the
class
select register
with the number of the class to read. The command
transfer from queue control RAM
(code 0x02) must be written
to the
transfer control register
. The SHAP4-B will then read the queue control RAM data and transfer it to the
all purpose data
register
. Bit 7 of the
transfer control register
shows the status of the transfer:
If bit 7 of the
transfer control register
is cleared the transfer is still pending. The data in the
all purpose data register
is not
yet valid
If bit 7 of the
transfer control register
is set the transfer is ready. The data in the
all purpose data register
is valid
Only after the transfer is completed the microprocessor reads the values from the
all purpose data register
.
5.2 Leaky Bucket select register
When working in single Leaky Bucket mode (controlled by bit 7 of the
Leaky Bucket control register
1) the SHAP4-B still has two
single Leaky Bucket parameters per class available. This register determines for each class whether single Leaky Bucket one or two
is used.
5.3 Read/Write Shaping settings
The shaping settings are stored in two RAMs:
The Leaky Bucket parameter RAM
The Leaky Bucket level RAM
Both RAMs can be set independently. It is allowed to change the Leaky Bucket settings while the SHAP4-B is active.
All shaping parameters for all classes whether they are used or not should be initialized after reset! If a class is not used the
related shaping parameters should be set to not OK (see chapter 3.2.2 Stop data stream).
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5.3.1 Write parameter or level RAM
To write to the RAM the
all purpose data register
must be written first. For the parameters it is the register 0..9, for the level it is
the register 0..7. Then the
class select register
must be set with the number of the class to write to. Finally the command
transfer to
parameter RAM
(code 0x05) or transfer to level RAM (code 0x15) must be written to the
transfer control register
. The SHAP4-B
will then update the corresponding RAM in such a way that it does not interfere with the normal operations. Bit 7 of the
transfer
control
register shows the status of the transfer:
If bit 7 of the
transfer control register
is cleared the transfer is still pending. No new data may be written to the
all purpose
data register
while a transfer is pending.
If bit 7 of the
transfer control register
is set the transfer is ready.
5.3.2 Read parameter or level RAM
To read the data from the Leaky Bucket parameter or level RAM, the first task of the microprocessor is to set the
class select register
with the number of the class to read. The command
transfer from parameter RAM
(code 0x04) or the command
transfer from level
RAM
(code 0x14) must be written to the
transfer control register
. The SHAP4-B will then read the corresponding RAM data and
transfer it to the
all purpose data register
. Bit 7 of the
transfer control register
shows the status of the transfer:
If bit 7 of the
transfer control register
is cleared the transfer is still pending. The data in the
all purpose data register
is not
yet valid.
If bit 7 of the
transfer control register
is set the transfer is ready. The data in the
all purpose data register is valid
.
Only after the transfer is complete the microprocessor can read the values from the
all purpose data register
.
5.3.3 Read/write static RAM
Read/write parameter set When reading parameter sets from or writing to the external static RAM the procedure is almost the
same as described above.
Two differences are to be observed:
1. Besides the
class select register
also the
parameter set control register
must be set with the parameter set number.
2. The transfer codes (was 0x05 & 0x04) should be 0x07 and 0x06.
Bit 7 of the
parameter set control register
must be set. Otherwise not the parameter sets but the pointer to the parameter set is
accessed.
Read/write parameter set pointer When reading the parameter set pointer from or writing to the external static RAM the proce-
dure is almost the same as described in chapter 5.3.3.1 Read/write parameter set.
1. Select a class using the
class select register
.
2. Write the parameter set pointer value to the
all purpose data register
9 (only necessary when writing).
3. Clear bit 7 of the
parameter set control register
.
4. The transfer codes should be 0x07 (for writing) and 0x06 (for reading).
After finishing the read transfer the
all purpose data register
9 holds the parameter set pointer value.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
6 CLP bit handling
The device can handle cells with and without CLP bit set differently. This is done by setting an indication-level for a class and
setting the CLP-discard bit in the
COLB register
. As soon as the queue level is beyond the indication-level all arriving cells which
have the CLP bit set are removed. The counter mode determines if these cells are also counted as discarded cells. The SHAP4-B is
not capable to remove cells with the CLP bit set that are already stored in the queue.
The CLP bit handling can be disabled for a certain class by filling the indication-level with a value equal to or larger than the queue
size. A general CLP enable bit must be set in order to handle cells with incoming CLP-bit set specially.
Bit 4 of the
COLB register
is a global CLP-cell discard enable/disable bit.
If bit 4 of the
COLB register
is set the indication level is used for the status interface and to discard CLP-bit cells as described
above.
If bit 4 of the
COLB register
is cleared the indication level is only used for the status interface.
7 Class assignment
Arriving cells must be assigned to a class. To do this the SHAP4-B uses parts of the cell header to read from a class lookup table.
From each arriving cell up to 24 bits are taken from the header (See
header mask register
). To these bits the number of the input
port at which the cell arrived can be added (programmable). This gives a value of 0 to 26 bits that are taken as address in the lookup
table. From the lookup table a byte is read. The LS 5 bits of this byte specify the class number where the cell should be written to.
7.1 Header mask
The header mask is used to extract up to 24 bits from the first five octets of a cell. Thus not only the cell header can be accessed
but also the HEC byte can be used to hold information for the SHAP4-B. The extracted bits are presented to the class lookup table.
The header bits are selected using five byte
header mask register
. Each bit set in a register will cause the corresponding header bit
or HEC bit to be used for selecting a class. If less than 24 bits are set in the mask, the remaining extracted bits are set to zero. If
more than 24 bits are set only the last 24 bits are used.
Header mask register
0 selects bits from octet 1, register 1 from octet 2, etc.
The LS bit of a register (bit 0) selects data arriving at input RxData[0].
The extracted value can be enhanced with two port-number bits that specify at which port the cell arrived. If the port-id bits are
used all header bits are shifted two positions to the left and the port-id is placed in the LS two bit positions:
00 0 0 000
0001
10111
X XX 1XXXX 1 X X1
11 1 7654321076543210 octet5 octet2 octet1
Mask
0001 111 00
252423
23 0
0 0 1010 01 10
543210
543210
PidPid
Header/HEC
Extracted
header
Extr. Header
+port id.
Figure 21: Header extraction mask plus port id
Bit 3 of the
Input control register
controls the port id extension:
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If bit 3 of the
IOC register
is cleared the extracted header data has no port id.
If bit 3 of the
IOC register
is set the two bit port id is added to the extracted header data.
With a port id the extracted header value can be maximum 26 bit long.
7.2 Lookup table
The size of the lookup table can vary between 1 byte and 64M bytes. As the memory of the SHAP4-B is allocated in blocks of
4096 words, the smallest lookup table requires 1 block of 4K words the largest requires 16M blocks of 4K words. The memory
connected to the SHAP4-B should be large enoughto hold the lookup table and still have enough storage left to store the cells from
the classes.
The maximum extracted header value of 26 bits is only present in excessive circumstances. In most cases the extracted header value
will be smaller and thus less memory is needed for the lookup table. However if the complete 26 bits are essential the SHAP4-B
only requires enough DRAM to fulfill the demands. The table below shows the memory required for the lookup table in relation to
the length of the extracted value.
No. of Bits set Memory required Memory required
in mask registers without port id with port id
Size/byte Blocks Size/byte Blocks
24 16M 1024 64M 4096
23 8M 512 32M 2048
22 4M 256 16M 1024
21 2M 128 8M 512
20 1M 64 4M 256
19 512K 32 2M 128
18 256K 16 1M 64
17 128K 8 512K 32
16 64K 4 256K 16
15 32K 2 128K 8
14 16K 1 64K 4
13 8K 1 32K 2
12 4K 1 16K 1
11 4K 1 8K 1
0..10 4K 1 4K 1
If less than 15 (or with port id less than 13) bits are used only a single block is required to hold the complete lookup table. Note
that if no header extraction bits are set the extraction logic always produces the value 0. Thus the first byte in the memory is used
to determine to which class the cell belongs. (With a port id the first four bytes in memory are used.) However as the memory is
allocated in blocks, 1 block (4K words) is the minimum lookup table size which is always required.
The SHAP4-B can transfer data to and from the class lookuptable. The microprocessor has no direct access towards the table. Even
if a link is fully loaded (no gaps or idle cells) it is possible to access the lookup table. The lookup table is located in the dynamic
RAM and each word is 32 bits wide. As for a class we need only 5 bits (as we have only 32 classes) one word holds 4 entries: the
LS 5 bits of each byte. Therefore a read or write access will always read/write 4 consecutive table entries.
Unused classes should not have an entry in the lookup table.
As the size of the lookup table is variable the number of address bits used to access the lookup table is also variable. The number
of address bits equals the number of bits set in the
header mask register
minus 2. Setting a wrong address during a read or write
access will cause the SHAP4-B to read or write at the wrong place in the memory. When writing data this can cause the SHAP4-B
to output damaged cells.
To update the lookup table the device has two registers:
Class lookup table address
This value is the address to access. It is 32 bits wide (
all purpose data register
4..7) where only the least X significant bits should be
used. X equals the number of bit set in the
header mask register
(minus 2 if the port-id is not used) The most significant bits should
be cleared for lookup table access.
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Class lookup table data
This value is the data to be read/written (
all purpose data register
0..3). From each byte the LS 5 bits are used to indicate one of the
32 queues. Byte 0 of word 0 correspondswith an extracted header value of 0x0000. The second byte of the first word with extracted
header value of 0x0001, etc.
To write towards the lookup table, the four class entries (
all purpose data register
0..3) and the destination address (
all purpose data
register
4..7) are written into the SHAP4-B. A write transfer will start after writing 0x01 to the
transfer control register
. To read
from the lookuptable, the source address is written into the SHAP4-B (
all purpose data register
4..7). A read transfer will start after
writing 0x00 to the
transfer control register
. The SHAP4-B will load the data from the table into it’s registers. In both cases the
transfer ready bit must be observed to prevent errors.
With a 19.44MHz clock a transfer will take maximum 5.4
sec (53 byte cell format).
7.3 General memory access
In the previous chapter we concentrated on reading from or writing to the lookup table. Therefore we restricted the number of
address bits that should be set to a value X (See previous chapter). However all the address bits of the class lookup table address
value can be used. This will only cause the SHAP4-B to access a different memory location. The same holds for the data registers.
For the lookup table all 32 bits can be set but only the LS 5 bits are used. For a general memory access all the 32 bits are valid.
The commands to read or write the memory are the same. General memory access can be used to perform a memory check on
the DRAM or to access the DRAM in a random way. It is only dangerous to do so when the SHAP4-B is operating as it may
inadvertently destroy data stored in the memory.
8 Class Rate Adaptation
Often the rate at which data is sent must be changed. This is what we call rate adaptation, which means that the output rate
parameters for the Leaky Bucket function can be changed during runtime either under software or under hardware control. This
function is available in two forms:
With external static RAM 32 rates are available per class per Leaky Bucket.
Without external static RAM 2 rates are available per class if working in single Leaky Bucket mode.
8.1 Parameter set select
One parameter set consists of either one dual Leaky Bucket parameter in dual Leaky Bucket mode or two single Leaky Bucket
parameters in single Leaky Bucket mode. As mentioned rate adaptation allows a user to choose one of 32 available output rates per
class. The output rate is stored in an external static RAM as 32 Leaky Bucket parameter sets for each of the 32 classes. Therefore
total 1024 parameter sets are stored in the external static RAM. Only one parameter set can be active for a class. Selecting a
parameter set can be done under software or hardware control. For each class a 5 bit parameter set pointer is also stored in the
external static RAM which points to the active parameter set. Hence 32 pointers are stored. This pointer indicates the number of
the active parameter set.
For example:
To select parameter set 5 the value of the pointer should be set to 0x5.
All parameter sets and all pointers in the external static RAM can be changed under CPU control (see chapter 5.9 Read/Write
Shaping parameters). For each class the actual parameters are stored in the parameter RAM of the SHAP4-B. The transfer of
parameters from the external RAM to the internal RAM can be performed in two ways:
If bit 4 of the
cell out control register
is cleared the new parameter set can be loaded under hardware control.
If bit 4 of the
cell out control register
is set the new parameter set can be loaded software controlled.
Two operations are possible to change the active parameter set: increment and decrement commands can be used to change the
pointer value.
The increment command always chooses the next higher rate. For the decrement command four different decrement modes are
available:
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Decrement by 1
Decrement by 25%
Decrement by 50%
Decrement by 75%
The decrement rate is programmed with bits 5 and 6 of the
parameter set control register
:
Bits [6:5] Decrement by
00 1
01 25%
10 50%
11 75%
If the lowest/highest parameter set is selected the decrement/increment command has no effect. The conversion from the various
decrement modes are shown in the conversion table below.
The conversion of the old parameter set pointer to the new parameter set pointer depends on the decrement mode bits [6:5] in the
parameter set control register
. The mode bits 6 & 5 are shown below the "New" text:
Old New New New New Old New New New New
00 01 10 11 00 01 10 11
0 0 0 0 0 16 15 12 8 4
1 0 0 0 0 17 16 13 8 4
2 1 1 1 0 18 17 14 9 4
3 2 2 1 0 19 18 15 9 4
4 3 3 2 1 20 19 15 10 5
5 4 4 2 1 21 20 16 10 5
6 5 5 3 1 22 21 17 11 5
7 6 6 3 1 23 22 18 11 5
8 7 6 4 2 24 23 18 12 6
9 8 7 4 2 25 24 19 12 6
10 9 8 5 2 26 25 20 13 6
11 10 9 5 2 27 26 21 13 6
12 11 9 6 3 28 27 21 14 7
13 12 10 6 3 29 28 23 14 7
14 13 11 7 3 30 29 23 15 7
15 14 12 7 3 31 30 24 15 7
The newvalue of the parameter set pointer is used to select the new parameter set in the external static RAM. The SHAP4-B transfers
this new parameter set from the external to the internal RAM. If the highest/lowest class is active further increment/decrement
requests are ignored.
8.2 Software rate control
To control the output rate under software there are two possibilities:
Write new parameters to the internal RAM.
Transfer parameters from the external static ram to the internal parameter RAM using the increment or decrement command.
The first method is described above and although it allows an arbitrary rate to be set it also requires that the microprocessor sets all
the registers and transfers the registers to the parameter RAM. To transfer parameters from the external static RAM to the internal
parameter RAM the increment and decrement commands can be performed under software control. Bit 4 of the
cell out control
register
must be set for software control. To increment/decrementthe pointer three microprocessor write actions must be performed:
1. Write the class number in the
class select register
, the inc/dec bits must be zero.
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2. Write the class number plus the increment/decrement bit in the
class select register
. The parameter set pointer of the class is
incremented/decremented. The new value of the parameter set pointer is used to select the new parameter set in the external
static RAM. The SHAP4-B transfers this parameter set from external to the on chip parameter RAM.
3. Write the class number in the
class select register
and set the inc/dec bits zero again.
It is also possible to set a new pointer value for the parameters under software control. However this command sets only the pointer
but does not loada new parameter set. An increment or decrementrequest is always handled in one cell time (53 or 56system clock
cycles). The next increment or decrement command must be at least 53 (or 56) system clock cycles after the first pulse. If the next
command is less than 53 (or 56) system clock cycles after the first one, this additional command may be accepted or not, depending
on the internal state of the state machine.
8.3 Hardware rate control
To control the output rate using external hardware control the SHAP4-B has seven input signals:
class [4:0]:
5 bits wide to select one of the 32 classes.
Par_inc:
The rising edge of this signal stores the selected class and increments the parameter set pointer of this class. The new value of the
parameter set pointer is used to select the new parameter set in the external static RAM. The SHAP4-B transfers this parameter set
from external to the on chip parameter RAM.
Par_dec:
The rising edge of this signal stores the selected class and decrements the parameter set pointer of this class, depending on one of
the above decrement formulas. The new value of the parameter set pointer is used to select the new parameter set in the external
static RAM. The SHAP4-B transfers this parameter set from external to the on chip parameter RAM.
With this method it is not possible to directly select one of the 32 available rates. Instead of this the next higher or a lower rate
(depending on the selected decrement formula!) is chosen 4. Signal timing:
Figure 22: Par_inc, Par_dec signal timing
PAR_inc, PAR_dec behavior:
When an PAR_inc or PAR_dec pulse arrives this event is stored together with the class number until the chip can execute this
command. An increment or decrement request is always handled in one cell time (53 or 56 cycles). The next PAR_inc or PAR_dec
pulse must be at least 53 (or 56) system clock cycles after the first pulse. If the next pulse is less than 53 (or 56) system clock cycles
after the first one this additional pulse may be accepted or not depending on the internal state of the state machine.
8.4 Parameter curves
Because of the increment-decrementsignals the parametersets in the table should be orderedin rising or fallingoutput rate. However
how fast rising or falling is up to the user. Some possible configurations are:
The linear rate change figure 23 is the most likely to be used. It will cause the shaper to go up or down in a regular way.
The logarithmic rising range figure 24 allows a rate increment and decrement to have small change at higher rates and a big change
at low rates. The complement from this function:
logarithmic falling
is not shown here but the reader can easily imagine what it
looks like. It allows a rate increment and decrement to have large changes at higher rates and a small change at low rates.
The PI-curve figure 24 allows changes in the middle to have lilt effect and at the low and high ends to have more impact. An
alternative to this is the S-curve which is not shown here. It causes changes in the middle of the curve to have a large impact
and increments/decrements at the extreme ends to give only little changes. It is also possible to fill all entries with the same data
effectively rendering the parameter change inoperable.
4Assuming the rates are stored from low rate to high rate.
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Figure 23: Linear rate change
8.5 Asymmetric change (ABR)
Thus far we handled the increment and decrement equal. As mentioned above the SHAP4-B has four modes in which a decrement
can occur:
Decrement by 1
Decrement by 25%
Decrement by 50%
Decrement by 75%
This option allows the SHAP4-B to be used in systems which require ABR or any other requirement of fast rate reduction. An
output reduction of 50% means the SHAP4-B will select the parameter set which is 50% below the current one. This does not mean
a reduction of 50% of the output rate as the output rate depends on the filling of the parameter table. Only if the parameter table is
set up linearly will a decrement of 50% also give an output rate reduction of 50%. Further more the reduction can slightly differ as
only 32 parameter sets are available. E.g. if parameter set 3 is activea reduction of 50% can not be performed (there is no parameter
set 1.5).
This option can be combined with the parameter curves described above allowing a large and flexible range of output rates. The
increment parameter always works with an increment of one.
9 Local cell transfer
Local cell transfer is a way to access cells in the SHAP4-B memory. For a normal passing cell stream the SHAP4-B does not allow
cells to be copied fromor to the memory. This is due to the fact that the memorypointers can change between microprocessor reads
or writes. Hence it is only possible to do this for classes that do not output cells (process incoming cells only) or which do not
input cells (process outgoing cells only). Reading or writing of cell data can be done under CPU control or under DMA control. As
the SHAP4-B is not primarily intended to be used as starting point or ending point for data the transfer rate of cells from or to the
memory is low due to several factors:
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 24: Logarithmic rate change
The data port is only 8 bits wide
Data transfer to or from the memory can happen worst case only once every 6 ¸tsec
No build–in DMA controller
However these options allow a user to inspect data in the memory, debug a stream or use a SHAP4-B class as AAL device for low
speed data. If really high speed data transfer to or from a microprocessor is needed the user can add a logic to the input port or to
the output port of the device:
This logic allows the microprocessor to write towards the SHAP4-B memory using an external FIFO at the input port. Data speeds
up to 200 (320) Mbit/sec can then be processed. The same holds for reading data from the SHAP4-B memory. A FIFO at the output
port connected to the CPU data bus allows a user to read data up to 200 (320) Mbit/sec from the SHAP4-B memory. If the data is
written in 53 byte format and read back in 56 byte format the data coming from the output port will contain the 24 bit time tamp
added to the cell. Note that the rate at which cells are forwarded to the CPU can be controlled by selecting a certain output rate for
that port. This allows a user to store high-speed arriving data at the input port and simultaneous start performing analysis on the
data coming from the output port but at a lower rate. The SHAP4-B memory will be filled up with the difference between input and
output rate. So the maximum number of analyzed cells can be increased.
9.1 CPU cell handling
When transferring cells from or to the SHAP4-B memory under CPU control it can be done on polling basis or under interrupt
control. At all times a complete cell must be read or written before a class switch is made. Thus once the transfer for a cell has
started it must be finished for that class. In the mean time another class may not be selected by the microprocessor. The SHAP4-B
has status bits which signals the status of the transfer and the cell interface unit.
9.2 DMA cell handling
When transferring cells from or to the SHAP4-B memory under DMA control it can be done for one class only at the time. Thus
once the transfer for a cell has started it must be finished before another class is serviced by the DMA controller. The SHAP4-B has
a DMAREQ* signal that is directly connected to bit 7 of the
transfer control register
. Therefore all transfers can be done by polling
bit 7 of the
transfer control register
or under DMA control using the DMAREQ* signal. Note that the SHAP4-B has no build-in
DMA controller. To perform access with a DMA controller extra logic is needed to put the chip in read mode for the
all purpose
data register
during a DMA access.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 25: Pi–Curve rate change
Figure 26: Faster access to SHAP4-B data
9.3 Read cell from data stream
Cells can be read from the class queue only if no cells are output. The
Leaky Bucket
parameter must be initialized with values that
always will result in a ’not OK’ decision (see chapter 3.2.2). The following actions must be performed to read a cell from a class
queue. First the class must be set in the
class select register
. A cell read transfer is started by writing 0x08 to the
transfer control
register
. The cell interface unit then calculates and loads the read address of the queue of the selected class. Using this address the
first four bytes of the cell are transferred to the
all purpose data register
0..3. To see if the transfer has finished the microprocessor
must check the status bit. When status bit 7 of the
transfer control register
is set the transfer is finished.
The first four bytes can now be read from the
all purpose data register
0..3. The transfer of the next four bytes is started when
writing to the
all purpose data register
3. So after the
all purpose data register
3 was read, an additional write access is needed to
start the transfer of the next four bytes (see section 23.3). The microprocessor must again wait until bit 7 of the
transfer control
register
is set. Then the next four bytes are available in the
all purpose data register
0..3. This cycle is done fourteen times, until
the complete cell (53 or 56 bytes) is read. Bit 6 of the
transfer control register
shows the status of the cell interface unit. When all
bytes of a cell have been read bit 6 of the
transfer control register
is set.
9.4 Insert cell in data stream
Cells can be written to the class queue only if no cells arrive at the input for the queue. To accomplish this the class index may not
be present in any entry of the class lookup table. The cell is output according to the Shaping function (unless the microprocessor
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
writes cells in slower as the Shaper function outputs). The following actions must be performed to write a cell to a class queue.
First the class must be set in the
class select register
.
The cell transfer is started by writing 0x09 to the
transfer control register
. The cell interface unit then calculates and loads the
address of the queue of the selected class. To see if the calculation is finished the microprocessor must check the status bit. When
status bit 7 of the
transfer control register
is set the calculation is finished. The first four bytes of the cell can now be written to the
all purpose data registers
0..3. The transfer of these bytes is started when writing the
all purpose data register
3. The microprocessor
must again wait until bit 7 of the
transfer control
register is set. Then the next four bytes can be written to the
all purpose data
register
0..3. This cycle is done fourteen times, until the complete cell (53 or 56 bytes) is written. If the 53 byte cell format is used
a dummy write to
all purpose data register
3 is needed to start the fourteenth transfer. Bit 6 of the
transfer control register
shows
the status of the cell interface unit. When all bytes have been written bit 6 of the
transfer control register
is set.
9.5 Cell interface transfer format
How the information is stored in the memory depends on the cell format programmed in the
input control register
. As the input
controller supports three types of cells, three different memory formats are possible: 53 bytes cells, 53 bytes cells with 3 bytes tag
where the cell header starts with the fourth byte, and 56 bytes cells. The input can also perform conversionfrom 56 byte cell format
to 53 byte cell format. In this mode the first three bytes of a cell are removed.
When operating in 53 byte format or in conversion mode 56 to 53 byte format the cell data is temporarily stored in the
all purpose
data register
according:
all purpose data register
reg 0 reg 1 reg 2 reg 3
header 0 header 1 header 2 header 3 0
HEC payload 0 payload 1 payload 2 1
payload 3 payload 4 payload 5 payload 6 2
3
...
payload 43 payload 44 payload 45 payload 46 12
payload 47 24 bit time stamp 13
LS byte MS byte
If storing 56 byte cells the information is stored as for 53 byte cells but the last 3 bytes contain cell data.
When operating in 53 byte cell format plus 3 bytes tag the cell data format is:
all purpose data register
reg 0 reg 1 reg 2 reg 3
tag 0 tag 1 tag 2 header 0 0
header 1 header 2 header 3 HEC 1
payload 0 payload 1 payload 2 payload 3 2
3
...
payload 40 payload 41 payload 42 payload 43 12
payload 44 payload 45 payload 46 payload 47 13
10 Special cell copy
The user can copy one cell or part of a cell from the data stream. The cell type can be recognized by the header. The SHAP4-B
contains 4 registers each 8 bit wide which specify the cell header value to be recognized. The cell header is divided in 8 parts each
4 bits wide. For each 4-bit part (nibble) the user can specify if these header bits should be used during header comparison or if they
are don’t care.
The cell copy header value register
specifies the 32 bit header value.
The cell copy nibble mask register
controls which part of the
header is checked. Each bit set in the
cell copy nibble mask register
enables the comparison of a nibble from the cell header.
The LS 6 bits of
cell copy low index register
specifies the start position, that is the first byte to be output of a cell. To read the first
byte of a cell this register should be written with the value 1.
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The LS 6 bits of
cell copy high index register
specifies the end position, that is the last byte to be output of a cell. To read only a
single byte of a cell this register should be written with the same value as the
cell copy low index register
.
The interface consists of 10 signals:
ex_D[7:0] signals
ex_start signal
ex_val* signal
The data is output in a number of bytes (1 up to 53 or 56), where each RxClk cycle a new byte appears at the data output. The last
byte output remains at the data output unchanged until a new "special" cell arrives. During the first byte a "ex_start" signal is active
high during one RxClk cycle (Compare with the Start–Of–Cell signal from the Utopia interface). During the time that bytes are
output a "ex_val*" signal is active low.
Figure 27: Cell copy interface timing, copy 4 bytes
If a single byte is extracted the data at the 8–bit output port will remain unchanged until a new ’special’ cell arrives. The arrival of
the new byte, even if it has the same value as the previous one, is always signaled by the "ex_start" and "ex_val*" signal.
Figure 28: Cell copy interface timing, copy single byte
A complete cell can be output by setting the
cell copy low index register
to 1 and the
cell copy high index register
to the cell length
(53 or 56). The timing of the ex_start and ex_val* signals is identical to the timing of the Utopia signals TxSOC and TxEnb*.
11 Queue status indication
A status indication about the level of each queue is presented at the output of the SHAP4-B device. The indication consists of two
bits having the following coding:
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
MS, LS Meaning
00 Queue is empty
01 0
>
Queue level
indication level
10 Queue level
indication level
11 Queue is full
For 32 queues this gives 64 status indication bits. As it is not possible to output each status indication bit on a separate pin a
multiplexed output is used. It consists of the following signals:
Name bits Function
sta_D[7:0] 8 Status indication for 4 queues, each queue having 2 status bits
sta_A[2:0] 3 Which queue status bits are output
status valid (sta_val) 1 Can be used for clocking status bits in external registers
Each set of status indication bits is present for 6 system clock cycles. Each set of status indication bits is accompanied by a status
address specifying which group of status indication bits is shown. An extra status "pulse" signal can be used as clock to load the
status indication bits in external registers. With eight 8-bit registers the complete 64 status indication bits are available again. The
status pulse signal is active for two system clock cycles in the middle of the status signals. Sta_A=0 means that the status indication
bits of queue 0..3 are present, Sta_A=1 is for queue 4..7, Sta_A=2 is for queue 8..11, etc.
Bit 5 of the
Leaky Bucket Control register 2
controls the operation of the
sta_val
signal.
If bit 5 of the
LCR2
is cleared the
sta_val
signal is low for two clock cycles in the middle of the status signals.
If bit 5 of the
LCR2
is set the
sta_val
signal is high for two clock cycles in the middle of the status signals.
The following timing diagram shows the timing of the status interface, with the
sta_val
signal active high.
Figure 29: Status interface timing
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
12 Traffic receiver & generator
The SHAP4-B is capable of sending or receiving a large number of cells in real-time. Therefore it can be used as traffic analyzer
and as traffic generator. To support these functions some additional features have been built in the SHAP4-B.
12.1 Traffic receiver
The SHAP4-B itself does not perform cell analysis. However it can store a large number of cells in real-time. After storing the
cells a microprocessor can read them from the memory and perform analysis of the received data. If using the maximum amount of
memory and running at maximum speed (every arriving cell is a data cell) the SHAP4-B can store data for 5.71 seconds. As extra
feature the input stream can be split and assigned to various classes thus providing some means of filtering of the received cells.
It is possible to assign all cells which do not need to be analyzed to a small queue. This queue will overflow very fast, but as the
information is not needed this is no problem.
During analysis it is often needed to know the arrival time of a cell. From the arrival time delay time, inter-arrival time and other
useful information can be derived. The ATM cell is stored in 14 words of 32 bits in the dynamic memory. With a cell of 53 bytes,
3 bytes are unused. These bytes are used when the input controller is running in 56 bytes cell mode (
cell type input control register
bit [6:5] = "11" or "10"). In all other modes (cell type = "00" or "01") the 3 unused bytes are used for a 3 byte time stamp. The cell
input controller of the SHAP4-B has a 24 bit time stamp counter. This counter is incremented every RxClk cycle or every 53 (or
56) RxClk cycles. This counter value is written at the end of the cell when the cell type is "00" or "01". This feature can be used
to measure the arrival time of the cells of a class. The Leaky Bucket parameters for that class can be programmed that no cell will
leave the SHAP4-B (always not OK, see chapter 3.3.2). So all arriving cells of this class are stored in the queue. These cells can be
read including the time stamp (see 9.3 Read cell from data stream). The counter overflows after
cycles and thus a minimum cell
distance is required.
The time stamp increment every RxClk clock cycle gives a very good resolution and can be used for discontinuous cell stream to
measure the distance between two cells in RxClk clock cycles. The disadvantage is that the minimum cell distance is a factor 53 (or
56) smaller.
The time stamp increment every 53 (or 56) RxClk clock cycles gives a low resolution and can be used for a continuous cell stream
to measure the distance between two cells in ’cell times’. In this mode at least one cell every 45 seconds is required.
Note that the counter is running on the RxClk clock and for reliable measurements a continuous running RxClk clock is necessary.
12.2 Traffic generator
Of course the SHAP4-B can function as traffic generator. A simple method of traffic generationis to write a large number of cells in
a class and then start the shaping function. The duration of the data output depends on the output rate. Even with a limited amount
of dynamic memory a user can produce traffic for a long period but only at a low rate. If using the maximum amount of memory
and running at maximum speed the SHAP4-B can produce 155.52 Mbit/s for 5.7 seconds.
A special option is built into the SHAP4-B which is called "
circular output mode
". In this mode the data from a class is output
continuously from the first to the last cell. To use this function the user must perform the following steps:
1. Disable the output of the class (see chapter 3.3.2 Stop data stream).
2. Set up the queue of the class for the number of cells to be sent.
3. Fill the complete queue with the pattern of cells which should be output.
4. Set the class in
circular output mode
(using bits 5 and 6 of the
cell out register
).
5. Start the cell output by filling the Shaping parameters.
The SHAP4-B will now output the data stream with the specified rate. Every cell in the queue is output and when the last cell is
output the SHAP4-B starts with the first cell of the queue again. This mode of traffic generationcan be used for testing purposes but
can also function very well as background traffic generator. Using the method described first it is also possible to use all classes in
non-circular mode to produce series of cells which are automatically output by the SHAP4-B as soon as class zero does not produce
data.
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An even more complextraffic generatorcan be build using the static RAM to store differenttraffic rates and then switching between
different rates for the various classes.
Bits 5 and 6 of the
COLB register control
the circular modes:
COLB [6:5] Operation mode
00 Normal operation, All queues in normal mode.
01 Queue 0 in circular mode, Queue 1..31 in normal mode.
10 Queue 8..23 in circular mode, Queue 0..7 and 24..31 in normal mode.
11 All queues in circular mode.
Those classes which operate in circular mode can only output traffic. As the queue is full they can not receive any incoming traffic.
Those classes which do not operate in circular mode can perform the normal traffic shaping operations.
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13 External memory
13.1 Dynamic memory
The SHAP4-B can work with various types of dynamic memory. Not all of them are currently available but with the rate dynamic
RAMs develop they will be in the future. The SHAP4-B can work with one or two memory banks. How many banks should be
used depends on the storage capacity a user wants to assign to the SHAP4-B.
13.1.1 Memory type
The SHAP4-B can handle four different types of dynamic memory chips:
256K x 32
1M x 32
4M x 32
16M x 32
The number of the row and column address bits should be equal (symmetric DRAMs) for 256K x 32, 1M x 32 and 16M x 32
configurations. For 4M x 32 configuration the SHAP4-B supports symmetric and asymmetric DRAMs with 12row/10 column
address bits. It is also possible to use hyper page mode (EDO) DRAMs. Bit 1 of the
Dynamic ram control register 1
defines the
DRAM type. In EDO mode the RAS signal is delayed by half a clock cycle.
dram type access time system clk frequency
any 70 ns up to 19.44 MHz
any 60 ns up to 25 MHz
any 50 ns up to 30 MHz
EDO 3.3V 50 ns up to 40 MHz
For optimal performance Bit 5 of the
dynamic ram control register 2
should be set (no additional CAS delay). The data bus
width of the dynamic RAM is 32 bits. Thus dependent on the chip type you need several memory chips.
For example:
If using 256Kx8 bit chips, 4 chips are needed, if you using 1Mx1 bit chips 32 chips are needed. The RAM modules as shown in the
pictures below do not reflect all these possibilities but are drawn ’generic’, i.e. without details about the internal configuration. The
DRAM chip type must be programmed in the
dynamic ram control register
of the SHAP4-B.
The SHAP4-B can use one or two memory banks with each of the above mentioned chips. This gives eight possible memory
configurations:
1. one bank of 256Kx32 bits (1M bytes, 17K cells)
2. two banks of 256Kx32 bits (2M bytes, 37K cells)
3. one bank of 1Mx32 bits (4M bytes, 72K cells)
4. two banks of 1Mx32 bits (8M bytes, 148K cells)
5. one bank of 4Mx32 bits (16M bytes, 293K cells)
6. two banks of 4Mx32 bits (32M bytes, 593K cells)
7. one bank of 16Mx32 bits (64M bytes, 1.1M cells)
8. two banks of 16Mx32 bits (128M bytes, 2.3M cells)
The pin-layout of the SHAP4-B is such that it can be connected to standard SIMM/PS2 5modules without crossing wires. It is up
to the user to program the queues such that the queue is inside the available memory. The SHAP4-B does not perform any checks
to see if the queue is set up wrongly.
5That is, to mostSIMM/PS2 modules as there are so many different ones.
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13.1.2 Refresh rate
Besides the type of RAM also the refresh rate can be programmed. The SHAP4-B has one time slot per cell to perform either a
refresh or a transfer to or from the memory. If possible the refresh rate should be programmed as low as possible as this increases
the number of transfers that can be made. Note that if a refresh once per cell time is programmed the SHAP4-B has no determined
means to access the memory. Instead it must wait for a time slot where no cell arrives or leaves the memory to perform a transfer.
The SHAP4-B has a built in refresh counter and uses the RAS only refresh mode that is supported by all dynamic RAMs. Both
banks are refreshed simultaneously. The refresh time of the dynamic RAM can be set in the
dynamic ram control register
:
The refresh cycle time is given by the following formula:
"
"
_
_
_
"
_
"
clk_freq : system clock frequency
bytes_per_cell : 53/56 depending on bit1 of the
cell out control register
refresh_num : refresh number selected by the
dynamic ram control register
For example:
clk_freq = 20 MHz
bytes_per_cell = 53
refresh_num = 6
refresh cycle time = 1/20 MHz * 6 * 53 = 15.9 E-06 sec
with a dynamic ram of 1Mx32, 1024 rows:
1024 * 15.9 E-06 s = 16.28 ms
which means 1024 refresh cycles every 16.28 ms
13.1.3 Configurations
The value of x in Figure 30 and Figure 31 depends on the memory type:
dram type x
256Kx32 8
1Mx32 9
4Mx32 10/116
16Mx32 11
If the DRAM has an OE* pin it should be connected to GND.
The configuration with one memory bank is shown in Figure 30.
The configuration with two memory banks is shown in Figure 31.
13.2 Static memory
The SHAP4-B can store 32 parameter sets for each class. If this feature is used an external static memory of 16Kx8 bits, 25 ns
access time must be connected to the SHAP4-B. Figure 32 shows one possibility by using a 15 ns, 32Kx8 cache RAM.
6For asymmetric DRAMs (4M x 32 configuration) with 12 row/10 column address bits.
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Figure 30: Memory configuration with one bank
Figure 31: Memory configuration with two banks
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Figure 32: Static RAM connected to SHAP4-B
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14 Register summary
The SHAP4-B has a number of dedicated registers whose tasks and functions do not alter. Besides the dedicated function an
all
purpose register
of twenty bytes is used to temporary store data that must be read from or written to the various memories. The
table below gives the addresses for all registers present in the SHAP4-B.
Address Register
0..4 Header mask register 0..4
5..8 Cell copy header value register 0..3
9 Cell copy nibble mask register
10 Cell copy low index
11 Cell copy high index
12 DRAM CAS additional delay register
13 DRAM RAS additional delay register
14 Dynamic ram control register 1
15 Revision number/Utopia output FIFO register
16 Input control register
17 Interrupt control register
18 Dynamic ram control register 2
19 Class select register
20..23 Leaky Bucket parameter select register 0..3
24 Leaky Bucket control register 1
25 Leaky Bucket 2/RxEnb control register
26 Parameter set control register
27 Cell out control register
28..47 All purpose data register 0..19
48 Transfer control register
49 Input status register
14.1 Dedicated registers
14.1.1 Header mask register (HDM) [Address 0..4]
Reg.
No. Function
0 header mask of the cell octet 1
1 header mask of the cell octet 2
2 header mask of the cell octet 3
3 header mask of the cell octet 4
4 header mask of the cell octet 5
14.1.2 Cell copy header value register (CCHV) [Address 5..8]
Reg.
No. Function
5 header value of the cell copy header octet 1
6 header value of the cell copy header octet 2
7 header value of the cell copy header octet 3
8 header value of the cell copy header octet 4
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14.1.3 Cell copy nibble mask register (CCNM) [Address 9]
Bit Function if bit cleared Function if bit set
0 LS nibble of header octet 1 is don’t care LS nibble of header octet 1 is checked
against the cell copy value 0 LS nibble
1 MS nibble of header octet 1 is don’t care MS nibble of header octet 1 is checked
against the cell copy value 0 MS nibble
2 LS nibble of header octet 2 is don’t care LS nibble of header octet 2 is checked
against the cell copy value 1 LS nibble
3 MS nibble of header octet 2 is don’t care MS nibble of header octet 2 is checked
against the cell copy value 1 MS nibble
4 LS nibble of header octet 3 is don’t care LS nibble of header octet 3 is checked
against the cell copy value 2 LS nibble
5 MS nibble of header octet 3 is don’t care MS nibble of header octet 3 is checked
against the cell copy value 2 MS nibble
6 LS nibble of header octet 4 is don’t care LS nibble of header octet 4 is checked
against the cell copy value 3 LS nibble
7 MS nibble of header octet 4 is don’t care MS nibble of header octet 4 is checked
against the cell copy value 3 MS nibble
14.1.4 Cell copy low index (CCLI) [Address 10]
Bits Function
[5:0] The byte number of the first extracted byte. Value 1 extracts cell header octet 1.
[7:6] Reserved for future extension
14.1.5 Cell copy high index (CCHI) [Address 11]
Bits Function
[5:0] The byte number of the last extracted octet. When extracting only one octet, the
upper value and the lower value must be the same.
[7:6] Reserved for future extension
14.1.6 DRAM CAS additional delay register (DCAD) [Address 12]
Bits Function
[3:0] Additional Delay value for rising edge of DRAM CAS, delay is value(0-15) times 1ns(typical).
[7:4] Additional Delay value for falling edge of DRAM CAS, delay is value(0-15) times 1ns(typical).
14.1.7 DRAM RAS additional delay register (DRAD) [Address 13]
Bits Function
[3:0] Additional Delay value for rising edge of DRAM RAS, delay is value(0-15) times 1ns(typical).
[7:4] Additional Delay value for falling edge of DRAM RAS, delay is value(0-15) times 1ns(typical).
14.1.8 Dynamic ram control register 1 (DRC1) [Address 14]
Bits Function if bit cleared Function if bit set
0 No additional RAS delay Additional RAS delay
1 Fast Page Mode EDO Mode
[7:2] Reserved for future extension
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14.1.9 Revision number/Utopia output FIFO register (RN/UOF) [Address 15]
Bits Function
[3:0] Revision Number: Shap4 is 0000, Shap4-B is 0001
Writing a ’1’ will clear a cell stored in the Utopia output FIFO port 0
4 Writing a ’0’ has no effect
Reading a ’1’ indicates that there is a cell stored in the Utopia output FIFO port 0
Reading a ’0’ indicates that the Utopia output FIFO port 0 is empty
Writing a ’1’ will clear a cell stored in the Utopia output FIFO port 1
5 Writing a ’0’ has no effect
Reading a ’1’ indicates that there is a cell stored in the Utopia output FIFO port 1
Reading a ’0’ indicates that the Utopia output FIFO port 1 is empty
Writing a ’1’ will clear a cell stored in the Utopia output FIFO port 2
6 Writing a ’0’ has no effect
Reading a ’1’ indicates that there is a cell stored in the Utopia output FIFO port 2
Reading a ’0’ indicates that the Utopia output FIFO port 2 is empty
Writing a ’1’ will clear a cell stored in the Utopia output FIFO port 3
7 Writing a ’0’ has no effect
Reading a ’1’ indicates that there is a cell stored in the Utopia output FIFO port 3
Reading a ’0’ indicates that the Utopia output FIFO port 3 is empty
14.1.10 Input control register (IOC) [Address 16]
Bit Function if bit cleared Function if bit set
0 Link input disabled Link input enabled
1 Input HEC byte ignored Input HEC check on
2 Input idle cells passed on Input idle cells removed
3 header_extract without input port header_extract with input port number
number
4 increment time stamp every Rxclk increment time stamp every 53 (or 56)
RxClks
[6:5] cell type
00 input cell 53 bytes, write dram 53 bytes + time stamp
01 input cell 53 bytes + 3 bytes tag, write dram 53 bytes,
+ time stamp (conversion 56 to 53 bytes)
10 input cell 56 bytes, write dram 56 bytes
11 input cell 53 bytes + 3 bytes tag, write dram 53 bytes + 3 bytes tag bytes
7 disable cell (part) copy enable cell (part) copy
14.1.11 Interrupt control register (IC) [Address 17]
Bit(s) Function if bit cleared Function if bit set
0 disable early cell sync interrupt enable early cell sync interrupt
1 disable late cell sync interrupt enable late cell sync interrupt
2 disable missing RxClk interrupt enable missing RxClk interrupt
3 disable counter overflow interrupt of enable counter overflow interrupt of the
the queue control unit queue control unit
4 disable FIFO full interrupt enable FIFO full interrupt
[7:5] must be cleared
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14.1.12 Dynamic ram control register 2 (DRC2) [Address 18]
Bit(s) Function if bit cleared Function if bit set
[1:0] Define the type and size of the external memory. For more details
see the table below.
[4:2] 000 one refresh every 53 (or 56) clks (56 if bit 1 of COLB is set)
001 one refresh every 2*53(or 56) clks (56 if bit 1 of COLB is set)
010 one refresh every 3*53(or 56) clks (56 if bit 1 of COLB is set)
011 one refresh every 4*53(or 56) clks (56 if bit 1 of COLB is set)
100 one refresh every 5*53(or 56) clks (56 if bit 1 of COLB is set)
101 one refresh every 6*53(or 56) clks (56 if bit 1 of COLB is set)
110 one refresh every 7*53(or 56) clks (56 if bit 1 of COLB is set)
111 one refresh every 8*53(or 56) clks (56 if bit 1 of COLB is set)
5 Additional CAS delay No additional CAS delay
[7:6] must be cleared
How the memory bits map onto the physical RAM bits depends on the size of the memory chosen (Bits 0&1 of the Bits 1 and 0
of the Dynamic Ram control register ). The SHAP4-B is intelligent that it uses only the lower address bits if smaller memory is
programmed. The table below shows how the various memory bits map on the output port of the SHAP4-B.
Memory configuration
Bits dr_a signals RAM Addr range Address range Cell storage
[1:0] used configuration bank 0 (hex) bank 1 (hex) (2 banks)
00 0 to 8 256kx32 0 .. 3FFFF 40000 .. 7FFFF 37K cells
01 0 to 9 1Mx32 0 .. FFFFF 100000 .. 1FFFFF 148K cells
10 0 to 10/1174Mx32 0 .. 3FFFFF 400000 .. 7FFFFF 593K cells
11 0 to 11 16Mx32 0 .. FFFFFF 1000000 .. 1FFFFFF 2.3M cells
14.1.13 Class select register (CLA) [Address 19]
Bit(s) Function
[4:0] class select
5 Increment parameter pointer
6 Decrement parameter pointer
7 Reserved for future extension
The increment decrement bits work only if the parameter selection is under software control. (See bit 4 of the cell out control
register).
14.1.14 Leaky Bucket parameter select register (CSL) [Address 20..23]
The
Leaky Bucket parameter select register
is used when operating in single Leaky Bucket mode. Each bit selects for a class if
parameter 1 or parameter 2 is active.
If the bit is cleared parameter 1 is active.
If the bit is set parameter 2 is active.
Leaky Bucket parameter select register 0
controls class 0..7, register one class 8..15, etc. The LS bit controls the lowest class. Thus
bit 0 of
Leaky Bucket parameter select register 0
controls class 0, bit 1 controls class 1, etc.
MS LS
Par. sel. Par. Sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. REG 0
Class 7 Class 6 Class 5 Class 4 Class 3 Class 2 Class 1 Class 0
Par. sel. Par. Sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. REG 1
Class 15 Class 14 Class 13 Class 12 Class 11 Class 10 Class 9 Class 8
Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. REG 2
Class 23 Class 22 Class 21 Class 20 Class 19 Class 18 Class 17 Class 16
Par. sel. Par. Sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. Par. sel. REG 3
Class 31 Class 30 Class 29 Class 28 Class 27 Class 26 Class 25 Class 24
7For asymmetric DRAMs (4M x 32 configuration) with 12 row/10 column address bits.
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14.1.15 Leaky Bucket control register 1 (LBC1) [Address 24]
Bit(s) Function if bit cleared Function if bit set
[5:0] Priority decoder static and round robin select see table hereafter.
6 disable Leaky Bucket operations enable Leaky Bucket operations
7 Dual Leaky Bucket mode Single Leaky Bucket mode
Priority Static Round-Robin Priority Static Round-Robin
code classes classes code classes classes
000000 - 0..31 010001 0..16 17..31
000001 0 1..31 010010 0..17 18..31
000010 0..1 2..318010011 0..18 19..31
000011 0..2 3..31 010100 0..19 20..31
000100 0..3 4..31 010101 0..20 21..31
000101 0..4 5..31 010110 0..21 22..31
000110 0..5 6..31 010111 0..22 23..31
000111 0..6 7..31 011000 0..23 24..31
001000 0..7 8..31 011001 0..24 25..31
001001 0..8 9..31 011010 0..25 26..31
001010 0..9 10..31 011011 0..26 27..31
001011 0..10 11..31 011100 0..27 28..31
001100 0..11 12..31 011101 0..28 29..31
001101 0..12 13..31 011110 0..29 30..31
001110 0..13 14..31 011111 0..30 31
001111 0..14 15..31 100000 0..31 -
010000 0..15 16..31
14.1.16 Leaky Bucket 2/RxEnb control register (LBC2) [Address 25]
Bit(s) Function if bit cleared Function if bit set
0 normal Leaky Bucket operations grouping of classes, 0 to 1 static, 2 to 11
groups round robin
1 disable RxEnb* assertion on FIFO full Assert RxEnb* with FIFO full
2 disable RxEnb* assertion on TxClav Assert RxEnb* with TxClav
3 Assert RxEnb* at the end of the cell Assert RxEnb* directly
4 RxEnb* bit if bit 1,2 = ’0’
5 signal sta_val active LOW signal sta_val active HIGH
[7:6] Reserved for future extension
For group mode the priority code in the LBC1 bits 5..0 should be set to 000010.
If bits 1 and 2 are set the RxEnb* signal is asserted if either of these conditions happens
14.1.17 Parameter set control register (PSC) [Address 26]
Bit(s) Function if bit cleared Function if bit set
[4:0] Parameter set
[6:5] decrement mode:
00 : new parameter set pointer = old parameter set pointer - 1
01 : new parameter set pointer = old parameter set pointer * 3/4
10 : new parameter set pointer = old parameter set pointer * 1/2
11 : new parameter set pointer = old parameter set pointer * 1/4
(See also the conversion table below)
7 write parameter set pointer to external write parameter set to external static ram
static ram
8This value should be used if group shaping is enabled.
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14.1.18 Cell out control register (COLB) [Address 27]
Bit(s) Function if bit cleared Function if bit set
0 cell out ctrl produces gaps of one cell cell out ctrl produces idle cells
1 cell out ctrl send 53 bytes/cell cell out ctrl send 56 bytes/cell
2 Idle cell with 3 zero tag bytes if bit 1 is set Idle cell with 51 byte idle payload if bit 1 is set.
3 must be cleared
4 discard CLP cell with CLP level > LEVEL do not discard
[6:5] 00 All Classes work normally
01 Class 0 works in circular mode, all others normal
10 Class 8..23 in circular mode, Class 0..7 and 24..31 in normal mode
11 All Classes in circular mode
7 must be cleared
If cell size is 53 bytes (bit 1 is cleared) bit 2 is don’t care.
Note that bit 1 also influences the rate of the classes (See chapter 3.1 Rate parameters).
14.1.19 Transfer control register (TRC) [Address 48]
Bit(s) Function if bit cleared Function if bit set
0 Transfer from device to up register Transfer from up register to device
[3:1] action:
000 : read/write from register to the class lookup table in the external dynamic ram
001 : read/write from register to the on chip queue control ram
010 : read/write from register to the on chip Leaky Bucket Level or Parameter ram
(depending on bit 4 of the
transfer control register
)
011 : read/write from register to the parameter data or pointer of the external static ram
(depending on bit 7 of the
parameter set control register
)
100 : read/write from register to the cell interface unit
110 : read/write from register to the output port table
4 read/write Parameter read/write Level
5 toggles every 53/56 clks depending on bit 1 of the
cell out control register
6 cell interface busy cell interface ready
7 Transfer still pending Transfer is ready
14.1.20 Input status register (IS) [Address 49]
Bit(s) Alarm condition
0 Early cell sync
1 Late cell sync
2 Missing RxClk
3 counter overflow irq of queue control
4 FIFO full, cell may be discarded
[7:5] don’t care
14.2 All purpose data register
The device has an
all purpose data register
used for data transfer between the microprocessor and the various storage locations. The
following storage locations can be identified:
Class lookup table in external dynamic RAM
Cell storage in external dynamic RAM
Parameter set table in external static RAM
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Parameter set pointer table in external static RAM
Queue control parameters in internal RAM
Leaky Bucket parameters in internal RAM
Leaky Bucket level in internal RAM
Output port table
The
transfer control register
described above specifies:
Which storage location is accessed.
If a transfer is made from or to a storage location.
For each of the seven possible storage locations a description of the
all purpose data register
is given.
14.2.1 Transferring from or to class lookup table
Register Bits Function
0 [4:0] selected class for extracted cell header address + 0
[7:5] don’t care
1 [4:0] selected class for extracted cell header address + 1
[7:5] don’t care
2 [4:0] selected class for extracted cell header address + 2
[7:5] don’t care
3 [4:0] selected class for extracted cell header address + 3
[7:5] don’t care
4 [7:0] Memory address bits [7:0]
5 [X:0] Memory address bits [X:8]
[X+1:7] Should be zero for lookup table access
6 [7:0] Should be zero for lookup table access
7 0 Should be zero for lookup table access
[7:1] don’t care
8..19 [7:0] don’t care
The register description given above is valid if reading data from the lookup table or writing data to the lookup table. The value of
X equals the number of header extraction mask bits set minus 2. However the command to access the look-up table can be used
in general to read from or write to the dynamic RAM. Although the complete 32 bits are transferred the lookup function of the
SHAP4-B uses only the LS 5 bits of each byte. The format shown below is valid for a general memory access.
14.2.2 Transferring from/to memory using class lookup table transfer command:
Register Bits Function
0 [7:0] Byte from memory bits [7:0]
1 [7:0] Byte from memory bits [15:8]
2 [7:0] Byte from memory bits [23:16]
3 [7:0] Byte from memory bits [31:24]
4 [7:0] Memory address bits [7:0]
5 [7:0] Memory address bits [15:8]
6 [7:0] Memory address bits [23:16]
7 0 Memory address bit 24
[7:1] don’t care
8..19 [7:0] don’t care
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14.2.3 Transferring from or to on chip Leaky Bucket Level RAM
Register Bits Function
0 0 don’t care
[7:1] Leaky Bucket 1 level fraction bits [6:0]
1 [7:0] Leaky Bucket 1 level bits [7:0]
2 [7:0] Leaky Bucket 1 level bits [15:8]
3 [7:0] Leaky Bucket 1 level bits [23:16]
4 0 don’t care
[7:1] Leaky Bucket 2 level fraction bits [6:0]
5 [7:0] Leaky Bucket 2 level bits [7:0]
6 [7:0] Leaky Bucket 2 level bits [15:8]
7 [7:0] Leaky Bucket 2 level bits [23:16]
8..19 [7:0] don’t care
The level of the LB’s for each class can be set independent of the rest of the Leaky Bucket parameters.
14.2.4 Transferring from/to Leaky Bucket Parameter set in internal or external RAM
Register Bits Function
0 [7:0] Leaky Bucket 1 limit bits [7:0]
1 [7:0] Leaky Bucket 1 limit bits [15:8]
2 [7:0] Leaky Bucket 1 limit bits [23:16]
3 [7:0] Leaky Bucket 2 limit bits [7:0]
4 [7:0] Leaky Bucket 2 limit bits [15:8]
5 [7:0] Leaky Bucket 2 limit bits [23:16]
6 [7:0] Leaky Bucket 1 splash bits [7:0]
7 [7:0] Leaky Bucket 2 splash bits [7:0]
8 [3:0] Leaky Bucket 1 leak bits [3:0]
[7:4] Leaky Bucket 2 leak bits [3:0]
9 [4:0] parameter set pointer
[7:5] don’t care
10..19 [7:0] don’t care
The parameter set pointer is related with the static parameter RAM. It points to the parameter set currently in use. As this value
can be controlled externally (using the PAR_INC and PAR_DEC signals) it is always possible that the actual parameter set pointer
differs from the one read.
14.2.5 Transferring from/to Leaky Bucket Parameter set pointer table in external RAM
Register Bits Function
0..8 [7:0] don’t care
9 [4:0] parameter set pointer
[7:5] don’t care
10..19 [7:0] don’t care
The parameter set pointer is special. When reading a parameter set from the external static RAM the parameter set as well as the
pointer are loaded. However when writing to the external static RAM first the pointer must be written and then a second write
command is needed to transfer the parameter set to the entry to which the pointer is pointing.
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14.2.6 Transferring from/to on chip queue control RAM
Register Bits Function if bit is cleared Function if bit is set
0 [7:0] queue base address bits [7:0]
1 [4:0] queue base address bits [12:8]
5 if the counter reaches the maximum value, the If the counter reaches the maximum value, roll
counter holds this value. over and set status bit.
6 count all discarded cells (discarded because count only cells discarded because the queue
the queue is full or level>indication level). is full.
7 This bit is used by the queue control algorithm and must be cleared when the queue control
parameters are initialized.
2 [7:0] queue size in cells bits [7:0]
3 [7:0] queue size in cells bits [15:8]
4 [4:0] queue size in cells bits [20:16]
[7:5] don’t care
5 [7:0] indication level bits [7:0]
6 [7:0] indication level bits [15:8]
7 [4:0] indication level bits [20:16]
[7:5] don’t care
8 [7:0] discarded cells counter bits [7:0]
9 [7:0] discarded cells counter bits [15:8]
10 [3:0] discarded cells counter bits [19:16]
[7:4] don’t care
11 [7:0] Write pointer bits [7:0]9
12 [7:0] Write pointer bits [15:8]
13 [4:0] Write pointer bits [20:16]
[7:5] don’t care
14 [7:0] Read pointer bits [7:0]
15 [7:0] Read pointer bits [15:8]
16 [4:0] Read pointer bits [20:16]
[7:5] don’t care
17 [7:0] queue level in cells bits [7:0]. This register is automatically updated when a parameter is read
from on chip queue control RAM.
18 [7:0] queue level in cells bits [15:8]. This register is automatically updated when a parameter is read
from on chip queue control RAM.
19 [4:0] queue level in cells bits [20:16].
5 queue is not empty queue is empty
6 queue is not full queue is full
7 queue length is
than the indication level queue length is above the indication level
All purpose data register
19 is automatically updated when the queue parameters are read from the on chip queue control RAM.
14.2.7 Transferring from/to the cell interface unit
Register Function
0 cell data 0
1 cell data 1
2 cell data 2
3 cell data 3
4..19 don’t care
The cell interface unit allows the user to access a cell in the memory reading or writing 4 bytes at the time.
14.2.8 Transferring from/to the output port table
The output port table assigns an output port to each class.
9The Write pointer and Read pointer bits must be cleared when the queue control parameters are initialized.
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Register Bits Function
0 [1:0] output port number class 0
[3:2] output port number class 1
[5:4] output port number class 2
[7:6] output port number class 3
1 [1:0] output port number class 4
[3:2] output port number class 5
[5:4] output port number class 6
[7:6] output port number class 7
2 [1:0] output port number class 8
[3:2] output port number class 9
[5:4] output port number class 10
[7:6] output port number class 11
3 [1:0] output port number class 12
[3:2] output port number class 13
[5:4] output port number class 14
[7:6] output port number class 15
4 [1:0] output port number class 16
[3:2] output port number class 17
[5:4] output port number class 18
[7:6] output port number class 19
5 [1:0] output port number class 20
[3:2] output port number class 21
[5:4] output port number class 22
[7:6] output port number class 23
6 [1:0] output port number class 24
[3:2] output port number class 25
[5:4] output port number class 26
[7:6] output port number class 27
7 [1:0] output port number class 28
[3:2] output port number class 29
[5:4] output port number class 30
[7:6] output port number class 31
Code 00 selects output port 0, Code 01 selects output port 1, etc.
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15 Signal description
15.1 ATM input port
Name I/O Description
RxData[7:0] Input ATM in data: These signals hold the 8 bit wide data. All arriving data between the last
byte of the previous cell and the first byte of the following cell (indicated by the SOC
signal) is ignored.
RxSOC Input ATM in cell sync: This signal is high during the first byte of an arriving cell. After this
signal is high the following 52 (or 55) bytes should contain valid data. The SHAP4-B
waits for another RxSOC signal after reading a complete cell.
RxClk Input ATM in byte clock: Up to 40 MHz. This signal is the clock of the incoming data.
Data is sampled after the rising edge of this signal.
RxEnb*[3:0] Output Enable: This signal is asserted by the SHAP4-B to indicate that RxData and RxSOC will
be sampled at the end of the next cycle.
RxClav[3:0] Input Cell Available: This signal is asserted by an external device to indicate it has data to
send.
15.2 ATM output ports
The signal TxClk (ATM out byte clock) is the system clock clk. This signal is the clock of the outgoing data. Data of the ATM
output ports changes after the rising edge of this signal.
Name I/O Description
TxData[7:0] Output ATM data output: These signals output the 8 bit wide data.
TxSOC Output ATM cell sync output: This signal is high during the first byte of a cell.
TxOE* Input ATM cell sync, data enable: If low it enables the cell sync and the data signal. If high
the cell sync and the data signal is tri-state.
TxEnb*[3:0] Output Enable: It will be low when a cell (including idle cells) is being transmitted at the
output.
TxClav[3:0] Input Cell Available: This signal is an active high signal from an external device. The
external device should assert this signal to indicate it can accept the transfer of a
complete cell.
15.3 Dynamic memory interface
Name I/O Description
dr_d[31:0] I/O Dynamic memory data bus: These signals hold data to be exchanged between the
SHAP4-B and the external dynamic memory.
dr_a[11:0] Output Dynamic memory address bus: These signals are used to select an entry in the
external dynamic memory.
dr_r/w* Output Dynamic memory read/not write: If
low
data is written from the SHAP4-B to the
memory. If
high
data is read from the memory to the SHAP4-B.
dr_ras0* Output Dynamic Memory Row Address Strobe bank 0: It is used to signal that the address
bus holds a valid row address for memory bank 0.
dr_ras1* Output Dynamic Memory Row Address Strobe bank 1: It is used to signal that the address
bus holds a valid row address for memory bank 1.
dr_cas* Output Dynamic Memory Column Address Strobe: It is used to signal that the address bus
holds a valid column address.
15.4 Static memory interface
The static memory is optional. It can store up to 32 parameter sets for each Leaky Bucket and for each class.
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Name I/O Description
sr_d[7:0] I/O Static memory data bus: They hold data to be exchanged between the SHAP4-B and the
external static memory.
sr_a[13:0] Output Static memory address bus: They are used to select an entry in the external static
memory.
sr_we* Output Static memory read/not write: If
low
data is written from the SHAP4-B to the memory.
If
high
data is read from the memory to the SHAP4-B.
sr_cs* Output Static memory chip select: If this signal is
low
the transfer to/from static RAM starts.
15.5 Microprocessor interface
For data transfer between the SHAP4-B and the local microprocessor
Name I/O Description
up_d[7:0] I/O Microprocessor data bus: These signals hold the data to be exchanged between the
SHAP4-B and a local microprocessor.
up_a[5:0] Input Microprocessor address bus: These signals are used to select one of the 37 direct
accessible register of the SHAP4-B.
up_r/w* Input Microprocessor read/not write - Motorola Mode: If
low
data is written from
the microprocessor to the SHAP4-B. If
high
data is read from the SHAP4-B to the
microprocessor.
Microprocessor not write - Intel Mode: If
low
data is written from the micro-
processor to the SHAP4-B.
up_oe*/ Input Microprocessor output enable - Motorola Mode: This signal should be
low
up_rd* for Motorola timing mode.
Microprocessor not read - Intel Mode: If
low
data is read from the SHAP4-B to the
microprocessor.
up_cs* Input Microprocessor Chip select: If this signal is
high
the SHAP4-B ignores all other signals
on it’s microprocessor bus. If this signal is
low
the SHAP4-B accepts the signals on it’s
microprocessor bus. When up_r/w* is
low
this signal should be glitch-free as in that
case data is loaded into the SHAP4-B at it’s rising edge.
up_irq* Output Microprocessor Interrupt Request: If this signal is
low
the SHAP4-B signals to the
microprocessor that an interrupt condition is pending inside the SHAP4-B. Otherwise no
interrupt is pending inside the SHAP4-B.
DMAREQ* Output DMA Request: This signal is internally connected to bit 7 of the
transfer control
register
. If this signal is
high
the DMA controller can transfer data to/from the SHAP4-B.
If this signal is
low
the DMA controller should stop sending/reading data from/to the
SHAP4-B.
15.6 Parameter select
Allows fast Leaky Bucket Parameter change.
Name I/O Description
class[4:0] Input Selected class number: They hold the class number for the increment or decrement
operation started by a Par_inc or Par_dec puls.
Par_dec Input Parameter decrement signal: A low to high pulse decrements the parameter set
pointer of the class given by the class signal and transfers the calculated parameter set
(of this class) to the on chip parameter RAM.
Par_inc Input Parameter increment signal: A low to high pulse increments the parameter set pointer
of the class given by the class signal and transfers the calculated parameter set (of this
class) to the on chip parameter RAM.
15.7 Status port
Shows the fill level of the queues
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Name I/O Description
sta_A[2:0] Output Queue status address: These signals form the MS 3 address bits of the Class number
who’s queue status is being output.
sta_D[7:0] Output Queue status data: These signals hold the status of the queue levels.
sta_val Output Queue status valid: It signals when the sta_Ax and sta_Dx signals are valid. It can be
programmed to be high or low active.
15.8 Extra cell port
Allows copying of complete or partial data from special cells from the data stream.
Name I/O Description
ex_start Output cell copy data start: It is high during the first byte output of the extra cell data.
ex_val Output cell copy data valid: It is asserted during each byte output of the extra cell data.
ex_D[7:0] Output cell copy data: These signals hold the data of the extra cells.
15.9 System signals
Name I/O Description
clk Input System clock: Up to 40 MHz see chapter 13.1.1. In the SHAP4-B this clock is used for
the memory controller, Leaky Bucket algorithm and the generation of the output
signals.
Test* Input Test signal: This signal is used for scan test. This signal should be
high
for normal
operation.
Reset* Input System reset: This is an active low input signal. This signal will cause the device to
enter the initial state.
bist Input This signal should be
low
for normal operation.
icptn Input This signal should be
high
for normal operation.
15.10 JTAG signals
Name I/O Description
Tdi Input JTAG Test Data Input: This signal needs an external Pull-up for JTAG operation.
Tms Input JTAG Test Mode Select Input: This signal needs an external Pull-up for JTAG operation.
Tck Input JTAG Test Clock Input: Connect this pin to ground for normal operation.
Trst* Input JTAG Test Reset Input: Connect this pin to ground for normal operation. This signal
needs an external Pull-up for JTAG operation.
Tdo Output JTAG Test Data Output.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
16 Pin Configuration
16.1 Pin Diagram: 208 Pin PQFP
Figure 33: Pin Diagram SHAP4-B
16.2 Pin Description
Pin No. Pin Name Type Description
1 gnd_pad Ground 0 Volt
2 vdd_pad Power 3.3 Volt
3 up_d6 I/O microprocessor data bus bit 6
4 up_d7 I/O microprocessor data bus bit 7
5 up_a0 Input microprocessor addr. Bus bit 0
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Pin No. Pin Name Type Description
6 up_a1 Input microprocessor addr. Bus bit 1
7 up_a2 Input microprocessor addr. Bus bit 2
8 up_a3 Input microprocessor addr. Bus bit 3
9 gnd_core Ground 0 Volt
10 vdd_core Power 3.3 Volt
11 up_a4 Input microprocessor addr. Bus bit 4
12 up_a5 Input microprocessor addr. Bus bit 5
13 test* Input test signal used for scan test
14 trst* Input JTAG test reset input
15 tdo Output JTAG test data output
16 tck Input JTAG test clock input
17 tms Input JTAG test mode select input
18 tdi Input JTAG test data input
19 clk Input system clock
20 gnd_pad Ground 0 Volt
21 vdd_pad Power 3.3 Volt
22 sr_d7 I/O static ram data bus bit 7
23 sr_d6 I/O static ram data bus bit 6
24 sr_d5 I/O static ram data bus bit 5
25 bist Input should be connected to Ground
26 icptn Input should be connected to 3.3 Volt
27 sr_d4 I/O static ram data bus bit 4
28 sr_d3 I/O static ram data bus bit 3
29 sr_d2 I/O static ram data bus bit 2
30 sr_d1 I/O static ram data bus bit 1
31 sr_d0 I/O static ram data bus bit 0
32 sr_a13 Output static ram addr. bus bit 13
33 sr_a12 Output static ram addr. bus bit 12
34 sr_a11 Output static ram addr. bus bit 11
35 sr_a10 Output static ram addr. bus bit 10
36 gnd_pad Ground 0 Volt
37 vdd_pad Power 3.3 Volt
38 sr_a9 Output static ram addr. bus bit 9
39 sr_a8 Output static ram addr. bus bit 8
40 sr_a7 Output static ram addr. bus bit 7
41 sr_a6 Output static ram addr. bus bit 6
42 sr_a5 Output static ram addr. bus bit 5
43 sr_a4 Output static ram addr. bus bit 4
44 sr_a3 Output static ram addr. bus bit 3
45 gnd_pad Ground 0 Volt
46 vdd_pad Power 3.3 Volt
47 sr_a2 Output static ram addr. bus bit 2
48 sr_a1 Output static ram addr. bus bit 1
49 sr_a0 Output static ram addr. bus bit 0
50 sr_we* Output static ram write/not read
51 sr_cs* Output static ram chip select
52 class4 Input class value bit 4
53 class3 Input class value bit 3
54 class2 Input class value bit 2
55 class1 Input class value bit 1
56 class0 Input class value bit 0
57 gnd_pad Ground 0 Volt
58 vdd_pad Power 3.3 Volt
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Pin No. Pin Name Type Description
59 Par_dec Input decrement parameter set
60 Par_inc Input increment parameter set
61 TxEnb0* Output Asserted by the SHAP4-B if ATM data is output for device 0
62 TxEnb1* Output Asserted by the SHAP4-B if ATM data is output for device 1
63 gnd_core Ground 0 Volt
64 vdd_core Power 3.3 Volt
65 TxEnb2* Output Asserted by the SHAP4-B if ATM data is output for device 2
66 TxEnb3* Output Asserted by the SHAP4-B if ATM data is output for device 3
67 TxClav0 Input Asserted by external device 0 to signal it can accept a cell from the SHAP4-B
68 TxClav1 Input Asserted by external device 1 to signal it can accept a cell from the SHAP4-B
69 TxClav2 Input Asserted by external device 2 to signal it can accept a cell from the SHAP4-B
70 TxClav3 Input Asserted by external device 3 to signal it can accept a cell from the SHAP4-B
71 gnd_pad Ground 0 Volt
72 vdd_pad Power 3.3 Volt
73 TxSOC Output ATM output port cell sync
74 TxOE* Input ATM output port tristate data and cell sync
75 TxData7 Output ATM output port data bit 7
76 TxData6 Output ATM output port data bit 6
77 TxData5 Output ATM output port data bit 5
78 TxData4 Output ATM output port data bit 4
79 TxData3 Output ATM output port data bit 3
80 TxData2 Output ATM output port data bit 2
81 gnd_pad Ground 0 Volt
82 vdd_pad Power 3.3 Volt
83 TxData1 Output ATM output port data bit 1
84 TxData0 Output ATM output port data bit 0
85 dr_d31 I/O dynamic ram data bus bit 31
86 dr_d30 I/O dynamic ram data bus bit 30
87 dr_d29 I/O dynamic ram data bus bit 29
88 dr_d28 I/O dynamic ram data bus bit 28
89 dr_d27 I/O dynamic ram data bus bit 27
90 dr_d26 I/O dynamic ram data bus bit 26
91 dr_d25 I/O dynamic ram data bus bit 25
92 gnd_pad Ground 0 Volt
93 vdd_pad Power 3.3 Volt
94 dr_d24 I/O dynamic ram data bus bit 24
95 dr_d23 I/O dynamic ram data bus bit 23
96 dr_d22 I/O dynamic ram data bus bit 22
97 dr_d21 I/O dynamic ram data bus bit 21
98 dr_d20 I/O dynamic ram data bus bit 20
99 dr_d19 I/O dynamic ram data bus bit 19
100 dr_d18 I/O dynamic ram data bus bit 18
101 dr_d17 I/O dynamic ram data bus bit 17
102 dr_d16 I/O dynamic ram data bus bit 16
103 gnd_pad Ground 0 Volt
104 vdd_pad Power 3.3 Volt
105 dr_r/w* Output dynamic ram read/not write
106 dr_ras1* Output dynamic ram row address strobe bank 1
107 dr_ras0* Output dynamic ram row address strobe bank 0
108 dr_cas* Output dynamic ram coloum address strobe
109 dr_a11 Output dynamic ram addr. bus bit 11
110 dr_a10 Output dynamic ram addr. bus bit 10
111 dr_a9 Output dynamic ram addr. bus bit 9
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Pin No. Pin Name Type Description
112 dr_a8 Output dynamic ram addr. bus bit 8
113 dr_d15 I/O dynamic ram data bus bit 15
114 gnd_pad Ground 0 Volt
115 vdd_pad Power 3.3 Volt
116 gnd_core Ground 0 Volt
117 vdd_core Power 3.3 Volt
118 dr_d14 I/O dynamic ram data bus bit 14
119 dr_d13 I/O dynamic ram data bus bit 13
120 dr_d12 I/O dynamic ram data bus bit 12
121 dr_d11 I/O dynamic ram data bus bit 11
122 dr_d10 I/O dynamic ram data bus bit 10
123 dr_d9 I/O dynamic ram data bus bit 9
124 dr_d8 I/O dynamic ram data bus bit 8
125 dr_a7 Output dynamic ram addr. bus bit 7
126 gnd_pad Ground 0 Volt
127 vdd_pad Power 3.3 Volt
128 dr_a6 Output dynamic ram addr. bus bit 6
129 dr_a5 Output dynamic ram addr. bus bit 5
130 dr_a4 Output dynamic ram addr. bus bit 4
131 dr_a3 Output dynamic ram addr. bus bit 3
132 dr_a2 Output dynamic ram addr. bus bit 2
133 dr_a1 Output dynamic ram addr. bus bit 1
134 dr_a0 Output dynamic ram addr. bus bit 0
135 dr_d7 I/O dynamic ram data bus bit 7
136 dr_d6 I/O dynamic ram data bus bit 6
137 gnd_pad Ground 0 Volt
138 vdd_pad Power 3.3 Volt
139 dr_d5 I/O dynamic ram data bus bit 5
140 dr_d4 I/O dynamic ram data bus bit 4
141 dr_d3 I/O dynamic ram data bus bit 3
142 dr_d2 I/O dynamic ram data bus bit 2
143 dr_d1 I/O dynamic ram data bus bit 1
144 dr_d0 I/O dynamic ram data bus bit 0
145 sta_A0 Output Status Class address bit 210
146 sta_A1 Output Status Class address bit 3
147 gnd_pad Ground 0 Volt
148 vdd_pad Power 3.3 Volt
149 sta_A2 Output Status Class address bit 4
150 sta_D0 Output Status Class 4n11 LS data bit
151 sta_D1 Output Status Class 4n MS data bit
152 sta_D2 Output Status Class 4n+1 LS data bit
153 sta_D3 Output Status Class 4n+1 MS data bit
154 sta_D4 Output Status Class 4n+2 LS data bit
155 gnd_pad Ground 0 Volt
156 vdd_pad Power 3.3 Volt
157 sta_D5 Output Status Class 4n+2 MS data bit
158 sta_D6 Output Status Class 4n+3 LS data bit
159 sta_D7 Output Status Class 4n+3 MS data bit
160 sta_val Output Status Class address and data bits are valid
161 RxData0 Input ATM input port data bit 0
162 RxData1 Input ATM input port data bit 1
10The status of 4 classes are output at the same time. Thus the Class address bit 0 and 1 do not exist
11n is the range 0..7. Thus we have class 0-3/4-7/8-11/12-15/16-19/20-23/24-27/28-31
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Pin No. Pin Name Type Description
163 RxData2 Input ATM input port data bit 2
164 RxData3 Input ATM input port data bit 3
165 RxData4 Input ATM input port data bit 4
166 RxData5 Input ATM input port data bit 5
167 gnd_core Ground 0 Volt
168 vdd_core Power 3.3 Volt
169 RxData6 Input ATM input port data bit 6
170 RxData7 Input ATM input port data bit 7
171 RxSOC Input ATM input port cell sync
172 RxEnb0* Output Asserted by the SHAP4-B if data may be sent by device 0
173 RxEnb1* Output Asserted by the SHAP4-B if data may be sent by device 1
174 RxEnb2* Output Asserted by the SHAP4-B if data may be sent by device 2
175 RxEnb3* Output Asserted by the SHAP4-B if data may be sent by device 3
176 RxClav0 Input Asserted by device 0 if it has a cell for the SHAP4-B
177 RxClav1 Input Asserted by device 1 if it has a cell for the SHAP4-B
178 RxClav2 Input Asserted by device 2 if it has a cell for the SHAP4-B
179 RxClav3 Input Asserted by device 3 if it has a cell for the SHAP4-B
180 RxClk Input ATM input port byte clock
181 gnd_pad Ground 0 Volt
182 vdd_pad Power 3.3 Volt
183 ex_start Output Indicates first byte of cell copy data output
184 ex_val* Output Asserted during each byte of cell copy data output
185 ex_D0 Output Cell copy data output bit 0
186 ex_D1 Output Cell copy data output bit 1
187 ex_D2 Output Cell copy data output bit 2
188 ex_D3 Output Cell copy data output bit 3
189 ex_D4 Output Cell copy data output bit 4
190 ex_D5 Output Cell copy data output bit 5
191 ex_D6 Output Cell copy data output bit 6
192 ex_D7 Output Cell copy data output bit 7
193 gnd_pad Ground 0 Volt
194 vdd_pad Power 3.3 Volt
195 up_oe*/up_rd* Input microprocessor output enable, should be Ground (Motorola
p-Interface),
microprocessor read (Intel
p-Interface),
196 Reset* Input system reset
197 DMAREQ* Output SHAP4-B transfer busy
198 up_irq* Output microprocessor interrupt req.
199 up_r/w* Input microprocessor read/not write
200 up_cs* Input microprocessor chip select
201 gnd_core Ground 0 Volt
202 vdd_core Power 3.3 Volt
203 up_d0 I/O microprocessor data bus bit 0
204 up_d1 I/O microprocessor data bus bit 1
205 up_d2 I/O microprocessor data bus bit 2
206 up_d3 I/O microprocessor data bus bit 3
207 up_d4 I/O microprocessor data bus bit 4
208 up_d5 I/O microprocessor data bus bit 5
All power and ground pads must be connected. Leaving some power or ground pads open while others are connected will cause
permanent damage to the device (see chapter 21.1 Connecting the power and ground pads for more information).
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
17 Mechanical Information
Figure 34: 208 Pin Copper Leadframe Short Plastic Quad Flat Pack
208 Pin Copper Leadframe Short Plastic Quad Flat Pack
Dimension Minimum Nominal Maximum
A 4.20
A1 0.25
A2 3.17 3.42 3.67
D 30.35 30.60 30.85
D1 27.90 28.00 28.10
E 30.35 30.60 30.85
E1 27.90 28.00 28.10
L 0.40 0.60 0.80
P 0.50
B 0.17 0.28
All dimensions in millimeters
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
18 Timing diagrams
18.1 CPU Interface Timing
The CPU Interface of the SHAP4-B supports both the Motorola and Intel timing modes. No Mode Select pin is required.
With Motorola devices, the Motorola r/w* signal is connected to the up_r/w* pin and the up_oe* pin is tied to ground. There is no
DS signal and the up_cs* signal is taken to be qualified with the DS signal.
When used with Intel devices, the read signal is connected to the up_oe* pin and the write signal is connected to the up_r/w* pin.
When performing a read operation, data is placed on the bus immediately after up_cs* signal is
low
for the Motorola timing mode
and after the up_cs* and up_oe* signals are
low
for Intel timing.
When performing a write operation in Motorola timing mode, the data is clocked into an SHAP4-B pre-load register on the rising
edge of the up_cs* signal. In Intel timing mode, the data is clocked into an SHAP4-B pre-load register on the rising edge of the
up_r/w* signal. Right after that transition, the data is transferred to the SHAP4-B internal register. Writing data into this register
can take up to 2 system clock cycles.
18.1.1 Read Cycle - Motorola and Intel Timing
Characteristics Sym Min Typ Max Units
1 R/W* setup time to up_cs* falling edge tWS 1 ns
2 data valid after up_oe*, up_cs* or up_a[5:0] tACC 17 ns
3 up_a[5:0] or up_r/w* hold time after up_cs* rising edge tAH 0 ns
4 Data hold time after rising edge of up_cs* or up_oe* tCH 1.5 ns
5 up_d[7:0] low impedance after falling edge of up_oe* tOE 2 14 ns
t
ACC
t
t
Data Valid
Address Valid
CH
WS
tOE
up_a[5:0]
AH
up_d[7:0]
up_oe*/up_rd*
up_cs*
up_r/w*
CH
t
t
Figure 35: Microprocessor read timing
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18.1.2 Write Cycle - Motorola Timing
Characteristics Sym Min Typ Max Units
1 up_r/w* setup time to up_cs* falling edge tWS 1 ns
2 Address and Data setup before rising edge tSU 5 ns
of up_cs*
3 up_a[5:0] and up_d[7:0] hold time after up_cs* tADH 0 ns
rising edge
4 up_r/w* low after rising edge of up_cs* tWH 0 ns
5 up_cs* high before next up_cs* low tCSH 12 2 system
clock
cycles
!!!!!!!!
"""""""
# #
$ $
% %&
WS
up_a[5:0]
up_d[7:0]
up_oe*/up_rd*
up_cs*
up_r/w*
Data Valid
Address Valid
t
tWH
tADH
tCSH
tSU
Figure 36: Microprocessor write timing - Motorola Mode
18.1.3 Write Cycle - Intel Timing
Characteristics Sym Min Typ Max Units
1 up_cs* setup time to up_r/w* falling edge tWS 1 ns
2 Address and Data setup before rising edge of up_r/w* tSU 5 ns
3 up_a[5:0], up_cs* and up_d[7:0] hold time after up_r/w* tADH 0 ns
rising edge
4 up_r/w* low after rising edge of up_cs* tCSH 1 ns
5 up_cs* high before next up_cs* low tWH 12 2 system
clock
cycles
18.2 DRAM Interface Timing
For the rest of the system almost all delay times are the same. In fact there are only two delay times:
Control signals from clock.
These are marked in the timing diagrams with number tD
12For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
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up_a[5:0]
up_d[7:0]
up_oe*/up_rd*
up_cs*
Data Valid
Address Valid
tADH
tSU
WS
t
up_r/w* tWH
tCSH
Figure 37: Microprocessor write timing - Intel Mode
Data signal from clock.
These are marked in the timing diagrams with number tSD.
Note that for the ATM-input signals the setup and hold times are related to the Rxclk, not the system clock.
# Description Sym Min. Typ Max Units
1 Control signal delay from system clock tD2 9 ns
2 Data signal delay from system clock tSD 2 16 ns
3 Signal setup against system clock edge tSC 0 ns
4 Signal hold after system clock edge tHC 2 ns
The followingtiming diagrams have a commonrun of the RAS signal in respect of the Fast Page and EDO Mode. The hatched area,
marked with “*”, shows the rising edge of the RAS signal during a ram access - the left bar is the rising edge in Fast Page mode,
the right one for EDO mode.
Column
clk
dr_ras0/1*
Data in
t
t
t
tt t
t
t
t
SC
HC
D
D
D
D D D
D
ColumnRow Column
dr_cas*
dr_d[31:0]
dr_r/w*
Data in Data in Data in
dr-a[11:0] *
Figure 38: Timing diagram read cell of the DRAM
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Column
clk
dr_ras0/1*
t
t
tt t
t
D
D
D D D
D
tD
Data out Data out Data out
tt SDSD
Column Column
dr_cas*
dr_d[31:0]
dr_r/w*
dr-a[11:0] Row
*
Figure 39: Timing diagram write cell of the DRAM
!
" "
# #
$$$
$$$
$$$
%%%
%%%
%%%
dr_ras0/1*
t
t
t
D
D
D
ColumnRow
dr_cas*
dr-a[11:0]
D
t
tD
Data in
tHC
dr_d[31:0]
dr_r/w*
tDtSC
clk
*
Figure 40: Microprocessor word read from dram memory
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
dr_ras0/1*
t
t
t
D
D
D
ColumnRow
dr_cas*
dr-a[11:0]
D
t
tD
tD
*
tSD
Data out
tSD
dr_r/w*
dr_d[31:0]
clk
Figure 41: Microprocessor word write to dram memory
clk
dr_ras0/1*
tD
dr-a[11:0] Refresh
tD
tD
tD
*
dr_cas*
Figure 42: Timing diagram refresh of the DRAM
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# Description Sym Min. Typ Max Units
1 CLK periode width tTCLK 24 25 ns
2 CLK periode width LOW tTCLKL 12.5 ns
3 CLK periode width HIGH tTCLKH 12.5 ns
4 CLK rising tCLKR 3 ns
5 CLK falling tCLKF 3 ns
6 Reset* pulse width tRST 10 system
clock
cycles
clk
rst
Reset*
t
t
tclklttclkh
ttclk
t tclkrl clkrf
Figure 43: Timing diagram System Clock and Reset
# Description Sym Min. Typ Max Units
1 TCK periode width tTCK 100 ns
2 TCK periode width LOW tTCKL 40 ns
3 TCK periode width HIGH tTCKH 40 ns
4 TDI setup time to TCK rising tTDIsu 1 ns
5 TDI hold time after TCK rising tTDIh 1 ns
6 TMS setup time to TCK rising tTMSsu 1 ns
7 TMS hold time after TCK rising tTMSh 1.5 ns
8 TDO delay from TCK falling tTDOd 1.5 12 ns
9 TRST* pulse width tTRST 15 ns
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TCKh
TCK
TCKl
TMSsu
TMS
TDIh
TMSh
TDIsu
t
t
TDI
t
t
TDOd
TRST
TRST*
t
t
t t
t
TCK
TDO
Figure 44: Timing diagram JTAG Port
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
19 Electrical Characteristics
VDD range : 3.0 to 3.6 V
All inputs are LVTTL and 5 V compatible
Estimated power consumption is 0.75 W
19.1 Absolute Maximum Ratings, (Referenced to VSS)
Symbol Parameter MIN MAX Unit
VDD DC supply voltage -0.3 3.9 V
VIN LVTTL compatible input voltage -1.0 VDD+0.3 V
5V compatible input voltage -1.0 +6.5 V
IIN DC input current -10 +10
A
TSTG Storage temperature range - 40 +125
C
ESD Per MIL-STD-883 Test Method 3015, Notice 8, Spec 2001V, Latchup
Over/undershoot:
150 mA, 125
C;VDD Overstress: 2*VDD(7.2V)
Ratings in this table are those beyond which permanent device damage is likely to occur. These values should not be used as the
limits for normal device operation.
19.2 Recommended Operation Conditions
Symbol Parameter MIN MAX Unit
VDD DC supply voltage 3.0 3.6 V
Operating ambient temperature range
TAIndustrial -40 +85
C
TJJunction temperature
150
C
For normal device operation, adhere to the limits in this table. Sustained operation of a device at conditions exceeding these values,
even if they are within the absolute maximum rating limits, may result in permanent device damage or impaired device reliability.
Device functionality to stated DC and AC limits is not guaranteed if conditions exceed recommendedoperation conditions.
19.3 DC Characteristics
Symbol Parameter MIN TYP MAX Unit Condition
VDD supply voltage 3.0 3.3 3.6 V
VIL Low level input voltage VSS-0.5 0.8 V
VIH High level input voltage 2.0 5.5 V 5 V compatible
VTSwitching threshold 1.4 2.0 V
VT+ Schmitt trigger, positive-going threshold 1.7 2.0 V
VT- Schmitt trigger, negative-going threshold 0.8 1.0 V
Schmitt trigger, hysteresis 0.6 0.7 V
IIN Input current -10
1 10
A VIN = VDD or VSS
VOL Low level output voltage 0.2 0.4 V Industrial
VOH High level output voltage 2.4 VDD V
IOH 3-state output leakage current -10
1 10
A VOH = VSS or VDD
CIN Input capacitance 3.0 pF 5 V compatible
COUT Output capacitance 3.0 pF
Industrial junction temperature range: -40 to +125
C,
power supply.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
20 Thermal data
The thermal resistance
(junction - ambient) with a tolerance of
at still air and with fan cooling:
LFPM 0 200 400 600
29.5 25.8 24.3 23.0
C/W
The thermal resistance
(junction - case) with a tolerance of
:
C/W
Operating free air temp range:
TA = -40 to +85
C
UL flammability rating of the IC packaging material :
The package meets the UL flammability rating UL94-V0.
21 Application notes
21.1 Connecting the power and ground pads
Figure 45 shows an example of the connection of the power and ground pads. The two power supply nets are decoupledthrough an
external capacity C. We have taken a multi-layer PCB for our test board with one GND and one VDD layer. We have used a 47nF
ceramic SMD capacitor for each GND, VDD pair. Each device has been decoupled with three Tantal capacitors C of 10
F.
C
C
VDD
GND
V _PAD
DD
V _CORE
DD
GND_PAD
GND_CORE
SHAP4
Figure 45: Decoupling the power and ground pads
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
22 Addendum
22.1 Connecting the SHAP4-B to the standard Utopia interface level 1/2
The SHAP4-B has a special interface as it supports four Utopia level-1 interfaces at it’s input and at the output. The output of the
SHAP4-B is Utopia compatible with the
ATM TX
layer.
Normally the input would be Utopia
PHY TX
compatible. However this type of interface can not be used for four multiplexed
inputs: The four devices transmitting data to the SHAP4-B share a number of signals like Data, SOC, etc. Thus we must take care
that the following conditions are true:
Only one device may be using the bus at any time
The data path may not be blocked
The first condition can be satisfied if we enable one device at a time. For this we need an enable signal that is activated by the
SHAP4-B. However before we enable a device we must know if it has data to send. Thus we need a signal telling if a device has
data.
The second condition can only be satisfied if we perform flow control on cell basis. We can not have the input blockedin the middle
of a cell and then have all the other devices wait until the complete cell is transmitted. The clock is chosen to be an input signal for
the SHAP4-B as this allows the input to behave also as a Utopia
PHY TX
interface. If the SHAP4-B should produce an input clock
the system clock of the SHAP4-B can be used for this.
22.1.1 Single port PHY input
In case that only one ATM-Device with only one 8 Bit wide data stream should be connected towards SHAP4-B the solution is very
simple. See Figure 46: Single port
PHY TX
interface.
Figure 46: Single port PHY TX interface
The output clk
TxClk
of the ATM-Device is connected directly to the
RxClk
of the SHAP4-B.
ATM-Data
and the
Start of cell
signal can be forwarded to
RxData
respectively
RxSOC
inputs of the SHAP4-B.
RxClav0
of the SHAP4-B has to be connected to
VDD.
RxClav1
,
RxClav2
and
RxClav3
must be deasserted all the time and are connected to ground. The inverted
RxEnb0*
signal
is linked with
TxClav
of the ATM-Device.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
22.1.2 Utopia level-2 PHY input
If multiple input ports with a
PHY TX
interface is needed, external FIFOs must be added to the device:
SHAP4-B can be used to simulate a Multiple Physical device according to Utopial Level 2 Multiple Physical. This can be used to
shape up to four data streams independently(depends on configurationof IOCR-REG of the SHAP4-B) for a followingreal multiple
Physical Device. Figure 47 shows the connection of a ATM-Devicewith Multiple Physical output towards SHAP4-B to shape more
than one data stream.
Figure 47: Multiple port PHY TX interface, example 1
This application needs an additional synchronous FIFO (First In First Out) with 9-Bit wide In- and Output port, a programmable
device and some glue logic. The output ports (
TxData
and
SOC
) of the ATM-device should be connected to the data-in port of
the FIFO. The Data-Out port of the FIFO must be linked with the Input-ports of SHAP4-B (
RxData
,
RxSOC
).
TxClav
of the
ATM-Device is always high. The output clk of the ATM-DEVICE is connected to the synchronous FIFO and
RxClk
input port of
SHAP4-B. The inverted
TxEnb*
port of the ATM-Device should be connected to the programmable device (Address decode) and
to the
Enable
of the FIFO-Input. The
Enable
Signal of the FIFO-Output is connected with the result of a NAND-operation of up to
4
RxEnb*
-signals of SHAP4-B.
The depth of the necessary FIFO should be more than one cell.
The programmable device is used to decode the
TxAddr
signals (provided by the ATM-device) for the
RxClav
-Input ports of the
SHAP4-B.
The PLD device should convert the UTOPIA-Level2
TxAddr
in a SHAP4-B compatible input-select format. This can be done
according the table below:
TxEnb* TxAddr(1:0) RxClav(3:0)
1 00 0001
1 01 0010
1 10 0100
1 11 1000
0 XX 0000
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
22.1.3 Multi level-1 PHY inputs
Up to four independent ATM-Devices can be connected to SHAP4-B. This is very useful to merge data streams. For example four
34 Mbit-data streams can be merged to one 155 Mbit cell stream. All combinations with up to four ATM-Devices and up to four
Physical Devices are possible. Figure 48 shows the connection of four independent ATM-Devices with SHAP4-B.
Four synchronous FIFOs are necessary for this application. The active low Half Full - flag of each FIFO is connected to the
TxClav
input of one ATM-device (If the used FIFO provides no HALF-FULL flag,
TxClav
can be connected to the inverted active low
EMPTY-Flag). Each
TxData
and
TxSOC
output of the ATM-devices is connected to one 9 Bit wide FIFO-input. The
TxClk
of
each device is used as the input port clock of the dedicated FIFO. The
TxEnb*
-signal is used as ENB-signal for the referring FIFO.
The active low empty-flag of each FIFO should be connected to one
RxClav
-input port of the SHAP4-B. The
RxClk
(same as
system clock) of SHAP4-B should beconnected to the output clockof the FIFO. The Data-Out port of the FIFOs must be connected
to the
RxData
and
RxSOC
port of SHAP4-B.
In all applications the system clock of the SHAP4-B must be high enough for the device to receive the maximum data rate and store
the incoming cells in memory. The output rate is then determined by the Dual Leaky Bucket shaper function.
If the
RxEnb*
signal is deasserted and the user ignores this signal and keeps transmitting cells towards the SHAP4-B the cells are
still processed. That is the SHAP4-B will correctly receive the cells and store them in a queue. Cells are lost on two conditions:
If the input FIFO overflows.
If the queue to store the arriving cell is full
The four cells input FIFO gets full.
If the input FIFO gets full the SHAP4-B can be programmedto deasserted the
RxEnb*
signal. However this can happen only if the
device can not read the cells fast enough from the FIFO. This is normally a system design error as the system clock must be fast
enough for the SHAP4-B to read the cells from the FIFO and write the cells in the main memory.
The queue is full
This is an indication that the traffic is too bursty or the queue is too small. However in this case an error counter keeps track of the
number of lost cells.
The
RxEnb*
signal will be deasserted (set to t’1t’) under two conditions:
1. If the TxClav is deasserted (t’0t’).
2. If the input FIFO gets full.
The
RxEnb*
signal can be programmed for different modes:
Deasserted when the internal FIFO gets full
Deasserted when the TxClav signal is deasserted
Deasserted when either of these two conditions happens
Deasserted by LBC2 register bit 4 (SW control)
If the RxEnb* signal is deasserted then it can be made active in two modes:
Asserted immediately
Asserted at the end of a cell
This last mode can be used to prevent one input port from blocking another input port. It is guaranteed that the cell is transferred
towards the SHAP4-B before the flow is stopped.
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
Figure 48: Multiple port PHY TX interface, (The clock line is drawn dashed to make it easier to follow all the signals in the picture.)
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The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
23 Migration of the SHAP4 into the SHAP4-B
23.1 Major changes
The power supply of the Shap4-B is 3.3V instead of 5V
All pins are 5V tolerant.
The Shap4-B supports EDO DRAM as well as Fast Page DRAM
The Shap4-B supports asymmetric DRAMs (12 row/10 column)
The Shap4-B supports Microprocessor Interface of Motorola and Intel type
The Shap4-B is 100% pin compatible to the SHAP4. In case of using the pin configuration of the SHAP4, the Motorola
Interface of the SHAP4-B is used automatically.
There are no internal pull-ups/pull-downs in any port of the SHAP4-B.
The Shap4-B is 100% register compatible to the SHAP4. There are four new registers, which where unused in the SHAP4.
The default values of the four registers sets the Fast Page DRAM mode of the SHAP4. To get the previous functionality of
the SHAP4, the software has not to be changed except when reading a cell via cell interface see Section 23.3.
Additional feature to handle cells stored in the Utopia output port FIFO see section 2.2.6.
Bug fixing : When one of the 32 queues in the external dram gets full, there is a problem filling other queues with cells via
cell interface. The write pointer does not advance in this case. This bug is fixed in the Shap4-B.
The JTAG configuration is different to the SHAP4, the new BSDL-file will be available under request.
23.2 List of items
The following Chapters have been changed:
Section 13.1 Dynamic Memory
Section 14.1 Dedicated registers
Section 15.5 Microprocessor Interface
Section 15.9 System signals
Chapter 16 Pin Configuration
Chapter 17 Mechanical Information
Section 18.1 CPU interface
Section 18.2 DRAM Interface Timing
Chapter 19 Electrical Characteristics
Chapter 20 Thermal data
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Page 81 of 82
The ATM-SHAP4-B: Multi port & grouping Traffic Shaper
23.3 SW change when using the SHAP4-B
Because of the new mixed Motorola/Intel up interface the read access is no longer synchronized to the system clk of the SHAP4.
Therefore an additional write access has to be added after the 4. byte is read. This is only necessary for the SHAP4-B 3.3V. The
SHAP4 5V does not need this additional write access. Here a sample code :
void read_cell_interface (struct t_shap4_register *reg, unsigned char class,
unsigned char *cell) {
int i;
volatile unsigned char *base_address=reg->base_address;
reg->driver_class_reg&=~CLASS_MASK;
reg->driver_class_reg|=(class&CLASS_MASK);
write_reg(base_address,CLAR_REG_ADDR, reg->driver_class_reg); /* program class */
write_reg(base_address,TRCR_REG_ADDR, TRF_CELL_INTERFACE); /* dma_req -> ’0’ */
while (!(read_reg(base_address,TRCR_REG_ADDR)&TRF_READY)); /* wait transfer ready ’1’*/
for (i=0;i<14;i++) {
cell[0+i*4]=read_reg(base_address,APDR_REG_ADDR);
cell[1+i*4]=read_reg(base_address,APDR_REG_ADDR+1);
cell[2+i*4]=read_reg(base_address,APDR_REG_ADDR+2);
cell[3+i*4]=read_reg(base_address,APDR_REG_ADDR+3);
#ifdef SHAP4-B
/* additional write access to trigger next read */
write_reg(base_address,APDR_REG_ADDR+3, cell[3+i*4]);
#endif
while (!(read_reg(base_address,TRCR_REG_ADDR)&TRF_READY)); /* wait transfer ready */
}
while (!(read_reg(base_address,TRCR_REG_ADDR)&TRF_CELL_DONE)); /* wait cell interfacs ready */
}
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November 9, 2000
