MAX3541ELM+T - Maxim Integrated

General Description

The MAX3541 complete single-conversion television

tuner is designed for use in analog/digital terrestrial appli-

cations and digital set-top boxes. This television tuner

draws only 760mW of power from a +3.3V supply voltage.

The MAX3541 is designed to convert PAL or DVB-T sig-

nals in the 47MHz to 68MHz, 174MHz to 230MHz, and

470MHz to 862MHz bands to an intermediate frequency

(IF) of 36MHz.

The MAX3541 includes a variable-gain low-noise amplifi-

er (LNA), multiband tracking filters, a harmonic-rejection

mixer, a low-noise IF amplifier, an IF power detector, and

a variable-gain IF amplifier. The MAX3541 also includes

fully monolithic VCOs and tank circuits, as well as a

complete frequency synthesizer. This highly integrated

design allows for low-power tuner-on-board applications

without the cost and power dissipation issues of dual-

conversion tuner solutions.

The MAX3541 is specified for operation in the -40°C to

+85°C temperature range and is available in a leadless

48-pin flip-chip (fcLGA) package.

Applications

Televisions

Analog/Digital Terrestrial Receivers

Digital Set-Top Boxes

Features

oLow Power Consumption: 760mW (typ) from a

+3.3V Supply Voltage

oIntegrated Tracking Filters

oLow Noise Figure: 4.9dB (typ)

oSmall 7mm x 7mm fcLGA Leadless Package

oIF Overload Detector Controls RF Variable-Gain

Amplifier

o2-Wire, I2C-Compatible Serial Control Interface

MAX3541

Complete Single-Conversion

Television Tuner

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-1029; Rev 3; 2/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX3541ELM+ -40°C to +85°C 48 LGA-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed paddle.

Pin Configuration/Functional Diagram

MAX3541

36 IFOUT1-1

SCL

35 IFOUT1+2SDA

34 IFOVLD

3VCC

33 VCC

4UHF_IN

32 VCC

VREF

5VHF_IN

31 GND

6RFGND2

30 IFIN+

7LEXT

29 IFIN-

8RFGND3

28 VCC

9RFAGC

27 GND

10VCC

26 IFAGC11GND

25 IFOUT2+

12GND

ADDR2GND

ADDR1GND

XTALPGND

XTALNGND

VCC

GND

CPGND

MUXGND

VCC

GND

VTUNEGND

GND_TUNEGND

LDOVCC

VCC

IFOUT2-

SERIAL

INTERFACE

÷ R PD CP

÷ N

VCO

DIVIDER

MAX3541

Complete Single-Conversion

Television Tuner

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA= -40°C to +85°C, no RF signals at RF inputs, default register settings, VRFAGC = VIFAGC

= +3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VCC to GND..............................................................-0.3V, +3.6V

RFIN, IFIN_ IFOUT1_, IFOUT2_, IFAGC, RFAGC,

VTUNE, LDO, MUX, CP,

XTAL to GND....................................-0.3V to (VCC + 0.3V)

SDA, SCL, ADDR2, ADDR1 to GND......................-0.3V to +3.6V

IFOUT__ Short-Circuit Duration .....................................Indefinite

RF Input Power ...............................................................+10dBm

Continuous Power Dissipation (TA= +70°C)

48-Pin fcLGA (derate 25mW/°C above +70°C) ..............1.4W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +165°C

Lead Temperature (soldering, 10s) .................................+250°C

Soldering Temperature (reflow) .......................................+240°C

CAUTION! ESD SENSITIVE DEVICE

PARAMETER CONDITIONS MIN TYP MAX UNITS

SUPPLY VOLTAGE AND CURRENT

Supply Voltage +3.1 +3.5 V

Receive mode 230 275

Supply Current Shutdown mode 5 mA

RF and IF AG C Inp ut Bi as C ur r ent At +0.5V and +3V -50 +50 μA

Minimum attenuation +3

RF and IF AGC Control Voltage (Note 1) Maximum attenuation +0.5 V

Digital Input Logic-Level Low 0.3 x VCC V

Digital Input Logic-Level High 0.7 x VCC V

SERIAL INTERFACE

Input Logic-Level Low 0.3 x VCC V

Input Logic-Level High 0.7 x VCC V

Input Hysteresis 0.05 x VCC V

SDA, SCL Input Current -10 +10 μA

Output Logic-Level Low 3mA sink current 0.4 V

Output Logic-Level High VCC - 0.5 V

MAX3541

Complete Single-Conversion

Television Tuner

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA= -40°C to +85°C, 75Ωsystem impedance, default register settings, VRFAGC = VIFAGC =

+3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA= +25°C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

RF INPUT TO IFOUT1 OUTPUT

47 68

174 230

Operating Frequency Range

(see Table 7)

Gain specification met across these

frequency bands

470 862

MHz

Analog channel PIX carrier 38.9

Output Frequency Digital channel center frequency 36 MHz

Maximum gain

(VRAVGC = 3V) 33 41 49

Voltage Gain

Source impedance

= 75Ω, load

impedance = 200ΩMinimum gain

(VRAVGC = 0.5V) -10

Input Return Loss Selected channel 10 dB

Noise Figure Maximum gain (VRFAGC = 3V) 4.9 dB

Maximum gain (VRFAGC = 3V) 20

Input IP2 (In-Band and Out-of-Band Tones) At 12.5dB of gain 30 dBm

Maximum gain (VRFAGC = 3V) -10

Input IP3 (In-Band and Out-of-Band Tones) At 12.5dB of gain 10 dBm

Maximum gain (VRFAGC = 3V) -38

Input P1dB At 12.5dB of gain -5 dBm

Beats Within Output 0dBmV PIX carrier level -40 dBc

VHF input, 140MHz to 500MHz -60

VHF input, 500MHz to 1400MHz -50

Beats, Converted to Output

UHF input, 950MHz to 1400MHz -60

dBc

Gain Flatness 47MHz to 54MHz 2.5 dBP-P

Isolation 5MHz to 50MHz, RF input to IF output,

relative to desired channel 60 dBc

Port-to-Port Isolation Isolation between RF input ports at 215MHz 27 dB

Image Rejection Measured at 77.8MHz above desired

channel’s center frequency 57 70 dBc

5Hz to 65MHz -40

Spurious Leakage at RF Input 65MHz to 878MHz -40 dBmV

1kHz -80

10kHz offset -85

100kHz offset (1.5kHz loop bandwidth) -105

Phase Noise (Single-Sideband)

1MHz offset (1.5kHz loop bandwidth) -125

dBc/Hz

Output Return Loss Balanced 50Ω load 20 dB

IF VARIABLE-GAIN AMPLIFIER

Input Impedance Balanced 2000 Ω

Output Impedance Balanced (Note 1) 300 Ω

MAX3541

Complete Single-Conversion

Television Tuner

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA= -40°C to +85°C, 75Ωsystem impedance, default register settings, VRFAGC = VIFAGC =

+3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA= +25°C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Maximum gain setting

(VIFAGC = 3V) 54 59 63

Passband Voltage Gain

S our ce l oad =

1.1kΩ,

output load = 1kΩMinimum gain setting

(VIFAGC = 0.5V) 21

Passband Gain Flatness 32MHz to 40MHz (Note 1) 1.2 dB

Output Voltage VIFAGC = 3V (Note 1) 2.5 VP-P

AGC Gain Slope VIFAGC = 3V to 0.5V (Note 1) 27 dB/V

Equivalent Input Voltage Noise Density At 36MHz, maximum gain (VIFAGC = 3V)

(Note 1) 7.3 nV/√Hz

Noise Figure Change vs. Attenuation < 0.35 dB/dB

IM3 VOUT = 1VP-P, 40dB < gain < 60dB (Note 1) -56 dBc

IF OVERLOAD DETECTOR (See the IF Overload Detector Section)

Output Overload Attack Point 0.7 VP-P

Attack Point Accuracy OD REG = 3 ±1 dB

Detector Output Voltage Range Negative polarity, overload reduces VDET

(open collector, 0.3mA sink) 0.5 3.0 V

Detector Gain 70 V/V

FREQUENCY SYNTHESIZER

REFERENCE OSCILLATOR

Frequency 8MHz

DIVIDERS

RF N-Divider Ratio 256 32,767

RF R-Divider Ratio 16 127

LO PHASE DETECTOR AND CHARGE PUMP

Comparison Frequency 63 250 kHz

CP = 00 0.5

CP = 01 1

CP = 10 1.5

Charge-Pump Current

CP = 11 2

Charge-Pump Three-State Current ±5 nA

Charge-Pump Compliance Range 0.4 VCC -

0.4 V

Charge-Pump Current Matching 5%

LOCAL OSCILLATOR

VCO Tuning Range Tank frequency 2200 4400 MHz

VCO Tuning Gain Tank oscillator gain 500 MHz/V

2-WIRE SERIAL INTERFACE

Clock Frequency 400 kHz

Note 1: Guaranteed by design and characterization.

MAX3541

Complete Single-Conversion

Television Tuner

_______________________________________________________________________________________ 5

SUPPLY CURRENT vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

MAX3541 toc01

3.1 3.2 3.3 3.4 3.5

216

220

224

228

232

-40°C

+25°C

+85°C

VHF VOLTAGE GAIN vs. RFAGC VOLTAGE

RFAGC VOLTAGE (V)

VHF VOLTAGE GAIN (dB)

MAX3541 toc02

0.5 1.0 1.5 2.0 2.5 3.0

-20

fRF = 64.5MHz

+85°C

-40°C

+25°C

UHF VOLTAGE GAIN vs. RFAGC VOLTAGE

RFAGC VOLTAGE (V)

UHF VOLTAGE GAIN (dB)

MAX3541 toc03

0.5 1.0 1.5 2.0 2.5 3.0

-20

fRF = 801MHz

+85°C

+25°C

-40°C

VHF VOLTAGE GAIN vs. FREQUENCY

FREQUENCY (MHz)

VHF VOLTAGE GAIN (dB)

MAX3541 toc04

45 50 55 60 65 70

+25°C

+85°C

-40°C

VHF VOLTAGE GAIN vs. FREQUENCY

FREQUENCY (MHz)

VHF VOLTAGE GAIN (dB)

MAX3541 toc05

170 180 190 200 210 220 230

+85°C

-40°C

+25°C

UHF VOLTAGE GAIN vs. FREQUENCY

FREQUENCY (MHz)

UHF VOLTAGE GAIN (dB)

MAX3541 toc06

470 570 670 770 870

+25°C

+85°C

-40°C

VHF NOISE FIGURE vs. FREQUENCY

FREQUENCY (MHz)

NOISE FIGURE (dB)

MAX3541 toc08

175 185 195 205 215 225

+25°C

-40°C

+85°C

+55°C

0°C

Typical Operating Characteristics

(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA= +25°C, unless otherwise noted.)

VHF NOISE FIGURE vs. FREQUENCY

FREQUENCY (MHz)

NOISE FIGURE (dB)

MAX3541 toc07

48 51 54 57 60 63

+25°C

-40°C

+85°C

+55°C

0°C

MAX3541

Complete Single-Conversion

Television Tuner

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA= +25°C, unless otherwise noted.)

UHF NOISE FIGURE vs. FREQUENCY

FREQUENCY (MHz)

NOISE FIGURE (dB)

MAX3541 toc09

470 560 650 740 830

+55°C

+85°C

+25°C0°C-40°C

VHF NOISE FIGURE vs. RFAGC VOLTAGE

RFAGC VOLTAGE (V)

NOISE FIGURE (dB)

MAX3541 toc10

1.8 2.0 2.2 2.4 2.6 2.8 3.0

fRF = 224.25MHz

+55°C

+85°C

+25°C

0°C

-40°C

UHF NOISE FIGURE vs. RFAGC VOLTAGE

RFAGC VOLTAGE (V)

NOISE FIGURE (dB)

MAX3541 toc11

1.8 2.0 2.2 2.4 2.6 2.8 3.0

fRF = 631.25MHz

+55°C+85°C

+25°C

0°C

-40°C

VHF IMAGE REJECTION vs. FREQUENCY

FREQUENCY (MHz)

VHF IMAGE REJECTION (dB)

MAX3541 toc12

47 51 55 59 63

-40°C

0°C

+85°C

+55°C

+25°C

VHF IMAGE REJECTION vs. FREQUENCY

FREQUENCY (MHz)

VHF IMAGE REJECTION (dB)

MAX3541 toc13

175 185 195 205 215 225

+25°C

-40°C

+85°C

+55°C

0°C

UHF IMAGE REJECTION vs. FREQUENCY

FREQUENCY (MHz)

UHF IMAGE REJECTION (dB)

MAX3541 to14

470 570 670 770 870

+25°C

-40°C

+85°C

+55°C

0°C

MAX3541

Complete Single-Conversion

Television Tuner

_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)

(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA= +25°C, unless otherwise noted.)

VHF PHASE NOISE AT 10kHz OFFSET

vs. CHANNEL FREQUENCY

CHANNEL FREQUENCY (MHz)

VHF PHASE NOISE (dBc/Hz)

MAX3541 toc15

45 50 55 60 65 70

-105

-103

-101

-99

-97

-95

VHF PHASE NOISE AT 10kHz OFFSET

vs. CHANNEL FREQUENCY

CHANNEL FREQUENCY (MHz)

VHF PHASE NOISE (dBc/Hz)

MAX3541 toc16

170 180 190 200 210 220 230 240

-100

-98

-96

-94

-92

-90

UHF PHASE NOISE AT 10kHz OFFSET

vs. CHANNEL FREQUENCY

CHANNEL FREQUENCY (MHz)

UHF PHASE NOISE (dBc/Hz)

MAX3541 toc17

400 500 600 700 800 900

-95

-92

-89

-86

-83

-80

VHF PHASE NOISE vs. OFFSET FREQUENCY

OFFSET FREQUENCY (kHz)

VHF PHASE NOISE (dBc/Hz)

MAX3541 toc18

-140

-120

-100

-80

-60

0.1 1 10 100 1000

fRF = 64.5MHz

UHF PHASE NOISE vs. OFFSET FREQUENCY

OFFSET FREQUENCY (kHz)

UHF PHASE NOISE (dBc/Hz)

MAX3541 toc19

-130

-120

-110

-100

-90

-80

-70

-60

0.1 1 10 100 1000

fRF = 801MHz

IFOUT1 NORMALIZED FREQUENCY RESPONSE

(5MHz to 200MHz)

FREQUENCY (MHz)

IFOUT1 POWER (dBm)

MAX3541 toc20

-20

-15

-10

-5

1 10 100 1000

MAX3541

Complete Single-Conversion

Television Tuner

8 _______________________________________________________________________________________

IFVGA VOLTAGE GAIN vs. IFAGC VOLTAGE

IFAGC VOLTAGE (V)

IFVGA VOLTAGE GAIN (dB)

MAX3541 toc21

0.5 1.0 1.5 2.0 2.5 3.0

+25°C

-40°C

+85°C

IFVGA IM3 vs. IFAGC VOLTAGE

IFAGC VOLTAGE (V)

IFVGA IM3 (dBc)

MAX3541 toc22

INPUT POWER (dBm)

-80

-60

-40

-20

0.5 1.0 1.5 2.0 2.5 3.0

-60

-50

-40

-30

-20

VOUT = 1.5 VP-P

IM3

Pin Description

Typical Operating Characteristics (continued)

(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA= +25°C, unless otherwise noted.)

PIN NAME DESCRIPTION

1 SCL 2-Wire Serial-Clock Interface. Requires a pullup resistor to V

2 SDA 2-Wire Serial-Data Interface. Requires a pullup resistor to V

3, 10, 23, 28,

32, 33, 37,

41, 44

Power Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor.

4 UHF_IN UHF RF Input. Requires a DC-blocking capacitor.

5 VHF_IN VHF RF Input. Requires a DC-blocking capacitor.

6 RFGND2 RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2

and RFGND3 together.

7 LEXT RF VGA Supply Voltage. Connect through a 270nH pullup inductor to V

8 RFGND3 RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2

and RFGND3 together.

9 RFAGC RF V G A G ai n C ontr ol V ol tag e. Accep ts a D C vol tag e fr om 0.5V ( m i ni m um g ai n) to 3V ( m axi m um g ai n) .

11–22, 27, 31 GND Ground. Connect to the PCB’s ground plane.

24 IFOUT2- Inver ti ng IF V G A Outp ut. C onnect to the i np ut of an anti - al i asi ng fi l ter . Req ui r es a D C - b l ocki ng cap aci tor .

25 IFOUT2+ N oni nver ti ng IF V GA O utp ut. C onnect to the i np ut of an anti - al i asi ng fi l ter . Req ui r es a D C - b l ocki ng cap aci tor .

26 IFAGC IF VGA Gain Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain).

29 IFIN- Inverting IF VGA Input. Connect to the output of an IF-SAW filter.

30 IFIN+ Noninverting IF VGA Input. Connect to the output of an IF-SAW filter.

34 IFOVLD IF Overload Detector Open-Collector Output. Requires a 10kΩ pullup resistor to V

35 IFOUT1+ Noninverting IF LNA Output. Requires a DC-blocking capacitor.

36 IFOUT1- Inverting IF LNA Output. Requires a DC-blocking capacitor.

38 LDO VCO LDO Bypass. Bypass to ground with a 0.47μF capacitor.

MAX3541

Complete Single-Conversion

Television Tuner

_______________________________________________________________________________________ 9

PIN NAME DESCRIPTION

39 GND_TUNE VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GNDs must

be connected to this pin (see the Typical Application Circuit).

40 VTUNE VCO Tuning Input. Connect to the PLL loop filter output.

42 MUX Test Output. Leave this pin unconnected during normal operation.

43 CP Charge-Pump Output. Connect to PLL loop filter input.

45 XTALN Crystal Oscillator Feedback. See the Typical Application Circuit.

46 XTALP Crystal Oscillator Feedback. See the Typical Application Circuit.

47 ADDR1 2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the

C-compatible serial interface.

48 ADDR2 2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the

C-compatible serial interface.

— EP Exposed Pad. Solder evenly to the PCB ground plane for proper operation.

Pin Description (continued)

MAX3541

Detailed Description

The MAX3541 includes 11 programmable registers and

2 read-only registers. The 11 programmable registers

include two N-divider registers, an R-divider register, a

VCO register, an IFOVLD/Charge Pump/Filter Select

Tracking Filter Control registers. These 11 programma-

ble registers are also readable. The read-only registers

include a status register and a ROM table data register.

Recommended default bit settings are provided for

user convenience only and are not guaranteed. The

user must write all registers after power-up and no ear-

lier than 100μs after power-up.

Complete Single-Conversion

Television Tuner

10 ______________________________________________________________________________________

MSB LSB

DATA BYTE

NAME

READ/

WRITE

ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

N-DIV High Both 0x00 0 N14 N13 N12 N11 N10 N9 N8

N-DIV Low Both 0x01 N7 N6 N5 N4 N3 N2 N1 N0

R-DIV Both 0x02 0 R6 R5 R4 R3 R2 R1 R0

VCO Both 0x03 VCO4 VCO3 VCO2 VCO1 VCO0 LD VDIV1 VDIV0

IFO V LD ,

C har g e P um p ,

and Fi l ter S el ect

Both 0x04 0 IFOVLD2 IFOVLD1 IFOVLD0 CP1 CP0 TF 0

Control Both 0x05 0 0 0 0 SHDN

_RF

SHDN

_IFVGA INPT1 INPT0

Shutdown Both 0x06 SHDN

_MIX1

SHDN

_MIX0

SHDN

_IF

SHDN

_OD

SHDN

_SYN 000

Tr acki ng Fi l ter

S er i es C ap aci tor Both 0x07 TFS7 TFS6 TFS5 TFS4 TFS3 TFS2 TFS1 TFS0

Tracking Fi l ter

P ar al lel Cap acitor Both 0x08 FLD 0 TFP5 TFP4 TFP3 TFP2 TFP1 TFP0

Tracking Filter

ROM Address Both 0x09 0 0 0 0 TFA3 TFA2 TFA1 TFA0

Reserved Both 0x0A X X X X X X X X

ROM Table

Data Readback Read 0x0B TFR7 TFR6 TFR5 TFR4 TFR3 TFR2 TFR1 TFR0

Status Read 0x0C POR LD2 LD1 LD0 X X X X

Table 1. Register Configuration

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

RESERVED 7 0 Must be set to 0.

N[14:8] 6-0 0000001 Sets the most significant bits of the PLL integer divider (N). Default

integer divider value is N = 4688. N can range from 256 to 32,767.

Table 2. N-DIV High Register (Address: 0000b)

MAX3541

Complete Single-Conversion

Television Tuner

______________________________________________________________________________________ 11

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

N[7:0] 7-0 10101011 Sets the least significant bits of the PLL integer divider (N). Default

integer divider value is N = 4688. N can range from 256 to 32,767.

Table 3. N-DIV Low Register (Address: 0001b)

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

RESERVED 7 0 Must be set to 0.

R[6:0] 6-0 0010000 Sets the PLL reference divider (R). Default reference divider value is

R = 64. R can range from 16 to 127.

Table 4. R-DIV Register (Address: 0010b)

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

VCO[4:3] 7-6 10

VCO select. Selects one of three possible VCOs.

00 = VCOs shut down

01 = Selects VCO1

10 = Selects VCO2

11 = Selects VCO3

VCO[2:0] 5-3 111

V C O sub - b and sel ect. S el ects one of ei g ht p ossi b l e V C O sub - b and s.

000 = Selects SB0

001 = Selects SB1

010 = Selects SB2

011 = Selects SB3

100 = Selects SB4

101 = Selects SB5

110 = Selects SB6

111 = Selects SB7

LD 2 1

Lock detect enable.

0 = Disabled

1 = Enabled

VDIV[1:0] 1-0 10

VCO divider ratio select.

00 = S ets V C O d i vi d er to 4

01 = S ets V CO d i vi d er to 8

10 = Sets VCO divider to 16

11 = Sets VCO divider to 32

Table 5. VCO Register (Address: 0011b)

MAX3541

Complete Single-Conversion

Television Tuner

12 ______________________________________________________________________________________

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

RESERVED 7 0 Must be set to 0.

IFOVLD[2:0] 6-4 000 Write content of ROM register OD[2:0] to this location.

CP[1:0] 3-2 00

Selects the typical charge-pump current.

00 = 0.5mA

01 = 1mA

10 = 1.5mA

11 = 2mA

TF 1 0

Selects the tracking filter band of operation.

0 = VHF

1 = UHF

RESERVED 0 0 Must be set to 0.

Table 6. IFOVLD, Charge Pump, and Filter Select Register (Address: 0100b)

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

RESERVED 7-4 0000 Must be set to 0000.

SHDN_RF 3 0

RF shutdown.

0 = RF circuitry enabled

1 = RF circuitry disabled

S H DN _IFV GA 2 0

IF VGA shutdown.

0 = IF VGA enabled

1 = IF VGA disabled

INPT[1:0] 1-0 01

Selects the RF input.

00 = Selects VHF_IN, LPF enabled

01 = Selects VHF_IN, LPF disabled

10 = Selects UHF_IN

11 = Factory use only

Table 7. Control Register (Address: 0101b)

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

SHDN_MIX 7-6 00

Mixer shutdown.

00 = Mixer enabled

01,10 = Factory use only

11 = Mixer disabled

SHDN_IF 5 0

IF shutdown.

0 = IF section enabled

1 = IF section disabled

SHDN_OD 4 0

IFOVLD shutdown.

0 = Power detector enabled

1 = Power detector disabled

SHDN_SYN 3 0

Frequency synthesizer shutdown.

0 = Synthesizer enabled

1 = Synthesizer disabled

RESERVED 2-0 000 Must be set to 000.

Table 8. Shutdown Register (Address: 0110b)

MAX3541

Complete Single-Conversion

Television Tuner

______________________________________________________________________________________ 13

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

TFS[7:0] 7-0 00001111* Programs series capacitor values in the tracking filter.

Table 9. Tracking Filter Series Capacitor Register (Address: 0111b)

*See the

RF Tracking Filter

section.

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

TFR[7:0] 7-0 00000000* Tracking filter data bits read from the device’s ROM table.

Table 13. ROM Table Data Readback Register (Address: 1011b)

*See the

RF Tracking Filter

section.

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

RESERVED 7-0 N/A Reserved. Do not program these bits during normal operation.

Table 12. Reserved Register (Address: 1010b)

*See the

RF Tracking Filter

section.

*See the

RF Tracking Filter

section.

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

FLD 7 0 Filter load bit. A 0 to 1 transition of this bit forces the loading of the

ROM Table Data Readback register.

RESERVED 6 0 Must be set to 0.

TFP[5:0] 5-0 001001* Programs parallel capacitor values in the tracking filter.

Table 10. Tracking Filter Parallel Capacitor Register (Address: 1000b)

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

RESERVED 7-4 0000 Must be set to 0000.

TFA[3:0] 3-0 0000* Address bits of the ROM register to be read.

Table 11. Tracking Filter ROM Address Register (Address: 1001b)

BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED

DEFAULT FUNCTION

POR 7 N/A

Power-on reset.

0 = Status register has been read

1 = Power reset since last status register read

LD[2:0] 6-4 N/A

VCO tuning voltage indicators.

000 = PLL not in lock, tune to the next lowest sub-band

001–110 = PLL in lock

111 = PLL not in lock, tune to the next higher sub-band

RESERVED 3-0 N/A Reserved.

Table 14. Status Register (Address: 1100b)

MAX3541

2-Wire Serial Interface

The MAX3541 use a 2-wire I2C-compatible serial inter-

face consisting of a serial-data line (SDA) and a serial-

clock line (SCL). SDA and SCL facilitate bidirectional

communication between the MAX3541 and the master at

clock frequencies up to 400kHz. The master initiates a

data transfer on the bus and generates the SCL signal to

permit data transfer. The MAX3541 behaves as a slave

device that transfers and receives data to and from the

master. Pull SDA and SCL high with external pullup

resistors (1kΩor greater) for proper bus operation.

One bit is transferred during each SCL clock cycle. A

minimum of nine clock cycles is required to transfer a

byte in or out of the MAX3541 (8 data bits and an

ACK/NACK). The data on SDA must remain stable during

the high period of the SCL clock pulse. Changes in SDA

while SCL is high and stable are considered control sig-

nals (see the

START and STOP Conditions

section). Both

SDA and SCL remain high when the bus is not busy.

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), which is a high-to-low transition on SDA while

SCL is high. The master terminates a transmission with

a STOP condition (P), which is a low-to-high transition

on SDA while SCL is high.

Acknowledge and Not-Acknowledge Conditions

Data transfers are framed with an acknowledge bit

(ACK) or a not-acknowledge bit (NACK). Both the mas-

ter and the MAX3541 (slave) generate acknowledge

bits. To generate an acknowledge, the receiving device

must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and

keep it low during the high period of the clock pulse.

To generate a not-acknowledge condition, the receiver

allows SDA to be pulled high before the rising edge of

the acknowledge-related clock pulse, and leaves SDA

high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the bus master must reattempt

communication at a later time.

Slave Address

The MAX3541 has a 7-bit slave address that must be

sent to the device following a START condition to initi-

ate communication. The slave address is determined

by the state of the ADDR2 and ADDR1 pins and is

equal to 11000[ADDR2][ADDR1]. The eighth bit (R/W)

following the 7-bit address determines whether a read

or write operation occurs. Table 15 shows the possible

address configurations.

The MAX3541 continuously awaits a START condition

followed by its slave address. When the device recog-

nizes its slave address, it acknowledges by pulling the

SDA line low for one clock period; it is ready to accept

or send data depending on the R/Wbit (Figure 1).

Complete Single-Conversion

Television Tuner

14 ______________________________________________________________________________________

SCL

SDA

123456789

S 1 1 0 0 0 ADDR2 ADDR1 R/W ACK

SLAVE ADDRESS

NOTE: TIMING PARAMETERS CONFORM WITH I2C BUS SPECIFICATIONS.

Figure 1. MAX3541 Slave Address Byte

ADDR2 ADDR1 WRITE ADDRESS READ ADDRESS

0 0 0xC0 0xC1

0 1 0xC2 0xC3

1 0 0xC4 0xC5

1 1 0xC6 0xC7

Table 15. MAX3541 Address Configurations

Write Cycle

When addressed with a write command, the MAX3541

allows the master to write to a single register or to multi-

ple successive registers.

A write cycle begins with the bus master issuing a

START condition followed by the seven slave address

bits and a write bit (R/W= 0). The MAX3541 issues an

ACK if the slave address byte is successfully received.

The bus master must then send to the slave the

address of the first register it wishes to write to. If the

slave acknowledges the address, the master can then

write one byte to the register at the specified address.

Data is written beginning with the most significant bit.

The MAX3541 again issues an ACK if the data is suc-

cessfully written to the register. The master can contin-

ue to write data to the successive internal registers with

the MAX3541 acknowledging each successful transfer,

or it can terminate transmission by issuing a STOP con-

dition. The write cycle does not terminate until the mas-

ter issues a STOP condition.

Figure 2 illustrates an example in which registers 0

through 2 are written with 0x0E, 0xD8, and 0xE1,

respectively.

Read Cycle

A read cycle begins with the bus master issuing a

START condition followed by the seven slave address

bits and a write bit (R/W= 0). The MAX3541 issues an

ACK if the slave address byte is successfully

received. The master then sends the 8-bit address of

the first register that it wishes to read. The MAX3541

then issues another ACK. Next, the master must issue

a START condition followed by the 7 slave address

bits and a read bit (R/W= 1). The MAX3541 issues an

ACK if it successfully recognizes its address and

begins sending data from the specified register

address starting with the most significant bit (MSB).

Data is clocked out of the MAX3541 on the rising

edge of SCL. On the 9th rising edge of SCL, the mas-

ter can issue an ACK and continue reading succes-

sive registers or it can issue a NACK followed by a

STOP condition to terminate transmission. The read

cycle does not terminate until the master issues a

STOP condition. Figure 3 illustrates an example in

which registers 0 and 1 are read back.

MAX3541

Complete Single-Conversion

Television Tuner

______________________________________________________________________________________ 15

START

WRITE DEVICE

ADDRESS R/W

11000[ADDR2][ADDR1] 0 —————

WRITE REGISTER

ADDRESS

0x00

ACK ACK ACK ACK ACK

WRITE DATA TO

0x0E

WRITE DATA TO

0xD8

WRITE DATA TO

0xE1

STOP

Figure 2. Example: Write Registers 0 Through 2 with 0x0E, 0xD8, and 0xE1, Respectively

START

WRITE DEVICE

ADDRESS R/W

110000[ADDR2][ADDR1]

WRITE DEVICE

ADDRESS

110000[ADDR2][ADDR1]0 ——

WRITE 1ST REGISTER

ADDRESS

0x00

ACK NACK

—

ACK READ DATA

REG 0

D7–D0

STOP

R/W

1—

ACK READ DATA

REG 1

D7–D0

—

ACK

START

Figure 3. Example: Read Data from Registers 0 and 1

MAX3541

Application Information

RF Inputs

The MAX3541 features separate UHF and VHF inputs

that are matched to 75Ω. Both inputs require a DC-

blocking capacitor. The active inputs are selected by

the input registers. In addition, the input registers

enable or disable the lowpass filter, which can be used

when the VHF input is selected. For the 47MHz to

68MHz, select the VHF_IN with the LPF filter enabled

(INPT = 00). For 174MHz to 230MHz, select VHF_IN

with LPF disabled (INPT = 01). For 470MHz to 862MHz,

select UHF_IN (INPT = 10).

RF Gain Control

The gain of the RF low-noise amplifier can be adjusted

over a typical range of 45dB with the RFAGC pin. The

RFAGC input accepts a DC voltage from 0.5V to 3V,

with 3V providing maximum gain. This pin can be con-

trolled with the IF power-detector output to form a

closed RF gain-control loop. See the

Closed-Loop RF

Gain Control

section for more information.

RF Tracking Filter

The MAX3541 includes a programmable tracking filter

for each band of operation to optimize rejection of

out-of-band interference while minimizing insertion

loss for the desired received signal. The center fre-

quency of each tracking filter is selected by a

switched-capacitor array that is programmed by the

TFS[7:0] bits in the Tracking Filter Series Capacitor

Parallel Cap register.

Optimal tracking filter settings for each channel varies

from part to part due to process variations. To accom-

modate part-to-part variations, each part is factory cal-

ibrated by Maxim. During calibration, the y-intercept

and slope for the series and parallel tracking capacitor

arrays is calculated and written into an internal ROM

table. The user must read the ROM table upon power-

up and store the data in local memory (8 bytes total) to

calculate the optimal TFS[7:0] and TFP[5:0] settings

for each channel. Table 16 shows the address and

bits for each ROM table entry. See the

Interpolating

Tracking Filter Coefficients

section for more informa-

tion on how to calculate the required values.

Reading the ROM Table

Each ROM table entry must be read using a two-step

process. First, the address of the ROM bits to be read

must be programmed into the TFA[3:0] bits in the

Tracking Filter ROM Address register (Table 11).

Complete Single-Conversion

Television Tuner

16 ______________________________________________________________________________________

MSB LSB

DATA BYTE

DESCRIPTION ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

Reserved 0x0 OD2 OD1 OD0 X X X X X

VHF Series

Y-Intercept 0x1 VS0[7] VS0[6] VS0[5] VS0[4] VS0[3] VS0[2] VS0[1] VS0[0]

VHF Series

Slope 0x2 VS1[7] VS1[6] VS1[5] VS1[4] VS1[3] VS1[2] VS1[1] VS1[0]

VHF Parallel

Y-Intercept 0x3 VP0[7] VP0[6] VP0[5] VP0[4] VP0[3] VP0[2] VP0[1] VP0[0]

VHF Parallel

Slope 0x4 VP1[7] VP1[6] VP1[5] VP1[4] VP1[3] VP1[2] VP1[1] VP1[0]

UHF Series

Y-Intercept 0x5 US0[7] US0[6] US0[5] US0[4] US0[3] US0[2] US0[1] US0[0]

UHF Series

Slope 0x6 US1[7] US1[6] US1[5] US1[4] US1[3] US1[2] US1[1] US1[0]

UHF Parallel

Y-Intercept 0x7 UP0[7] UP0[6] UP0[5] UP0[4] UP0[3] UP0[2] UP0[1] UP0[0]

UHF Parallel

Slope 0x8 UP1[7] UP1[6] UP1[5] UP1[4] UP1[3] UP1[2] UP1[1] UP1[0]

Table 16. ROM Table

Once the address has been programmed, the data

stored in that address is transferred to the TFR[7:0] bits

in the ROM Table Data Readback register (Table 13).

The ROM data at the specified address can then be

read from the TFR[7:0] bits and stored in the micro-

processor’s local memory.

Interpolating Tracking Filter Coefficients

The TFS[7:0] and TFP[5:0] bits must be reprogrammed

for each channel frequency to optimize performance.

The optimal settings for each channel can be calculat-

ed from the ROM table data using the equations below:

VHF filter:

UHF filter:

where:

fRF = operating frequency in megahertz.

TFS = decimal value of the optimal TFS[7:0] setting

(Table 9) for the given operating frequency.

TFP = decimal value of the optimal TFP[5:0] setting

(Table 10) for the given operating frequency.

VS0, VS1, VP0, VP1, US0, US1, UP0, and UP1 = the

decimal values of the ROM table coefficients (Table

16).

IF Overload Detector

The MAX3541 includes a broadband IF overload detec-

tor, which provides an indication of the total power pre-

sent at the RF input. The overload-detector output voltage

is compared to a reference voltage, and the difference is

amplified. This error signal drives an open-collector tran-

sistor whose collector is connected to the IFOVLD pin,

causing the IFOVLD pin to sink current. The nominal full-

scale current sunk by the IFOVLD pin is 300μA. The

IFOVLD pin requires a 10kΩpullup resistor to VCC.

The IF overload detector is calibrated at the factory to

attack at 0.7VP-P at the IFOUT1. Upon power-up, the

baseband processor must read OD[2:0] from the ROM

table and store it in the IFVOLD register.

Closed-Loop RF Gain Control

Closed-loop RF gain control can be implemented by

connecting the IFOVLD output to the RFAGC input.

Using a 10kΩpullup resistor on the IFOVLD pin as

shown in the

Typical Application Circuit

results in a

nominal control voltage range of 0.5V to 3V.

VCO and VCO Divider Selection

The MAX3541 frequency synthesizer includes three

VCOs and eight VCO sub-bands to guarantee a

2200MHz to 4400MHz VCO frequency range. The fre-

quency synthesizer also features an additional VCO fre-

quency divider that must be programmed to either 4, 8,

16, or 32 by the VDIV[1:0] bits in the VCO register based

on the channel being received.

To ensure PLL lock, the proper VCO and VCO sub-band

for the channel being received must be chosen by itera-

tively selecting a VCO and VCO sub-band, then reading

the LD[2:0] bits to determine if the PLL is locked. Any

reading from 001 to 110 indicates the PLL is locked. If

LD[2:0] reads 000, the PLL is unlocked and the selected

VCO is at the bottom of its tuning range; a lower VCO

sub-band must be selected. If LD[2:0] reads 111, the PLL

is unlocked and the selected VCO is at the top of its tun-

ing range; a higher VCO sub-band must be selected. The

VCO and VCO sub-band settings should be progressive-

ly increased or decreased until the LD[2:0] reading falls in

the 001 to 110 range.

Due to overlap between VCO sub-band frequencies, it is

possible that multiple VCO settings can be used to tune

to the same channel frequency. System performance at

a given channel should be similar between the various

possible VCO settings, so it is sufficient to select the first

VCO and VCO sub-band that provides lock.

Layout Considerations

The MAX3541 EV kit can serve as a guide for PCB lay-

out. Keep RF signal lines as short as possible to mini-

mize losses and radiation. Use controlled impedance on

all high-frequency traces. The exposed paddle must be

soldered evenly to the board’s ground plane for proper

operation. Use abundant vias beneath the exposed pad-

dle for maximum heat dissipation. Use abundant ground

vias between RF traces to minimize undesired coupling.

To minimize coupling between different sections of the

IC, the ideal power-supply layout is a star configuration,

which has a large decoupling capacitor at the central

VCC node. The VCC traces branch out from this node,

with each trace going to separate VCC pins of the

MAX3541. Each VCC pin must have a bypass capacitor

with a low impedance to ground at the frequency of

interest. Do not share ground vias among multiple con-

nections to the PCB ground plane.

TFS INT[10

[US0

256 5US1

256 -1) 5

×+ ××( 110 f ]

[UP0

256 5UP

-3 RF ]10

TFP INT[10

×+

−

(11

256 -1) 5 10 f ]

-3 RF ]

×× ×

TFS 10

[VS0

256 5VS1

256 -1) 1.5

×+ ×

INT[

(×××

×+

10 f ]

[VP0

256 5VP1

-2 RF

TFP INT[10

]

(556 -1) 10 f ]

-2 RF ]

××

MAX3541

Complete Single-Conversion

Television Tuner

______________________________________________________________________________________ 17

MAX3541

Complete Single-Conversion

Television Tuner

18 ______________________________________________________________________________________

MAX3541

36 IFOUT1-

SCL

35 IFOUT1+

SDA

34 IFOVLD

VCC

33 VCC

UHF_IN

32 VCC

VREF

VHF_IN

31 GND

RFGND2

30 IFIN+

LEXT

29 IFIN-

RFGND3

28 VCC

RFAGC

27 GND

VCC

26 IFAGC

GND

25 IFOUT2+

GND

1000pF

ADDR2GND

ADDR1GND

XTALPGND

XTALNGND

VCC

GND

CPGND

MUXGND

VCC

GND

VTUNEGND

GND_TUNEGND

LDOVCC

VCC

IFOUT2-

SERIAL

INTERFACE

÷ R PD CP

÷ N

VCO

DIVIDER

ANTI-ALIASING

FILTER

2.7kΩ

1000pF

IFOUT+

VIFAGC

IFOUT-

IFOVLD

VCC

0.1μF

1000pF

0.1μF

VCC

1000pF

10kΩ

VCC

1000pF

VCC

1000pF

VCC

1000pF

2.7kΩ

2.7kΩ2.7kΩ

IFOVLD

0.1μF

1000pF

47μF

100Ω

820pF 560pF

0.033μF

2.2kΩ

VCC

IF-SAW

FILTER

680nH

1000pF

22pF

8MHz

4.3kΩ

220pF

270nH

1000pF

VCC

SDATA

SCLK

ADDRESS 2

ADDRESS 1

VCC

1000pF

VCC

** CONNECT TO COMMON GROUND POINT AT PIN 39

Typical Application Circuit

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maxim-ic.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

48 LGA-EP L4877F+15 21-0152 90-0303

MAX3541

Complete Single-Conversion

Television Tuner

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 10/07 Initial release —

1 12/07 Correct TOC01 graph and a few errors 1, 2, 5, 7

2 4/08 Converted part number in Ordering Information to lead-free 1

3 2/11 Corrected soldering temperature and lead temperature in Absolute Maximum

Ratings 2