74AHCT2G32DP,125 - NEXPERIA

74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

Rev. 4 — 18 December 2018 Product data sheet

1. General description

The 74AHC2G32; 74AHCT2G32 are high-speed Si-gate CMOS devices. They provide two 2-input

OR gates.

The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.

The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V

2. Features and benefits

•Symmetrical output impedance

•High noise immunity

•ESD protection:

••HBM JESD22-A114E exceeds 2000 V

•MM JESD22-A115-A exceeds 200 V

•CDM JESD22-C101C exceeds 1000 V

•Low power dissipation

•Balanced propagation delays

•Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74AHC2G32DP

74AHCT2G32DP

-40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8

leads; body width 3 mm; lead length 0.5 mm

SOT505-2

74AHC2G32DC

74AHCT2G32DC

-40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package;

8 leads; body width 2.3 mm

SOT765-1

4. Marking

Table 2. Marking

Type number Marking code[1]

74AHC2G32DP A32

74AHCT2G32DP C32

74AHC2G32DC A32

74AHCT2G32DC C32

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

5. Functional diagram

mna733

1B 1Y

2B 2Y

Fig. 1. Logic symbol

mna734

≥ 1

Fig. 2. IEC logic symbol

mna166

Fig. 3. Logic diagram (one gate)

6. Pinning information

6.1. Pinning

74AHC2G32

74AHCT2G32

1A VCC

1B 1Y

2Y 2B

GND 2A

001aaj504

Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)

6.2. Pin description

Table 3. Pin description

Symbol Pin Description

1A, 2A 1, 5 data input

1B, 2B 2, 6 data input

GND 4 ground (0 V)

1Y, 2Y 7, 3 data output

VCC 8 supply voltage

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level.

Input Output

nA nB nY

LLL

L H H

H L H

HHH

Product data sheet Rev. 4 — 18 December 2018 2 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +7.0 V

VIinput voltage -0.5 +7.0 V

IIK input clamping current VI < -0.5 V [1] -20 - mA

IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA

IOoutput current -0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - 75 mA

IGND ground current -75 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [2] - 250 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.

For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.

9. Recommended operating conditions

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

74AHC2G32 74AHCT2G32Symbol Parameter Conditions

Min Typ Max Min Typ Max

Unit

VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V

VIinput voltage 0 - 5.5 0 - 5.5 V

VOoutput voltage 0 - VCC 0 - VCC V

Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C

VCC = 3.3 V ± 0.3 V - - 100 - - - ns/VΔt/ΔV input transition rise and

fall rate VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V

10. Static characteristics

Table 7. Static characteristics

Voltages are referenced to GND (ground = 0 V).

25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

74AHC2G32

VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V

VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V

VIH HIGH-level

input voltage

VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V

VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V

VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V

VIL LOW-level

input voltage

VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V

Product data sheet Rev. 4 — 18 December 2018 3 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

VI = VIH or VIL

IO = -50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = -50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

IO = -50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V

VOH HIGH-level

output voltage

IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.70 - V

VI = VIH or VIL

IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V

VOL LOW-level

output voltage

IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current

VI = 5.5 V or GND;

VCC = 0 V to 5.5 V

- - 0.1 - 1.0 - 2.0 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 5.5 V

- - 1.0 - 10 - 40 μA

CIinput

capacitance

- 1.5 10 - 10 - 10 pF

74AHCT2G32

VIH HIGH-level

input voltage

VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

VIL LOW-level

input voltage

VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

VI = VIH or VIL; VCC = 4.5 V

IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V

VOH HIGH-level

output voltage

IO = -8.0 mA 3.94 - - 3.8 - 3.70 - V

VI = VIH or VIL; VCC = 4.5 V

IO = 50 μA - 0 0.1 - 0.1 - 0.1 V

VOL LOW-level

output voltage

IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current

VI = 5.5 V or GND;

VCC = 0 V to 5.5 V

- - 0.1 - 1.0 - 2.0 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 5.5 V

- - 1.0 - 10 - 40 μA

ΔICC additional

supply current

per input pin; VI = 3.4 V;

other inputs at VCC or GND;

IO = 0 A; VCC = 5.5 V

- - 1.35 - 1.5 - 1.5 mA

CIinput

capacitance

- 1.5 10 - 10 - 10 pF

Product data sheet Rev. 4 — 18 December 2018 4 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

11. Dynamic characteristics

Table 8. Dynamic characteristics

GND = 0 V; for test circuit see Fig. 6.

25 °C -40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max Min Max

Unit

74AHC2G32

nA, nB to nY; see Fig. 5 [1]

VCC = 3.0 V to 3.6 V [2]

CL = 15 pF - 4.4 7.9 1.0 9.5 1.0 10.0 ns

CL = 50 pF - 6.3 11.4 1.0 13.0 1.0 14.5 ns

VCC = 4.5 V to 5.5 V [3]

CL = 15 pF - 3.2 5.5 1.0 6.5 1.0 7.0 ns

tpd propagation

delay

CL = 50 pF - 4.6 7.5 1.0 8.5 1.0 9.5 ns

CPD power

dissipation

capacitance

per buffer;

CL = 50 pF; fi = 1 MHz;

VI = GND to VCC

[4] - 16 - - - - - pF

74AHCT2G32

nA, nB to nY; see Fig. 5 [1]

VCC = 4.5 V to 5.5 V [3]

CL = 15 pF - 3.3 6.9 1.0 8.0 1.0 9.0 ns

tpd propagation

delay

CL = 50 pF - 4.8 7.9 1.0 9.0 1.0 10.0 ns

CPD power

dissipation

capacitance

per buffer;

CL = 50 pF; fi = 1 MHz;

VI = GND to VCC

[4] - 17 - - - - - pF

[1] tpd is the same as tPLH and tPHL.

[2] Typical values are measured at VCC = 3.3 V.

[3] Typical values are measured at VCC = 5.0 V.

[4] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC

2 x fi x N + Σ(CL x VCC

2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ(CL x VCC

2 x fo) = sum of the outputs.

Product data sheet Rev. 4 — 18 December 2018 5 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

11.1. Waveforms and test circuit

mna224

nA, nB input

nY output

tPLH

tPHL

GND

VOH

VOL

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 5. The input (nA and nB) to output (nY) propagation delays

Table 9. Measurement points

Input OutputType

VMVM

74AHC2G32 0.5VCC 0.5VCC

74AHCT2G32 1.5 V 0.5VCC

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

Test data is given in Table 10.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator;

CL = Load capacitance including jig and probe capacitance; RL = Load resistance; S1 = Test selection switch.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Input Load S1 positionType

VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ

74AHC2G32 VCC ≤ 3 ns 15 pF, 50 pF 1 kΩ open GND VCC

74AHCT2G32 3 V ≤ 3 ns 15 pF, 50 pF 1 kΩ open GND VCC

Product data sheet Rev. 4 — 18 December 2018 6 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

12. Package outline

UNIT A1

max. A2 A3 bp L HE Lp w y v

c e D(1) E(1) Z(1) θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9 0.65 4.1

3.9

0.70

0.35

8°

0°

0.13 0.1 0.2 0.5

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.47

0.33

SOT505-2 - - - 02-01-16

w M

0.25

1 4

8 5

(A3)

detail X

v M A

2.5 5 mm 0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2

1.1

pin 1 index

Fig. 7. Package outline SOT505-2 (TSSOP8)

Product data sheet Rev. 4 — 18 December 2018 7 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT765-1 MO-187

sot765-1_po

07-06-02

16-05-31

Unit

max

nom

min

0.15 0.27 0.23 2.1

0.5

0.4

max.

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1

A1A2

0.85

A3bpc D(1) E(2) e HEL

0.4

LpQ v w

1 0.12 0.10.2 0.08

y Z(1)

3.0 0.152.2 0.190.00 0.17 0.08 1.9 0.10.60 0°

3.2 0.402.4 0.21 8°

scale

5 mm

detail X

v A

1 4

(A3)

pin 1 index

Fig. 8. Package outline SOT765-1 (VSSOP8)

Product data sheet Rev. 4 — 18 December 2018 8 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

13. Abbreviations

Table 11. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

14. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHC_AHCT2G32 v.4 20181218 Product data sheet - 74AHC_AHCT2G32 v.3

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Type numbers 74AHC2G32GD and 74AHCT2G32GD removed.

74AHC_AHCT2G32 v.3 20130514 Product data sheet - 74AHC_AHCT2G32 v.2

Modifications: •For type number 74AHC2G32GD and 74AHCT2G32GD XSON8U has changed to

XSON8.

74AHC_AHCT2G32 v.2 20090120 Product data sheet - 74AHC_AHCT2G32 v.1

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Added type number 74AHC2G32GD and 74AHCT2G32GD (XSON8U package).

74AHC_AHCT2G32 v.1 20040223 Product specification - -

Product data sheet Rev. 4 — 18 December 2018 9 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

15. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

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changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

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Product data sheet Rev. 4 — 18 December 2018 10 / 11

Nexperia 74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Marking.......................................................................... 1

5. Functional diagram.......................................................2

6. Pinning information......................................................2

6.1. Pinning.........................................................................2

6.2. Pin description............................................................. 2

7. Functional description................................................. 2

8. Limiting values............................................................. 3

9. Recommended operating conditions..........................3

10. Static characteristics..................................................3

11. Dynamic characteristics.............................................5

11.1. Waveforms and test circuit........................................ 6

12. Package outline.......................................................... 7

13. Abbreviations.............................................................. 9

14. Revision history..........................................................9

15. Legal information......................................................10

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 18 December 2018

Product data sheet Rev. 4 — 18 December 2018 11 / 11