Features
•Floating channel designed for bootstrap operation
Fully operational to +500V or +600V
Tolerant to negative transient voltage
dV/dt immune
•Gate drive supply range from 10 to 20V
•Undervoltage lockout for both channels
•3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground ±5V offset
•CMOS Schmitt-triggered inputs with pull-down
•Cycle by cycle edge-triggered shutdown logic
•Matched propagation delay for both channels
•Outputs in phase with inputs
Data Sheet No. PD60147 rev.U
HIGH AND LOW SIDE DRIVER
Product Summary
VOFFSET (IR2110) 500V max.
(IR2113) 600V max.
IO+/- 2A / 2A
VOUT 10 - 20V
ton/off (typ.) 120 & 94 ns
Delay Matching (IR2110) 10 ns max.
(IR2113) 20ns max.
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Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output chan-
nels. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. Logic inputs are compatible with
standard CMOS or LSTTL output, down to 3.3V logic. The output
drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 500 or 600 volts.
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Typical Connection
Packages
14-Lead PDIP
IR2110/IR2113
16-Lead SOIC
IR2110S/IR2113S
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol Definition Min. Max. Units
VBHigh side floating supply voltage (IR2110) -0.3 525
(IR2113) -0.3 625
VSHigh side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VCC Low side fixed supply voltage -0.3 25
VLO Low side output voltage -0.3 VCC + 0.3
VDD Logic supply voltage -0.3 VSS + 25
VSS Logic supply offset voltage VCC - 25 VCC + 0.3
VIN Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3
dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C (14 lead DIP) — 1.6
(16 lead SOIC) — 1.25
RTHJA Thermal resistance, junction to ambient (14 lead DIP) — 75
(16 lead SOIC) — 100
TJJunction temperature — 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) — 300
°C/W
W
V
°C
Symbol Definition Min. Max. Units
VBHigh side floating supply absolute voltage VS + 10 VS + 20
VSHigh side floating supply offset voltage (IR2110) Note 1 500
(IR2113) Note 1 600
VHO High side floating output voltage VSVB
VCC Low side fixed supply voltage 10 20
VLO Low side output voltage 0 VCC
VDD Logic supply voltage VSS + 3 VSS + 20
VSS Logic supply offset voltage -5 (Note 2) 5
VIN Logic input voltage (HIN, LIN & SD) VSS VDD
TAAmbient temperature -40 125 °C
V
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
ton Turn-on propagation delay 7 — 120 150 VS = 0V
toff Turn-off propagation delay 8 — 94 125 VS = 500V/600V
tsd Shutdown propagation delay 9 — 110 140 VS = 500V/600V
trTurn-on rise time 10 — 25 35
tfTurn-off fall time 11 — 17 25
MT Delay matching, HS & LS (IR2110) — — — 10
turn-on/off (IR2113) — — — 20
ns
Dynamic Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25°C and VSS = COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
VIH Logic “1” input voltage 12 9.5 — —
VIL Logic “0” input voltage 13 — — 6.0
VOH High level output voltage, VBIAS - VO14 — — 1.2 IO = 0A
VOL Low level output voltage, VO15 — — 0.1 IO = 0A
ILK Offset supply leakage current 16 — — 50 VB=VS = 500V/600V
IQBS Quiescent VBS supply current 17 — 125 230 VIN = 0V or VDD
IQCC Quiescent VCC supply current 18 — 180 340 VIN = 0V or VDD
IQDD Quiescent VDD supply current 19 — 15 30 VIN = 0V or VDD
IIN+ Logic “1” input bias current 20 — 20 40 VIN = VDD
IIN- Logic “0” input bias current 21 — — 1.0 VIN = 0V
VBSUV+ VBS supply undervoltage positive going 22 7.5 8.6 9.7
threshold
VBSUV- VBS supply undervoltage negative going 23 7.0 8.2 9.4
threshold
VCCUV+ VCC supply undervoltage positive going 24 7.4 8.5 9.6
threshold
VCCUV- VCC supply undervoltage negative going 25 7.0 8.2 9.4
threshold
IO+ Output high short circuit pulsed current 26 2.0 2.5 — VO = 0V, VIN = VDD
PW ≤ 10 µs
IO- Output low short circuit pulsed current 27 2.0 2.5 — VO = 15V, VIN = 0V
PW ≤ 10 µs
Static Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15V, TA = 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
V
µA
V
A
4www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Functional Block Diagram
Lead Definitions
Symbol Description
VDD Logic supply
HIN Logic input for high side gate driver output (HO), in phase
SD Logic input for shutdown
LIN Logic input for low side gate driver output (LO), in phase
VSS Logic ground
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
VCC Low side supply
LO Low side gate drive output
COM Low side return
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Lead Assignments
Part Number
14 Lead PDIP
IR2110/IR2113
16 Lead SOIC (Wide Body)
IR2110S/IR2113S
14 Lead PDIP w/o lead 4
IR2110-1/IR2113-1
14 Lead PDIP w/o leads 4 & 5
IR2110-2/IR2113-2
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit
Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition
Figure 6. Delay Matching Waveform DefinitionsFigure 5. Shutdown Waveform Definitions
10
µF
0.1
µF
V =15V
cc
936
5
7
1
2
13
12
11
10
HIN
SD
LIN
HO
LO
0.1
µF
10
µF
10
µF
CL
CL
VB
+
-
S
V
(0 to 500V/600V)
15V
10
µF
0.1
µF
V =15V
cc
936
5
7
1
2
13
12
11
10
HO
0.1
µF
OUTPUT
MONITOR
10KF6
10KF6
200
µH10KF6 100µF
+
IRF820
HV = 10 to 500V/600V
dV
S>50 V/ns
dt
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 8A. Turn-Off Time vs. Temperature
Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. VCC/VBS Supply Voltage
0
50
100
150
200
250
10 12 14 16 18 20
Turn-On Delay Time (ns)
Max.
Typ.
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-On Delay Time (ns)
Max.
Typ.
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-Off Delay Time (ns)
Max.
Typ.
0
50
100
150
200
250
0 2 4 6 8 101214161820
Ma x .
Typ.
Figure 7C. Turn-On Time vs. VDD Supply Voltage
Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage
0
50
100
150
200
250
10 12 14 16 18 20
Turn-Off Delay Time (ns)
Max.
Typ.
0
50
100
150
200
250
0246810121416182
0
Ma x .
Typ
Figure 8C. Turn-Off Time vs. VDD Supply Voltage
VDD Supply Voltage (V)
Turn-On Delay Time (ns)
VCC/VBS Supply Voltage (V)
VCC/VBS Supply Voltage (V) VDD Supply Voltage (V)
Turn-Off Delay Time (ns)
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 9B. Shutdown Time vs. VCC/VBS Supply Voltage
Figure 9A. Shutdown Time vs. Temperature
0
50
100
150
200
250
10 12 14 16 18 20
Shutdown Delay time (ns)
Max.
Typ.
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (°C)
Shutdown Delay Time (ns)
Max.
Typ.
0
50
100
150
200
250
02468101214161820
VDD Supply Voltage (V)
Max .
T
yp
Shutdown Delay Time (ns)
Figure 9C. Shutdown Time vs. VDD Supply Voltage Figure 10A. Turn-On Rise Time vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-On Rise Time (ns)
Max.
Typ.
Figure 10B. Turn-On Rise Time vs. Voltage
0
20
40
60
80
100
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn-On Rise Time (ns)
Max.
Typ.
Figure 11A. Turn-Off Fall Time vs. Temperature
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-Off Fall Time (ns)
Max.
Typ.
VCC/VBS Supply Voltage (V)
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 11B. Turn-Off Fall Time vs. Voltage
0
10
20
30
40
50
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn-Off Fall Time (ns)
Max.
Typ.
Figure 12A. Logic “1” Input Threshold vs. Tempera-
ture
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "1" Input Threshold (V)
Min.
Max
Figure 12B. Logic “1” Input Threshold vs. Voltage Figure 13A. Logic “0” Input Threshold vs. Tempera-
ture
0.0
3.0
6.0
9.0
12.0
15.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Threshold (V)
Max.
Min.
Figure 13B. Logic “0” Input Threshold vs. Voltage Figure 14A. High Level Output vs. Temperature
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
High Level Output Voltage (V)
Max.
Logic " 1" Input Threshold (V)
0
3
6
9
12
15
0 2 4 6 8 10 12 14 16 18 20
Max.
VDD Logic Supply Voltage (V)
0
3
6
9
12
15
02468101214161820
Min.
Logic "0" Input Threshold (V)
VDD Logic Supply Voltage (V)
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 14B. High Level Output vs. Voltage
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VBIAS Supply Voltage (V)
High Level Output Voltage (V)
M ax.
Figure 15A. Low Level Output vs. Temperature
0.00
0.20
0.40
0.60
0.80
1.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Low Level Output Voltage (V)
Max.
Figure 15B. Low Level Output vs. Voltage
0.00
0.20
0.40
0.60
0.80
1.00
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Low Level Output Voltage (V)
Max.
Figure 16A. Offset Supply Current vs. Temperature
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
Offset Supply Leakage Current (µA)
Max.
Figure 16B. Offset Supply Current vs. Voltage
0
100
200
300
400
500
0 100 200 300 400 500 600
VB Boost Voltage (V)
Offset Supply Leakage Current (µA)
Max.
IR2110 IR2113
Figure 17A. VBS Supply Current vs. Temperature
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
VBS Supply Current (µA)
Max.
Typ.
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 19B. VDD Supply Current vs. VDD Voltage Figure 20A. Logic “1” Input Current vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "1" Input Bias Current (µA)
Max.
Typ.
Figure 17B. VBS Supply Current vs. Voltage
0
100
200
300
400
500
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VBS Supply Current (µA)
Max.
Typ.
Figure 18A. VCC Supply Current vs. Temperature
0
125
250
375
500
625
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCC Supply Current (µA)
Max.
Typ.
Figure 18B. VCC Supply Current vs. Voltage
0
125
250
375
500
625
10 12 14 16 18 20
VCC Fixed Supply Voltage (V)
VCC Supply Current (µA)
Max.
Typ.
Figure 19A. VDD Supply Current vs. Temperature
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (°C)
VDD Supply Current (µA)
Max.
Typ.
0
10
20
30
40
50
60
02468101214161820
VDD Supply Current (µA)
VDD Logic Supply Voltage (V)
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 21A. Logic “0” Input Current vs. Temperature
Figure 21B. Logic “0” Input Current vs. VDD Voltage
Figure 20B. Logic “1” Input Current vs. VDD Voltage
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Bias Current (µA)
Max.
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VBS Undervoltage Lockout + (V)
Max.
Typ.
Min.
Figure 22. VBS Undervoltage (+) vs. Temperature
Figure 23. VBS Undervoltage (-) vs. Temperature
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VBS Undervoltage Lockout - (V)
Max.
Typ.
Min.
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCC Undervoltage Lockout + (V)
Max.
Typ.
Min.
Figure 24. VCC Undervoltage (+) vs. Temperature
Logic “1” Input Bias Current (µA)
VDD Logic Supply Voltage (V)
0
10
20
30
40
50
60
02468101214161820
Logic “0” Input Bias Current (µA)
VDD Logic Supply Voltage (V)
0
1
2
3
4
5
02468101214161820
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 26B. Output Source Current vs. Voltage
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Output Source Current (A)
Min.
Typ.
Figure 27A. Output Sink Current vs. Temperature
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Sink Current (A)
Min.
Typ.
Figure 27B. Output Sink Current vs. Voltage
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Output Sink Current (A)
Min.
Typ.
Figure 28. IR2110/IR2113 TJ vs. Frequency
(IRFBC20) RGATE = 33ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V
140V
10V
Figure 25. VCC Undervoltage (-) vs. Temperature
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCC Undervoltage Lockout - (V)
Max.
Typ.
Min.
Figure 26A. Output Source Current vs. Temperature
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Source Current (A)
Min.
Typ.
14 www.irf.com
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 29. IR2110/IT2113 TJ vs. Frequency
(IRFBC30) RGATE = 22ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V
140V
10V
Figure 30. IR2110/IR2113 TJ vs. Frequency
(IRFBC40) RGATE = 15ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V 140V
10V
Figure 31. IR2110/IR2113 TJ vs. Frequency
(IRFPE50) RGATE = 10ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V 140V
10V
Figure 32. IR2110S/IR2113S TJ vs. Frequency
(IRFBC20) RGATE = 33ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V 140V
10V
Figure 33. IR2110S/IR2113S TJ vs. Frequency
(IRFBC30) RGATE = 22ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V 140V
10V
Figure 34. IR2110S/IR2113S TJ vs. Frequency
(IRFBC40) RGATE = 15ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V 140V
10V
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
Figure 35. IR2110S/IR2113S TJ vs. Frequency
(IRFPE50) RGATE = 10ΩΩ
ΩΩ
Ω, VCC = 15V
0
25
50
75
100
125
150
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Junction Temperature (°C)
320V 140V 10V
Figure 36. Maximum VS Negative Offset vs.
VBS Supply Voltage
-10.0
-8.0
-6.0
-4.0
-2.0
0.0
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VS Offset Supply Voltage (V)
Typ.
Figure 37. Maximum VSS Positive Offset vs.
VCC Supply Voltage
0.0
4.0
8.0
12.0
16.0
20.0
10 12 14 16 18 20
VCC Fixed Supply Voltage (V)
VSS Logic Supply Offset Voltage (V)
Typ.
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
01-6010
01-3002 03 (MS-001AC)
14-Lead PDIP
Case Outlines
14-Lead PDIP w/o Lead 4 01-6010
01-3008 02 (MS-001AC)
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
16-Lead SOIC (wide body) 01 6015
01-3014 03 (MS-013AA)
16 Lead PDIP w/o Leads 4 & 5 01-6015
01-3010 02
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IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
LEADFREE PART MARKING INFORMATION
ORDER INFORMATION
14-Lead PDIP IR2110 order IR2110PbF
14-Lead PDIP IR2110-1 order IR2110-1PbF
14-Lead PDIP IR2110-2 order IR2110-2PbF
14-Lead PDIP IR2113 order IR2113PbF
14-Lead PDIP IR2113-1 order IR2113-1PbF
14-Lead PDIP IR2113-2 order IR2113-2PbF
16-Lead SOIC IR2110S order IR2110SPbF
16-Lead SOIC IR2113S order IR2113SPbF
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
P
?MARKING CODE
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been qualified per industrial level
Data and specifications subject to change without notice 3/23/2005
Part only available Lead Free
