FEATURES Wideband Digital IF Parallel Output Wideband Digital IF Parallel Input Allows Cascade of Chips for Additional Channels Programmable IF and Modulation for Each Channel Programmable Interpolating RAM Coefficient Filter High-Speed CIC Interpolating Filter NCO Frequency Translation Worst Spur Better than 100 dBc Tuning Resolution Better than 0.02 Hz Real or Complex Outputs Digital Summation of Channels Clipped or Wrapped Overrange Two's Complement or Offset Binary Output Separate 3-Wire Serial Data Input for Each Channel Microprocessor Control JTAG Boundary Scan FUNCTIONAL BLOCK DIAGRAM CH A SPORT RCF CIC FILTER NCO CH B SPORT RCF CIC FILTER NCO CH C SPORT RCF CIC FILTER NCO RCF CIC FILTER NCO CH D SPORT JTAG 18 SUMMATION a Four-Channel, 75 MSPS Digital Transmit Signal Processor (TSP) AD6622 18 PORT APPLICATIONS Cellular/PCS Base Stations Micro/Pico Cell Base Stations WBCDMA Wireless Local Loop Base Stations Phase Array Beam Forming Antennas PRODUCT DESCRIPTION The AD6622 comprises four identical digital Transmit Signal Processors (TSPs) complete with synchronization circuitry and cascadable wideband channel summation. An external digitalto-analog converter (DAC) is all that is required to complete a wide band digital up-converter. On-chip tuners allow the relative phase and frequency for each RF carrier to be independently controlled. Each TSP has three cascaded signal processing elements: a RAM-programmable Coefficient interpolating Filter (RCF), a programmable Cascaded Integrator Comb (CIC) interpolating filter, and a Numerically Controlled Oscillator/tuner (NCO). The outputs of the four TSPs are summed and scaled on-chip. In multichannel wideband transmitters, multiple AD6622s may be combined using the chip's cascadable output summation stage. Each channel provides independent serial data inputs that may be directly connected to the serial port of DSP chips. User programmable FIR filters can be used to filter linear inputs. All control registers and coefficient values are programmed through a generic microprocessor interface. Two microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compatible. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 AD6622-SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Test Level Min VDD TAMBIENT IV IV 2.4 -40 Test Level Min AD6622AS Typ 3.0 +25 Max Unit 3.3 +70 V C Max Unit VDD + 0.3 +0.8 10 10 V V A A pF ELECTRICAL CHARACTERISTICS AD6622AS Typ Parameter (Conditions) Temp LOGIC INPUTS (5 V TOLERANT) Logic Compatibility Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Full Full Full Full Full 25C IV IV IV IV V 2.0 -0.3 LOGIC OUTPUTS Logic Compatibility Logic "1" Voltage (IOH = 0.25 mA) Logic "0" Voltage (IOL = 0.25 mA) Full Full Full IV IV VDD - 0.05 IDD SUPPLY CURRENT CLK = 60 MHz, 3.3 V1 CLK = GSM Example CLK = IS-136 Example CLK = WBCDMA Example Sleep Mode POWER DISSIPATION CLK = 60 MHz, 3.3 V1 CLK = GSM Example CLK = IS-136 Example CLK = WBCDMA Example Sleep Mode 3.0 V CMOS Full Full Full Full 1 1 4 VDD - 0.035 0.02 0.05 IV V V V IV 506 2972 2402 2092 0.1 5661 IV V V V IV 1.77 0.892 0.722 0.6272 0.33 1.87 0.5 1.65 V V mA mA mA mA mA W W W W mW NOTES 1 This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimum interpolation in both CIC stages, maximum switching of input data, and maximum VDD of 3.3 V. In an actual application the power will be less; see the Thermal Management section of the data sheet for further details. 2 GSM interpolation = 120 at 65 MHz, 4 channels active, IS-136 interpolation = 2560 at 62.208 MHz, 4 channels active. WBCDMA interpolation = 64, 4 channels interleaved at 61.44 MHz. Specifications subject to change without notice. -2- REV. 0 AD6622 TIMING CHARACTERISTICS1 (C LOAD = 40 pF, all outputs unless specified) Temp Test Level Min AD6622AS Typ Max Unit CLK Timing Requirements: tCLK CLK Period CLK Width Low tCLKL tCLKH CLK Width High Full Full Full IV IV IV 13.3 5.5 5.5 0.5 x tCLK 0.5 x tCLK ns ns ns RESET Timing Requirements: tRESL RESET Width Low Full IV 30.0 ns Input Wideband Data Timing Requirements: tSI Input to CLK Setup Time tHI Input to CLK Hold Time Full Full IV IV 0.5 3.5 ns ns Parallel Output Switching Characteristics: tSO CLK to Output Setup Time tHO CLK to Output Hold Time tZO Output Three-State Time Full Full Full IV IV V 4.1 SYNC Timing Requirements: tSS SYNC to CLK Setup Time tHS SYNC to CLK Hold Time Full Full IV IV 2.6 1.5 Serial Port Timing Requirements: tDSCLK CLK to SCLK Delay tDSDFS SCLK to SDFS Delay tSSI SDI to SCLK Setup Time SDI to SCLK Hold Time tHSI tSCS Serial Clock Skew Full Full Full Full Full V IV IV IV IV -1.2 8.5 5.5 MODE INM Write Timing: tHWR WR(R/W) to RDY(DTACK) Hold Time tSAM Address/Data to WR(R/W) Setup Time Address/Data to RDY(DTACK) Hold Time tHAM tDRDY WR(R/W) to RDY(DTACK) Delay tACCFAST WR(R/W) to RDY(DTACK) High Delay tACCMEDIUM WR(R/W) to RDY(DTACK) High Delay tACCSLOW WR(R/W) to RDY(DTACK) High Delay Full Full Full Full Full Full Full IV IV IV IV IV IV IV 0 0 0 MODE INM Read Timing: Address to RD(DS) Setup Time tSAM tHA Address to Data Hold Time Data Three-State Delay tZD tDD RDY(DTACK) to Data Delay tDRDY RD(DS) to RDY(DTACK) Delay RD(DS) to RDY(DTACK) High Delay tACCFAST tACCMEDIUM RD(DS) to RDY(DTACK) High Delay tACCSLOW RD(DS) to RDY(DTACK) High Delay Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 0 0 3.4 Name Parameter (Conditions) 12 5 ns ns ns ns ns 8.5 +2.4 7 ns ns ns ns ns MICROPROCESSOR PORT, MODE INM (MODE = 0) REV. 0 -3- 2 x tCLK 3 x tCLK 4 x tCLK 2 x tCLK 3 x tCLK 4 x tCLK 7 10.2 3 x tCLK 4 x tCLK 5 x tCLK ns ns ns ns ns ns ns 10.5 tCLK - 10 10.2 3 x tCLK 4 x tCLK 5 x tCLK ns ns ns ns ns ns ns ns AD6622 Temp Test Level MODE MNM Write Timing: tHDS DS(RD) to DTACK(RDY) Hold Time tHRW R/W(WR) to DTACK(RDY) Hold Time Address/Data to R/W(WR) Setup Time tSAM tHAM Address/Data to R/W(WR) Hold Time tDDTACK DS(RD) to DTACK(RDY) Delay R/W(WR) to DTACK(RDY) Low Delay tACCFAST tACCMEDIUM R/W(WR) to DTACK(RDY) Low Delay tACCSLOW R/W(WR) to DTACK(RDY) Low Delay Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 0 0 0 0 MODE MNM Read Timing: tSAM Address to DS(RD) Setup Time Address to Data Hold Time tHA Data Three-State Delay tZD tDD DTACK(RDY) to Data Delay DS(RD) to DTACK(RDY) Delay tDDTACK tACCFAST DS(RD) to DTACK(RDY) Low Delay tACCMEDIUM DS(RD) to DTACK(RDY) Low Delay tACCSLOW DS(RD) to DTACK(RDY) Low Delay Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 0 0 0 Name Parameter (Conditions) Min AD6622AS Typ Max Unit MICROPROCESSOR PORT, MODE MNM (MODE = 1) 2 x tCLK 3 x tCLK 4 x tCLK 2 x tCLK 3 x tCLK 4 x tCLK 1 x tCLK 3 x tCLK 4 x tCLK 5 x tCLK ns ns ns ns ns ns ns ns tCLK - 10 1 x tCLK 3 x tCLK 4 x tCLK 5 x tCLK ns ns ns ns ns ns ns ns NOTES 1 All Timing Specifications valid over VDD range of 2.4 V to 3.3 V. Specifications subject to change without notice. tCLK CLK tCLKL tSI CLK tHI tCLKH IN[17:0], QIN tSO Figure 3. Wideband Input Timing OUT[17:0], QOUT tHO tZO tZO CLK OEN tSS Figure 1. Parallel Output Switching Characteristics tHS SYNC Figure 4. SYNC Timing Inputs CLK tDSCLK SCLK CLKn tDSDFS tDSDFS SDFS tSSI SDI tHSI DATAn Figure 2. Serial Port Switching Characteristics -4- REV. 0 AD6622 RD (DS) tHWR WR (R/W) CS tHAM tSAM VALID ADDRESS A[2:0] tHAM tSAM VALID DATA D[7:0] tDRDY RDY (DTACK) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY. 2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 5. INM Microport Write Timing Requirements RD (DS) WR (R/W) CS tSAM A[2:0] VALID ADDRESS tHA tDD tZD tZD VALID DATA D[7:0] tDRDY RDY (DTACK) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY. 2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 6. INM Microport Read Timing Requirements REV. 0 -5- AD6622 tHDS DS (RD) tHRW R/W (WR) CS tSAM tHAM VALID ADDRESS A[2:0] tSAM tHAM VALID DATA D[7:0] tDDTACK DTACK (RDY) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK. 2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 7. MNM Microport Write Timing Requirements tHDS DS (RD) R/W (WR) CS tSAM A[2:0] VALID ADDRESS tHA tDD tZD tZD VALID DATA D[7:0] tDDTACK DTACK (RDY) tACC 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK. 2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1 3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER VERSUS A RAM REGISTER. 4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS. Figure 8. MNM Microport Read Timing Requirements -6- REV. 0 AD6622 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V Input Voltage . . . . -0.3 V to VDD +0.3 V (Not 5 V Tolerant) IN[17:0], QIN, OEN Input Voltage . . . . . . . . . . . . . -0.3 V to +3.6 V (5 V Tolerant) CLK, RESET, DS, R/W, MODE, A[2:0], D[7:0], SYNC, TRST, TCK, TMS, TDI, SDINA, SDINB, SDINC, SDIND Output Voltage Swing . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280C I. 100% Production Tested. II. 100% Production Tested at 25C, and Sample Tested at Specified Temperatures. III. Sample Tested Only. IV. Parameter Guaranteed by Design and Analysis. V. Parameter is Typical Value Only. VI. 100% Production Tested at 25C, and Sample Tested at Temperature Extremes. *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 128-Lead MQFP: JA = 33C/W, No Airflow JA = 27C/W, 200 LFPM Airflow JA = 24C/W, 400 LFPM Airflow JC = 5.5C/W Thermal measurements made in the horizontal position on a 2-layer board. ORDERING GUIDE Model Temperature Range Package Description Package Option AD6622AS AD6622S/PCB -40C to +70C (Ambient) 128-Lead MQFP (Metric Quad Flatpack) Evaluation Board with AD6622 and Software S-128A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6622 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 -7- WARNING! ESD SENSITIVE DEVICE AD6622 65 GND 67 CLK 66 VDD 68 GND 69 GND 71 IN17 70 QIN 72 GND 73 GND 74 IN16 75 IN15 76 IN14 78 VDD 77 IN13 79 IN12 80 IN11 81 IN10 83 GND 82 IN9 85 GND 84 GND 86 IN8 88 IN6 87 IN7 90 VDD 89 IN5 91 IN4 93 IN2 92 IN3 95 GND 94 IN1 97 IN0 96 GND 99 GND 98 GND 101 TCK 100 TRST 102 GND PIN CONFIGURATION GND 103 VDD 104 63 GND GND 105 62 SYNC TMS 106 TDO 107 61 RESET 60 CS 59 VDD 64 GND TDI 108 SCLKA 109 58 A0 VDD 110 SDFSA 111 56 A2 57 A1 SDINA 112 55 MODE 54 GND SCLKB 113 AD6622 SDFSB 114 GND 115 GND 116 53 GND 52 GND TOP VIEW (Not to Scale) 51 R/W(WR) GND 117 SDINB 118 SCLKC 119 50 DTACK(RDY) SDFSC 120 SDINC 121 47 VDD 49 DS(RD) 48 D0 46 D1 VDD 122 SCLKD 123 44 D3 SDFSD 124 SDIND 125 42 GND 45 D2 43 D4 GND 126 VDD 127 41 VDD 40 D5 PIN 1 IDENTIFIER D6 37 GND 38 GND 35 GND 36 D7 33 GND 34 GND 32 GND 31 QOUT 30 OUT17 29 OUT15 27 24 OUT13 OUT16 28 23 OUT12 VDD 26 22 OUT11 OUT14 25 21 GND GND 20 GND 19 OUT9 17 OUT10 18 9 GND OUT8 16 8 OUT2 OUT7 15 7 OUT1 VDD 14 6 OUT0 OUT6 13 5 GND OUT5 12 4 GND OUT4 11 3 GND OUT3 10 1 2 OEN 39 GND GND GND 128 DENOTES I/O POWER PIN DENOTES CORE POWER PIN -8- REV. 0 AD6622 PIN FUNCTION DESCRIPTIONS Pin Number Name 1, 3-5, 9, 19-21, 31, 32, GND 34-36, 38, 39, 42, 52-54, 63-65, 68, 69, 72, 73, 83-85, 95, 96, 98, 99, 102, 103, 105, 115-117, 126, 128 2 OEN Type Description P Ground Connection I Active High Output Enable Pin (Actively Pulled Down If Not Connected) (Not 5 V Tolerant) Wideband Output Data 27-29, 22-25, 15-18, 10-13, 6-8 14, 26, 41, 47, 122 59, 66, 78, 90, 104, 110, 127 30 33, 37, 40, 43-46, 48 49 50 OUT[17:0] O/T VDD VDD QOUT D[7:0] DS (RD) DTACK (RDY) P P O/T I/O/T I O 51 55 56-58 60 61 62 R/W (WR) MODE A[2:0] CS RESET SYNC I I I I I I 67 70 CLK QIN I I 71, 74-77, 79-82, 86-89, 91-94, 97 100 101 106 107 108 109 111 112 113 114 118 119 120 121 123 124 125 IN[17:0] I TRST TCK TMS TDO TDI SCLKA SDFSA SDINA SCLKB SDFSB SDINB SCLKC SDFSC SDINC SCLKD SDFSD SDIND I I I O I O O I O O I O O I O O I REV. 0 +3.0 V Supply (I/O Supply) +3.0 V Supply (Core Supply) Indicates Q Output Data (Complex Output Mode) Microprocessor Interface Data INM Mode: Read Signal, MNM Mode: Data Strobe Signal Acknowledgment of a Completed Transaction (Signals when P Port Is Ready for an Access) Open Drain, Must Be Pulled Up Externally Read/Write Line (Write Signal) Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0, INM Mode Microprocessor Interface Address Chip Select, Enable the Chip for P Access Active Low Reset Pin (Actively Pulled Up If Not Connected) SYNC Signal for Synchronizing Multiple AD6622s (Actively Pulled Down If Not Connected) Input Clock (Actively Pulled Down If Not Connected) Indicates Q Input Data (Complex Input Mode) (Actively Pulled Down If Not Connected) (Not 5 V Tolerant) Wideband Input Data (Allows Cascade of Multiple AD6622 Chips In a System) (Actively Pulled Down If Not Connected) (Not 5 V Tolerant) Test Reset Pin (Actively Pulled Up If Not Connected) Test Clock Input (Actively Pulled Down If Not Connected) Test Mode Select (Actively Pulled Up If Not Connected) Test Data Output Test Data Input (Actively Pulled Down If Not Connected) Serial Clock Output Channel A Serial Data Frame Sync Output Channel A Serial Data Input Channel A (Actively Pulled Down If Not Connected) Serial Clock Output Channel B Serial Data Frame Sync Output Channel B Serial Data Input Channel B (Actively Pulled Down If Not Connected) Serial Clock Output Channel C Serial Data Frame Sync Output Channel C Serial Data Input Channel C (Actively Pulled Down If Not Connected) Serial Clock Output Channel D Serial Data Frame Sync Output Channel D Serial Data Input Channel D (Actively Pulled Down If Not Connected) -9- AD6622 AD6622 SPORT SDINB SDFSB SCLKB SPORT SDINC SDFSC SCLKC SPORT DATA DATA DATA I RCF Q I RCF Q RCF Q I I CIC FILTER Q NCO I CIC FILTER Q NCO I CIC FILTER Q NCO DATa QIN IN [17:0] DATb SUMMATION SDINA SDFSA SCLKA DATc SYNC OEN QOUT SDIND SDFSD SCLKD SPORT DATA I RCF I CIC FILTER Q Q NCO DATd OUT [17:0] CLK RESET CS A[2:0] R/W MODE DS D[7:0] TMS TRST TDI TDO TCK DTACK MICROPORT JTAG Figure 9. Functional Block Diagram THEORY OF OPERATION As digital-to-analog converters (DACs) achieve higher sampling rates, analog bandwidth, and dynamic range, it becomes increasingly attractive to accomplish the first IF stage of a transmitter in the digital domain. Digital IF signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high-dynamic-range analog designs. The AD6622 Four-Channel Transmit Signal Processor (TSP) is designed to bridge the gap between DSPs and high-speed DACs. The wide range of interpolation factors in each filter stage makes the AD6622 useful for creating both narrowband and wideband carriers in a high-speed sample stream. The high-resolution NCO allows flexibility in frequency planning and supports both digital and analog air interface standards. The RAM-based architecture allows easy reconfiguration for multimode applications. The interpolating filters remove unwanted images of signals sampled at a fraction of the wideband rate. When the channel of interest occupies far less bandwidth than the wideband output signal, rejecting out-of-band noise is called "processing gain." For large interpolation factors, this processing gain allows a 14-bit DAC to express the sum of multiple 16-bit signals sampled at a lower rate without significantly increasing the noise floor about each carrier. In addition, the programmable RAM coefficient stage allows anti-imaging, and static equalization functions to be combined in a single, cost-effective filter. The high-speed NCO can be used to tune a quadrature sampled signal to an IF channel, or the NCO can be directly frequencymodulated at an IF channel. Multicarrier phase synchronization pins and phase offset registers allow intelligent management of the relative phase of the independent RF channels. This capability supports the requirements for phased array antenna architectures and management of the wideband peak/power ratio to minimize clipping at the DAC. noise. The wideband ports can be configured for real or quadrature outputs. Quadrature sampled outputs (I and Q) are limited to half the master clock rate on the shared output bus. FUNCTIONAL OVERVIEW The following descriptions explain the functionality of each of the core sections of the AD6622. Detailed timing, application, and specifications are described in detail in their respective portions of the data sheet. SERIAL DATA PORT The AD6622 has four independent Serial Ports (A, B, C, and D) of which accepts data to its own channel (1, 2, 3, or 4) of the device. Each serial port has three pins: SCLK, SDFS, and SDIN. The SCLK and SDFS pins are outputs that provide serial clock and framing. The SDIN pins are inputs that accept channel data. The serial ports do not accept configuration or control inputs. The serial ports do not accept external clock or framing signals, although it is possible to synchronize the AD6622 serial ports to meet an external timing requirement. The serial clock output, SCLK, is created by a programmable internal counter that divides down the master clock. When the channel is reset, SCLK is held low. SCLK starts on the first rising edge of CLK after Channel Reset is removed (D0 through D3 of External Address 4). Once active, the SCLK frequency is determined by the master CLK frequency and the SCLK divider, according to the equation below. The SCLK divider is a 5-bit unsigned value located in Channel Register 0x0D. The user must select the SCLK divider to ensure that SCLK is fast enough to accept full input sample words at the input sample rate. See the design example at the end of this section. The maximum SCLK frequency is 1/2 of the master clock frequency. The minimum SCLK frequency is 1/64 of the master clock frequency. The wideband input and output ports allow multiple AD6622s to be cascaded into a single DAC. The master clock for the entire system is based on the DAC clock rate (up to 75 MSPS). The external 18-bit resolution reduces summation of truncation -10- f SCLK = fCLK 2 x (SCLK DIVIDER + 1) (1) REV. 0 AD6622 The serial data frame sync output, SDFS, is pulsed high for one SCLK cycle at the input sample rate. The input sample rate is determined by the master clock divided by channel interpolation factor. If the SCLK rate is not an integer multiple of the input sample rate, the SDFS will continually adjust the period by one SCLK cycle in order to keep the average SDFS rate equal to the input sample rate. When the channel is in sleep mode, SDFS is held low. The first SDFS is delayed by the channel reset latency after the Channel Reset is removed. The channel reset latency varies dependent on channel configuration. The serial data input, SDIN, accepts 32-bit words as channel input data. The 32-bit word is interpreted as two 16 bit two's complement quadrature words, I followed by Q, MSB first. The first bit is shifted into the serial port starting on the second rising edge of SCLK after SDFS goes high, as shown by the timing diagram below. PROGRAMMABLE INTERPOLATING RAM COEFFICIENT FILTER (RCF) Each channel has a fully independent RAM Coefficient Filter (RCF). The RCF accepts data from the serial port, filters it, and passes the result to the CIC filter. The RCF implements a FIR filter with optional interpolation. The FIR filter can produce impulse responses up to 128 output samples long. The FIR response may be interpolated up to a factor of 128, although the best filter performance is usually achieved if the RCF interpolation factor is confined to 8 or below. FIR Filter Implementation The RCF accepts quadrature samples from the serial port with a fixed point resolution of 16 bits each, for I and Q. SDFS SCLK SDIN RCF DATA MEM SERIAL PORT 16,16 CLK 16,16 ACCUMULATOR tDSCLK IQ TO CIC FILTER 16,16 SCLK CLKn tDSDFS RCF COARSE SCALE COEFFICIENT MEM tDSDFS Figure 11. RCF Block Diagram SDFS tSSI tHSI DATAn SDI Figure 10. Serial Port Switching Characteristics As an example of the serial port operation, consider a CLK frequency of 62.208 MSPS and a channel interpolation of 2560. In that case, the input sample rate is 24.3 kSPS (62.208 MSPS/ 2560), which is also the SDFS rate. Substituting, fSCLK 32 x fSDFS into the equation below and solving for SCLKDIVIDER, we find the maximum value for SCLKDIVIDER according to Equation 2. SCLK DIVIDER fCLK 64 x fSDFS -1 In conclusion, the SDFS rate is determined by the AD6622 master clock rate and the interpolation rate of the channel. The SDFS rate is equal to the channel input rate. The channel interpolation is equal to RCF interpolation times CIC5 interpolation, times CIC2 interpolation (3) The SCLK rate is determined by the AD6622 master clock rate and SCLKDIVIDER. The SCLK is a divided version of the AD6622 master CLK. The SCLK divide ratio is determined by SCLKDIVIDER as shown in Equation 2. The SCLK must be fast enough to input 32 bits of data prior to the next SDFS. Extra SCLKs are ignored by the serial port. REV. 0 fIN LRCF fIN LRCF a b NRCF TAP fIN LRCF FIR FILTER h[n] c Figure 12. RCF Interpolation (2) Evaluating this equation for our example, SCLKDIVIDER must be less than or equal to 39. Since the SCLKDIVIDER channel register is a 5-bit unsigned number it can only range from 0 to 31. Any value in that range will be valid for this example, but if it is important that the SDFS period is constant, then there is another restriction. For regular frames, the ratio fSCLK/fSDFS must be equal to an integer of 32 or larger. For this example, constant SDFS periods can only be achieved with an SCLK divider of 19. L = LRCF x LCIC 5 x LCIC 2 The AD6622 RCF realizes a sum-of-products filter using a polyphase implementation. This mode is equivalent to an interpolator followed by a FIR filter running at the interpolated rate. In Figure 12, the interpolating block increases the rate by the RCF interpolation factor (LRCF) by inserting LRCF-1 zero valued samples between every input sample. The next block is a filter with a finite impulse response length (NRCF) and an impulse response of h[n], where n is an integer from 0 to NRCF-1. The difference equation for Figure 12 is written below, where h[n] is the RCF impulse response, b[n] is the interpolated input sample sequence at point "b" in Figure 12, and c[n] is the output sample sequence at point "c" in the Figure 12. N RCF -1 c[n ] = h[k - n ] x b[n ] (4) k=0 This difference equation can be described by the transfer function from point "b" to "c" as shown Equation 5. N RCF -1 H bc ( z ) = h[n ] x z - n (5) n=0 The actual implementation of this filter uses a polyphase decomposition to skip the multiply-accumulates when b[n] is zero. Compared to the diagram above, this implementation has the benefits of reducing by a factor of LRCF both the time needed to calculate an output and the required data memory (DMEM). The price of these benefits is that the user must place the coefficients into the coefficient memory (CMEM) indexed by the interpolation phase. The process of selecting the coefficients and placing them into the CMEM is broken into three steps shown below. -11- AD6622 1. Select the Impulse Response Length (NRCF) and the Interpolation Factor (L RCF ). The Impulse Response Length (NRCF) is limited in three ways: by the available calculation time, by the data memory size (DMEM), and by the coefficient memory size (CMEM). The equation below shows that NRCF is limited to the minimum of these three conditions. Time Restriction N RCF -1 LRCF k=0 CMEM Restriction L N RCF min , 16 x LRCF , 128 2 DMEM Restriction (6) where: L = LRCF x LCIC5 x LCIC2 2. The interpolation rate (LRCF) may be any integer of NRCF ranging from 1 to 128, while meeting the above equation. Most filter designs can be optimized by choosing the smallest LRCF that does not compromise the image rejection of the subsequent CIC filter. The quality of an interpolating filter is a strong function of the NRCF/LRCF ratio and a weaker function of NRCF. The best filters are usually achieved by maximizing NRCF/LRCF (no larger than 16) and then increasing both NRCF and LRCF by the same ratio until the filter becomes time or CMEM limited. 3. Once NRCF and LRCF are selected, Channel Register 0x0A is programmed to NRCF - 1, and Channel Register 0x0C is programmed to NRCF/LRCF - 1. ChannelCenterGainp = 2- g x h[k x LRCF + p ] 6. The worst-case peak is calculated similarly to the channel center gain, except that the input sequence swings from fullscale positive to full-scale negative to match the polarity of the coefficient by which it will be multiplied, so that each product is positive. This results in a maximal that must be less than one to guarantee no possibility of wrapping. Note that when LRCF is greater than one, each phase may produce its worst-case peak in response to a different input sequence. 7. Programming DMEM and CMEM. The DMEM must be initialized to all zeros to avoid any unpredictable start-up transients since a reset does not clear the memory. The impulse response h[n] must be reordered by phase for the CMEM as shown in the code below. Several filters with impulse lengths that total less than 128 can be programmed into the CMEM simultaneously and selected later using the RCF offset pointer (ORCF) which is set by Channel Register 0x0B. /* Reorder Fir Coefficients for AD6622 CMEM */ for (p=0; p<L_RCF; p++) for (k=0; k<N_RCF/L_RCF; k++) CMEM[O_RCF + p*N_RCF/L_RCF + k] = C[k*L_RCF +p]; /* End of routine */ Table I. RCF Control Registers 4. Determine the Impulse Response. The impulse response relative to the RCF output rate can be calculated using ordinary FIR design techniques. In most cases, it is desirable to precompensate the inband frequency roll-off of the CIC filter that follows. There are no symmetry requirements, so the RCF can also be used for static phase equalization. The impulse response must be quantized to 16-bit two's complement numbers for the CMEM. The channel center gain and worst-case peak can be calculated for each of the LRCF phases (p) according to the equations below. A RCF coarse scale factor (g) that ranges between 0 and 3 is provided to limit the gain without excessive loss of resolution in the CMEM. The coarse scale factor is located in Channel Register 0x0D. N RCF -1 LRCF (8) WorstCasePeakp = 2- g x |h[k x LRCF + p ]| Channel Address Bit Width 0x0A 8 0x0B 8 0x0C 8 0x0D 8 0x0E 0x0F 0x10 0x11 0x20-0x3F 0x80-0xFF 16 16 16 16 16 16 (7) k=0 5. The channel center gain is the response to a constant fullscale input at every output phase. The summation is split into phases because the interpolation of the data insures that only NRCF/LRCF coefficients can be active for any single output. For LRCF = 1, there is only one phase and the channel center gain is the simple sum of all the coefficients, scaled by 2-g. If the channel center gain is not the same for every value of p, some or all of the images of the channel center will be imperfectly rejected by the RCF. -12- Description 7: Reserved (Must Be Written to 0) 6-0: NRCF-1 7: Reserved (Must Be Written to 0) 6-0: ORCF 7-6: Reserved 5-4: Reserved (Must Be Written to 0) 3-0: NRCF/LRCF-1 7-6: RCF Coarse Scale: 00 = 0 dB 01 = -6 dB 10 = -12 dB 11 = -18 dB 5: Reserved (Must Be Written to 0) 4-0: Serial Clock Divider 15-0: Reserved 15-0: Reserved 15-0: Reserved (Must Be Written to 0) 15-0: Reserved (Must Be Written to 0) 15-0: Data Memory (DMEM) 15-0: Coefficient Memory (CMEM) REV. 0 AD6622 CASCASDED INTEGRATOR COMB (CIC) INTERPOLATING FILTER The I and Q outputs of the RCF stage are interpolated in integer factors by two cascaded integrator comb (CIC) filters. The CIC section is separated into three discrete blocks: a fifth order filter (CIC5), a second order filter (CIC2), and a scaling block (CIC Scaling). The CIC5 and CIC2 blocks each exhibit a gain that increases with respect to their interpolation factors, LCIC5 and LCIC2. The product of these gains must be compensated for in a shared CIC Scaling block. 2-CIC_SCALE LCIC5 LCIC2 CIC_SCALE CIC5 CIC2 Figure 13. CIC Data Path CIC Scaling The CIC5 and CIC2 stages have a baseband gain of LCIC54 x LCIC2. The CIC scaling block is used to avoid numeric overflow in the CIC stages. The CIC scale block reduces the signal level without truncation or loss of resolution. The overall gain of the CIC section is given by Equation 9. x LCIC 2 x 2 L x f sin CIC 5 f 1 CIC 5 CIC5( f ) = LCIC 5 f sin L CIC 5 (13) 10 -10 -30 (9) - CIC _ Scale 5 As an example, we will consider an input from the RCF whose bandwidth is 0.141 of the RCF output rate, centered at baseband. Interpolation by a factor of five reveals five images, as shown in Figure 14. -50 dB CIC _ Gain = 4 LCIC 5 The frequency response of the CIC5 can be expressed as follows. The initial 1/LCIC5 factor normalizes for the increased rate, which is appropriate when the samples are destined for a DAC with a zero order hold output. The maximum gain is (LCIC5)4 at baseband, but internal registers peak in response to various dynamic inputs. As long as LCIC5 is confined to 32 or less, there is no possibility of overflow at any register. The value CIC_Scale may range from 0 to 25, and can be independently programmed for each channel at Control Register 0x06. CIC_Scale may be safely calculated according Equation 10 to ensure the net gain through the CIC stages. -70 -90 -110 -130 4 CIC_Scale = ceil (log 2( LCIC 5 x LCIC 2 )) (10) -150 The ceil function is the next highest integer. While this normally constitutes a small loss, it can be recovered in the RCF scaling. Likewise, if the RCF output level is known to be less than full scale, the CIC gain can be increased by reducing CIC_Scale. CIC5 The CIC5 is a fifth order interpolating cascaded integrator comb whose impulse response is completely defined by its interpolation factor, LCIC5. The value L CIC5 -1 can be independently programmed for each channel at location 0x09. While this control register is 8-bits wide, LCIC5 should be confined to the range from 1 to 32 to avoid the possibility of internal overflow for full-scale inputs. The transfer function of the CIC5 is given by the following equations with respect to the CIC5 output sample rate, fSAMP5. 1 - z - L CIC5(z ) = 1 - z -1 -2 -1 0 1 2 Figure 14. Unfiltered CIC Interpolation Image The CIC5 rejects each of the undesired images while passing the image at baseband. The images of a pure tone at channel center (dc) are nulled perfectly, but as the bandwidth increases the rejection is diminished. The lower band edge of the first image always has the least rejection. In this example, the CIC5 is interpolating by a factor of five and the input signal has a bandwidth of 0.141 of the RCF output sample rate. The plot below shows -110 dBc rejection of the lower band edge of the first image. All other image frequencies have better rejection. 10 -10 -30 5 CIC 5 (11) dB -50 This polynomial fraction can be completely reduced as follows, demonstrating a finite impulse response with perfect phase linearity for all values of LCIC5. L CIC 5( z ) = z - k k=0 5 LCIC 5-1 CIC 5-1 = k =1 k j 2 z -1 - e L CIC 5 -70 -90 -110 5 -130 (12) -150 -2 -1 0 1 2 Figure 15. Filtered CIC5 Interpolation Images REV. 0 -13- AD6622 Table II lists maximum bandwidth that will be rejected to various levels for CIC5 interpolation factors from 1 to 32. Figure 15 corresponds to the listing in the -110 dB column and the LCIC5 = 5 row. It is worth noting that the rejection of the CIC5 improves as the interpolation factor increases. Table III. Maximum LCIC2 Limits Table II. CIC5 Alias Protection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -110 dB -100 dB -90 dB -80 dB -70 dB Full 0.101 0.126 0.136 0.141 0.143 0.144 0.145 0.146 0.146 0.147 0.147 0.147 0.147 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 0.148 Full 0.127 0.159 0.170 0.175 0.178 0.179 0.180 0.181 0.182 0.182 0.182 0.183 0.183 0.183 0.183 0.183 0.183 0.183 0.184 0.184 0.184 0.184 0.184 0.184 0.184 0.184 0.184 0.184 0.184 0.184 0.184 Full 0.160 0.198 0.211 0.217 0.220 0.222 0.224 0.224 0.225 0.226 0.226 0.226 0.226 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.227 0.228 Full 0.203 0.246 0.262 0.269 0.272 0.275 0.276 0.277 0.278 0.278 0.279 0.279 0.279 0.280 0.280 0.280 0.280 0.280 0.280 0.280 0.280 0.280 0.280 0.281 0.281 0.281 0.281 0.281 0.281 0.281 0.281 Full 0.256 0.307 0.325 0.333 0.337 0.340 0.341 0.342 0.343 0.344 0.344 0.345 0.345 0.345 0.345 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 0.346 LCIC5 Max LCIC2 1-19 20 21 22 23 24 25 26 27 28 29 30 31 32 256 209 172 143 119 101 85 73 63 54 47 41 36 32 The transfer function of the CIC2 is given by the following equations with respect to the CIC2 output sample rate, fOUT. 1 - z - L CIC 2( z ) = 1 - z -1 2 CIC 2 (14) This polynomial fraction can be completely reduced as follows, demonstrating a finite impulse response with perfect phase linearity for all values of LCIC2. 2 L CIC 2( z ) = z - k = k=0 CIC 2-1 LCIC 2-1 k =1 k j 2 z -1 - e L CIC 2 2 (15) The frequency response of the CIC2 can be expressed as follows. The maximum gain is LCIC2 at baseband. The initial 1/LCIC2 factor normalizes for the increased rate, which is appropriate when the samples are destined for a DAC with a zero order hold output. LCIC2 x f sin f 1 OUT CIC 2( f ) = LCIC2 f sin fOUT CIC2 The CIC2 is a second-order interpolating cascaded integrator comb whose impulse response is completely defined by its interpolation factor, LCIC2. The value LCIC2-1 can be independently programmed for each channel at location 0x08. While this control register is 8 bits wide, LCIC2 should be confined to the ranges shown by the table below according to the interpolation factor of the CIC5. Exceeding the recommended guidelines may result in overflow for input sequences at or near full scale. While relatively small values of LCIC5 allow for the larger overall interpolation factors with minimal power consumption, LCIC5 should be maximized to achieve the best overall image rejection. 2 (16) As an example, we will consider an input from the CIC5 whose bandwidth is 0.0033 of the CIC5 rate, centered at baseband. Interpolation by a factor of five reveals five images, as shown below. -14- REV. 0 AD6622 Table IV lists maximum bandwidth that will be rejected to various levels for CIC2 interpolation factors from 1 to 32. The example above corresponds to the listing in the -110 dB column and the LCIC2 = 5 row. It is worth noting that the rejection of the CIC2 improves as the interpolation factor increases. 10 -10 -30 dB -50 Table IV. CIC2 Alias Protection -70 -90 -110 -130 -150 -2 -1 0 1 2 Figure 16. Unfiltered CIC2 Interpolation Images The CIC2 rejects each of the undesired images while passing the image at baseband. The images of a pure tone at channel center (dc) are nulled perfectly, but as the bandwidth increases the rejection is diminished. The lower band edge of the first image always has the least rejection. In this example, the CIC2 is interpolating by a factor of five and the input signal has a bandwidth of 0.0033 of the CIC5 output sample rate. Figure 17 shows -110 dBc rejection of the lower band edge of the first image. All other image frequencies have better rejection. 10 -10 -30 dB -50 -70 -90 -110 -130 -150 -2 -1 0 1 2 Figure 17. Filtered CIC2 Interpolation Images REV. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -15- -110 dB -100 dB -90 dB -80 dB -70 dB Full 0.0023 0.0029 0.0032 0.0033 0.0034 0.0034 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 0.0035 Full 0.0040 0.0052 0.0057 0.0059 0.0060 0.0061 0.0062 0.0062 0.0062 0.0062 0.0062 0.0062 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 0.0063 Full 0.0072 0.0093 0.0101 0.0105 0.0107 0.0108 0.0109 0.0110 0.0110 0.0110 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0111 0.0112 0.0112 0.0112 0.0112 0.0112 0.0112 0.0112 0.0112 0.0112 Full 0.0127 0.0165 0.0179 0.0186 0.0189 0.0192 0.0193 0.0194 0.0195 0.0195 0.0196 0.0196 0.0196 0.0197 0.0197 0.0197 0.0197 0.0197 0.0197 0.0197 0.0197 0.0197 0.0197 0.0198 0.0198 0.0198 0.0198 0.0198 0.0198 0.0198 0.0198 Full 0.0226 0.0292 0.0316 0.0328 0.0334 0.0338 0.0341 0.0343 0.0344 0.0345 0.0346 0.0346 0.0347 0.0347 0.0347 0.0348 0.0348 0.0348 0.0348 0.0348 0.0348 0.0348 0.0348 0.0349 0.0349 0.0349 0.0349 0.0349 0.0349 0.0349 0.0349 AD6622 PHASE OFFSET 16 16 I DATA FROM CIC5 NCO FREQUENCY WORD 32 D Q 32 ICOS 32 D Q ANGLE TO CARTESIAN CONVERSION 32 PHASE ON OFF AMPLITUDE PN GEN. ON OFF PN GEN. CLK QSIN Q DATA FROM CIC5 Figure 18. NCO Block Diagram NUMERICALLY CONTROLLED OSCILLATOR (NCO) TUNER Each channel has a fully independent tuner. The tuner accepts data from the CIC filter, tunes it to a digital Intermediate Frequency (IF), and passes the result to a shared summation block. The tuner consists of a 32-bit quadrature NCO and a Quadrature Amplitude Mixer (QAM). The NCO serves as a local oscillator and the QAM translates the interpolated channel data from baseband to the NCO frequency. The worst-case spurious signal from the NCO is better than -100 dBc for all output frequencies. The tuner can produce real or complex outputs as requested by the shared summation block. energy. If the phase truncation spurs are small, phase dither will not be effective in reducing them further, but a slight elevation in total error energy will occur. Amplitude Dither In the complex mode, the NCO serves as a quadrature local oscillator running at fCLK/2, capable of producing any frequency between -f CLK /4 and +f CLK /4 with a resolution of fCLK /2 33 (0.0087 Hz for fCLK = 75 MHz). Amplitude dither can also be used to improve spurious performance of the NCO. Amplitude dither is enabled by writing a one to Bit 4 of Channel Register at 0x01. When enabled, amplitude dither can reduce spurs due to truncation at the input to the QAM. If the entire frequency word is close to a fraction that has a small denominator, the spurs due to amplitude truncation will be large and amplitude dither will spread these spurs effectively. Amplitude dither also will increase the total error energy by approximately 3 dB. For this reason amplitude dither should be used judiciously. Phase Offset In the real mode, the NCO serves as a quadrature local oscillator running at fCLK, capable of producing any frequency between -fCLK/2 and +fCLK/2 with a resolution of fCLK/232 (0.017 Hz for fCLK = 75 MHz). The quadrature portion of the output is discarded. Negative frequencies are distinguished from positive frequencies solely by spectral inversion. The phase offset (Channel Register 0x04) adds an offset to the phase accumulator of the NCO. This is a 16-bit register that is interpreted as a 16-bit unsigned integer. Phase offset ranges from 0 to nearly 2 radians with a resolution of /32768 radians. This register allows multiple NCOs to be synchronized to produce sine waves with a known phase relationship. The digital IF is calculated using Equation 17 below. NCO Frequency Update and Phase Offset Update Hold-Off Counters f IF = f NCO x NCO_ frequency 232 (17) where: NCO_frequency is the value written to 0x02, fIF is the desired intermediate frequency, and fNCO is fCLK/2 for complex outputs and fCLK for real outputs. Phase Dither The AD6622 provides a phase dither option for improving the spurious performance of the NCO. Phase dither is enabled by writing a one to Bit 3 of Channel Register 0x01. When phase dither is enabled, spurs due to phase truncation in the NCO are randomized. The choice of whether phase dither is used in a system will ultimately be decided by the system goals and the choice of IF frequency. The 18 most significant bits of the phase accumulator are used by the angle to Cartesian conversion. If the NCO frequency has all zeroes below the 18th bit, then phase dither has no effect. If the fraction below the 18th bit is near a 1/2 or 1/3, etc., of the 18th bit, then spurs will accumulate separated from the IF by 1/2 or 1/3, etc., of the CLK frequency. The smaller the denominator of this residual fraction, the larger the spurs due to phase truncation will be. If the phase truncation spurs are unacceptably high for a given frequency, the phase dither can reduce these at the penalty of a slight elevation in total error The update of both the NCO Frequency and Phase Offset can be synchronized with internal hold-off counters. Both of these counters are 16-bit unsigned integers and are clocked at the master CLK rate. These hold-off counters, used in conjunction with the frequency or phase offset registers, allow Beam Forming and Frequency Hopping. See the Synchronization section of this data sheet for additional details. The NCO phase can also be cleared on Sync (set to 0x0000) by setting Bit 2 of Channel Register 0x01 high. NCO Output Scale The output of the NCO can be scaled in four steps of 6 dB each via Channel Register 0x01, Bits 1-0. Table V is a table of the control scale. The NCO always has loss to accommodate the possibility that both the I and Q inputs may reach full-scale simultaneously, resulting in a 3 dB input magnitude. Table V. Control Scale 0x01 Bit 1 0 0 1 1 -16- 0x01 Bit 0 0 1 0 1 NCO Output Level -6 dB -12 dB -18 dB -24 dB REV. 0 AD6622 SUMMATION BLOCK The summation block of the AD6622 serves to combine the outputs of each channel to create a composite multicarrier signal. The four channels are summed together and the result is then added with the 18-bit wideband input bus (IN[17:0]). The final summation is then driven on the 18-bit wideband output bus (OUT[17:0]) on the rising edge of the high speed clock. If the OEN input is high, this output bus is three-stated. If the OEN input is low, this bus will be driven by the summed data. The OEN is active high to allow the wideband output bus to be connected to other buses without using extra logic. Most other buses (like 374-type registers) require a low output enable, which is opposite the AD6622 OEN, thus eliminating extra circuitry. The wideband output bus may be interpreted as a two's complement number or as an offset binary number as defined by Bit 1 of the Summation Mode Control Register at address 0x000. When this bit is high, the wideband output is in two's complement mode and when it is low it is configured for offset binary output data. The MSB (Bit 17) of the wideband output bus is typically used as a guard bit for the purpose of clipping the wideband output bus when Bit 0 of the Summation Mode Control Register at address 0x000 is high. If clip detection is enabled, Bit 17 of the output bus is not used as a data bit. Instead, Bit 16 will become the MSB and be connected to the MSB of the DAC. Configuring the DAC in this manner gives the summation block a gain of 0 dB. When clip detection is not enabled and Bit 17 is used as a data bit, then the summation block will have a gain of -6.02 dB. There are two data output modes. The first is offset binary. This mode is used only when driving offset binary DACs. Two's complement mode may be used in one of two circumstances. The first is when driving a DAC that accepts two's complement data. The second is when driving another AD6622 in cascade mode. When clipping is enabled, the two's complement mode output bus will clip to 0x0FFFF for output signals more positive than the output can express, and it will clip to 0x10000 for signals more negative than the output can express. In offset binary mode the output bus will clip to 0x1FFFF for output signals more positive than the output can express, and it will clip to 0x00000 for signals more negative than the output can express. out of the system by use of the start hold-off counter. The preceding AD6622 in a cascaded chain can be started two high-speed clock cycles before the following AD6622 is started and the data from each AD6622 will arrive at the DAC on the same clock cycle. In systems where the individual signals are not correlated, this is usually not necessary. The AD6622 is capable of outputting both real and complex data. When in real mode, the QIN input is tied low signaling that all inputs on the wideband input bus are real and that all outputs on the wideband output bus are real. The wideband input bus will be pulled low and no data will be added to the composite signal if this port is unused (not connected). If complex data is desired, there are two ways this can be obtained. The first method is simply to set the QIN input of the AD6622 high and set the wideband input bus low. This allows the AD6622 to output complex data on the wideband output bus. The I data samples would be identified when QOUT is low and the Q data samples would be identified when QOUT is high. The second method of obtaining complex data is to provide a QIN signal that toggles on every rising edge of the high-speed clock. This could be obtained by connecting the QOUT of another AD6622 to QIN. In a cascaded system the QIN of the first AD6622 in the chain would typically be tied high and the QOUT of the first AD6622 would be connected to the QIN of the following part. All AD6622s will synchronize themselves to the QIN input so that the proper samples are always paired and the wideband output bus represents valid complex data samples. Table VII. QIN, QOUT Functionality QIN Wideband Input IN[17:0] Output Data Type OUT[17:0] QOUT Low High Pulsed Real Zero Complex Real Complex Complex Low Pulse Pulse TWO'S COMPLEMENT, CLIPPING DISABLED LOGIC1 QIN OFFSET BIN, CLIPPING ENABLED QOUT QIN OUT [17:0] IN [17:0] AD6622 AD6622 LOGIC0 Table VI. Numerical Data Representation Number Represented Output Representation +Full-Scale Two's Complement -Full-Scale Two's Complement +Full-Scale Offset Binary -Full-Scale Offset Binary 0x0FFFF 0x10000 0x1FFFF 0x00000 The wideband input is always interpreted as an 18-bit two's complement number and is typically connected to the wideband output bus of another AD6622 in order to send more than four carriers to a single DAC. The Output Bus of the proceeding AD6622 should be configured in two's complement mode and clip detection disabled. The 18-bit resolution ensures that the noise and spur performance of the wideband data stream does not become the limiting factor as large numbers of carriers are summed. There is a two-clock cycle latency from the wideband input bus to the wideband output bus. This latency may be calibrated REV. 0 IN [17:0] OUT [16:3] 14-BIT DAC Figure 19. Cascade Operation of Two AD6622s SYNCHRONIZATION Three types of synchronization can be achieved with the AD6622. These are Start, Hop, and Beam. Each is described in detail below. The synchronization is accomplished with the use of a shadow register and a hold-off counter. See Figure 20 for a simplified schematic of the NCO Shadow Register and NCO Freq HoldOff Counter to understand basic operation. Enabling the clock (AD6622 CLK) for the Hold-Off Counter can occur with either a Soft Sync (via the Microport), or a Pin Sync (via the AD6622 sync pin, Pin 62). The functions that include shadow registers to allow synchronization include: 1. Start 2. Hop (NCO Frequency) 3. Beam (NCO Phase Offset) -17- AD6622 Start refers to the start-up of an individual channel, chip, or multiple chips. If a channel is not used, it should be put in the Sleep Mode to reduce power dissipation. Following a hard reset (low pulse on the AD6622 RESET pin), all channels are placed in the Sleep Mode. NCO FREQUENCY REGISTER 32 D Q NCO REGISTER 32 D Q MICROPROCESSOR INTERFACE 16 D Q 32 3. Write the Start bit and the SyncX(s) bit high (External Address 5). 4. This starts the Start Update Hold-Off Counter counting down. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one the Sleep bit of the appropriate channel(s) is set low to activate the channel(s). HOLD-OFF COUNTER 16 D C=1 Start with Pin Sync PL C = 0 A sync pin is provided on the AD6622 to provide the most accurate synchronization, especially between multiple AD6622s. Synchronization of start with an external signal is accomplished with the following method. ENA HOP SYNC START COUNTER START HOLD-OFF 16 D D Q 16 D Q 1. Set the appropriate channels to sleep mode (a hard reset to the AD6622 RESET pin brings all four channels up in sleep mode). 2. Write the Start Update Hold-Off Counter(s) (0x00) to the appropriate value (greater than 1 and less than 216-1). If the chip(s) is not initialized, all other registers should be loaded at this step. NCO PHASE ACCUMULATOR ENA HOP HOLD-OFF Hold-Off Counter delays the start of a channel(s) by its value (number of AD6622 CLKs). The following method is used to synchronize the start of multiple channels via microprocessor control. C=1 SLEEP 1. Set the appropriate channels to sleep mode (a hard reset to the AD6622 RESET pin brings all four channels up in sleep mode). SET PL C = 0 ENA 2. Write the Start Update Hold-Off Counter(s) (0x00) to the appropriate value (greater than 1 and less than 216-1). If the chip(s) is not initialized, all other registers should be loaded at this step. START SYNC EXTERNAL ADDRESS 4 CLK 3. Set the start on pin sync bit and the appropriate sync pin enable high (0x001). RESET PIN 4. When the sync pin is sampled high by the AD6622 CLK, it enables the countdown of the Start Update Hold-Off Counter. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one, the sleep bit of the appropriate channel(s) is set low to activate the channel(s). Figure 20. NCO Shadow Register and Hold-Off Counter Start with No Sync If no synchronization is needed to start multiple channels or multiple AD6622s, the following method can be used to initialize the device. 1. To program a channel, it must first be set to the Program Mode (bit high) and Sleep Mode (bit high) (External Address 4). The Program Mode allows programming of data memory and coefficient memory (all other registers are programmable whether or not in Program Mode). Since no synchronization is used all sync bits are set low (External Address 5). All appropriate control and memory registers (filter) are then loaded. The Start Update Hold-Off Counter (0x00) should be set to 0. 2. Set the appropriate program and sleep bits low (External Address 4). This enables the channel. The channel must have Program and Sleep Mode low to activate a channel. Hop is a jump from one NCO frequency to a new NCO frequency. This change in frequency can be synchronized via microprocessor control or an external sync signal as described below. To set the NCO frequency without synchronization the following method should be used. Set Freq No Hop 1. Set the NCO Freq Hold-Off Counter to 0. 2. Load the appropriate NCO frequency. The new frequency will immediately be loaded to the NCO. Hop with Soft Sync Start with Soft Sync The AD6622 includes the ability to synchronize channels or chips under microprocessor control. One action to synchronize is the start of channels or chips. The Start Update Hold-Off Counter (0x00) in conjunction with the start bit and sync bit (External Address 5) allow this synchronization. Basically the Start Update The AD6622 includes the ability to synchronize a change in NCO frequency of multiple channels or chips under microprocessor control. The NCO Freq Hold-Off Counter (0x03), in conjunction with the hop bit and the sync bit (Ext Address 5), allow this synchronization. Basically the NCO Freq Hold-Off Counter delays the new frequency from being loaded into the NCO by its value (number of AD6622 CLKs). The following method is used to synchronize a hop in frequency of multiple channels via microprocessor control. -18- REV. 0 AD6622 1. Write the NCO Freq Hold-Off (0x03) Counter to the appropriate value (greater than 1 and less then 216-1). 2. Write the NCO Frequency Register(s) to the new desired frequency. 3. Write the hop bit and the sync(s) bit high (Ext Address 5). 4. This starts the NCO Freq Hold-Off Counter counting down. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one, the new frequency is loaded into the NCO. Hop with Pin Sync A sync pin is provided on the AD6622 to provide the most accurate synchronization, especially between multiple AD6622s. Synchronization of hopping to a new NCO frequency with an external signal is accomplished with the following method. 1. Write the NCO Freq Hold-Off Counter(s) (0x03) to the appropriate value (greater than 1 and less than 216-1). 2. Write the NCO Frequency register(s) to the new desired frequency. 3. Set the hop on pin sync bit and the appropriate sync pin enable high (0x001). 4. When the sync pin is sampled high by the AD6622 CLK this enables the countdown of the NCO Freq Hold-Off Counter. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one the new frequency is loaded into the NCO. Beam is a change in phase for a particular channel and can be synchronized with respect to other channels or AD6622s. This change in phase can be synchronized via microprocessor control or an external sync signal as described below. To set the amplitude without synchronization the following method should be used. Set Phase No Beam 1. Set the NCO Phase Offset Update Hold-Off Counter (0x05) to 0. 2. Load the appropriate NCO Phase Offset (0x04). The NCO Phase Offset will be immediately loaded. Beam with Pin Sync A sync pin is provided on the AD6622 to provide the most accurate synchronization, especially between multiple AD6622s. Synchronization of beaming to a new NCO Phase Offset with an external signal is accomplished with the following method. 1. Write the NCO Phase Offset Hold-Off (0x05) counter(s) to the appropriate value (greater than 1 and less than 216-1). 2. Write the NCO Phase Offset register(s) to the new desired phase and amplitude. 3. Set the beam on pin sync bit and the appropriate sync pin enable high (0x001). 4. When the sync pin is sampled high by the AD6622 CLK, it enables the countdown of the NCO Phase Offset Hold-Off Counter. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one, the new phase is loaded into the NCO registers. JTAG INTERFACE The AD6622 supports a subset of IEEE Standard 1149.1 specifications. For additional details of the standard, please see "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE-1149 publication from IEEE. The AD6622 has five pins associated with the JTAG interface. These pins are used to access the on-chip Test Access Port and are listed in Table VIII. Table VIII. JTAG Pin List Name Pin Number Description TRST TCK TMS TDI TDO 100 101 106 108 107 Test Access Port Reset Test Clock Test Access Port Mode Select Test Data Input Test Data Output The AD6622 supports four op codes as shown in Table IX. These instructions set the mode of the JTAG interface. Table IX. JTAG Op Codes Beam with Soft Sync The AD6622 includes the ability to synchronize a change in NCO phase of multiple channels or chips under microprocessor control. The NCO Phase Offset Update Hold-Off Counter, in conjunction with the beam bit and the sync bit (Ext Address 5), allow this synchronization. Basically the NCO Phase Offset Update Hold-Off Counter delays the new phase from being loaded into the NCO/RCF by its value (number of AD6622 CLKs). The following method is used to synchronize a beam-in phase of multiple channels via microprocessor control. 1. Write the NCO Phase offset Update Hold-Off Counter (0x05) to the appropriate value (greater than 1 and less then 216-1). 2. Write the NCO Phase Offset Register(s) to the new desired phase and amplitude. 3. Write the beam bit and the sync(s) bit high (External Address 5). 4. This starts the NCO Phase Offset Update Hold-Off counter counting down. The counter is clocked with the AD6622 CLK signal. When it reaches a count of one, the new phase is loaded into the NCO. REV. 0 Instruction Op Code IDCODE BYPASS SAMPLE/PRELOAD EXTEST 10 11 01 00 The Vendor Identification Code can be accessed through the IDCODE instruction and has the following format. Table X. JTAG ID String MSB Version Part Number Manufacturing ID # LSB Mandatory 000 0010 0111 1000 0000 000 1110 0101 1 A BSDL file for this device is available from Analog Devices, Inc. Contact Analog Devices Inc. for more information. -19- AD6622 SCALING Proper scaling of the wideband output is critical to maximize the spurious and noise performance of the AD6622. A relatively small overflow anywhere in the data path can cause the spurious free dynamic range to drop precipitously. Scaling down the output levels also reduces dynamic range relative to an approximately constant noise floor. A well-balanced scaling plan at each point in the signal path will be rewarded with optimum performance. The scaling plan can be separated into two parts: multicarrier scaling and single-carrier scaling. Multicarrier Scaling An arbitrary number of AD6622s can be cascaded to create a composite digital IF with many carriers. As the number of carriers increases, the peak-to-rms ratio of the composite digital IF will increase as well. It is possible and beneficial to limit the peak-torms ratio through careful frequency planning and controlled phase offsets. Nevertheless, in most cases with a large number of carriers, the worst-case peak is an unlikely event. The AD6622 immediately preceding the DAC can be programmed to clip rather than wrap around (see the Summation Block description). For a large number of carriers, a rare but finite chance of clipping at the AD6622 wideband output will result in superior dynamic range compared to lowering each carrier level until clipping is impossible. This will also be the case for most DACs. Through analysis or experimentation, an optimal output level of individual carriers can be determined for any particular DAC. Single-Carrier Scaling Once the optimal power level is determined for each carrier, one must determine the best way to achieve that level. The maximum SNR can be achieved by maximizing the intermediate power level at each processing stage. This can be done by assuming the proper level at the output and working backwards along the signal path: Summation, NCO, CIC, and finally, RCF. The summation block is intended to combine multiple carriers, with each carrier at least 6 dB below full scale. For this configuration, the AD6622 driving the DAC should have clip detection enable. OUT17 becomes a clip indicator that reports clipping in both polarities. If the DAC requires offset binary outputs, the internal offset binary conversion should be enabled as well. Any preceding cascaded AD6622s should disable clip detection and offset binary conversion. The IN17-IN0 of the first AD6622 in the cascade should be grounded. See the Summation Block section for details. In this configuration, intermediate OUT17s will serve as guard bits that allow intermediate sums to exceed full scale. As long as the final output does not exceed 6 dB over full scale, the clip detector will perform correctly. If a single carrier needs to exceed -6 dB full scale, hardwired scaling can be accomplished according to the table below. This is most useful when the AD6622 is processing a Single Wideband Carrier such as UMTS or CDMA 2000. Table XI. Output Bit Scaling Max SingleCarrier Level -12.04 dB -6.02 dB 0 dB +6.02 dB +12.04 dB +18.06 dB +24.08 dB Connect to DAC MSB OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 Clip Detect N/A +Only +Only +Only +Only +Only Offset Binary Compensation Internal Internal 0x18000 0x1C000 0x1E000 0x1F000 0x1F800 The NCO/Tuner is equipped with an output scalar that ranges from -6.02 dB to -24.08 dB below full scale, in 6.02 dB steps. See the NCO/Tuner section for details. The best SNR will be achieved by maximizing the input level to the NCO and using the largest possible NCO attenuation. For example, to achieve an output level -20 dB below full scale, one should set the CIC output level to -1.94 dB below full scale and attenuate by -18.06 dB in the NCO. The CIC is equipped with an output scalar that ranges from 0 dB to -150.51 dB below full scale in 6.02 dB steps. This large attenuation is necessary to compensate for the potentially large gains associated with CIC interpolation. See the CIC section for details. For example to achieve an output level of -1.94 dB below full scale, with a CIC5 interpolation of 27 (114.51 dB gain) and a CIC2 interpolation of 3 (9.54 dB gain), one should set the CIC_Scale to 20 and the RCF output level to -5.59 dB below full scale. (18) -1.94 - 9.54 - 114.51 + 20 x 6.02 = -5.59 The RCF is equipped with an output scalar that ranges from 0 dB to -18.06 dB below full scale in 6.02 dB steps. This attenuation can be used to compensate for filter gain in the RCF. For example, if the desired RCF output is -5.59 dB and the maxim gain of the RCF coefficients is 11.04 dB, then the RCF_Coarse_Scale should be set to two and the coefficients should be scaled so that the largest coefficient is -4.59 dB below full scale. The largest possible gain of the RCF coefficients is when the largest coefficient of the impulse response is normalized to one. This means that all of the coefficients are as large as possible so the sum of the coefficients are as large as possible. This maximum gain will determine the RCF_Coarse_Scale, which should be used to make the total RCF gain between 0 dB and -6.02 dB. After the RCF_Coarse_Scale is chosen, the coefficients can be rescaled, as in the example, to set the total RCF gain to a desired level. See the RCF section for additional information. (19) -5.59 - 11.04 + 2 x 6.02 = -4.59 Finally, as described in the RCF section, there may be a worstcase peak of a phase that is larger than the channel center gain. In the preceding example, if the worst-case to channel center ratio is larger than 4.59 dB (potentially overflowing the RCF), the RCF_Coarse_Scale should be reduced by one and the CIC_Scale should be increased by one. In the preceding example, if the worstcase to channel center ratio is larger than 5.59 dB (potentially overflowing the RCF and CIC), the RCF_Coarse_Scale should be reduced by one and the NCO_Output_Scale should be increased by one. MICROPORT INTERFACE The Microport interface is the communications port between the AD6622 and the host controller. There are two modes of bus operation: Intel Nonmultiplexed Mode (INM), and Motorola Nonmultiplexed Mode (MNM), which is set by hard wiring the MODE pin to either ground or supply. The mode is selected based on the use of the Microport control lines (DS or RD, DTACK or RDY, R/W or WR) and the capabilities of the host processor. See the timing diagrams for details on the operation of both modes. The External Memory Map provides data and address registers to read and write the extensive control registers in the Internal Memory Map. The control registers access global chip functions and multiple control functions for each independent channel. -20- REV. 0 AD6622 Microport Control All accesses to the internal registers and memory of the AD6622 are accomplished indirectly through the use of the microprocessor port external registers shown in Table XII. Accesses to the External Registers are accomplished through the 3-bit address bus (A[2:0]) and the 8-bit data bus (D[7:0]) of the AD6622 (Microport). External Address [3:0] provides access to data read from or written to the internal memory (up to 32 bits). External Address [0] is the least significant byte and External Address [3] is the most significant byte. External Address [4] controls the resets of each channel. External Address [5] controls the sync status of each channel. External Address [7:6] determines the Internal Address selected and whether this address is incremented after subsequent reads and/or writes to the internal registers. EXTERNAL MEMORY MAP The External Memory Map is used to gain access to the Internal Memory Map described below. External Address [7:6] sets the Internal Address to which subsequent reads or writes will be performed. The top two bits of External Address [7] allow the user to set the address to autoincrement after reads, writes, or both. All internal data words have widths that are less than or equal to 32 bits. Accesses to External Address [0] trigger accesses to the AD6622's internal memory map. Thus during writes to the internal registers, External Address [0] must be written last to ensure all data is transferred. Reads are the opposite in that External Address [0] must be the first data register read (after setting the appropriate internal address) to initiate an internal access. External Address [5:4] reads and writes are immediately transferred to internal control registers. External Address [4] is the reset register. The reset bits can be set collectively by the address. The reset bits can be cleared by operation of start syncs (described below). External Address [5] is the sync register. These bits are write only. There are three types of syncs: start, hop, and beam. Each of these can be sent to any or all of the four channels. For example, a write of X0010100 would issue a start sync to Channel C only. A write of X1101111 would issue a beam sync and a hop sync to all channels. The internal address bus is 11 bits wide and the internal data bus is 32 bits wide. External Address 7 is the Chan (Channel) and stores the upper three bits of the address space in Chan[2:0]. Chan[7:6] define the autoincrement feature. If Bit 6 is high, the internal address in incremented after an internal read. If Bit 7 is high, the internal address is incremented after an internal write. If both bits are high, the internal address in incremented after either a write or a read. This feature is designed for sequential access to internal locations. External Address 6 is the Addr (Address) and stores the lower eight bits of the internal address. External Addresses 3 through 0 store the 32 bits of the internal data. All internal accesses are two clock cycles long. bits of the internal address (it does not matter if the Addr is written before the Chan as long as both are written before the internal access). Since the data width of the internal address is 16 bits, only Data Register 1 and Data Register 0 are needed. Data Register 1 must be written first because the write to Data Register 0 triggers the internal access. Data Register 0 must always be the last register written to initiate the internal write. Reading from the Microport is accomplished in a similar manner. The internal address is first written. A read from Data Register 0 activates the internal read, thus register 0 must always be read first to initiate an internal read. This provides the 8 LSBs of the internal read through the Microport (D[7:0]). Additional bytes are then read by changing the external address (A[2:0]) and performing additional reads. If Data Register 3 (or any other) is read before Data Register 0, incorrect data will be read. Data Register 0 must be read first in order to transfer data from the core memory to the external memory locations. Once data register is read, the remaining locations may be examined in any order. The Microport of the AD6622 allows for multiple accesses while CS is held low (CS can be tied permanently low if the Microport is not shared with additional devices). The user can access multiple locations by pulsing the WR or RD line and changing the contents of the external 3-bit address bus. Access to the external registers of Table XII is accomplished in one of two modes using the CS, RD, WR, and MODE inputs. The access modes are Intel Nonmultiplexed Mode and Motorola Nonmultiplexed Mode. These modes are controlled by the MODE input (MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR control the access type for each mode. Intel Nonmultiplexed Mode (INM) MODE must be tied low to operate the AD6622 Microport in INM Mode. The access type is controlled by the user with the CS, RD (DS), and WR (R/W) inputs. The RDY (DTACK) signal is produced by the Microport to communicate to the user the Microport is ready for an access. RDY (DTACK) goes low at the start of the access and is released when the internal cycle is complete. See the timing diagrams for both the read and write modes in the specifications. Motorola Nonmultiplexed Mode (MNM) MODE must be tied high to operate the AD6622 microprocessor in MNM mode. The access type is controlled by the user with the CS, DS (RD), and R/W (WR) inputs. The DTACK (RDY) signal is produced by the Microport to acknowledge the completion of an access to the user. DTACK (RDY) goes low when an internal access is complete and then will return high after DS (RD) is deasserted. See the timing diagrams for both the read and write modes in the Specifications. The DTACK pin is configured as an open drain so that multiple devices may be tied together at the microprocessor/microcontroller without contention. Writing to an internal location with a data width of 16 bits is achieved by first writing the upper three bits of the address to Bits 2 through 0 of the Chan. (Bits 7 and 6 of the Chan are written to determine whether or not the auto increment feature is enabled.) The Addr is then written with the lower eight REV. 0 -21- AD6622 Table XII. External Memory Map External Address 7: Chan 6: Addr 5: Sync 4: Reset 3: Byte3 2: Byte2 1: Byte1 0: Byte0 D7 D6 D5 External Data D4 D3 D2 D1 D0 Wrinc IA7 Rdinc IA6 Beam Prog C ID30 ID22 ID14 ID6 IA5 Hop Prog B ID29 ID21 ID13 ID5 IA4 Start Prog A ID28 ID20 ID12 ID4 IA10 IA2 Sync C Sleep C ID26 ID18 ID10 ID2 IA9 IA1 Sync B Sleep B ID25 ID17 ID9 ID1 IA8 IA0 Sync A Sleep A ID24 ID16 ID8 ID0 Prog D ID31 ID23 ID15 ID7 IA3 Sync D Sleep D ID27 ID19 ID11 ID3 External Address 7 Upper Address Register (Chan) External Address 4 Reset Sets the three most significant bits of the internal address, effectively selecting channels 1, 2, 3, or 4 (D2:D0). The autoincrement of read and write are also set (D7:D6). Bits in this register determine how the chip is programmed and enables the channels. The program bits (D7:D4) must be set high to allow programming of CMEM and DMEM for each channel. Sleep bits (D3:D0) are used to activate or sleep channels. These can be used manually by the user to bring up a channel by simply writing the required channel high. These bits can also be used in conjunction with the Start and Sync signals available in External Address 5 to synchronize the channels. See the Synchronization section of the data sheet for detailed explanation of different modes. External Address 6 Lower Address Register (Addr) Sets the internal address 8 LSBs (D7:D0). External Address 5 Sync This register is read only. Bits in this address control the synchronization of the AD6622 channels. If the user intends to bring up channels with no synchronization requirements, then all bits of this register should be written low. Two types of sync signals are available with the AD6622. The first is Soft Sync. Soft Sync is software synchronization enabled through the Microport. The second synchronization method is Pin Sync. Pin Sync is enabled by a signal applied to the sync pin (Pin 62). See the Synchronization section of the data sheet for detailed explanations of the different modes. External Address 3:0 (Data Bytes) These bits set the internal address to be accessed for a read or write. -22- REV. 0 AD6622 INTERNAL CONTROL REGISTERS AND ON-CHIP RAM Listed below is the mapping of internal AD6622 registers. Table XIII. Internal Memory Map Address Bit Width Name Notation Description Common Function Registers (Not Associated with a Particular Channel) 0x000 8 Summation MODE Control 0x001 8 Sync MODE Control 0: Clip Wideband Output 1: Offset Binary Wideband Output 2: Reserved, Must Be Set High 3-7: Reserved, Should Be Set Low 0: Ch. A Sync Pin Enable 1: Ch. B Sync Pin Enable 2: Ch. C Sync Pin Enable 3: Ch. D Sync Pin Enable 4: Start on Pin Sync 5: Hop on Pin Sync 6: Beam Steer on Pin Sync 7: First Sync Only Channel Function Registers (0x1XX = Ch. A, 0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D ) 0x100 0x101 16 8 Start Update Hold-Off Counter NCO Control 0x102 0x103 0x104 0x105 0x106 32 16 16 16 8 NCO Frequency NCO Freq Hold Off NCO Phase Offset NCO Phase Hold Off CIC Scale 0x107 0x108 0x109 0x10A 8 8 8 8 Reserved CIC2 Interpolation-1 CIC5 Interpolation-1 RCF Coefficient Count NRCF-1 0x10B 8 RCF Coefficient Offset ORCF 0x10C 8 Channel MODE Control 1 NRCF/LRCF-1 0x10D 8 Channel MODE Control 2 0x10E 0x10F 0x110 0x111 0x112-0x11F 0x120-0x13F 0x140-0x17F 0x180-0x1FF 16 16 16 16 16 16 16 Reserved Reserved Reserved Data Memory Reserved Coefficient Memory Start Update Hold Off Counter 1-0: Ch. A NCO Output Scale 2: Ch. A NCO Clear Phase Accum on Sync 3: Ch. A NCO Phase Dither Enable 4: Ch. A NCO Amp Dither Enable 7-5: Reserved Ch. A NCO Frequency Value Ch. A NCO Frequency Update Hold-Off Ctr Ch. A NCO Phase Offset Ch. A NCO Phase Offset Update Hold-Off Ctr 4-0: Ch. A CIC Scale 7-5: Reserved 7-0: Reserved Ch. A CIC2 Interpolation Factor-1 Ch. A CIC5 Interpolation Factor-1 6-0: Ch. A RCF Coefficient Count, N RCF-1 7: Reserved 6-0: Ch. A RCF Coefficient Offset 7: Reserved 3-0: Ch. A NRCF/LRCF-1 5-4: Ch. A Input Format: 00 = FIR 6: Reserved 7: Reserved 4-0: Ch. A Serial Clock Divider 5: Ch. A Phase EQ Enable 7-6: Ch. A RCF Coarse Scale: 00 = 0 dB 01 = -6 dB 10 = -12 dB 11 = -18 dB 15-0: Reserved 15-0: Reserved Reserved Reserved Reserved Ch. A Data Memory Reserved Ch. A Coefficient Memory Channel B Channel C Channel D Ch. B Registers (Organized as Ch. A Above) Ch. C Registers (Organized as Ch. A Above) Ch. D Registers (Organized as Ch. A Above) Additional Channels 0x200-0x2FF 0x300-0x3FF 0x400-0x4FF REV. 0 Various Various Various -23- AD6622 (0x000) Summation Mode Control (0xn05) NCO Phase Offset Update Hold-Off Counter Controls functions in the summation block of the AD6622. When set high, Bit 0 causes the output data to be clipped (no wraparound) when overrange of the output occurs. When Bit 0 is low, overrange will result in wraparound. When set low, Bit 1 formats the output data as two's complement. Bit 1 set high will format output data as offset binary. The Hold-Off Counter is used to synchronize the change of NCO phases. See the Synchronization section of the data sheet for detailed explanation. If no synchronization is required, this register should be set to 0. (0xn06) CIC Scale Bits 5:0 set the CIC scaling per the equation below. (0x001) Sync Mode Control 4 CIC _ Scale = ceil (log2 ( LCIC 5 x LCIC 2 )) (21) Bits 3-0 when high enable synchronization of these channels. See the Synchronization section of the data sheet for detailed explanation. See CIC section of the data sheet for details. Bits 7:6 are reserved and should be set to 0. Channel Function Registers (0xn07) Reserved The following registers are channel-specific. "0x" denotes that these values are represented as hexadecimal numbers. "n" represents the specified channel. Valid channels are n = 1, 2, 3, and 4. This register is reserved and should be set to 0. (0xn00) Start Update Hold-Off Counter The Start Update Hold-Off Counter is used to synchronize start up of AD6622 channels and can be used to synchronize multiple chips. The Start Update Hold-Off Counter is clocked by the AD6622 CLK (master clock). See the Synchronization section of the data sheet for detailed explanation. If no synchronization is required, this register should be set to 0. (0xn01) NCO Control Bit 1:0 set the NCO scaling per the Table XIV. 0x01 Bit 0 NCO Output Level 0 0 1 1 0 1 0 1 -6 dB -12 dB -18 dB -24 dB This register sets the interpolation rate for the CIC2 filter stage (unsigned integer). The programmed value is the CIC2 Interpolation - 1. Maximum interpolation is limited by the CIC scaling available (See CIC section of the data sheet). (0xn09) CIC5 Interpolation - 1 This register sets the interpolation rate for the CIC5 filter stage (unsigned integer). The programmed value is the CIC5 Interpolation - 1. Maximum interpolation is limited by the CIC scaling available (See CIC section of the data sheet). (0xn0A) Number of RCF Coefficients - 1 This register sets the number of RCF Coefficients and is limited to a maximum of 128. The programmed value is the number of RCF Coefficients - 1. Table XIV. Control Scale 0x01 Bit 1 (0xn08) CIC2 Interpolation - 1 (0xn0B) RCF Coefficient Offset This register sets the offset for RCF Coefficients and is normally set to 0. It can be viewed as a pointer that selects the portion of the CMEM used when computing the RCF filter. This allows multiple filters to be stored in the coefficient memory space, selecting the appropriate filter by setting the offset. Bit 2, when high, clears the NCO phase accumulator to 0 on either a Soft Sync or Pin Sync (see Synchronization for details). (0xn0C) Channel Mode Control 1 Bits 3:0 set NRCF/LRCF-1. Bit 3, when high, enables NCO phase dither. Bit 4, when high, enables NCO amplitude dither. Bits 7:5 are reserved and should be written low. Bits 5:4 set the channel input format as shown below. Table XV. Filter Mode (0xn02) NCO Frequency This register is a 32-bit unsigned integer that sets the NCO Frequency. The NCO Frequency contains a shadow register for synchronization purposes. The shadow can be read back directly, the NCO Frequency cannot. f NCOFrequency = 232 x channel CLK (20) (0xn03) NCO Frequency Update Hold-Off Counter The Hold-Off Counter is used to synchronize the change of NCO frequencies. See the Synchronization section of the data sheet for detailed explanation. If no synchronization is required, this register should be set to 0. Bit 5 Bit 4 Input Mode 0 0 1 1 0 1 0 1 FIR Reserved Reserved Reserved Bit 6 Reserved. Bit 7 Reserved. (0xn0D) Channel Mode Control 2 Bits 4:0 set the SCLKDIVIDER which determines the serial clock frequency based on the following equation. (0xn04) NCO Phase Offset This register is a 16-bit unsigned integer that is added to the phase accumulator of the NCO. This allows phase synchronization of multiple channels of the AD6622(s). See the Synchronization section of the data sheet for details. The NCO Phase Offset contains a shadow register for synchronization purposes. The shadow can be read back directly, the NCO Phase Offset cannot. -24- f SCLK = CLK 2 x (SCLK DIVIDER + 1) (22) REV. 0 AD6622 Bit 5 Reserved. Must be set low. Bits 7:6 set the RCF Coarse Scale as shown below. READ PSEUDOCODE Void Read_Micro(ext_address); Main() Table XVI. RCF Scaling Bit 7 Bit 6 RCF Coarse Scale 0 0 1 1 0 1 0 1 0 dB -6 dB -12 dB -18 dB (0xn0E) Reserved (0xn0F) Reserved (0xn10) Reserved (Must Be Written to 0) (0xn11) Reserved (Must Be written to 0) (0xn12-0xn1F) Reserved (0xn20-0xn3F) Data Memory This group of registers contain the RCF Filter Data. See the RCF section of the data sheet for additional detail. (0xn40-0xn7F) Reserved (0xn80-0xnFF) Coefficient Memory This group of registers contain the RCF Filter Coefficients. See the RCF section of the data sheet for additional detail. WRITE PSEUDOCODE Void Write_Micro(ext_address, int data); { /* This code shows the reading of the NCO frequency register using the Read_Micro function defined above. The variable address is the External Address A[2:0] Internal Address = 0x102, channel 1 */ /*Holding registers for NCO byte wide access data*/ int d3, d2, d1, d0; /*NCO frequency word (32 bits wide)*/ /*write Chan */ Write_Micro(7, 0x01); /*write Addr*/ Write_Micro(6,0x02); /*read Byte 0, all data is moved from the Internal Registers to the interface registers on this access, thus Byte 0 must be accessed first for the other Bytes to be valid*/ d0=Read_Micro(0) & 0xFF; /*read Byte 1*/ d1=Read_Micro(1) & 0xFF; /*read Byte 2*/ d2=Read_Micro(2) & 0xFF; /*read Byte 0 */ d3=Read_Micro(3) & 0xFF; } Main() { /* This code shows the programming of the NCO frequency register using the Write_Micro function defined above. The variable address is the External Address A[2:0] and data is the value to be placed in the external interface register. Internal Address = 0x102, channel 1 */ /*Holding registers for NCO byte wide access data*/ int d3, d2, d1, d0; /*NCO frequency word (32 bits wide)*/ NCO_FREQ=0x1BEFEFFF; /*write Chan */ Write_Micro(7, 0x01); /*write Addr */ Write_Micro(6,0x02); /*write Byte 3*/ d3=(NCO_FREQ & 0xFF000000)>>24; Write_Micro(3,d3); /*write Byte 2*/ d2=(NCO_FREQ & 0xFF0000)>>16; Write_Micro(2,d2); /*write Byte 1*/ d1=(NCO_FREQ & 0xFF00)>>8; Write_Micro(1,d1); /*write Byte 0, Byte 0 is written last and causes an internal write to occur*/ d0=NCO_FREQ & 0xFF; Write_Micro(0,d0); } REV. 0 APPLICATIONS The AD6622 provides considerable flexibility for the control of the synchronization, relative phasing, and scaling of the individual channel inputs. Implementation of a multichannel transmitter invariably begins with an analysis of the output spectrum that must be generated. DIGITAL-TO-ANALOG CONVERTER (DAC) SELECTION The selection of a high-performance DAC depends on a number of factors. The dynamic range of the DAC must be considered from a noise and spectral purity perspective. The 14-bit AD9754 and AD9772 are the best choices for overall bandwidth, noise, and spectral purity. In order to minimize the complexity of the analog interpolation filter which must follow the DAC, the sample rate of the master clock is generally set to at least three times the maximum analog frequency of interest. In the case where a 15 MHz band of interest is to be up-converted to RF, the lowest frequency might be 5 MHz and the upper band edge at 20 MHz (offset from dc to afford the best image reject filter after the first digital IF). The minimum sample rate would be set to 75 MSPS. Consideration must also be given to data rate of the incoming data stream, interpolation factors, and the clock rate of the DSP. -25- AD6622 Time Restriction MULTIPLE TSP OPERATION Each of the four Transmit Signal Processors (TSPs) of the AD6622 can adequately reject the interpolation images of narrow bandwidth carriers such as AMPS, IS-136, GSM, EDGE, and PHS. Wider bandwidth carriers such as IS-95 and UMTS require a coordinated effort of multiple processing channels. L N RCF min , 16 x LRCF , 128 2 This section demonstrates how to coordinate multiple TSPs to create wider bandwidth channels without sacrificing image rejection. As an example, a UMTS carrier is modulated using four TSPs (an entire AD6622). The same principals can be applied to different designs using more or fewer TSPs. This section does not explore techniques for using multiple TSPs to solve problems other than Serial Port or RCF throughput. Designing filter coefficients and control settings for deinterleaved TSPs is no harder than designing a filter for a single TSP. For example, if four TSPs are to be used, simply divide the input data rate by four and generate the filter as normal. For any design, a better filter can always be realized by incrementing the number of TSPs to be used. When it is time to program the TSPs, only two small differences must be programmed. First each channel is configured with exactly the same filter, scalars, modes and NCO frequency. Since each channel receives data at 1/4 the data rate and in a staggered fashion, the Start Hold-Off Counters must also be staggered (see Programming Multiple TSPs section below). Second, the phase offset of each NCO must be set to match the demultiplexed ratio (1/4 in this example). Thus the phase offset should be set to 90 degrees (16384, which is 1/4 of a 16-bit register). Determining the Number of TSPs to Use There are three limitations of a single TSP that can be overcome by deinterleaving an input stream into multiple TSPs: Serial Port bandwidth, the time restriction to the RCF impulse response length (NRCF), and the DMEM restriction to NRCF. If the input sample rate is faster than the Serial Port can accept data, the data can be deinterleaved into multiple Serial Ports. Recalling from the Serial Port description, the SCLK frequency (fSCLK) is determined by the equation below. To minimize the number of processing channels, SCLKDIVIDER should be set as low as possible to get the highest fSCLK that the serial data source can accept. f SCLK = fCLK 2 x (SCLK DIVIDER + 1) (23) (25) DMEM Restriction where: L = LRCF x LCIC5 x LCIC2 = N TSP x fCLK f IN Deinterleaving the input data into multiple TSPs will extend the time restriction and may possibly extend the DMEM restriction, but will not extend the CMEM restriction. Deinterleaving the input stream to multiple TSPs divides the input sample rate to each TSP by the number of TSPs used (NTSP). To keep the output rate fixed, L must be increased by a factor of NCH, which extends the time restriction. This increase in L may be achieved by increasing any one or more of LRCF, LCIC5, or LCIC2 within their normal limits. Achieving a larger L by increasing LRCF instead of LCIC5 or LCIC2, will relieve the DMEM restriction as well. In a UMTS example, NTSP = 4, fCLK = 61.44 MHz, and fIN = 3.84 MHz, resulting in L = 64. Factoring L into LRCF = 8, LCIC = 8, and LCIC2 = 1, results in a maximum NRCF = 32 due to the time restriction. Figure 22 shows an example RCF impulse response that has a frequency response as shown in Figure 23 from 0 Hz to 7.68 MHz (fIN x LRCF/NTSP). The composite RCF and CIC frequency response is shown in Figure 24, on the same frequency scale. This figure demonstrates a good approximation to a root-raised-cosine with a roll-off factor of 0.22, a pass-band ripple of 0.1 dB, and a stopband ripple better than -65 dB until the lobe of the first image which peaks at -50 dB about 5.6 MHz from the carrier center. This lobe could be reduced by shifting more of the interpolation towards the RCF, but that would sacrifice near-in performance. As shown, the first image can easily be rejected by an analog filter further up the signal path. Scaling must be considered as normal with an interpolation factor of L, to guarantee no overflow in the RCF, CIC, or NCOs. The output level at the summation port should be calculated using an interpolation factor of L/NTSP. Programming Multiple TSPs A minimum of 32 SCLK cycles are required to accept an input sample, so the minimum number of TSPs (NTSP) due to limited Serial Port bandwidth is a function of the input sample rate (fIN), as shown by the equation below. 32 x f IN NTSP ceil fSCLK CMEM Restriction (24) For a sample UMTS system, we will assume fCLK = 61.44 MHz, and the serial data source can drive data at 30.72 MBPS (SCLKDIVIDER = 0). To achieve fIN = 3.84 MHz, the minimum NTSP is 4. (This is TSP channels, not TSP ICs.) Multiple TSPs are also required if the RCF does not have enough time or DMEM space to calculate the required RCF filter. Recalling the maximum NTAPS equation from the RCF description, are three restrictions to the RCF impulse response length, NRCF. Configuring the TSPs for deinterleaved operation is straightforward. All of the Channel Registers and CMEM of each TSP are programmed identically, except the Start Hold-Off Counters and NCO Phase Offset. In order to separate the input timing to each TSP, the HoldOff Counters must be used to start each TSP successively in response to a common Start SYNC. The Start SYNC may originate from the SYNC pin or the Microport. Each subsequent TSP must have a Hold-Off Counter value L/NTSP larger than its predecessor's. If the TSPs are located on cascaded AD6622s, the Hold-Off Counters of the upstream device should be incremented by an additional one. In the UMTS example, L = 64 and NTSP = 4, so in order to respond as quickly as possible to a Start SYNC, the Hold-Off Counter values should be 1, 17, 33, and 49. -26- REV. 0 AD6622 Driving Multiple TSP Serial Ports 10 When properly configured, the AD6622 will drive each SDFS out of phase. Each new piece of data should be driven only into the TSP that pulses its SDFS pin at that time. RAM COEFFICIENT FILTER 0 -10 -20 In the UMTS example, L = 64 and NTSP = 4, so each serial port need only accept every 4th input sample. Each serial port is shifting at peak capacity, so sample 1, 2, and 3 begin shifting into Serial Ports B, C, and D before Sample 0 is completed into Serial Port A. dBc -30 -40 -50 -60 -70 SDFSA SDFSB 0 -80 4 5 1 -90 SDFSC 6 2 SDFSD -100 0 7 3 8.196MSPS 65.536MSPS RAM I COEF Q CIC NCO FILTER 1.024 MCPS 32 -20 6000 7000 8000 HCIC(f) ( LEVEL ) dB -30 -40 5 SPEC( f ) -50 dBc 8.196MSPS 65.536MSPS RAM I CIC NCO COEF Q FILTER 32 5000 -10 SUMMATION 32 DATA REFORMATTER 4.096 MCPS 4000 0 AD6622 1.024 MCPS 3000 Figure 24. Typical FIR Frequency Response for WBCDMA 8.196MSPS 65.536MSPS RAM I COEF Q CIC NCO FILTER 32 2000 kHz Figure 21. SDFS Timing for WBCDMA 1.024 MCPS 1000 65.536 MSPS -60 -70 DAC -80 dB(AD6624(f)) -90 -100 -110 8.196MSPS 65.536MSPS RAM I CIC NCO COEF Q FILTER 1.024 MCPS 32 -120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 f MHz Figure 25. Typical Composite Frequency Response for WBCDMA COMPLEX SIGNAL 32 BITS (16 I, 16 Q) REAL OR IMAGINARY SIGNAL Figure 22. Block Diagram for WBCDMA THERMAL MANAGEMENT The power dissipation of the AD6622 is primarily determined by three factors: the clock rate, the number of channels active, and the distribution of interpolation rates. The faster the clock rate the more power dissipated by the CMOS structures of the AD6622; the more channels active, the higher the overall power of the chip. Low interpolation rates in the CIC stages (CIC5, CIC2) results in higher power dissipation. All these factors should be analyzed as each application has different thermal requirements. 1.0 0.5 COEF - J 0 0 5 10 15 20 25 30 The AD6622 128-lead MQFP is specially designed to provide excellent thermal performance. To achieve the best performance, the power and ground leads should be connected directly to planes on the PC board. This provides the best thermal transfer from the AD6622 to the PC board. Figure 23. Typical Impulse Response for WBCDMA REV. 0 -27- AD6622 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.685 (17.40) 0.669 (17.00) 0.555 (14.10) 0.547 (13.90) 0.134 (3.40) MAX 0.041 (1.03) 0.031 (0.78) C3772-8-5/00 (rev. 0) 00968 128-Lead MQFP (Metric Quad Flatpack) (S-128A) 128 1 103 102 SEATING PLANE 0.791 (20.10) 0.783 (19.90) TOP VIEW (PINS DOWN) 0.921 (23.40) 0.906 (23.00) 0.003 (0.08) MAX 0.010 (0.25) MIN 38 39 0.020 (0.50) BSC 0.011 (0.27) 0.007 (0.17) PRINTED IN U.S.A. 0.110 (2.80) 0.102 (2.60) 65 64 -28- REV. 0