For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1901/MAX1902/MAX1904 are buck-topology,
step-down, switch-mode, power-supply controllers that
generate logic-supply voltages in battery-powered sys-
tems. These high-performance, dual/triple-output devices
include on-board power-up sequencing, power-good sig-
naling with delay, digital soft-start, secondary winding
control, low dropout circuitry, internal frequency-compen-
sation networks, and automatic bootstrapping.
Up to 97% efficiency is achieved through synchronous
rectification and Maxim’s proprietary Idle Mode™ control
scheme. Efficiency is greater than 80% over a 1000:1
load-current range, which extends battery life in system
suspend or standby mode. Excellent dynamic response
corrects output load transients within five clock cycles.
Strong 1A on-board gate drivers ensure fast external N-
channel MOSFET switching.
These devices feature a logic-controlled and synchroniz-
able, fixed-frequency, pulse-width modulation (PWM)
operating mode. This reduces noise and RF interference
in sensitive mobile communications and pen-entry appli-
cations. Asserting the SKIP pin enables fixed-frequency
mode, for lowest noise under all load conditions.
The MAX1901/MAX1902/MAX1904 include two PWM reg-
ulators, adjustable from 2.5V to 5.5V with fixed 5.0V and
3.3V modes. All these devices include secondary feed-
back regulation, and the MAX1902 contains a 12V/120mA
linear regulator. The MAX1901/MAX1904 include a sec-
ondary feedback input (SECFB), plus a control pin
(STEER) that selects which PWM (3.3V or 5V) receives the
secondary feedback signal. SECFB provides a method
for adjusting the secondary winding voltage regulation
point with an external resistor divider, and is intended to
aid in creating auxiliary voltages other than fixed 12V.
The MAX1901/MAX1902 contain internal output overvolt-
age and undervoltage protection features.
________________________Applications
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Desktop CPU Local DC-DC Converters
Features
♦97% Efficiency
♦4.2V to 30V Input Range
♦2.5V to 5.5V Dual Adjustable Outputs
♦Selectable 3.3V and 5V Fixed or Adjustable
Outputs (Dual Mode™)
♦12V Linear Regulator
♦Adjustable Secondary Feedback
(MAX1901/MAX1904)
♦5V/50mA Linear Regulator Output
♦Precision 2.5V Reference Output
♦Programmable Power-Up Sequencing
♦Power-Good (RESET) Output
♦Output Overvoltage Protection
(MAX1901/MAX1902)
♦Output Undervoltage Shutdown
(MAX1901/MAX1902)
♦333kHz/500kHz Low-Noise, Fixed-Frequency
Operation
♦Low-Dropout, 98% Duty-Factor Operation
♦2.5mW Typical Quiescent Power (12V input, both
SMPSs on)
♦4µA Typical Shutdown Current
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
________________________________________________________________ Maxim Integrated Products 1
5V
LINEAR
12V
LINEAR
POWER-UP
SEQUENCE
POWER-
GOOD
3.3V
SMPS
5V
SMPS
RESETON/OFF
5V (RTC)
3.3V
INPUT
5V
12V
Functional Diagram
19-2224; Rev 3; 12/03
Ordering Information
Idle Mode is a trademark of Maxim Integrated Products, Inc.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1901EAI -40°C to +85°C 28 SSOP
MAX1901ETJ -40°C to +85°C32 Thin QFN 5m m x 5m m
MAX1902EAI -40°C to +85°C 28 SSOP
MAX1902ETJ -40°C to +85°C32 Thin QFN 5m m x 5m m
MAX1904EAI -40°C to +85°C 28 SSOP
MAX1904ETJ -40°C to +85°C32 Thin QFN 5m m x 5m m
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = 15V, both PWMs on, SYNC = VL, VLload = 0, REF load = 0, SKIP = 0, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND ..............................................................-0.3V to +36V
PGND to GND.....................................................................±0.3V
VLto GND ................................................................-0.3V to +6V
BST3, BST5 to GND ..............................................-0.3V to +36V
CSH3, CSH5 to GND................................................-0.3V to +6V
FB3 to GND ..............................................-0.3V to (CSL3 + 0.3V)
FB5 to GND ...............................................-0.3V to (CSL5 +0.3V)
LX3 to BST3..............................................................-6V to +0.3V
LX5 to BST5..............................................................-6V to +0.3V
REF, SYNC, SEQ, STEER, SKIP,
TIME/ON5, SECFB, RESET to GND ........-0.3V to (VL+ 0.3V)
VDD to GND............................................................-0.3V to +20V
RUN/ON3, SHDN to GND.............................-0.3V to (V+ + 0.3V)
12OUT to GND ..........................................-0.3V to (VDD + 0.3V)
DL3, DL5 to PGND........................................-0.3V to (VL+ 0.3V)
DH3 to LX3 ..............................................-0.3V to (BST3 + 0.3V)
DH5 to LX5 ..............................................-0.3V to (BST5 + 0.3V)
VL, REF Short to GND ................................................Momentary
12OUT Short to GND..................................................Continuous
REF Current...........................................................+5mA to -1mA
VLCurrent.........................................................................+50mA
12OUT Current . .............................................................+200mA
VDD Shunt Current............................................................+15mA
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.52mW/°C above +70°C) ......762mW
32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ..1702mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ............................-65°C to +160°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
MAIN SMPS CONTROLLERS
Input Voltage Range 4.2 30.0 V
3V Output Voltage in Adjustable Mode V+ = 4.2V to 30V, CSH3 - CSL3 = 0,
CSL3 tied to FB3 2.42 2.5 2.58 V
3V Output Voltage in Fixed Mode V+ = 4.2V to 30V, 0 < CSH3 - CSL3
< 80mV, FB3 = 0 3.20 3.39 3.47 V
5V Output Voltage in Adjustable Mode V+ = 4.2V to 30V, CSH5 - CSL5 = 0,
CSL5 tied to FB5 2.42 2.5 2.58 V
5V Output Voltage in Fixed Mode V+ = 5.3V to 30V, 0 < CSH5 - CSL5
< 80mV, FB5 = 0 4.85 5.13 5.25 V
Output Voltage Adjust Range Either SMPS REF 5.5 V
Adjustable-Mode Threshold Voltage Dual-mode comparator 0.5 1.1 V
Load Regulation Either SMPS, 0 < CSH_ - CSL_ < 80mV -2 %
Line Regulation Either SMPS, 5.2V < V+ < 30V 0.03 %/V
CSH3 - CSL3 or CSH5 - CSL5 80 100 120
Current-Limit Threshold SKIP = VL or VDD < 13V or SECFB < 2.44V -50 -100 -150 mV
Idle Mode Threshold SKIP = 0, not tested 10 25 40 mV
Soft-Start Ramp Time From enable to 95% full current limit with
respect to fOSC (Note 1) 512 clks
SYNC = VL450 500 550
Oscillator Frequency SYNC = 0 283 333 383 kHz
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, both PWMs on, SYNC = VL, VLload = 0, REF load = 0, SKIP = 0, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SYNC = VL95 97
Maximum Duty Factor SYNC = 0 (Note 2) 96.5 98 %
SYNC Input High-Pulse Width Not tested 200 ns
SYNC Input Low-Pulse Width Not tested 200 ns
SYNC Rise/Fall Time Not tested 200 ns
SYNC Input Frequency Range 400 583 kHz
Current-Sense Input Leakage Current V+ = VL = 0,
CSL3 = CSH3 = CSL5 = CSH5 = 5.5V 0.01 10 µA
FLYBACK CONTROLLER
VDD Regulation Threshold Falling edge (Note 3) 13 14 V
SECFB Regulation Threshold Falling edge (MAX1901/MAX1904) 2.44 2.60 V
DL Pulse Width VDD < 13V or SECFB < 2.44V 0.75 µs
VDD Shunt Threshold Rising edge, hysteresis = 1% (Note 3) 18 20 V
VDD Shunt Sink Current VDD = 20V (Note 3) 10 mA
VDD Leakage Current VDD = 5V, off mode (Notes 3, 4) 30 µA
12V LINEAR REGULATOR (Note 3)
12OUT Output Voltage 13V < VDD < 18V, 0 < ILOAD < 120mA 11.65 12.10 12.50 V
12OUT Current Limit 12OUT forced to 11V, VDD = 13V 150 mA
Quiescent VDD Current VDD = 18V, run mode, no 12OUT load 50 100 µA
INTERNAL REGULATOR AND REFERENCE
VL Output Voltage SHDN = V+, RUN/ON3 = TIME/ON5 = 0,
5.4V < V+ < 30V, 0mA < ILOAD < 50mA 4.7 5.1 V
VL Undervoltage Lockout-Fault Threshold Falling edge, hysteresis = 1% 3.5 3.6 3.7 V
VL Switchover Threshold Rising edge of CSL5, hysteresis = 1% 4.2 4.5 4.7 V
REF Output Voltage No external load (Note 5) 2.45 2.5 2.55 V
0 < ILOAD < 50µA 12.5
REF Load Regulation 0 < ILOAD < 5mA 100.0 mV
REF Sink Current 10 µA
REF Fault-Lockout Voltage Falling edge 1.8 2.4 V
V+ Operating Supply Current VL switched over to CSL5, 5V SMPS on 5 50 µA
V+ Standby Supply Current V+ = 5.5V to 30V, both SMPSs off, includes
current into SHDN 30 60 µA
V+ Standby Supply Current in Dropout V+ = 4.2V to 5.5V, both SMPSs off, includes
current into SHDN 50 200 µA
V+ Shutdown Supply Current V+ = 4.0V to 30V, SHDN = 0 4 10 µA
(Note 3) 2.5 4
Quiescent Power Consumption
Both SMPSs enabled,
FB3 = FB5 = 0,
CSL3 = CSH3 = 3.5V,
CSL5 = CSH5 = 5.3V MAX1901/MAX1904 1.5 4
mW
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, both PWMs on, SYNC = VL, VLload = 0, REF load = 0, SKIP = 0, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
FAULT DETECTION (MAX1901/MAX1902)
Overvoltage Trip Threshold With respect to unloaded output voltage 4 7 10 %
Overvoltage Fault Propagation Delay CSL_ driven 2% above overvoltage trip
threshold 1.5 µs
Output Undervoltage Threshold With respect to unloaded output voltage 60 70 80 %
Output Undervoltage Lockout Time From each SMPS enabled, with respect to
fOSC 5,000 6,144 7,000 clks
Thermal-Shutdown Threshold Typical hysteresis = 10°C 150 °C
RESET
RESET Trip Threshold With respect to unloaded output voltage,
falling edge; typical hysteresis = 1% -7 -5.5 -4 %
RESET Propagation Delay Falling edge, CSL_ driven 2% below RESET
trip threshold 1.5 µs
RESET Delay Time With respect to fOSC 27,000 32,000 37,000 clks
INPUTS AND OUTPUTS
Feedback-Input Leakage Current FB3, FB5; SECFB = 2.6V 1 50 nA
Logic Input-Low Voltage RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC 0.6 V
Logic Input-High Voltage RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC 2.4 V
Input Leakage Current RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC, SEQ; VPIN = 0V or 3.3V ±1µA
Logic Output-Low Voltage RESET, ISINK = 4mA 0.4 V
Logic Output-High Current RESET = 3.5V 1 mA
TIME/ON5 Input Trip Level SEQ = 0 or VL2.4 2.6 V
TIME/ON5 Source Current TIME/ON5 = 0, SEQ = 0 or VL2.5 3 3.5 µA
TIME/ON5 On-Resistance TIME/ON5; RUN/ON3 = 0, SEQ = 0 or VL15 80 Ω
Gate-Driver Sink/Source Current DL3, DH3, DL5, DH5; forced to 2V 1 A
SSOP package 1.5 7
Gate-Driver On-Resistance High or low (Note 6) QFN package 1.5 8
Ω
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS
(V+ = 15V, both PWMs on, SYNC = VL, VLload = 0, REF load = 0, SKIP = 0, TA= -40°C to +85°C, unless otherwise noted.) (Note 7)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MAIN SMPS CONTROLLERS
Input Voltage Range 4.2 30.0 V
3V Output Voltage in Adjustable Mode V+ = 4.2V to 30V, CSH3 - CSL3 = 0,
CSL3 tied to FB3 2.42 2.58 V
3V Output Voltage in Fixed Mode V+ = 4.2V to 30V, 0 < CSH3 - CSL3
< 80mV, FB3 = 0 3.20 3.47 V
5V Output Voltage in Adjustable Mode V+ = 4.2V to 30V, CSH5 - CSL5 = 0,
CSL5 tied to FB5 2.42 2.58 V
5V Output Voltage in Fixed Mode V+ = 5.3V to 30V, 0 < CSH5 - CSL5
< 80mV, FB5 = 0 4.85 5.25 V
Output Voltage Adjust Range Either SMPS REF 5.5 V
Adjustable-Mode Threshold Voltage Dual-mode comparator 0.5 1.1 V
CSH3 - CSL3 or CSH5 - CSL5 80 120
Current-Limit Threshold SKIP = VL or VDD < 13V or SECFB < 2.44V -50 -150 mV
SYNC = VL450 550
Oscillator Frequency SYNC = 0 283 383 kHz
SYNC = VL95
Maximum Duty Factor SYNC = 0 (Note 2) 97 %
SYNC Input Frequency Range 400 583 kHz
FLYBACK CONTROLLER
VDD Regulation Threshold Falling edge (Note 3) 13 14 V
SECFB Regulation Threshold Falling edge (MAX1901/MAX1904) 2.44 2.60
VDD Shunt Threshold Rising edge, hysteresis = 1% (Note 3) 18 20
V
V
VDD Shunt Sink Current VDD = 20V (Note 3) 10 mA
12V LINEAR REGULATOR (Note 3)
12OUT Output Voltage 13V < VDD < 18V, 0mA < ILOAD < 100mA 11.65 12.50 V
Quiescent VDD Current VDD = 18V, run mode, no 12OUT load 100 µA
INTERNAL REGULATOR AND REFERENCE
VL Output Voltage SHDN = V+, RUN/ON3 = TIME/ON5 = 0,
5.4V < V+ < 30V, 0 < ILOAD < 50mA 4.7 5.1 V
VL Undervoltage Lockout-Fault Threshold Falling edge, hysteresis = 1% 3.5 3.7 V
VL Switchover Threshold Rising edge of CSL5, hysteresis = 1% 4.2 4.7 V
REF Output Voltage No external load (Note 5) 2.45 2.55 V
0 < ILOAD < 50µA 12.5
REF Load Regulation 0 < ILOAD < 5mA 100.0 mV
REF Sink Current 10 µA
REF Fault Lockout Voltage Falling edge 1.8 2.4 V
V+ Operating Supply Current VL switched over to CSL5, 5V SMPS on 50 µA
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, both PWMs on, SYNC = VL, VLload = 0, REF load = 0, SKIP = 0, TA= -40°C to +85°C, unless otherwise noted.) (Note 7)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V+ Standby Supply Current V+ = 5.5V to 30V, both SMPSs off, includes
current into SHDN 60 µA
V+ Standby Supply Current in Dropout V+ = 4.2V to 5.5V, both SMPSs off, includes
current into SHDN 200 µA
V+ Shutdown Supply Current V+ = 4.0V to 30V, SHDN = 0 10 µA
(Note 3) 4
Quiescent Power Consumption
Both SMPSs enabled,
FB3 = FB5 = 0,
CSL3 = CSH3 = 3.5V,
CSL5 = CSH5 = 5.3V MAX1901/MAX1904 4
mW
FAULT DETECTION (MAX1901/MAX1902)
Overvoltage Trip Threshold With respect to unloaded output voltage 4 10 %
Output Undervoltage Threshold With respect to unloaded output voltage 60 80 %
Output Undervoltage Lockout Time From each SMPS enabled, with respect to
fOSC 5,000 7,000 clks
RESET
RESET Trip Threshold With respect to unloaded output voltage,
falling edge; typical hysteresis = 1% -7 -4
RESET Delay Time With respect to fOSC 27,000 37,000
%
clks
INPUTS AND OUTPUTS
Feedback-Input Leakage Current FB3, FB5; SECFB = 2.6V 50 nA
Logic Input-Low Voltage RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC 0.6 V
Logic Input-High Voltage RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC 2.4 V
Logic Output-Low Voltage RESET, ISINK = 4mA 0.4 V
Logic Output-High Current RESET = 3.5V 1 mA
TIME/ON5 Input Trip Level SEQ = 0 or VL2.4 2.6 V
TIME/ON5 Source Current TIME/ON5 = 0, SEQ = 0 or VL2.5 3.5 µA
TIME/ON5 On-Resistance TIME/ON5; RUN/ON3 = 0, SEQ = 0 or VL80 Ω
SSOP package 7
Gate-Driver On-Resistance High or low (Note 6) QFN package 8
Ω
Note 1: Each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mV increments.
Note 2: High duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating frequency
(see the Dropout Operation section).
Note 3: MAX1902 only.
Note 4: Off mode for the 12V linear regulator occurs when the SMPS that has flyback feedback (VDD) steered to it is disabled. In situa-
tions where the main outputs are being held up by external keep-alive supplies, turning off the 12OUT regulator prevents a leak-
age path from the output-referred flyback winding, through the rectifier, and into VDD.
Note 5: Since the reference uses VLas its supply, the reference’s V+ line-regulation error is insignificant.
Note 6: Production testing limitations due to package handing require relaxed maximum on-resistance specifications for the thin
QFN package. The SSOP and thin QFN package contain the same die, and the thin QFN package imposes no additional
resistance incircuit.
Note 7: Specifications from to 0°C to -40°C are guaranteed by design, not production tested.
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 7
100
50
0.001 0.01 0.1 1 10
EFFICIENCY vs. 5V OUTPUT CURRENT
60
MAX1901 toc01
5V OUTPUT CURRENT (A)
EFFICIENCY (%)
70
80
90
85
75
65
55
95
ON5 = 5V
ON3 = 0V
f = 500kHz
MAX1901/MAX1904
V+ = 15V
V+ = 6V
100
50
0.001 0.01 0.1 1 10
EFFICIENCY vs. 3.3V OUTPUT CURRENT
60
MAX1901 toc02
3.3V OUTPUT CURRENT (A)
EFFICIENCY (%)
70
80
90
85
75
65
55
95
ON5 = ON3 = 5V
f = 500kHz
MAX1901/MAX1904
V+ = 15V
V+ = 6V
800
600
400
200
0
01051520
MAXIMUM VDD OUTPUT CURRENT
vs. INPUT VOLTAGE
MAX1901 toc03
INPUT VOLTAGE (V)
MAXIMUM VDD OUTPUT CURRENT (mA)
5V LOAD = 0
5V LOAD = 3A
100
0.01
01052030
NO LOAD INPUT CURRENT
vs. INPUT VOLTAGE
0.1
1
10
MAX1901 toc04
INPUT VOLTAGE (V)
INPUT CURRENT (mA)
15 25
SKIP = 0V
SKIP = VL
ON5 = ON3 = 5V
NO LOAD
10,000
1
01052030
V+ STANDBY INPUT CURRENT
vs. INPUT VOLTAGE
10
100
1000
MAX1901 toc05
INPUT VOLTAGE (V)
INPUT CURRENT (µA)
15 25
ON5 = ON3 = 0V
NO LOAD 0
2
6
4
8
10
0105 15202530
SHUTDOWN INPUT CURRENT
vs. INPUT VOLTAGE
MAX1901 toc06
INPUT VOLTAGE (V)
INPUT CURRENT (µA)
SHDN = 0V
0.001 0.01 1
MINIMUM VIN TO VOUT DIFFERENTIAL
vs. 5V OUTPUT CURRENT
MAX1901 toc07
5V OUTPUT CURRENT (A)
MINIMUM VIN TO VOUT DIFFERENTIAL (mV)
1000
10
100
0.1 10
f = 500kHz
f = 333kHz
VOUT > 4.8V
1000
0.1
0.001 0.01 1 10
SWITCHING FREQUENCY
vs. LOAD CURRENT
1
10
100
MAX1901 toc08
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
0.1
3.3V, VIN = 15V
5V, VIN = 15V
3.3V, VIN = 6.5V
5V, VIN = 6.5V
4.90
4.92
4.96
4.94
4.98
5.00
02010 30 40 50
VL REGULATOR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1901 toc09
OUTPUT CURRENT (mA)
VL OUTPUT VOLTAGE (V)
VIN = 15V
ON3 = ON5 = 0V
Typical Operating Characteristics
(Circuit of Figure 1, Table 1, 6A/500kHz components, TA = +25°C, unless otherwise noted.)
STARTUP WAVEFORMS
MAX1901 toc11
0
0
0
0
3.3V OUTPUT
2V/div
5V OUTPUT
5V/div
TIME
2V/div
RUN
5V/div
2ms/div
SEQ = VL, O.O1µF CAPACITOR ON TIME
5V LOAD TRANSIENT RESPONSE
MAX1901 toc12
10V
0
5A
0
ILX5
5A/div
VLX5
10V/div
5V OUTPUT
5OmV/div
AC-COUPLED
20µs/div
VIN = 8V, IOUT = 1A TO 5A
3.3V LOAD TRANSIENT RESPONSE
MAX1901 toc13
10V
0
5A
0
ILX3
5A/div
VLX3
10V/div
3.3V OUTPUT
5OmV/div
AC-COUPLED
20µs/div
VIN = 8V, IOUT = 1A TO 5A
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, Table 1, 6A/500kHz components, TA = +25°C, unless otherwise noted.)
2.505
2.500
2.495
2.490
2.485
0312 456
REF OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1901 toc10
OUTPUT CURRENT (mA)
REF OUTPUT VOLTAGE (V)
VIN = 15V
ON3 = ON5 = 0
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
_______________________________________________________________________________________ 9
Pin Description
PIN
SSOP QFN NAME FUNCTION
1 29 CSH3 Current-Sense Input for the 3.3V SMPS. Current-limit level is 100mV referred to CSL3.
2 30 CSL3 Current-Sense Input. Also serves as the feedback input in fixed-output mode.
3 31 FB3
Feedback Input for the 3.3V SMPS. Regulates at FB3 = REF (approx. 2.5V) in
adjustable mode. FB3 is a dual-mode input that also selects the 3.3V fixed output
voltage setting when connected to GND. Connect FB3 to a resistor-divider for
adjustable-output mode.
12OUT
(MAX1902)
12V/120mA Linear-Regulator Output. Input supply comes from VDD. Bypass 12OUT to
GND with 1µF (min).
41
STEER
(MAX1901/
MAX1904)
Logic-Control Input for Secondary Feedback. Selects the PWM that uses a transformer
and secondary feedback signal (SECFB):
STEER = GND: 3.3V SMPS uses transformer
STEER = VL: 5V SMPS uses transformer
VDD
(MAX1902)
Supply Voltage Input for the 12OUT Linear Regulator. Also connects to an internal
resistor-divider for secondary winding feedback and to an 18V overvoltage shunt
regulator clamp.
52
SECFB
(MAX1901/
MAX1904)
Secondary Winding Feedback Input. Normally connected to a resistor-divider from an
auxiliary output. SECFB regulates at VSECFB = 2.5V (see the Secondary Feedback
Regulation Loop section). Connect to VL if not used.
6 3 SYNC
Oscillator Synchronization and Frequency Select. Connect to VL for 500kHz operation;
connect to GND for 333kHz operation. Can be driven at 400kHz to 583kHz for external
synchronization.
7 4 TIME/ON5 Dual-Purpose Timing Capacitor Pin and ON/OFF Control Input. See the Power-Up
Sequencing and ON/
OFF
Controls section.
8 5 GND Low-Noise Analog Ground and Feedback Reference Point
9 7 REF 2.5V Reference Voltage Output. Bypass to GND with 1µF (min).
10 8 SKIP Log i c- contr ol i np ut that d i sab l es i d l e m od e w hen hi g h. C onnect to GN D for nor m al use.
11 9 RESET Active-Low Timed Reset Output. RESET swings GND to VL. Goes high after a fixed
32,000 clock-cycle delay following power-up.
12 10 FB5
Feedback Input for the 5V SMPS. Regulates at FB5 = REF (approx. 2.5V) in adjustable
mode. FB5 is a dual-mode input that also selects the 5V fixed output voltage setting
when connected to GND. Connect FB5 to a resistor-divider for adjustable-output
mode.
13 11 CSL5 C ur r ent- S ense Inp ut for the 5V S M P S . Al so ser ves as the feed b ack i np ut i n fi xed - outp ut
m od e, and as the b ootstr ap sup p l y i np ut w hen the vol tag e on C S L5/V
L i s > 4.5V .
14 12 CSH5 Current-Sense Input for the 5V SMPS. Current-limit level is 100mV referred to CSL5.
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
QSOP QFN NAME FUNCTION
15 13 SEQ
Pin-strap input that selects the SMPS power-up sequence:
SEQ = GND: 5V before 3.3V, RESET output determined by both outputs
SEQ = REF: Separate ON3/ON5 controls, RESET output determined by 3.3V
output
SEQ = VL: 3.3V before 5V, RESET output determined by both outputs
16 14 DH5 Gate-Drive Output for the 5V, High-Side N-Channel Switch. DH5 is a floating driver
output that swings from LX5 to BST5, riding on the LX5 switching node voltage.
17 15 LX5 Switching-Node (Inductor) Connection. Can swing 2V below ground without hazard.
18 17 BST5 Boost Capacitor Connection for High-Side Gate Drive (0.1µF)
19 18 DL5 Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0 to VL.
20 19 PGND Power Ground
21 20 VL
5V Internal Linear-Regulator Output. VL is also the supply-voltage rail for the chip.
After the 5V SMPS output has reached 4.5V (typ), VL automatically switches to the
output voltage through CSL5 for bootstrapping. Bypass to GND with 4.7µF. VL
supplies up to 25mA for external loads.
22 21 V+ Battery Voltage Input, 4.2V to 30V. Bypass V+ to PGND close to the IC with a 0.22µF
capacitor. Connects to a linear regulator that powers VL.
23 22 SHDN
Shutdown Control Input, Active Low. Logic threshold is set at approximately 1V. For
automatic startup, connect SHDN to V+ through a 220kΩ resistor and bypass SHDN to
GND with a 0.01µF capacitor.
24 23 DL3 Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0 to VL.
25 24 BST3 Boost Capacitor Connection for High-Side Gate Drive (0.1µF)
26 26 LX3 Switching-Node (Inductor) Connection. Can swing 2V below ground without hazard.
27 27 DH3 Gate-Drive Output for the 3.3V, High-Side N-Channel Switch. DH3 is a floating driver
output that swings from LX3 to BST3, riding on the LX3 switching-node voltage.
28 28 RUN/ON3 ON/OFF Control Input. See the Power-Up Sequencing and ON/
OFF
Controls section.
—6, 16, 25, 32 N.C. No Connection
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 11
MAX1901
MAX1904
V+ SHDN VL
SECFB
INPUT ON/OFF
C3
7V TO 24V
REF SEQ
1µF
2.5V ALWAYS ON
*1A SCHOTTKY DIODE REQUIRED
FOR THE MAX1901 (SEE THE OUTPUT
OVERVOLTAGE PROTECTION SECTION).
5V ALWAYS ON
Q1
5V ON/OFF
3.3V ON/OFF
Q4
0.1µF
0.1µF
L2 R2 3.3V OUTPUT
C2
*
4.7µF
0.1µF
4.7µF
0.1µF
10Ω
C4
0.1µF
Q3
C5
0.1µF
DL3
CSH3
CSL3
FB3
RESET RESET OUTPUT
SKIP
STEER
Q2
L1
R1
5V OUTPUT
C1 DL5
LX5
DH5
BST5 BST3
SYNC
DH3
LX3
PGND
CSL5
CSH5
RUN/ON3
TIME/ON5
FB5
*
GND
Figure 1. Standard 3.3V/5V Application Circuit (MAX1901/MAX1904)
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
12 ______________________________________________________________________________________
Standard Application Circuit
The basic MAX1901/MAX1904 dual-output 3.3V/5V
buck converter (Figure 1) is easily adapted to meet a
wide range of applications with inputs up to 28V by
substituting components from Table 1. These circuits
represent a good set of tradeoffs between cost, size,
and efficiency, while staying within the worst-case
specification limits for stress-related parameters, such
as capacitor ripple current. Don’t change the frequency
of these circuits without first recalculating component
values (particularly inductance value at maximum bat-
tery voltage). Adding a Schottky rectifier across each
synchronous rectifier improves the efficiency of these
circuits by approximately 1%, but this rectifier is other-
wise not needed because the MOSFETs required for
these circuits typically incorporate a high-speed silicon
diode from drain to source. Use a Schottky rectifier
rated at a DC current equal to at least one-third of the
load current.
Detailed Description
The MAX1901/MAX1902/MAX1904 are dual, BiCMOS,
switch-mode power-supply controllers designed pri-
marily for buck-topology regulators in battery-powered
applications where high-efficiency and low-quiescent
supply current are critical. Light-load efficiency is
enhanced by automatic Idle-Mode operation, a vari-
able-frequency pulse-skipping mode that reduces tran-
sition and gate-charge losses. Each step-down,
power-switching circuit consists of two N-channel
MOSFETs, a rectifier, and an LC output filter. The out-
put voltage is the average AC voltage at the switching
node, which is regulated by changing the duty cycle of
the MOSFET switches. The gate-drive signal to the
N-channel high-side MOSFET must exceed the battery
voltage, and is provided by a flying-capacitor boost cir-
cuit that uses a 100nF capacitor connected to BST_.
Table 1. Component Selection for Standard 3.3V/5V Application
LOAD CURRENT
COMPONENT 4A/333kHz 4A/500kHz 6A/500kHz
Input Range 7V to 24V 7V to 24V 7V to 24V
Frequency 333kHz 500kHz 500kHz
Q1, Q3 High-Side
MOSFETs
1/2 Fairchild FDS6982S or
1/2 International Rectifier
IRF7901D1
1/2 Fairchild FDS6982S or
1/2 International Rectifier
IRF7901D1
Fairchild FDS6612A or
International Rectifier
IRF7807V
Q2, Q4 Low-Side
MOSFETs with Integrated
Schottky Diodes
1/2 Fairchild FDS6982S or
1/2 International Rectifier
IRF7901D1
1/2 Fairchild FDS6982S or
1/2 International Rectifier
IRF7901D1
Fairchild FDS6670S or
International Rectifier
IRF7807DV1
C3 Input Capacitor 3 ✕ 10µF, 25V ceramic
Taiyo Yuden TMK432BJ106KM
3 ✕ 10µF, 25V ceramic
Taiyo Yuden TMK432BJ106KM
4 ✕ 10µF, 25V ceramic
Taiyo Yuden TMK432BJ106KM
C1 Output Capacitor 150µF, 6V POSCAP
Sanyo 6TPC150M
150µF, 6V POSCAP
Sanyo 6TPC150M
2 ✕ 150µF, 6V POSCAP
Sanyo 6TPC150M
C2 Output Capacitor 2 ✕ 150µF, 4V POSCAP
Sanyo 4TPC150M
2 ✕ 150µF, 4V POSCAP
Sanyo 4TPC150M
2 ✕ 220µF, 4V POSCAP
Sanyo 4TPC220M
R1, R2 Resistors 0.018Ω
Dale WSL2512-R018-F
0.018Ω
Dale WSL2512-R018-F
0.012Ω
Dale WSL2512-R012-F
L1 Inductor 10µH, 4.5A Ferrite
Sumida CDRH124-100
7.0µH, 5.2A Ferrite
Sumida CEI122-H-7R0
4.2µH, 6.9A Ferrite
Sumida CEI122-H-4R2
L2 Inductor 7.0µH, 5.2A Ferrite
Sumida CEI122-H-7R0
5.6µH, 5.2A Ferrite
Sumida CEI122-H-5R6
4.2µH, 6.9A Ferrite
Sumida CEI122-H-4R2
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 13
The MAX1901/MAX1902/MAX1904 contain ten major
circuit blocks (Figure 2).
The two pulse-width-modulation (PWM) controllers
each consist of a Dual Mode feedback network and
multiplexer, a multi-input PWM comparator, high-side
and low-side gate drivers, and logic. MAX1901/
MAX1902 contain fault-protection circuits that monitor
the main PWM outputs for undervoltage and overvolt-
age. A power-on sequence block controls the power-
up timing of the main PWMs and determines whether
one or both of the outputs are monitored for undervoltage
faults. The MAX1902 includes a secondary feedback net-
work and 12V linear regulator to generate a 12V output
from a coupled-inductor flyback winding. The
MAX1901/MAX1904 have a secondary feedback input
(SECFB) instead, which allows a quasi-regulated,
adjustable output, coupled-inductor flyback winding to be
attached to either the 3.3V or the 5V main inductor. Bias
generator blocks include the 5V IC internal rail (VL) linear
regulator, 2.5V precision reference, and automatic boot-
strap switchover circuit. The PWMs share a common
333kHz/500kHz synchronizable oscillator.
These internal IC blocks aren’t powered directly from
the battery. Instead, the 5V VLlinear regulator steps
down the battery voltage to supply both VLand the
gate drivers. The synchronous-switch gate drivers are
directly powered from VL, while the high-side switch
gate drivers are indirectly powered from VLvia an
external diode-capacitor boost circuit. An automatic
bootstrap circuit turns off the 5V linear regulator and
powers the IC from the 5V PWM output voltage if the
output is above 4.5V.
PWM Controller Block
The two PWM controllers are nearly identical. The only
differences are fixed output settings (3.3V vs. 5V), the
VL/CSL5 bootstrap switch connected to the 5V PWM,
and SECFB. The heart of each current-mode PWM con-
troller is a multi-input, open-loop comparator that sums
three signals: the output-voltage error signal with
respect to the reference voltage, the current-sense sig-
nal, and the slope-compensation ramp (Figure 3). The
PWM controller is a direct-summing type, lacking a tra-
ditional error amplifier and the phase shift associated
with it. This direct-summing configuration approaches
ideal cycle-by-cycle control over the output voltage.
When SKIP = low, Idle Mode circuitry automatically
optimizes efficiency throughout the load current range.
Idle Mode dramatically improves light-load efficiency
by reducing the effective frequency, which reduces
switching losses. It keeps the peak inductor current
above 25% of the full current limit in an active cycle,
allowing subsequent cycles to be skipped. Idle Mode
transitions seamlessly to fixed-frequency PWM opera-
tion as load current increases.
With SKIP = high, the controller always operates in fixed-
frequency PWM mode for lowest noise. Each pulse from
the oscillator sets the main PWM latch that turns on the
high-side switch for a period determined by the duty fac-
tor (approximately VOUT / VIN). As the high-side switch
turns off, the synchronous rectifier latch sets; 60ns later,
the low-side switch turns on. The low-side switch stays on
until the beginning of the next clock cycle.
In PWM mode, the controller operates as a fixed-fre-
quency current-mode controller where the duty ratio is
set by the input/output voltage ratio. The current-mode
feedback system regulates the peak inductor current
value as a function of the output-voltage error signal. In
continuous-conduction mode, the average inductor
current is nearly the same as the peak current, so the
circuit acts as a switch-mode transconductance ampli-
fier. This pushes the second output LC filter pole, nor-
mally found in a duty-factor-controlled (voltage-mode)
PWM, to a higher frequency. To preserve inner-loop
stability and eliminate regenerative inductor current
“staircasing”, a slope-compensation ramp is summed
into the main PWM comparator to make the apparent
duty factor less than 50%.
The MAX1901/MAX1902/MAX1904 use a relatively low
loop gain, allowing the use of lower-cost output capaci-
tors. The relative gains of the voltage-sense and cur-
rent-sense inputs are weighted by the values of current
sources that bias three differential input stages in the
main PWM comparator (Figure 4). The relative gain of
the voltage comparator to the current comparator is
internally fixed at K = 2:1. The low loop gain results in
the 2% typical load-regulation error. The low value of
loop gain helps reduce output filter capacitor size and
cost by shifting the unity-gain crossover frequency to a
lower level.
Table 2. Component Suppliers
MANUFACTURER USA PHONE FACTORY FAX
Dale-Vishay 402-564-3131 402-563-6418
Fairchild
Semiconductor 408-721-2181 408-721-1635
International
Rectifier 310-322-3331 310-322-3332
Sanyo 619-661-6835 619-661-1055
Sumida 847-956-0666 847-956-0702
Taiyo Yuden 408-573-4150 408-573-4159
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
14 ______________________________________________________________________________________
LPF
50kHz
REF
1.75V
2.388V
R3
R4
-
+
+
-
4.5V
REF
2.5V
REF
333kHz
TO
500kHz
OSC
5V
PWM
LOGIC
5V
LINEAR
REG
VL
BST3
DH3
LX3
DL3
3.3V
VL
ON/OFF
INPUT
7V to 24V
5V ALWAYS ON
CSL5
SHDN V+ SYNC
12V
LINEAR
REG
12V
13V BST5 RAW 15V
DH5
DL5
VL
PGND
CSH5
CSL5
CSH3
CSL3
FB5
RESET
SEQ
2.6V
1V
0.6V 0.6V
VL
GND RUN/ON3
TIME/ON5
REF
LX5 5V
12OUT
VDD
IN
SECFB
3.3V
PWM
LOGIC
REF
OUTPUTS
UP
-
+
-
+
+
-
-
+
-
+
+
-
+
-
LPF
50kHz
TIMER
POWER-ON
SEQUENCE
LOGIC
R1
R2
FB3
-
+
+
-
MAX1902
OV/UV
FAULT
2.68V
Figure 2. MAX1902 Functional Diagram
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 15
SHOOT-
THROUGH
CONTROL
R
Q
30mV
RQ
LEVEL
SHIFT
0.75µs
SINGLE-SHOT
1X
MAIN PWM
COMPARATOR
OSC
LEVEL
SHIFT
CURRENT
LIMIT
SYNCHRONOUS
RECTIFIER CONTROL
REF
SHDN
CK
-100mV
CSH_
CSL_
FROM
FEEDBACK
DIVIDER
BST_
DH_
LX_
VL
DL_
PGND
S
S
SLOPE COMP
SKIP
REF
SECFB
COUNTER
DAC
SOFT-START
Figure 3. PWM Controller Functional Block Diagram
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
16 ______________________________________________________________________________________
The output filter capacitors (Figure1, C1 and C2) set a
dominant pole in the feedback loop that must roll off the
loop gain to unity before encountering the zero intro-
duced by the output capacitor’s parasitic resistance
(ESR) (see the Design Procedure section). A 50kHz
pole-zero cancellation filter provides additional rolloff
above the unity-gain crossover. This internal 50kHz
low-pass compensation filter cancels the zero due to fil-
ter capacitor ESR. The 50kHz filter is included in the
loop in both fixed-output and adjustable-output modes.
Synchronous Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky catch
diode with a low-resistance MOSFET switch. Also, the
synchronous rectifier ensures proper startup of the
boost gate-driver circuit.
If the circuit is operating in continuous-conduction
mode, the DL drive waveform is simply the complement
of the DH high-side drive waveform (with controlled
dead time to prevent cross-conduction or “shoot
through”). In discontinuous (light-load) mode, the syn-
chronous switch is turned off as the inductor current falls
through zero. The synchronous rectifier works under all
operating conditions, including Idle Mode.
The SECFB signal further controls the synchronous switch
timing in order to improve multiple-output cross-regulation
(see the Secondary Feedback Regulation Loop section).
Internal VL and REF Supplies
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, logic, reference, and other
blocks within the IC. This 5V low-dropout linear regula-
tor supplies up to 25mA for external loads, with a
reserve of 25mA for supplying gate-drive power.
Bypass VLto GND with 4.7µF.
Important: Ensure that VLdoes not exceed 6V.
Measure VLwith the main output fully loaded. If it is
pumped above 5.5V, either excessive boost-diode
capacitance or excessive ripple at V+ is the probable
cause. Use only small-signal diodes for the boost cir-
cuit (10mA to 100mA Schottky or 1N4148 are pre-
ferred), and bypass V+ to PGND with 4.7µF directly at
the package pins.
Table 3. SKIP PWM Table
SKIP LOAD CURRENT MODE DESCRIPTION
Low Light Idle Pulse-skipping, supply current = 250µA at VIN =12V, discontinuous inductor
Low Heavy PWM Constant-frequency PWM continuous-inductor current
High Light PWM Constant-frequency PWM continuous-inductor current
High Heavy PWM Constant-frequency PWM continuous-inductor current
FB_
REF
CSH_
CSL_
SLOPE COMPENSATION
VL
I1
R1 R2
TO PWM
LOGIC
OUTPUT DRIVER
UNCOMPENSATED
HIGH-SPEED
LEVEL TRANSLATOR
AND BUFFER
I2 I3 VBIAS
Figure 4. Main PWM Comparator Block Diagram
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 17
The 2.5V reference (REF) is accurate to ±2% over tem-
perature, making REF useful as a precision system ref-
erence. Bypass REF to GND with 1µF minimum. REF
can supply up to 5mA for external loads. (Bypass REF
with a minimum 1µF/mA reference load current.)
However, if extremely accurate specifications for both
the main output voltages and REF are essential, avoid
loading REF more than 100µA. Loading REF reduces
the main output voltage slightly, because of the refer-
ence load-regulation error.
When the 5V main output voltage is above 4.5V, an
internal P-channel MOSFET switch connects CSL5 to
VL, while simultaneously shutting down the VL linear
regulator. This action bootstraps the IC, powering the
internal circuitry from the output voltage, rather than
through a linear regulator from the battery.
Bootstrapping reduces power dissipation due to gate
charge and quiescent losses by providing that power
from a 90%-efficient switch-mode source, rather than
from a much less efficient linear regulator.
Boost High-Side Gate-Drive Supply
(BST3 and BST5)
Gate-drive voltage for the high-side N-channel switches
is generated by a flying-capacitor boost circuit (Figure 2).
The capacitor between BST_ and LX_ is alternately
charged from the VL supply and placed parallel to the
high-side MOSFET’s gate-source terminals. On startup,
the synchronous rectifier (low-side MOSFET) forces LX_
to 0V and charges the boost capacitors to 5V. On the
second half-cycle, the SMPS turns on the high-side MOS-
FET by closing an internal switch between BST_ and
DH_. This provides the necessary enhancement voltage
to turn on the high-side switch, an action that “boosts” the
5V gate-drive signal above the battery voltage.
Ringing at the high-side MOSFET gate (DH3 and DH5)
in discontinuous-conduction mode (light loads) is a nat-
ural operating condition. It is caused by residual ener-
gy in the tank circuit, formed by the inductor and stray
capacitance at the switching node, LX. The gate-drive
negative rail is referred to LX, so any ringing there is
directly coupled to the gate-drive output.
Current-Limiting and Current-Sense
Inputs (CSH and CSL)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor (R1) must be sized for
80mV/ IPEAK, where IPEAK is the required peak-inductor
current to support the full load current, while compo-
nents must be designed to withstand continuous-
current stresses of 120mV/R1.
For breadboarding or for very-high-current applica-
tions, it may be useful to wire the current-sense inputs
with a twisted pair, rather than PC traces. (This twisted
pair need not be special; two pieces of wire-wrap wire
twisted together is sufficient.) This reduces the possible
noise picked up at CSH_ and CSL_, which can cause
unstable switching and reduced output current. The
CSL5 input also serves as the IC’s bootstrap supply
input. Whenever VCSL5 > 4.5V, an internal switch con-
nects CSL5 to VL.
Oscillator Frequency and
Synchronization (SYNC)
The SYNC input controls the oscillator frequency. Low
selects 333kHz; high selects 500kHz. SYNC can also
be used to synchronize with an external 5V CMOS or
TTL clock generator. SYNC has a guaranteed 400kHz
to 583kHz capture range. A high-to-low transition on
SYNC initiates a new cycle.
500kHz operation optimizes the application circuit for
component size and cost. 333kHz operation provides
increased efficiency, lower dropout, and improved
load-transient response at low input-output voltage dif-
ferences (see the Low-Voltage Operation section).
Shutdown Mode
Holding SHDN low puts the IC into its 4µA shutdown
mode. SHDN is logic input with a threshold of about 1V
(the VTH of an internal N-channel MOSFET). For automat-
ic startup, bypass SHDN to GND with a 0.01µF capacitor
and connect it to V+ through a 220kΩresistor.
Power-Up Sequencing and
ON/
OFF
Controls
Startup is controlled by RUN/ON3 and TIME/ON5 in
conjunction with SEQ. With SEQ tied to REF, the two
control inputs act as separate ON/OFF controls for
each supply. With SEQ tied to VL or GND, RUN/ON3
becomes the master ON/OFF control input and
TIME/ON5 becomes a timing pin, with the delay
between the two supplies determined by an external
capacitor. The delay is approximately 800µs/nF. The
3.3V supply powers up first if SEQ is tied to VL, and the
5V supply is first if SEQ is tied to GND. When driving
TIME/ON5 as a control input with external logic, always
place a resistor (>1kΩ) in series with the input. This
prevents possible crowbar current due to the internal
discharge pulldown transistor, which turns on in stand-
by mode and momentarily at the first power-up or in
shutdown mode.
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
18 ______________________________________________________________________________________
RESET
Power-Good Voltage Monitor
The power-good monitor generates a system RESET
signal. At first power-up, RESET is held low until both
the 3.3V and 5V SMPS outputs are in regulation. At this
point, an internal timer begins counting oscillator puls-
es, and RESET continues to be held low until 32,000
cycles have elapsed. After this timeout period (64ms at
500kHz or 96ms at 333kHz), RESET is actively pulled
up to VL. If SEQ is tied to REF (for separate ON3/ON5
controls), only the 3.3V SMPS is monitored—the 5V
SMPS is ignored.
Output Undervoltage Shutdown
Protection (MAX1901/MAX1902)
The output undervoltage lockout circuit is similar to
foldback current limiting, but employs a timer rather
than a variable current limit. Each SMPS has an under-
voltage protection circuit that is activated 6144 clock
cycles after the SMPS is enabled. If either SMPS output
is under 70% of the nominal value, both SMPSs are
latched off and their outputs are clamped to ground by
the synchronous rectifier MOSFETs (see the Output
Overvoltage Protection section). They won’t restart until
SHDN or RUN/ON3 is toggled, or until V+ power is
cycled below 1V. Note that undervoltage protection can
make prototype troubleshooting difficult, since you
have only 12ms or 18ms to figure out what might be
wrong with the circuit before both SMPSs are latched
off. In extreme cases, it may be useful to substitute the
MAX1904 into the prototype breadboard until the proto-
type is working properly.
Output Overvoltage Protection
(MAX1901/MAX1902)
Both SMPS outputs are monitored for overvoltage. If
either output is more than 7% above the nominal regu-
lation point, both low-side gate drivers (DL_) are
latched high until SHDN or RUN/ON3 is toggled, or
until V+ power is cycled below 1V. This action turns on
the synchronous rectifiers with 100% duty, in turn rapid-
ly discharging the output capacitors and forcing both
SMPS outputs to ground. The DL outputs are also kept
high whenever the corresponding SMPS is disabled,
and in shutdown if VLis sustained.
Discharging the output capacitor through the main
inductor causes the output to momentarily go below
GND. Clamp this negative pulse with a back-biased 1A
Schottky diode across the output capacitor (Figure 1).
To ensure overvoltage protection on initial power-up,
connect signal diodes from both output voltages to VL
(cathodes to VL) to eliminate the VLpower-up delay.
This circuitry protects the load from accidental overvolt-
age caused by a short circuit across the high-side
power MOSFETs. This scheme relies on the presence
of a fuse, in series with the battery, which is blown by
the resulting crowbar current. Note that the overvoltage
circuitry will interfere with external keep-alive supplies
that hold up the outputs (such as lithium backup or hot-
swap power supplies); in such cases, the MAX1904
should be used.
Low-Noise Operation (PWM Mode)
PWM mode (SKIP = high) minimizes RF and audio inter-
ference in noise-sensitive applications (such as hi-fi multi-
media-equipped systems), cellular phones, RF
communicating computers, and electromagnetic pen
entry systems. See the summary of operating modes in
Table 2. SKIP can be driven from an external logic signal.
Table 4. Operating Modes
SHDN SEQ RUN/ON3 TIME/ON5 MODE DESCRIPTION
Low X X X Shutdown All circuit blocks turned off.
Supply current = 4µA.
High REF Low Low Standby Both SMPSs off. Supply current = 30µA.
High REF High Low Run 3.3V SMPS enabled/5V off.
High REF Low High Run 5V SMPS enabled/3.3V off.
High REF High High Run Both SMPSs enabled.
High GND Low Timing Capacitor Standby Both SMPSs off. Supply current = 30µA.
High GND High Timing Capacitor Run Both SMPSs enabled. 5V enabled before 3.3V.
High VL Low Timing Capacitor Standby Both SMPSs off. Supply current = 30µA.
High VL High Timing Capacitor Run Both SMPSs enabled. 3.3V enabled Before 5V.
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 19
Interference due to switching noise is reduced in PWM
mode by ensuring a constant switching frequency, thus
concentrating the emissions at a known frequency out-
side the system audio or IF bands. Choose an oscillator
frequency for which switching frequency harmonics
don’t overlap a sensitive frequency band. If necessary,
synchronize the oscillator to a tight-tolerance external
clock generator. To extend the output-voltage regula-
tion range, constant operating frequency is not main-
tained under overload or dropout conditions (see the
Dropout Operation section).
PWM mode (SKIP = high) forces two changes upon the
PWM controllers. First, it disables the minimum-current
comparator, ensuring fixed-frequency operation.
Second, it changes the detection threshold for reverse
current limit from 0 to -100mV, allowing the inductor cur-
rent to reverse at light loads. This results in fixed-fre-
quency operation and continuous inductor-current flow.
This eliminates discontinuous-mode inductor ringing and
improves cross regulation of transformer-coupled multi-
ple-output supplies, particularly in circuits that don’t use
additional secondary regulation via SECFB or VDD.
In most applications, tie SKIP to GND to minimize qui-
escent supply current. VL supply current with SKIP high
is typically 30mA, depending on external MOSFET gate
capacitance and switching losses.
Internal Digital Soft-Start Circuit
Soft-start allows a gradual increase of the internal cur-
rent-limit level at startup to reduce input surge currents.
Both SMPSs contain internal digital soft-start circuits,
each controlled by a counter, a digital-to-analog con-
verter (DAC), and a current-limit comparator. In shut-
down or standby mode, the soft-start counter is reset to
zero. When an SMPS is enabled, its counter starts
counting oscillator pulses, and the DAC begins incre-
menting the comparison voltage applied to the current-
limit comparator. The DAC output increases from 0 to
100mV in five equal steps as the count increases to
512 clocks. As a result, the main output capacitor
charges up relatively slowly. The exact time of the out-
put rise depends on output capacitance and load cur-
rent, and is typically 600µs with a 500kHz oscillator.
Dropout Operation
Dropout (low input-output differential operation) is
enhanced by stretching the clock pulse width to
increase the maximum duty factor. The algorithm fol-
lows: If the output voltage (VOUT) drops out of regula-
tion without the current limit having been reached, the
SMPS skips an off-time period (extending the on-time).
At the end of the cycle, if the output is still out of regula-
tion, the SMPS skips another off-time period. This
action can continue until three off-time periods are
skipped, effectively dividing the clock frequency by as
much as four.
The typical PWM minimum off-time is 300ns, regardless
of the operating frequency. Lowering the operating fre-
quency raises the maximum duty factor above 97%.
Adjustable-Output Feedback
(Dual Mode FB)
Fixed, preset output voltages are selected when FB_ is
connected to ground. Adjusting the main output volt-
age with external resistors is simple for any of the
MAX1901/MAX1902/MAX1904, through resistor divi-
ders connected to FB3 and FB5 (Figure 2). Calculate
the output voltage with the following formula:
VOUT = VREF (1 + R1 / R2)
where VREF = 2.5V nominal.
The nominal output should be set approximately 1% or
2% high to make up for the MAX1901/MAX1902/
MAX1904 -2% typical load-regulation error. For exam-
ple, if designing for a 3.0V output, use a resistor ratio
that results in a nominal output voltage of 3.05V. This
slight offsetting gives the best possible accuracy.
Recommended normal values for R2 range from 5kΩto
100kΩ. To achieve a 2.5V nominal output, simply con-
nect FB_ directly to CSL_.
Remote output-voltage sensing, while not possible in
fixed-output mode due to the combined nature of the
voltage-sense and current-sense inputs (CSL3 and
CSL5), is easy to do in adjustable mode by using the top
of the external resistor-divider as the remote sense point.
When using adjustable mode, it is a good idea to
always set the “3.3V output” to a lower voltage than the
“5V output.” The 3.3V output must always be less than
VL, so that the voltage on CSH3 and CSL3 is within the
common-mode range of the current-sense inputs. While
VL is nominally 5V, it can be as low as 4.7V when lin-
early regulating, and as low as 4.2V when automatically
bootstrapped to CSH5.
Secondary Feedback Regulation Loop
(SECFB or VDD)
A flyback-winding control loop regulates a secondary
winding output, improving cross-regulation when the
primary output is lightly loaded or when there is a low
input-output differential voltage. If VDD or SECFB falls
below its regulation threshold, the low-side switch is
turned on for an extra 0.75µs. This reverses the induc-
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
20 ______________________________________________________________________________________
tor (primary) current, pulling current from the output fil-
ter capacitor and causing the flyback transformer to
operate in forward mode. The low impedance present-
ed by the transformer secondary in forward mode
dumps current into the secondary output, charging up
the secondary capacitor and bringing VDD or SECFB
back into regulation. The secondary feedback loop
does not improve secondary output accuracy in normal
flyback mode, where the main (primary) output is heavi-
ly loaded. In this condition, secondary output accuracy
is determined by the secondary rectifier drop, trans-
former turns ratio, and accuracy of the main output volt-
age. A linear post-regulator may still be needed to meet
strict output-accuracy specifications.
MAX1902 has a VDD pin that regulates at a fixed 13.5V,
set by an internal resistor-divider. The MAX1901/
MAX1904 have an adjustable secondary-output voltage
set by an external resistor-divider on SECFB (Figure 5).
Ordinarily, the secondary regulation point is set 5% to
10% below the voltage normally produced by the flyback
effect. For example, if the output voltage as determined
by turns ratio is 15V, set the feedback resistor ratio to pro-
duce 13.5V. Otherwise, the SECFB one-shot might be
triggered unintentionally, unnecessarily increasing supply
current and output noise.
12V Linear Regulator Output (MAX1902)
The MAX1902 includes a 12V linear regulator output
capable of delivering 120mA of output current.
Typically, greater current is available at the expense of
output accuracy. If an accurate output of more than
120mA is needed, an external pass transistor can be
added. The circuit in Figure 6 delivers more than
200mA. Total output current is constrained by the V+
input voltage and the transformer primary load (see
Maximum VDD Output Current vs. Input Voltage graphs
in the Typical Operating Characteristics).
Design Procedure
The three predesigned 3V/5V standard application cir-
cuits (Figure 1 and Table 1) contain ready-to-use solu-
tions for common application needs. Also, one
standard flyback transformer circuit supports the
12OUT linear regulator in the Applications Information
section. Use the following design procedure to optimize
these basic schematics for different voltage or current
requirements. But before beginning a design, firmly
establish the following:
Maximum Input (Battery) Voltage, VIN(MAX). This value
should include the worst-case conditions, such as no-
load operation when a battery charger or AC adapter is
MAX1901
MAX1904
POSITIVE
SECONDARY
OUTPUT
MAIN
OUTPUT
DH_
V+
SECFB
2.5V REF
R2
R1
1-SHOT
TRIG
DL_
WHERE VREF (NOMINAL) = 2.5V+VTRIP = VREF (1 + –––)
R1
R2
MAX1902
VDD OUTPUT
12V OUTPUT
200mA
MAIN
OUTPUT
2N3906
0.1µF
0.1µF
0.1µF
2.2µF
10µF
10Ω
V+
VDD
12OUT
DH_
DL_
Figure 5. Adjusting the Secondary Output Voltage with SECFB Figure 6. Increased 12V Linear Regulator Output Current
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 21
connected but no battery is installed. VIN(MAX) must not
exceed 30V.
Minimum Input (Battery) Voltage, VIN(MIN).This should
be taken at full load under the lowest battery condi-
tions. If VIN(MIN) is less than 4.2V, use an external cir-
cuit to externally hold VLabove the VLundervoltage
lockout threshold. If the minimum input-output differ-
ence is less than 1.5V, the filter capacitance required to
maintain good AC load regulation increases (see the
Low-Voltage Operation section).
Inductor Value
The exact inductor value isn’t critical and can be freely
adjusted to make trade-offs between size, cost, and
efficiency. Lower inductor values minimize size and
cost, but reduce efficiency due to higher peak-current
levels. The smallest inductor is achieved by lowering
the inductance until the circuit operates at the border
between continuous and discontinuous mode. Further
reducing the inductor value below this crossover point
results in discontinuous-conduction operation even at
full load. This helps lower output-filter capacitance
requirements, but efficiency suffers due to high I2R
losses. On the other hand, higher inductor values mean
greater efficiency, but resistive losses due to extra wire
turns will eventually exceed the benefit gained from
lower peak-current levels. Also, high inductor values
can affect load-transient response (see the VSAG equa-
tion in the Low-Voltage Operation section). The equa-
tions that follow are for continuous-conduction
operation, since the MAX1901/MAX1902/MAX1904 are
intended mainly for high-efficiency, battery-powered
applications. Discontinuous conduction doesn’t affect
normal idle-mode operation.
Three key inductor parameters must be specified:
inductance value (L), peak current (IPEAK), and DC
resistance (RDC). The following equation includes a
constant (LIR) which is the ratio of inductor peak-to-
peak AC current to DC load current. A higher LIR value
allows smaller inductance, but results in higher losses
and higher ripple. A good compromise between size
and losses is found at a 30% ripple-current to load-cur-
rent ratio (LIR = 0.3), which corresponds to a peak-
inductor current 1.15 times higher than the DC load
current.
where: f = switching frequency, normally 333kHz or
500kHz
IOUT = maximum DC load current
LIR = ratio of AC to DC inductor current, typi-
cally 0.3; should be >0.15
The nominal peak-inductor current at full load is 1.15 ✕
IOUT if the above equation is used; otherwise, the peak
current can be calculated by:
The inductor’s DC resistance should be low enough that
RDC ✕IPEAK < 100mV, as it is a key parameter for effi-
ciency performance. If a standard off-the-shelf inductor is
not available, choose a core with an LI2rating greater
than L ✕IPEAK2and wind it with the largest-diameter wire
that fits the winding area. Ferrite core material is strongly
preferred. Shielded-core geometries help keep noise,
EMI, and switching-waveform jitter low.
Current-Sense Resistor Value
The current-sense resistor value is calculated accord-
ing to the worst-case low current-limit threshold voltage
(from the Electrical Characteristics) and the peak
inductor current:
Use IPEAK from the second equation in the Inductor
Value section.
Use the calculated value of RSENSE to size the MOS-
FET switches and specify inductor saturation-current
ratings according to the worst-case high current-limit
threshold voltage:
Low-inductance resistors, such as surface-mount
metal-film, are recommended.
Input-Capacitor Value
The input filter capacitor is usually selected according
to input ripple current requirements and voltage rating,
rather than capacitor value. Ceramic capacitors or
Sanyo OS-CON capacitors are typically used to handle
the power-up surge-currents, especially when connect-
ing to robust AC adapters or low-impedance batteries.
RMS input ripple current (IRMS) is determined by the
input voltage and load current, with the worst case
occurring at VIN = 2 ✕VOUT:
ImV
R
PEAK MAX SENSE
()
=120
RmV
I
SENSE PEAK
=80
II VV V
fLV
PEAK LOAD
OUT IN MAX OUT
IN MAX
=+
()
×× ×
(()
()
-
2
LVV V
V f I LIR
OUT IN MAX OUT
IN MAX OUT
=
()
×× ×
()
()
-
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
22 ______________________________________________________________________________________
Therefore, when VIN is 2 x VOUT:
Bypassing V+
Bypass the V+ input with a 4.7µF tantalum capacitor
paralleled with a 0.1µF ceramic capacitor, close to the
IC. A 10Ωseries resistor to VIN is also recommended.
Bypassing VL
Bypass the VL output with a 4.7µF tantalum capacitor
paralleled with a 0.1µF ceramic capacitor, close to the
device.
Output-Filter Capacitor Value
The output-filter capacitor values are generally deter-
mined by the ESR and voltage-rating requirements,
rather than actual capacitance requirements for loop sta-
bility. In other words, the low-ESR electrolytic capacitor
that meets the ESR requirement usually has more output
capacitance than is required for AC stability. Use only
specialized low-ESR capacitors intended for switching-
regulator applications, such as AVX TPS, Sanyo
POSCAP, or Kemet T510. To ensure stability, the capaci-
tor must meet both minimum capacitance and maximum
ESR values as given in the following equations:
These equations are worst case, with 45°of phase mar-
gin to ensure jitter-free, fixed-frequency operation and
provide a nicely damped output response for zero to
full-load step changes. Some cost-conscious designers
may wish to bend these rules with less-expensive
capacitors, particularly if the load lacks large step
changes. This practice is tolerable if some bench test-
ing over temperature is done to verify acceptable noise
and transient response.
No well-defined boundary exists between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope won’t quite sync up. Technically speaking, this
jitter (usually harmless) is unstable operation, since the
duty factor varies slightly. As capacitors with higher
ESRs are used, the jitter becomes more pronounced, and
the load-transient output-voltage waveform starts looking
ragged at the edges. Eventually, the load-transient wave-
form has enough ringing on it that the peak noise levels
exceed the allowable output-voltage tolerance. Note that
even with zero phase margin and gross instability pre-
sent, the output-voltage noise never gets much worse
than IPEAK ✕RESR (under constant loads).
The output-voltage ripple is usually dominated by the
filter capacitor’s ESR, and can be approximated as
IRIPPLE ✕RESR. There is also a capacitive term, so the
full equation for ripple in continuous-conduction mode
is VNOISE (p-p) = IRIPPLE ✕[RESR + 1/(2 ✕π✕f ✕
COUT)]. In idle mode, the inductor current becomes
discontinuous, with high peaks and widely spaced
pulses, so the noise can actually be higher at light load
(compared to full load). In idle mode, calculate the out-
put ripple as follows:
Transformer Design
(for Auxiliary Outputs Only)
Buck-plus-flyback applications, sometimes called “cou-
pled-inductor” topologies, need a transformer to gener-
ate multiple output voltages. Performing the basic
electrical design is a simple task of calculating turns
ratios and adding the power delivered to the secondary
to calculate the current-sense resistor and primary
inductance. However, extremes of low input-output dif-
ferentials, widely different output loading levels, and
high turns ratios can complicate the design due to par-
asitic transformer parameters such as interwinding
capacitance, secondary resistance, and leakage
inductance. For examples of what is possible with real
world transformers, see the Maximum VDD Output
Current vs. Input Voltage graph in the Typical
Operating Characteristics.
Power from the main and secondary outputs is combined
to get an equivalent current referred to the main output
voltage (see the Inductor Value section for parameter
definitions). Set the current-sense resistor value at 80mV
/ ITOTAL.
VR
R
LV VV
RC
NOISE P P ESR
SENSE
OUT IN OUT
SENSE OUT
()
.
.[//()]
-
-
=×+
×× +
×
0 025
0 0003 1 1
2
CVVV
VR f
RRV
V
OUT
REF OUT IN MIN
OUT SENSE
ESR SENSE OUT
REF
>+
××
<×
(/)
()
1
II
RMS LOAD
=2
II VVV
V
RMS LOAD
OUT IN OUT
IN
=× ()-
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 23
PTOTAL = The sum of the output power from all outputs
ITOTAL = PTOTAL / VOUT = The equivalent output cur-
rent referred to VOUT
where: VSEC = the minimum required rectified sec
ondary output voltage
VFWD = the forward drop across the secondary
rectifier
VOUT(MIN) = the minimum value of the main out
put voltage (from the Electrical
Characteristics tables)
VRECT = the on-state voltage drop across the
synchronous rectifier MOSFET
VSENSE = the voltage drop across the sense
resistor
In positive-output applications, the transformer sec-
ondary return is often referred to the main output volt-
age, rather than to ground, to reduce the needed turns
ratio. In this case, the main output voltage must first be
subtracted from the secondary voltage to obtain VSEC.
Selecting Other Components
MOSFET Switches
The high-current N-channel MOSFETs must be logic-
level types with guaranteed on-resistance specifica-
tions at VGS = 4.5V. Lower gate threshold
specifications are better (i.e., 2V max rather than 3V
max). Drain-source breakdown voltage ratings must at
least equal the maximum input voltage, preferably with
a 20% derating factor. The best MOSFETs will have the
lowest on-resistance per nanocoulomb of gate charge.
Multiplying RDS(ON) ✕QGprovides a good figure for
comparing various MOSFETs. Newer MOSFET process
technologies with dense cell structures generally per-
form best. The internal gate drivers tolerate >100nC
total gate charge, but 70nC is a more practical upper
limit to maintain best switching times.
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
I2R power losses are the greatest heat contributor for
both high-side and low-side MOSFETs. I2R losses are
distributed between Q1 and Q2 according to duty fac-
tor (see the following equations). Generally, switching
losses affect only the upper MOSFET, since the
Schottky rectifier clamps the switching node in most
cases before the synchronous rectifier turns on. Gate
charge losses are dissipated by the driver and don’t
heat the MOSFET. Calculate the temperature rise
according to package thermal-resistance specifications
to ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature. The
worst-case dissipation for the high-side MOSFET
occurs at both extremes of input voltage, and the
worst-case dissipation for the low-side MOSFET occurs
at maximum input voltage:
where: On-state voltage drop VQ_ = ILOAD ✕RDS(ON)
CRSS = MOSFET reverse transfer capacitance
IGATE = DH driver peak output current capability
(1A typ)
20ns = DH driver inherent rise/fall time
Under output short-circuit, the MAX1904 synchronous
rectifier MOSFET suffers extra stress because its duty
factor can increase to greater than 0.9. It may need to
be oversized to tolerate a continuous DC short circuit.
During short circuit, the MAX1901/MAX1902’s output
undervoltage shutdown protects the synchronous recti-
fier under output short-circuit conditions.
To reduce EMI, add a 0.1µF ceramic capacitor from the
high-side switch drain to the low-side switch source.
Rectifier Clamp Diode
The rectifier diode is a clamp across the low-side MOS-
FET that catches the negative inductor swing during
the 60ns dead time between turning one MOSFET off
and each low-side MOSFET on. The latest generations
of MOSFETs incorporate a high-speed Schottky diode,
which serves as an adequate clamp diode. For
MOSFETs without integrated Schottky diodes, place a
Schottky diode in parallel with the low-side MOSFET.
PD I R DUTY
VI f
VC
Ins
PD I R DUTY
DUTY V V V V
upperFET LOAD DS ON
IN LOAD
IN RSS
GATE
upperFET LOAD DS ON
OUT Q IN Q
=× ×
+× ××
×+
=× ×
=+
()()
2
2
21
20
1
()
()
()
/
-
-
LVV V
V f I LIR
Turns Ratio N VV
VVV
PRIMARY
OUT IN MAX OUT
IN MAX TOTAL
SEC FWD
OUT MIN RECT SENSE
=×× ×
=+
++
()
()
()
()
-
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
24 ______________________________________________________________________________________
Use a Schottky diode with a DC current rating equal to
one third of the load current. The Schottky diode’s rated
reverse breakdown voltage must be at least equal to
the maximum input voltage, preferably with a 20% der-
ating factor.
Boost-Supply Diode
A signal diode such as a 1N4148 works well in most
applications. If the input voltage can go below +6V, use
a small (20mA) Schottky diode for slightly improved
efficiency and dropout characteristics. Don’t use large
power diodes, such as 1N5817 or 1N4001, since high
junction capacitance can pump up VLto excessive
voltages.
Rectifier Diode (Transformer Secondary Diode)
The secondary diode in coupled-inductor applications
must withstand flyback voltages greater than 60V,
which usually rules out most Schottky rectifiers.
Common silicon rectifiers, such as the 1N4001, are also
prohibited because they are too slow. This often makes
fast silicon rectifiers such as the MURS120 the only
choice. The flyback voltage across the rectifier is relat-
ed to the VIN - VOUT difference, according to the trans-
former turns ratio:
VFLYBACK = VSEC + (VIN - VOUT) ✕N
where: N = the transformer turns ratio SEC/PRI
VSEC = the maximum secondary DC output
voltage
VOUT = the primary (main) output voltage
Subtract the main output voltage (VOUT) from VFLY-
BACK in this equation if the secondary winding is
returned to VOUT and not to ground. The diode reverse-
breakdown rating must also accommodate any ringing
due to leakage inductance. The rectifier diode’s current
rating should be at least twice the DC load current on
the secondary output.
Low-Voltage Operation
Low input voltages and low input-output differential volt-
ages each require extra care in their design. Low
absolute input voltages can cause the VLlinear regulator
to enter dropout and eventually shut itself off. Low input
voltages relative to the output (low VIN - VOUT differential)
can cause bad load regulation in multi-output flyback
applications (see the design equations in the Transformer
Design section). Also, low VIN - VOUT differentials can
also cause the output voltage to sag when the load cur-
rent changes abruptly. The amplitude of the sag is a
function of inductor value and maximum duty factor (an
Electrical Characteristics parameter, 97% guaranteed
over temperature at f = 333kHz), as follows:
The cure for low-voltage sag is to increase the output
capacitor’s value. Take a 333kHz/6A application circuit
as an example, at VIN = +5.5V, VOUT = +5V, L = 6.7µH,
f = 333kHz, ISTEP = 3A (half-load step), a total capaci-
tance of 470µF keeps the sag less than 200mV. The
capacitance is higher than that shown in the Typical
Application Circuit because of the lower input voltage.
Note that only the capacitance requirement increases,
and the ESR requirements don’t change. Therefore, the
added capacitance can be supplied by a low-cost bulk
capacitor in parallel with the normal low-ESR capacitor.
Applications Information
Heavy-Load Efficiency Considerations
The major efficiency-loss mechanisms under loads are,
in the usual order of importance:
•P(I2R) = I2R losses
•P(tran) = transition losses
•P(gate) = gate-charge losses
•P(diode) = diode-conduction losses
•P(cap) = input capacitor ESR losses
•P(IC) = losses due to the IC’s operating supply current
Inductor core losses are fairly low at heavy loads
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores, such as Kool-Mu, can work well:
Efficiency = POUT/PIN ✕100%
= POUT/(POUT + PTOTAL) ✕100%
PTOTAL = P(I2R) + P(tran) + P(gate) + P(diode) +
P(cap) + P(IC)
P (I2R) = ILOAD2x (RDC + RDS(ON) + RSENSE)
where RDC is the DC resistance of the coil, RDS(ON) is
the MOSFET on-resistance, and RSENSE is the current-
sense resistor value. The RDS(ON) term assumes identi-
cal MOSFETs for the high-side and low-side switches:
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
VIL
CV DV
SAG STEP
OUT IN MIN MAX OUT
=×
×× ×
2
2( )
() -
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 25
where CRSS is the reverse transfer capacitance of the
high-side MOSFET (a data sheet parameter), IGATE is
the DH gate-driver peak output current (1.5A typical),
and 20ns is the rise/fall time of the DH driver (20ns typ).
P(gate) = QG✕f ✕VL
where VLis the internal-logic-supply voltage (5V), and
QGis the sum of the gate-charge values for low-side
and high-side switches. For matched MOSFETs, QGis
twice the data sheet value of an individual MOSFET. If
VOUT is set to less than 4.5V, replace VLin this equa-
tion with VBATT. In this case, efficiency can be
improved by connecting VLto an efficient 5V source,
such as the system 5V supply:
P(diode) = ILOAD ✕VFWD ✕tD✕f
where tDis the diode-conduction time (120ns typ) and
VFWD is the forward voltage of the diode.
This power is dissipated in the MOSFET body diode if
no external Schottky diode is used:
P(cap) = (IRMS)2x RESR
where IRMS is the input ripple current as calculated in the
Design Procedure and Input-Capacitor Value sections.
Light-Load Efficiency Considerations
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This makes the
inductor current’s AC component high compared to the
load current, which increases core losses and I2R loss-
es in the output filter capacitors. For best light-load effi-
ciency, use MOSFETs with moderate gate-charge
levels, and use ferrite, MPP, or other low-loss core
material.
P tran V I
fVCI ns
IN LOAD
IN RSS GATE
()
/
=× ×
×× ×
()
[]
3
220-
SYMPTOM CONDITION ROOT CAUSE SOLUTION
Sag or droop in VOUT
under step-load change
Low VIN - VOUT
differential, <1.5V
Limited inductor-current slew rate
per cycle.
Increase bulk output capacitance per
formula (see the Low-Voltage Operation
section). Reduce inductor value.
Dropout voltage is too
high (VOUT follows VIN as
VIN decreases)
Low VIN - VOUT
differential, <1V
Maximum duty-cycle limits
exceeded.
Reduce operation to 333kHz. Reduce
MOSFET on-resistance and coil DCR.
Unstable—jitters between
different duty factors and
frequencies
Low VIN - VOUT
differential, <0.5V
Normal function of internal low-
dropout circuitry.
Increase the minimum input voltage or
ignore.
Secondary output won’t
support a load
Low VIN - VOUT
differential,
VIN < 1.3 ✕
VOUT(MAIN)
Not enough duty cycle left to
initiate forward-mode operation.
Small AC current in primary can’t
store energy for flyback
operation.
Reduce operation to 333kHz. Reduce
secondary impedances; use a Schottky
diode, if possible. Stack secondary
winding on the main output.
Poor efficiency Low input voltage,
<5V
VL linear regulator is going into
dropout and isn’t providing good
gate-drive levels.
Use a small 20mA Schottky diode for
boost diode. Supply VL from an external
source.
Won’t start under load or
quits before battery is
completely dead
Low input voltage,
<4.5V
VL output is so low that it hits the
VL UVLO threshold.
Supply VL from an external source other
than VIN, such as the system 5V supply.
Table 5. Low-Voltage Troubleshooting Chart
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
26 ______________________________________________________________________________________
Lossless-Inductor Current-Sensing
The DC resistance (DCR) of the inductor can be used
to sense inductor current to improve the efficiency and
to reduce the cost by eliminating the sense resistor.
Figure 7 shows the sense circuit, where L is the induc-
tance, RLis the inductor DCR, RS, and CSform an RC
low-pass sense network. If the time constant of the
inductor is equal to that of the sense network, i.e.:
then the voltage across CSbecomes
where ILis the inductor current.
Determine the required sense-resistor value using the
equation given in the Current-Sense Resistor Value
section. Choose an inductor with DCR equal or greater
than the sense resistor value. If the DCR is greater than
the sense-resistor value, use a divider to scale down
the voltage. Use the maximum inductance and mini-
mum DCR to get the maximum possible inductor time
constant. Select RSand CSso that the maximum sense
network time constant is equal or greater than the maxi-
mum inductor time constant.
Reduced Output Capacitance Application
In applications where higher output ripple is accept-
able, lower output capacitance or higher ESR output
capacitors can be used. In such cases, cycle-by-cycle
stability is maintained by adding feedforward compen-
sation to offset for the increased output ESR. Figure 8
shows the addition of the feedforward compensation
circuit. CFB provides noise filtering, RFF is the feedfor-
ward resistor and CLX provides DC blocking. Use
100pF for CFB and CLX. Select RFF according to the
equation below:
Set the value for RFF close to the calculation. Do not
make RFF too small as that will introduce too much
feedforward, possibly causing an overvoltage to be
seen at the feedback pin, and changing the mode of
operation to a voltage mode.
PC Board Layout Considerations
Good PC board layout is required in order to achieve
specified noise, efficiency, and stability performance.
The PC board layout artist must be given explicit
instructions, preferably a pencil sketch showing the
placement of power-switching components and high-
current routing. A ground plane is essential for optimum
RRLf
ESR
FF ≤×××43
VRI
SLL
=×
L
RRC
LSS
=
L
DL_
DH_
LX_
MAX1901
MAX1902
MAX1904 CSH_
CSL_
INDUCTOR
RLVOUT
VIN
CIN
COUT
CS
RS
Figure 7. Lossless Inductor Current Sensing
R3
R4
FB_
L
CIN
DL_
DH_
LX_
MAX1901
MAX1902
MAX1904
CSH_
CSL_
VIN
CLX RFF CFB
RSENSE VOUT
COUT
Figure 8. Adding Feedforward Compensation
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 27
performance. In most applications, the circuit will be
located on a multilayer board, and full use of the four or
more copper layers is recommended. Use the top layer
for high-current connections, the bottom layer for quiet
connections (REF, SS, GND), and the inner layers for
an uninterrupted ground plane. Use the following step-
by-step guide:
1) Place the high-power components (Figure 1, C1, C3,
C4, Q1, Q2, L1, and R1) first, with their grounds
adjacent.
•Priority 1: Minimize current-sense resistor trace
lengths and ensure accurate current sensing with
Kelvin connections (Figure 9).
•Priority 2: Minimize ground trace lengths in the
high-current paths (discussed below).
•Priority 3: Minimize other trace lengths in the high
current paths.
Use >5mm-wide traces
CIN to high-side MOSFET drain: 10mm max
length
Rectifier diode cathode to low-side MOSFET:
5mm max length
LX node (MOSFETs, rectifier cathode, inductor):
15mm max length
Ideally, surface-mount power components are butted up
to one another with their ground terminals almost touch-
ing. These high-current grounds are then connected to
each other with a wide filled zone of top-layer copper so
they don’t go through vias. The resulting top layer “sub-
ground-plane” is connected to the normal inner-layer
ground plane at the output ground terminals, which
ensures that the IC’s analog ground is sensing at the sup-
ply’s output terminals without interference from IR drops
and ground noise. Other high-current paths should also
be minimized, but focusing primarily on short ground and
current-sense connections eliminates about 90% of all PC
board layout problems.
2) Place the IC and signal components. Keep the main
switching nodes (LX nodes) away from sensitive
analog components (current-sense traces and REF
capacitor). Place the IC and analog components on
the opposite side of the board from the power-
switching node. Important: the IC must be no more
than 10mm from the current-sense resistors. Keep
the gate-drive traces (DH_, DL_, and BST_) shorter
than 20mm and route them away from CSH_, CSL_,
and REF.
3) Use a single-point star ground where the input
ground trace, power ground (sub-ground-plane), and
normal ground plane meet at the supply’s output
ground terminal. Connect both IC ground pins and all
IC bypass capacitors to the normal ground plane.
MAX1901/MAX1902/MAX1904
SENSE RESISTOR
HIGH-CURRENT PATH
Figure 9. Kelvin Connections for the Current-Sense Resistors
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
28 ______________________________________________________________________________________
2.2µF
5
RESET
FB5
MAX1902
PGND
SEQ
REF
11
9
15
12
13
14
20
19
17
16 Q3
Q4
T2
1:2.2
R2
D5
D2
18
POWER-GOOD
7
10 8
5V ON/OFF
SKIP
DL5
LX5
DH5
BST5
VDD
2.2µF
0.1µFC2
0.1µF
1µF
1N5819
5V OUTPUT
GND
2.5V REF
3
*
2
1
24
Q1
D1
Q2
L1
R1 0.1µF
0.1µF
1N5819
3.3V OUTPUT (3A)
ON/OFF
*
TIME/ON5
RUN/ON3
FB3
28
3V ON/OFF
26
25
27
CSL5
CSH5
CSL3
CSH3
DL3
LX3
DH3
BST3
SHDN
SYNC
INPUT
6.5V TO 28V
4
23
22
10Ω
621
V+ VL
0.1µF
0.1µF
4.7µF
4.7µF
12OUT
C3
C1
C4
TO 3.3V OUTPUT TO 5V OUTPUT
12V AT 120mA
5V ALWAYS ON
*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED
FOR THE MAX1902 ONLY (SEE THE OUTPUT OVERVOLTAGE PROTECTION
AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).
**
Figure 10. Triple Output Application for MAX1902
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 29
OPEN
MAX1901
MAX1904
V+ SHDN VL
SECFB
INPUT
6V TO 24V
C3
10Ω
ON/OFF
GND
REF SEQ SYNC
1µF
5V ALWAYS ON
Q1
ON/OFF
ON/OFF
0.1µF
0.1µF
4.7µF
4.7µF
0.1µF
Q3
DL3
CSH3
CSL3
FB3
RESET RESET OUTPUT
SKIP
STEER
L1
R1
5V OUTPUT
C1 DL5
LX5
DH5
BST5 BST3
DH3
LX3
PGND
CSL5
CSH5
RUN/ON3
TIME/ON5
0Ω
FB5
0.1µF
0.1µF
L2 R2 3.3V OUTPUT
*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED
FOR THE MAX1901 ONLY (SEE THE OUTPUT OVERVOLTAGE PROTECTION
AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).
*
**
OPEN
0Ω
*Q4
1N5819
Q2
1N5819
C2
Figure 11. Dual 6A Notebook Computer Power Supply
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
30 ______________________________________________________________________________________
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RUN/ON3
DH3
LX3
BST3
DL3
SHDN
SEQ
V+
VL
PGND
DL5
BST5
LX5
DH5
CSH5
CSL5
FB5
RESET
SKIP
REF
GND
TIME/ON5
SYNC
VDD
12OUT
FB3
CSL3
CSH3
SSOP
MAX1902
TOP VIEW
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RUN/ON3
DH3
LX3
BST3
DL3
SHDN
SEQ
V+
VL
PGND
DL5
BST5
LX5
DH5
CSH5
CSL5
FB5
RESET
SKIP
REF
GND
TIME/ON5
SYNC
SECFB
STEER
FB3
CSL3
CSH3
MAX1901
MAX1904
32
31
30
29
28
27
26
N.C.
FB3
CSL3
CSH3
RUN/ON3
DH3
LX3
25 N.C.
9
10
11
12
13
14
15
RESET
FB5
CSL5
CSH5
SEQ
DH5
LX5
16N.C.
17
18
19
20
21
22
23
BST5
DL5
PGND
VL
V+
SHDN
DL3
8
7
6
5
4
3
2
SKIP
REF
N.C.
GND
TIME/ON5
SYNC
SECFB
MAX1901
MAX1904
32 THIN QFN 5mm × 5mm
1STEER 24 BST3
32
31
30
29
28
27
26
N.C.
FB3
CSL3
CSH3
RUN/ON3
DH3
LX3
25 N.C.
9
10
11
12
13
14
15
RESET
FB5
CSL5
CSH5
SEQ
DH5
LX5
16N.C.
17
18
19
20
21
22
23
BST5
DL5
PGND
VL
V+
SHDN
DL3
8
7
6
5
4
3
2
SKIP
REF
N.C.
GND
TIME/ON5
SYNC
VDD
MAX1902
32 THIN QFN 5mm × 5mm
112OUT 24 BST3
Pin Configurations
Selector Guide
DEVICE AUXILLARY OUTPUT SECONDARY FEEDBACK OVER/UNDERVOLTAGE
PROTECTION
MAX1901 None (SECFB input) Selectable (STEER pin) Yes
MAX1902 12V Linear Regulator Feeds into the 5V SMPS Yes
MAX1904 None (SECFB input) Selectable (STEER pin) No
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
______________________________________________________________________________________ 31
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056 C
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
7.90
H
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX N
A
D
eA1 L
C
HE
N
12
B
0.068
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
32 ______________________________________________________________________________________
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15 C B
0.15 C A
DOCUMENT CONTROL NO.
21-0140
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
PROPRIETARY INFORMATION
APPROVAL
TITLE:
C
REV.
2
1
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45∞
L
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
k
L
L
MAX1901/MAX1902/MAX1904
500kHz Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
2
2
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
COMMON DIMENSIONS EXPOSED PAD VARIATIONS
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
C
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
