22-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
●DELTA-SIGMA A/D CONVERTER
●22 BITS NO MISSING CODES
●20 BITS EFFECTIVE RESOLUTION AT 10Hz
AND 16 BITS AT 1000Hz
●LOW POWER: 1.4mW
●DIFFERENTIAL INPUTS
●PROGRAMMABLE GAIN AMPLIFIER
●SPI™ COMPATIBLE SSI INTERFACE
●PROGRAMMABLE CUTOFF FREQUENCY
UP TO 6.25kHz
●INTERNAL/EXTERNAL REFERENCE
●ON-CHIP SELF-CALIBRATION
●ADS1213 INCLUDES 4-CHANNEL MUX
DESCRIPTION
The ADS1212 and ADS1213 are precision, wide dynamic
range, delta-sigma Analog-to-Digital (A/D) converters with
24-bit resolution operating from a single +5V supply. The
differential inputs are ideal for direct connection to transduc-
ers or low-level voltage signals. The delta-sigma architec-
ture is used for wide dynamic range and to ensure 22 bits of
no-missing-code performance. An effective resolution of 20
bits is achieved through the use of a very low-noise input
amplifier at conversion rates up to 10Hz. Effective resolu-
tions of 16 bits can be maintained up to a sample rate of
1kHz through the use of the unique Turbo Modulator mode
of operation. The dynamic range of the converters is further
increased by providing a low-noise programmable gain
amplifier with a gain range of 1 to 16 in binary steps.
The ADS1212 and ADS1213 are designed for high-resolution
measurement applications in smart transmitters, industrial
process control, weigh scales, chromatography and portable
instrumentation. Both converters include a flexible synchro-
nous serial interface that is SPI compatible and also offers a
two-wire control mode for low-cost isolation.
The ADS1212 is a single channel converter and is offered in
both DIP-18 and SO-18 packages. The ADS1213 includes a
4-channel input multiplexer and is available in DIP-24,
SO-24, and SSOP-28 packages.
APPLICATIONS
●INDUSTRIAL PROCESS CONTROL
●INSTRUMENTATION
●BLOOD ANALYSIS
●SMART TRANSMITTERS
●PORTABLE INSTRUMENTS
●WEIGH SCALES
●PRESSURE TRANSDUCERS
ADS1212
ADS1213
ADS1212
ADS1213
ADS1213
ADS1212
ADS1213
PGA
+2.5V
Reference +3.3V Bias
Generator Clock Generator
Serial Interface
Second-Order
∆∑
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
MODE
DSYNC CS DRDY
A
IN
P
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
MUX
ADS1213 Only ADS1212, 1213
A
IN
1P
A
IN
1N
A
IN
2P
A
IN
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
PATENTS PENDING
www.ti.com
Copyright © 1996-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SBAS064B – JANUARY 1996 – REVISED FEBRUARY 2004
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADS1212, 1213
2SBAS064A
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled,
and external 2.5V reference, unless otherwise specified.
SPECIFICATIONS
ADS1212U, P/ADS1213U, P, E
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Input Voltage Range(1) 0+5V
With VBIAS(2) –10 +10 V
Input Impedance G = Gain, TMR = Turbo Mode Rate 20/(G • TMR)(3) MΩ
Programmable Gain Amplifier User Programmable: 1, 2, 4, 8, or 16 1 16
Input Capacitance 5pF
Input Leakage Current At +25°C550pA
TMIN to TMAX 1nA
SYSTEMS PERFORMANCE
No Missing Codes fDATA = 10Hz 22 Bits
fDATA = 60Hz 19 Bits
fDATA = 100Hz, TMR of 4 21 Bits
fDATA = 250Hz, TMR of 8 20 Bits
fDATA = 500Hz, TMR of 16 20 Bits
fDATA = 1000Hz, TMR of 16 18 Bits
Integral Linearity fDATA = 60Hz ±0.0015 %FSR
fDATA = 1000Hz, TMR of 16 ±0.0015 %FSR
Integral Linearity (Single-Ended) 0.01 %FSR
Unipolar Offset Error(4) See Note 5
Unipolar Offset Drift(6) 1 ppm/°C
Gain Error(4) See Note 5
Gain Error Drift(6) 4 ppm/°C
Common-Mode Rejection(9) At DC, TMIN to TMAX 90 100 dB
50Hz, fDATA = 50Hz(7) 160 dB
60Hz, fDATA = 60Hz(7) 160 dB
Normal-Mode Rejection 50Hz, fDATA = 50Hz(7) 100 dB
60Hz, fDATA = 60Hz(7) 100 dB
Output Noise See Typical Performance Curves
Power Supply Rejection DC, 50Hz, and 60Hz 60 dB
VOLTAGE REFERENCE
Internal Reference (REFOUT) 2.4 2.5 2.6 V
Drift 25 ppm/°C
Noise 50 µVp-p
Load Current Source or Sink 1 mA
Output Impedance 2Ω
External Reference (REFIN) 2.0 3.0 V
Load Current 2.5 µA
VBIAS Output Using Internal Reference 3.15 3.3 3.45 V
Drift 50 ppm/°C
Load Current Source or Sink 10mA
DIGITAL INPUT/OUTPUT
Logic Family TTL Compatible CMOS
Logic Level: (all except XIN)
VIH IIH = +5µA 2.0 DVDD +0.3 V
VIL IIL = +5µA –0.3 0.8 V
VOH IOH = 2 TTL Loads 2.4 V
VOL IOL = 2 TTL Loads 0.4 V
XIN Input Levels: VIH 3.5 DVDD +0.3 V
VIL –0.3 0.8 V
XIN Frequency Range (fXIN) 0.5 2.5 MHz
Output Data Rate (fDATA) User Programmable and TMR = 1 to 16 0.96 6,250 Hz
fXIN = 500kHz 0.48 3,125 Hz
fXIN = 2.5MHz 2.4 15,625 Hz
Data Format User Programmable
Two’s Complement
or Offset Binary
SYSTEM CALIBRATION
Offset and Full-Scale Limits VFS = Full-Scale Differential Voltage(8)
0.7 • (2 • REFIN)/G
VFS – | VOS |V
OS = Offset Differential Voltage(8)
1.3 • (2 • REFIN)/G
ADS1212, 1213 3
SBAS064A
POWER SUPPLY REQUIREMENTS
Power Supply Voltage 4.75 5.25 V
Power Supply Current:
Analog Current 95 µA
Digital Current 185 µA
Additional Analog Current with
REFOUT Enabled 1.8 mA
VBIAS Enabled No Load 1 mA
Power Dissipation At +25°C 1.4 mW
TMIN to TMAX 1.8 mW
TMR of 16 6 8.5 mW
fXIN = 2.5MHz 2.2 mW
fXIN = 2.5MHz, TMR of 16 7.5 mW
Sleep Mode 0.45 mW
TEMPERATURE RANGE
Specified –40 +85 °C
Storage –60 +125 °C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential (AINN = 2 • REFIN – AINP). If the input is single-ended (AINN or
AINP is fixed), then the full-scale range is one-half that of the differential range. (2) This range is set with external resistors and VBIAS (as described in the text).
Other ranges are possible. (3) Input impedance is higher with lower fXIN. (4) Applies after calibration. (5) After system calibration, these errors will be of the order
of the effective resolution of the converter. Refer to the Typical Performance Curves which apply to the desired mode of operation. (6) Recalibration can remove
these errors. (7) The specification also applies at fDATA/i, where i is 2, 3, 4, etc. (8) Voltages at the analog inputs must remain within AGND to AVDD. (9) The common-
mode rejection test is performed with 100mV differential input.
SPECIFICATIONS (Cont.)
ADS1212U, P/ADS1213U, P, E
PARAMETER CONDITIONS MIN TYP MAX UNITS
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled,
and external 2.5V reference, unless otherwise specified.
Analog Input: Current................................................ ±100mA, Momentary
±10mA, Continuous
Voltage ................................... AGND –0.3V to AVDD +0.3V
AVDD to DVDD ...........................................................................–0.3V to 6V
AVDD to AGND .........................................................................–0.3V to 6V
DVDD to DGND.........................................................................–0.3V to 6V
AGND to DGND ................................................................................ ±0.3V
REFIN Voltage to AGND............................................ –0.3V to AVDD +0.3V
Digital Input Voltage to DGND ..................................–0.3V to DVDD +0.3V
Digital Output Voltage to DGND ...............................–0.3V to DVDD +0.3V
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (Any package) .................................................. 500mW
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDERING INFORMATION
For the latest package and ordering information, see the
Package Option Addendum located at the end of this data
sheet.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ADS1212, 1213
4SBAS064A
PGA
+2.5V
Reference +3.3V Bias
Generator Clock Generator
Serial Interface
Second-Order
∆Σ
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
11
9
10
12
13
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
3
1
2
16 17 18 4 7 8
65 1415
DSYNC CS DRDYMODE
A
IN
P
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
ADS1212
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
AINP
AINN
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
ADS1212 SIMPLIFIED BLOCK DIAGRAM
ADS1212 PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
INP Noninverting Input.
2A
INN Inverting Input.
3 AGND Analog Ground.
4V
BIAS Bias Voltage Output, +3.3V nominal.
5 CS Chip Select Input.
6 DSYNC Control Input to Synchronize Serial Output Data.
7X
IN System Clock Input.
8X
OUT System Clock Output.
9 DGND Digital Ground.
10 DVDD Digital Supply, +5V nominal.
11 SCLK Clock Input/Output for serial data transfer.
12 SDIO Serial Data Input (can also function as Serial Data
Output).
13 SDOUT Serial Data Output.
14 DRDY Data Ready.
15 MODE SCLK Control Input (Master = 1, Slave = 0).
16 AVDD Analog Supply, +5V nominal.
17 REFOUT Reference Output, +2.5V nominal.
18 REFIN Reference Input.
TOP VIEW DIP/SOIC
ADS1212 PIN CONFIGURATION
ADS1212, 1213 5
SBAS064A
PGA
+2.5V
Reference +3.3V Bias
Generator Clock Generator
Serial Interface
Second-Order
∆∑
Modulator Third-Order
Digital Filter
Modulator Control
14
12
13
15
16
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
6 19 20 21 7 10 11
98 1718
DSYNC CS DRDYMODE
SCLK
DGND
DV
DD
SDIO
SDOUT
4
5
2
3
24
1
22
23
MUX
A
IN
1P
A
IN
1N
A
IN
2P
A
IN
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Micro Controller
ADS1213 SIMPLIFIED BLOCK DIAGRAM
ADS1213P AND ADS1213U PIN DEFINITIONS
TOP VIEW DIP/SOIC
ADS1213P AND ADS1213U PIN CONFIGURATION
PIN NO NAME DESCRIPTION
1A
IN3N Inverting Input Channel 3.
2A
IN2P Noninverting Input Channel 2.
3A
IN2N Inverting Input Channel 2.
4A
IN1P Noninverting Input Channel 1.
5A
IN1N Inverting Input Channel 1.
6 AGND Analog Ground.
7V
BIAS Bias Voltage Output, +3.3V nominal.
8 CS Chip Select Input.
9 DSYNC Control Input to Synchronize Serial Output Data.
10 XIN System Clock Input.
11 XOUT System Clock Output.
12 DGND Digital Ground.
13 DVDD Digital Supply, +5V nominal.
14 SCLK Clock Input/Output for serial data transfer.
15 SDIO Serial Data Input (can also function as Serial Data
Output).
16 SDOUT Serial Data Output.
17 DRDY Data Ready.
18 MODE SCLK Control Input (Master = 1, Slave = 0).
19 AVDD Analog Supply, +5V nominal.
20 REFOUT Reference Output: +2.5V nominal.
21 REFIN Reference Input.
22 AIN4P Noninverting Input Channel 4.
23 AIN4N Inverting Input Channel 4.
24 AIN3P Noninverting Input Channel 3.
ADS1213P
ADS1213U
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
ADS1212, 1213
6SBAS064A
ADS1213E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
NIC
NIC
CS
DSYNC
XIN
XOUT
DGND
AIN3P
AIN4N
AIN4P
REFIN
REFOUT
AVDD
MODE
NIC
NIC
DRDY
SDOUT
SDIO
SCLK
DVDD
ADS1213E PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
IN3N Inverting Input Channel 3.
2A
IN2P Noninverting Input Channel 2.
3A
IN2N Inverting Input Channel 2.
4A
IN1P Noninverting Input Channel 1.
5A
IN1N Inverting Input Channel 1.
6 AGND Analog Ground.
7V
BIAS Bias Voltage Output, +3.3V nominal.
8 NIC Not Internally Connected.
9 NIC Not Internally Connected.
10 CS Chip Select Input.
11 DSYNC Control Input to Synchronize Serial Output Data.
12 XIN System Clock Input.
13 XOUT System Clock Output.
14 DGND Digital Ground.
15 DVDD Digital Supply, +5V nominal.
16 SCLK Clock Input/Output for serial data transfer.
17 SDIO Serial Data Input (can also function as Serial Data
Output).
18 SDOUT Serial Data Output.
19 DRDY Data Ready.
20 NIC Not Internally Connected.
21 NIC Not Internally Connected.
22 MODE SCLK Control Input (Master = 1, Slave = 0).
23 AVDD Analog Supply, +5V nominal.
24 REFOUT Reference Output: +2.5V nominal.
25 REFIN Reference Input.
26 AIN4P Noninverting Input Channel 4.
27 AIN4N Inverting Input Channel 4.
28 AIN3P Noninverting Input Channel 3.
ADS1213E PIN CONFIGURATION
TOP VIEW SSOP
ADS1212, 1213 7
SBAS064A
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external
2.5V reference, unless otherwise noted.
24
22
20
18
16
14
12
10
8
EFFECTIVE RESOLUTION vs DATA RATE
(1MHz Clock)
Data Rate (Hz)
1 10 100 1k
Effective Resolution in Bits (rms)
PGA 1 PGA 4
PGA 2
PGA 16
PGA 8
24
22
20
18
16
14
12
10
8
EFFECTIVE RESOLUTION vs DATA RATE
(2.5MHz Clock)
Data Rate (Hz)
1 10 100 1k
Effective Resolution in Bits (rms)
PGA 1 PGA 2 PGA 4
PGA 16
PGA 8
LINEARITY vs TEMPERATURE
(60Hz Data Rate)
Analog Input Differential Voltage (V)
–5–4–3–2–1012345
Integral Nonlinearity (ppm)
8
6
4
2
0
–2
–4
–6
–40°C
+25°C
+85°C
24
22
20
18
16
14
12
EFFECTIVE RESOLUTION vs DATA RATE
(1MHz Clock)
Data Rate (Hz)
1 10 100 1k
Effective Resolution in Bits (rms)
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
24
22
20
18
16
14
12
EFFECTIVE RESOLUTION vs DATA RATE
(2.5MHz Clock)
Data Rate (Hz)
1 10 100 1k
Effective Resolution in Bits (rms)
Turbo 1
Turbo 2
Turbo 4
Turbo 16
Turbo 8
RMS NOISE vs INPUT VOLTAGE LEVEL
(60Hz Data Rate)
Analog Input Differential Voltage (V)
–5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0
RMS Noise (ppm)
14
12
10
8
6
4
ADS1212, 1213
8SBAS064A
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, AVDD = DVDD = +5V, fXIN = 1MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled, VBIAS disabled, and external
2.5V reference, unless otherwise noted.
POWER DISSIPATION vs PGA SETTING
(REF
OUT
Enabled)
PGA Setting
124816
Power Dissipation (mW)
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
ANALOG CURRENT vs PGA SETTING
(REF
OUT
Enabled)
PGA Setting
124816
Analog I
DD
(µA)
2700
2600
2500
2400
2300
2200
2100
2000
1900
1800
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
ANALOG CURRENT vs PGA SETTING
(External Reference; REF
OUT
Disabled)
PGA Setting
124816
Analog I
DD
(µA)
980
880
780
680
580
480
380
280
180
80
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
POWER DISSIPATION vs PGA SETTING
(External Reference; REF
OUT
Disabled)
PGA Setting
124816
Power Dissipation (mW)
6
5
4
3
2
1
0
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
ADS1212, 1213 9
SBAS064A
THEORY OF OPERATION
The ADS1212 and ADS1213 are precision, high dynamic
range, self-calibrating, 24-bit, delta-sigma A/D converters
capable of achieving very high resolution digital results.
Each contains a programmable gain amplifier (PGA); a
second-order delta-sigma modulator; a programmable digi-
tal filter; a microcontroller including the Instruction, Com-
mand and Calibration registers; a serial interface; a clock
generator circuit; and an internal 2.5V reference. The
ADS1213 includes a 4-channel input multiplexer.
In order to provide low system noise, common-mode rejec-
tion of 100dB and excellent power supply rejection, the
design topology is based on a fully differential switched
capacitor architecture. Turbo Mode, a unique feature of the
ADS1212/13, can be used to boost the sampling rate of the
input capacitor, which is normally 7.8kHz with a 1MHz
clock. By programming the Command Register, the sam-
pling rate can be increased to 15.6kHz, 31.2kHz, 62.5kHz,
or 125kHz. Each increase in sample rate results in an
increase in performance when maintaining the same output
data rate.
The programmable gain amplifier (PGA) of the ADS1212/
13 can be set to a gain of 1, 2, 4, 8 or 16—substantially
increasing the dynamic range of the converter and simplify-
ing the interface to the more common transducers (see Table
I). This gain is implemented by increasing the number of
samples taken by the input capacitor from 7.8kHz for a gain
of 1 to 125kHz for a gain of 16. Since the Turbo Mode and
PGA functions are both implemented by varying the sam-
pling frequency of the input capacitor, the combination of
PGA gain and Turbo Mode Rate is limited to 16 (see Table
II). For example, when using a Turbo Mode Rate of 8
(62.5kHz at 1MHz), the maximum PGA gain setting is 2.
The output data rate of the ADS1212/13 can be varied from
less than 1Hz to as much as 6.25kHz, trading off lower
resolution results for higher data rates. In addition, the data
rate determines the first null of the digital filter and sets the
–3dB point of the input bandwidth (see the Digital Filter
section). Changing the data rate of the ADS1212/13 does not
result in a change in the sampling rate of the input capacitor.
The data rate effectively sets the number of samples which
are used by the digital filter to obtain each conversion result.
A lower data rate results in higher resolution, lower input
bandwidth, and different notch frequencies than a higher
data rate. It does not result in any change in input impedance
or modulator frequency, or any appreciable change in power
consumption.
The ADS1212/13 also includes complete on-board calibra-
tion that can correct for internal offset and gain errors or
limited external system errors. Internal calibration can be
run when needed, or automatically and continuously in the
background. System calibration can be run as needed and the
appropriate input voltages must be provided to the ADS1212/
13. For this reason, there is no continuous system calibration
mode. The calibration registers are fully readable and writ-
able. This feature allows for switching between various
configurations—different data rates, Turbo Mode Rates, and
gain settings—without re-calibrating.
The various settings, rates, modes, and registers of the
ADS1212/13 are read or written via a synchronous serial
interface. This interface can operate in either a self-clocked
mode (Master Mode) or an externally clocked mode (Slave
Mode). In the Master Mode, the serial clock (SCLK) fre-
quency is one-quarter of the ADS1212/13 XIN clock fre-
quency.
The high resolution and flexibility of the ADS1212/13 allow
these converters to fill a wide variety of A/D conversion
tasks. In order to ensure that a particular configuration will
meet the design goals, there are several important items
which must be considered. These include (but are certainly
not limited to) the needed resolution, required linearity,
desired input bandwidth, power consumption goal, and sen-
sor output voltage.
The remainder of this data sheet discusses the operation of
the ADS1212/13 in detail. In order to allow for easier
comparison of different configurations, “effective resolu-
tion” is used as the figure of merit for most tables and
graphs. For example, Table III shows a comparison between
data rate (and –3dB input bandwidth) versus PGA setting at
a Turbo Mode Rate of 1 and a clock rate of 1MHz. See the
Definition of Terms section for a definition of effective
resolution.
ANALOG ANALOG INPUT
INPUT(1) UTILIZING VBIAS(1,2)
FULL- EXAMPLE FULL- EXAMPLE
SCALE VOLTAGE SCALE VOLTAGE
GAIN RANGE RANGE(3) RANGE RANGE(3)
SETTING (V) (V) (V) (V)
1 10 0 to 5 40 ±10
2 5 1.25 to 3.75 20 ±5
4 2.5 1.88 to 3.13 10 ±2.5
8 1.25 2.19 to 2.81 5 ±1.25
16 0.625 2.34 to 2.66 2.5 ±0.625
NOTE: (1) With a 2.5V reference, such as the internal reference. (2) This
example utilizes the circuit in Figure 12. Other input ranges are possible. (3)
The ADS1212/13 allows common-mode voltage as long as the absolute
input voltage on AINP or AINN does not go below AGND or above AVDD.
TABLE I. Full-Scale Range vs PGA Setting.
TURBO MODE RATE AVAILABLE PGA SETTINGS
1 1, 2, 4, 8, 16
2 1, 2, 4, 8
4 1, 2, 4
8 1, 2
16 1
TABLE II. Available PGA Settings vs Turbo Mode Rate.
ADS1212, 1213
10 SBAS064A
DATA -3DB
RATE FREQUENCY
(HZ) (HZ) G = 1 G = 2 G = 4 G = 8 G = 16
10 2.62 20 20 20 19 18
25 6.55 19 19 19 18 18
30 7.86 19 19 18 18 17
50 13.1 17 17 17 17 16
60 15.7 17 17 17 16 16
100 26.2 15 15 15 15 15
250 65.5 12 12 12 12 12
EFFECTIVE RESOLUTION (BITS RMS) For example, when the converter is configured with a
2.5V reference and placed in a gain setting of 2, the
typical input voltage range is 1.25V to 3.75V (common-
mode voltage = 2.5V). However, an input range of 0V to
2.5V (common-mode voltage = 1.25V) or 2.5V to 5V
(common-mode voltage = 3.75V) would also cover the
converter’s full-scale range.
Voltage Span—This is simply the magnitude of the typical
analog input voltage range. For example, when the converter
is configured with a 2.5V reference and placed in a gain
setting of 2, the input voltage span is 2.5V.
Least Significant Bit (LSB) Weight—This is the theoreti-
cal amount of voltage that the differential voltage at the
analog input would have to change in order to observe a
change in the output data of one least significant bit. It is
computed as follows:
where N is the number of bits in the digital output.
Effective Resolution—The effective resolution of the
ADS1212/13 in a particular configuration can be expressed
in two different units: bits rms (referenced to output) and
microvolts rms (referenced to input). Computed directly
from the converter’s output data, each is a statistical calcu-
lation based on a given number of results. Knowing one, the
other can be computed as follows:
The 10V figure in each calculation represents the full-scale
range of the ADS1212/13 in a gain setting of 1. This means
that both units are absolute expressions of resolution—the
performance in different configurations can be directly com-
pared regardless of the units. Comparing the resolution of
different gain settings expressed in bits rms requires ac-
counting for the PGA setting.
Main Controller—A generic term for the external micro-
controller, microprocessor, or digital signal processor which
is controlling the operation of the ADS1212/13 and receiv-
ing the output data.
TABLE III. Effective Resolution vs Data Rate and Gain
Setting. (Turbo Mode Rate of 1 and a 1MHz
clock.)
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog Input Differential Voltage—For an analog signal
that is fully differential, the voltage range can be compared
to that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1212 are at 2.5V, then the differ-
ential voltage is 0V. If one is at 0V and the other at 5V, then
the differential voltage magnitude is 5V. But, this is the case
regardless of which input is at 0V and which is at 5V, while
the digital output result is quite different.
The analog input differential voltage is given by the follow-
ing equation: AINP – AINN. Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced when-
ever the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the positive full-
scale output is produced when the analog input differential
is 2.5V. The negative full-scale output is produced when the
differential is –2.5V. In each case, the actual input voltages
must remain within the AGND to AVDD range (see Table I).
Actual Analog Input Voltage—The voltage at any one
analog input relative to AGND.
Full-Scale Range (FSR)—As with most A/D converters,
the full-scale range of the ADS1212/13 is defined as the
“input” which produces the positive full-scale digital output
minus the “input” which produces the negative full-scale
digital output.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [2.5V (positive full scale) minus –2.5V (negative
full scale)] = 5V.
Typical Analog Input Voltage Range—This term de-
scribes the actual voltage range of the analog inputs which
will cover the converter’s full-scale range, assuming that
each input has a common-mode voltage that is greater than
REFIN/PGA and smaller than (AVDD – REFIN/PGA).
LSB Weight =Full−Scale Range
2
N
ER in bits rms =
20•log
10V
PGA
ER in Vrms
−1.76
6.02
ER in Vrms =
10
10V
PGA
6.02•ER in bits rms +1.76
20
ADS1212, 1213 11
SBAS064A
f
DATA
=f
XIN
•Turbo Mode
128• Decimation Ratio +1
()
fMOD =fXIN •Turbo Mode
128
fXIN—The frequency of the crystal oscillator or CMOS
compatible input signal at the XIN input of the ADS1212/13.
fMOD—The frequency or speed at which the modulator of the
ADS1212/13 is running, given by the following equation:
fSAMP—The frequency or switching speed of the input
sampling capacitor. The value is given by the following
equation:
fDATA, tDATA—The frequency of the digital output data
produced by the ADS1212/13 or the inverse of this (the
period), respectively, fDATA is also referred to as the data rate.
Conversion Cycle—The term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the tDATA time period.
However, each digital output is actually based on the modu-
lator results from the last three tDATA time periods.
DIGITAL FILTER
The digital filter of the ADS1212/13 computes the output
result based on the most recent results from the delta-sigma
modulator. The number of modulator results that are used
depend on the decimation ratio set in the Command Regis-
ter. At the most basic level, the digital filter can be thought
of as simply averaging the modulator results and presenting
this average as the digital output.
While the decimation ratio determines the number of modu-
lator results to use, the modulator runs faster at higher Turbo
Modes. These two items, together with the ADS1212/13
clock frequency, determine the output data rate:
Also, since the conversion result is essentially an average,
the data rate determines where the resulting notches are in
the digital filter. For example, if the output data rate is 1kHz,
then a 1kHz input frequency will average to zero during the
1ms conversion cycle. Likewise, a 2kHz input frequency
will average to zero, etc.
In this manner, the data rate can be used to set specific notch
frequencies in the digital filter response (see Figure 1 for the
normalized response of the digital filter). For example, if the
rejection of power line frequencies is desired, then the data
rate can simply be set to the power line frequency. Figures
2 and 3 show the digital filter response for a data rate of
50Hz and 60Hz, respectively.
fSAMP =fXIN •Turbo Mode•Gain Setting
128
FILTER RESPONSE
Frequency (Hz)
–40
–60
–80
–100
–120
–140
–16045 46 47 48 49 50 51 52 53 54 55
FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160 0 50 100 150 200 250 300
Gain (dB) Gain (dB)
NORMALIZED DIGITAL FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160 0123456
Gain (dB)
FIGURE 3. Digital Filter Response at a Data Rate of 60Hz.
FIGURE 1. Normalized Digital Filter Response.
FIGURE 2. Digital Filter Response at a Data Rate of 50Hz.
If the effective resolution at a 50Hz or 60Hz data rate is not
adequate for the particular application, then power line fre-
quencies could still be rejected by operating the ADS1212/13
at 25/30Hz, 16.7/20Hz, 12.5/15Hz, etc. If a higher data rate
is needed, then power line frequencies must either be rejected
before conversion (with an analog notch filter) or after
conversion (with a digital notch filter running on the main
controller).
FILTER RESPONSE
Frequency (Hz)
–40
–60
–80
–100
–120
–140
–16055 56 57 58 59 60 61 62 63 64 65
FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160 0 50 100 150 200 250 300
Gain (dB) Gain (dB)
fDATA =fXIN •Turbo Mode
128• Decimation Ratio +1
()
,t
DATA =1
fDATA
ADS1212, 1213
12 SBAS064A
Filter Equation
The digital filter is described by the following transfer
function:
where N is the Decimation Ratio.
This filter has a (sin(x)/x)3 response and is referred to a sinc3
filter. For the ADS1212/13, this type of filter allows the data
rate to be changed over a very wide range (nearly four orders
of magnitude). However, the –3dB point of the filter is 0.262
times the data rate. And, as can be seen in Figures 1 and 2,
the rejection in the stopband (frequencies higher than the
first notch frequency) may only be –40dB.
These factors must be considered in the overall system
design. For example, with a 50Hz data rate, a significant
signal at 75Hz may alias back into the passband at 25Hz.
The analog front end can be designed to provide the needed
attenuation to prevent aliasing, or the system may simply
provide this inherently. Another possibility is increasing the
data rate and then post filtering with a digital filter on the
main controller.
Filter Settling
The number of modulator results used to compute each
conversion result is three times the Decimation Ratio. This
means that any step change (or any channel change for the
ADS1213) will require at least three conversions to fully
settle. However, if the change occurs asynchronously, then at
least four conversions are required to ensure complete set-
tling. For example, on the ADS1213, the fourth conversion
result after a channel change will be valid (see Figure 4).
|H(f)|=sin π•f•N
f
MOD
N•sin π•f
f
MOD
3
the effective resolution of the output data at a given data rate,
but there is also an increase in power dissipation. For Turbo
Mode Rates 2 and 4, the increase is slight. For rates 8 and
16, the increase is more substantial. See the Typical Perfor-
mance Curves for more information.
In a Turbo Mode Rate of 16, the ADS1212/13 can offer 16
bits of effective resolution at a 1kHz data rate. A comparison
of effective resolution versus Turbo Mode Rates and output
data rates is shown in Table IV while Table V shows the
corresponding noise level in µVrms.
TURBO MODE
The ADS1212/13 offers a unique Turbo Mode feature which
can be used to increase the modulator sampling rate by 2, 4,
8, or 16 times normal. With the increase of modulator
sampling frequency, there can be a substantial increase in
DATA TURBO TURBO TURBO TURBO TURBO
RATE MODE MODE MODE MODE MODE
(HZ) RATE 1 RATE 2 RATE 4 RATE 8 RATE 16
10 20 21 21
20 19 20 21 21
40 18 20 21 21 21
50 17 19 20 21 21
60 17 19 20 21 21
100 15 17 19 21 21
250 12 14 16 19 20
1000 12 14 16
EFFECTIVE RESOLUTION (BITS RMS)
FIGURE 4. Asynchronous ADS1212/13 Analog Input Volt-
age Step or ADS1213 Channel Change to Fully
Settled Output Data.
DRDY
Serial
I/O
Valid
Data Valid
Data Valid
Data Valid
Data
Data
not
Valid
Data
not
Valid
Data
not
Valid
Significant Analog Input Change
or
ADS1213 Channel Change
t
DATA
TABLE IV. Effective Resolution vs Data Rate and Turbo Mode
Rate. (Gain setting of 1 and 1MHz clock.)
DATA TURBO TURBO TURBO TURBO TURBO
RATE MODE MODE MODE MODE MODE
(Hz) RATE 1 RATE 2 RATE 4 RATE 8 RATE 16
10 7.6 3.8 3.8
20 15 7.6 3.8 3.8
40 30 7.6 3.8 3.8 3.8
50 60 15 7.6 3.8 3.8
60 60 15 7.6 3.8 3.8
100 240 60 15 3.8 3.8
250 1900 480 120 15 7.6
1000 1900 480 120
NOISE LEVEL (µVrms)
TABLE V. Noise Level vs Data Rate and Turbo Mode Rate.
(Gain setting of 1 and 1MHz clock.)
The Turbo Mode feature allows trade-offs to be made
between the ADS1212/13 XIN clock frequency, power dissi-
pation, and effective resolution. If a 0.5MHz clock is avail-
able but a 1MHz clock is needed to achieve the desired
performance, a Turbo Mode Rate of 2X will result in the
same effective resolution. Table VI provides a comparison
of effective resolution at various clock frequencies, data
rates, and Turbo Mode Rates.
DATA XIN CLOCK TURBO EFFECTIVE
RATE FREQUENCY MODE RESOLUTION
(Hz) (MHz) RATE (Bits rms)
60 2 2 20
60 1 4 20
60 0.5 8 20
100 2 2 19
100 1 4 19
100 0.5 8 19
TABLE VI. Effective Resolution vs Data Rate, Clock
Frequency, and Turbo Mode Rate. (Gain set-
ting of 1.)
ADS1212, 1213 13
SBAS064A
The Turbo Mode Rate (TMR) is programmed via the Sam-
pling Frequency bits of the Command Register. Due to the
increase in input capacitor sampling frequency, higher Turbo
Mode settings result in lower analog input impedance;
AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR)
where G is the gain setting. Because the modulator rate also
changes in direct relation to the Turbo Mode setting, higher
values result in a lower impedance for the REFIN input:
REFIN Impedance (Ω) = (1MHz/fXIN)•5E6/TMR
The Turbo Mode Rate can be set to 1, 2, 4, 8, or 16. Consult
the graphs shown in the Typical Performance Curves for full
details on the performance of the ADS1212/13 operating in
different Turbo Mode Rates. Keep in mind that higher Turbo
Mode Rates result in fewer available gain settings as shown
in Table II.
PROGRAMMABLE GAIN AMPLIFIER
The programmable gain amplifier gain setting is programmed
via the PGA Gain bits of the Command Register. Changes
in the gain setting (G) of the programmable gain amplifier
results in an increase in the input capacitor sampling fre-
quency. Thus, higher gain settings result in a lower analog
input impedance:
AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR)
where TMR is the Turbo Mode Rate. Because the modulator
speed does not depend on the gain setting, the input imped-
ance seen at REFIN does not change.
The PGA can be set to gains of 1, 2, 4, 8, or 16. These gain
settings with their resulting full-scale range and typical
voltage range are shown in Table I. Keep in mind that higher
Turbo Mode Rates result in fewer available gain settings as
shown in Table II.
SOFTWARE GAIN
The excellent performance, flexibility, and low cost of the
ADS1212/13 allow the converter to be considered for de-
signs which would not normally need a 24-bit ADC. For
example, many designs utilize a 12-bit converter and a high-
gain INA or PGA for digitizing low amplitude signals. For
some of these cases, the ADS1212/13 by itself may be a
solution, even though the maximum gain is limited to 16.
To get around the gain limitation, the digital result can
simply be shifted up by “n” bits in the main controller—
resulting in a gain of “n” times G, where G is the gain
setting. While this type of manipulation of the output data
is obvious, it is easy to miss how much the gain can be
increased in this manner on a 24-bit converter.
For example, shifting the result up by three bits when the
ADS1212/13 is set to a gain of 16 results in an effective gain
of 128. At lower data rates, the converter can easily provide
more than 12 bits of resolution. Even higher gains are
possible. The limitation is a combination of the needed data
rate, desired noise performance, and desired linearity.
CALIBRATION
The ADS1212/13 offers several different types of calibra-
tion, and the particular calibration desired is programmed
via the Command Register. In the case of Background
Calibration, the calibration will repeat at regular intervals
indefinitely. For all others, the calibration is performed once
and then normal operation is resumed.
Each type of calibration is covered in detail in its respective
section. In general, calibration is recommended immediately
after power-on and whenever there is a “significant” change
in the operating environment. The amount of change which
should cause a re-calibration is dependent on the applica-
tion, effective resolution, etc. Where high accuracy is impor-
tant, re-calibration should be done on changes in tempera-
ture and power supply. In all cases, re-calibration should be
done when the gain, Turbo Mode, or data rate is changed.
After a calibration has been accomplished, the Offset Cali-
bration Register and the Full-Scale Calibration Register
contain the results of the calibration. The data in these
registers are accurate to the effective resolution of the
ADS1212/13’s mode of operation during the calibration.
Thus, these values will show a variation (or noise) equiva-
lent to a regular conversion result.
For those cases where this error must be reduced, it is
tempting to consider running the calibration at a slower data
rate and then increasing the converter’s data rate after the
calibration is complete. Unfortunately, this will not work as
expected. The reason is that the results calculated at the
slower data rate would not be valid for the higher data rate.
Instead, the calibration should be done repeatedly. After
each calibration, the results can be read and stored. After the
desired number of calibrations, the main controller can
compute an average and write this value into the calibration
registers. The resulting error in the calibration values will be
reduced by the square root of the number of calibrations
which were averaged.
The calibration registers can also be used to provide system
offset and gain corrections separate from those computed by
the ADS1212/13. For example, these might be burned into
E2PROM during final product testing. On power-on, the
main controller would load these values into the calibration
registers. A further possibility is a look-up table based on the
current temperature.
Note that the values in the calibration registers will vary from
configuration to configuration and from part to part. There is
no method of reliably computing what a particular calibration
register should be to correct for a given amount of system
error. It is possible to present the ADS1212/13 with a known
amount of error, perform a calibration, read the desired
calibration register, change the error value, perform another
calibration, read the new value and use these values to
interpolate an intermediate value.
ADS1212, 1213
14 SBAS064A
Valid
Data
DRDY
Serial
I/O
Valid
Data
SOC
(1)
t
DATA
Normal
Mode
Offset
Calibration on
System Offset
(2)
Analog
Input
Conversion
System Offset
Calibration Mode
Possibly
Valid
Data
Possibly
Valid
Data
Normal
Mode
NOTES: (1) SOC = System Offset Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
FIGURE 5. Self-Calibration Timing.
Mode bits are reset to 000 (Normal Mode). A single conver-
sion is done with DRDY HIGH. After this conversion, the
DRDY signal goes LOW indicating resumption of normal
operation.
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the offset calibration
is performed. In this case, the digital filter already contains
a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. In addition, the
offset calibration error will be the rms sum of the conversion
error and the noise on the system offset voltage. See the
System Calibration Limits section for information regarding
the limits on the magnitude of the system offset voltage.
System Full-Scale Calibration
A system full-scale calibration is performed after the bits
011 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 7). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The full-scale calibration will be per-
formed on the differential input voltage (2 • REFIN/G)
present at the converter’s input over the next three conver-
sion periods (four in Slave Mode). When this is done, the
Operation Mode bits are reset to 000 (Normal Mode). A
single conversion is done with DRDY HIGH. After this
conversion, the DRDY signal goes LOW indicating resump-
tion of normal operation.
FIGURE 7. System Full-Scale Calibration Timing.
FIGURE 6. System Offset Calibration Timing.
Valid
Data
DRDY
Serial
I/O
Valid
Data
SC
(1)
t
DATA
Normal
Mode
Valid
Data Valid
Data
Normal
Mode
Offset
Calibration on
Internal Offset
(2)
Self-Calibration
Mode
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
Valid
Data
DRDY
Serial
I/O
Valid
Data
SFSC(1)
tDATA
Normal
Mode
Full-Scale
Calibration on
System Full-Scale(2)
Analog
Input
Conversion
System Full-Scale
Calibration Mode
Possibly
Valid
Data
Possibly
Valid
Data
Normal
Mode
NOTES: (1) SFSC = System Full-Scale Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
Self-Calibration
A self-calibration is performed after the bits 001 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This initiates the following sequence
at the start of the next conversion cycle (see Figure 5). The
DRDY signal will not go LOW but will remain HIGH and
will continue to remain HIGH throughout the calibration
sequence. The inputs to the sampling capacitor are discon-
nected from the converter’s analog inputs and are shorted
together. An offset calibration is performed over the next
three conversion periods (four in Slave Mode). Then, the
input to the sampling capacitor is connected across REFIN,
and a full-scale calibration is performed over the next three
conversions.
After this, the Operation Mode bits are reset to 000 (Normal
Mode) and the input capacitor is reconnected to the input.
Conversions proceed as usual over the next three cycles in
order to fill the digital filter. DRDY remains HIGH during
this time. On the start of the fourth cycle , DRDY goes LOW
indicating valid data and resumption of normal operation.
System Offset Calibration
A system offset calibration is performed after the bits 010
have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 6). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be per-
formed on the differential input voltage present at the
converter’s input over the next three conversion periods
(four in Slave Mode). When this is done, the Operation
ADS1212, 1213 15
SBAS064A
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the full-scale calibra-
tion is performed. In this case, the digital filter already
contains a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. The calibration
error will be a sum of the rms noise on the conversion result
and the input signal noise. See the System Calibration Limits
section for information regarding the limits on the magni-
tude of the system full-scale voltage.
Pseudo System Calibration
The Pseudo System Calibration is performed after the bits
100 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 8). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed
on the differential input voltage present at the converter’s
input over the next three conversion periods (four in Slave
Mode). Then, the input to the sampling capacitor is discon-
nected from the converter’s analog input and connected
across REFIN. A gain calibration is performed over the next
three conversions.
After this, the Operation Mode bits are reset to 000 (Nor-
mal Mode) and the input capacitor is then reconnected to
the input. Conversions proceed as usual over the next three
cycles in order to fill the digital filter. DRDY remains
HIGH during this time. On the next cycle, the DRDY signal
goes LOW indicating valid data and resumption of normal
operation.
The system offset calibration range of the ADS1212/13
is limited and is listed in the Specifications Table. For
more information on how to use these specifications, see
the System Calibration Limits section. To calculate VOS,
use 2 • REFIN/ GAIN for VFS.
Background Calibration
The Background Calibration Mode is entered after the bits
101 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
continuous sequence (see Figure 9). At the start of the next
conversion cycle, the DRDY signal will not go LOW but
will remain HIGH. The inputs to the sampling capacitor are
disconnected from the converter’s analog input and shorted
together. An offset calibration is performed over the next
three conversion periods (in Slave Mode, the very first offset
calibration requires four periods, and all subsequent offset
calibrations require three periods). Then, the input capacitor
is reconnected to the input. Conversions proceed as usual
over the next three cycles in order to fill the digital filter.
DRDY remains HIGH during this time. On the next cycle,
the DRDY signal goes LOW indicating valid data.
FIGURE 8. Pseudo System Calibration Timing.
FIGURE 9. Background Calibration Timing.
Valid
Data
DRDY
Serial
I/O
Valid
Data
PSC
(1)
t
DATA
Normal
Mode
Valid
Data Valid
Data
Normal
Mode
Offset
Calibration on
System Offset
(2)
Pseudo System
Calibration Mode
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
Normal
Mode Background Calibration
Mode
Valid
Data
DRDY
Serial
I/O
Valid
Data
BC(1)
tDATA
Offset
Calibration on
Internal Offset(2)
Analog
Input
Conversion
Analog
Input
Conversion
Cycle Repeats
with Offset
Calibration
Full-Scale
Calibration on
Internal Full-Scale
NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset
calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles.
ADS1212, 1213
16 SBAS064A
Also, during this cycle, the sampling capacitor is discon-
nected from the converter’s analog input and is connected
across REFIN. A gain calibration is initiated and proceeds
over the next three conversions. After this, the input capaci-
tor is once again connected to the analog input. Conversions
proceed as usual over the next three cycles in order to fill the
digital filter. DRDY remains HIGH during this time. On the
next cycle, the DRDY signal goes LOW indicating valid
data, the input to the sampling capacitor is shorted, and an
offset calibration is initiated. At this point, the Background
Calibration sequence repeats.
In essence, the Background Calibration Mode performs
continuous self-calibration where the offset and gain cali-
brations are interleaved with regular conversions. Thus, the
data rate is reduced by a factor of 6. The advantage is that
the converter is continuously adjusting to environmental
changes such as ambient or component temperature (due to
airflow variations).
The ADS1212/13 will remain in the Background Calibra-
tion Mode indefinitely. To move to any other mode, the
Command Register Operation Mode bits (MD2 through
MD0) must be set to the appropriate values.
System Calibration Offset and Full-Scale
Calibration Limits
The System Offset and Full-Scale Calibration range of the
ADS1212/13 is limited and is listed in the Specifications
Table. The range is specified as:
(VFS – | VOS |) < 1.3 • (2 • REFIN)/GAIN
(VFS – | VOS |) > 0.7 • (2 • REFIN)/GAIN
where VFS is the system full-scale voltage and | VOS | is the
absolute value of the system offset voltage. In the following
discussion, keep in mind that these voltages are differential
voltages.
For example, with the internal reference (2.5V) and a gain of
two, the previous equations become (after some manipulation):
VFS – 3.25 < VOS < VFS – 1.75
If VFS is perfect at 2.5V (positive full-scale), then VOS must
be greater than –0.75V and less than 0.75V. Thus, when offset
calibration is performed, the positive input can be no more
than 0.75V below or above the negative input. If this range is
exceeded, the ADS1212/13 may not calibrate properly.
This calculation method works for all gains other than one.
For a gain of one and the internal reference (2.5V), the
equation becomes:
VFS – 6.5 < VOS < VFS – 3.5
With a 5V positive full-scale input, VOS must be greater than
–1.5V and less than 1.5V. Since the offset represents a
common-mode voltage and the input voltage range in a gain
of one is 0V to 5V, a common-mode voltage will cause the
actual input voltage to possibly go below 0V or above 5V.
The specifications also show that for the specifications to be
valid, the input voltage must not go below AGND by more
than 30mV or above AVDD by more than 30mV.
This will be an important consideration in many systems
which use a 2.5V or greater reference, as the input range is
constrained by the expected power supply variations. In
addition, the expected full-scale voltage will impact the
allowable offset voltage (and vice-versa) as the combination
of the two must remain within the power supply and ground
potentials, regardless of the results obtained via the range
calculation shown previously.
There are only two solutions to this constraint: either the
system design must ensure that the full-scale and offset
voltage variations will remain within the power supply and
ground potentials, or the part must be used in a gain of 2 or
greater.
SLEEP MODE
The Sleep Mode is entered after the bits 110 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This mode is exited by entering a new
mode into the MD2-MD0 bits.
The Sleep Mode causes the analog section and a good deal
of the digital section to power down. For full analog power
down, the VBIAS generator and the internal reference must
also be powered down by setting the BIAS and REFO bits
in the Command Register accordingly. The power dissipa-
tion shown in the Specifications Table is with the internal
reference and the VBIAS generator disabled.
To establish serial communication with the converter while
it is in Sleep Mode, one of the following procedures must be
used: If CS is being used, simply taking CS LOW will
enable serial communication to proceed normally. If CS is
not being used (tied LOW) and the ADS1212/13 is in the
Master Mode, then a falling edge must be produced on the
SDIO line. If SDIO is LOW, the SDIO line must be taken
HIGH for 4 • tXIN periods (minimum) and then taken LOW.
Alternatively, SDIO can be forced HIGH after putting the
ADS1212/13 to “sleep” and then taken LOW when the
Sleep Mode is to be exited. Finally, if CS is not being used
(tied LOW) and the ADS1212/13 is in the Slave Mode, then
simply sending a normal Instruction Register command will
re-establish communication.
Once serial communication is resumed, the Sleep Mode is
exited by changing the MD2-MD0 bits to any other mode.
When a new mode (other than Sleep) has been entered, the
ADS1212/13 will execute a very brief internal power-up
sequence of the analog and digital circuitry. Once this has
been done, one normal conversion cycle is performed before
the new mode is actually entered. At the end of this conversion
cycle, the new mode takes effect and the converter will
respond accordingly. The DRDY signal will remain HIGH
through the first conversion cycle. It will also remain HIGH
through the second, even if the new mode is the Normal Mode.
If the VBIAS generator and/or the internal reference have
been disabled, then they must be manually re-enabled via the
appropriate bits in the Command Register. In addition, the
internal reference will have to charge the external bypass
capacitor(s) and possibly other circuitry. There may also be
ADS1212, 1213 17
SBAS064A
considerations associated with VBIAS and the settling of
external circuitry. All of these must be taken into account
when determining the amount of time required to resume
normal operation. The timing diagram shown in Figure 10
does not take into account the settling of external circuitry.
FIGURE 10. Sleep Mode to Normal Mode Timing.
DRDY
Serial
I/O
NOTE: (1) Assuming that the external circuitry has
been stable for the previous three t
DATA
periods.
t
DATA
One
Normal
Conversion
(Other
Modes
Start Here)
Data
Not
Valid
Valid
Data
(1)
Valid
Data
(1)
Sleep Mode
Change to Normal Mode Occurs Here
ANALOG OPERATION
ANALOG INPUT
The input impedance of the analog input changes with
ADS1212/13 clock frequency (fXIN), gain (G), and Turbo
Mode Rate (TMR). The relationship is:
AIN Impedance (Ω) = (1MHz/fXIN)•20E6/(G•TMR)
Figure 11 shows the basic input structure of the ADS1212.
The ADS1213 includes an input multiplexer, but this has
little impact on the analysis of the input structure. The
impedance is directly related to the sampling frequency of
the input capacitor. The XIN clock rate sets the basic sam-
pling rate in a gain of 1 and Turbo Mode Rate of 1. Higher
gains and higher Turbo Mode Rates result in an increase of
the sampling rate, while slower clock (XIN) frequencies
result in a decrease.
FIGURE 11. Analog Input Structure.
This input impedance can become a major point of consid-
eration in some designs. If the source impedance of the input
signal is significant or if there is passive filtering prior to the
ADS1212/13, then a significant portion of the signal can be
lost across this external impedance. How significant this
effect is depends on the desired system performance.
There are two restrictions on the analog input signal to the
ADS1212/13. Under no conditions should the current into
or out of the analog inputs exceed 10mA. In addition, while
the analog signal must reside within this range, the linearity
of the ADS1212/13 is only ensured when the actual analog
input voltage resides within a range defined by AGND –
30mV and AVDD +30mV. This is due to leakage paths
which occur within the part when AGND and AVDD are
exceeded.
For this reason, the 0V to 5V input range (gain of 1 with a 2.5V
reference) must be used with caution. Should AVDD be 4.75V,
the analog input signal would swing outside of the tested
specifications of the device. Designs utilizing this mode of
operation should consider limiting the span to a slightly smaller
range. Common-mode voltages are also a significant concern
in this mode and must be carefully analyzed.
An input voltage range of 0.75V to 4.25V is the smallest
span that is allowed if a full system calibration will be
performed (see the Calibration section for more details).
This also assumes an offset error of zero. A better choice
would be 0.5V to 4.5V (a full-scale range of 9V). This span
would allow some offset error, gain error, power supply
drift, and common-mode voltage while still providing full
system calibration over reasonable variation in each of these
parameters.
The actual input voltage exceeding AGND or AVDD should not
be a concern in higher gain settings as the input voltage range
will reside well within 0V to 5V. This is true unless the
common-mode voltage is large enough to place positive full-
scale or negative full-scale outside of the AGND to AVDD range.
REFERENCE INPUT
The input impedance of the REFIN input changes with clock
frequency (fXIN) and Turbo Mode Rate (TMR). The relationship
is:
REFIN Impedance (Ω) = (1MHz/fXIN)•5E6/TMR
Unlike the analog input, the reference input impedance has
a negligible dependency on the PGA gain setting.
The reference input voltage can vary between 2V and 3V. A
nominal voltage of 2.5V appears at REFOUT, and this can be
directly connected to REFIN. Higher reference voltages will
cause the full-scale range to increase while the internal
circuit noise of the converter remains approximately the
same. This will increase the LSB weight but not the internal
noise, resulting in increased signal-to-noise ratio and effec-
tive resolution. Likewise, lower reference voltages will
decrease the signal-to-noise ratio and effective resolution.
REFERENCE OUTPUT
The ADS1212/13 contains an internal +2.5V reference.
Tolerances, drift, noise, and other specifications for this
reference are given in the Specification Table. Note that it is
not designed to sink or to source more than 1mA of current.
In addition, loading the reference with a dynamic or variable
load is not recommended. This can result in small changes
in reference voltage as the load changes. Finally, for designs
approaching or exceeding 20 bits of effective resolution, a
low-noise external reference is recommended as the internal
reference may not have adequate performance.
RSW
(8kΩ typical)
Switching Frequency
= fSAMP
High
Impedance
> 1GΩ
CINT
5pF Typical
VCM
AIN
ADS1212, 1213
18 SBAS064A
ADS1212
AINP
AINN
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
XTAL
C1
6pF
DVDD
GND
DGND
DGND
DGND
R1
3kΩ
R2
3kΩR4
1kΩ
R3
1kΩ
C2
6pF
±10V
±10V
AVDD AGND
DVDD
1.0µF
FIGURE 12. ±10V Input Configuration Using VBIAS.
The circuitry which generates the +2.5V reference can be
disabled via the Command Register and will result in a lower
power dissipation. The reference circuitry consumes a little over
1.6mA of current with no external load. When the ADS1212/13
is in its default state, the internal reference is enabled.
VBIAS
The VBIAS output voltage is dependent on the reference input
(REFIN) voltage and is approximately 1.33 times as great.
This output is used to bias input signals such that bipolar
signals with spans of greater than 5V can be scaled to match
the input range of the ADS1212/13. Figure 12 shows a
connection diagram which will allow the ADS1212/13 to
accept a ±10V input signal (40V full-scale range).
This method of scaling and offsetting the ±20V differential
input signal will be a concern for those requiring minimum
power dissipation. VBIAS will supply 1.68mA for every chan-
nel connected as shown. For the ADS1213, the current draw
is within the specifications for VBIAS, but, at 12mW, the
power dissipation is significant. If this is a concern, resistors
R1 and R2 can be set to 9kΩ and R3 and R4 to 3kΩ. This will
reduce power dissipation by one-third. In addition, these
resistors can also be set to values which will provide any
arbitrary input range. In all cases, the maximum current into
or out of VBIAS should not exceed its specification of 10mA.
Note that the connection diagram shown in Figure 12 causes
a constant amount of current to be sourced by VBIAS. This
will be very important in higher resolution designs as the
voltage at VBIAS will not change with loading, as the load is
constant. However, if the input signal is single-ended and one
side of the input is grounded, the load will not be constant and
VBIAS will change slightly with the input signal. Also, in all
cases, note that noise on VBIAS introduces a common-mode
error signal which is rejected by the converter.
The circuitry to generate VBIAS is disabled when the
ADS1212/13 is in its default state, and it must be enabled,
via the Command Register, in order for the VBIAS voltage to
be present. When enabled, the VBIAS circuitry consumes
approximately 1mA with no external load.
On power-up, external signals may be present before VBIAS
is enabled. This can create a situation in which a negative
voltage is applied to the analog inputs (–2.5V for the circuit
shown in Figure 12), reverse biasing the negative input
protection diode. This situation should not be a problem as
long as the resistors R1 and R2 limit the current being
sourced by each analog input to under 10mA (a potential of
0V at the analog input pin should be used in the calculation).
DIGITAL OPERATION
SYSTEM CONFIGURATION
The Micro Controller (MC) consists of an ALU and a
register bank. The MC has two states: power-on reset and
convert. In the power-on reset state, the MC resets all the
registers to their default state, sets up the modulator to a
stable state, and performs self-calibration at a 340Hz data
rate. After this, it enters the Convert Mode, which is the
normal mode of operation for the ADS1212/13.
The ADS1212/13 has 5 internal registers, as shown in Table
VII. Two of these, the Instruction Register and the Com-
mand Register, control the operation of the converter. The
Data Output Register (DOR) contains the result from the
most recent conversion. The Offset and Full-Scale Calibra-
tion Registers (OCR and FCR) contain data used for correct-
ing the internal conversion result before it is placed into the
DOR. The data in these two registers may be the result of a
calibration routine, or they may be values which have been
written directly via the serial interface.
TABLE VII. ADS1212/13 Registers.
INSR Instruction Register 8 Bits
DOR Data Output Register 24 Bits
CMR Command Register 32 Bits
OCR Offset Calibration Register 24 Bits
FCR Full-Scale Calibration Register 24 Bits
Communication with the ADS1212/13 is controlled via the
Instruction Register (INSR). Under normal operation, the INSR
is written as the first part of each serial communication. The
instruction that is sent determines what type of communication
will occur next. It is not possible to read the INSR.
ADS1212, 1213 19
SBAS064A
The Command Register (CMR) controls all of the ADS1212/
13’s options and operating modes. These include the PGA
gain setting, the Turbo Mode Rate, the output data rate
(decimation ratio), etc. The CMR is the only 32-bit register
within the ADS1212/13. It, and all the remaining registers,
may be read from or written to.
Instruction Register (INSR)
The INSR is an 8-bit register which commands the serial
interface either to read or to write “n” bytes beginning at the
specified register location. Table VIII shows the format for
the INSR.
Each serial communication starts with the 8-bits of the INSR
being sent to the ADS1212/13. This directs the remainder of
the communication cycle, which consists of n bytes being
read from or written to the ADS1212/13. The read/write bit,
the number of bytes n, and the starting register address are
defined, as shown in Table VIII. When the n bytes have been
transferred, the INSR is complete. A new communication
cycle is initiated by sending a new INSR (under restrictions
outlined in the Interfacing section).
Command Register (CMR)
The CMR controls all of the functionality of the ADS1212/
13. The new configuration takes effect on the negative
transition of SCLK for the last bit in each byte of data being
written to the command register. The organization of the
CMR is shown in Table X.
The internal reference circuitry consumes approximately
1.6mA of steady state current with no external load. See the
Reference Output section for full details on the internal
reference.
TABLE VIII. Instruction Register.
R/W (Read/Write) Bit—For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:
MB1, MB0 (Multiple Bytes) Bits—These two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:
A3-A0 (Address) Bits—These four bits select the begin-
ning register location which will be read from or written to,
as shown in Table IX. Each subsequent byte will be read
from or written to the next higher location. (If the BD bit in
the Command Register is set, each subsequent byte will be
read from the next lower location. This bit does not affect the
write operation.) If the next location is not defined in Table
IX, then the results are unknown. Reading or writing contin-
ues until the number of bytes specified by MB1 and MB0
have been transferred.
A3 A2 A1 A0 REGISTER BYTE
0000Data Output Register Byte 2 (MSB)
0001Data Output Register Byte 1
0010Data Output Register Byte 0 (LSB)
0100Command Register Byte 3 (MSB)
0101Command Register Byte 2
0110Command Register Byte 1
0111Command Register Byte 0 (LSB)
1000Offset Cal Register Byte 2 (MSB)
1001Offset Cal Register Byte 1
1010Offset Cal Register Byte 0 (LSB)
1100Full-Scale Cal Register Byte 2 (MSB)
1101Full-Scale Cal Register Byte 1
1110Full-Scale Cal Register Byte 0 (LSB)
Note: MSB = Most Significant Byte, LSB = Least Significant Byte
R/W
0 Write
1 Read
MB1 MB0
0 0 1 Byte
0 1 2 Bytes
1 0 3 Bytes
1 1 4 Bytes
TABLE IX. A3-A0 Addressing.
MSB LSB
R/W MB1 MB0 0 A3 A2 A1 A0
The VBIAS circuitry consumes approximately 1mA of steady
state current with no external load. See the VBIAS section for
full details. When the internal reference (REFOUT) is con-
nected to the reference input (REFIN), VBIAS is 3.3V, nominal.
REFO (Reference Output) Bit—The REFO bit controls
the internal reference (REFOUT) state, either on (2.5V) or off
(disabled), as follows:
REFO INTERNAL REFERENCE REFOUT STATUS
0 Off High Impedance
1 On 2.5V Default
BIAS (Bias Voltage) Bit—The BIAS bit controls the VBIAS
output state—either on (1.33 • REFIN) or off (disabled), as
follows:
BIAS VBIAS GENERATOR VBIAS STATUS
0 Off Disabled Default
1On1.33•REFIN
Most Significant Bit
Byte 3
DSYNC(1)
BIAS REFO DF U/B BD MSB SDL DRDY
0 Off 1 On 0 Two’s 0 Biplr 0 MSByte 0 MSB 0 SDIO 0 Defaults
NOTE: (1) DSYNC is Write only, DRDY is Read only.
Byte 2
MD2 MD1 MD0 G2 G1 G0 CH1 CH0
000 Normal Mode 000 Gain 1 00 Channel 1 Defaults
Byte 1
SF2 SF1 SF0 DR12 DR11 DR10 DR9 DR8
000 Turbo Mode Rate of 1 00000 Defaults
Byte 0
Least Significant Bit
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
(00000) 0001 0111 (23) Data Rate of 326Hz Defaults
TABLE X. Organization of the Command Register and
Default Status.
ADS1212, 1213
20 SBAS064A
DF (Data Format) Bit—The DF bit controls the format of
the output data, either Two’s Complement or Offset Binary,
as follows:
DF FORMAT ANALOG INPUT DIGITAL OUTPUT
0 Two’s +Full-Scale 7FFFFFHDefault
Complement Zero 000000H
–Full-Scale 800000H
1 Offset Binary +Full-Scale FFFFFFH
Zero 800000H
–Full-scale 000000H
These two formats are the same for all bits except the most
significant, which is simply inverted in one format vs the
other. This bit only applies to the Data Output Register—it
has no effect on the other registers.
U/B (Unipolar) Bit—The U/B bit controls the limits im-
posed on the output data, as follows:
U/B MODE LIMITS
0 Bipolar None Default
1 Unipolar Zero to +Full-Scale only
The particular mode has no effect on the actual full-scale
range of the ADS1212/13, data format, or data format vs
input voltage. In the bipolar mode, the ADS1212/13 oper-
ates normally. In the unipolar mode, the conversion result is
limited to positive values only (zero included).
This bit only controls what is placed in the Data Output
Register. It has no effect on internal data. When cleared, the
very next conversion will produce a valid bipolar result.
BD (Byte Order) Bit—The BD bit controls the order in
which bytes of data are read, either most significant byte
first or least significant byte, as follows:
SDL (Serial Data Line) Bit—The SDL bit controls which
pin on the ADS1212/13 will be used as the serial data output
pin, either SDIO or SDOUT, as follows:
BD BYTE ACCESS ORDER
0 Most Significant Default
to Least Significant Byte
1 Least Significant
to Most Significant Byte
Note that when BD is clear and a multi-byte read is initiated,
A3-A0 of the Instruction Register is the address of the most
significant byte and subsequent bytes reside at higher ad-
dresses. If BD is set, then A3-A0 is the address of the least
significant byte and subsequent bytes reside at lower ad-
dresses. The BD bit only affects read operations; it has no
effect on write operations.
MSB (Bit Order) Bit—The MSB bit controls the order in
which bits within a byte of data are read, either most
significant bit first or least significant bit, as follows:
MSB BIT ORDER
0 Most Significant Bit First Default
1 Least Significant Bit First
The MSB bit only effects read operations; it has no affect on
write operations.
SDL SERIAL DATA OUTPUT PIN
0 SDIO Default
1 SDOUT
If SDL is LOW, then SDIO will be used for both input and
output of serial data—see the Timing section for more
details on how the SDIO pin transitions between these two
states. In addition, SDOUT will remain in a tri-state condi-
tion at all times.
Important Note: Since the default condition is SDL LOW,
SDIO has the potential of becoming an output once every
data output cycle if the ADS1212/13 is in the Master Mode.
This will occur until the Command Register can be written
and the SDL bit set HIGH. See the Interfacing section for
more information.
DRDY (Data Ready) Bit—The DRDY bit is a read-only bit
which reflects the state of the ADS1212/13’s DRDY output
pin, as follows:
DRDY MEANING
0 Data Ready
1 Data Not Ready
DSYNC (Data Synchronization) Bit—The DSYNC bit is
a write-only bit which occupies the same location as DRDY.
When a ‘one’ is written to this location, the effect on the
ADS1212/13 is the same as if the DSYNC input pin had
been taken LOW and returned HIGH. That is, the modulator
count for the current conversion cycle will be reset to zero.
The DSYNC bit is provided in order to reduce the number of
interface signals that are needed between the ADS1212/13
and the main controller. Consult “Making Use of DSYNC”
in the Serial Interface section for more information.
MD2-MD0 (Operating Mode) Bits—The MD2-MD0 bits
initiate or enable the various calibration sequences, as follows:
DSYNC MEANING
0 No Change in Modulator Count
1 Modulator Count Reset to Zero
MD2 MD1 MD0 OPERATING MODE
0 0 0 Normal Mode
0 0 1 Self-Calibration
0 1 0 System Offset Calibration
0 1 1 System Full-Scale Calibration
1 0 0 Pseudo System Calibration
1 0 1 Background Calibration
1 1 0 Sleep
1 1 1 Reserved
The Normal Mode, Background Calibration Mode, and
Sleep Mode are permanent modes and the ADS1212/13 will
remain in these modes indefinitely. All other modes are
temporary and will revert to Normal Mode once the appro-
priate actions are complete. See the Calibration and Sleep
Mode sections for more information.
ADS1212, 1213 21
SBAS064A
Table XI. Decimation Ratios for Various Data Rates (Turbo Mode Rate of 1 and 1MHz clock).
CH1 CH0 ACTIVE INPUT
0 0 Channel 1 Default
0 1 Channel 2
1 0 Channel 3
1 1 Channel 4
TURBO AVAILABLE
MODE PGA
SF2 SF1 SF0 RATE SETTINGS
00011, 2, 4, 8, 16Default
00121, 2, 4, 8
0104 1, 2, 4
0118 1, 2
10016 1
Most Significant Bit
Byte 2
DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
Byte 1
DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR9 DOR8
Byte 0
Least Significant Bit
DOR7 DOR6 DOR5 DOR4 DOR3 DOR2 DOR1 DOR0
TABLE XII. Data Output Register.
G2-G0 (PGA Control) Bits—The G2-G0 bits control the
gain setting of the PGA, as follows:
GAIN AVAILABLE TURBO
G2 G1 G0 SETTING MODE RATES
0 0 0 1 1, 2, 4, 8, 16 Default
0 0 1 2 1, 2, 4, 8
0 1 0 4 1, 2, 4
011 8 1, 2
100 16 1
The gain is partially implemented by increasing the input
capacitor sampling frequency, which is given by the follow-
ing equation:
fSAMP = G • TMR • fXIN/128
where G is the gain setting and TMR is the Turbo Mode
Rate. The product of G and TMR cannot exceed 16. The
sampling frequency of the input capacitor directly relates to
the analog input impedance. See the Programmable Gain
Amplifier and Analog Input sections for more details.
CH1-CH0 (Channel Selection) Bits—The CH1 and CH0 bits
control the input multiplexer on the ADS1213, as follows:
(For the ADS1212, CH1 and CH0 must always be zero.) The
channel change takes effect when the last bit of byte 2 has
been written to the Command Register. Output data will not
be valid for the next three conversions despite the DRDY
signal indicating that data is ready. On the fourth time that
DRDY goes LOW after a channel change has been written
to the Command Register, valid data will be present in the
Data Output Register (see Figure 4).
SF2-SF0 (Turbo Mode Rate) Bits—The SF2-SF0 bits
control the input capacitor sampling frequency and modula-
tor rate, as follows:
The input capacitor sampling frequency and modulator rate
can be calculated from the following equations:
fSAMP = G • TMR • fXIN/128
fMOD = TMR • fXIN/128
where G is the gain setting and TMR is the Turbo Mode
Rate. The sampling frequency of the input capacitor directly
relates to the analog input impedance. The modulator rate
relates to the power consumption of the ADS1212/13 and
the output data rate. See the Turbo Mode, Analog Input, and
Reference Input sections for more details.
DR12-DR0 (Decimation Ratio) Bits—The DR12-DR0 bits
control the decimation ratio of the ADS1212/13. In essence,
these bits set the number of modulator results which are used in
the digital filter to compute each individual conversion result.
Since the modulator rate depends on both the ADS1212/13
clock frequency and the Turbo Mode Rate, the actual output
data rate is given by the following equation:
fDATA = fXIN • TMR/(128 • (Decimation Ratio + 1))
where TMR is the Turbo Mode Rate. Table XI shows
various data rates and corresponding decimation ratios (with
a 1MHz clock). Valid decimation ratios are from 19 to 8000.
Outside of this range, the digital filter will compute results
incorrectly due to inadequate or too much data.
Data Output Register (DOR)
The DOR is a 24-bit register which contains the most recent
conversion result (see Table XII). This register is updated
with a new result just prior to DRDY going LOW. If the
contents of the DOR are not read within a period of time
defined by 1/fDATA –24•(1/fXIN), then a new conversion
result will overwrite the old. (DRDY is forced HIGH prior
to the DOR update, unless a read is in progress).
The contents of the DOR can be in Two’s Complement or
Offset Binary format. This is controlled by the DF bit of the
Command Register. In addition, the contents can be limited to
unipolar data only with the U/B bit of the Command Register.
DATA DECI-
RATE MATION
(HZ) RATIO DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
391190000000010011
250300000000011110
100770000001001101
601290000010000001
501550000010011011
203900000110000110
107800001100001100
0.96 8000 1 1 1 1 1 0 1 0 0 0 0 0 0
ADS1212, 1213
22 SBAS064A
t4t5t6t8
t7t9
SCLK
(Internal)
SDIO
(as input)
SDOUT
(or SDlO
as output)
Offset Calibration Register (OCR)
The OCR is a 24-bit register which contains the offset
correction factor that is applied to the conversion result before
it is placed in the Data Output Register (see Table XIII). In
most applications, the contents of this register will be the
result of either a self-calibration or a system calibration.
The OCR is both readable and writeable via the serial
interface. For applications requiring a more accurate offset
calibration, multiple calibrations can be performed, each
resulting OCR value read, the results averaged, and a more
precise offset calibration value written back to the OCR.
The actual OCR value will change from part-to-part and
with configuration, temperature, and power supply. Thus,
the actual OCR value for any arbitrary situation cannot be
accurately predicted. That is, a given system offset could not
be corrected simply by measuring the error externally, com-
puting a correction factor, and writing that value to the OCR.
In addition, be aware that the contents of the OCR are not
used to directly correct the conversion result. Rather, the
correction is a function of the OCR value. This function is
linear and two known points can be used as a basis for
interpolating intermediate values for the OCR. Consult the
Calibration section for more details.
Most Significant Bit
Byte 2
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
Byte 1
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR9 OCR8
Byte 0
Least Significant Bit
OCR7 OCR6 OCR5 OCR4 OCR3 OCR2 OCR1 OCR0
TABLE XIII. Offset Calibration Register.
The contents of the OCR are in Two’s Complement format.
This is not affected by the DF bit in the Command Register.
Full-Scale Calibration Register (FCR)
The FCR is a 24-bit register which contains the full-scale
correction factor that is applied to the conversion result before
it is placed in the Data Output Register (see Table XIV). In
most applications, the contents of this register will be the
result of either a self-calibration or a system calibration.
TABLE XIV. Full-Scale Calibration Register.
Most Significant Bit
Byte 2
FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
Byte 1
FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR9 FSR8
Byte 0
Least Significant Bit
FSR7 FSR6 FSR5 FSR4 FSR3 FSR2 FSR1 FSR0
The FCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate full-scale
calibration, multiple calibrations can be performed, each
resulting FCR value read, the results averaged, and a more
precise calibration value written back to the FCR.
The actual FCR value will change from part-to-part and
with configuration, temperature, and power supply. Thus,
the actual FCR value for any arbitrary situation cannot be
accurately predicted. That is, a given system full-scale error
cannot be corrected simply by measuring the error exter-
nally, computing a correction factor, and writing that value
to the FCR. In addition, be aware that the contents of the
FCR are not used to directly correct the conversion result.
Rather, the correction is a function of the FCR value. This
function is linear and two known points can be used as a
basis for interpolating intermediate values for the FCR.
Consult the Calibration section for more details. The con-
tents of the FCR are in unsigned binary format. This is not
affected by the DF bit in the Command Register.
TIMING
Table XV and Figures 13 through 21 define the basic digital
timing characteristics of the ADS1212/13. Figure 13 and the
associated timing symbols apply to the XIN input signal.
Figures 14 through 20 and associated timing symbols apply
to the serial interface signals (SCLK, SDIO, SDOUT, and
CS) and their relationship to DRDY. The serial interface is
discussed in detail in the Serial Interface section. Figure 21
and the associated timing symbols apply to the maximum
DRDY rise and fall times.
FIGURE 13. XIN Clock Timing.
t
XIN
t
2
X
IN
t
3
FIGURE 14. Serial Input/Output Timing, Master Mode.
FIGURE 15. Serial Input/Output Timing, Slave Mode.
t10 t11 t12 t14
t13 t15
SCLK
(External)
SDIO
(as input)
SDOUT
(or SDlO
as output)
ADS1212, 1213 23
SBAS064A
SYMBOL DESCRIPTION MIN NOM MAX UNITS
fXIN XIN Clock Frequency 0.5 1 2.5 MHz
tXIN XIN Clock Period 400 2000 ns
t2XIN Clock High 0.4 • tXIN ns
t3XIN Clock LOW 0.4 • tXIN ns
t4Internal Serial Clock HIGH 2 • tXIN ns
t5Internal Serial Clock LOW 2 • tXIN ns
t6Data In Valid to Internal SCLK Falling Edge (Setup) 40 ns
t7Internal SCLK Falling Edge to Data In Not Valid (Hold) 20 ns
t8Data Out Valid to Internal SCLK Falling Edge (Setup) 2 • tXIN –25 ns
t9Internal SCLK Falling Edge to Data Out Not Valid (Hold) 2 • tXIN ns
t10 External Serial Clock HIGH 5 • tXIN ns
t11 External Serial Clock LOW 5 • tXIN ns
t12 Data In Valid to External SCLK Falling Edge (Setup) 40 ns
t13 External SCLK Falling Edge to Data In Not Valid (Hold) 20 ns
t14 Data Out Valid to External SCLK Falling Edge (Setup) tXIN –40 ns
t15 External SCLK Falling Edge to Data Out Not Valid (Hold) 4 • tXIN ns
t16 Falling Edge of DRDY to First SCLK Rising Edge 12 • tXIN ns
(Mode, CS Tied LOW)
t17 Falling Edge of Last SCLK for INSR to Rising Edge of First 10 • tXIN ns
SCLK for Register Data (Master Mode)
t18 Falling Edge of Last SCLK for Register Data to Rising Edge 6 • tXIN ns
of DRDY (Master Mode)
t19 Falling Edge of Last SCLK for INSR to Rising Edge of First 13 • tXIN ns
SCLK for Register Data (Slave Mode) ns
t20 Falling Edge of Last SCLK for Register Data to Rising Edge 8 • tXIN 10 • tXIN ns
of DRDY (Slave Mode)
t21 Falling Edge of DRDY to Falling Edge of CS (Master and 3 • tXIN ns
Slave Mode)
t22 Falling Edge of CS to Rising Edge of SCLK (Master Mode) 10 • tXIN 12 • tXIN ns
t23 Rising Edge of DRDY to Rising Edge of CS (Master and 2 • tXIN ns
Slave Mode)
t24 Falling Edge of CS to Rising Edge of SCLK (Slave Mode) 11 • tXIN ns
t25 Falling Edge of Last SCLK for INSR to SDIO Tri-state 4 • tXIN ns
(Master Mode)
t26 SDIO as Output to Rising Edge of First SCLK for Register 4 • tXIN ns
Data (Master and Slave Modes)
t27 Falling Edge of Last SCLK for INSR to SDIO Tri-state 6 • tXIN 8 • tXIN ns
(Slave Mode)
t28 SDIO Tri-state Time (Master and Slave Modes) 2 • tXIN ns
t29 Falling Edge of Last SCLK for Register Data to SDIO Tri-State 2 • tXIN ns
(Master Mode)
t30 Falling Edge of Last SCLK for Register Data to SDIO 4 • tXIN 6 • tXIN ns
Tri-state (Slave Mode)
t31 DRDY Fall Time 30 ns
t32 DRDY Rise Time 30 ns
t33 Minimum DSYNC LOW Time 21 • tXIN ns
t34 DSYNC Valid HIGH to Falling Edge of XIN (for Exact 10 ns
Synchronization of Multiple Converters Only)
t35 Falling Edge of XIN to DSYNC Not Valid LOW (for Exact 10 ns
Synchronization of Multiple Converters Only)
t36 Falling Edge of Last SCLK for Register Data to Rising Edge 41 • tXIN ns
of First SCLK of next INSR (Slave Mode, CS Tied LOW)
t37 Rising Edge of CS to Falling Edge of CS (Slave Mode, 22 • tXIN ns
Using CS)
t38 Falling Edge of DRDY to First SCLK 11 • tXIN ns
Rising Edge (Slave Mode, CS Tied LOW)
TABLE XV. Digital Timing Characteristics.
ADS1212, 1213
24 SBAS064A
t
16
t
17
t
18
IN7 IN1 IN0 INM IN1 IN0
IN7 IN1 IN0 OUTM OUT1 OUT0
Write Register Data
OUTM OUT1 OUT0
IN7 IN1 IN0
Read Register Data using SDIO
Read Register Data using SDOUT
DRDY
SCLK
SDIO
SDIO
SDIO
SDOUT
FIGURE 17. Serial Interface Timing (CS LOW), Slave Mode.
FIGURE 16. Serial Interface Timing (CS LOW), Master Mode.
t
21
DRDY
CS
SCLK
SDIO
t
23
IN0IN1IN0IN1IN7 INM
t
22
t
17
Write Register Data
t
18
SDIO OUT0OUT1IN0IN1IN7 OUTM
Read Register Data using SDIO
SDIO IN0IN1IN7
SDOUT OUT0OUT1OUTM
Read Register Data using SDOUT
DRDY
CS
SCLK
SDIO OUT0OUT1OUTM
Continuous Read of Data Output Register using SDIO
Continuous Read of Data Output Register using SDOUT
t
18
t
16
SDOUT OUT0OUT1OUTM
FIGURE 18. Serial Interface Timing (Using CS), Master Mode.
t20
t36
t38
t19
IN7IN0IN1INMIN1 IN0IN7
Write Register Data
OUT0OUT1OUTM
Read Register Data using SDOUT
IN7
IN7
OUT0OUT1OUTMIN1 IN0IN7
IN1 IN0IN7
Read Register Data using SDIO
DRDY
SCLK
SDIO
SDIO
SDIO
SDOUT
ADS1212, 1213 25
SBAS064A
FIGURE 19. Serial Interface Timing (Using CS), Slave Mode.
t21
DRDY
CS
SCLK
SDIO
t37
t23
t24
IN7IN0IN1IN0IN1IN7 INM
t24 t19
Write Register Data
t20
SDIO IN7OUT0OUT1IN0IN1IN7 OUTM
Read Register Data Using SDIO
SDIO IN7IN0IN1IN7
SDOUT OUT0OUT1OUTM
Read Register Data Using SDOUT
DRDY
CS
SCLK
SDIO OUT0OUT1OUTM
Continuous Read of Data Output Register using SDIO
Continuous Read of Data Output Register using SDOUT
t20
t16
SDOUT OUT0OUT1OUTM
FIGURE 20. SDIO Input to Output Transition Timing.
FIGURE 21. DRDY Rise and Fall Time.
t31 t32
DRDY
OUT M OUT0
OUT MSB OUT0
t26
t16
t22
t24
t38 t19
SDIO is an input SDIO is an output
t28
t21
IN7
IN7 IN6
t23
t18
t29
t20
t30
t27
t17
t25
t26
IN5 IN2 IN1 IN0
IN0
DRDY
CS(1)
SDIO
SCLK
SCLK
SDIO
Master
Mode
Slave
Mode
NOTE: (1) CS is optional.
ADS1212, 1213
26 SBAS064A
Synchronizing Multiple Converters
A negative going pulse on DSYNC can be used to synchro-
nize multiple ADS1212/13s. This assumes that each
ADS1212/13 is driven from the same master clock and is set
to the same Decimation Ratio and Turbo Mode Rate. The
affect that this signal has on data output timing in general is
discussed in the Serial Interface section.
The concern here is what happens if the DSYNC input is
completely asynchronous to this master clock. If the DSYNC
input rises at a critical point in relation to the master clock
input, then some ADS1212/13s may start-up one XIN clock
cycle before the others. Thus, the output data will be syn-
chronized, but only to within one XIN clock cycle.
For many applications, this will be more than adequate. In
these cases, the timing symbols which relate the DSYNC
signal to the XIN signal can be ignored. For other multiple-
converter applications, this one XIN clock cycle difference
could be a problem. These types of applications would
include using the DRDY and/or the SCLK output from one
ADS1212/13 as the “master” signal for all converters.
To ensure exact synchronization to the same XIN edge, the
timing relationship between the DSYNC and XIN signals,
as shown in Figure 22, must be observed. Figure 23 shows
a simple circuit which can be used to clock multiple
ADS1212/13s from one ADS1212/13, as well as to ensure
that an asynchronous DSYNC signal will exactly synchro-
nize all the converters.
FIGURE 22. DSYNC to XIN Timing for Synchronizing
Mutliple ADS1212/13s.
SERIAL INTERFACE
The ADS1212/13 includes a flexible serial interface which
can be connected to microcontrollers and digital signal
processors in a variety of ways. Along with this flexibility,
there is also a good deal of complexity. This section de-
scribes the trade-offs between the different types of interfac-
ing methods in a top-down approach—starting with the
overall flow and control of serial data, moving to specific
interface examples, and then providing information on vari-
ous issues related to the serial interface.
Multiple Instructions
The general timing diagrams which appear throughout this
data sheet show serial communication to and from the
ADS1212/13 occurring during the DRDY LOW period (see
Figures 4 through 10 and Figure 36). This communication
represents one instruction that is executed by the ADS1212/
13, resulting in a single read or write of register data.
However, more than one instruction can be executed by the
ADS1212/13 during any given conversion period (see Fig-
ure 24). Note that DRDY remains HIGH during the subse-
quent instructions. There are several important restrictions
on how and when multiple instructions can be issued during
any one conversion period.
DRDY
Serial
I/O
24 • t
XIN
Internal
Update of DOR
FIGURE 24. Timing of Data Output Register Update.
The first restriction is that the converter must be in the Slave
Mode. There is no provision for multiple instructions when
the ADS1212/13 is operating in the Master Mode. The
second is that some instructions will produce invalid results
if started at the end of one conversion period and carried into
the start of the next conversion period.
FIGURE 23. Exactly Synchronizing Multiple ADS1212/13s to an Asynchronous DSYNC Signal.
C
2
6pF
C
1
6pF
XTAL
DSYNC
X
IN
X
OUT
DGND
ADS1212/13
SDOUT
SDIO
SCLK
DV
DD
D
CLK
1/2 74HC74
1/6 74HC04
Q
Q
DSYNC
X
IN
X
OUT
DGND
ADS1212/13
SDOUT
SDIO
SCLK
DV
DD
DSYNC
X
IN
X
OUT
DGND
ADS1212/13
SDOUT
SDIO
SCLK
DV
DD
Asynchronous
DSYNC
Strobe
DGND
t
33
t
34
t
35
X
IN
DSYNC
ADS1212, 1213 27
SBAS064A
Start
Writing
ADS1212/13
drives DRDY LOW
CS
state
ADS1212/13
generates 8
serial clock cycles
and receives
Instruction Register
data via SDIO
ADS1212/13
generates n
serial clock cycles
and receives
specified
register data
via SDIO
ADS1212/13
drives DRDY HIGH
End
ADS1212/13
generates 8 serial clock
cycles and receives
Instruction Register
data via SDIO
ADS1212/13 generates n
serial clock cycles
and transmits specified
register data via SDOUT
End
Start
Reading
ADS1212/13
drives DRDY LOW
CS
state
Continuous
Read
Mode?
ADS1212/13
drives DRDY HIGH
SDOUT returns to
tri-state condition
SDOUT becomes
active from tri-state
Use
SDIO for
output?
LOW
No
Yes
LOW
HIGH
No
Yes
ADS1212/13 generates n
serial clock cycles
and transmits specified
register data via SDIO
SDIO transitions to
tri-state condition
SDIO input to
output transition
HIGH
CS
state
L
O
W
HIGH
For example, Figure 24 shows that just prior to the DRDY
signal going LOW, the internal Data Output Register (DOR)
is updated. This update involves the Offset Calibration
Register (OCR) and the Full-Scale Register (FSR). If the
OCR or FSR are being written, their final value may not be
correct, and the result placed into the DOR will certainly not
be valid. Problems can also arise if certain bits of the
Command Register are being changed.
Note that reading the Data Output Register is an excep-
tion. If the DOR is being read when the internal update is
initiated, the update is blocked. The old output data will
remain in the DOR and the new data will be lost. The old
data will remain valid until the read operation has com-
pleted. In general, multiple instructions may be issued, but
the last one in any conversion period should be complete
within 24 • XIN clock periods of the next DRDY LOW
time. In this usage, “complete” refers to the point where
DRDY rises in Figures 17 and 19 (in the Timing Section).
Consult Figures 25 and 26 for the flow of serial data
during any one conversion period.
FIGURE 25. Flowchart for Writing and Reading Register Data, Master Mode.
ADS1212, 1213
28 SBAS064A
Start
Writing
ADS1212/13
drives DRDY LOW
CS
state
External device
generates 8
serial clock cycles
and transmits
instruction register
data via SDIO
External device
generates n
serial clock cycles
and transmits
specified
register data
via SDIO
ADS1212/13
drives DRDY HIGH
End
External device generates
8 serial clock cycles
and receives
instruction register
data via SDIO
External device generates
n serial clock cycles
and receives
specified register
data via SDOUT
End
Start
Reading
ADS1212/13
drives DRDY LOW
CS
state
Continuous
Read
M
ode
?
ADS1212/13
drives DRDY HIGH
SDOUT returns to
tri-state condition
SDOUT becomes
active
Use
SDIO for
output?
LOW
HIGH
No
Yes
LOW
No
Yes
External device generates
n serial clock cycles
and receives
specified register
data via SDIO
SDIO transitions to
tri-state condition
SDIO input to
output transition
More
Instructions?
No
Yes Is Next
Instruction
a Read?
To Read
Flowchart
From Read
Flowchart
CS taken high
for 22 t
periods
minimum (see text
if CS tied LOW).
CS
state
LOW
HIGH
More
Instructions?
No
Is Next
Instruction
a Write?
To Write
Flowchart
Yes
See text
for restrictions Yes
To Write
Flowchart
CS taken high
for 22 t
periods
minimum (see text
if CS tied low).
CS
state
LOW
HIGH
No
See text
for restrictions Yes
No
HIGH
XIN
XIN
FIGURE 26. Flowchart for Writing and Reading Register Data, Slave Mode.
transmits
ADS1212, 1213 29
SBAS064A
Using CS and Continuous Read Mode
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other.
The CS signal does not directly control the tri-state condition
of the SDOUT or SDIO output. These signals are normally
in the tri-state condition. They only become active when
serial data is being transmitted from the ADS1212/13. If the
ADS1212/13 is in the middle of a serial transfer and SDOUT
or SDIO is an output, taking CS HIGH will not tri-state the
output signal.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, then the CS signal must be used. The
ADS1212/13 may be in the Master Mode or the Slave Mode.
In the Master Mode, the CS signal is used to hold-off serial
communication with a “ready” (DRDY LOW) ADS1212/13
until the main controller can accommodate the communica-
tion. In the Slave Mode, the CS signal is used to enable
communication with the ADS1212/13.
The CS input has another use. If the CS state is left LOW
after a read of the Data Output Register has been performed,
then the next time that DRDY goes LOW, the ADS1212/13
Instruction Register will not be entered. Instead, the Instruc-
tion Register contents will be re-used, and the new contents
of the Data Output Register, or some part thereof, will be
transmitted. This will occur as long as CS is LOW and not
toggled.
This mode of operation is called the Continuous Read Mode
and is shown in the read flowcharts of Figures 25 and 26. It
is also shown in the Timing Diagrams of Figures 18 and 19
in the Timing section. Note that once CS has been taken
HIGH, the Continuous Read Mode will be enabled (but not
entered) and can never be disabled. The mode is actually
entered and exited as described above.
Power-On Conditions for SDIO
Even if the SDIO connection will be used only for input,
there is one important item to consider regarding SDIO. This
only applies when the ADS1212/13 is in the Master Mode
and CS will be tied LOW. At power-up, the serial I/O lines
of most microcontrollers and digital signal processors will be
in a tri-state condition, or they will be configured as inputs.
When power is applied to the ADS1212/13, it will begin
operating as defined by the default condition of the Com-
mand Register (see Table X in the System Configuration
section). This condition defines SDIO as the data output pin.
Since the ADS1212/13 is in the Master Mode and CS is tied
LOW, the serial clock will run whenever DRDY is LOW and
an instruction will be entered and executed. If the SDIO line
is HIGH, as it might be with an active pull-up, then the
instruction is a read operation and SDIO will become an
output every DRDY LOW period—for 32 serial clock cycles.
When the serial port on the main controller is enabled, signal
contention could result.
The recommended solution to this problem is to actively pull
SDIO LOW. If SDIO is LOW when the ADS1212/13 enters
the instruction byte, then the resulting instruction is a write
of one byte of data to the Data Output Register, which results
in no internal operation.
If the SDIO signal cannot be actively pulled LOW, then
another possibility is to time the initialization of the
controller’s serial port such that it becomes active between
adjacent DRDY LOW periods. The default configuration for
the ADS1212/13 produces a data rate of 326Hz—a conver-
sion period of 2.9ms. This time should be more than ad-
equate for most microcontrollers and DSPs to monitor DRDY
and initialize the serial port at the appropriate time.
Master Mode
The Master Mode is active when the MODE input is HIGH.
All serial clock cycles will be produced by the ADS1212/13
in this mode, and the SCLK pin is configured as an output.
The frequency of the serial clock will be one-quarter of the
XIN frequency. Multiple instructions cannot be issued during
a single conversion period in this mode—only one instruc-
tion per conversion cycle is possible.
The Master Mode will be difficult for some microcontrollers,
particularly when the XIN input frequency is greater than
2MHz, as the serial clock may exceed the microcontroller’s
maximum serial clock frequency. For the majority of digital
signal processors, this will be much less of a concern. In
addition, if SDIO is being used as an input and an output,
then the transition time from input to output may be a
concern. This will be true for both microcontrollers and
DSPs. See Figure 20 in the Timing section.
Note that if CS is tied LOW, there are special considerations
regarding SDIO as outlined previously in this section. Also
note that if CS is being used to control the flow of data from
the ADS1212/13 and it remains HIGH for one or more
conversion periods, the ADS1212/13 will operate properly.
However, the result in the Data Output Register will be lost
when it is overwritten by each new result. Just prior to this
update, DRDY will be forced HIGH and will return LOW
after the update.
Slave Mode
Most systems will use the ADS1212/13 in the Slave Mode.
This mode allows multiple instructions to be issued per
conversion period as well as allowing the main controller to
set the serial clock frequency and pace the serial data
transfer. The ADS1212/13 is in the Slave Mode when the
MODE input is LOW.
There are several important items regarding the serial clock
for this mode of operation. The maximum serial clock
frequency cannot exceed the ADS1212/13 XIN frequency
divided by 10 (see Figure 15 in the Timing section).
ADS1212, 1213
30 SBAS064A
Reset, Power-On Reset and Brown-Out
The ADS1212/13 contains an internal power-on reset cir-
cuit. If the power supply ramp rate is greater than 50mV/ms,
this circuit will be adequate to ensure the device powers up
correctly. (Due to oscillator settling considerations, commu-
nication to and from the ADS1212/13 should not occur for
at least 25ms after power is stable).
If this requirement cannot be met or if the circuit has
brown-out considerations, the timing diagram of Figure 27
can be used to reset the ADS1212/13. This timing applies
only when the ADS1212/13 is in the Slave Mode and
accomplishes the reset by controlling the duty cycle of the
SCLK input. In general, reset is required after power-up,
after a brown-out has been detected, or when a watchdog
timer event has occured.
If the ADS1212/13 is in the Master Mode, a reset of the
device is not possible. If the power supply does not meet
the minimum ramp rate requirement or brown-out is of
concern, low on-resistance MOSFETs or equivalent should
be used to control power to the ADS1212/13. When pow-
ered down, the device should be left unpowered for at least
300ms before power is reapplied. An alternate method
would be to control the MODE pin and temporarily place
the ADS1212/13 in the Slave Mode while a reset is
initiated as shown in Figure 27.
Two-Wire Interface
For a two-wire interface, the Master Mode of operation may
be preferable. In this mode, serial communication occurs
only when data is ready, informing the main controller as to
the status of the ADS1212/13. The disadvantages are that the
ADS1212/13 must have a dedicated serial port on the main
controller and only one instruction can be issued per data
ready period.
In the Slave Mode, the main controller must read and write
to the ADS1212/13 “blindly.” Writes to the internal regis-
ters, such as the Command Register or Offset Calibration
Register, might occur during an update of the Data Output
Register. This can result in invalid data in the DOR. A two-
wire interface can be used if the main controller can read
and/or write to the converter either much slower or much
faster than the data rate. For example, if much faster, the
main controller can use the DRDY bit to determine when
data is becoming valid (polling it multiple times during one
conversion cycle). Thus, the controller obtains some idea of
when to write to the internal registers. If much slower, then
reads of the DOR might always return valid data (mulitple
conversions have occurred since the last read of the DOR or
since any write of the internal registers).
As with the Master Mode of operation, when using SDIO as
edge of the last serial clock cycle of the instruction byte, the
SDIO pin will begin its transition from input to output.
Between six and eight XIN cycles after this falling edge, the
SDIO pin will become an output. This transition may be too
fast for some microcontrollers and digital signal processors.
If a serial communication does not occur during any conver-
sion period, the ADS1212/13 will continue to operate prop-
erly. However, the results in the Data Output Register will be
lost when they are overwritten by the new result at the start of
the next conversion period. Just prior to this update, DRDY
will be forced HIGH and will return LOW after the update.
Making Use of DSYNC
The DSYNC input pin and the DSYNC write bit in the
Command Register reset the current modulator count to
zero. This causes the current conversion cycle to proceed as
normal, but all modulator outputs from the last data output
to the point where DSYNC is asserted are discarded. Note
that the previous two data outputs are still present in the
ADS1212/13 internal memory. Both will be used to com-
pute the next conversion result, and the most recent one will
be used to compute the result two conversions later. DSYNC
does not reset the internal data to zero.
There are two main uses of DSYNC. In the first case,
DSYNC allows for synchronization of multiple converters.
In regards to the DSYNC input pin, this case was discussed
under “Synchronizing Multiple Converters” in the Timing
section. In regards to the DSYNC bit, it will be difficult to
set all of the converter’s DSYNC bits at the same time
unless all of the converters are in the Slave Mode and the
same instruction can be sent to all of the converters at the
same time.
The second use of DSYNC is to reset the modulator count
to zero in order to obtain valid data as quickly as possible.
For example, if the input channel is changed on the ADS1213,
the current conversion cycle will be a mix of the old channel
and the new channels. Thus, four conversions are needed in
order to ensure valid data. However, if the channel is
changed and then DSYNC is used to reset the modulator
count, the modulator data at the end of the current conver-
sion cycle will be entirely from the new channel. After two
additional conversion cycles, the output data will be com-
pletely valid. Note that the conversion cycle in which
DSYNC is used will be slightly longer than normal. Its
length will depend on when DSYNC was set.
FIGURE 27. Resetting the ADS1212/13 (Slave Mode only).
t1: > 512 • tXIN
< 800 • tXIN
t2: > 10 • tXIN
t3: > 1024 • tXIN
< 1800 • tXIN
t4:≥ 2048 • tXIN
< 2400 • tXIN
t2
t3t1t3t4
t2t2
SCLK
Reset occurs
at 2048 • tXIN
ADS1212, 1213 31
SBAS064A
FIGURE 28. Three-Wire Interface with a 8xC32 Microprocessor.
FIGURE 29. Three-Wire Interface with a 8xC51 Microprocessor.
Three-Wire Interface
Figure 28 shows a three-wire interface with a 8xC32 micro-
processor. Note that the Slave Mode is selected and the
SDIO pin is being used for input and output.
Figure 29 shows a different type of three-wire interface with
an 8xC51 microprocessor. Here, the Master Mode is used.
The interface signals consist of SDOUT, SDIO, and SCLK.
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD
TXD
INT0
INT1
T0
T1
WR
RD
X2
X1
V
SS
8xC32
C
2
27pF
C
1
27pF
R
1
10kΩ
DV
DD
AGND DGND
DGND
AV
DD
DV
DD
D
CLK
Q
Q
D
CLK
Q
Q
1/2 74HC74 1/2 74HC74
XTAL
AGND
1.0µF
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
V
CC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
8xC51
C
1
6pF
(1)
C
2
6pF
(1)
DV
DD
AGND
DGND
DGND
AV
DD
DV
DD
XTAL
AGND
1.0µF
R
1
10kΩ
NOTE: (1) Acceptable capacitive load not to exceed 6pF (±30%).
ADS1212, 1213
32 SBAS064A
Four-Wire Interface
Figure 30 shows a four-wire interface with a 8xC32 micro-
processor. Again, the Slave Mode is being used.
Multi-Wire Interface
Figures 31 and 32 show multi-wire interfaces with a 8xC51
or 68HC11 microprocessor. In these interfaces, the mode of
the ADS1212/13 is actually controlled dynamically. This
could be extremely useful when the ADS1212/13 is to be
used in a wide variety of ways. For example, it might be
desirable to have the ADS1212/13 produce data at a steady
rate and to have the converter operating in the Continuous
Read Mode. But for system calibration, the Slave Mode
might be preferred because multiple instructions can be
issued per conversion period.
Note that the MODE input should not be changed in the
middle of a serial transfer. This could result in misoperation
of the device. A Master/Slave Mode change will not affect
the output data.
Note that the XIN input can also be controlled. It is possible
with some microcontrollers and digital signal processors to
produce a continuous serial clock, which could be connected
to the XIN input. The frequency of the clock is often settable
over some range. Thus, the power dissipation of the
ADS1212/13 could be dynamically varied by changing both
the Turbo Mode and XIN input, trading off conversion speed
and resolution for power consumption.
I/O Recovery
If serial communication stops during an instruction or data
transfer for longer than 4 • tDATA, the ADS1212/13 will reset
its serial interface. This will not affect the internal registers.
The main controller must not continue the transfer after this
event, but must restart the transfer from the beginning.
This feature is very useful if the main controller can be reset
at any point. After reset, simply wait 8 • tDATA before
starting serial communication.
FIGURE 31. Full Interface with a 8xC51 Microprocessor.
ADS1212
AINP
AINN
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
8xC51
C2
6pF
C1
6pF
XTAL
AGND
DGND
AVDD
DVDD
DGND
AGND
1.0µF
R2
10kΩ
R1
10kΩ
FIGURE 30. Four-Wire Interface with a 8xC32 Microprocessor.
DGND
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD
TXD
INT0
INT1
WR
RD
X2
X1
V
SS
8xC32
C
2
27pF
C
1
27pF
DV
DD
AGND DGND
AV
DD
DV
DD
D
CLK
Q
Q
D
CLK
Q
Q
1/2 74HC74 1/2 74HC74
XTAL
AGND
1.0µF
R
1
10kΩ
ADS1212, 1213 33
SBAS064A
FIGURE 32. Full Interface with a 68HC11 Microprocessor.
Isolation
The serial interface of the ADS1212/13 provides for simple
isolation methods. An example of an isolated four-wire
interface is shown in Figure 33. The ISO150 is used to
transmit the digital signals over the isolation barrier.
In addition, the digital outputs of the ADS1212/13 can, in
some cases, drive opto-isolators directly. Figures 34 and 35
show the voltage of the SDOUT pin versus source or sink
current under worst-case conditions. Worst-case conditions
for source current occur when the analog input differential
FIGURE 33. Isolated Four-Wire Interface.
ADS1212
AINP
AINN
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PE0
PE1
PE2
XIRQ
RESET
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
XTAL
68HC11
C2
6pF
C1
6pF
AGND
DGND
AVDD
DVDD
XTAL
AGND
1.0µF
R2
10kΩ
R1
10kΩ
ADS1212
AINP
AINN
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
XTAL
C2
6pF
C1
6pF
VDD1
AGND
DGND
DGND
AVDD
VDD1
ISO150
D1A
R/T1A
VSA
GB
R/T1B
D1B
D2A
R/T2A
GA
VSB
R/T2B
D2B
VDD2
VDD1
VDD1
VDD2
R1
100ΩDGND
GND
DGND GND
SCLK
SDIN
VDD2
VDD1
VDD2
DGND
DGND GND
SDOUT
DRDY
ISO150
D1A
R/T1A
VSA
GB
R/T1B
D1B
D2A
R/T2A
GA
VSB
R/T2B
D2B
AGND
1.0µF
ADS1212, 1213
34 SBAS064A
ADS1213U, P
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
AV
DD
+5V
+5V
V
OL
0V
V
OL
+5V
R
1
49.9kΩ
C
2
6pF
C
1
6pF
DGND
XTAL
DGND
REF1004
+2.5V
0V
+5V
P1
2kΩ
1.0µF
+5V
ADS1213U, P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
AIN3P
AIN4N
AIN4P
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
1.0µF
AVDD
+5V
+5V
+5V
0V
+5V
R1
49.9kΩ
C2
6pF
C1
6pF
XTAL
DGND
DGND
REF1004
+2.5V
+5V
+5V
VOH
VOH
P1
2kΩ
DRDY A
DRDY B
DRDY C
DSYNC
t
DATA
t
DATA
t
DATA
t
DATA
voltage is 5V and the output format is Offset Binary
(FFFFFFH). For sink current, the worst-case condition oc-
curs when the analog input differential voltage is 0V and the
output format is Two’s Complement (000000H).
Note that SDOUT is tri-stated for the majority of the
conversion period and the opto-isolator connection must
take this into account.
Synchronization of Multiple Converters
The DSYNC input is used to synchronize the output data of
multiple ADS1212/13s. Synchronization involves configur-
ing each ADS1212/13 to the same Decimation Ratio and
Turbo Mode setting, and providing a common signal to the
XIN inputs. Then, the DSYNC signal is pulsed LOW (see
Figure 22 in the Timing section). This results in an internal
reset of the modulator count for the current conversion.
Thus, all the converters start counting from zero at the same
time, producing a DRDY LOW signal at approximately the
same point (see Figure 36).
FIGURE 36. Effect of Synchronization on Output Data
Timing.
FIGURE 35. Sink Current vs VOL for SDOUT Under Worst-Case Conditions.
30
25
20
15
10
5
0
SINK CURRENT
VOL (V)
012345
IOUT (mA)
25°C
85°C
–40°C
FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions.
30
25
20
15
10
5
0
SOURCE CURRENT
V
OH
(V)
021345
I
OUT
(mA)
25°C
85°C
–40°C
Note that an asynchronous DSYNC input may cause mul-
tiple converters to be different from one another by one XIN
clock cycle. This should not be a concern for most applica-
tions. However, the Timing section contains information on
exactly synchronizing multiple converters to the same XIN
clock cycle.
ADS1212, 1213 35
SBAS064A
LAYOUT
POWER SUPPLIES
The ADS1212/13 requires the digital supply (DVDD) to be
no greater than the analog supply (AVDD) +0.3V. In the
majority of systems, this means that the analog supply must
come up first, followed by the digital supply. Failure to
observe this condition could cause permanent damage to the
ADS1212/13.
Inputs to the ADS1212/13, such as SDIO, AIN, or REFIN,
should not be present before the analog and digital supplies
are on. Violating this condition could cause latch-up. If these
signals are present before the supplies are on, series resistors
should be used to limit the input current (see the Analog
Input and VBIAS sections of this data sheet for more details
concerning these inputs).
The best scheme is to power the analog section of the design
and AVDD of the ADS1212/13 from one +5V supply and the
digital section (and DVDD) from a separate +5V supply. The
analog supply should come up first. This will ensure that AIN
and REFIN do not exceed AVDD and that the digital inputs
are present only after AVDD has been established, and that
they do not exceed DVDD.
The requirements for the digital supply are not as strict.
However, high frequency noise on DVDD can capacitively
couple into the analog portion of the ADS1212/13. This
noise can originate from switching power supplies, very fast
microprocessors or digital signal processors.
For either supply, high frequency noise will generally be
rejected by the digital filter except at interger multiplies of
fMOD. Just below and above these frequencies, noise will
alias back into the passband of the digital filter, affecting the
conversion result.
If one supply must be used to power the ADS1212/13, the
AVDD supply should be used to power DVDD. This connec-
tion can be made via a 10Ω resistor which, along with the
decoupling capacitors, will provide some filtering between
DVDD and AVDD. In some systems, a direct connection can
be made. Experimentation may be the best way to determine
the approprate connection between AVDD and DVDD.
GROUNDING
The analog and digital sections of the design should be
carefully and cleanly partitioned. Each section should have
its own ground plane with no overlap between them. AGND
should be connected to the analog ground plane as well as all
other analog grounds. DGND should be connected to the
digital ground plane and all digital signals referenced to this
plane.
For a single converter system, AGND and DGND of the
ADS1212/13 should be connected together, underneath the
converter. Do not join the ground planes, but connect the
two with a moderate signal trace. For multiple converters,
connect the two ground planes at one location as central to
all of the converters as possible. In some cases, experimen-
tation may be required to find the best point to connect the
two planes together. The printed circuit board can be de-
signed to provide different analog/digital ground connec-
tions via short jumpers. The initial prototype can be used to
establish which connection works best.
DECOUPLING
Good decoupling practices should be used for the ADS1212/
13 and for all components in the design. All decoupling
capacitors, but specifically the 0.1µF ceramic capacitors,
should be placed as close as possible to the pin being
decoupled. A 1µF to 10µF capacitor, in series with a 0.1µF
ceramic capacitor, should be used to decouple AVDD to
AGND. At a minimum, a 0.1µF ceramic capacitor should be
used to decouple DVDD to DGND, as well as for the digital
supply on each digital component.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding
will change depending on the requirements and specific
design of the overall system. Achieving 20 bits or more of
effective resolution is a great deal more difficult than achiev-
ing 12 bits. In general, a system can be broken up into four
different stages:
Analog Processing
Analog Portion of the ADS1212/13
Digital Portion of the ADS1212/13
Digital Processing
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a self-contained
microcontroller, and one clock source, high-resolution could
be achieved by powering all components by a common
power supply. In addition, all components could share a
common ground plane. Thus, there would be no distinctions
between “analog” and “digital” power and ground. The
layout should still include a power plane, a ground plane,
and careful decoupling.
In a more extreme case, the design could include: multiple
ADS1212/13s; extensive analog signal processing; one or
more microcontrollers, digital signal processors, or micro-
processors; many different clock sources; and interconnec-
tions to various other systems. High resolution will be very
difficult to achieve for this design. The approach would be
to break the system into a many different parts as possible.
For example, each ADS1212/13 may have its own analog
processing front end, its own “analog” power and ground
(possibly shared with the analog front end), and its own
“digital” power and ground. The converter’s “digital” power
and ground would be separate from the power and ground
for the system’s processors, RAM, ROM, and “glue” logic.
ADS1212, 1213
36 SBAS064A
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
C
2
6pF
C
1
6pF
DV
DD
AGND
DGND
AGND
AV
DD
DV
DD
DGND
1/2 OPA1013
3kΩ
AGND
XTAL
AGND
1.0µF
FIGURE 37. Bridge Transducer Interface with Voltage Excitation.
FIGURE 38. Bridge Transducer Interface with Current Excitation.
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
C
2
6pF
C
1
6pF
XTAL
DV
DD
DGND
DGND
AGND
DGND
AGND
AV
DD
DV
DD
INA118
10kΩ1
35
8
2
6
R
G
+In
–In
R
1
6kΩ
7
AB
O
C
IREF200
12 34
865
100µA 100µA
AGND
1.0µF
APPLICATIONS
The ADS1212/13 can be used in a broad range of data
acquisition tasks. The following application diagrams show
the ADS1212 and/or ADS1213 being used for bridge trans-
ducer measurements, temperature measurement, and 4-20mA
receiver applications.
ADS1212, 1213 37
SBAS064A
FIGURE 39. PT100 Interface.
FIGURE 40. Complete 4-20mA Receiver.
FIGURE 41. Single Supply, High-Accuracy Thermocouple.
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
C
2
6pF
C
1
6pF
DV
DD
AGND
DGND
DGND
DGND
AGND XTAL
AGND
AV
DD
DV
DD
INA118
1
37
4
8
2
6
5
R
G
+In
–In
AB
REF200
100µA 100µA
R
3
14kΩ
R
2
100Ω
R
1
100ΩAGND
1.0µF
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
C
2
6pF
C
1
6pF
DV
DD
AGND
DGND
DGND
DGND
XTAL
AV
DD
DV
DD
RCV420
15
+In
3
2
–In
1
C
T
–15V
14
13
5
+15V
4–20mA
AGND
1.0µF
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
C
2
6pF
C
1
6pF
DV
DD
AGND
DGND
DGND
DGND
XTAL
+5V
DV
DD
INA128
R
G
R
1
10kΩAGND
1
37
8
2
6
4
5
+In
–In
Termination AGND
1.0µF
ADS1212, 1213
38 SBAS064A
FIGURE 42. Dual Supply, High-Accuracy Thermocouple.
FIGURE 43. Single Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
ADS1212
AINP
AINN
AGND
VBIAS
CS
DSYNC
XIN
XOUT
DGND
REFIN
REFOUT
AVDD
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
C2
6pF
C1
6pF
DVDD
DGND
DGND
DGND
XTAL
+5V
DVDD
AGND
AGND
INA128
RG
R1
10kΩ
1
37
8
2
6
4
5
+In
–In
–5V
AGND
1.0µF
C
2
6pF
C
1
6pF
DV
DD
DGND
XTAL
+5V
DV
DD
AGND
AGND
AGND
DGND
DGND
INA118
R
G
R
1
10kΩ
R
2
13kΩ
AGND
1
37
8
2
6
4
5
+In
–In
ADS1213U, P
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
AGND
1N4148
AGND
1.0µF
ADS1212, 1213 39
SBAS064A
ADS1212
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
C
2
6pF
C
1
6pF
XTAL
DV
DD
AGND
A
VDD
DGND
DGND
AGND
AV
DD
DV
DD
10kΩ
–In +In
R
1
6kΩ
7
AB
O
C
IREF200
12 34
865
100µA 100µA
AGND
1.0µF
FIGURE 44. Dual Supply, High-Accuracy Thermocouple Interface with Cold Junction Compensation.
FIGURE 45. Low-Cost Bridge Transducer Interface with Current Excitation.
C
2
6pF
C
1
6pF
DV
DD
DGND
XTAL
–5V
+5V
DV
DD
AGND
AGND
DGND
DGND
INA118
R
G
R
1
10kΩ
R
2
13kΩ
AGND
1
37
8
2
6
4
5
+In
–In
ADS1213U, P
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
AGND
1N4148
AGND
1.0µF
ADS1212, 1213
40 SBAS064A
TOPIC INDEX
TOPIC PAGE TOPIC PAGE
ANALOG OPERATION ................................................................. 17
ANALOG INPUT ....................................................................................... 17
REFERENCE INPUT................................................................................ 17
REFERENCE OUTPUT............................................................................ 17
VBIAS ..................................................................................................................................................... 18
DIGITAL OPERATION ..................................................................18
SYSTEM CONFIGURATION.................................................................... 18
Instruction Register (INSR) ................................................................... 19
Command Register (CMR).................................................................... 19
Data Output Register (DOR)................................................................. 21
Offset Calibration Register (OCR) ........................................................ 22
Full-Scale Calibration Register (FCR)................................................... 22
TIMING ..................................................................................................... 22
Synchronizing Multiple Converters........................................................ 26
SERIAL INTERFACE ............................................................................... 26
Multiple Instructions............................................................................... 26
Using CS and Continuous Read Mode ................................................ 29
Power-On Conditions for SDIO............................................................. 29
Master Mode.......................................................................................... 29
Slave Mode............................................................................................ 29
Making Use of DSYNC ......................................................................... 30
Reset, Power-On Reset, and Brown-Out ............................................. 30
Two-Wire Interface ................................................................................ 30
Three-Wire Interface.............................................................................. 30
Four-Wire Interface................................................................................ 30
Multi-Wire Interface ............................................................................... 32
I/O Recovery.......................................................................................... 32
Isolation ................................................................................................. 33
Synchronization of Multiple Converters ................................................ 34
LAYOUT ........................................................................................35
POWER SUPPLIES ................................................................................. 35
GROUNDING............................................................................................ 35
DECOUPLING .......................................................................................... 35
SYSTEM CONSIDERATIONS ................................................................. 35
APPLICATIONS ............................................................................36
FEATURES..................................................................................... 1
APPLICATIONS ............................................................................. 1
DESCRIPTION ............................................................................... 1
SPECIFICATIONS .......................................................................... 2
ABSOLUTE MAXIMUM RATINGS............................................................. 3
ELECTROSTATIC DISCHARGE SENSITIVITY ........................................ 3
PACKAGE INFORMATION ........................................................................ 3
ORDERING INFORMATION ...................................................................... 3
ADS1212 SIMPLIFIED BLOCK DIAGRAM................................................ 4
ADS1212 PIN CONFIGURATION.............................................................. 4
ADS1212 PIN DEFINITIONS ..................................................................... 4
ADS1213 SIMPLIFIED BLOCK DIAGRAM................................................ 5
ADS1213P and ADS1213U PIN CONFIGURATION................................. 5
ADS1213P and ADS1213U PIN DEFINITIONS ........................................ 5
ADS1213E PIN CONFIGURATION ........................................................... 6
ADS1213E PIN DEFINITIONS................................................................... 6
TYPICAL PERFORMANCE CURVES ........................................... 7
THEORY OF OPERATION ............................................................ 9
DEFINITION OF TERMS ......................................................................... 10
DIGITAL FILTER ...................................................................................... 11
Filter Equation ....................................................................................... 12
Filter Settling.......................................................................................... 12
TURBO MODE ......................................................................................... 12
PROGRAMMABLE GAIN AMPLIFIER..................................................... 13
SOFTWARE GAIN ................................................................................... 13
CALIBRATION .......................................................................................... 13
Self-Calibration ...................................................................................... 14
System Offset Calibration ..................................................................... 14
System Full-Scale Calibration ............................................................... 14
Pseudo System Calibration ................................................................... 15
Background Calibration ......................................................................... 15
System Calibration Offset and Full-Scale Calibration Limits................ 16
SLEEP MODE .......................................................................................... 16
ADS1212, 1213 41
SBAS064A
FIGURE INDEX TABLE INDEX
FIGURE TITLE PAGE
Figure 1 Normalized Digital Filter Response ......................................... 11
Figure 2 Digital Filter Response at a Data Rate of 50Hz ..................... 11
Figure 3 Digital Filter Response at a Data Rate of 60Hz ..................... 11
Figure 4 Asynchronous ADS1212/13 Analog Input Voltage Step
or ADS1213 Channel Change to Fully Settled Output Data.. 12
Figure 5 Self-Calibration Timing ............................................................ 14
Figure 6 System Offset Calibration Timing ........................................... 14
Figure 7 System Full-Scale Calibration ................................................. 14
Figure 8 Pseudo System Calibration Timing ......................................... 15
Figure 9 Background Calibration ........................................................... 15
Figure 10 Sleep Mode to Normal Mode Timing ...................................... 17
Figure 11 Analog Input Structure............................................................. 17
Figure 12 ±10V Input Configuration Using VBIAS .................................................... 18
Figure 13 XIN Clock Timing...................................................................... 22
Figure 14 Serial Input/Output Timing, Master Mode ............................... 22
Figure 15 Serial Input/Output Timing, Slave Mode ................................. 22
Figure 16 Serial Interface Timing (CS LOW), Master Mode................... 24
Figure 17 Serial Interface Timing (CS LOW), Slave Mode..................... 24
Figure 18 Serial Interface Timing (Using CS), Master Mode.................. 24
Figure 19 Serial Interface Timing (Using CS), Slave Mode.................... 25
Figure 20 SDIO Input to Output Transition Timing ................................. 25
Figure 21 DRDY Rise and Fall Time....................................................... 25
Figure 22 DSYNC to XIN Timing for Synchronizing Multiple
ADS1212/13s........................................................................... 26
Figure 23 Exactly Synchronizing Multiple ADS1212/13s
to Asynchronous DSYNC Signal............................................. 26
Figure 24 Timing of Data Output Register Update ................................. 26
Figure 25
Flowchart for Writing and Reading Register Data, Master Mode 27
Figure 26
Flowchart for Writing and Reading Register Data, Slave Mode .. 28
Figure 27 Resetting the ADS1212/13 (Slave Mode Only) ...................... 30
Figure 28 Three-Wire Interface with an 8xC32 Microprocessor ............. 31
Figure 29 Three-Wire Interface with an 8xC51 Microprocessor ............. 31
Figure 30 Four-Wire Interface with an 8xC32 Microprocessor ............... 32
Figure 31 Full Interface with an 8xC51 Microprocessor ......................... 32
Figure 32 Full Interface with a 68HC11 Microprocessor ........................ 33
Figure 33 Isolated Four-Wire Interface .................................................... 33
Figure 34 Source Current vs VOH for SDOUT Under
Worst-Case Conditions............................................................ 34
Figure 35 Sink Current vs VOL for SDOUT Under
Worst-Case Conditions............................................................ 34
Figure 36 Effect of Synchronization on Output Data Timing .................. 34
Figure 37 Bridge Transducer Interface with Voltage Excitation.............. 36
Figure 38 Bridge Transducer Interface with Current Excitation .............. 36
Figure 39 PT100 Interface ....................................................................... 37
Figure 40 Complete 4-20mA Receiver .................................................... 37
Figure 41 Single Supply, High-Accuracy Thermocouple......................... 37
Figure 42 Dual Supply, High-Accuracy Thermocouple ........................... 38
Figure 43 Single Supply, High-Accuracy Thermocouple Interface
with Cold Junction Compensation........................................... 38
Figure 44 Dual Supply, High-Accuracy Thermocouple Interface
with Cold Junction Compensation........................................... 39
Figure 45
Low-Cost Bridge Transducer Interface with Current Excitation .....
39
TABLE TITLE PAGE
Table I Full-Scale Range vs PGA Setting ............................................. 9
Table II Available PGA Settings vs Turbo Mode Rate .......................... 9
Table III Effective Resolution vs Data Rate and Gain Setting ............. 10
Table IV Effective Resolution vs Data Rate and Turbo Mode Rate ..... 12
Table V Noise Level vs Data Rate and Turbo Mode Rate .................. 12
Table VI Effective Resolution vs Data Rate, Clock Frequency, and
Turbo Mode Rate .................................................................... 12
Table VII ADS1212/13 Registers ............................................................ 18
Table VIII Instruction Register.................................................................. 19
Table IX A3-A0 Addressing.................................................................... 19
Table X Organization of the Command Register and Default Status .. 19
Table XI Decimation Ratios vs Data Rates ........................................... 21
Table XII Data Output Register............................................................... 21
Table XIII Offset Calibration Register ...................................................... 22
Table XIV Full-Scale Calibration Register................................................ 22
Table XV Digital Timing Characteristics .................................................. 23
PACKAGE OPTION ADDENDUM
www.ti.com 27-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS1212P ACTIVE PDIP N 18 20 Green (RoHS
& no Sb/Br) Call TI N / A for Pkg Type
ADS1212PG4 ACTIVE PDIP N 18 20 Green (RoHS
& no Sb/Br) Call TI N / A for Pkg Type
ADS1212U ACTIVE SOP DTC 18 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1212U/1K ACTIVE SOP DTC 18 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1212U/1KG4 ACTIVE SOP DTC 18 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1212UG4 ACTIVE SOP DTC 18 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1213E ACTIVE SSOP DB 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1213E/1K ACTIVE SSOP DB 28 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1213E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1213EG4 ACTIVE SSOP DB 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1213P ACTIVE PDIP NT 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1213PG4 ACTIVE PDIP NT 24 15 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS1213U ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1213U/1K ACTIVE SOIC DW 24 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1213U/1KG4 ACTIVE SOIC DW 24 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1213UG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 27-Jul-2011
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1212U/1K SOP DTC 18 1000 330.0 24.4 10.9 12.0 2.7 12.0 24.0 Q1
ADS1213E/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
ADS1213U/1K SOIC DW 24 1000 330.0 24.4 10.85 15.8 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1212U/1K SOP DTC 18 1000 367.0 367.0 45.0
ADS1213E/1K SSOP DB 28 1000 367.0 367.0 38.0
ADS1213U/1K SOIC DW 24 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS095 – APRIL 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DTC (R-PDSO-G18) PLASTIC SMALL-OUTLINE
4202498/A 03/01
Area 1
18 10
9
0.4469 (11,35)
0.4625 (11,75)
–A– 0°–8°
0.016 (0,40)
0.050 (1,27)
0.2914 (7,40)
0.2992 (7,60)
0.394 (10,00)
0.419 (10,65)
0.010 (0,25) B
0.0091 (0,23)
0.0125 (0,32)
Base
Plane
Seating
Plane
0.004 (0,10)
0.0118 (0,30)
0.0926 (2,35)
0.1043 (2,65)
0.004 (0,10)
0.010 (0,25)
0.029 (0,75)
0.050 (1,27)
0.013 (0,33)
0.020 (0,51)
Index
x 45°
M
C
D–B–
M
E
0.010 (0,25) M M
CA B
S
–C–
E
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body length dimension does not include mold flash,
protrusions or gate burrs. Mold flash, protrusions and
gate burrs shall not exceed 0.006 (0,15) per side.
D. Body width dimension does not include inter-lead
flash or protrusions. Inter-lead flash and protrusions
shall not exceed 0.010 (0,25) per side.
E. The chamfer on the body is optional. If it is not
present, a visual index feature must be located within
the cross-hatched area.
F. Falls within JEDEC MS-013-AB.
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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