LM3202TLX/NOPB - NATIONAL SEMICONDUCTOR

November 2006

LM3202

650mA Miniature, Adjustable, Step-Down DC-DC Converter

for RF Power Amplifiers

General Description

The LM3202 is a DC-DC converter optimized for powering RF

power amplifiers (PAs) from a single Lithium-Ion cell, however

they may be used in many other applications. It steps down

an input voltage from 2.7V to 5.5V to a variable output voltage

from 1.3V to 3.16V. Output voltage is set using a VCON analog

input for controlling power levels and efficiency of the RF PA.

The LM3202 offers superior performance for mobile phones

and similar RF PA applications. Fixed-frequency PWM oper-

ation minimizes RF interference. Shutdown function turns the

device off and reduces battery consumption to 0.01 µA (typ.).

The LM3202 is available in a 8-pin lead free micro SMD pack-

age. A high switching frequency (2 MHz) allows use of tiny

surface-mount components. Only three small external sur-

face-mount components, an inductor and two ceramic capac-

itors are required.

Features

■2 MHz (typ.) PWM Switching Frequency

■Operates from a single Li-Ion cell (2.7V to 5.5V)

■Variable Output Voltage (1.3V to 3.16V)

■Fast Output Voltage Transient (1.3V to 3.16V in 20µs)

■650mA Maximum load capability

■High Efficiency (96% Typ at 3.6VIN, 3.16VOUT at 400mA)

from internal synchronous rectification

■8-pin micro SMD Package

■Current Overload Protection

■Thermal Overload Protection

■Soft Start function

Applications

■Cellular Phones

■Hand-Held Radios

■RF PC Cards

■Battery Powered RF Devices

Typical Application

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FIGURE 1. LM3202 Typical Application

LM3202 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers

Connection Diagrams

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8–Bump Thin Micro SMD Package, Large Bump

NS Package Number TLA08HPA

Order Information

Order Number Package Marking (Note) Supplied As

LM3202TL XTS/29 250 units, Tape-and-Reel

LM3202TLX XTS/29 3000 units, Tape-and-Reel

Note: The actual physical placement of the package marking will vary from part to part. The package marking “X” designates the date code. “T” is a NSC internal

code for die traceability. “S” designates the device type as switcher device. Both will vary considerably. “29” identifies the device (part number, option, etc.).

Pin Descriptions

Pin # Name Description

A1 PVIN Power Supply Voltage Input to the internal PFET switch.

B1 VDD Analog Supply Input.

C1 EN Enable Input. Set this digital input high for normal operation. For shutdown, set low.

C2 VCON Voltage Control Analog input. VCON controls VOUT in PWM mode.

C3 FB Feedback Analog Input. Connect to the output at the output filter capacitor.

B3 SGND Analog and Control Ground

A3 PGND Power Ground

A2 SW Switch node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current

Limit specification of the LM3202.

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LM3202

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VDD, PVIN to SGND −0.2V to +6.0V

PGND to SGND −0.2V to +0.2V

EN, FB, VCON (SGND −0.2V)

to (VDD +0.2V)

w/6.0V max

SW (PGND −0.2V)

to (PVIN +0.2V)

w/6.0V max

PVIN to VDD −0.2V to +0.2V

Continuous Power Dissipation

(Note 3) Internally Limited

Junction Temperature (TJ-MAX)+150°C

Storage Temperature Range −65°C to +150°C

Maximum Lead Temperature

(Soldering, 10 sec) +260°C

ESD Rating (Notes 4, 13)

Human Body Model:

Machine Model:

2 kV

200V

Operating Ratings (Notes 1, 2)

Input Voltage Range 2.7V to 5.5V

Recommended Load Current 0mA to 650mA

Junction Temperature (TJ) Range −30°C to +125°C

Ambient Temperature (TA) Range

(Note 5)

−30°C to +85°C

Thermal Properties

Junction-to-Ambient Thermal 100°C/W

Resistance (θJA), TLA08 Package

(Note 6)

Electrical Characteristics (Notes 2, 7, 8) Limits in standard typeface are for TA = TJ = 25°C. Limits in

boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, all

specifications apply to LM3202 with: PVIN = VDD = EN = 3.6V.

Symbol Parameter Conditions Min Typ Max Units

VFB, MIN Feedback Voltage at minimum

setting

VCON = 0.4V(Note 8) 1.21 1.30 1.39 V

VFB Feedback Voltage VCON = 1.1V(Note 8) 2.693 2.75 2.835 V

VFB, MAX Feedback Voltage at maximum

setting

VCON = 1.4V(Note 8) 3.03 3.17 3.29 V

ISHDN Shutdown supply current EN = SW = VCON = 0V,

(Note 9) 0.01 2µA

IQDC bias current into VDD VCON = 1V, FB = 0V,

No Switching (Note 10) 1 1.4 mA

RDSON(P) Pin-pin resistance for PFET ISW = 200mA 140 200

230 mΩ

RDSON(N) Pin-pin resistance for NFET ISW = -200mA 300 415

485 mΩ

ILIM,PFET Switch peak current limit (Note 11) 935 1100 1200 mA

FOSC Internal oscillator frequency 1.7 22.3 MHz

VIH,EN Logic high input threshold 1.2 V

VIL,EN Logic low input threshold 0.5 V

IPIN,ENABLE Pin pull down current 5 10 µA

VCON,MIN VCON Threshold

Commanding VFB,MIN

VCON swept down(Note 8) 0.484 0.52 0.556 V

VCON,MAX VCONThreshold

Commanding VFB,MAX

VCON swept up(Note 8) 1.208 1.27 1.312 V

ZCON VCON input resistance 100 kΩ

Gain VCON to VOUT Gain 0.556V ≤ VCON ≤ 1.208V 2.5 V/V

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LM3202

System Characteristics The following spec table entries are guaranteed by design providing the component

values in the typical application circuit are used. These parameters are not guaranteed by production testing. Min and Max

limits apply over the full operating ambient temperature range (−30°C ≤ TA ≤ 85°C) and over the VIN range = 2.7V to 5.5V unless

otherwise specified, Typical values are at TA = 25°C, PVIN = VDD = EN = 3.6V unless otherwise specified, L = 3.3µH, DCR of L ≤

100mΩ, CIN = 10µF, 0603, 6.3V (4.7µF||4.7µF, 0603, 6.3V can also be used), COUT = 4.7µF, 0603, 6.3V

Symbol Parameter Conditions Min Typ Max Units

TRESPONSE Time for VOUT to rise from

1.3V to 3.16V

VIN = 4.2V, COUT = 4.7µF, L = 3.3µH,

RLOAD = 5Ω 20 30

µs

Time for VOUT to fall from

3.16V to 1.3V

VIN = 4.2V, COUT = 4.7µF, L = 3.3µH,

RLOAD = 10Ω 20 30

CCON VCON input capacitance VCON = 1V,

Test frequency = 100 kHz 20 pF

Linearity Linearity in control

range 0.556V to 1.208V

VIN = 3.6V

Monotonic in nature -3 +3 %

ICON Control pin input current -10 10 µA

T_ON Turn on time

(time for output to reach

3.16V from Enable low to

high transition)

EN = Low to High, VIN = 4.2V, VO = 3.16V,

COUT = 4.7µF, IOUT ≤ 1mA 210 750 µs

ηEfficiency

(L = 3.3µH, DCR ≤ 100mΩ)

VIN = 3.6V, VOUT = 1.3V, IOUT = 90mA 87 %

VIN = 3.6V, VOUT = 3.16V, IOUT = 400mA 96 %

VOUT_ripple Ripple voltage, PWM mode VIN = 3V to 4.5V, VOUT = 1.3V, IOUT = 10mA to

400mA (Note 12) 10 mVp-p

Line_tr Line transient response VIN = 600mV perturbance, over Vin range 3V

to 5.5V

TRISE = TFALL = 10µs, VOUT = 1.3V, IOUT =

100mA

50 mVpk

Load_tr Load transient response VIN = 3.1/3.6/4.5V, VOUT = 1.3V, transients up

to 100mA, TRISE = TFALL = 10µs 50 mVpk

PSRR VIN = 3.6V, VOUT = 1.3V,

IOUT = 100mA

sine wave perturbation

frequency = 10kHz, amplitude = 100mVp-p 40 dB

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins. The LM3202 is designed for mobile phone applications where turn-on after power-up is

controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO)

circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V.

Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ

= 130°C (typ.).

Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200pF

capacitor discharged directly into each pin.

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-

rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation

of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following

equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

Note 6: Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC

standard JESD51-7. A 4 layer, 4" x 4", 2/1/1/2 oz. Cu board as per JEDEC standards is used for the measurements.

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Due to the pulsed nature of the testing TA = TJ for the electrical characteristics table.

Note 8: The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = VDD = 3.6V. For performance over the input voltage

range and closed loop results refer to the datasheet curves.

Note 9: Shutdown current includes leakage current of PFET.

Note 10: IQ specified here is when the part is operating at 100% duty cycle.

Note 11: Current limit is built-in, fixed, and not adjustable. Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and

temperature. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle limit is activated).

Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%.

Note 12: Ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and capacitors.

Note 13: National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling

techniques can result in damage.

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LM3202

Typical Performance Characteristics (Circuit in Figure 3, PVIN = VDD = EN = 3.6V, L = 3.3uH, DCR of

L ≤ 100mΩ, CIN = 10uF, 0603, 6.3V ( 4.7uF||4.7uF, 0603, 6.3V can be used), COUT = 4.7uF, 0603, 6.3V unless otherwise noted)

Quiescent Current vs Supply Voltage

(VCON = 2V, FB = 0V, No Switching)

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Shutdown Current vs Temperature

(VCON = 0V, EN = 0V)

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Switching Frequency Variation vs Temperature

(VOUT = 1.3V, IOUT = 200mA)

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Output Voltage vs Supply Voltage

(VOUT = 1.3V: low clamp)

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LM3202

Output Voltage vs Temperature

(VIN = 3.6V, VOUT = 1.3V: low clamp)

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Output Voltage vs Temperature

(VIN = 3.6V, VOUT = 3.16V: high clamp)

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Open/Closed Loop Current Limit vs Temperature

(PWM mode)

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VCON Voltage vs Output Voltage

(VIN = 4.2V, RLOAD = 8Ω)

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Efficiency vs Output Voltage

(VIN = 3.6V)

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Efficiency vs Output Current

(VOUT = 1.3V)

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LM3202

Efficiency vs Output Current

(VOUT = 3.16V)

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Load Transient Response

(VOUT = 1.3V)

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Load Transient Response

(VOUT = 3.16V)

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Startup

(VIN = 3.6V, VOUT = 1.3V, IOUT < 1mA)

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Startup

(VIN= 4.2V, VOUT = 3.16V, IOUT < 1mA)

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LM3202

Shutdown Response

(VIN = 4.2V, VOUT = 3.16V, RLOAD = 10Ω)

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Line Transient Response

(VIN = 3.0V to 3.6V, IOUT = 100mA)

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VCON Voltage Response

(VIN = 4.2V, VCON = 0V/1.4V, RLOAD = 10Ω)

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VCON and Load Transient

(VIN = 4.2V, VCON = 0V/1.4V, 15Ω/8Ω, same time)

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Timed Current Limit Response

(VIN = 3.6V)

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Output Voltage Ripple

(VOUT = 1.3V)

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LM3202

Output Voltage Ripple in Pulse Skip

(VIN = 3.547V, VOUT = 3.16V, RLOAD = 5Ω)

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RDSON vs Temperature

(P-ch, ISW = 200mA)

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RDSON vs Temperature

(N-ch, ISW = -200mA)

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EN High Threshold vs. Vin

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VCON Threshold min vs. Vin

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VCON Threshold max vs. Vin

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LM3202

VFB min vs. VIN

(VCON = 0.4V,RLOAD = 10Ω

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VFB max vs. VIN

(VCON = 1.4V, RLOAD = 10Ω)

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Block Diagram

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FIGURE 2. Functional Block Diagram

Operation Description

The LM3202 is a simple, step-down DC-DC converter opti-

mized for powering RF power amplifiers (PAs) in mobile

phones, portable communicators, and similar battery pow-

ered RF devices. It is designed to allow the RF PA to operate

at maximum efficiency over a wide range of power levels from

a single Li-Ion battery cell. It is based on a current-mode buck

architecture, with synchronous rectification for high efficiency.

It is designed for a maximum load capability of 650mA in PWM

mode.

Maximum load range may vary from this depending on input

voltage, output voltage and the inductor chosen.

Efficiency is typically around 96% for a 400mA load with 3.16V

output, 3.6V input. The output voltage is dynamically pro-

grammable from 1.3V (typ) to 3.16V (typ) by adjusting the

voltage on the control pin without the need for external feed-

back resistors. This ensures longer battery life by being able

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LM3202

to change the PA supply voltage dynamically depending on

its transmitting power.

Additional features include current overload protection, ther-

mal overload shutdown and soft start.

The LM3202 is constructed using a chip-scale 8-pin micro

SMD package. This package offers the smallest possible

size, for space-critical applications such as cell phones,

where board area is an important design consideration. Use

of a high switching frequency (2MHz) reduces the size of ex-

ternal components. As shown in Figure 1, only three external

power components are required for implementation. Use of a

micro SMD package requires special design considerations

for implementation. (See Micro SMD Package Assembly and

use in the Applications Information section.) Its fine bump-

pitch requires careful board design and precision assembly

equipment. Use of this package is best suited for opaque-

case applications, where its edges are not subject to high-

intensity ambient red or infrared light. Also, the system

controller should set EN low during power-up and other low

supply voltage conditions. (See Shutdown Mode in the Device

Information section.)

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FIGURE 3. Typical Operating System Circuit

Circuit Operation

Referring to Figure 1 and Figure 2, the LM3202 operates as

follows. During the first part of each switching cycle, the con-

trol block in the LM3202 turns on the internal PFET (P-

channel MOSFET) switch. This allows current to flow from the

input through the inductor to the output filter capacitor and

load. The inductor limits the current to a ramp with a slope of

around (VIN - VOUT) / L, by storing energy in a magnetic field.

During the second part of each cycle, the controller turns the

PFET switch off, blocking current flow from the input, and then

turns the NFET (N-channel MOSFET) synchronous rectifier

on. In response, the inductor’s magnetic field collapses, gen-

erating a voltage that forces current from ground through the

synchronous rectifier to the output filter capacitor and load.

As the stored energy is transferred back into the circuit and

depleted, the inductor current ramps down with a slope

around VOUT / L. The output filter capacitor stores charge

when the inductor current is high, and releases it when low,

smoothing the voltage across the load.

The output voltage is regulated by modulating the PFET

switch on time to control the average current sent to the load.

The effect is identical to sending a duty-cycle modulated rect-

angular wave formed by the switch and synchronous rectifier

at SW to a low-pass filter formed by the inductor and output

filter capacitor. The output voltage is equal to the average

voltage at the SW pin.

While in operation, the output voltage is regulated by switch-

ing at a constant frequency and then modulating the energy

per cycle to control power to the load. Energy per cycle is set

by modulating the PFET switch on-time pulse width to control

the peak inductor current. This is done by comparing the sig-

nal from the current-sense amplifier with a slope compensat-

ed error signal from the voltage-feedback error amplifier. At

the beginning of each cycle, the clock turns on the PFET

switch, causing the inductor current to ramp up. When the

current sense signal ramps past the error amplifier signal, the

PWM comparator turns off the PFET switch and turns on the

NFET synchronous rectifier, ending the first part of the cycle.

If an increase in load pulls the output down, the error amplifier

output increases, which allows the inductor current to ramp

higher before the comparator turns off the PFET. This in-

creases the average current sent to the output and adjusts for

the increase in the load.

Before appearing at the PWM comparator, a slope compen-

sation ramp from the oscillator is subtracted from the error

signal for stability of the current feedback loop. The minimum

on time of PFET in PWM mode is 50ns (typ.)

Shutdown Mode

Setting the EN digital pin low (<0.5V) places the LM3202 in a

0.01µA (typ.) Shutdown mode. During shutdown, the PFET

switch, NFET synchronous rectifier, reference voltage

source, control and bias circuitry of the LM3202 are turned

off. Setting EN high (>1.2V) enables normal operation.

EN should be set low to turn off the LM3202 during power-up

and under voltage conditions when the power supply is less

than the 2.7V minimum operating voltage. The LM3202 is de-

signed for compact portable applications, such as mobile

phones. In such applications, the system controller deter-

mines power supply sequencing and requirements for small

package size outweigh the additional size required for inclu-

sion of UVLO (Under Voltage Lock-Out) circuitry.

Internal Synchronous Rectification

The LM3202 uses an internal NFET as a synchronous rectifier

to reduce rectifier forward voltage drop and associated power

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LM3202

loss. Synchronous rectification provides a significant im-

provement in efficiency whenever the output voltage is rela-

tively low compared to the voltage drop across and ordinary

rectifier diode.

The internal NFET synchronous rectifier is turned on during

the inductor current down slope in the second part of each

cycle. The synchronous rectifier is turned off prior to the next

cycle. The NFET is designed to conduct through its intrinsic

body diode during transient intervals before it turns on, elim-

inating the need for an external diode.

Current Limiting

A current limit feature allows the LM3202 to protect itself and

external components during overload conditions. In PWM

mode, an 1200mA (max.) cycle-by-cycle current limit is nor-

mally used. If an excessive load pulls the output voltage down

to approximately 0.375V, then the device switches to a timed

current limit mode. In timed current limit mode the internal

PFET switch is turned off after the current comparator trips

and the beginning of the next cycle is inhibited for 3.5us to

force the instantaneous inductor current to ramp down to a

safe value. The synchronous rectifier is off in timed current

limit mode. Timed current limit prevents the loss of current

control seen in some products when the output voltage is

pulled low in serious overload conditions.

Dynamically Adjustable Output

Voltage

The LM3202 features dynamically adjustable output voltage

to eliminate the need for external feedback resistors. The out-

put can be set from VFB,MIN to VFB,MAX by changing the voltage

on the analog VCON pin. This feature is useful in PA applica-

tions where peak power is needed only when the handset is

far away from the base station or when data is being trans-

mitted. In other instances the transmitting power can be re-

duced. Hence the supply voltage to the PA can be reduced,

promoting longer battery life. See Setting the Output Volt-

age in the Application Information section for further details.

Thermal Overload Protection

The LM3202 has a thermal overload protection function that

operates to protect itself from short-term misuse and overload

conditions. When the junction temperature exceeds around

150°C, the device inhibits operation. Both the PFET and the

NFET are turned off in PWM mode. When the temperature

drops below 125°C, normal operation resumes. Prolonged

operation in thermal overload conditions may damage the de-

vice and is considered bad practice.

Application Information

SETTING THE OUTPUT VOLTAGE

The LM3202 features a pin-controlled variable output voltage

to eliminate the need for external feedback resistors. It can

be programmed for an output voltage from 1.3V (typ) to 3.16V

(typ) by setting the voltage on the VCON pin, as in Table 1.

TABLE 1. Output Voltage Selection

VCON(V) VOUT (V)

VCON ≤ 0.484 VFB,MIN

0.556 < VCON <1.208 VOUT = 2.5 x VCON

VCON ≥ 1.312 VFB,MAX

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FIGURE 4. VCON Voltage vs Output Voltage

Refer to Figure 4 for the relation between VOUT and VCON.

When the control pin voltage is between 0.556V and 1.208V,

the output voltage will vary in a monotonic fashion with re-

spect to the voltage on the control pin as per the above Table

1 equation.

Internally the control pin is clamped before it is fed to the error

amplifier inputs. If voltage on the control pin is less than

0.484V, the output voltage is regulated at VFB,MIN and if the

voltage is greater than 1.312V, the output is regulated at

VFB,MAX.

INDUCTOR SELECTION

A 3.3µH inductor with saturation current rating over 1200mA

and low inductance drop at the full DC bias condition is rec-

ommended for almost all applications. The inductor’s DC

resistance should be less than 0.2Ω for good efficiency. For

low dropout voltage, lower DCR inductors are advantageous.

The lower limit of acceptable inductance is 2.3µH at 1200mA

over the operating temperature range. Full attention should

be paid to this limit, because some small inductors show large

inductance drops at high DC bias. These can not be used with

the LM3202. Taiyo-Yuden NR3015T3R3M is an example of

an inductor with the lowest acceptable limit (as of Nov./05).

Table 2 suggests some inductors and suppliers.

TABLE 2. Suggested inductors and their suppliers

Model Size (WxLxH) [mm] Vendor

NR3015T3R3M 3.0 x 3.0 x 1.5 Taiyo-

Yuden

DO3314-332MXC 3.3 x 3.3 x 1.4 Coilcraft

If a smaller inductance inductor is used in the application, the

LM3202 may become unstable during line and load transients

and VCON transient response times may get affected.

For low-cost applications, an unshielded bobbin inductor is

suggested. For noise-critical applications, a toroidal or shield-

ed-bobbin inductor should be used. A good practice is to lay

out the board with footprints accommodating both types for

design flexibility. This allows substitution of a low-noise

toroidal inductor, in the event that noise from low-cost bobbin

models is unacceptable. Saturation occurs when the mag-

netic flux density from current through the windings of the

inductor exceeds what the inductor’s core material can sup-

port with a corresponding magnetic field. This can cause poor

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LM3202

efficiency, regulation errors or stress to a DC-DC converter

like the LM3202.

CAPACITOR SELECTION

The LM3202 is designed for use with ceramic capacitors for

its input and output filters. Use a 10µF ceramic capacitor for

input and a 4.7µF ceramic capacitor for output. They should

maintain at least 50% capacitance at DC bias and tempera-

ture conditions. Ceramic capacitors types such as X5R, X7R

are recommended for both filters. These provide an optimal

balance between small size, cost, reliability and performance

for cell phones and similar applications. Table 3 lists some

suggested part numbers and suppliers. DC bias characteris-

tics of the capacitors must be considered when selecting the

voltage rating and case size of the capacitor. A few manufac-

tures can supply 4.7µF capacitors in the 0805 case size which

maintain at least 50% of their value, but TDK is currently the

only manufacturer which can provide such capacitors in the

0603 case size. As of November, 2005, no manufacture can

supply 10µF capacitors in the 0603 case size which maintain

50% of their value. If it is necessary to choose a 0603-size

capacitor for VIN, the operation of the LM3202 should be care-

fully evaluated on the system board. Output capacitors with

smaller case sizes mitigate piezo electric vibrations when the

output voltage is stepped up and down at fast rates. However,

they have a larger percentage drop in value with dc bias. Use

of multiple 2.2µF or 1µF capacitors in parallel may also be

considered.

TABLE 3. Suggested capacitors and their suppliers

Model Vendor

0805ZD475KA 4.7µF, 10V AVX

C1608X5R0J475M, 4.7µF, 6.3V TDK

C2012X5R0J106M,10µF, 6.3V TDK

The input filter capacitor supplies AC current drawn by the

PFET switch of the LM3202 in the first part of each cycle and

reduces the voltage ripple imposed on the input power

source. The output filter capacitor absorbs the AC inductor

current, helps maintain a steady output voltage during tran-

sient load changes and reduces output voltage ripple. These

capacitors must be selected with sufficient capacitance and

sufficiently low ESR (Equivalent Series Resistance) to per-

form these functions. The ESR of the filter capacitors is

generally a major factor in voltage ripple.

EN PIN CONTROL

Drive the EN pin using the system controller to turn the

LM3202 ON and OFF. Use a comparator, Schmidt trigger or

logic gate to drive the EN pin. Set EN high (>1.2V) for normal

operation and low (<0.5V) for a 0.01µA (typ.) shutdown mode.

Set EN low to turn off the LM3202 during power-up and under

voltage conditions when the power supply is less than the

2.7V minimum operating voltage. The part is out of regulation

when the input voltage is less than 2.7V. The LM3202 is de-

signed for mobile phones where the system controller con-

trols operation mode for maximizing battery life and require-

ments for small package size outweigh the additional size

required for inclusion of UVLO (Under Voltage Lock-Out) cir-

cuitry.

Micro SMD PACKAGE ASSEMBLY AND USE

Use of the Micro SMD package requires specialized board

layout, precision mounting and careful re-flow techniques, as

detailed in National Semiconductor Application Note 1112.

Refer to the section Surface Mount Technology (SMD) As-

sembly Considerations. For best results in assembly, align-

ment ordinals on the PC board should be used to facilitate

placement of the device. The pad style used with Micro SMD

package must be the NSMD (non-solder mask defined) type.

This means that the solder-mask opening is larger than the

pad size. This prevents a lip that otherwise forms if the solder-

mask and pad overlap, from holding the device off the surface

of the board and interfering with mounting. See Application

Note 1112 for specific instructions how to do this.

The 8-Bump package used for LM3202 has 300micron solder

balls and requires 10.82mil pads for mounting on the circuit

board. The trace to each pad should enter the pad with a 90°

entry angle to prevent debris from being caught in deep cor-

ners. Initially, the trace to each pad should be 7mil wide, for

a section approximately 7mil long , as a thermal relief. Then

each trace should neck up or down to its optimal width. The

important criterion is symmetry. This ensures the solder

bumps on the LM3202 re-flow evenly and that the device sol-

ders level to the board. In particular, special attention must be

paid to the pads for bumps A1, A3 and B3. Because PGND

and PVIN are typically connected to large copper planes, in-

adequate thermal relief’s can result in late or inadequate re-

flow of these bumps.

The Micro SMD package is optimized for the smallest possi-

ble size in applications with red or infrared opaque cases.

Because the Micro SMD package lacks the plastic encapsu-

lation characteristic of larger devices, it is vulnerable to light.

Backside metallization and/or epoxy coating, along with front-

side shading by the printed circuit board, reduce this sensi-

tivity. However, the package has exposed die edges. In

particular, Micro SMD devices are sensitive to light, in the red

and infrared range, shining on the package’s exposed die

edges.

BOARD LAYOUT CONSIDERATIONS

20141508

FIGURE 5. Current Loop

The LM3202 converts higher input voltage to lower output

voltage with high efficiency. This is achieved with an inductor-

based switching topology. During the first half of the switching

cycle, the internal PMOS switch turns on, the input voltage is

applied to the inductor, and the current flows from PVDD line

to the output capacitor (C2) through the inductor. During the

second half cycle, the PMOS turns off and the internal NMOS

turns on. The inductor current continues to flow via the induc-

tor from the device PGND line to the output capacitor (C2).

Referring to Figure 5, the LM3202 has two major current loops

where pulse and ripple current flow. The loop shown in the

left hand side is most important, because pulse current shown

in Figure 5 flows in this path. The right hand side is next. The

current waveform in this path is triangular, as shown in Figure

5. Pulse current has many high-frequency components due

13 www.national.com

LM3202

to fast di/dt. Triangular ripple current also has wide high-fre-

quency components. Board layout and circuit pattern design

of these two loops are the key factors for reducing noise ra-

diation and stable operation. Other lines, such as from battery

to C1(+) and C2(+) to load, are almost DC current, so it is not

necessary to take so much care. Only pattern width (current

capability) and DCR drop considerations are needed.

20141509

FIGURE 6. Evaluation Board Layout

BOARD LAYOUT FLOW

1. Minimize C1, PVIN, and PGND loop. These traces should

be as wide and short as possible. This is most important.

2. Minimize L1, C2, SW and PGND loop. These traces also

should be wide and short. This is the second priority.

3. Above layout patterns should be placed on the

component side of the PCB to minimize parasitic

inductance and resistance due to via-holes. It may be a

good idea that the SW to L1 path is routed between C2

(+) and C2(-) land patterns. If vias are used in these large

current paths, multiple via-holes should be used if

possible.

4. Connect C1(-), C2(-) and PGND with wide GND pattern.

This pattern should be short, so C1(-), C2(-), and PGND

should be as close as possible. Then connect to a PCB

common GND pattern with as many via-holes as

possible.

5. SGND should not connect directly to PGND. Connecting

these pins under the device should be avoided. (If

possible, connect SGND to the common port of C1(-), C2

(-) and PGND.)

6. VDD should not be connected directly to PVIN. Connecting

these pins under the device should be avoided. It is good

idea to connect VDD to the C1(+) to avoid switching noise

injection to the VDD line.

7. FB line should be protected from noise. It is a good idea

to use an inner GND layer (if available) as a shield.

Note: The evaluation board shown in Figure 6 for the LM3202 was designed

with these considerations, and it shows good performance. However

some aspects have not been optimized because of limitations due to

evaluation-specific requirements. The board can be used as a refer-

ence, but it is not the best. Please refer questions to a National

representative.

www.national.com 14

LM3202

Physical Dimensions inches (millimeters) unless otherwise noted

8-Bump Thin Micro SMD, Large Bump

X1 = 1.692mm ± 0.030mm

X2 = 1.844mm ±0.030mm

X3 = 0.600mm ±0.075mm

NS Package Number TLA08HPA

15 www.national.com

LM3202

Notes

LM3202 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers

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