BUK9K45-100E,115 - NXP Semiconductors

BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

26 March 2013 Product data sheet

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1. General description

Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS

technology. This product has been designed and qualified to AEC Q101 standard for use

in high performance automotive applications.

2. Features and benefits

•Q101 compliant

•Repetitive avalanche rated

•Suitable for thermally demanding environments due to 175 °C rating

•True logic level gate with VGS(th) > 0.5 V @ 175 °C

3. Applications

•12 V Automotive systems

•Motors, lamps and solenoid control

•Start-stop micro-hybrid applications

•Transmission control

•Ultra high performance power switching

4. Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V

IDdrain current VGS = 5 V; Tmb = 25 °C; Fig. 1 - - 21 A

Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 53 W

Static characteristics FET1 and FET2

RDSon drain-source on-state

resistance

VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 38.3 45 mΩ

Dynamic characteristics FET1 and FET2

QGD gate-drain charge ID = 5 A; VDS = 80 V; VGS = 10 V;

Tj = 25 °C; Fig. 15; Fig. 14

- 7.3 - nC

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 2 / 13

5. Pinning information

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1 S1 source1

2 G1 gate1

3 S2 source2

4 G2 gate2

5 D2 drain2

6 D2 drain2

7 D1 drain1

8 D1 drain1

321 4

678 5

LFPAK56D (SOT1205)

mbk725

G1S1

D1 D2

G2S2

6. Ordering information

Table 3. Ordering information

PackageType number

Name Description Version

BUK9K45-100E LFPAK56D Plastic single ended surface mounted package (LFPAK56D); 8

leads

SOT1205

7. Marking

Table 4. Marking codes

Type number Marking code

BUK9K45-100E 94510E

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V

VDGR drain-gate voltage RGS = 20 kΩ; Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V

Tj ≤ 175 °C; DC -10 10 VVGS gate-source voltage

Tj ≤ 175 °C; Pulsed [1][2] -15 15 V

Tmb = 25 °C; VGS = 5 V; Fig. 1 - 21 AIDdrain current

Tmb = 100 °C; VGS = 5 V; Fig. 1 - 15 A

IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 83 A

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 3 / 13

Symbol Parameter Conditions Min Max Unit

Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 53 W

Tstg storage temperature -55 175 °C

Tjjunction temperature -55 175 °C

Source-drain diode FET1 and FET2

ISsource current Tmb = 25 °C - 21 A

ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 83 A

Avalanche Ruggedness FET1 and FET2

EDS(AL)S non-repetitive drain-source

avalanche energy

ID = 21 A; Vsup ≤ 100 V; VGS = 5 V;

Tj(init) = 25 °C; Fig. 3

[3][4] - 48 mJ

[1] Accumulated Pulse duration up to 50 hours delivers zero defect ppm

[2] Significantly longer life times are achieved by lowering Tj and or VGS.

[3] Refer to application note AN10273 for further information

[4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C

003aaj502

0 50 100 150 200

Tmb(°C)

(A)

Fig. 1. Continuous drain current as a function of

mounting base temperature

Tmb (°C)

0 20015050 100

03aa16

120

Pder

(%)

Fig. 2. Normalized total power dissipation as a

function of mounting base temperature

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 4 / 13

003aaj658

10-2

10-1

102

103

10-3 10-2 10-1 1 10

tAL(ms)

IAL

(A)

(1)

(2)

(3)

Fig. 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and

FET2

003aaj501

1 10 102103

10-1

102

103

VDS (V)

(A)(A)

DCDC

100 ms100 ms

10 ms

1 ms1 ms

100 us100 us

tp = 10 ustp = 10 us

Limit RDSon = VDS / ID

Fig. 4. Safe operating area; continuous and peak drain current as a function of drain-source voltage

9. Thermal characteristics

Table 6. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance

from junction to

mounting base

Fig. 5 - - 2.84 K/W

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 5 / 13

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance

from junction to

ambient

Minimum footprint; mounted on a

printed circuit board

- 95 - K/W

003aaj500

single shot

0.2

0.1

0.05

10-2

10-1

10-6 10-5 10-4 10-3 10-2 10-1 1

(s)

Zth(j-mb)

(K/W)

δ = 0.5

0.02

δ =

Fig. 5. Transient thermal impedance from junction to ambient as a function of pulse duration

10. Characteristics

Table 7. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics FET1 and FET2

ID = 250 µA; VGS = 0 V; Tj = -55 °C 90 - - VV(BR)DSS drain-source

breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 100 - - V

ID = 1 mA; VDS = VGS; Tj = 25 °C;

Fig. 10; Fig. 11

1.4 1.7 2.1 V

ID = 1 mA; VDS = VGS; Tj = 175 °C;

Fig. 10; Fig. 11

0.5 - - V

VGS(th) gate-source threshold

voltage

ID = 1 mA; VDS = VGS; Tj = -55 °C;

Fig. 10; Fig. 11

- - 2.45 V

VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µAIDSS drain leakage current

VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA

VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nAIGSS gate leakage current

VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA

VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 38.3 45 mΩ

VGS = 5 V; ID = 5 A; Tj = 175 °C;

Fig. 12; Fig. 13

- 103 124 mΩ

RDSon drain-source on-state

resistance

VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12 - 35.3 42 mΩ

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 6 / 13

Symbol Parameter Conditions Min Typ Max Unit

Dynamic characteristics FET1 and FET2

QG(tot) total gate charge - 33.5 - nC

QGS gate-source charge

ID = 5 A; VDS = 80 V; VGS = 10 V;

Tj = 25 °C; Fig. 14; Fig. 15 - 3.5 - nC

QGD gate-drain charge ID = 5 A; VDS = 80 V; VGS = 10 V;

Tj = 25 °C; Fig. 15; Fig. 14

- 7.3 - nC

Ciss input capacitance - 1614 2152 pF

Coss output capacitance - 113 136 pF

Crss reverse transfer

capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz;

Tj = 25 °C; Fig. 16

- 72 99 pF

td(on) turn-on delay time - 4 - ns

trrise time

VDS = 80 V; RL = 16 Ω; VGS = 10 V;

RG(ext) = 10 Ω; Tj = 25 °C; ID = 5 A - 8.47 - ns

td(off) turn-off delay time - 41.34 - ns

tffall time

VDS = 80 V; RL = 16 Ω; VGS = 10 V;

RG(ext) = 10 Ω; ID = 18 A; Tj = 25 °C;

ID = 5 A

- 27.75 - ns

Source-drain diode FET1 and FET2

VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.78 1.2 V

trr reverse recovery time - 29.6 - ns

Qrrecovered charge

IS = 5 A; dIS/dt = -100 A/µs; VGS = 0 V;

VDS = 50 V; Tj = 25 °C - 42.9 - nC

003aaj490

120

0 10 20 30

ID(A)

gfs

(S)

Fig. 6. Forward transconductance as a function of

drain current; typical values

003aaj491

100

0 2 4 6 8

VGS(V)

(A)

Tj= 25 °CTj= 175 °C

Fig. 7. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 7 / 13

003aaj492

100

2 3 4 5

VGS(V)

RDSon

(mΩ)

Fig. 8. Drain-source on-state resistance as a function

of gate-source voltage; typical values

003aaj493

0 1 2 3 4

VDS(V)

(A)

VGS(V) = 2.6

2.8

3.54.5

2.4

2.2

Fig. 9. Output characteristics: drain current as a

function of drain-source voltage; typical values

003aah025

0.5

1.5

2.5

-60 0 60 120 180

Tj(°C)

VGS(th)

(V)

max

typ

min

Fig. 10. Gate-source threshold voltage as a function of

junction temperature

003aah026

10-6

10-5

10-4

10-3

10-2

10-1

0 1 2 3

VGS (V)

(A)

maxtypmin

Fig. 11. Sub-threshold drain current as a function of

gate-source voltage

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 8 / 13

003aaj499

100

5 10 15 20 25 30

ID(A)

RDSon

(mW)

4.5

VGS (V) =

2.6 2.8

3.5

Fig. 12. Drain-source on-state resistance as a function

of drain current; typical values

003aaj820

0.6

1.2

1.8

2.4

-60 0 60 120 180

Tj(°C)

Fig. 13. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aaa508

VGS

VGS(th)

QGS1 QGS2

QGD

VDS

QG(tot)

QGS

VGS(pl)

Fig. 14. Gate charge waveform definitions

003aaj496

0 10 20 30 40

QG(nC)

VGS

(V) V DS=

14 V

80 V

Fig. 15. Gate-source voltage as a function of gate

charge; typical values

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 9 / 13

003aaj497

102

103

104

10-1 1 10 102

VDS(V)

(pF) Ciss

Crss

Coss

Fig. 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

003aaj498

0 0.25 0.5 0.75 1 1.25

VSD(V)

(A)

Tj= 25 °CTj= 175°C

Fig. 17. Source current as a function of source-drain

voltage; typical values

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 10 / 13

11. Package outline

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT1205

sot1205_po

13-02-19

13-02-21

Unit

max

nom

min

1.05 0.1

0.0

4.4

4.1

0.25

0.19

0.30

0.24

4.70

4.45

3.5

5.30

4.95

0.85 0.85

0.40

Dimensions

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

Plastic single ended surface mounted package (LFPAK56D); 8 leads SOT1205

A1b

0.50

0.35

b1c c1D(1)

0.1

8°

0°

y θD1(1)

4.8

(ref) E(1) E1(1)

1.8

1.6

E2e

1.27

6.2

5.9

1.3

0.8

0.55

0.30

0.25

0 2.5 5 mm

scale

detail X

A1C

mounting

base

(8x) w A

1 2 3 4

Fig. 18. Package outline LFPAK56D (SOT1205)

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 11 / 13

12. Legal information

12.1 Data sheet status

Document

status [1][2]

Product

status [3]

Definition

Objective

[short] data

sheet

Development This document contains data from

the objective specification for product

development.

Preliminary

[short] data

sheet

Qualification This document contains data from the

preliminary specification.

Product

[short] data

sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the Internet at URL http://www.nxp.com.

12.2 Definitions

Preview — The document is a preview version only. The document is still

subject to formal approval, which may result in modifications or additions.

NXP Semiconductors does not give any representations or warranties as to

the accuracy or completeness of information included herein and shall have

no liability for the consequences of use of such information.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

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customer have explicitly agreed otherwise in writing. In no event however,

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is deemed to offer functions and qualities beyond those described in the

Product data sheet.

12.3 Disclaimers

Limited warranty and liability — Information in this document is believed

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Notwithstanding any damages that customer might incur for any reason

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Suitability for use in automotive applications — This NXP

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Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

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Applications — Applications that are described herein for any of these

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

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Characteristics sections of this document is not warranted. Constant or

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NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 12 / 13

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

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12.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,

FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,

ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,

QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,

TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

NXP Semiconductors BUK9K45-100E

Dual N-channel TrenchMOS logic level FET

Product data sheet 26 March 2013 13 / 13

13. Contents

1 General description ............................................... 1

2 Features and benefits ............................................1

3 Applications ........................................................... 1

4 Quick reference data ............................................. 1

5 Pinning information ............................................... 2

6 Ordering information ............................................. 2

7 Marking ................................................................... 2

8 Limiting values .......................................................2

9 Thermal characteristics .........................................4

10 Characteristics .......................................................5

11 Package outline ................................................... 10

12 Legal information .................................................11

12.1 Data sheet status ............................................... 11

12.2 Definitions ...........................................................11

12.3 Disclaimers .........................................................11

12.4 Trademarks ........................................................ 12

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Date of release: 26 March 2013

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