1 Introduction...........................................................................................................................................................1

2 Notation ................................................................................................................................................................2

3 Key Features ........................................................................................................................................................4

4 PSD3XX Family Feature Summary ......................................................................................................................5

5 Partial Listing of Microcontrollers Supported ........................................................................................................6

6 Applications ..........................................................................................................................................................6

10.2 Port A (PA0-PA7).....................................................................................................................................16

10.2.1 Port A (PA0-PA7) in Multiplexed Address/Data Mode................................................................16

10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode........................................................17

10.3 Port B (PB0-PB7).....................................................................................................................................18

10.3.1 Port B (PA0-PA7) in Multiplexed Address/Data Mode................................................................18

10.3.2 Port B (PA0-PA7) in Non-Multiplexed Address/Data Mode........................................................19

10.4 Port C (PC0-PC2)....................................................................................................................................20

10.5 ALE/AS Input Pin.....................................................................................................................................20

11 PSD Memory ......................................................................................................................................................21

11.1 EPROM....................................................................................................................................................21

12.3 RD/E/DS (DS option not available on 3X1 devices)................................................................................22

12.4 PSEN or PSEN........................................................................................................................................22

12.5 A19/CSI ...................................................................................................................................................23

12.6 Reset Input ..............................................................................................................................................24

13 Program/Data Space and the 8031....................................................................................................................26

14 Systems Applications..........................................................................................................................................27

15 Security Mode.....................................................................................................................................................30

16 Power Management............................................................................................................................................30

16.1 CSI Input..................................................................................................................................................30

16.2 CMiser Bit................................................................................................................................................30

“glue logic”. The part’s integration, small form factor, low power consumption, and ease of

use make it the ideal part for interfacing to virtually any microcontroller.

The major functional blocks of the PSD3XX include:

The PSD3XX family architecture (Figure 1) can efficiently interface with, and enhance,

For a complete product comparison, refer to Table 1.

PSD3XX references the standard version of the PSD3XX family, which are ideal for

general-purpose embedded control applications.

ZPSD3XXRV SRAM-less version of the ZPSD3XXV.

Throughout this data sheet, references are made to the PSD3XX. In most cases, these

references also cover the entire family. Exceptions will be noted. References, such as

“3X1 only” cover all parts that have a 301 or 311 in the part number. Use the following table

to determine what references cover which product versions:

PSD3XX only X X

SRAM-less XX X

The PSD3XX I/O ports can be used for:

external devices.

the following features:

in the PADs.

local data bus

Use the following table to determine which PSD product will fit your needs. Refer back to

PSD301R 14 256 Kb 5 V x8 or x16 50 µA

PSD311R 14 256 Kb 5 V x8 50 µA

PSD302R 18 512 Kb X 5 V x8 or x16 50 µA

PSD312R 18 512 Kb X 5 V x8 50 µA

PSD303R 18 1 Mb X 5 V x8 or x16 50 µA

ZPSD313R 18 1 Mb X 5 V X x8 10 µA

ZPSD301 14 256 Kb 16 Kb 5 V X x8 or x16 10 µA

ZPSD311 14 256 Kb 16 Kb 5 V X x8 10 µA

ZPSD302 18 512 Kb 16 Kb X 5 V X x8 or x16 10 µA

ZPSD312V118 512 Kb 16 Kb X 2.7 V X x8 1 µA

ZPSD303V118 1 Mb 16 Kb X 2.7 V X x8 or x16 1 µA

ZPSD313V118 1 Mb 16 Kb X 2.7 V X x8 1 µA

Port A lines or Low-order multiplexed D0–D7 data bus byte

Port B I/O and/or CS0–CS7 I/O and/or CS0–CS7

bus byte

address/data byte

Port B I/O and/or CS0–CS7 High-order data bus byte

(Figure 4). PAD A is used to generate chip select signals derived from the input address to

the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals.

PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the

decoding to select external devices or as a random logic replacement.

PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft

based on the designer’s input. The PAD’s non-volatile configuration is stored in a

re-programmable CMOS EPROM. Windowed packages are available for erasure by the

user. See Table 4 for a list of PAD A and PAD B functions.

WR or R/W This is the write pulse or R/W select signal.

address/data bus in the track mode controls the input direction of Port A.

The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level.

occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to

to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The

as input as output

Port A Data Register Data in DFF = ‘0’ Data in DFF = ‘1’ 0

of Port A may output an address signal, the pin is position-dependent. In other words, pin

Track Mode sets the entire port to track the signals on AD0/A0-AD7/A7, depending on

specific address ranges defined by the PAD’s CSADIN, CSADOUT1, and CSADOUT2

signals. This feature lets the user interface the microcontroller to shared external resources

without requiring external buffers and decoders. In Track Mode, Port A effectively operates

as a bi-directional buffer, allowing external MCUs or host processors to access the local

data bus. Keep the following information in mind when setting up Track Mode:

In this mode, Port A becomes the low-order data bus byte of the chip. When reading an

internal location, data is presented on Port A pins to the MCU. When writing to an internal

location, data present on Port A pins from the MCU is written to the desired location.

Each pin of Port B can be individually configured. The following table summarizes what the

The default configuration of Port B is MCU I/O. In this mode, every pin can be set

(at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR

FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s

data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the

pin. The contents of the Pin Register indicate the true state of the PSD driving the pin

through the DFF or an external source driving the pin. Pins can be configured as CMOS

or open-drain using WSI’s PSDsoft software. Open-drain pins require external pull-up

Alternatively, each bit of Port B can be configured to provide a chip-select output signal

In this mode, Port B becomes the low-order data bus byte to the MCU chip. When reading

an internal high-order location, data is presented on Port B pins to the MCU. When writing

to an internal high-order location, data present on Port B pins from the MCU is written to the

Each pin of Port C (Figure 7) can be configured as an input to PAD A and PAD B, or as an

output from PAD B. As inputs, the pins are referenced as A16-A18. Although the pins are

given this reference, they can be used for any address or logic input. [For example, A8-A10

any or all PAD equations.

The following sections explain the various memory blocks and memory options within the

the necessary time to latch data on its outputs. After this, it powers down and remains in

Standby Mode until the next address change. This happens automatically, and the designer

has to do nothing special.

The EPROM is divided into eight equal-sized banks. Each bank can be placed in any

address location by programming the PAD. Bank0-Bank7 are selected by PAD A outputs

ES0-ES7, respectively. There is one product term for each bank select (ESi).

Like the EPROM, the optional SRAM in the PSD3XX devices is built using Zero-power

technology.

All PSD3XX parts which do not have an R suffix contain 2 Kbytes of SRAM (Table 1). The

SRAM is selected by the RS0 output of the PAD. There is one product term dedicated to

space (at offset 18h); see Table 5. The Page Register is connected to the lowest nibble of

the data bus (D3-D0). The outputs of the Page Register, P3-P0, are connected to PAD A,

and therefor can be used in any chip select (internal or external) equations. The contents of

the page register are reset to zero at power-up and after any chip-level reset.

Programming the device can be done using the following methods:

Upon delivery from WSI, or after each erasure (using windowed part), the PSD3XX device

has all bits in PAD and EPROM in the HI state (logic 1). The configuration bits are in the LO

state (logic 0).

However, the erasure times will be much longer than when using the recommended 2537 Å

wavelength. Note: exposure to sunlight will eventually erase the device. If used in such an

environment, the package window should be covered with an opaque substance.

In Figure 12, the PSD3XX is configured to interface with Motorola’s 68HC11, which is a

user dependent.

In Figure 13, the PSD3XX is configured to work directly with Intel’s 80C196KB

Port A is configured to work in Track Mode, in which (for certain conditions) PA0–PA7 tracks

lines AD0/A0–AD7/A7. Port B is configured to generate CS0–CS7. In this example, PB2

peripherals. These 8-bit wide peripherals are connected to the shared bus of Port A. The

WAIT signal also drives the buswidth input of the microcontroller, so that every external

peripheral cycle becomes an 8-bit data bus cycle. PB3 and PB4 are open-drain output

signals; thus, they are pulled up externally.

Security Mode in the PSD3XX locks the contents of PAD A, PAD B, and all the configuration

PSDs from all PSD3XX families use Zero-power memory techniques that place memory

into Standby Mode between MCU accesses. The memory becomes active briefly after an

address transition, then delivers new data to the outputs, latches the outputs, and returns to

Standby. This is done automatically and the designer has to do nothing special to benefit

from this feature.

In addition to the benefits of Zero-power memory technology, there are ways to gain addi-

The total current consumption for the PSD is calculated by summing the currents from

memory, PAD logic, and I/O pins, based on your design parameters and the power

management options used.

Driving the CSI pin inactive (logic 1) disables the inputs of the PSD and forces the entire

and control) or other PSD inputs. During this time, the PSD device draws only standby

operation. See Tables 7A and 7B for information on signal states during Power-down Mode.

The CSI pin feature is available only if enabled in the PSDsoft Configuration utility.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

the PAD logic will draw only standby current (micro-amps) while no PAD inputs change.

Whenever there is a transition on any PAD input (including MCU address and control

signals), the PAD logic will power up and will generate new outputs, latch those outputs,

then go back to Standby Mode. Keep in mind that the signal propagation delay through the

PAD logic increases by 10 nsec for non-V devices, and 20 nsec for V devices while in

non-turbo mode. Use of the Turbo Bit does not affect the operation or power consumption

of memory.

mode. This essentially reduces the DC power consumption of the PAD logic to zero. It also

inputs change at a rate less than 40 MHz for non-V devices, and less than 20 MHz for V

devices. Use Figures 14 and 15 to calculate AC and DC current usage in the PAD with the

Turbo Bit on and off. You will need to know the number of product terms that are used in

Given the above product term allocation, keep the following points in mind when calculating

the total number of product terms your design will require:

1) The EPROM block selects, CSIOPORT select, and SRAM select will use a product term

whether you use these blocks or not. This means you start out with 10 product terms,

and go up from there.

2) For Port B, if you use a pin as an output and your logic equation requires only one

product term, you still have to include all the available product terms for that pin for

3) The following PSD functions do not consume product terms: MCU I/O mode, Latched

Address Output, and PAD inputs (logic or address).

The composite frequency of the input signals to the PADs is calculated by considering all

transitions on any PAD input signal (including the MCU address and control inputs). Once

essentially zero when the turbo feature is disabled, and that the AC component increases

are more transitions on any PAD input within the 25 nsec period, these transitions will not

add to power consumption because the PAD logic is already active. This effect helps

transitions on input signals may count as just one transition when estimating the composite

frequency.

Note that the “knee” frequency in Figure 14 is 40 MHz, which means that the PAD will

consume less power only if the composite frequency of all PAD inputs is less than 40 MHz.

down (inputs are spaced less than 25 nsec) and no power savings can be achieved. Figure

Take the following steps to calculate the composite frequency:

1) Determine your highest frequency input for either PAD A or PAD B.

2) Calculate the period of this input and use this period as a basis for determining the

6) The result is the period of the composite frequency. Divide into one to get the composite

frequency value.

Unfortunately, this procedure is complicated and usually not deterministic since different

inputs may be changing in various cycles. Therefore, we recommend you think of the

situation that has the most activity on the inputs to the PLD and use this to calculate the

composite frequency. Then you will have a number that represents your best estimate at

the worst case scenario.

Since this is a complicated process, the following example should help.

Suppose you had the following circuit:

All the inputs shown, except CSI, go to the PAD logic. These signals must be taken into

The calculation of the composite frequency is as follows:

Once you have read the “Power Management” section, you should be able to calculate

(5 V ± 10%)

VCC Supply Voltage With Respect to GND – 0.6 + 7 V