1/184September 2003
■HIGH PERFORMANCE 32 OR 40 MHZ CPU WITH
DSP FUNCTION
– 16-bit CPU With 4-stage Pipeline
– 50ns (or 62.5ns) Instruction Cycle Time at 40MHz (or
32MHz) Max CPU Clock
– Multiply/accumulate Unit (Mac) 16 X 16-bit Multipli-
cation, 40-bit Accumulator
– Repeat Unit
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operat-
ing Systems
– Single-cycle Context Switching Support
■MEMORY ORGANIZATION
– 128K or 256K Byte On-chip Flash Memory Single Volt-
age With Erase/program Controller
– Up to 1K Erasing/programming Cycles
– Up to 16 MByte Linear Address Space For Code And
Data (5 MBytes With CAN)
– 2K Byte On-chip Internal RAM (IRAM)
– 10K Byte On-chip Extension RAM (XRAM)
■FAST AND FLEXIBLE BUS
– Programmable External Bus Characteristics for Dif-
ferent Address Ranges
– 8-bit or 16-bit External Data Bus
– Multiplexed or Demultiplexed External Address/data
Buses
– Five Programmable Chip-select Signals
– Hold-acknowledge Bus Arbitration Support
■INTERRUPT
– 8-channel Peripheral Event Controller for Single Cy-
cle Interrupt Driven Data Transfer
– 16-priority-level Interrupt System with 56 Sources,
Sampling Rate Down to 25ns at 40MHz (31.25ns at
32MHz)
■TIMERS
– Two Multi-functional General Purpose Timer Units
with 5 Timers
■TWO 16-CHANNEL CAPTURE / COMPARE UNITS
■A/D CONVERTER
– 16-channel 10-bit
– 4.85µs Conversion Time at 40MHz CPU Clock
(6.06µs at 32MHz)
■4-CHANNEL PWM UNIT
■SERIAL CHANNELS
– Synchronous / Asynchronous Serial Channel
– High-speed Synchronous Channel
■TWO CAN 2.0B INTERFACES OPERATING ON
ONE OR TWO CAN BUSSES (30 OR 2x15
MESSAGE OBJECTS)
■FAIL-SAFE PROTECTION
– Programmable Watchdog Timer
– Oscillator Watchdog
■ON-CHIP BOOTSTRAP LOADER
■CLOCK GENERATION
– On-chip PLL
– Direct or Prescaled Clock Input
■REAL TIME CLOCK
■UP TO 111 GENERAL PURPOSE I/O LINES
– Individually Programmable as Input, Output or Spe-
cial Function
– Programmable Threshold (Hysteresis)
■IDLE AND POWER DOWN MODES
■SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED
REGULATOR FOR 2.7 or 3.3 V CORE SUPPLY).
■TEMPERATURE RANGES: -40 +125°C / -40 to 85°C
■144-PIN PQFP/TQFP PACKAGES
PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack)
TQFP144 (20 x 20 x 1.40 mm) (Thin Quad Flat Pack)
CAN2_TXD
CAN1_TXD
CAN1_RX D
CAN2_RX D
0
t
r
o
P
1
t
r
o
P
4
t
r
o
P
Port 6 Port 5 Port 3
2
t
r
o
P
1
T
P
G
t
r
a
s
u C
S
A
BRG
CPU-Core and MAC Unit Internal
RAM
Watchdog
Interrupt Controller
8
32 16
PEC
16
16
CAN1
Port 7 Port 8
s
u
B
l
a
n
r
e
t
x
E
C
D
A
t
i
B
-
0
1
BRG
C
S
S
M
W
P
2
M
O
C
P
A
C
1
M
OC
P
AC
16
Oscillator
r
e
l
l
o
r
t
n
o
C
16
16
128K or 256KByte
and PLL
Flash Memory
XTAL1 XTAL2
2K Byte
16 15 88
8
16
3.3V Voltage
Regulator
10K Byte
XRAM
CAN2
2
T
P
G
ST10F269Zx
16-BIT MCU WITH MAC UNIT,
128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM
DATASHEET
ST10F269
2/184
TABLE OF CONTENTS PAGE
ST10F269
1 - Introduction ................................................................................................................. 6
2 - Pin Data ...................................................................................................................... 7
3 - Functional D escription .............................................................................................. 13
4 - Memory Organization ............................................................................................... 14
5 - Internal Flash Memory .............................................................................................. 17
5.1 - OVERVIEW ...................................................................................................................17
5.2 - OPERATIONAL OVERVIEW ........................................................................................17
5.3 - ARCHITECTURAL DESCRIPTION ..............................................................................19
5.3.1 - Read Mode ....................................................................................................19
5.3.2 - Comm and M ode . ...........................................................................................19
5.3.3 - Ready/Busy Signal ........................................................................................19
5.3.4 - Flash Status Register ....................................................................................19
5.3.5 - Flash Protection Register ..............................................................................21
5.3.6 - Instructions Description .................................................................................21
5.3.7 - Reset Processing and Initial State ................................................................26
5.4 - FLASH MEMORY C ONFIGURATION ..........................................................................26
5.5 - APPLICATION EXAMPLES ..........................................................................................26
5. 5. 1 - Handlin g of Fla sh Addre sse s . .............. ....... ....... ....... ........ .............. ....... .......26
5.5.2 - Basic Flash Acce ss Control ...........................................................................27
5.5.3 - Programming Examples ................................................................................28
5.6 - BOOTSTRAP LOADER ..............................................................................................31
5.6.1 - Entering the Bootstrap Loader ......................................................................31
5. 6. 2 - Me mory Co nf igura tion After Reset ..... ....... ....... .............. ....... ....... ............... ..32
5.6.3 - Loading the Startu p Code .............................................................................33
5.6.4 - Exiting Bootstrap Loader M ode .....................................................................33
5.6.5 - C ho os ing the Baud Rate for the BSL ............................................................34
6 - Centra l Processing Unit (CPU ) ..................................................... ............................ 35
6.1 - MULTIPLIER-ACCUMULATOR UNIT (MAC) ...............................................................36
6.1.1 - Features ........................................................................................................37
6.1.1.1 -Enhanced Addressing Capabilities ..................................... .. ........... 37
6.1.1 .2 -Multip ly-Accumulate Unit............. ....... ....... ....... ....... .............. ....... .... 37
6.1.1 .3 -Pro g r a m Cont r o l.. ....... ....... ....... ....... ....... ....... ........ .............. ....... ...... 37
6.2 - INSTRUCTION SET SUMMARY ..................................................................................38
6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS ...................................................39
7 - External Bus Controller ............................................................................................. 43
7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL ...............................................43
7.2 - READY PROGRAMMABLE PO LARITY .......................................................................43
8 - Interrupt System ....................................................................................................... 45
8.1 - EXTERNAL INTERRUPTS ...........................................................................................45
8.2 - INTERRUPT REGISTERS AND VECTORS LOCATION LIST .....................................46
8.3 - INTERRUPT CONTROL REGISTERS .........................................................................47
ST10F269
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TABLE OF CONTENTS PAGE
8.4 - EXCEPTION AND ERROR TRAPS LIST .....................................................................48
9 - Capture/Com pare (CAPC OM) Units ............................................. ............................ 49
10 - General Purpose Timer Uni t ......................................................... ............................ 52
10.1 - GPT1 .............................................................................................................................52
10.2 - GPT2 .............................................................................................................................53
11 - PWM Module ........ .................................................................................................... 56
12 - Par alle l Ports ............................................................................................................ 57
12.1 - INTRODUCTION ...........................................................................................................57
12.2 - I/O’S SPECIAL FEATURES ..........................................................................................59
12.2.1 - Open Drain Mo de ..........................................................................................59
12.2.2 - Input Threshold Control ...............................................................................59
12.2.3 - Output Driver C ontrol ..................................................................................60
12.2.4 - Alternate Port Functions ................................................................................62
12.3 - PORT0 ..........................................................................................................................63
12.3.1 - Alternate Functions of PORT0 ......................................................................64
12.4 - PORT1 ..........................................................................................................................66
12.4.1 - Alternate Functions of PORT1 ......................................................................66
12.5 - PORT 2 .........................................................................................................................68
12.5.1 - Alternate Functions of Port 2 .........................................................................68
12.6 - PORT 3 .........................................................................................................................71
12.6.1 - Alternate Functions of Port 3 .........................................................................73
12.7 - PORT 4 .........................................................................................................................76
12.7.1 - Alternate Functions of Port 4 .........................................................................77
12.8 - PORT 5 .........................................................................................................................80
12.8.1 - Alternate Functions of Port 5 .........................................................................81
12.8.2 - Port 5 Schmitt Trigger Analog Input s ............................................................82
12.9 - PORT 6 .........................................................................................................................82
12.9.1 - Alternate Functions of Port 6 .........................................................................83
12.10 - PORT 7 .........................................................................................................................86
12.10.1 - Alternate Functions of Port 7 .........................................................................87
12.11 - PORT 8 .........................................................................................................................90
12.11.1 - Alternate Functions of Port 8 .........................................................................91
13 - A/D Converter ...........................................................................................................93
14 - Serial Channels ........................................................................................................ 95
14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INT ERFACE (ASCO) .......................95
14.1.1 - ASC O in Asynchron ous Mode .......................................................................95
14.1.2 - ASC O in Syn chronous Mode ........................................................................98
14.2 - HI GH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) .. .............. ....... ...............101
15 - C AN Modules ........ .................................................................................................. 103
15.1 - CAN MODULES MEMORY MAPPING .......................................................................103
15.1.1 - CAN1 ...........................................................................................................103
15.1.2 - CAN2 ...........................................................................................................103
15.2 - CAN BUS CONFIGURATI ONS .... ........ .............. ....... ....... ....... .............. ....... ........ .......103
ST10F269
4/184
TABLE OF CONTENTS PAGE
16 - R eal T ime Clock ..................................................................................................... 105
16.1 - RTC REGISTERS .......................................................................................................106
16.1.1 - RTCCON: RTC Control Register .................................................................1 06
16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers . .... ........ .............. ............108
16.1.3 - RTCDH & RTCDL: RTC DIVIDER Counters ...............................................108
16.1.4 - RTCH & RTCL: RTC Programmable COUNTER Registers ........................109
16.1 .5 - RTCAH & RTCAL: RTC ALARM Register s ........ ....... ............... ....... ............110
16.2 - PROGRAMMING THE RT C ........................................................................................1 10
17 - Watchdog Timer ..................................................................................................... 112
18 - System Reset ......................................................................................................... 114
18.1 - LONG HARDWARE RESE T .......................................................................................114
18.1.1 - Async hronous Res et . ..................................................................................114
18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level) .1 15
18.1.3 - Exit of Long Hardware Reset ......................................................................1 16
18.2 - SHORT HARDWARE RESET .....................................................................................1 16
18.3 - SOFTWARE RESET ...................................................................................................1 17
18.4 - WATCHDOG TIMER RESET ......................................................................................117
18.5 - RSTOUT, RSTIN, BIDIRECTIONAL RESET ..............................................................1 18
18.5.1 - RSTOUT Pin ...............................................................................................118
18.5.2 - Bidirectional Reset ......................................................................................118
18.5.3 - RSTIN pin ....................................................................................................118
18.6 - RESET CIRCUITRY ....................................................................................................118
19 - Pow er Reduction Modes ......................................................................................... 122
19.1 - IDLE MODE ................................................................................................................122
19.2 - POWER DOWN MODE ..............................................................................................122
19.2.1 - Protected Power Down Mode ......................................................................122
19.2.2 - Interruptible Power Down M ode ..................................................................1 22
20 - Special Func tion R egis ter O ver view ....................................................................... 125
20.1 - IDENTIFICATION REGISTERS ..................................................................................1 31
20.2 - SYSTEM CONFIGURATION REGISTERS ................................................................1 32
21 - El e ctrical Characteristi cs ........................................................................................ 139
21.1 - ABSO LUT E MAXI MUM RATI NGS ......... ....... ....... ....... ....... ....... ............... ....... ....... .....139
21.2 - PARAMETER INTERPRETATION .............................................................................1 39
21.3 - DC CHARACTERISTICS ............................................................................................139
21.3.1 - A/D Converter Characte ristics .....................................................................144
21.3.2 - Conversion Timing Control ........................................................................1 45
21.4 - AC CHARACTERISTICS ............................................................................................1 46
21.4.1 - Test Waveforms .........................................................................................1 46
21.4.2 - Definition of Internal Timing .........................................................................1 46
21.4.3 - Clock Generation Modes .............................................................................1 48
21.4.4 - Prescaler Operation ....................................................................................1 49
21.4.5 - Direct Drive ..................................................................................................149
21.4 .6 - Os cil lator Watch dog (OWD) ............... ....... ....... ....... ....... ....... ....... ...............149
ST10F269
5/184
TABLE OF CONTENTS PAGE
21.4.7 - Phase Loc ked Loop . ....................................................................................1 49
21.4.8 - External Clock Drive XTAL1 ........................................................................1 50
21.4.9 - Memory Cycle Variables .............................................................................151
21.4 .10 - Mul tiplexed Bus ............... ....... ....... ....... ....... ....... ....... ............... ....... ....... .....152
21.4 .11 - De multipl e xe d Bus .......... ....... ....... ....... ....... ....... ....... ........ .............. ....... .....160
21.4.12 - CLK O UT and RE ADY .................................................................................1 68
21.4.13 - External Bu s Arbitration ...............................................................................171
21.4.14 - Hi gh-S peed Synchron ous Serial Interface (SSC) Timing ............................174
21.4.14.1Master Mode ................................................................................ 174
21.4.14.2Slave mode.................................................................................. 175
22 - Package Mechanical Da ta ........................................................... .......................... 178
23 - Ordering Inform a tion ............................................................................................... 180
ERRATA SHEET
1 - DESC RIPTION ....................................................................................................... 181
2 - FUNCTIONAL PR OBLEMS .................................................................................... 181
2.1 - PWRDN.1 - EXECUTION OF PWRDN INSTR UCTION .............................................181
2.2 - MAC.9 - COCMP INSTRUCTION INVERTED OPERANDS .......................................182
2.3 - MAC.10 - E FLAG EVALUATION FOR COSHR AND COASHR INSTRUCTI ONS WHEN
SATURAT IO N MODE IS ENABLE D .... ....... ....... ....... ....... .............. ....... ....... ........ .......182
2.4 - ST_PORT.3 - BAD BEHAVIOR OF HYSTERESIS FUNCTION ON INPUT FALLING
EDGE ..........................................................................................................................183
3 - DEVIATIONS FROM DC/AC PRELIMINAR Y SPECIF ICATION ............................183
4 - ERR ATA SHEET VERSION INFORMA TION ......................................................... 183
1 - INTRODUCTION ST10F 269
6/184
1 - INTR O DUCTION
The ST10F269 is a derivative of the
STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers. It combines
high CPU performance (up to 20 million
instructions per second) with high peripheral
funct ionality and enhanced I/O-cap abilities. It also
provides on-chip high-speed single voltage Flash
memory, on-chip high-speed RAM, and clock
generat i on via PLL.
ST10F269 is processed in 0.35µm CMOS
technology. The MCU core and the logic is
supplied with a 5V to 3.3V on chip voltage
regulator on PQFP144 devices (or 5V to 2.7V on
TQFP144 devices). The part is supplied with a
single 5V supply and I/Os work at 5V.
The device is upward compatible with the
ST10F168 device, with the following set of
differences:
– The Multiply/Accumulate unit is available as
standard. This MAC unit adds powerful DSP
functions to the ST10 architecture, but maintains
full compatibili ty for existi ng code.
– Flash control interface is now based on
STMicroelectronics third generation of
stand-alone Flash memories, with an embedded
Erase/Program Controller. This completely
frees up the CPU during programming or
erasing the Flash.
– 128-KByte Flash Option
– Two dedicated pins (DC1 and DC2) on the
144-pin package are used for decoupling the
internally generated 3. 3V (or 2.7V on T QF P1 44
devices) core logic supply. Do not connect
these two pins to 5.0V external supply.
Instead, these pins should be connected to a
decoupling capaci tor (ceramic type, value ≥ 33 0
nF).
– The A/D Converter characteristics are different
from previous ST10 derivatives ones. Refer to
Section 21.3.1 -.
– The A C and DC pa rameters are a dapted to the
40MHz maximum C PU frequency on PQFP1 44
devices (32MHz on TQFP144 devices). The
characterization is performed with CL = 50pF
max on output pins. Refer to Sect ion 21.3 -.
– In order to reduce EMC, the rise/fall time and the
sink/source capability of the drivers of the I/O
pads are programmable. Refer to Section 12.2 -.
– The Real Time Clock fun ctionality is added.
– The external interrupt sources can be selected
with the EXISEL register.
– The reset source is identified by a dedicated
status bit in the WDTCON register.
Fi gure 1 : Logic Symbol
XTAL1
RSTIN
XTAL2
RSTOUT
NMI
EA
READY
ALE
RD
WR/WRL
Port 5
16-bit
Port 6
8-bit
Port 4
8-bit
Port 3
15-bit
Port 2
16-bit
Port 1
16-bit
Port 0
16-bit
VDD VSS
Port 7
8-bit
Port 8
8-bit
VAREF
VAGND
RPD
DC1 DC2
ST10F269
ST10F269 2 - PIN D ATA
7/184
2 - PIN DATA
Table 1 : Pin Description
Fi gure 2 : Pin Conf i guration (top view)
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.6/CC22IO
P8.7/CC23IO
DC2
VSS
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P8.5/CC21IO
RPD
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
P0H.0/AD8
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2AD2
P0L.A/AD1
P0L.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7A23/CAN2_TxD
P4.6A22/CAN1_TxD
P4.5A21/CAN1_RxD
P4.4A20/CAN2_RxD
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
VSS
VDD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
VAREF
VAGND
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VSS
VDD
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
VSS
DC1
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IOEX2IN
P2.11/CC11IOEX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
VSS
VDD
VSS
NMI
VDD
RSTOUT
RSTIN
VSS
XTAL1
XTAL2
VDD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSS
VDD
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
VSS
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
ST10F269
2 - PIN DATA ST10F269
8/184
Symbol Pin Type Function
P6.0 - P6.7 1 - 8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. P rogramming a n I/ O p in a s inp ut forces the corr espo nding out put dri ver to h igh
impedance state. Port 6 outputs can be configured as push-pull or open drain
drivers. The following Port 6 pins have alternate functions:
1OP6.0CS0 Chip Select 0 Output
... ... ... ... ...
5OP6.4CS4 Chip Select 4 Output
6IP6.5HOLD External Master Hold Requ est Input
7OP6.6HLDA Hold Acknowledg e Output
8 O P6.7 BREQ Bus Request Output
P8.0 - P8.7 9-16 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. P rogramming a n I/ O p in a s inp ut forces the corr espo nding out put dri ver to h igh
impedance state. Port 8 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins have alternate functions:
9 I/O P8.0 CC16IO CAPCOM2: CC16 Capture Input / Compare Output
... ... ... ... ...
16 I/O P8.7 CC23IO CAPCOM2: CC23 Capture Input / Compare Output
P7.0 - P7.7 19-26 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. P rogramming a n I/ O p in a s inp ut forces the corr espo nding out put dri ver to h igh
impedance state. Port 7 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins have alternate functions:
19 O P7.0 POUT0 PWM Channel 0 Output
... ... ... ... ...
22 O P7.3 POUT3 PWM Channel 3 Output
23 I/O P7.4 CC28IO CAPCOM2: CC28 Capture Input / Compare Output
... ... ... ... ...
26 I/O P7.7 CC31IO CAPCOM2: CC31 Capture Input / Compare Output
P5.0 - P5.9
P5.10 - P5.15 27-36
39-44 I
I16-bit in put-on ly port with Schmit t-Trig ger ch aracter isti cs. The pins of Port 5 can be
the a nalog inp ut ch anne ls (u p to 16 ) for the A/D conver ter, where P5.x equ als A Nx
(Analog input channel x), or they are timer inputs:
39 I P5.10 T6EUD GPT2 Timer T6 External Up / Down Control Input
40 I P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input
41 I P5.12 T6IN GPT2 Timer T6 Count Input
42 I P5.13 T5IN GPT2 Timer T5 Count Input
43 I P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input
44 I P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input
ST10F269 2 - PIN D ATA
9/184
P2.0 - P2.7
P2.8 - P2.15 47-54
57-64 I/O 16-bit bidirectional I/O por t, bit-wise programma ble for input or output via direction
bit. P rogramming a n I/ O p in a s inp ut forces the corr espo nding out put dri ver to h igh
impedance state. Port 2 outputs can be configured as push-pull or open drain
drivers. The input threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins have alternate functions:
47 I/O P2.0 CC0IO CAPCOM: CC0 Capture Input / Compare Output
... ... ... ... ...
54 I/O P2.7 CC7IO CAPCOM: CC7 Capture Input / Compare Output
57 I/O P2.8 CC8IO CAPCOM: CC8 Capture Input / Compare Output
I EX0IN Fast External Interrupt 0 Input
... ... ... ... ...
64 I/O P2.15 CC15IO CAPCOM: CC15 Capture Input / Compare Output
I EX7IN Fast External Interrupt 7 Input
I T7IN CAPCOM2 Timer T7 Count Input
P3.0 - P3.5
P3.6 - P3.13,
P3.15
65-70,
73-80,
81
I/O
I/O
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driv er to high impedance state. Port 3 outputs can be configured as push-pull
or open drain drivers. The input threshold of Port 3 is selectable (TTL or special).
The following Port 3 pins have alternate functions:
65 I P3.0 T0IN CAPCOM Timer T0 Count Input
66 O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
67 I P3.2 CAPIN GPT2 Register CAPREL Capture Input
68 O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
69 I P3.4 T3EUD GPT1 Timer T3 External Up / Down Control Input
70 I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture
73 I P3.6 T3IN GPT1 Timer T3 Count / Gate Input
74 I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture
75 I/O P3.8 MRST SSC Master-Receiver / Slave-Transmitter I/O
76 I/O P3.9 MTSR SSC Master-Transmitter / Slave-Receiver O/I
77 O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous /
Synchronous)
78 I/O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous)
79 O P3.12 BHE External Memory High Byte Enable Signal
WRH External Memory High Byte Write Strobe
80 I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input
81 O P3.15 CLKOUT System Clock Output (=CPU Clock)
Symbol Pin Type Function
2 - PIN DATA ST10F269
10/184
P4.0 –P4.7 85-92 I/O P ort 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output
via direc tion bit. Programming an I/O pin as input forces the corresponding output
driver to high impedance state. The input t hreshold is selectable (TTL or special).
Port 4.6 & 4.7 outputs can be configured as push-pull or open drain drivers.
In ca se o f an exter nal bus co nfigu ra tion, Port 4 can be use d to out put the segm ent
address lines:
85 O P4.0 A16 Segment Address Line
86 O P4.1 A17 Segment Address Line
87 O P4.2 A18 Segment Address Line
88 O P4.3 A19 Segment Address Line
89 O P4.4 A20 Segment Address Line
I CAN2_RxD CAN2 Receive Data Input
90 O P4.5 A21 Segment Address Line
I CAN1_RxD CAN1 Receive Data Input
91 O P4.6 A22 Segment Address Line
O CAN1_TxD CAN1 Transmit Data Output
92 O P4.7 A23 Most Significant Segment Address Line
O CAN2_TxD CAN2 Transmit Data Output
RD 95 O External Memory Read Strobe. RD is activated for every external instruction or data
read access.
WR/WRL 96 O Exter nal Memo ry Wr ite Strobe. In WR -mode this pin is activated for ever y exte rnal
data write access. In WRL mode this pin is activated for low Byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
READY/
READY 97 I Ready Input. The active level is programmable. When the Ready function is
enabled, t he selecte d inactive leve l at this p in, dur ing an exter nal memo ry a ccess,
will force the in sertion o f waitsta te cyc les un til the pin re tur ns t o the s elect ed act ive
level.
ALE 98 O Address Latch Enable Output. In case of use of external addressing or of multi-
plexed mode, this signal is the latch command of the address lines.
EA 99 I Exter nal Access En able pin. A low level appl ied to this pin dur ing and after Re set
forces the ST10F269 to start the program from the exte rnal mem ory spac e. A high
level forces the MCU to start in the internal memory space.
Symbol Pin Type Function
ST10F269 2 - PIN D ATA
11/184
P0L.0 - P0L.7,
P0H.0
P0H.1 - P0H.7
100-107,
108,
111-117
I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state.
In case of an exter nal bus configuration, PO RT0 ser ves as the addres s (A) and as
the ad dress / data (A D) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bu s modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7 I/O D8 - D15
Multip lexed bus modes
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7 A8 – A15 AD8 - AD15
P1L.0 - P1L.7
P1H.0 - P1H.7 118-125
128-135 I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus (A)
in demultiplex ed bus modes and also after switching from a demultiple xed bus mode
to a multiplexed bus mode .
The following PORT1 pins have alternate functions:
132 I P1H.4 CC24IO CAPCOM2: CC24 Capture Input
133 I P1H.5 CC25IO CAPCOM2: CC25 Capture Input
134 I P1H.6 CC26IO CAPCOM2: CC26 Capture Input
135 I P1H.7 CC27IO CAPCOM2: CC27 Capture Input
XTAL1 138 I XTAL1 Oscillator amplifier and/or external clock input.
XTAL2 137 O XTAL2 Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
RSTIN 140 I Reset Input with Schmitt-Trigger char acteristics. A low level at this pin for a specified
duration while the oscillator is running resets the ST10F269. An internal pull-up
resistor permits power-on reset using only a capacitor connected to VSS. In bidirec-
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT 141 O Internal Reset Ind ication Output. This pin is driven to a low level during hardware,
software or watchd og timer res et.
RSTOUT
remains low until the EIN IT (end of ini-
tialization) instruction is executed.
NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to th e NMI trap routine. If bi t PW DCFG = ‘0 ’ in SYSC ON regist er, w hen the
PWRD N (power down) instructio n is execut ed, the NMI p in mu st be low in o rder to
force the ST10F269 to go into power down mode. If NMI is high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF 37 - A/D converter reference voltage.
VAGND 38 - A/D converter reference ground.
RPD 84 - Timing pin for the return from interruptible powerdown mode and synchronous /
asynchronous reset selection.
Symbol Pin Type Function
2 - PIN DATA ST10F269
12/184
VDD 46, 72,
82,93,
109,
126,
136, 144
- Digital Supply Vo ltage:
= + 5V during normal operation and idle mode.
VSS 18,45,
55,71,
83,94,
110,
127,
139, 143
- Digital Ground.
DC1
DC2 56
17 -
-3.3V Decoupling pin (2.7V on TQFP144 devices): a decoupling capacitor of ≥ 330
nF must be connected between this pin and nearest VSS pin.
Symbol Pin Type Function
ST10F269 3 - FUNCTIONAL DESCRIPTION
13/184
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F269 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
block diagram gives an overview of the different
on-chip components and the high bandwidth
intern al bus structure of the ST10F269.
Fi gure 3 : Block Diagram
P4.7 CAN2_TXD
P4.6 CAN1_TXD
P4.5 CAN1_RXD
P4.4 CAN2_RXD
Port 0
Port 1Port 4
Port 6 Port 5 Port 3
Port 2
GPT1
GPT2
ASC usa rt
BRG
CPU-Core and MAC Unit Internal
RAM
Watchdog
Interrupt Controller
8
32 16
PEC
16
16
CAN1
Port 7 Port 8
Exte r n a l Bus
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
16
Oscillator
Controller
16
16
128K/256 K Byte
and PLL
Flash Memory
XTAL1 XTAL2
2K Byte
16 15 88
8
16
3.3V Voltage
Regulator
10K Byte
XRAM
CAN2
4 - MEMORY ORGANIZATION ST10F 269
14/184
4 - MEM ORY ORGANI ZATION
The memory s pace of the ST10F269 is confi gured
in a unified memory architecture. Code memory,
data memory, registers and I/O ports are
organi zed within the same linear address space of
16M Bytes. The entire memory space can be
accessed Byte wise or Word wise. Particular
portions of the on-chip memory have additionally
been mad e directly bit addressable.
Flash: 128K or 256K Bytes of on-chip Flash
memory.
IRAM: 2K Bytes of on-chip internal RAM
(dual-port) is provided as a storage for data,
system sta ck, gener al pu rpose register banks and
code. A register bank is 16 W ordwi de (R0 to R15)
and / or Bytewide (RL0, RH0, …, RL7, RH7)
general purpose registers.
XRAM: 10K Bytes of on-chip extension RAM
(single port XRAM) is provided as a storage for
data, user stack and code.
The XRAM is divided into 2 areas, the first 2K
Bytes named XRAM1 and the second 8K Bytes
named XRAM2, connected to the internal XBUS
and are accessed like an external memory in
16-bit demultiplexed bus-mode without wait state
or read/write delay (50ns access at 40MHz CPU
clock on PQFP 144 devices and 62.5ns access at
32MHz CPU clock on TQFP144 devices). Byte
and Word accesses are allowed.
The XRAM1 address range is 00’E000h
- 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are
set. If XRAM1EN or XPEN is cleared, then any
access i n the address r ange 00’E 000h - 00’E7FFh
will be directed to external memory interface,
using the BUSCONx register corresponding to
addres s matching AD DRSELx register
The XRAM2 address range is 00’C000h
- 00’DFFFh if XPEN (bit 2 of SYSCON register),
and XRAM 2 (bit 3 of XPERC ON registe r are set).
If bit XRAM2EN or XPEN is cleared, then any
access in the address range 00’C000h
- 00’DFFFh will be directed to external memory
interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register.
As the XRAM appears like external memory, it
cannot be used as system stack or as register
banks. The XRAM is not provided for single bit
storage and therefore is not bit addressable.
SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of
address space is reserv ed for the special funct ion
register areas. SFRs are Wordwide registers
which are used to control and to monitor the
function of the different on-chip units.
CA N1: Address range 00’EF00h - 00’EFFFh is
reserved for the CAN1 Module access. The CAN1
is enabled by setting XPEN bit 2 of the SYSCON
register and by setting CAN1EN bit 0 of the new
XPERCON register. Accesses to the CAN Module
use demultiplexed addresses and a 16-bit data
bus (Byte accesses are pos sible). Two wait states
give an access time of 100ns at 40MHz CPU clock
on PQFP144 devices (or 125ns at 32MHz CPU
clock on TQFP144 devices). No tri-state wait
states are used.
CA N2: Address range 00’EE00h - 00’EEFFh is
reserved for the CAN2 Module access. The CAN2
is enabled by setting XPEN bit 2 of the SYSCON
register and by setting CAN2EN bit 1 of the new
XPERCON register. Accesses to the CAN Module
use demultiplexed addresses and a 16-bit data
bus (Byte accesses are pos sible). Two wait states
give an access time of 100ns at 40MHz CPU clock
on PQFP144 devices (or 125ns at 32MHz CPU
clock on TQFP144 devices). No tri-state wait
states are used.
In order to meet the needs of designs where more
memory is required than is provided on chip, up to
16M Bytes of external RAM and/or ROM can be
connected to the microcontroller .
Note If one or the tw o CAN mo dul es are used , P o rt
4 cannot be programmed to output all 8
segment address lines. Thus, only 4 segment
address lines can be used, reducing the
ex tern al memory sp ace to 5M Bytes (1M Byte
per CS line) .
Vis ibil i ty of XB U S Peripher als
In order to keep the ST10F269 compatible with
the ST10C1 67 and with the ST10F167, the XBUS
perip hera ls can be sel ected to be visible and / or
accessible on the external address / data bus.
CAN1EN and CAN2EN bits of XPERCON register
must be set. If these bits are cleared before the
global enabling with XPEN-bit in SYSCON
register, the corresponding address space, port
pins and interrupts are not occupied by the
peripheral, thus the peripheral is not visible and
not available. Refer to Chapter : S pecial F unction
Registe r Overvi ew on page 125.
ST10F 269 4 - MEMORY ORGA NIZAT ION
15/184
Fi gure 4 : ST10F2 69 On-chip M emo ry Mapping
14
07
06
05
04
00’4000
01
00
00’0000
02
00’C000
00’FFFF
SFR : 512 Byt es
00’FE00
00’FDFF
IRAM : 2K Bytes
00’F600
** Bank 0L may be remapped from segment 0 to segment 1 (Bank 1L) by setting SYSCON-ROMS1 (before EINIT)
RAM, SFR and X-pheripherals are
ma pped int o t he address space.
Segment 4Segment 3Segment 2Segment 1Segme nt 0
Data
Page
Number
Absolute
Memory
Address
00’6000
00’F1FF
ES FR : 512 Bytes
00’F000
00’EFFF
CAN1 : 25 6 By tes
00’EF00
00’EEFF
CAN2 : 25 6 By tes
00’EE00
00’E7FF
XRAM1 : 2K Bytes
00’E000
00’DFFF
XRAM2 : 8K Bytes
00’C000
03
00’EC14
Real Time Clock
00’EC00
Block 2 = 8K Bytes
Internal
Flash
Memory
Block 1 = 8K Bytes
Block 0 = 16K Bytes
Bank OL
01’0000
01’8000
02’0000
03’0000
0C
04’0000
10
05’0000
Block6 = 64K B yt es*
Block5 = 64K B yt es*
Block4 = 64K B yt es
Block3 = 32K Bytes
Block2**
Block1**
Block0** Bank 1L
Bank 1H
Data Page Number and Absolute Mem ory Addr ess are he xadecim al values.
08
*R eserve d area for 128K versions.
4 - MEMORY ORGANIZATION ST10F 269
16/184
XPERCON (F02 4h / 12h ) ESFR R eset Value: - - 05h
Note: - When both CAN are disabled via XPER-
CON setting, then any access in the
address range 00’EE00h - 00’EFFFh will
be directed to external memory interface,
using the BUSCONx register correspond-
ing to address m atching ADDRSELx regis-
ter . P4.4 and P4.7 can be used as General
Purpose I/O when CAN2 is disabled, and
P4.5 and P4.6 can be used as General
Pur pos e I/O when CAN1 is disabled.
- The default XPER selection after Reset is
identical to XBUS configuration of
ST10C167: XCAN1 is enabled, XCAN2 is
disabled, XRAM1 (2K Byte compatible
XRAM) is enabled, XRAM2 (new 8K Byte
XRAM) is d isabled.
- Register XPERCON cannot be changed
after the global enabling of XPeripherals,
i.e. after the setting of bit XPEN in the
SYSCON register.
- In EMUlation mode, all the XPERipherals
are enabled (XPERCON bit are all set).
The access to external memory and/or
XBus is controlled by the bondout chip.
- When the Real Time Clock is disabled
(RTCEN = 0), the clock oscillator is
switch-off if the ST10 enters in
power-down mode. Otherwise, when the
Real Time Clock is enabled, the bit
RTCOFF of the RTCCON register allows
to choose the power-down mode of the
clock oscillator (See Chapter : Real Time
Clock on page 105).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-----------
RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN
RW RW RW RW RW
CAN1EN CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XPeripher al and its functions are disabled. P4.5 and P4.6 pins can be
used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if
CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XPeripher al and its functions are disabled. P4.4 and P4.7 pins can be
used as general purpose I/Os. Address r ange 00’EE00h-00’EEFFh is only directed to external memory if
CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1EN XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1
are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2EN XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal
XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTCEN RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access is perf ormed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also
’1’: The on-chip Real Time Clock is enabled and can be accessed.
ST10F269 5 - INTERNAL FLASH MEMORY
17/184
5 - INTERNAL FLASH MEMORY
5.1 - Overview
– 128K or 256K Byte on-ch ip Flash mem ory
– Two possibilities of Flash mapping into the CPU
address space
– Flash memory can be used for code and data
storage
– 32-bit, zero waitstate read access (50ns cycle
time at fCPU = 40MHz on PQFP144 devi ces and
62. 5ns cycl e tim e at fCPU = 32MHz on TQFP 144
devices)
– Erase-Program Controller (EPC) similar to
M29F400B S TM’s stand-alo ne Flash memo ry
• W ord-by-Word P rogrammabl e (16µs typical )
• Data polling and Toggle Protocol for EPC
Status
• Ready/Busy signal connected on XP2INT
inte r ru pt line
• Int ernal Power-On detec tion circuit
– M em ory Erase in blocks
• One 16K Byte, two 8K Byte, one 32K Byte, one
to th ree 64K Byte blocks
• Each block can be erased separately
(1.5 second typi cal)
• C hip erase (8.5 second typical)
• Each block can be separately protected
against programming and erasing
• Each protected bl ock can be temporary unpro-
tected
• When enabled, the read protection prevents
access to data in Flash memory using a pro-
gram running out of the Flash memory space.
Access to data of internal Flash can only be per-
formed with an inner pr otected program
– E ras e Su spend and Resum e Modes
• Read and Program another Block during erase
suspend
– Single Voltage operation, no need of de dicated
supply pin
– Low Power Consum pt ion:
• 4 5mA m ax. Read current
• 6 0mA m ax. Program or Erase current
• Automatic Stand-by-mode (50µA maximum)
– 1000 Erase-Progr am Cycl es per block, 20 years
of data retention time
– Operating temperature: -40 to +125oC / -40 to
+125oC
5.2 - Operational Overview
Read Mode
In standard mode (the normal operating mode)
the Flash appears like an on-chip ROM with the
same timing and functionality. The Flash module
offers a fast access time, allowing zero waitstate
access with CPU frequency up to 40MHz on
PQ FP144 devices and u p to 32 MHz on T QF P1 44
devices. Instruction fetches and data operand
reads are performed wi th all addressing modes of
the ST10F 269 inst ruct ion set.
In order to optimize the programming time of the
internal Flash, blocks of 8K Bytes, 16K Bytes,
32K Bytes, 64K By tes can be used. But the size of
the blocks does not apply to the whole memory
spa ce, see details in Table 2.
*Not available on 128K versions (reser ved areas).
Table 2 : 128K or 256K Byte Flash Memory Block Organi zation
Block Addresses (Segment 0) Addresses (Segment 1) Size (byte)
0
1
2
3
4
5*
6*
00’0000h to 00’3FFFh
00’4000h to 00’5FFFh
00’6000h to 00’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh*
04’0000h to 04’FFFFh*
01’0000h to 01’3FFFh
01’4000h to 01’5FFFh
01’6000h to 01’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh*
04’0000h to 04’FFFFh*
16K
8K
8K
32K
64K
64K*
64K*
5 - INTERNAL FLASH MEMORY ST10F269
18/184
Instructions and Commands
All operations besides normal read operations are
initiated and controlled by command sequences
wr i tte n to the Fla sh C om ma n d I nter fac e ( CI). T he
Command Interface (CI) interprets words written
to the Flash memory and enables one of the
foll owi ng operations:
– R ead memory array
– P rogram Word
– Block Erase
– Chip Erase
– E ras e Su spend
– E ras e Resum e
– B lock Pro tection
– B lock Tem porary Unprot ection
– Code Protection
Commands are composed o f several write cycles
at specific addresses of the Flash memory. The
different write cycles of such command
sequences offer a fail-safe feature to protect
against an inadvertent write.
A command only starts when the Command
Interface has decoded the last write cycle of an
operation. Until tha t last wr ite is perfor med, Flash
memo ry r emains in R ead Mode
Notes: 1. As it is not possible to perform write
operations in the Flash while fetching c ode
from Flash, the Flash commands must be
written by instructions executed from
inte rnal RAM or extern al memory.
2. Command write cycles do not need to
be consecutively received, pauses are
allowed, save for Block Erase command.
During this operation all Erase Confirm
commands must be sent to complete any
block erase operation before time-out
period expires (typically 96µs). Command
sequencing must be followed exactly. Any
invali d combination of commands wi l l reset
the Command Interface to Read Mode.
Status Registe r
This register is used to flag the status of the
memory and the result of an operation. This
register can be accessed by read cycles during
the Erase-Program Controller (EPC) operation.
Erase Operation
This Flash memory features a block erase
architecture with a chip erase capability too. Erase
is accomplished by executing the six cycle erase
command sequence. Additional command write
cycles can then be perfor med to erase more than
one block in parallel. When a time-out period
elapses (96µs) after the last cycle, the
Erase-Program Controller (EPC) automatically
starts and times the erase pulse and executes the
erase operation. There is no need to program the
block to be erased with ‘0000h’ before an erase
operation . Termi nation of operation is indicated in
the Flash status register. After erase operation,
the Flash memory locations are read as 'FFFFh’
value.
Erase Suspend
A block erase operation is typically executed
within 1.5 second f or a 64K Byte block. Erasure of
a memory block may be suspended, in order to
read data from another block or to program dat a in
anoth er block, and then resumed.
In-System P rogramming
In-system programming is fully supported. No
spec ial pr ogramming voltage is required. Because
of the automatic execution of erase and
programming algorithms, write operations are
reduced to t ransferring commands and data t o the
Flash and reading the status. Any code that
pro grams or erases Flash mem ory lo cations (that
writes data to the Flash) must be executed from
memory outside the on-chip Flash memory itself
(on-chip RAM or external memory).
A boot mechanism is provided to support
in-system programming. It works using serial link
via USA RT interf ace and a PC compatible or other
prog ramming host.
Read/ Write Protection
The Flash module supports read and write
protection in a very comfortable and advanced
protection functionality. If Read Protection is
installed, the whole Flash memory is protected
against any "external" read access; read
accesses are only possible with instructions
fetched directly from program Flash memor y. For
update of the Flash m emory a temporary disable
of Fl ash Read Protection is supported.
The device also features a block write protection.
Software locking of selectable memory blocks is
provided to protect code and data. This feature
will disable both program and e rase operations in
the selected block(s) of the memory. Block
Protection is accomplished by block specific
lock-bit which are programmed by ex ecuting a four
cycle command sequence. The locked state of
blocks is indicated by specific flags in the
according bl oc k status registers. A block may only
ST10F269 5 - INTERNAL FLASH MEMORY
19/184
be temporarily unlocked for update (write)
operations.
With the two possibilities for write protection -
whole memory or block specific - a flexible
installation of write protection is supported to
protect the Flash memory or parts of it from
unauthorized programming or erase accesses
and to provide virus-proof protection for al l sys tem
code blocks. All write protection also is enabled
during boot operation.
Power Supply, Reset
The F lash modul e uses a single p ower supply for
both read and write functions. Internally
generated and regulated voltages are provided f or
the program and erase operations from 5V supply.
Once a program or erase cycle has been
comple ted , the device resets to the standard read
mode. At power-on, the Flash memory has a
setup phase of some microseconds (dependent
on t he power s upply ram p-up). During this p hase,
Flash can not be read. Thus, if EA pin is high
(e x e cut ion will start from Flash memory), the CPU
will remains in reset state until the Flash can be
accessed.
5.3 - Arch i tectural Descri ption
The Flash module distinguishes two basic
operating modes, the standard read mode and the
command mode. The initial state after power-on
and after reset is the standard read mode.
5.3.1 - Read Mode
The Flash module enters the standard operating
mode, the read mode:
– After Reset command
– A f ter every completed erase operation
– A f ter every completed programm ing operation
– After every other completed command
execution
– Few microseconds after a CPU-reset has
started
– After incorrect address and data values of
command sequences or writing them in an
improper sequence
– After incorre ct write access to a read protected
Flash memory
The read mode remains active until the last
command of a command sequence is decoded
which starts directly a Flash array operation, such
as:
– eras e one or several blocks
– program a word into Flash array
– protect / temporary unprotect a block.
In the standard read mode read accesses are
directly controlled by the Flash memory array,
delivering a 32-bit double Word from the
addressed position. Read accesses are always
aligned to double Word boundaries. Thus, both
low order address bit A1 and A0 are not used in
the Fla sh array for read accesses. T he h igh order
addres s bit A 17/ A 16 de fine t he physical 64K Byte
seg men t being accessed within the Flash array.
5.3.2 - Command Mode
Every operation besides standard read operations
is initiated by commands written to the Flash
command register. The addresses used for
command cycles define in conjunction with the
actual state the specific step within command
sequences . Wit h the last command of a comm and
sequence, the Erase-Program Controller (EPC)
starts the execution of the command. The EPC
stat us is indicated during com mand exec ution by:
– The Status Register,
– The Ready/Busy signal.
5.3.3 - Ready/Busy Signal
The Ready/Busy (R/B) signal is connected to the
XPER2 i n terru p t node (XP2IC). When R/B is high,
the Flash is busy with a Program or Erase
operation and will not accept any additional
program or erase instruction. When R/B is Low,
the Flash is ready for any Read/Write or Erase
operation. The R/B will also be low when the
mem ory is put in Erase Susp end mod e.
This signal can be polled by reading XP2IC
register, or can be used to trigger an interrupt
when the Flash goes from Busy to Ready.
5.3.4 - Flash Status Register
The Flash Status register is used t o f lag the status
of the Flash memory and the result of an
operation . This register can be accessed by Re ad
cycles during the program-Erase Controller
operations. The program or erase operation can
be controlled by data polling on bit FSB.7 of
Status Register, detecti on of Toggle on FSB.6 and
FSB.2, or Error on FSB.5 and Erase Time-out on
FSB.3 bit. Any read attempt in Flash during EPC
operation will automat ically output these five bits.
The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6
and F SB.7. O ther bits are res er ve d for fu ture use
and sho uld be masked.
5 - INTERNAL FLASH MEMORY ST10F269
20/184
Fla sh Status (see note for address)
Note: The Address of Flash Status Register is the address of the word being programmed when
Programming operation is in progress, or an address within block being erased when Erasing
operation i s in progress .
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- FSB.7 FSB.6 FSB.5 - FSB.3 FSB.2 - -
RRR R R
FSB.7 Flash Status bit 7: Data Polling Bit
Programming Operation: this bit outputs the complement of the bit 7 of the word being
pro gram med, and afte r complet ion , w ill ou t p ut the bit 7 of the wo rd prog r ammed.
Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion.
If the block selected f or erasure is (are) protect ed, FSB.7 will be set to ‘0’ for about 100 µs , and
then return to the pre vious addres sed memory data value.
FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the
Erase Suspend.
During P rogram operation in Erase Su spend M ode, FSB.7 will have t he sam e behaviour as in
nor m al Program exe cu tion outside the Suspend mod e.
FSB.6 Flash St at us bi t 6: To ggl e Bit
Programming or Erasing O pera tions: successive read operations of Flash Status register will
deliver complementary value s. FSB.6 will toggle each time the Flash Status register is read.
The Program operation is completed when two successive reads yield the same value. The
next read will out put the bit last programm ed, or a ‘1’ after Erase opera tio n
FSB.6 will be set to‘1’ if a read operation is attempted on an Erase Suspended block. In
addition , an Erase Suspe nd/R esu me command w ill caus e FS B.6 to toggle.
FSB.5 Flash Status bit 5: Erro r Bit
This bit is set to ‘1’ when there is a failure of Program, block or chip erase operations.This bit
will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently
programmed wit h ‘0’.
The error bit resets after Read/Reset instruction.
In case o f suc ces s, the Erro r bit wil l be set to ‘0’ during Program or Erase and then will o u tpu t
the bit la st programmed or a ‘1’ after erasing
FSB.3 Flash Status bit 3: Erase Time-out Bit
This bit is cleared by the EPC when the last Block Erase command h as been entered to the
Command Interface and it is awaiting the Erase start. When the time-out period is finished,
after 96 µs, FSB.3 retur ns back to ‘1’.
FSB.2 Flash St at us bi t 2: To ggl e Bit
This toggle bit, together with FSB .6, can be used to determine the chip st atus during the Erase
Mode or Erase Suspend Mode. It can be used also to identify the block being Erased
Suspended. A R ead operation will caus e FSB.2 to Toggle du ring the Erase Mod e. If the Flash
is in Erase Suspend Mode, a Read operation from the Erase suspen ded block or a Program
operation into the Erase susp ended block will cause FSB.2 to toggle.
When the Fl ash is in Prog ram Mode during Erase Suspend, FSB.2 will be read as ‘1’ if addr ess
used is the address of the word being programmed.
After Erase completion with an Error status, FSB .2 will toggle when reading the faulty sector.
ST10F269 5 - INTERNAL FLASH MEMORY
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5.3.5 - Flash Protection Register
The Flash Protection register is a non-volatile register that contains the protection status. This register
can be read by using the Read Protection Status (RP) command, and programmed by using the dedi-
cated S et Protection com ma nd.
Flash Protection Register (PR)
*Not avalaible for 128K versions (reserved areas)
5.3.6 - Instructions Description
Twelve instructions dedicated to Flash memory
accesses are defined as follow:
Read/Reset (RD). The Read/Reset instruction
consist of one wr ite cycle with data XXF0h. it can
be optionally preceded by two CI enable coded
cycles (data xxA8h at address 1554h + data
xx54h at address 2AA8h). Any successive read
cycle following a R ead/Reset instruction will read
the memory array. A Wait cycle of 10µs is
necessary after a Read/Reset command if the
mem ory was in program or Erase mode.
Program Word (PW). This instruction uses four
write cycles. Afte r the t wo Cl enabl e coded cycl es,
the Program Word command xxA0h is written at
address 1554h. The followi ng write cycle wil l latch
the address and data of the word to be
pro grammed. Mem or y programming c an be do ne
only by writing 0's instead of 1's, otherwise an
error occurs. During programming, the Flash
Status is checked by reading the Flash Status bit
FSB.2, FSB.5, FSB.6 and FSB.7 which show the
status of the EPC. FSB.2, FSB.6 and FSB.7
determine if programming is on going or has
comple ted , and FSB.5 allows a check to be made
for any possible error.
Block Erase (BE). This instruction uses a
minimum of six command cycles. The erase
enable command xx80h is written at address
1554h after the two-cycle CI enable sequence.
The erase confirm code xx30h must be written at
an address related to the block to be erased
pre ce ded by the exec ution of a second CI enable
sequence. Additional erase confirm codes must
be given to erase m ore than on e block in parallel.
Additional erase confirm commands must be
wr itten within a def ined time-out p erio d. The input
of a new Block Erase command will restart the
time-o ut period .
W hen th is time-out peri od has elapsed, the erase
starts. The status of the internal timer can be
monitored through the level of FSB.3, if FSB.3 is
‘0’, the Block Erase command has been giv en and
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP - - - - - - - - BP6* BP5* BP4 BP3 BP2 BP1 BP0
BPx Block x Protection Bit (x = 0...6)
‘0’: the Block Protection is enabled for block x. Programming or erasing the block is not
possible, unless a Block Temporary Unprotection command is issued.
1’: the Block Protection is disabled for block x.
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Block Protection using the Block Temporary Unprotection instruction.
CP Code Protection Bit
‘0’: the Flash Code Protection is enabled. Read accesses to the Flash for execution not
performed in the Flash itself are not allowed, the returned value will be 009Bh, whatever the
content of the Flash is.
1’: the Flash Code Protection is disabled: read accesses to the Flash from external or internal
RAM are allowed
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Code Protection using the Code Temporary Unprotection instruction.
ST10F269 5 - INTERNAL FLASH MEMORY
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If the second command given is not an erase
confirm or if the coded cycles are wrong, the
instr uction aborts, and the device is reset to Read
Mode. It is not necessary to program the block
with 0000h as the EPC will do this automatically
before the erasing to FFFFh. Read operations
after the EPC has started, output the Flash Status
Register.
Durin g the execution of the erase by the EPC, the
device accepts only the Erase Suspend and
Read/Reset instructions. Data Polling bit FSB.7
returns ‘0’ while the erasure i s in progress, and ‘1’
when it has com pleted. The To ggle bit FSB.2 and
FSB.6 toggle during the erase operation. They
stop when erase is completed. After completion,
the Error bit FSB.5 returns ‘1’ if there has been an
erase failure because erasure has not completed
even after the maximum number of erase cycles
have been executed by the EPC, in this case, it
will be necessary to input a Read/Reset to the
Command Interface in order to reset the EPC.
Chip Erase (CE). This instruction uses six write
cycles. The Erase Enable command xx80h, must
be written at address 1554h after CI-Enable
cycles. The Ch ip Erase command xx10h m ust be
given on the sixth cycle after a second C I-Enabl e
sequence. An error in command sequence will
reset the CI to Read mode. It is NOT necessary to
pro gram the block with 00 00h as the EPC will do
this automatically before the erasing to FFFFh.
Read operations after the EPC has st arted output
the Flas h Status Register. During the execution of
the erase by the EPC, Data Polling bit FSB.7
returns ‘0’ while the erasure i s in progress, and ‘1’
when it has completed. The FSB.2 and FSB.6 bit
toggle during the erase operation. They stop when
erase is f inished. T he FSB .5 error bit r eturns "1" in
case of failure of the erase operation. The error
flag is set after the maximum number of erase
cycles have been executed by the EPC. In this
case, it will be necessary to input a Read/Reset to
the Comma nd Interface in order to reset the EPC.
Erase Suspend (ES). This instruction can be
used to suspend a Block Erase operation by
giving the command xxB0h without any specific
address. No CI-Enable cycles is required. Erase
Suspend operation allows reading of data from
another block and/or the program ming in another
block while erase is in progress. If this command
is given during t he t ime-out period, it will termi nate
the time-out period in addition to erase Suspend.
The Toggle bit FSB.6, when monitored at an
address that belongs to the block being erased,
stops togg ling when Erase Suspend Com mand is
effective, It happens between 0.1µs and 15µs
after the Erase Suspend Command has been
written. The Flash will then go in normal Read
Mode, and read from blocks not being erased is
valid, while read from block being erased will
output FSB.2 toggling. During a Suspend phase
the o nly instructions valid are Erase Resum e and
Program Word. A Read / Reset instruction d uring
Erase s uspend wi ll definitely abor t the E rase a nd
result in invalid data in the block being erased.
Erase Resume (ER). This instruction can be
given when the memory is in Erase Suspend
State. Erase can be resumed by writing the
command xx30h at any address without any
Cl-enable sequence .
Program during Erase Suspend. The Program
Word instructi on during Erase Suspend is allowed
only on bl oc ks that ar e not Er as e-suspended. This
instruction is the same than the Program Word
instruction.
Set Protection ( SP) . This inst ruction can be used
to enable both Block Protection (to protect each
block independently from accidental Erasing-Pro-
gramming Operation) and Code Protection (to
avoid code dump). The Set Protection Command
must be given after a speci al CI-Protection Enab le
cycles (see instruction table). The follow ing Write
cycle, will progr am the Protec tion Regi ster. To pr o-
tect the block x (x = 0 t o 6), the dat a bit x must be
at ‘0 ’. To protec t the code, bit 15 of the data must
be ‘0’. Enabling Block or Code Protection is per-
manent and can be cleared only by STM. Block
Temporary Unprotection and Code Temporary
Unprotec tion instruct ions are avai lable to allow the
customer to update the code.
Notes: 1. The new value programmed in
protection register w ill only becom e active
after a reset .
2. Bit that are already at ’0’ in protection
register must be confirmed at ’0’ also in
data latched during the 4th cycle of set
protection command, otherwise an error
may o ccu r.
Read Protection Status (RP). This instruction is
used to read the Block Protection status and the
Code Protection status. To read the protection
register (see Table 3), the CI-Protection Enable
cycles must be executed followed by the
command xx90h at address x2A54h. The
following Read Cycles at any odd word address
will output th e Block Protection Sta tus. The Read/
Reset command xxF0h must be written to reset
the protection interface.
Note: After a modification of protection register
(using Set Protection com mand), the Read
5 - INTERNAL FLASH MEMORY ST10F269
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Protection Status will return the new PR
val ue only after a reset .
Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the
blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block
Temporary Unprotection command xxC1h must be given to enable Block Temporary Unprotection. The
Command must be preceded by the CI-Protection Enable cycles and followed by the Read/Reset
comm and x xF0h.
Set Code Protection (SCP). This kind of protection allows the custom er to protect the propr ietar y code
written in Flash. If installed and active, Flash Code Protection prevents data operand accesses and
program branches into the on-chip Flash area from any location outside the Flash memory itself. Data
operand accesses and branches to Flash locations are only and exclusively allowed for instructions
ex ecuted from the Flash memory itself . Every read or jump to Flash perf ormed from another memory (like
internal RAM, external me mory) while Code P rotec tion is en abled, will give the opcode 009B h related to
TRAP #00 ill egal instruction. The CI-Prot ection Enable cycles m ust be sent to set the Code Prot ec tion. By
wr iting da ta 7FFF h at any odd word add ress, the Code Protec ted status is stored in the Flash Prot ecti on
Register (PR). Protection is permanent and cannot be cleared by the user. It is possible to temporarily
disable the Code Protection using Code Tempo rary Unprotec tion instr uction.
Note: Bits that are already at ’ 0’ in protection register must be confirmed at ’0’ also in data latched during
the 4th cycle of set protection command, otherw ise an error may occur.
Code Temporary Unprotection (CTU). This instruction must be used to temporary disable Code
Protection. This instruction is effective only if executed from Flash memory space. To restore the
pro tection status, without us ing a re set, it i s necessar y to use a Cod e Temporar y Pro tection instruction.
Syste m reset will reset also the Code Temporary Unprotected status. The Code Temporary Unprotection
comm and consists of the following write cycle:
MOV MEM, Rn ; This instruction MUST be executed from Flash memory space
W here MEM is an absolute address inside mem ory space, Rn is a register loaded with data 0FFFFh.
Code Temp orary Protection ( C TP). This instructi on allows to restore Code Protection. This operation is
effective only if executed from Flash memory and is necessar y to restore the protection status after the
use of a Code Temporary Unprotection instructi on.
The Code Temporary Protection comm and cons ists of the fol lowing write cycle :
MOV MEM, Rn ; This instruction MUST be executed from Flash memory space
W here MEM is an absolute address inside mem ory space, Rn is a register loaded with data 0FFFB h.
Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the
Flash with protected code (SCP), since the write/erase routines must be executed from a memory
external to Flash space. Usually, the wr ite/erase routines, executed in RAM, ends with a retur n to Fl ash
spa ce where a CTP instruction restore the protection.
ST10F269 5 - INTERNAL FLASH MEMORY
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Table 3 : Instructi ons
Notes 1. Address bi t A14, A15 and a bove are don’t c are for coded address in puts.
2. X = Do n’ t Care.
3. WA = Wr i te Addr es s: addre ss of me mory l ocation t o be programmed.
4. WD = Write Data: 16-bit data to be programmed
5. Opt i onal, addition al bl ock s addresses must be enter ed wi thin a tim e-out delay (96 µs) af te r l ast wr i te entry, t i m e-out stat us can be
verified t hrough FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is c ompleted or suspended.
6. Read Data Polling or Toggle bit until Erase complete s.
7. WP R = Write protec tion regi ster. To protect code, bit 15 of WP R must be ‘0 ’. To protect blo ck N (N=0,1,...), bit N of WPR must b e
‘0’. Bit that are already at ‘0’ in p ro tection register must also b e ‘0’ in WPR, else a writing error will occurs (it is not possible to write a
‘1’ in a bit already programmed at ‘0’).
Instruction Mne Cycle 1st
Cycle 2nd
Cycle 3rd Cycle 4th Cycle 5th
Cycle 6th
Cycle 7th
Cycle
Read/Reset RD 1+ Addr.1X 2Read Memory Array until a new write cycle is initiated
Data xxF0h
Read/Reset RD 3+ Addr.1x1554h x2AA8h xxxxxh Read Memory Array until a new write
cycle is initiated
Data xxA8h xx54h xxF0h
Program Word PW 4 Addr.1x1554h x2AA8h x1554h WA 3Read Data Polling or Tog-
gle bit until Program com-
pletes.
Data xxA8h xx54h xxA0h WD 4
Block Erase BE 6 Addr.1x1554h x2AA8h x1554h x1554h x2AA8h BA BA’ 5
Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h
Chip Erase CE 6 Addr.1x1554h x2AA8h x1554h x1554h x2AA8h x1554h Note 6
Data xxA8h xx54h xx80h xxA8h xx54h xx10h
Erase Suspend ES 1 Addr.1X2Read until Toggle stops, then read or program all data needed
from block(s) not being erased then Resume Erase.
Data xxB0h
Erase Resume ER 1 Addr.1X2Read Data Polling or Toggle bit until Erase completes or Erase is
suspen ded anoth er time.
Data xx30h
Set Block/Code
Protection SP 4
Addr.1x2A54h x15A8h x2A54h Any odd
word
address 9
Data xxA8h xx54h xxC0h WPR 7
Read
Protection
Status RP 4
Addr.1x2A54h x15A8h x2A54h Any odd
word
address 9Read Protection Register
until a new write cycle is
initiated.
Data xxA 8h xx5 4h xx90h Read PR
Block
Temporary
Unprotection BTU 4 Addr.1x2A54h x15A8h x2A54h X2
Data xxA8h xx54h xxC1h xxF0h
Code
Temporary
Unprotection CTU 1 Addr.1MEM 8Write cycles must be executed from Flash.
Data FFFFh
Code
Temporary
Protection CTP 1 Addr.1MEM 8Write cycles must be executed from Flash.
Data FFFBh
5 - INTERNAL FLASH MEMORY ST10F269
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8. MEM = any add ress insid e the F lash m emor y s pace. Abso lute add res si ng mod e must be used (M OV MEM , Rn) , and i nst ruct ion
must be exe cuted from Fl ash memory space.
9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h...
– Generally, command sequences cannot be
written to Flash by in structions fetched from t he
Flash itself. Thus, the Flash commands m ust be
written by instructions, executed from internal
RAM or external memo ry.
– Command cycles on t he CPU interface need not
to be consecutively received (pa uses allowed).
The CPU inter face delivers dummy read data for
not used cycles within command sequenc es.
– All addresses of command cycles shall be
defined only with Register-indirect addressing
mode in the acco rd i ng move inst ru cti o n s. Di re ct
addressing is not allowed for command
sequences. Address segment or data page
pointer are taken in to accoun t for the c om ma nd
address value.
5.3.7 - Reset Processing and Initial State
The Flash m odule distinguis hes two kinds of CPU
reset types
The lengtheni ng of CPU reset:
– Is not reported to external devices by
bidirectional pin
– Is not enabled in case of external start of CPU
after reset.
5.4 - Flash Memory Configuration
The default memory configuration of the
ST10F269 Memory is determined by the state of
the EA pin at reset. This value is stored in the
Internal ROM Enable bit (named ROMEN) of the
SYSCON register.
When RO MEN = 0, the interna l Flash is disabled
and external ROM is used for startup control.
Flash m em ory can la ter be enabled by setting the
ROMEN bit of SYSCON to 1. The code
performing this setting must not run from a
seg men t of the extern al ROM t o be replaced by a
segment of the Flash memory, otherwise
unexpected behaviour may occur.
For example, if external ROM code is located in
the first 32K Bytes of segment 0, the first
32K Bytes of the Flash must then be enabled in
seg men t 1. This is done by setting the ROMS1 bit
of SYSCON to 0 before or simultaneously with
setting of ROMEN bit. This must be done in the
externally supplied program before the execution
of the EIN IT i nstructi on.
If progra m execution starts from ex ternal memory,
but access to the Flash memory mapped in
segment 0 is later required, then the code that
performs the setting of ROMEN bit must be
executed either in the segment 0 but above
address 00’8000h, or from the internal RAM.
Bit ROMS1 only affects the mapping of the first
32K Bytes of the Flash memor y. All other par t s of
the Flash memory (addresses 01’8000h -
04’FFFFh) remain unaf f ect ed.
The SGT DIS Segmentation Disable / Enabl e m ust
also be set to 0 to allow the use of the full
256K Bytes of on-chip memory in addition to the
external boot memory. The correct procedure on
changing the segment ation registers must also be
obs erved t o prevent an unwanted trap condition:
– Instructions that configure the internal memory
must only be executed f rom external memory or
from the internal RAM .
– An Absolute Inter-Segment Jump (JMPS)
instruction must be executed after Flash
enabling, to the next i nstruct ion, even if this next
instruction is located in the consecutive addr ess.
– Whenever the internal Memory is disabled,
enabled or remapped, the DPPs must be
explicitly (re)loaded to enable correct data
accesses to the internal memory and/or external
memory.
5.5 - Application Examples
5.5.1 - Handling of Flash Addresses
All comman d, Block, Data and register addresses
to the Flash have to be located within the active
Flash memory space. The active space is that
address range to which the physical Flash
addresses are mapped as defined by the user.
When using data page pointer (DPP) for block
addresses make sure that address bit A15 and
A14 of the block address are reflected in both
LSBs of the selected DPPS.
Note: - For Command Instructions, address bit
A14, A15, A16 and A17 are don’t care.
This sim plify a l ot the appl ication sof tware,
becau se it min imize the use of DPP regis-
ters when using Command in the Com-
mand Interface.
- Direct addressing is not allowed for
Command sequence operations to the
Flash. Only Register-indirect addressing
can be used for command, block or
write-dat a accesse s.
ST10F269 5 - INTERNAL FLASH MEMORY
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5.5.2 - Basic Flash Access Control
When accessing the Flash all command write addresses have to be located within the active Flash
memory space. The active Flash memory space is that logical address range which is covered by the
Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that
address bi t A15 and A14 of the command addresses are reflected in both LSBs of the selected data page
pointer (A15 - DPPx.1 and A14 - DPPx.0).
In case of the command write addresses , address bit A14, A15 and abov e are don’t care. Thus, comm and
wr ites c an be performed by onl y using one DPP registe r. T his a llow to have a more s imple and c om pact
application sof tware.
Another - advantageous - possibility is to use the extended segm ent instruct ion for addressin g.
Note: The direct addressing mode is not allowed for write access to the Flash address/command
register. Be aware that the C compiler may use this kind of addressing. For write accesses to
Flash modu le alway s the indirect addre ssing mode has to be selected.
The following basic ins truction sequences show examples for diff erent addressing possibilities.
Princi ple example of address generation for Flash commands and registers:
W hen using data page pointer (D PP0 is this examp le)
MOV DPP0,#08h ;adjust data page pointers according to the
;addresses: DPP0 is used in this example, thus
;ADDRESS must have A14 and A15 bit set to ‘0’.
MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence
;address 2AA8h, 1554h ... ) or the Flash write
;address
MOV Rwn,#DATA ;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV [Rwm],Rwn;indirect addressing
W hen using the extended s egm ent instr uc tion:
MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence
;address (2AA8h, 1554h ... ) or the Flash write
;address
MOV Rwo,#DATA ;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV Rwn,#SEGMENT ;the value of SEGMENT represents the segment
;number and could be 0, 1, 2, 3 or 4 (depending
;on sector mapping) for 256KByte Flash.
EXTS Rwn,#LENGTH ;the value of Rwn determines the 8-bit segment
;valid for the corresponding data access for any
;long or indirect address in the following(s)
;instruction(s). LENGTH defines the number of
;the effected instruction(s) and has to be a value
;between 1...4
MOV [Rwm],Rwo;indirect addressing with segment number from
;EXTS
5 - INTERNAL FLASH MEMORY ST10F269
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5.5.3 - Programming Examples
Most of the microcontroller programs are written in the C language where the data page pointers are
automatical ly set by the compiler. But because the C compiler m ay use the not allow ed direct addressing
mode for Flash write addresses, it is necessary to program the organizati onal Flash accesses (command
seq uences ) with assembler in-line routines which use indire ct addressing.
Example 1 Perform ing the command Read/ Reset
We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been
mapp ed to segm ent 1.
According to the usual wa y of ST10 data addressing with data page pointers, address bit A15 and A14 of
a 16-bi t command write address sele ct the data page pointer (DPP) w hich contain s the upp er 10-bit for
building the 24-bit physical data address. Address bit A13...A0 represent the address offset. As the bit
A14... A17 are "don’t care" when written a Flash command in the Command Interf ace (CI), we can choose
the mos t convenient DPPx register for add ress hand ling.
The following examples are making usage of DPP0. We just have to make sure, that DPP0 points to
acti ve F las h m emory spa c e.
To be independent of mapping of sector 0 we choose for all DPPs which are used for Flash address
handling, to point to segment 2.
For this reason we load DPP0 with value 08h (00 0000 l000b).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SCXT DPPO, #08h ;push data page pointer 0 and load it to point to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #0F0h ;load register R7 with Read/Reset command
MOV [R5], R7 ;command cycle 3. Address is don’t care
POP DPP0 ;restore DPP0 value
In the example above the 16-bit registers R5 and R6 are used as auxiliary registers for indirect
addressing.
Example 2 Perform ing a Program Word c om man d
We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been
mapp ed to segme nt 1.Th e dat a to be written is loaded in register R13, the a ddress to be programme d is
loaded in register R11/R12 (segment number in R11, segment offset in R12).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SXCT DPPO, #08h ;push data page pointer 0 and load it to point to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #0A0h ;load register R7 with Program Word command
MOV [R5], R7 ;command cycle 3
POP DPP0 ;restore DPP0: following addressing to the Flash
;will use EXTended instructions
;R11 contains the segment to be programmed
ST10F269 5 - INTERNAL FLASH MEMORY
29/184
;R12 contains the segment offset address to be
;programmed
;R13 contains the data to be programmed
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R13 ;command cycle 4: the EPC starts execution of
;Programming Command
Data_Polling:
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
MOV R6, R7 ;save it in R6 register
;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.7)
XOR R7, R13
JNB R7.7, Prog_OK
;Check if FSB.5 = 1 (Programming Error)
JNB R6.5, Data_Polling
;Programming Error: verify is Flash programmed
;data is OK
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
;Check if FSB.7 = Data.7
XOR R7, R13
JNB R7.7, Prog_OK
;Programming failed: Flash remains in Write
;Operation.
;To go back to normal Read operations, a Read/Reset
;command
;must be performed
Prog_Error:
MOV R7, #0F0h ;load register R7 with Read/Reset command
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;address is don’t care for Read/Reset command
... ;here place specific Error handling code
...
...
;When programming operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Prog_OK:
....
....
5 - INTERNAL FLASH MEMORY ST10F269
30/184
Example 3 Performing the Block Erase com man d
We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been
mapped to segment 1.The registers R11/R12 contain an address related to the block to be erased
(segment number in R11, segment of fset i n R12, f or e xample R11 = 01h, R12= 4000h wil l erase the bloc k
1 - first 8K b yte block).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SXCT DPPO, #08h ;push data page pointer 0 and load it to point ;to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #080h ;load register R7 with Block Erase command
MOV [R5], R7 ;command cycle 3
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 4
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 5
POP DPP0 ;restore DPP0: following addressing to the Flash
;will use EXTended instructions
;R11 contains the segment of the b lock to be erased
;R12 contains the segment offset address of the
;block to be erased
MOV R7, #030h ;load register R7 with erase confirm code
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;command cycle 6: the EPC starts execution of
;Erasing Command
Erase_Polling:
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
;Check if FSB.7 = ‘1’ (i.e. R7.7 = ‘1’)
JB R7.7, Erase_OK
;Check if FSB.5 = 1 (Erasing Error)
JNB R7.5, Erase_Polling ;Programming failed: Flash remains in Write
;Operation.
;To go back to normal Read operations, a Read/Reset
;command
;must be performed
Erase_Error:
MOV R7, #0F0h ;load register R7 with Read/Reset command
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;address is don’t care for Read/Reset command
... ;here place specific Error handling code
...
...
;When erasing operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Erase_OK:
....
ST10F269 5 - INTERNAL FLASH MEMORY
31/184
....
5 .6 - Bo ots trap Loa de r
The built-in bootstrap loader (BSL) of the
ST10F269 provides a mechanism to load the
startup program through the serial interface after
reset. In th is case , no e xternal memory or inte rnal
Flash memory is required for the initialization
code st arting at location 00’0000h (see Figure 5).
The bootstrap loader moves code/data into the
internal RAM, but can also transfer data via the
serial interface into an external RAM using a
second level loader routine. Flash Memory
(internal or external) is not necessary, but it may
be used to provide lookup tables or “core-code”
like a set of general purpose subroutines for I/O
operations, number crunching, system
in it ia li zat io n, etc.
The bootstrap loader can be used to load the
complete application software into ROMless
systems, to load temporary software into
complete systems for testing or calibration, or to
load a programming routi ne for Flash devices.
The BSL mechanism can be used for standard
system startup as well as for special occasions
like system maintenance (firmer update) or
end-of-line programming or testing.
5.6.1 - Entering the Bootstrap Loader
The ST10F269 e nters BSL mode whe n pin P 0L.4
is s ampled low at the end o f a hardware reset. In
this case the built-in bootstrap loader is activated
independent of the selected bus mode.
The bootstrap loader code is stored in a special
Boot-ROM. No part of the standard mask Memory
or Flash Memory area is required for this.
After entering BSL mode and the respective
initialization the S T10F269 scans the RXD0 l ine to
receive a zero Byte, one start bit, eight ‘ 0’ data bits
and one stop bit.
From the duration of this zero Byte it calculates
the corresponding Baud rate f actor wit h respect to
the current CPU clock, initializes the serial
interface ASC0 accordingly and switches pin
TxD0 to output.
Using this Baud rate, an identification Byte is
returned to the host that provides the loaded data.
This identification Byte identifies the device to
be booted. The identification byte is D5h for
ST10F269.
Fi gure 5 : Bootstrap Loader Sequence
0
0
0
0
0
0
0
0
00
00
00
00
RSTIN
TxD0
Internal Boot Memory (BSL) routine 32 Byte user software
2)
3)
RxD0
CSP:IP
4)
0
00
00000
6)
P0L.4
1) BSL initialization time
2) Z ero Byte (1 start bit, ei ght ‘ 0’ data bits, 1 st op bit), s ent by host.
3) Identification Byte (D5h), sent by ST10F269.
4) 32 Bytes of co de / data, sent by h ost.
5) Cau t i o n: T xD0 is onl y driven a c ertain tim e af ter rece ptio n of t h e zero By te.
6) Int e rnal Boo t ROM.
1)
0
0
000000000000000000000000000000000000000000000000000000000000000
5)
5 - INTERNAL FLASH MEMORY ST10F269
32/184
W hen the S T1 0F269 has entered B S L m ode, the following configu ration is automat ically set (values that
deviate from t he normal reset v alues, are marked):
In this case, the watchdog timer is disabled, so the
bootstrap loading sequence is not time limited.
Pin TXD0 is configured as output, so the
ST 10F2 69 can retur n the identification Byte.
Even if the internal Flash is enabled, n o code can
be executed out of it.
The h ardware that activate s the BSL during res et
may be a simple pull-down resistor on P0L.4 for
systems that use this feature upon every
hardware reset.
A switchable solution (via jumper or an external
signal) can be used for systems that
only temporarily use the bootstrap loader (see
Figure 6).
After sending the identification Byte the
ASC0 receiver is enabled and is ready to
receive the initial 32 Bytes from the host. A half
duplex connection is therefore sufficient to feed
the BSL .
5.6.2 - Memor y Configuration After Reset
The configuration (and the accessibility) of the
ST10F269’s memory areas after reset in
Bootstrap-Loader mode differs from the standard
case. Pin EA is not evaluated when BSL mode is
selec ted, and accesses to the i nter nal Flash area
are partly redirected, while the ST10F269 is in
BSL mode (see Figure 7). All code fetches are
made from the special Boot-ROM, while data
accesses read from the internal user Flash. Data
accesses will return undefined values on
ROMless devices.
The code in the Boot-ROM is not an invariant
feature of the ST10F269. User software should
not try to execute code from the internal Flash
area while the BSL mode is still active, as these
fetches will be redirected to the Boot-ROM. The
Boot-ROM will also “move” to segment 1, when
the internal Flash area is mapped to segment 1
(see Figure 7).
Watchdog Timer: Disabled Register SYSCON: 0E00h
Context Po inter CP: FA00h Register STKUN: FA40h
Stack Pointer SP: FA40h Register STKOV: FA0Ch 0<->C
Register S0CON: 8011h Register BUSCON0: acc. to startup configuration
Register S0BG: Acc. to ‘00’ Byte P3.10 / TXD0: ‘1’
DP3.10: ‘1’
Fi gure 6 : Hardware P rovisions to Activat e the B SL
RPOL.4
8kΩ
Circuit 1
POL.4 POL.4 Normal Boot
BSL
External
Signal
RPOL.4
8kΩ
Circuit 2
ST10F269 5 - INTERNAL FLASH MEMORY
33/184
Fi gure 7 : Memory Configuration after Reset
5.6.3 - Loading the Startu p Code
After sending the identification Byte the BSL
enters a loop to receiv e 32 Bytes via ASC0. These
Byte are stored sequentially into locations
00’FA40h through 00’FA5Fh of the internal RAM.
So up to 16 instructions may be placed into the
RAM area. To execute the loaded code the BSL
then jum ps to location 00 ’FA40h, which is the first
loaded instruc t ion.
The bootstrap loading sequence is now
ter minated, t he ST10F269 remains in BSL mo de,
howe ver. Most probably the initially loaded routine
will load additional code or data, as an average
application is likely to require substantially more
than 16 instructions. This second receive loop
may directly use the pre-initialized interf ace ASC0
to receive data and store it to arbitrary
user-define d loc ati ons.
This sec ond level of loade d c ode may be t he f ina l
application code. It may also be another, more
sophisticated, loader routine that adds a
transmission protocol to enhance the integrity of
the loaded code or data. It may also contain a
code sequence to change the system
conf i guration and enable the bus i nterface to store
the received data into extern al memory.
This process m ay go t hrough s everal iterations or
may directly execute the final application. In all
cases the ST10F269 will still run in BSL mode,
that m eans with the watchdo g timer disabled a nd
limited access to the internal Flash area.
All code fetches from the internal Flash area
(00’0000h...00’7FFFh or 01’0000h...01’7FFFh, if
mapped to segment 1) are redirected to the
special Boot-ROM. Data fetches access will
access the interna l B oot-ROM of the ST10F2 69, if
any is available, but will return undefined data on
ROMless devices.
5.6.4 - Exiting Bootstr ap Loader Mode
In order to execute a program in norm al mode, the
BSL mode must be terminated first. The
ST 10F269 ex its BSL mode upon a software reset
(ignores the level on P0L.4) or a hardware reset
(P0L.4 mu st be h igh). After a res et the ST 10F2 69
will start executing from location 00’0000h of the
internal Flash or the external memory, as
programmed via pin EA.
16M Bytes 16M Bytes 16M Bytes
BSL mode active Yes (P0L.4=’0’) Yes (P0L.4=’0’) No (P0L.4=’1’)
EA pin High Low Access to application
Code fetch from internal
Flash area Test-Flash access Test-Flash access User Flash access
Data fetch from internal
Flash area User Flash access User Flash access User Flash access
IRAM
1
0
User
Flash
Test
Flash
Segment
2
255
Access to:
external
bus
disabled
internal
enabled
Flash
1
0
User
Flash
Test
Flash
Segment
2
255
Access to:
external
bus
enabled
internal
enabled
Flash
IRAM 1
0User
Flash
Segment
2
255
Access:
depends on
reset config
EA, Port0
depends on
reset config
EA, Port0
IRAM
5 - INTERNAL FLASH MEMORY ST10F269
34/184
5.6.5 - Choosing the Baud Rate fo r the BSL
The calculation of the serial Baud rate for ASC0
from the length of the first zero Byte that is
received, allows the operation of the bootstrap
loader of the ST10F269 with a wide range of B aud
rates. However, the upper and lo wer limits have to
be kept, in order to insure pr oper dat a transfer.
The ST10F269 uses timer T6 to measure the
length of the initial zero Byte. The quantization
uncertainty of this measurement implies the first
deviation from the real Baud rate, the next
deviation is implied by the computation of the
S0BRL reload value from the timer contents. The
formula below shows the association:
For a correct data transfer from the host to the
ST10F269 the maximum deviation between the
internal initializ ed Baud r ate for ASC0 and the real
Baud rate of the host shoul d be below 2.5%. The
devi ation (FB, in pe rcent) bet ween host Baud rat e
and ST10F269 Baud rate can be calculated via
the for m ula below:
Note: Function (FB) does not consider the
tolerances of os cillators and ot her devices
supporting the serial communication.
This Baud rate deviation is a nonlinear function
depending on the CPU clock and the Baud rate of
the host. The maxima of the function (FB)
increase with the host Baud rate due to the
smaller Baud rate pre-scaler factors and the
impl i ed higher quantization error (see Figure 8).
The minimum Baud r at e (BLow in the Figure 8) is
determined by the maximum count capacity of
timer T6, when measuring the zero Byte, and it
depends on the CPU clock. Using the maximum
T6 count 216 in the formula the minimum Baud
rate can be calcula ted. Th e lowest standard Ba ud
rate in t his case would be 1200 B aud. Baud rates
below BLow would cause T6 to overflow. In this
case AS C0 cann ot be initialized properly.
The maximum Baud rate (BHigh in the Figure 8)
is the highest Baud rate where the deviation still
does not exceed the limit, so all Baud rates
between BLow and BHigh are below the deviation
limit. The maxi m um standard Baud rate that fulfills
this requirement is 19200 Bau d.
Higher Baud rates, however, may be used as
long as the actual deviation does not exceed the
limit. A certain Baud rate (marked ’I’ in Figure 8)
may violate the deviation limit, while an even
higher Baud rate (marked ’II’ in Figure 8) stays
very well below it. This depends on the host
interface.
fCPU
32 S0BRL 1
+
()×
------------------------------------------------
BST10F269 =
S0BRL T6 36
–
72
--------------------
=
T6 9
4
---
fCPU
BHost
-----------------
×
=
,
FBBContr BHost
–
BContr
--------------------------------------------
100×
=
%,
FB2.5≤%
Fi gure 8 : Baud Rate Deviation Betw een Host and ST10F269
BLow
2.5%
FB
BHigh
I
II BHOST
ST10F 269 6 - CENTRA L PRO CESSING UNIT (CPU)
35/184
6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. A dditional hardware has been added
for a separate multiply and d ivide unit, a bit-mask
genera tor and a barrel shifter.
Most of the ST10F269 instructions can be exe-
cuted in one instruc tion cycle which requires 50ns
at 40MHz CPU clock (PQFP144 devices) and
62.5ns at 32MHz CPU clock (TQFP144 devices).
For exam ple, shift and rotate instruct ions are pro-
cessed in one instruction cycle i ndependent of the
number of bits to be shifted.
Multiple-cycle instructions have been optimized:
branches are carried out in 2 cycles, 16 x 16-bit
multiplication in 5 cycles and a 32/16-bit division
in 10 cycles .
The jump cache reduces the execution time of
repeatedly performed jumps in a loop, from
2 cycles to 1 cycle .
The CP U uses a bank of 16 word registers to run
the current cont ext. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip Internal RAM (IRAM) area. A Context
Pointer (CP) register determines the base
address of the activ e register bank t o be accessed
by the CPU.
The num ber of register bank s is only restricted by
the available Internal RAM space. For easy
parameter passing, a register bank may overlap
others.
A system stack of up to 1024 bytes is provided as
a storage for temporar y data. Th e system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register.
Two separate SFRs, STKOV and STKUN, are
implicitly compared against the stack pointer
value upon each stack access for the det ection of
a stac k overflow or underfl ow.
Fi gure 9 : CPU Bl ock Diagram (MAC Unit not included)
32
Internal
RAM
2K Byte
General
Purpose
Registers
R0
R15
MDH
MDL
Barrel-Shift
Mul./Div.-HW
Bit- Ma sk Gen.
ALU
16-Bit
CP
SP
STKOV
STKUN
Ex ec. Un it
Instr. Ptr
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Pg. Ptrs Code Seg. Ptr.
CPU
128K /25 6K Byt e
Flash
memory
16
16
Bank
n
Bank
i
Bank
0
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269
36/184
The System Con figuration Register SYSCON
This bit-addressable register provides general system configuration and control functions. The reset
value for register SYSCO N depends on the state of the PORT0 pins dur ing reset.
SYSCON (FF12h / 89h) SF R Reset Value: 0xx0h
Notes: 1. These bits are set directly or indirectly according to PORT0 and EA p i n configuration durin g reset sequence.
2. Register SYSCON cannot b e changed after execution of the EINIT instruction.
6.1 - Multiplier-a ccumulator Unit (MAC)
The MAC co-processor is a specialized co-pro-
cessor added to the ST10 CPU Core in order to
improve the performances of the ST10 Family in
signal proces sing algor ithm s.
Signal pr oces sing needs at leas t three specialized
units operating in parallel to achieve maximum
performance:
– A Multip ly - Acc u m u late Unit ,
– An Address Generation Unit, able to feed the
MAC Unit with 2 operands per cycle,
– A Rep eat Unit, to execute series of multiply-ac-
cumulate instructi ons.
The existing ST10 CPU has been modified to
include new addressing capabilities which enable
the CPU to supply the new co-processor with up
to 2 operands per instruction cy cle.
This new co-processor (so-called MAC) contains
a fast multiply-accumulate unit and a repeat unit.
The co-processor instructions extend the ST10
CPU instruction set with multiply, multiply-accu-
mulate, 32-bit signed arithmet ic operations.
A new transfer instruction CoMOV has also been
added to tak e benefit of the ne w addressing capa-
bilities.
1514131211109876543210
STKSZ ROM
S1 SGT
DIS ROM
EN BYT
DIS CLK
EN WR
CFG CS
CFG PWD
CFG OWD
DIS BDR
STEN XPEN VISI
BLE XPER-
SHARE
RW RW RW RW1RW1RW RW1RW RW RW RW RW RW RW
Bit Function
XPEN 0
1
XBUS Peripheral Enable Bit
Accesses to the on-chip X-Peripherals and their functions are disabled
The on-chip X-Peripherals are enabled and can be accessed.
BDRSTEN 0
1
Bidirectional Reset Enable
RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin
RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
OWDDIS 0
1
Oscillator Watchdog Disable Control
Oscillato r Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activ ity. If
there is no activity on XTAL1 for at least 1 µs, the CPU clock is switched automatically to PLL’s
base frequency (2 to 10MHz).
OWD is disabled. If the PLL is bypassed, the CPU cloc k is alwa ys driv en by XTAL1 signal. The PLL
is turned off to reduce power supply current.
PWDCFG 0
1
Power Down Mode Configuration Control
Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, oth-
erwise the instr uction h as no effect. To exit Power Down Mode, a n ex ternal reset must occurs by
asserting the RSTIN pin.
Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin.
CSCFG 0
1
Chip Select Configuration Control
Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
Unlatched Chip Select lines: CSx change with rising edge of ALE
ST10F 269 6 - CENTRA L PRO CESSING UNIT (CPU)
37/184
6.1.1 - Features
6.1.1.1 - Enhanced Ad dressing Capabilities
– New addressi ng m ode s inclu ding a double in di-
rect addressing mode with pointer post-modifi-
cation.
– Parallel Data Move: this mechanism allows one
operand move during Multiply-Accumulate in-
structions without penalty.
– New transfer i nstructions CoSTORE ( for fast ac-
cess to the MAC SFRs) and CoMOV (for fast
memory to memory table transfer).
6.1 .1 .2 - M u lti ply-Accumulate Unit
– One-cyc le execution for all MAC operations.
– 16 x 16-bit signed/unsigned par allel multiplier.
– 40-bit signed arithmetic unit with automatic sat-
uration mode.
– 40-b it ac c umulat or .
– 8-bi t left/right shifter.
– Full instruc tion set with mult iply and multiply-ac-
cumulate, 32-bi t signed arithmetic and compare
instructions.
6.1.1.3 - Program Cont rol
– Repeat Unit: allows some M AC c o-processor in -
structions to be re peated up to 8192 tim es. Re-
peated instructions may be interrupted.
– M A C interrupt (Class B Trap) on MAC condition
flags.
Fi gure 10 : MAC Unit Architecture
Note: * Sh ared with standard ALU.
Op erand 2Operan d 1
Control Un it
Repeat Unit
ST10 CPU
Interrupt
Controller
MSW
MRW
MAH MAL
MCW
Flags MAE
Mux
8-bit Left/Ri ght
Shifter
Mux
Mux
Sign Exte nd
16 x 16
Concatenation
signed/unsigned
Multiplier
40-bit Signed Arithmetic Unit
0h 0h08000h
40
16
40 40
32 32
16
40
40
40
40
40
Scaler
AB
40
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Regi st e r
QR1 GPR Offset Regi st e r
QX0 IDX Offset Register
QX1 IDX Offset Register
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269
38/184
6.2 - Instruction Set Summary
The Table 4 li sts the instr uc tions of the S T10 F269. Th e various addres sing m odes, instruct ion ope ration,
paramet ers for condi tional execution of instruct ions, opcod es and a deta iled description o f each instruc -
tion can be found in the “ST10 Fam ily Programming Manual ”.
Table 4 : Instruction Se t Su mmary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bit-wise AND, (word/byte operands) 2 / 4
OR(B) Bit-wise OR, (word/byte operands) 2 / 4
XOR(B) Bit-wise XOR, (word/byte operands) 2 / 4
BCLR C lear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bit-wise modify masked high/low byte of bit-addressable direct word memory
with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct word GPR and store result
in direct word GPR 2
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
ST10F 269 6 - CENTRA L PRO CESSING UNIT (CPU)
39/184
6.3 - MAC Co processor Speci fic Instructions
The following table gives an over view of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used with each
instruction.
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not.
New addressing capabilities enable the CPU to
suppl y t he MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accumulate, 32-bit signed arithmetic
operations and the CoMOV transfer instruction
have been added to the standard instruction set.
Full details are provided in the ‘ST10 Family Pro-
gramming Manual’. Double indirect addressing
requires two pointers. Any GPR can be used for
one pointer, the other poi nter is pro vided b y one of
two specific SFRs IDX0 and IDX1. Two pairs of
offset regist ers QR0/QR1 and QX0/QX1 are asso-
ciated wi th each pointer (GPR or IDXi).
The GPR pointer allows access to the entire
mem ory space, but IDXi are limited to t he in ter nal
Dual-P ort RAM, except f or the CoMOV instruction.
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update register with word
operand 4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct
word register from system stack 2
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Table 4 : Instruction Se t Su mmary
Mnemonic Description Bytes
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269
40/184
Mnemonic Addressing Modes Repeatability
CoMUL
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
CoMULu
CoMULus
CoMULsu
CoMUL-
CoMULu-
CoMULus-
CoMULsu-
CoMUL, rnd
CoMULu, rnd
CoMULu s, rnd
CoMULsu, rnd
CoMAC
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
CoMACu
CoMACus
CoMACsu
CoMAC-
CoMACu-
CoMACus-
CoMACsu-
CoMAC , rnd
CoMACu, rnd
CoMACus, rnd
CoMACsu, rnd
CoMACR
CoMACRu
CoMACRus
Rwn, Rwm
[IDXi⊗], [Rwn⊗]
Rwn, [RWm⊗]
No
No
No
CoMACRsu
CoMACR, rnd
CoMACRu, rnd
CoMACRus, rnd
CoMACRsu, rnd
CoNOP
[Rwm⊗] Yes
[IDXi⊗]Yes
[IDXi⊗], [Rwm⊗] Yes
CoNEG -NoCoNEG, rnd
CoRND
CoSTORE Rwn, CoReg No
[Rwn⊗], Coreg Yes
CoMOV [IDXi⊗], [Rwm⊗] Yes
ST10F 269 6 - CENTRA L PRO CESSING UNIT (CPU)
41/184
CoMACM
[IDXi⊗], [Rwm⊗] Yes
CoMACMu
CoMACMus
CoMACMsu
CoMACM-
CoMACMu-
CoMACMus-
CoMACMsu-
CoMACM, rnd
CoMACMu, rnd
CoMACMus, rnd
CoMACMsu, rnd
CoMACMR
CoMACMRu
CoMACMRus
CoMACMRsu
CoMACMR, rnd
CoMACMRu, rnd
CoMACMRus, rnd
CoMACMRsu, r nd
CoADD
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
CoADD2
CoSUB
CoSUB2
CoSUBR
CoSUB2R
CoMAX
CoMIN
CoLOAD
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
CoLOAD- No
CoLOAD2 No
CoLOAD2- No
CoCMP
CoSHL Rwm
#data4
[Rwm⊗]
Yes
No
Yes
CoSHR
CoASHR
CoASHR, rnd
CoABS
-
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
Mnemonic Addressing Modes Repeatability
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269
42/184
The Tab le 5 shows the various combi nations of pointer post- modific ation f or each of these 2 new address-
ing mod es. In this document the symbols “[Rwn⊗]” and “[IDXi⊗]” refer to t hese addressing modes .
Table 5 : Pointer Post- modification Combinat ions for IDXi and Rwn
Symbol Mnemonic Address Pointer Operation
“[IDXi⊗]” stand s for [I DXi](IDX
i) ← (IDXi) (no-op)
[IDXi+](IDX
i) ← (IDXi) + 2 (i=0,1)
[IDXi-] (IDXi) ← (IDXi) - 2 (i=0,1)
[IDXi + QXj](IDX
i) ← (IDXi) + (QXj) (i, j =0,1)
[IDXi - QXj](IDX
i) ← (IDXi) - (QXj) (i, j =0,1)
“[Rwn⊗]” stands for [Rwn] (Rwn) ← (Rwn) (no-op)
[Rwn+] (Rwn) ← (Rwn) + 2 (n=0-15)
[Rwn-] (Rwn) ← (Rwn) - 2 (n=0-15)
[Rwn + QRj] (Rwn) ← (Rwn) + (QRj) (n=0-15; j =0,1)
[Rwn - QRj] (Rwn) ← (Rwn) - (QRj) (n=0-15; j =0,1)
Table 6 : MAC Registers Referenced as ‘CoReg‘
Registers Description Address in Opcode
MSW MAC-Unit Status Word 00000b
MAH MAC-Unit Accumulator High 00001b
MAS “limited” MAH /signed 00010b
MAL MAC-Unit Accumulator Low 00100b
MCW MAC-Unit Control Word 00101b
MRW MAC-Unit Repeat Word 00110b
ST10F269 7 - EXTERNAL BUS CONTROLLER
43/184
7 - EXTERNAL BUS CONTRO LL ER
All of the external memory accesses are
performed by the on-chip externa l bus controller.
The EB C can be programmed to single c hip mode
when no external memory is required, or to one of
four diff erent external memory access modes:
– 16- / 18- / 20- / 24-bit address es and 16-bit data,
demultiplexed
– 16- / 18- / 20- / 24-bit address es and 16-bit data,
multiplexed
– 16- / 18- / 20- / 24-bit a ddress es and 8-bit data,
multiplexed
– 16- / 18- / 20- / 24-bit a ddress es and 8-bit data,
demultiplexed
In demul tiplexed bus modes addresses are output
on POR T 1 and dat a is input / output on PORT0 or
P0L, respectively. In the multiplexed bus modes
both addresses and data use PORT0 for input /
output.
Timing characteristics of the external bus
interface (memory cycle time, memory tri-state
time, length of ALE and read / write delay) are
programmable giving the choice of a wide range
of memories and external periph erals.
Up to 4 independent address windows may be
defined (using register pairs ADDRSELx /
BUSC ONx) to acces s different reso urces an d bus
characteristics.
These address windows are arranged
hierarchically where BUSCON4 overrides
BUSC ON3 and BUSCO N 2 overrides BUSCON 1.
All accesses to locations not covered by these 4
address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus
default) can be generated in order to sav e ext ernal
glue logic. Access to very slow memories is
sup ported by a ‘Ready’ fun ction.
A HOLD / HLDA protocol is available for bus
arbitration which shares external resources with
other bus masters.
The bus arbitration is enabled by setting bit
HLDEN in register PSW. After setting HLDEN
onc e, pins P6.7...P6.5 (BREQ, H LDA , HO L D) are
automatically controlled by the EBC. In master
mode (default after reset) the HLDA pin is an
output . By setting bit DP6.7 to’1’ the s lave mode is
selected where pin HLDA is switched to input.
This directly connects the slave controller to
anoth er master controller without glue logic.
For applications which require less external
memory space, the address space can be
restric ted t o 1M Byte, 256K Bytes or to 64K Bytes.
Port 4 outputs all 8 address lines if an address
spac e of 16M Byt es is used, otherwise four , two or
no address lines.
Chip select timing can be made programmable.
By default (after reset), the CSx lines chan ge half
a CPU clock cycle after the rising edge of ALE.
With the CSCFG bit set in the SYSCON register
the CSx lines change with the rising edge of ALE.
The activ e le vel of the READY pin can be set by bit
RDYPOL in the BUSCONx registers. When the
READY function is enabled for a specific address
window, each bus cycle within the window must
be terminated with the active level defined by bit
RDY PO L in the associated BUSCON register.
7.1 - Programmab le Chip Select Timing
Control
The ST10F269 allows the user to adjust the
pos ition of t he CSx line c hanges. By default (after
reset), the CSx lines change half a CPU clock
cycle (12.5ns at 40MHz of CPU clock on
PQ FP144 devices and 3 1.25 ns at 32M Hz of CPU
clock on TQFP144 devices ) after the rising edge
of ALE. With the CSCFG bit set in the SYSCON
register the CSx lines change with the rising edge
of ALE, thus the CSx lines and the address lines
cha nge at the same time (see Figure 11 ).
7.2 - READY Programmable Polarity
The active level of t he READY pin can be selected
by software via the RDY POL bit in the BUSC ONx
registers.
When the READY function is enabled for a
specific address window, each bus cycle within
this window must be terminated with the active
level def ined b y this RDYPOL bit in the associated
BUSC ON register.
BUSCONx r egisters are described in Secti on 20.2
-: S ys tem Configuration Registers .
Note ST10F269 as no internal pull-up resistor
on READY pin.
ST10F 269 8 - INTERRUPT S YSTEM
45/184
8 - INTERRUPT SYST EM
The interrupt response time for internal program
execution is from 125ns to 300ns at 40MHz CPU
clock on PQFP144 devices and 156.25ns to
375ns at 32MHz of CPU clock on TQFP144
devices.
The ST10F269 architecture supports several
mechanisms for fast and flexible response to
service requests that can be generated from
various sources (internal or external) to the
microcontroller. Any of these interrupt requests
can be serviced by the Interrupt Controller or by
the Peripheral Event Cont roller (PEC).
In contrast to a standard interrupt service where
the c urrent prog ram ex ecution is suspended and a
branch to the interrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service
implies a single Byte or Word data transfer
between any two memory locations with an
additional increment of either the PEC source or
destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
ser v i ce except when perfor mi ng in the cont inuous
transfer mode. When t his count er rea ch es zero, a
standard interrupt is performed to the
corresponding source related vector location.
PEC services are very well suited to perform the
transmission or the reception of blocks of data.
The ST10F269 has 8 PEC channels, each of
them offers such fast interrupt-driven data transfer
capabilities.
An interrupt control register which contains an
interr upt reques t flag, an interrupt ena ble flag and
an interrupt priority bit-field is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to o ne
of sixteen inter rupt priority levels. Onc e starting to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
pro cessing, each of the possible interrupt sources
has a dedicated vector location.
Software interrupt s are supported by means of the
‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
8.1 - External Interru pts
Fast external interrupt inputs are provided to
service external interrupts with high precision
requirements. These fast interrupt inputs feature
pro grammable edge dete ction (ri sing edge, falling
edge or both edges).
Fast external interrupts may also have interrupt
sources selected from other peripherals; for
example the CANx controller receive signal
(CANx_RxD) can be used to interru pt the syst em.
This new function is control led usi ng the ‘Ex ter na l
Inter ru pt Source Se lecti o n’ re gi ster EXISEL.
EXISEL (F1DAh / EDh) ESFR Reset Value: 0000h
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External In terru pt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alter nat e source ”.
‘11’: Inp ut from Por t 2 pin ANDed with “alternate source”.
EXIxSS Port 2 pin Alternate Source
0P2.8 CAN1_RxD
1P2.9 CAN2_RxD
2 P2.10 RTCSI (Timed)
3 P2.11 RTCAI (Alarm)
4...7 P2.12...15 Not used (zero)
8 - INTERRUPT SYSTEM ST 10F269
46/184
8.2 - Interrupt Registers and Vector s Location List
Table 7 shows all the available ST10F269 interrupt sources and the corresponding hardware-related
interrupt flags, vectors, v ector locations and trap (interrupt) numbers:
Table 7 : Interrupt Sources
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
ST10F 269 8 - INTERRUPT S YSTEM
47/184
Hardware traps are exceptions or error cond itions
that ar ise du ring run -time. They cau se immediate
non-maskable system reaction similar to a
standard interrupt service (branching to a
dedicat ed vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prioritized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap ser vices cannot not be interrupted
by standard interrupt or by P E C interrupt s.
8.3 - Interrupt Control Registers
All interrupt control registers are identically
org anized. The lower 8 bit s of an i nte rr upt control
register contain the complete interrupt status
information of the associated source, which is
required during one round of prioritization, the
upper 8 bits of the respective register are
reserved. All interrupt control registers are bit
addres sable and all bits can be re ad or written via
software.
This allows each interrupt source to be
programmed or modified with just one instruction.
When accessing interrupt control registers
through instructions which operate on Word data
types, their upper 8 bits (15...8) will return zeros,
when read, and will discard written data.
The la yout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h
GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
CAN1 Interface XP0IR XP0IE XP0INT 00’0100h 40h
CAN2 Interface XP1IR XP1IE XP1INT 00’0104h 41h
FLASH Ready / Busy XP2IR XP2IE XP2INT 00’0108h 42h
PLL Unlock/OWD XP3IR XP3IE XP3INT 00’010Ch 43h
Table 7 : Interrupt Sources (continued)
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
8 - INTERRUPT SYSTEM ST 10F269
48/184
xxIC (yyyyh / zzh) SFR Area Reset Value: - - 0 0h
8.4 - Exception an d Error Tra ps List
Table 8 s hows all of the possible ex cept ion s or erro r conditions that can arise durin g run-time :
* - All the class B traps ha v e the same trap number (and vector) and the same lower priority compare to the class A traps and to th e re se ts.
- Eac h class A tra ps h as a dedi cated trap numbe r (and vector). They are prior i tized in the second prior i ty l evel.
- The resets have the highest priority lev el and the same trap number.
- Th e PSW.ILVL CP U prio rity is forc ed to the highest level (15) when these excep tions are s ervi ced.
1514131211109876543210
--------xxIR xxIE ILVL GLVL
RW RW RW RW
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
Table 8 : Trap P riorities
Excep tion Cond ition Trap
Flag Trap
Vector Vector
Location Trap
Number Trap*
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
I
I
I
I
I
Reserved [002Ch - 003Ch] [0Bh - 0Fh]
Software Traps
TRAP Instruction Any
0000h – 01FCh
in steps of 4h
Any
[00h - 7Fh] Current
CPU
Priority
ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS
49/184
9 - CAPTURE/COMPARE (CAPCOM) UNITS
The ST10F269 has two 16 channels CAPCOM
units as described in Figure 12. These support
genera tion and control of timing se quences on up
to 32 channels with a maximum resolution of
200ns at 40M Hz CPU clock on PQF P144 devices
and 250ns at 32MHz CPU clock on TQFP144
devices. The CAPC OM units are typically used to
handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion,
software timing, or time recording relative to
external events.
Four 16-bit timers (T0/T1, T7/T8) with reload
registers provide two independent time bases for
the capture/compare register array (See Figures
Figure 13 and Figure 14).
The input clock for the timers is program mable to
several prescaled values of the internal system
clock, or may be derived from an overflow/
underflow of timer T6 in module GPT2. This
provides a wide range of variation for the timer
period and resolution and allows precise
adjustments to application specific requirements.
In addition, external count inputs for CAPCOM
timers T0 and T7 allow event scheduling for the
capture/compare registers relative to external
events.
Each of the two capture/compare register arrays
contain 16 dual purpose capture/compare
registers, each of which may be individually
allocated to eit her CAPCOM t i mer T0 or T1 (T7 or
T8, respectively), and programmed for capture or
compare functions. Each of the 32 registers has
one associated por t pin which serves as an input
pin for triggering the capture function, or as an
output pi n to indi cate the occurrence of a com pare
event. Figure 12 shows the basic structure of the
two CAPCOM units .
Fi gure 12 : CAP CO M Unit Block Diagram
Pin Tx
Input
Control
2n n = 3...10
GPT2 Timer T6
Pin
TxIN
CPU
Clock
Mode
Control
(Capture
or
Compare)
16
Capture inputs
Com pare ou tputs
Pin
Ty
Input
Control
2n n = 3...10
GPT2 Timer T 6
Over / Unde rflow
CPU
Clock
Reload Register TxREL
CAPCOM Timer Tx
Interrupt
Request
Sixt een 16-bi t
(Capture/Compare)
Registers
Over / Underflow
CAPCOM Timer Ty
Reload Register TyREL
16
Capture / Compare *
Interrupt Requests
Interrupt
Request
x = 0, 7
y = 1, 8
9 - CAPTURE/COMPARE (CAPCOM) UNITS ST10F269
50/184
* Th e CA PCOM2 unit provides 16 ca pture inputs, bu t only 12 co m pare outputs. CC2 4I to C C27I are inputs on l y.
Fi gure 13 : Block Diagram of CAPCOM Timers T0 and T7
Fi gure 14 : Block Diagram of CAPCOM Timers T1 and T8
Note: When an external input signal is
connected to the input lines of both T0 and
T7, these timers count the input signal
synchronously. T hus the two t i mers can be
regarded as one timer whose contents can
be compared with 32 capture registers.
When a capture/compare register has been
select ed for capture mode, the current contents of
the allocated timer will be latched (captured) into
the capture/compare register in response to an
external event at the por t pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is
genera ted.
Either a positiv e, a negative, or both a positiv e and
a negat ive external signal t ransition at the pi n can
be selected as the triggering eve nt. The contents
of all registers which have been selected for one
of the five compare modes are continuously
compared with the contents of the allocated
timers.
When a match occurs between the timer value
and the value in a capture /compare register,
specific actions will be taken based on the
selected compare mode (see Table 9).
The input frequencies fTx, for the timer input
selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies,
resolution and periods which result from the
selected pre-scaler option in TxI when using a
40MHz CPU clock on PQFP144 devices (or a
32MHz CPU clock on TQFP144 devices) are
listed in Table 10 and Ta ble 11 .
The numbe rs for th e timer periods are based on a
reload value of 0000h. Note that some numbers
may b e rounded to 3 significant figures.
Pin
X
Txl
CPU
Clock
TxR
MUX
GPT2 Timer T6
Over / Underflow
Edge Sel ect
TxIN
Txl
Txl TxM
Input
Control
Reload Register TxREL
CAPCO M Ti mer Tx TxIR Interrupt
Request
x = 0, 7
X
Txl
CPU
Clock
TxR
MUX
GPT2 Timer T6
Over / Underflow
TxM
Reload Register TxREL
CAPCOM Timer Tx TxIR Interrupt
Request
x = 1, 8
ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS
51/184
Table 9 : Compare Mo des
Compare Modes Function
Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match; several compare events per timer period are possible
Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer
period is generated
Double Register
Mode Two registers operate on one pin; pin toggles on each compare match; several compare events
per timer period are possible.
Table 10 : CAPCOM Timer Input Frequencies, Resolution and Periods (PQFP144 devices)
fCPU = 40MHz Timer Input Selection TxI
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler for fCPU 8 16 32 64 128 256 512 1024
Input Frequency 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
Period 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
Table 11 : CAPCOM Timer Input Frequencies, Resolution and Periods (TQFP144 devices)
fCPU = 32MHz Timer Input Selection TxI
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler for fCPU 8 16 32 64 128 256 512 1024
Input Frequency 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.125KHz
Resolution 250ns 500ns 1µs2µs4µs8µs16µs32µs
Period 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s 2.1s
10 - GENERAL PURPOSE TIMER UNIT ST10F269
52/184
10 - GENERAL PURPOSE TI MER UNIT
The GPT unit is a flexible multifunctional timer/
counter structure which is used for time related
tasks such as event timing and counting, pulse
width and duty cycle measurements, pulse
generation, or pulse multiplication. The GPT unit
contains five 16-bit timers organized into two
separate modules GPT1 and GPT2. Each t imer in
each module may operate independently in
several different modes, or may be concatenated
with another timer of the same module.
10.1 - GPT1
Each of the three timers T2, T3, T4 of the GPT1
module can be configured individually for one of
four basic modes of operat ion: timer, gated t imer,
counter mode and incremental interface
mode.
In timer mode, the input cloc k f or a t imer is derived
from the CPU clock, divided by a programmable
prescaler.
In counter mode, the timer is clocked in reference
to exter nal event s.
Pulse width or duty cycle measurement is
supported in gated timer mode where the
operation of a t imer is controlled by the ‘gate’ level
on an external input pin. For these purposes, each
timer has one associated port pin (TxIN) which
ser ves as gate or clock input.
Table 12 GPT1 Timer Input Frequencies,
Resolution and Periods (PQFP144 devices) and
Table 13 GPT1 Timer Input Frequencies,
Resolution and Periods (TQFP144 devices) list
the t imer input f requencies , resolut ion and periods
for each pre-scaler option at 40MHz (Table 12
GPT1 Timer Input Frequencies, Resolution and
Periods (PQFP144 devices)) or 32MHz (Table 13
GPT1 Timer Input Frequencies, Resolution and
Periods (TQFP144 devices)) CPU clock. This also
applie s to the Gated Time r Mod e of T3 a nd t o the
auxiliary timers T2 and T4 in Timer and Gated
Timer Mode. The count direction (up/down) for
each timer is programmable by software or may
be al tered dynam ically by an exter nal sig nal on a
po rt pin (TxEUD).
In Incremental Interface Mode, the GPT1 timers
(T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by
thei r respective inputs TxIN and TxE UD.
Direction and count signals are internally derived
from these two input signals so that the contents
of the respective timer Tx corresponds to the
sensor position. The third position sensor signal
TOP0 can be connected to an interrupt input.
Timer T3 has output t oggle latches (TxOTL) which
changes state on each timer ov er flow / underflow.
The st ate of this latch may be output on por t pins
(TxOUT) for time out monitoring of external
hardware components, or may be used internally
to clock timers T2 and T4 for high resolution of
long duration measurem ent s.
In addition to their basic operating modes, timers
T2 and T4 may be c onfigured as reload or capture
registers for timer T3. When used as capture or
reload registers, timers T2 and T4 are stopped.
The cont ents of timer T3 is captured into T2 or T4
in response to a signal at their associated input
pi ns (T x IN).
Timer T3 is reloaded wi t h the contents of T2 or T4
triggered either by an external signal or by a
selectable state transition of its toggle latch
T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions
of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated
without soft war e in te rven ti on.
Table 12 : GPT1 Timer Input Frequencies , Resolution and Periods (PQFP144 devices)
fCPU = 40MHz Timer Input Selection T2I / T3I / T4I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 8 16 32 64 128 256 512 1024
Input Freq 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
Period maximum 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
ST10F269 10 - G ENERAL PURPOSE TIMER UNIT
53/184
Table 13 : GPT1 Timer Input Frequencies , Resolution and Periods (TQFP144 devices)
Fi gure 15 : Block Diagram of GPT1
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement . It includes tw o t imers (T5,
T6) and a capture/reload register ( CA PREL). Both
timers can be c locked with an inp ut clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction (up/down) for each timer is
pro grammable by software or may additionally be
alter ed dynamically by an e xternal signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
overf lo w/underflow.
The st ate of this latch may be used to c lock timer
T5, or it ma y be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and t o cause a reload f rom the CA PREL re gister.
The CAPREL regist er may capture the contents of
timer T5 bas ed on an extern al signal transition on
the corresp ondin g port pin (CA P IN), an d tim er T 5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT 1 timer
T3 inputs T3IN and/or T3EUD. This is
advantageous when T3 operates in Incremental
Interface Mo de.
Table 14 GPT2 Timer Input Frequencies,
Resolution and Period (PQFP144 devices) and
Table 15 GPT2 Timer Input Frequencies,
fCPU = 32MHz Timer Input Selection T2I / T3I / T4I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 8 16 32 64 128 256 512 1024
Input Freq 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.125KHz
Resolution 250ns 500ns 1µs2µs4µs8µs16µs32µs
Period maximum 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s 2.1s
2n n=3...10
2n n=3...10
2n n=3...10
T2EUD
T2IN
CPU Clock
CPU Cl ock
CPU Clock
T3IN
T4IN
T3EUD
T4EUD
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
GPT1 Timer T2
GPT1 Timer T3
GPT1 Timer T4
T3OTL
Reload
Capture
U/D
U/D
Reload
Capture
Interrupt
Request
Interrupt
Request
Interrupt
Request
T3OUT
U/D
10 - GENERAL PURPOSE TIMER UNIT ST10F269
54/184
Reso lution a nd Period (TQ FP144 devices) list the
timer inpu t frequencie s, resolution and pe rio ds for
each pr e-scaler option at 40MHz (or 32MHz) CPU
clock. This al so applies t o the Gate d Timer Mo de
of T6 and to the auxiliary timer T5 in Timer and
Gated Timer Mode.
Table 14 : GPT2 Timer Input Frequencies , Resoluti on and Period (PQFP144 devices)
Table 15 : GPT 2 Timer Input Frequencies, Resolution and Pe rio d (TQFP144 devices)
fCPU = 40MHz Timer Input Selection T5I / T6I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 4 8 16 32 64 128 256 512
Input Freq 10MHz 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz
Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs
Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms
fCPU = 32MHz Timer Input Selection T5I / T6I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 4 8 16 32 64 128 256 512
Input Freq 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz
Resolution 125ns 250ns 500ns 1µs2µs4µs8µs16µs
Period maximum 8.19ms 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s
ST10F269 10 - G ENERAL PURPOSE TIMER UNIT
55/184
Fi gure 16 : Block Diagram of GPT2
2n n=2...9
2n n=2...9
T5EUD
T5IN
CPU Clock
CPU Clock
T6IN
T6EUD
T5
Mode
Control
T6
Mode
Control
GPT2 Timer T5
GPT2 Ti mer T6
U/D
Interrupt
Request
U/D
GPT2 CAPREL
T60TL
Toggle FF
T6OUT
CAPIN
Reload Interrupt
Request
to CAPCOM
Timers
Capture
Clear
Interrupt
Request
11 - PWM MODULE ST10F269
56/184
11 - PWM MOD U LE
The pulse width mo dulation module can generate
up to four PWM output si gnals using edge-al igned
or centre-aligned PWM. In addition, the PWM
module can generate PWM burst signals and
single shot outputs. Table 16 and Table 17 show
the PWM frequencies for diff erent resolutions. The
level of the output signals is selectable and the
PWM module can gener ate interrupt requests.
Table 16 : PWM U nit Frequenc ie s and Resolution at 40MHz CPU Clock (P QF P 144 devices)
Table 17 : PWM U nit Frequenc ie s and Resolution at 32MHz CPU Clock (TQFP1 44 dev i ces)
Fi gure 17 : Block Diagram of PWM Module
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 156.25kHz 39.1kHz 9.77kHz 2.44Hz 610Hz
CPU Clock/64 1.6µs 2.44Hz 610Hz 152.6Hz 38.15Hz 9.54Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz
CPU Clock/64 1.6µs 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz
PPx Period Register
Comparator
PTx
16-bit Up/Down Counter
Shadow Register
PWx Pulse Width Register
Input
Run
Control
Clock 1
Clock 2
Comparator
*
*
*
Up/Down/
Clear Control
Match
Output Control
Match
Write Control
*User readable / writeable register
Enable POUTx
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 31.25ns 125KHz 31.25KHz 7.81KHz 1.953KHz 976.6Hz
CPU Clock/64 2.00 µs 1.953KHz 488.3Hz 122.1Hz 30.52Hz 7.63Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 31.25ns 62.5KHz 15.62KHz 3.90KHz 976.6Hz 244.1Hz
CPU Clock/64 2.00 µs 976.6Hz 244.1Hz 61Hz 15.26Hz 3.81Hz
ST10F269 12 - PARALLEL PORTS
57/184
12 - PARALL EL PORTS
12.1 - Introduction
The S T10F269 M CU provides up to 111 I/O lines
with programmable features. These capabilities
bring very flexible adaptation of this MCU to wi de
range of applications.
ST10F269 has 9 groups of I/O lines gathered as
following:
– P ort 0 i s a 2 time 8-bit port named P0L (Low as
less significant Byte) and P0H (high as most sig-
nificant Byte)
– Port 1 is a 2 time 8-bit port named P 1L and P1H
– P ort 2 is a 1 6-bit port
– Port 3 is a 15-bit port (P3.14 line is not imple-
mented)
– P ort 4 is a 8-bit port
– Port 5 is a 16-bit port input only
– P ort 6, Port 7 and Port 8 are 8-bit port
These ports may be used as general purpose
bidirectional input or output, software controlled
with dedicated registers.
For example the output drivers of six of the por ts
(2, 3, 4, 6, 7, 8) can be configured (bit-wise) for
push-pull or open drain operation using ODPx
registers.
In add ition, the sin k and th e sourc e capabil ity a nd
the rise / fall time of the transition of the signal of
some of the push-pull buffers can be programmed
to fit the driving requirements of the application
and t o m ini mize EM I. T his feature is i mp lem ented
on Port 0, 1, 2, 3, 4, 6, 7 and 8 with the control
registers POCONx. The output driv ers capabilities
of ALE, RD, WR control lines are programmable
with the dedicated bits of POCON20 control
register.
The input threshold levels are programmable
(TTL/CMOS) for 5 ports (2, 3, 4, 7, 8). The logic
level of a pin is clocked into the input latch once
per state time, regardless whether the port is
configured for input or output. The threshold is
selected with the PICON register control bits.
A write operation to a port pin configured as an
input causes the value to be written into the port
output latch, while a read operation returns the
latched state of the pin itself. A read-modify-write
operation reads the value of the pin, modifies it,
and writes it back to t he out put latch.
Writing to a pin configured as an output
(DPx. y=‘1’) ca uses the output latch and the pin t o
have the written value, since the output buffer is
enabled. Reading this pin retur ns the value of the
output latch. A read-modify-write operation reads
the value of the output latch, modifies it, and
writes it back to the output latch, thus also
modi fying the level at th e pin.
I/O lines support an alternate function which is
detailed in the following description of each port.
12 - PARALLEL PORTS ST10F269
58/184
Fi gure 18 : SFRs and Pins Ass ociated with t he Parallel Ports
Data I nput / O utput R egister
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YP0L
----- - - - YYYYYYYYP0H
----- - - - YYYYYYYYP1L
----- - - - YYYYYYYYP1H
YYYYY YYYYYYYYYYYP2
Y-YYY YYYYYYYYYYYP3
----- - - - YYYYYYYYP4
YYYYY YYYYYYYYYYYP5
----- - - - YYYYYYYYP6
----- - - - YYYYYYYYP7
----- - - - YYYYYYYYP8
Direction Control Registers
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YDP0L
----- - - - YYYYYYYYDP0H
----- - - - YYYYYYYYDP1L
----- - - - YYYYYYYYDP1H
YYYYY YYYYYYYYYYYDP2
Y-YYY YYYYYYYYYYYDP3
----- - - - YYYYYYYYDP4
----- - - -YYYYYYYYDP6
----- - - - YYYYYYYYDP7
----- - - -YYYYYYYYDP8
Threshold / Open Drain Control
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
-
4
Y
3
Y
2
Y
1
Y
0
YPICON
YYYYY YYYYYYYYYYYODP2
--Y-Y YYYYYYYYYYYODP3
--------YY------ODP4
----- - - -YYYYYYYYODP6
----- - - -YYYYYYYYODP7
----- - - -YYYYYYYYODP8
Output D river Control Register
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YPOCON0L
----- - - - YYYYYYYYPOCON0H
----- - - - YYYYYYYYPOCON1L
----- - - - YYYYYYYYPOCON1H
YYYYY YYYYYYYYYYYPOCON2
Y-YYY YYYYYYYYYYYPOCON3
----- - - - YYYYYYYYPOCON4
----- - - -YYYYYYYYPOCON6
----- - - - YYYYYYYYPOCON7
----- - - -YYYYYYYYPOCON8
----- - - -YYYYYYYYPOCON20 *
* RD, WR, ALE lines only
Y : Bit has an I/O function
- : Bit has no I/O dedicated function or is not im p lem en ted
Regis t er belongs to E S F R are aE:
YYYYY YYYYYYYYYYYP5DIDIS
PICON: P2LIN P2HIN
P3LIN P3H IN
P4LIN
P6 LI N (to b e im plemented)
P7LIN
P8LIN
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
ST10F269 12 - PARALLEL PORTS
59/184
12.2 - I/O’s S pecial Features
12.2. 1 - Open D rain M ode
Some of the I/O ports of ST10F269 support the
open drain capability. This programmable feature
may be used with an external pull-up resistor, in
order to get an AND wired logi cal function.
This feature is implemented for ports P2, P3, P4,
P6, P7 and P8 (see respective sections), and is
controlled through the respective Open Drain
Control Registers ODPx. These registers allow
the individual bit-wise selection of the open drain
mode for each port line. If the respective control
bit ODPx.y is ‘0’ (default after reset), the output
dri ver is in the push-pull mode. If ODPx .y is ‘1’, the
open drain configuration is selected. Note that all
ODPx registers are located in the ESFR space
(See Figure 19).
12.2 .2 - Input Th res h old Con trol
The standard inputs of the ST10F269 determine
the status of input signals according to TTL levels.
In order to accept and recognize noisy signals,
CMOS-like input thresholds can be selected
instea d of the stan dard TTL thresho lds for all pins
of Por t 2, Port 3, Port 4, Port 7 and Po r t 8. These
special thresholds are defined above the TTL
thresholds and feature a defined hysteresis to
prevent the inputs from toggling while the
respec tive i nput signal lev el is near the threshol ds.
The Por t Input Control register PICON is used to
select these thresholds for each Byte of the
indicated p or ts, this means the 8-bit por ts P 4, P7
and P 8 are controlled by one bit each while ports
P2 and P3 are controlled by two bits each.
All opti ons for individual di rection and outpu t mode
control are available for each pin, independent of
the selected input threshold. The input hysteresis
provides stable inputs from noisy or slowly
changing external signals (See Figure 20).
PICON (F1C4h / E2h) ESFR Reset Value: --00h
1514131211109876543210
--------P8LINP7LIN-P4LINP3HINP3LINP2HINP2LIN
RW RW RW RW RW RW RW
Bit Function
PxLIN Port x Low Byte Input Level Selection
0: Pins Px.7...Px.0 switch on standard TTL input levels
1: Pins Px.7...Px.0 switch on special threshold input levels
PxHIN Port x High Byte Input Level Selection
0: Pins Px.15...Px.8 switch on standard TTL input levels
1: Pins Px.15...Px.8 switch on special threshold input levels
Fi gure 19 : Output Drivers in Push-pull Mode and in Open Drain Mode
Pin
Q
Push-Pull Output Driver
Q
Open Drain Output Driver
External
Pullup
Pin
12 - PARALLEL PORTS ST10F269
60/184
12.2.3 - Output Driver Control
The port output control registers POCONx allow
to sele ct the port output driver characteristics of a
port. The aim of these selections is to adapt the
output drivers to the application’s requirements,
and to improve the EMI behaviour of the device.
Two chara cteristics may be sel e cte d :
Edge characteristic defines the rise/fall time for
the respective output. Slow edges reduce the
peak currents that are sinked/sourced when
changing the voltage level of an external
capacit iv e load. For a b us interf ace or pins that are
changing at frequency higher than 1MHz,
however, fast edges may still be required.
Driver characteristic defines either the general
driving capability of the respective driver, or if the
driver strength is reduced after the target output
level has been reached or not. Reducing the
driver strength increases the output’s internal
resistance, which attenuates noise that is
imported via the output line. For driving LEDs or
power transistors, however, a stable high output
current may still be required as descr ibed below.
This rise / fall time of 4 I/O pads (a nibble) is
selected using 2-bit named PNxEC. That means
Port Nibbl e (x = nib ble number, it could be 3 as for
Port 2.15 to 2.12) Edge Characteristic.
The sink / source capability of the same 4 I/O
pads is selected using 2-bit named PNxDC. T hat
means Port Nibble (x = nibble number) Drive
Characteris tic (See Table 18).
PO CONx (F0yyh / zzh) for 8 -bit Ports ESFR Reset Value: --00h
PO CONx (F0yyh / zzh) for 1 6-bit Ports ESFR Reset Value: 0000h
Note: In case of reading an 8 bit P0CONX regist er, high By te (bit 15 ..8) is read as 00h
Fi gure 20 : Hys teres is for Spe cial Input Thresholds
Input level
Bit state
Hysteresis
1514131211109876543210
--------PN1DC PN1EC PN0DC PN0EC
RW RW RW RW
1514131211109876543210
PN3DC PN3EC PN2DC PN2EC PN1DC PN1EC PN0DC PN0EC
RW RW RW RW RW RW RW RW
Bit Function
PNxEC Port Nibble x Edge Characteri stic (rise/fall time)
00: Fast edge mode , rise/fall times depend on the size of the driver.
01: Slow edg e mode, rise/fall times ~60 ns
10: Reserved
11: Reserved
PNxDC Por t Nibble x Driver Characteri stic (output curren t)
00: High Current mode:
Dri ver always operates with maximu m strength.
01: Dynamic Current mode:
Dri ver strength is reduced aft er the target le vel has been reached.
10: Low Current m ode:
Dri ver always operates with reduced strength.
11: Reserved
ST10F269 12 - PARALLEL PORTS
61/184
The table lists the defined PO CON registers and the allocation of control bit-fields and por t pins.
Dedicated P ins Output Con trol
Programmable pad drivers also are supported f or the dedicat ed pins ALE, RD and WR. For these pads, a
spe cial POCON20 register is provided.
PO CON20 (F0A Ah / 55h) ESFR Reset Value: --00h
Table 18 : Port Contro l Register Allocation
Control
Register Physical
Address 8-bit
Address Controlled Port Nibble
3210
POCON0L F080h 40h P0L.7...4 P0L.3...0
POCON0H F082h 41h P0H.7...4 P0H.3...0
POCON1L F084h 42h P1L.7...4 P1L.3...0
POCON1H F086h 43h P1H.7...4 P1H.3...0
POCON2 F088h 44h P2.15...12 P2.11...8 P2.7...4 P2.3...0
POCON3 F08Ah 45h P3.15, 3.13, 3.12 P3.11...8 P3.7...4 P3.3...0
POCON4 F08Ch 46h P4.7...4 P4.3...0
POCON6 F08Eh 47h P6.7...4 P6.3...0
POCON7 F090h 48h P7.7...4 P7.3...0
POCON8 F092h 49h P8.7...4 P8.3...0
1514131211109876543210
--------PN1DC PN1EC PN0DC PN0EC
RW RW RW RW
PN0EC RD, WR Edge Characteristic (rise/fall time)
00: Fast edge mode , rise/fall times depend on the size of the driver.
01: Slow edg e mode, rise/fall times ~60 ns
10: Reserved
11: Reserved
PN0DC RD, WR Driver Charac teris tic (output current)
00: High Current mode:
Dri ver always operates with maximu m strength.
01: Dynamic Current mode:
Dri ver strength is reduced aft er the target le vel has been reached.
10: Low Current m ode:
Dri ver always operates with reduced strength.
11: Reserved
PN1EC ALE Edge Characteristic (rise/fall time)
00: Fast edge mode , rise/fall times depend on the size of the driver.
01: Slow edg e mode, rise/fall times ~60 ns
10: Reserved
11: Reserved
PN1DC AL E Driver Characteristic (output current)
00: High Current mode:
Dri ver always operates with maximu m strength.
01: Dynamic Current mode:
Dri ver strength is reduced aft er the target le vel has been reached.
10: Low Current m ode:
Dri ver always operates with reduced strength.
11: Reserved
12 - PARALLEL PORTS ST10F269
62/184
12.2.4 - Alternate Port Functions
Each por t line h as one associated programmable
alternate input or output function.
– PORT0 and PORT1 may be used as address
and data lines when accessing externa l memory.
– Port 2, Port 7 and Port 8 are associated with the
capture inputs or compare outputs of the CAP-
COM units and/or with the outputs of the PWM
module.
Por t 2 is also used for fast exter nal interru pt in-
puts and for timer 7 input.
– P ort 3 includes the alternate functions of timers,
serial interfaces, th e optional bu s control signal
BHE and the system clock output (CLKOUT).
– Port 4 outputs the additional segment address
bit A16 to A23 in systems where segmentation
is enabled to access more than 64K Bytes of
memory.
– Port 5 is used as analog input channels of the
A/D converter or as timer control signals.
– Port 6 provides optional bus arbitration signals
(BREQ, HLDA, H O L D) and chip select signals.
If an alternate output function of a pin is to be
used, the direction of this pin must be
programmed for output (DPx.y=‘1’), except for
some si gnals that are used directly after reset and
are configured automatically. Otherwise the pin
remains in the high-impedance state and is not
effected by the alternate output function. The
respec tive port latc h should hold a ‘1’, because its
output is ANDed with the alternate output data
(except for PWM out put signals).
If an alter nate input function of a pin is used, the
direction of the pin must be programm ed for input
(DPx.y= ‘0’) if an extern al device is dr iving the pin.
The input direction is the default after reset. If no
external device is connected to the pin, however,
one can also set the di rection for this pin to out put .
In this case, the pin reflects the state of the port
output latch. Thus, the alternate input function
reads the value stored in the port output latch.
This can be used for testing purposes to allow a
software trigger of an alternate input function by
wr iting to the port output latch.
On most of the por t lines, th e application software
must set the proper direction when using an
alternate input or output function of a pin. This is
done by setting or clearing the direction control bit
DPx.y of the pin before enabling the alternate
function. The re are port lines, however, where t he
direction of the port line is swi tc hed automat i cally.
For instance, in the multiplexed external bus
mode s of P ORT0, the direction must be switched
several times for an instruction fetch in order to
output the addresses and to input the data.
Obviously, this cannot be done through
instructions. In these cases, the direction of the
port line is switched automatically by hardware if
the alter nat e function of such a pin is enabled.
To determine the appropriate level of the port
output latches check how the alternate data
output is combined with the respective port latch
output.
There is one basic structure for all port lines
supporting only one alternate input function. Port
lines with only one alternate output function,
however, have different structures. It has to be
adapted to support the normal and the alternate
funct ion features.
All por t lines that are not used for these alter nate
functions may be used as general purpose I/O
lines. When using port pins for general purpose
outpu t, the initial output value sh ould be wr itten to
the port latch prior to enabling the output drivers,
in order to avoid undesired transitions on the
output pins. This applies to single pins as well as
to pin groups (see examples below).
SINGLE_BIT: BSET P4.7 ; Initial output level is "high"
BSET DP4.7 ; Switch on the output driver
BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high"
BFLDH DP4, #24H, #24H ; Switch on the output drivers
Note: When using se veral BSET pair s to control more pins of one port, these pairs must be separat ed by
instructions, which do not apply to the respective port (See Chapter : Central Processing Unit
(CPU) on page 35).
ST10F269 12 - PARALLEL PORTS
63/184
12.3 - PORT0
The two 8-bit ports P0H and P0L represent the
higher and lower part of PORT0, respectively.
Both halves of PORT0 can be written (via a PEC
transfer) without effecting the other half.
If this port is used for general purpose I/O, the
direction of each line can be configured via the
corresponding direction registers DP0H and
DP0L.
P0L (FF00h / 80h) SF R Reset Value: --00h
P0H (FF02h / 81h) SFR Reset Value: --00h
DP0L (F100h / 80h) ESFR Reset Value: --00h
DP0H (F102h / 81h) ESFR Reset Value: --00h
1514131211109876543210
--------P0L.7P0L.6P0L.5P0L.4P0L.3P0L.2P0L.1P0L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------P0H.7P0H.6P0H.5P0H.4P0H.3P0H.2P0H.1P0H.0
RW RW RW RW RW RW RW RW
P0X.y Port Data Register P 0H or P0L Bit y
1514131211109876543210
--------DP0L.7DP0L.6DP0L.5DP0L.4DP0L.3DP0L.2DP0L.1DP0L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------DP0H.7DP0H.6DP0H.5DP0H.4DP0H.3DP0H.2DP0H.1DP0H.0
RW RW RW RW RW RW RW RW
DP0X.y Port Direction Register DP0H o r DP0L Bit y
DP0X.y = 0: Port line P0X.y is an input (high-impedance)
DP0X.y = 1: Port line P0X.y is an output
12 - PARALLEL PORTS ST10F269
64/184
12.3.1 - Alternate Functions of PORT0
W hen an external bus is enabled, P ORT0 is us ed
as data bus or address/data bus.
Note that a n extern al 8-bit demultiplexed bus only
use s P0L , wh ile P0H is free for I/O (provided t hat
no other bus mode is enabled).
PO RT 0 is also used t o select the s ystem star t-up
configuration. During reset, PORT0 is configured
to input, and each line is held high through an
internal pull-up device.
Each line can now be individually pulled to a low
level (see Section 21.3 -: DC Characteristics)
through an external pull-down device. A default
configuration is selected when the respective
PORT0 lines are at a high level. Through pulling
individual lines to a low level, this default can be
changed according to the needs of the
applicat ions.
The in terna l pull-up devices are de signed in suc h
wa y that an e xt ernal pull-down resistors (see Data
Sheet specification) can be used to apply a
correct low le v el.
These external pull-down resistors can remain
con nected to the PORT0 p ins also d uring nor mal
operation, however, care has to be taken in order
to not disturb the normal function of PORT0 (this
might be the case, for example, if the external
resistor value is too low).
With the end of reset, the selected bus
configuration will be written to the BUSCON0
register.
The configuration of the high byte of PORT0, will
be copied into the special register RP0H. This
read-only register holds the selection for the
number of chip selects and segment addresses.
Software can read this register in order to react
according to the selected configuration, if
required.
When the reset is terminated, the inter nal pull-up
devices are switched off, and PORT0 will be
switched to the appropriate operating mode.
During external accesses in multiplexed bus
modes PORT0 first outputs the 16-bit
intra-segment address as an alternate output
function. PORT0 is then switched to
high-impeda nce i nput mode to read the incoming
instruction or data. In 8-bit data bus mode, two
memory cycles are required for word accesses,
the first for the low Byte and the second for the
high Byte of the Word .
During write cycles PORT0 outputs the data Byte
or Word after outputting the address. During
external accesses in demultiplexed bus modes
PORT0 reads the incoming instruction or data
Word or outputs the data Byte or Word.
Fi gure 21 : PORT0 I/O and Alternate Functi ons
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
PORT0
P0H
P0L
Alternate Function a) b) c) d)
General Purpose
Input/Output 8-bit
Demultipl exed Bu s 16-bit
Demultiplexed Bus 8-bit
Multipl exed Bu s 16-bit
Multipl exed Bus
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ST10F269 12 - PARALLEL PORTS
65/184
When an external bus mode is enabled, the
direction of the port pin and the loading of data
into the port output latch are controlled by the bus
controller hardware.
The input of the port output Buffer i s disconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a m ulti ple xer.
The alt ernate data can be t he 16-bi t intra-segment
address or the 8/16-bit data information. The
incoming data on PORT0 is read on the line
“Alternate Data Input”. While an external bus
mode is enabled, the user software should not
write to the port output latch, otherwise
unpredi ctable results ma y oc cu r.
When the external bus modes are disabled, the
cont ents of the direct ion register last writt en b y the
use r becomes active.
The Figure 22 shows the structure of a PORT0
pin.
Fi gure 22 : Block Diagram of a PORT0 Pin
Direction
Latch
Write DP0H.y / DP0L.y
Read DP0H.y / DP0L.y
Port Output
Latch
Write P0H.y / P0L.y
Read P0H.y / P0L.y
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
Alternate
Direction
Input
Latch
Clock
P0H.y
P0L.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
Port Data
Output
12 - PARALLEL PORTS ST10F269
66/184
12.4 - PORT1
The two 8-bit ports P 1H and P1L repr es ent t he higher and lower part of POR T1, respect ively. Both halves
of PORT1 can be w ritten (via a PEC transfe r) without effecting the other half.
If this port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction registers DP1H and DP1L.
P1L (FF04h / 82h) SF R Reset Value: --00h
P1H (FF06h / 83h) SFR Reset Value: --00h
DP1L (F104h / 82h) ESFR Res et Value: --00h
DP1H (F106h / 83h) ESFR Reset Value: --00h
12.4.1 - Alternate Functions of PORT1
W hen a demultiplexed external bus is enabled, PORT1 is used as address bus.
Note: Dem ultiplexed bus m odes us e PORT1 as a 16-bit port. Otherwise all 16 po rt lines can be used for
general purpose I/O.
The upper 4 pins of PORT1 (P1H.7...P1H.4) are used as capture input lines (CC27IO...CC24IO).
Durin g externa l accesses in demultiplexed bus modes PORT1 out puts the 16-bi t intra-segment address
as an alter nat e outp ut function.
Durin g ext ernal accesses in multiplexed bus m odes, when no B USCON register selects a demultiplexed
bus mode, PORT1 is not used and is available fo r gene ral purp os e I/O.
1514131211109876543210
--------P1L.7P1L.6P1L.5P1L4P1L.3P1L.2P1L.1P1L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------P1H.7P1H.6P1H.5P1H.4P1H.3P1H.2P1H.1P1H.0
RW RW RW RW RW RW RW RW
P1X.y Port Data Register P 1H or P1L Bit y
1514131211109876543210
- - - - - - - - DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
- - - - - - - - DP1H.7 DP1H.6 DP1H.5 DP1H.4 DP1H.3 DP1H.2 DP1H.1 DP1H.0
RW RW RW RW RW RW RW RW
DP1X.y Port Direc tion Register DP1H or DP1L Bit y
DP1X.y = 0: Port line P1X.y i s an input (high-impedance)
DP1X.y = 1: Port line P1X.y i s an output
ST10F269 12 - PARALLEL PORTS
67/184
Fi gure 23 : PORT1 I/O and Alternate Functi ons
When an external bus mode is enabled, the
direction of the port pin and the loading of data
into the port output latch are controlled by the bus
controller hardware.
The input of the por t Buffer latch is disconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer.
The alternate data is the 16-bit intra-segment
address. While an external bu s mode is enabled,
the user software should not write to the port
output latch, otherwise unpredictable results may
occur . When the e xternal bus modes are disabled,
the contents of the direction register last writt en by
the user become s active.
The Figure 24 shows the structure of a PORT1
pin.
PORT1
P1H
P1L
Alternate Function a)
General Purpos e I nput/Out put 8/ 16-bit Demultiplexed Bus
b)
CAPCOM2 Capture Inputs only
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CC27IO
CC26IO
CC25IO
CC24IO
Fi gure 24 : Block Diagram of a PORT1 Pin
Direction
Latch
Write DP1H.y / DP1L.y
Read DP1H.y / DP1L.y
Port Output
Latch
Write P1H.y / P1L.y
Read P1H.y / P1L.y
Internal Bu s
MUX
0
1
MUX
0
1
MUX
0
1
“1”
Input
Latch
Clock
P1H.y
P1L.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
Port Data
Output
Alternate
Data
Output
12 - PARALLEL PORTS ST10F269
68/184
12.5 - Port 2
If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction regi ster DP2. Each por t line can be switched into pus h/pull or op en drain mode
via the open drain control register ODP2.
P2 (FFC0h / E0h) SFR Reset Value: 0000h
DP2 (FFC2h / E1h) SFR Reset Value: 0000h
ODP2 (F1C2h / E1h) ESFR Reset Value: 0000h
12.5.1 - Alternate Functions of Port 2
All Port 2 lines (P2.15...P2.0) serve as capture
inputs or compare outputs (CC15IO...CC0IO) for
the CAPC OM 1 unit.
W hen a Port 2 line is used as a capture input, the
state of the input latch, which represents the state
of the port pin, is directed to the CAPCOM unit via
the line “Alternate Pin Data Input”. If an external
capture trigger signal is used, the direction of the
respec tive pin must be set to input.
If the direction is set t o output, the stat e of the port
output latch will be read since the pin represents
the state of the output latch.
This can be used to trigger a capture event
through software by setting or clearing the port
latch. Note that in the output configuration, no
external device may drive the pin, otherwise
conflicts would occu r.
When a Port 2 line is used as a compare output
(compare m odes 1 and 3), the compa re event (or
the timer overflow in compare mode 3) directly
effects the por t output latch. In compare m ode 1,
when a valid compare match occurs, the state of
the port output latch is read by the CAPCOM
cont rol hardware via the line “Alternate Latch Data
Input”, inverted, and written back to the latch via
the li ne “Alternate Data Output”.
The port output latch is clocked by the signal
“Compare Trigger” which is generated by the
CAPCOM unit. In compare mode 3, when a match
occurs, the value '1' is written to the port output
latch via the line “Alternate Data Output”. When
an overflow of the corresponding timer occurs, a
'0' is written to the port output latch. In both cases,
1514131211109876543210
P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
P2.y Port Data Register P2 Bit y
1514131211109876543210
DP2
.15 DP2
.14 DP2
.13 DP2
.12 DP2
.11 DP2
.10 DP2
.9 DP2
.8 DP2
.7 DP2
.6 DP2
.5 DP2
.4 DP2
.3 DP2
.2 DP2
.1 DP2
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DP2.y Port Direction Register DP2 Bit y
DP2.y = 0: Port line P2.y is an input (h igh-impeda nce )
DP2.y = 1: Port line P2.y is an output
1514131211109876543210
ODP2
.15 ODP2
.14 ODP2
.13 ODP2
.12 ODP2
.11 ODP2
.10 ODP2
.9 ODP2
.8 ODP2
.7 ODP2
.6 ODP2
.5 ODP2
.4 ODP2
.3 ODP2
.2 ODP2
.1 ODP2
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ODP2.y Port 2 Open Drain Control Register Bit y
ODP 2.y = 0: Port line P2.y out put driv er i n push/pull mode
ODP 2.y = 1: Port line P2.y out put driv er i n open drai n mode
ST10F269 12 - PARALLEL PORTS
69/184
the out put latch is clocked by t he signal “Compare
Tri gger”.
The di rection of the pi n should be se t to output by
the user, otherwise the pin will be in the
h igh-im peda nc e state and w ill not reflec t the state
of the output latch.
As can be seen from the port structure in
Figure 26, the user software always has free
access to the port pin even when it is used as a
compare output. This is useful for setting up the
initial level of the pin when using compare mode 1
or the double-register mode. In these modes,
unlike in compare mode 3, the pin is not set to a
specific value when a compare match occurs, but
is toggled instead.
When the user wants to wri te to the port pin at the
same time a compare trigger tries to clock the
output latch, the write operation of the user
software has priority. Each time a CPU write
access to the port output latch occurs, the input
multiplexer of the port output latch is switched to
the line connected to the internal bus. The port
output latch will receive the v alue f rom the internal
bus and the hardware triggered change will be
lost.
As all other capture inputs, the capture input
funct ion of pins P2.15 ...P2.0 can a lso be used as
external interrupt inputs (200ns sample rate at
40MHz CPU clock on PQFP144 devices and
250ns sample rate at 32MHz CPU clock on
T Q FP14 4 d evices).
The upper eight Port 2 lines (P2.15...P2.8) also
can serve as Fast External Interrupt inputs from
EX0I N to EX7IN (Fast ex ternal interrupt sampli ng
rate is 25ns at 40MHz CPU cl ock and 31.25n s at
32MHz CPU clock).
P2.15 in addition serves as input for CAPCOM2
timer T7 (T7IN). The Table 19 summarizes the
alternate functions of Port 2.
Table 19 : Alternate Functions of Port 2
Port 2 Pin Alternate Function a) Alternate Function b) Alternate Function c)
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
CC0IO
CC1IO
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
CC9IO
CC10IO
CC11IO
CC12IO
CC13IO
CC14IO
CC15IO
-
-
-
-
-
-
-
-
EX0IN Fast External Interrupt 0 Input
EX1IN Fast External Interrupt 1 Input
EX2IN Fast External Interrupt 2 Input
EX3IN Fast External Interrupt 3 Input
EX4IN Fast External Interrupt 4 Input
EX5IN Fast External Interrupt 5 Input
EX6IN Fast External Interrupt 6 Input
EX7IN Fast External Interrupt 7 Input
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T7IN T7 External Count Input
12 - PARALLEL PORTS ST10F269
70/184
Fi gure 25 : Port 2 I/O and Alternate Functions
Port 2
Alternate Function a)
Genera l Purpos e
Input / Output CAPCOM1
Capture Input / Compare Output
b)
Fast Exte rnal
Interrupt Input
c)
CAPCOM2
Timer T7 Input
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
CC15IO
CC14IO
CC13IO
CC12IO
CC11IO
CC10IO
CC9IO
CC8IO
CC7IO
CC6IO
CC5IO
CC4IO
CC3IO
CC2IO
CC1IO
CC0IO
EX7IN
EX6IN
EX5IN
EX4IN
EX3IN
EX2IN
EX1IN
EX0IN
T7IN
ST10F269 12 - PARALLEL PORTS
71/184
The pins of Port 2 combin e internal bus data with alternate data output before the port latch input.
12.6 - Port 3
If this 15-bit por t is used for general purpose I/O,
the direct ion of each line can be confi gured by the
corresponding direction register DP3. Most port
lines can be switch ed into p us h-pull or open drain
mode by the open drain control register ODP2
Fi gure 26 : Block Diagram of a Port 2 Pin
Open Drain
Latch
Write ODP2.y
Read O D P2.y
Direction
Latch
Write DP2.y
Read D P 2.y
Internal Bus
MUX
0
1
Alterna te Data Input
Input
Latch
Clock
P2.y
CCyIO
Output
Buffer
x = 7...0
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Port P2.y
Compare Trigger
Read P 2.y
Fast External Interrupt Input
EXxIN
y = 15...0
12 - PARALLEL PORTS ST10F269
72/184
(pins P3. 15, P3.14 and P3.12 do not s upport open
drain mode). Due to pin limitations register bit P3.14 is not
conne c ted to an output p in.
P3 (FFC4h / E2h) SFR Reset Value: 0000h
DP3 (FFC6h / E3h) SFR Reset Value: 0000h
ODP3 (F1C6h / E3h) ESFR Reset Value: 0000h
1514131211109876543210
P3.15 - P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
P3.y Port Data Reg ister P3 Bit y
1514131211109876543210
DP3
.15 -DP3
.13 DP3
.12 DP3
.11 DP3
.10 DP3
.9 DP3
.8 DP3
.7 DP3
.6 DP3
.5 DP3
.4 DP3
.3 DP3
.2 DP3
.1 DP3
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DP3.y Port Direct ion Register DP3 Bit y
DP3.y = 0: Port line P3.y is an input (high-impe danc e)
DP3.y = 1: Port line P3.y is an output
1514131211109876543210
--ODP3
.13 -ODP3
.11 ODP3
.10 ODP3
.9 ODP3
.8 ODP3
.7 ODP3
.6 ODP3
.5 ODP3
.4 ODP3
.3 ODP3
.2 ODP3
.1 ODP3
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ODP3.y P ort 3 Op en Drain Control Register Bit y
ODP3.y = 0: Port line P3.y output driver in push-pull mode
ODP3.y = 1: Port line P3.y output driver in open drain mod e
ST10F269 12 - PARALLEL PORTS
73/184
12.6.1 - Alternate Functions of Port 3
The pins of Port 3 serve for various functions which include external timer control lines, the two serial
interfaces and the control lines BHE/WRH and CLKOUT.
The structure of the Por t 3 pins depen ds on their
alternate function (see figures Figure 28 and
Figure 29). When the on-chip peripheral
associated with a Port 3 pin is configured to use
the alternate input function, it reads the input
latch, which represents the state of the pin, via the
line labeled “Alternate Data Input ”. P ort 3 pins with
alternate input functions are: T0IN, T2IN, T3IN,
T4IN, T3EUD and CAPIN.
When the on-chip peripheral associated with a
Port 3 pin is configured to use the alternate output
function, i ts “Alternat e Data Out put” line is ANDed
with the port output latch line. When using these
alternate functions, the user mu st set the direction
of the port line to output (DP3.y=1) and must set
the port output latch (P3.y=1). Otherwise the pin is
in its high-impedance state (when configured as
input) or the pin is stuck at '0' (when the port
output l atch is cleared). When the alternat e output
functions are not used, the “Alternate Data
Out put” line is in its inactive state, which is a high
level ( '1') .
Port 3 pins with alternate output functions are:
T6OUT, T3OUT, TxD0, BH E and CLKOUT.
Table 20 : Port 3 Alter nat ive Functions
Port 3 Pin Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
T0IN CAPCOM1 Timer 0 Count Input
T6OUT Timer 6 Toggle Output
CAPIN GPT2 Capture Input
T3OUT Timer 3 Toggle Output
T3EUD Timer 3 External Up/Down Input
T4IN Timer 4 Count Input
T3IN Timer 3 Count Input
T2IN Timer 2 Count Input
MRST SSC Master Receive / Slave Transmit
MTSR SSC Master Transmit / Slave Receive
TxD0 ASC0 Transmit Data Output
RxD0 ASC0 Receive Data Input (Output in synchronous mode)
BHE/WRH Byte High Enable / Write High Output
SCLK SSC Shift Clock Input/Output
--- No pin assigned
CLKOUT System Clock Output
Fi gure 27 : Port 3 I/O and Alternate Functions
Port 3
No Pin
Alternate Function a) b)
Genera l Purpos e Input/Outp ut
P3.15
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
CLKOUT
SCLK
BHE
RxD0
TxD0
MTSR
MRST
T2IN
T3IN
T4IN
T3EUD
T3OUT
CAPIN
T6OUT
T0IN
WRH
12 - PARALLEL PORTS ST10F269
74/184
When the on-chip peripheral associated with
a Port 3 pi n is configured to use both the alternate
input and output function, the descriptions above
apply to the respective current operating mode.
The direct ion must be set accordingly. Por t 3 pins
with alternate input/output functions are: MTSR,
MRST, Rx D0 and SCLK.
Note: Enabling the CLKOUT function automati-
cally enables the P3.15 output driver. Set-
ting bit DP3.15=’1’ is n ot required.
Fi gure 28 : Block Diagram of Port 3 Pin with Alternate Input or Alternate Output Function
Open Drain
Latch
Write ODP3.y
Read ODP3.y
Direction
Latch
Write DP3.y
Read DP3.y
Internal Bus
MUX
0
1
Alternate
Data
Input
Input
Latch
Clock
P3.y
Output
Buffer
y = 13, 11...0
Port Output
Latch
Read P3.y
Write DP3.y
&
Alternate
Data Output
Port Data
Output
ST10F269 12 - PARALLEL PORTS
75/184
Pin P3.12 (BHE/WRH) is another pin with an
altern ate out put function, however, i ts structure is
slightly different.
After reset the BHE or WRH function must be
used depending on the system start-up
con figuration. In either of these cases, there is no
possibility to program any port latches before.
Thus, the appropriate alternate function is
select ed automat ically. If BHE/WRH is not used in
the system, this pin can be used for general
purpose I/O by disabling the alternate function
(BYTDIS = ‘1’ / WRCFG=’0’).
Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit
DP3.12=’1’ is not r equired.
During bus hold pin P3.12 is switched back to its standard function and is then controlled by
DP3.12 and P3 .12. Keep DP3.12 = ’0’ in this case to ensure floating in hold mode.
Fi gure 29 : Block Diagr am of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH)
Direction
Latch
Write DP3.x
Read DP3.x
Port Output
Latch
Write P3.x
Read P3.x
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
Clock
P3.12/BHE
P3.15/CLKOUT
Output
Buffer
x = 15, 12
Alternate
Function
Enable
12 - PARALLEL PORTS ST10F269
76/184
12.7 - Port 4
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction register DP4.
P4 (FFC8h / E4h) SFR Reset Value: --00h
DP4 (FFCAh / E5h) SFR Reset Value: --00h
For CAN configuration support (see section 15), Port 4 has an open drain function, controlled with the
ODP 4 register:
ODP4 (F1CA h / E5h) ESFR Reset Value: --00h
Note: Only bit 6 and 7 are implemented, all other bit will be read as “0”.
1514131211109876543210
- - - - - - - - P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
RW RW RW RW RW RW RW RW
P4.y Port Data Reg ister P4 Bit y
1514131211109876543210
--------DP4.7DP4.6DP4.5DP4.4DP4.3DP4.2DP4.1DP4.0
RW RW RW RW RW RW RW RW
DP4.y Port Direct ion Register DP4 Bit y
DP4.y = 0: Port line P4.y is an input (high-impe danc e)
DP4.y = 1: Port line P4.y is an output
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - - ODP4.7 ODP4.6 - - - - - -
RW RW
ODP4.y P ort 4 Op en Drain Control Register Bit y
ODP4.y = 0: Port line P4.y output driver in push/pull mode
ODP4.y = 1: Por t line P 4.y ou tput dri ve r in ope n d rain m ode if P 4.y is not a segmen t
address line output
ST10F269 12 - PARALLEL PORTS
77/184
12.7.1 - Alternate Functions of Port 4
Durin g ext ernal bus cycles that use segmentation
(address space above 64K Bytes) a number of
Port 4 pins m ay out put t he segment address lines.
The number of pins that is used for segment
address output determines the external address
spa ce whi ch is direct ly a ccessible. The ot her p ins
of Por t 4 may be used for general pu rpose I/O. If
seg men t a ddress lin es are sel ec ted, the alt er nat e
function of Port 4 may be necessary to access
external memory directly after reset. For this
reason Port 4 will be switched to this alternate
funct ion autom atically.
The num ber of segment address lines is select ed
via PORT0 during reset. The selected value can
be read from bitfield SALSEL in register RP0H
(read only) in order to check the configuration
during run t i me.
The CAN interfaces use 2 or 4 pins of Port 4 to
interface each CAN Modules to an external CAN
transceiver. In this case the number of possible
seg men t address lines is reduced.
The Table 21 summarizes the alternate functions
of Port 4 depending on the number of selected
segment address lines (coded via bitfield
SALSEL)
Table 21 : Port 4 Alter nat e Functions
Port 4 Standard Function
SALSEL = 01
64K Bytes
Alternate Function
SALSEL = 11
256K Bytes
Alternate Function
SALSEL = 00
1M Byte
Alternate Function
SALSEL = 10
16M Bytes
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
GPIO
GPIO
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment Address A16
Segment Address A17
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment. Address A16
Segment Address A17
Segment Address A18
Segment Address A19
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Segment Addre ss A16
Segment Addre ss A17
Segment Addre ss A18
Segment Addre ss A19
Segment Addre ss A20
Segment Addre ss A21
Segment Addre ss A22
Segment Addre ss A23
Fi gure 30 : Port 4 I/O and Alternate Functions
Port 4
Alternate Function a)
General Purpose
Input / Output
b)
Segment Address
Lines Cans I/O and General Purpose
Input / Output
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
A23
A22
A21
A20
A19
A18
A17
A16
CAN2_TxD
CAN1_TxD
CAN1_RxD
CAN2_RxD
-
-
-
-
ST10F269 12 - PARALLEL PORTS
79/184
Fi gure 32 : Block Diagram of P4.4 and P4.5 Pins
Direction
Latch
Write DP4. x
Read DP4. x
Port Output
Latch
Write P4.x
Read P4.x
Intern a l Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
Clock
P4.x
x = 5, 4
Alternate
Function
Enable 0
1
“0”
MUX
MUX
0
1
“0”
Output
Buffer
&
≤ 1y = 1, 2 (CA N Cha nnel )
z = 2, 1
a = 0, 1
b = 1, 0
CANy.RxD
XPERCON.a
XPERCON.b
(CANyEN)
(CANzEN)
12 - PARALLEL PORTS ST10F269
80/184
Fi gure 33 : Block Diagram of P4.6 and P4.7 Pins
12.8 - Port 5
This 16-bit input port can only read dat a. There is no output latch and no direction register. Data writt en to
P5 will be lost.
P5 (FFA2h / D1h) SFR Reset Value: XXXXh
1514131211109876543210
P5.15 P5.14 P5.13 P5.12 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
RRRRRRRRRRRRRRRR
P5.y Po r t Data Register P5 Bit y (Read only)
MUX
0
1
"0"
Open Drain
Latch
Write ODP4.x
Read ODP4.x
Direction
Latch
Write D P4.x
Read DP4.x
Internal Bus
MUX0
1
Input
Latch
Clock
P4.xOutput
Buffer
Port Output
Latch
Read P4.x
Write P4.x Alternate
Data
Output MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable
MUX
0
1
"1" MUX
MUX
0
1
"0"
MUX
0
1
MUX
≤ 1
CANy.TxD
XPERCON.a
(CANyEN)
XPERCON.b
(CANzEN)
Data output
x = 6, 7
y = 1, 2 (CAN Channel )
z = 2, 1
a = 0, 1
b = 1, 0
ST10F269 12 - PARALLEL PORTS
81/184
12.8.1 - Alternate Functions of Port 5
Each line of Port 5 is also connected to one of the
multiplexer of the Analog/Digital Converter. All
port lines (P5.15...P5.0) can accept analog
signals (AN15...AN0) to be conv erted by the ADC .
No special programming is required for pins that
sha ll be used as anal og inputs. Some pi ns of Por t
5 also serve as external timer control lines for
GP T1 and GP T2 .
The Table 22 summarizes the alternate functions
of Po r t 5.
Table 22 : Port 5 Alter nat e Functions
Port 5 Pin Alternate Function a) Alternate Function b)
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
Analog Input AN0
Analog Input AN1
Analog Input AN2
Analog Input AN3
Analog Input AN4
Analog Input AN5
Analog Input AN6
Analog Input AN7
Analog Input AN8
Analog Input AN9
Analog Input AN10
Analog Input AN11
Analog Input AN12
Analog Input AN13
Analog Input AN14
Analog Input AN15
-
-
-
-
-
-
-
-
-
-
T6EUD Timer 6 external Up/Down Input
T5EUD Timer 5 external Up/Down Input
T6IN Timer 6 Count Input
T5IN Timer 5 Count Input
T4EUD Timer 4 external Up/Down Input
T2EUD Timer 2 external Up/Down Input
Fi gure 34 : Port 5 I/O and Alternate Functions
Port 5
Alternate Function a)
General Purpose Inputs
b)
A/D Converter Input s Timer Inputs
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P5.15
P5.14
P5.13
P5.12
P5.11
P5.10
P5.9
P5.8 AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
T2EUD
T4EUD
T5IN
T6IN
T5EUD
T6EUD
12 - PARALLEL PORTS ST10F269
82/184
Port 5 pins have a special port struct ure (see Figure 35), first because i t is an input only port, and second
because the analog input channels are directly connected to the pins rather than to the input latches .
12.8.2 - Por t 5 Schmitt Trigger Analog Inputs
A Sc hmitt tr igger protection c an be acti vated on eac h pin of Port 5 by setting the dedicated bit of register
P5DIDIS.
P5DIDIS (FFA4h / D2h) SFR Reset Value: 0000h
12.9 - Port 6
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction regi ster DP6. Each por t line can be switched into pus h/pull or op en drain mode
via the open drain control register ODP6.
P6 (FF CCh / E6h) SFR Reset Value: --00h
DP6 (FFCEH / E7 H ) SFR Reset Value: --00h
Fi gure 35 : Block Diagram of a Port 5 Pin
1514131211109876543210
P5DI
DIS.15 P5DI
DIS.14 P5DI
DIS.13 P5DI
DIS.12 P5DI
DIS.11 P5DI
DIS.10 P5DI
DIS.9 P5DI
DIS.8 P5DI
DIS.7 P5DI
DIS.6 P5DI
DIS.5 P5DI
DIS.4 P5DI
DIS.3 P5DI
DIS.2 P5DI
DIS.1 P5DI
DIS.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
P5DIDIS.y Port 5 Digital Disable Register Bit y
P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigg er enabled)
P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled,
necessary for input leak age current reduction)
1514131211109876543210
- - - - - - - - P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
RW RW RW RW RW RW RW RW
P6.y Port Data Register P6 Bit y
1514131211109876543210
--------DP6.7DP6.6DP6.5DP6.4DP6.3DP6.2DP6.1DP6.0
RW RW RW RW RW RW RW RW
Read Port P5.y
Internal Bus
Input
Latch
Clock
P5.y/ANy
Read
Buffer
to Sample + Hold
Circuit
Channel
Select
Analog
Switch
y = 15...0
ST10F269 12 - PARALLEL PORTS
83/184
ODP6 (F1CEH / E7 H) ESFR Reset Value: --00h
12.9.1 - Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control registers
(BUSCON4. ..BUSCON0) can be output on 5 pins of Port 6.
The number of chip select signals is selected via PORT0 during reset. The selected value can be read
from bit-field CSSEL in register RP0 H (read only) in order to check the conf iguration during run time.
The Table 23 summarizes the alternate functions of Port 6 depending on the number of selected chip
selec t lines (coded via bit-field CSSE L).
Fi gure 36 : Port 6 I/O and Alternate Functions
DP6.y Port Di rection Register DP6 Bit y
DP6.y = 0: Port line P6.y is an input (high impedance)
DP6.y = 1: Port line P6.y is an output
1514131211109876543210
--------ODP6.7ODP6.6ODP6.5ODP6.4ODP6.3ODP6.2ODP6.1ODP6.0
RW RW RW RW RW RW RW RW
ODP6.y P ort 6 Op en Drain Control Register Bit y
ODP6.y = 0: Port line P6.y output driver in push-pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mod e
Table 23 : Port 6 Alter nat e Functions
Port 6 Alternate Function
CSSEL = 10 Alternate Function
CSSEL = 01 Alternate Function
CSSEL = 00 Alternate Function
CSSEL = 11
P6.0
P6.1
P6.2
P6.3
P6.4
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
General purpose I/O
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
P6.5
P6.6
P6.7
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Port 6
Alternate Function a)
General Purpose Input/Output
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0
12 - PARALLEL PORTS ST10F269
84/184
The chip select lines of Port 6 have an internal
weak pull-up device. This device is switched on
durin g reset. This feature is implemented to drive
the chip select lines high during reset in order to
avoid multiple chip selection.
After reset the CS function must be used, if
selected so. In this case there is no possibility to
program any port latches before. Thus the
alternate f unction ( CS) is selec ted aut omatically in
this case.
Note: The open drain output option can only be
selected via software earliest during the
initialization routine; at least signal CS0
will be in push/pull output driver mode
di re ctly afte r r e se t.
Fi gure 37 : Block Diagr am of Port 6 Pins with an Alternate Out put Function
MUX
0
1
"0"
Open Drain
Latch
Write ODP6.y
Read ODP6.y
Direction
Latch
Write DP6.y
Read DP6.y
In ter nal Bus
MUX
0
1
Input
Latch
Clock
P6.y
Output
Buffer
Port Output
Latch
Read P6 .y
Write DP6.y Alternate
Data
Output MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable
y = (0...4, 6, 7)
12 - PARALLEL PORTS ST10F269
86/184
12.10 - Port 7
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the
correspon ding direction register DP 7. Each port line can be switched into push -p ull o r open d rain mode
via the open drain control register ODP7.
P7 (FFD0h / E8h) SFR Reset Value: --00h
DP7 (FFD2h / E9h) SFR Reset Value: --00h
ODP7 (F1D2h / E9h) ESFR Reset Value: --00h
1514131211109876543210
- - - - - - - - P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0
RW RW RW RW RW RW RW RW
P7.y Po r t Data Register P7 Bit y
1514131211109876543210
--------DP7.7DP7.6DP7.5DP7.4DP7.3DP7.2DP7.1DP7.0
RW RW RW RW RW RW RW RW
DP7.y Port Direction Register DP7 Bit y
DP7.y = 0: Port line P7.y is an input (high impedance )
DP7.y = 1: Port l ine P7.y is an output
1514131211109876543210
--------ODP7.7ODP7.6ODP7.5ODP7.4ODP7.3ODP7.2ODP7.1ODP7.0
RW RW RW RW RW RW RW RW
ODP7.y Port 7 Open Drain Control Register Bit y
OD P7.y = 0: Port line P7.y output dr iver in push-pull mode
OD P7.y = 1: Port line P7.y output driver in open drain mode
ST10F269 12 - PARALLEL PORTS
87/184
12.10 .1 - Altern ate Functions of Port 7
The uppe r 4 lines of Port 7 (P7. 7...P7.4) serve as
capture inputs or compare outputs
(CC31IO...CC28IO) for the CAPCOM 2 unit.
The usage o f the por t lines by the CAPCO M unit,
its accessibility via software and the precautions
are the same as describe d for t he Po rt 2 lin es.
As all other capture inputs, the capture input
function of pins P7.7...P7.4 can also be used as
external interrupt inputs (200ns sample rate at
40MHz CPU clock on PQFP144 devices and
250ns sample rate at 32MHz CPU clock on
T Q FP144 devi ces) .
The lower 4 lines of Por t 7 (P7.3...P7.0) serve as
outputs from the PWM module
(POUT3...POUT0).
At these pins the value of the respective port
output latch i s EXORed with the value of the PWM
outpu t rather than ANDed , as the other pins do.
This allo ws to use the alt ernate output value either
as it is (port latch holds a ‘0’) or to inv ert its lev el at
the pin (port latch holds a ‘1’).
Note that the PWM outputs must be enabled via
the respective PENx bit in PWMCON1.
The Table 24 summarizes the alternate functions
of Po r t 7.
Table 24 : Port 7 Alter nat e Functions
Port 7 Alternate Function
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
POUT0 PWM mode channel 0 output
POUT1 PWM mode channel 1 output
POUT2 PWM mode channel 2 output
POUT3 PWM mode channel 3 output
CC28IO Capture input / compare outpu t channel 28
CC29IO Capture input / compare outpu t channel 29
CC30IO Capture input / compare outpu t channel 30
CC31IO Capture input / compare outpu t channel 31
Fi gure 39 : Port 7 I/O and Alternate Functions
Port 7
Alternate Func tion
General Purpose Input/ Output
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
CC31IO
CC30IO
CC29IO
CC28IO
POUT3
POUT2
POUT1
POUT0
12 - PARALLEL PORTS ST10F269
88/184
The structure of Port 7 differs in the wa y the output
latches are connected to the internal bus and to
the pin driver. Pins P7.3...P7.0 (POUT3...POUT0)
EXOR the alternate data output with the por t latch
output, which allows to use the alternate data
directly or inverted at the pin driver.
Fi gure 40 : Block Diagram of Port 7 Pins P7.3...P7.0
Open Drain
Latch
Write ODP7.y
Read ODP7.y
Direction
Latch
Write DP7.y
Read DP7.y
Internal Bus
MUX
0
1
Input
Latch
Clock
P7.y/POUTy
Output
Buffer
y = 0...3
Port Output
Latch
Read P7.y
Write DP7.y
=1
Port Data
Output EXOR
Alternate
Data
Output
ST10F269 12 - PARALLEL PORTS
89/184
Fi gure 41 : Block Diagr am of Port 7 Pi ns P7.7...P7.4
Open Drain
Latch
Write ODP7.y
Re ad O DP 7.y
Direction
Latch
Write DP7.y
Read DP7. y
Internal Bus
MUX
0
1
Al te rnate Latch
Da ta Input
Input
Latch
Clock
P7.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1Output
Latch
≥ 1
Write Port P7.y
Compare Trigger
Read P7.y
y = (4...7)
z = (28...31)
Alternat e Pin
Da ta Input
12 - PARALLEL PORTS ST10F269
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12.11 - Port 8
If this 8-bit port is used for general purpose I/O,
the direct ion of each line can be configured via the
corresponding direction register DP8. Each port
line can be switched into push/pull or open drain
mode via the open drain control register ODP8.
P8 (FFD4h / EAh) SFR Reset Value: --00h
DP8 (FFD6h / EBh) SFR Reset Value: --00h
ODP8 (F1D6h / EBh) ESFR Reset Value: --00h
1514131211109876543210
- - - - - - - - P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0
RW RW RW RW RW RW RW RW
P8.y Po r t Data Register P8 Bit y
1514131211109876543210
--------DP8.7DP8.6DP8.5DP8.4DP8.3DP8.2DP8.1DP8.0
RW RW RW RW RW RW RW RW
DP8.y Port Direction Register DP8 Bit y
DP8.y = 0: Port line P8.y is an input (high impedance )
DP8.y = 1: Port l ine P8.y is an output
1514131211109876543210
--------ODP8.7ODP8.6ODP8.5ODP8.4ODP8.3ODP8.2ODP8.1ODP8.0
RW RW RW RW RW RW RW RW
ODP8.y Port 8 Open Drain Control Register Bit y
OD P8.y = 0: Port line P8.y output dr iver in push-pull mode
OD P8.y = 1: Port line P8.y output driver in open drain mode
ST10F269 12 - PARALLEL PORTS
91/184
12.11 .1 - Altern ate Functions of Port 8
The 8 lines of Port 8 serve as capture input s or as
compare outputs (CC23IO...CC16IO) for the
CAPC OM 2 unit.
The usage o f the por t lines by the CAPCO M unit,
its accessibility via software and the precautions
are the same as describe d for t he Po rt 2 lin es.
As all other capture inputs, the capture input
function of pins P8.7...P8.0 can also be used as
external interrupt inputs (200ns sample rate at
40MHz CPU clock on PQFP144 devices and
250ns sample rate at 32MHz CPU clock on
T Q FP144 devi ces) .
The Table 25 summarizes the alternate functions
of Po r t 8.
Table 25 : Port 8 Alter nat e Functions
Port 7 Alternate Function
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
CC16IO Capture input / compare output channel 16
CC17IO Capture input / compare output channel 17
CC18IO Capture input / compare output channel 18
CC19IO Capture input / compare output channel 19
CC20IO Capture input / compare output channel 20
CC21IO Capture input / compare output channel 21
CC22IO Capture input / compare output channel 22
CC23IO Capture input / compare output channel 23
Fi gure 42 : Port 8 I/O and Alternate Functions
Port 8
Alternate FunctionGeneral Purpose Input / Output
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
CC23IO
CC22IO
CC21IO
CC20IO
CC19IO
CC18IO
CC17IO
CC16IO
12 - PARALLEL PORTS ST10F269
92/184
The structure of P ort 8 di ff er s in the way the output
latches are connected to the internal bus and to
the pin driver (see Figure 43). Pins P8.7...P8.0
(CC23IO...CC16IO) combine internal bus data
and alternate data output before the port latch
input, as do the Port 2 pins.
Fi gure 43 : Block Diagram of Port 8 Pins P8.7...P8.0
Open Dr ain
Latch
Write ODP8.y
Read OD P8. y
Direction
Latch
Write DP8.y
Read DP8.y
In te rna l Bus
MUX
0
1
Alternat e Lat ch
Data Input
Input
Latch
Clock
P8.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1Output
Latch
≥ 1
Write Port P8.y
Compar e Trigger
Read P8.y
y = (7...0)
z = (16...23)
Alternat e Pin
Data Input
ST10F269 13 - A/D CONVERTER
93/184
13 - A/D CONVERT ER
A 10-bit A/D converter with 16 multiplexed input
channels and a sample and hold circuit is
integrated on-chip. The sample time (for loading
the capacitors) and the conversion time is
programmable and can be adjusted to the
external circuitr y.
To remove high frequency components from the
analog input signa l, a low-pass filter must be con-
nec ted at the ADC input.
Overrun error detection / protection is controlled
by the ADDAT register. Either an interrupt reques t
is generated when the result of a previous
conversion has not been read from the result
register at the time the next conversion is
complete, or the next conversion is suspended
until the previous result has been read. For
applications which require less than 16 analog
input channels, the re maining channel inputs can
be used as digital input port pins. The A/D
converter of the ST10F269 supports different
conv ersion modes:
– Single chann el sing le con versi on : the anal og
level of the selected channel is sampled once
and converted. The result of the conversion is
stored in the ADDAT register.
– Single channel continuous conversion: the
analog level of the selected channel is repeated-
ly sampled and convert ed. The result of the con-
version is stored in the ADDAT register.
– Auto scan singl e conversion: the analog level
of the selec ted cha nnels are sampl ed onc e a nd
converted. After each conversion the result is
stored in the ADDAT register. The da ta can be
transferred to the RAM by interrupt software
management or using the powerful Peripheral
Event Controller (PEC) data transfe r.
– Auto scan continuous conversion: the analog
level of the selected channels are repeatedly
sampled and converted. The result of the con-
version is stored in the ADDAT register. The
data can b e t ransferred to the RAM by interrupt
software management or using the PEC data
transfer.
– Wait for ADDAT read mode: when using con-
tinuous modes, in order to avoid to overwrite
the result of the current conversion by the next
one, the ADWR bit of ADCON control register
must be activated. Then, until the ADDAT regis-
ter is read, the new result is stored in a tempo-
rary buffer and the con version is on hold.
– Channel injection mode: when using
continuous modes, a selected channel can be
converted in between without changing the
current operating mode. The 10-bit data of the
conversion are stored in ADRES field of
ADDAT2. The current continuous mode remains
active after the single conversion is completed
Notes: 1. Section 21.4.5 -: Direct Drive for TCL definition.
2. tCC = TCL x 24
Table 26 : ADC S ample Clock and Conv ersion Clock (PQFP144 devices)
ADCTC Conversion Clock tCC ADSTC Sample Clock tSC
TCL1 = 1/2 x fXTAL At fCPU = 40MHz tSC =At f
CPU = 40MHz
00 TCL x 24 0.3µs00 t
CC 0.3µs 2
01 Reserved, do not use Reserved 01 tCC x 2 0.6µs 2
10 TCL x 96 1.2 µs10t
CC x 4 1.2µs 2
11 TCL x 48 0.6 µs11t
CC x 8 2.4µs 2
13 - A/D CONVERTER ST10F269
94/184
Table 27 : ADC S ample Clock and Conv ersion Clock (TQFP144 devices)
Notes: 1. Section 21.4.5 -: Direct Drive for TCL definition.
2. tCC = TCL x 24
ADCON 15/14
ADCTC
Conversion Clock tCC ADCON 13/12
ADSTC
Sample Clock tSC
TCL1 = 1/2 x fXTAL At fCPU = 32MHz tSC =At f
CPU = 32MHz
00 TCL x 24 0.375µs00 t
CC 0.375µs 2
01 Reserved, do not use Reserved 01 tCC x 2 0.75µs 2
10 TCL x 96 1.5 µs10t
CC x 4 1.50µs 2
11 TCL x 48 0.75 µs11t
CC x 8 3.00µs 2
ST10F269 14 - SERIAL CHANNELS
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14 - SERIAL CHANNELS
Serial communication with other microcontro llers,
microprocessors, terminals or external peripheral
components is provided by two serial interfaces:
the asynchronous / synchronous serial channel
(ASCO) and the high-speed synchronous serial
channel (SSC). Two dedicated Baud rate
genera tors set up all standard B aud rates without
the requirement of oscillator tuning. For
transmission, reception and erroneous reception,
3 separate interrupt vectors are provided for each
serial channel .
14.1 - Asynchronous / Synchronous Serial
Interface (ASCO)
The asynchronous / synchronous serial interface
(ASCO) provides serial communication between
the ST10F269 and other microcontrollers,
microproces sors or extern al peri pherals.
A set of registers is used to configure and to
con trol the ASCO ser ial interface:
– P 3, DP3, ODP3 for pin configuration
– SOBG for Baud rate generator
– SOTBUF for transmit buffer
– SOTIC for transmit interrupt control
– S OT B IC for transmit buffer interrupt control
– S OC ON for control
– SORBUF fo r rec eive buffer (re ad only)
– S ORIC for receive interrupt control
– S OEI C for error interrupt control
14.1.1 - ASCO in Asynchronous Mode
In asynchronous mode, 8 or 9-bit data transfer,
parity generation and the number of stop bit can
be selected. Parity framing and overrun error
detection is provided to increase the reliability of
data transfers . Transmissi on and reception of data
is double-buffered. Full-duplex communication up
to 1.25M Bauds (at 40MHz fCPU on PQFP144
devices) and up to 1MBaud (at 32MHz fCPU on
TQF P1 44 device s) is supported in this mode.
Figure 44 : A synchron ous Mode of Ser ial Channel ASC0
Pin
2
CPU
Clock
S0R
Baud Rate Timer
Relo ad Regis te r
16
Clock
Serial Po rt Control
Shift Clo ck
S0M S0STP S0FE S0OE
S0PE
S0REN
S0FEN
S0PEN
S0OEN
S0LB
S0RIR
S0TIR
S0EIR
Re ceive Int errupt
Request
Tra nsmit Inte r r upt
Request
Error Inte rrupt
Request
Transmit Shift
Register
Receive Shift
Register TXD0 / P3.10
Tr ansmit Buf f er
Register S0TBUF
Recei ve Buffer
Regi ster S0 RB UF
SamplingMUX
0
1
Pin
Input
Internal Bus
RXD0/P3.11
Output
14 - SERIAL CHANNELS ST10F269
96/184
Asynch ronous Mode Ba ud rate s
For asynchronous operation, the Baud rate
generator provides a clock with 16 times the rate
of the est ablished Baud rate. Every recei ved bit is
sampled at the 7th, 8th and 9th cycle of this clock.
The Baud rate for asynchronous operation of
serial channel ASC0 and the required reload
value for a given Baud rate c an be deter mi ned by
the following for mulas :
(S0BRL) represents the content of the reload
register, taken as unsigned 13-bit integer,
(S0BRS) represents the value of bit S0BRS (‘0’ or
‘1’), taken as integ er.
Using the above equation, the maximum Baud
rate can be calcul ated for any given clock speed.
Baud rate versus reload register v alue (SOBRS=0
and SOBRS=1) is described in Table 28. and
Table 29
Note: The deviation errors given in the Table 28 are rounded. To avoid deviation errors us e a B aud rat e
cr y stal (providing a multiple of the ASC0/SSC s amp ling frequency ).
BAsync = fCPU
16 x [2 + (S0BRS)] x [(S0B RL) + 1]
S0BRL = ( fCPU
16 x [2 + (S0BRS)] x BAsync ) - 1
Table 28 : Comm only Used Baud Rates by Reload Value and Deviation Errors (PQFP144 devices)
S0BRS = ‘0’, fCPU = 40MHz S0BRS = ‘1’, fCPU = 40MHz
Baud Rate (Baud) Deviation Error Reload Value
(hexa) Baud Rate (Baud) Deviation Error Reload Value
(hexa)
1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007
56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E
38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015
19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B
9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056
4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD
2 400 +0.2% / -0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B
1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6
600 0.0% / 0.0% 0822 / 0823 600 +0.1% / -0.0% 056B / 056C
300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9
153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9
ST10F269 14 - SERIAL CHANNELS
97/184
Note: The deviation errors given in the Table 29 are rounded. To avoid deviation errors us e a B aud rat e
cr y stal (providing a multiple of the ASC0/SSC s amp ling frequency ).
Table 29 : Comm only Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices)
S0BRS = ‘0’, fCPU = 32MHz S0BRS = ‘1’, fCPU = 32MHz
Baud Rate (Baud) Deviation Error Reload Value Baud Rate (Baud) Deviation Error Reload Value
1000 000 ±0.0% 0000h 666 667 ±0.0% 0000h
56000 +5.0% / -0.8% 0010h / 001h 56000 +8.2% / -0.8% 000Ah / 000Bh
38400 +0.2% / -3.5% 0019h / 0020h 38400 +2.1% / -3.5% 0010h / 0011h
19200 +0.2% / -1.7% 0033h / 0034h 19200 +2.1% / -0.8% 0021h / 0022h
9600 +0.2% / -0.8% 0067h/ 0068h 9600 +0.6% / -0.8% 0044h / 0045h
4800 +0.5% / -0.3% 00CFh / 00CEh 4800 +0.6% / -0.1% 0089h / 008Ah
2400 +0.2% / -0.1% 019Fh / 01A0h 2400 +0.3% / -0.1% 0114h / 0115h
1200 +0.1% / -0.1% 0340h / 0341h 1200 +0.1% / -0.1% 022Ah / 022Bh
600 +0.1% / -0.1% 0681h / 0682h 600 +0.1% / -0.1% 0456h / 0457h
95 +0.1% / -0.1% 291Dh / 291Eh 75 +0.1% / 0.1% 22B7h / 22B8h
63 +0.1% / -0.1% 2955h / 2956h
14 - SERIAL CHANNELS ST10F269
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14.1.2 - ASCO in Synchronous Mode
In synch ronous mod e, data are transmitted or received synchronously to a shift clock which is generated
by the ST10F269. Half-duplex communication up to 5M Baud (at 40MHz fCPU) or 4M Baud (at 32MHz) is
pos sible in this mode.
Figure 45 : Synchronous Mode of Serial Channel ASC0
2
CPU
Clock
S0R
Baud Rate Timer
Reload Register
4
Clock
Serial Port Control
Shif t Clock
S0 M = 000 B S0OE
S0REN
S0OEN
S0LB
S0RIR
S0TIR
S0EIR
Rec eiv e Interrupt
Request
Transmit Int errupt
Request
Error Interrupt
Request
Transmi t Shift
Register
Rece iv e Sh ift
Register
Trans mi t Buffer
Regis ter S 0TBUF
Receive Buf fer
Regis ter S0RB UF
MUX
0
1
Pin
In te rnal Bus
Receive
Output
Transmit
Pin
Input/Output
TDX0/P3.10
RXD0/P3.11
ST10F269 14 - SERIAL CHANNELS
99/184
Synchronous Mode Baud Rates
For synchronous operation, the Baud rate
generator provides a clock wi th 4 times the rate of
the established Baud rate. The Baud rate for
synchronous operation of serial channel ASC0
can be deter m ined by the fo llowing formula:
(S0BRL) represents the content of the reload
register, taken as unsigned 13-bit integers,
(S0BRS) represents the value of bit S0BRS (‘0’ or
‘1’), taken as integ er.
Using the above equation, the maximum Baud
rate can be calculated for any clock speed as
given in Table 30.and Table 31
Note: The deviation errors given in the Table 30 are rounded. To avoid deviation errors us e a B aud rat e
cr y stal (providing a multiple of the ASC0/SSC s amp ling frequency )
BSync =
S0BRL = ( fCPU
4 x [2 + (S0BRS)] x BSync ) - 1
fCPU
4 x [2 + (S0BRS)] x [(S0BRL) + 1]
Table 30 : Comm only Used Baud Rates by Reload Value and Deviation Errors (PQFP144 devices)
S0BRS = ‘0’, fCPU = 40MHz S0BRS = ‘1’, fCPU = 40MHz
Baud Rate (Baud) Deviation Error Reload Value
(hexa) Baud Rate (Baud) Deviation Error Reload Value
(hexa)
5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D
56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B
38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056
19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD
9 600 +0.2% / -0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B
4 800 +0.1% / -0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6
2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / -0.0% 056B / 056C
1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9
900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3
612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE
14 - SERIAL CHANNELS ST10F269
100/184
Table 31 : Comm only Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices)
Note: The deviation errors given in the Table 31 are rounded. To avoid deviation errors us e a B aud rat e
cr y stal (providing a multiple of the ASC0/SSC s amp ling frequency )
S0BRS = ‘0’, fCPU = 32MHz S0BRS = ‘1’, fCPU = 32MHz
Baud Rate (Baud) Deviation Error Reload Value Baud Rate (Baud) Deviation Error Reload Value
4 000 000 ±0.0% 0000h 2 666 667 ±0.0% 0000h
224 000 +5.0% / -0.8% 0011h / 0012h 224 000 +8.2% / -0.8% 000Bh / 000Ch
112 000 +2.0% / -0.8% 0023h / 0024h 112 000 +3.5% / -0.8% 0017h / 0018h
56 000 +0.6% / -0.8% 0046h / 0047h 56 000 +1.3% / -0.8% 002Fh / 0030h
38 400 +0.2% / -0.85% 0077h / 0078h 38 400 +0.6% / -0.8% 0044h / 0045h
19 200 +0.2% / -0.3% 00BFh / 00C0h 19 200 +0.6% / -0.1% 008Ah / 008Bh
9 600 +0.2% / -0.1% 01A0h/ 01A1h 9 600 +0.3% / -0.1% 0115h / 0116h
4 800 +0.0% / -0.1% 0340h / 0341h 4 800 +0.1% / -0.1% 022Bh / 022Ch
2 400 +0.0% / -0.0% 0682h / 0683h 2 400 +0.0% / -0.1% 0456h / 0457h
1 200 +0.0% / -0.0% 004h / 0D05h 1 200 +0.0% / -0.0% 08ACh / 08ADh
600 +0.0% / -0.0% 1A0Ah / 1A0Bh 600 +0.0% / -0.0% 115Bh / 115C7h
490 +0.0% / -0.0% 1FE2h / 1FE3h 320 +0.2% 1FFFh
ST10F269 14 - SERIAL CHANNELS
101/184
14. 2 - Hi gh Spee d Sync hronou s Serial Chann el
(SSC)
The High-Speed Synchronous Serial Interface
SSC provides flexible high-speed serial
commu nicati on b etween th e S T1 0F269 and other
microcontrollers, microprocessors or external
peripherals.
The SSC supports full-duplex and half-duplex
synchronous communication. The serial clock
signal can be generated by the SSC itself (master
mode) or be received from an external master
(slave mode). Data width, shift direction, clock
polarity and phase are programm able.
This allows communication with SPI-compatible
devices. Transmission and reception of data is
double-buffered. A 16-bit Baud rate generator
provides the SSC with a separate serial clock
signal. The serial channel SSC has its own
dedicated 16-bit Baud rate generator with 16-bit
reload capability, allowing Baud rate generation
independent from the timers.
Fi gure 46 : Synchronous Serial Channel SSC Block Diagram
Baud Rate Gene rator
SSC Control
Block
Pin
Internal Bus
Clock Control
CPU
Clock
Slave Clock
Master Clock SCLK
Shift
Clock
Status Control
Receive Interr upt Reque st
Transmit Interrupt Request
Error Interrupt Request
16-Bit Shift Regis ter
Pin
Control
Pin
Pin
MTSR
MRST
Transmit Buffer
Register SSCT B Receive Buffer
Register SSCRB
14 - SERIAL CHANNELS ST10F269
102/184
Baud Rate Generatio n
The Baud rate generator is clock ed by fCPU/2 . Th e
timer is counting downwards and can be started
or stopped through the global enable bit SSCEN
in register SSCCON. Register SSCBR is the
dual-function Baud Rate Generator/Reload
register. Reading SSCBR, while the SSC is
enabled, retur ns the content of the timer. Readi ng
SSCBR, while the SSC is disabled, returns the
programmed reload value. In this mode the
des ired reload value can be written to SSCBR.
Note Never write to SSCBR, while the SSC is
enabled.
The formulas below calculate the resulting Baud
rate for a given reload value and the required
reload va lue for a g iven Baud rate:
(SSCBR) represents the content of the reload
register, taken as unsigned 16-bit integer.
Table 32 lists some possible Baud rates against
the required reload values and the resulting bit
times f o r a 40MHz CPU cloc k.
Table 33 lists some possible Baud rates against
the required reload values and the resulting bit
times f o r a 32MHz CPU cloc k.
.
Table 32 : Synchronous Baud Rate and Reload
Values (PQFP144 devices)
Baud Rate Bit Time Reload Value
Reserved use a
reload value > 0. --- ---
10M Baud 100ns 0001h
5M Baud 200ns 0003h
2.5M Baud 400ns 0007h
1M Baud 1µs 0013h
100K Baud 10µs 00C7h
10K Baud 100µs 07CFh
1K Baud 1ms 4E1Fh
306 Baud 3.26ms FF4Eh
Baud rateSSC = fCPU
2 x [(SSCBR ) + 1]
SSCBR = ( fCPU
2 x Baud ra teSSC ) - 1
Table 33 : Synchronous Baud Rate and Reload
Values (TQFP144 devices)
Baud Rate Bit Time Reload Value
Reserved use a
reload value > 0. --- ---
8MBaud 125ns 0001h
4MBaud 250ns 0003h
2MBaud 500ns 0007h
1MBaud 1µs000Fh
500KBaud 2µs001Fh
100KBaud 10µs009Fh
10KBaud 100µs030Ch
1K Baud 1ms 3E7Fh
244.14 Baud 5.24ms FFFFh
ST10F269 15 - CAN MODULES
103/184
15 - CAN MODULES
The two integrated CAN modules (CAN1 and
CAN2) are identical and handle the completely
autonomous transmission and reception of CAN
frames according to the CAN specification V2.0
pa rt B (a ctiv e).
Each on-chip CAN module can receive and
transmit standard f rames wi th 11-bit identifiers as
well as extended frames with 29-bit identifiers.
These t wo CAN m odules are both identical to t he
CAN module of the ST10F 167.
Because of duplication of the CAN controllers , the
foll owi ng adjustments are to be considered:
– Same internal register addresses of both CAN
controllers, but with base ad dresses differing in
address bit A8; separate chip select for each
CAN module. Refer to Chapter : Memory Organ-
ization on page 14.
– The CAN1 transmit line (CAN1_TxD) is the
alternate function of the Port P4.6 pin and the
receive line (CAN1_RxD) is the alternate
function of the Port P4.5 pin.
– The CAN2 transmit line (CAN2_TxD) is the
alternate function of the Port P4.7 pin and the
receive line (CAN2_RxD) is the alternate
function of the Port P4.4 pin.
– Interrupt request line of the CAN1 module is
connected to the XBUS interrupt line XP0,
interrupt of the CAN2 module is connected to
the lin e XP1.
– The CAN modules must be selected with
corresponding CANxEN bit of XPERCON register
before the b it XPEN of SYSCON registe r is set.
– The reset default configuration is: CAN1 is
enabled, CAN2 is disabled.
15.1 - CAN Mo dules M emory Mapping
15.1.1 - CAN1
Address range 00’EF00h - 00’EFFFh is reserved
for the CAN1 Module access. CAN1 is enabled by
setti ng XPEN b it 2 of t he SY SCON reg ister and by
setting b it 0 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states g ive an access time of
125ns at 40MHz CPU clock or at 32MHz CPU
clock. No tri-state wait states are used.
15.1.2 - CAN2
Address range 00’EE00h - 00’EEFFh is rese rved
for the CAN2 Module access. CAN2 is enabled by
setti ng XPEN b it 2 of t he SY SCON reg ister and by
setting b it 1 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states g ive an access time of
125ns at 40MHz or 32MHz CP U clock. No tri-state
wait states are used.
Note: If one or both CAN modules is used,
Port 4 cannot be p rogrammed t o output al l
8 segment address lines. Thus, only
4 segment address lines can be used,
reducing the external memory space to
5M Bytes (1M Byte per CS line).
15.2 - CAN Bus Co n figurations
Dependi ng on application, CA N bus configuration
may be one single bus with a single or multiple
interfaces or a multiple bus with a single or
multiple interfaces. The ST10F269 is able to
sup port these 2 cases.
Single CAN Bus
The single CAN Bus multiple interfaces
configuration may be implemented using 2 CAN
transceivers as shown in Figure 4 7.
Fi gure 47 : Single CAN Bus Multiple Interfaces,
Multiple Trans c eive r s
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver CAN
Transceiver
CAN_H
CAN_H CAN bus
15 - CAN MODULES ST10F269
104/184
The ST10F269 also supports single CAN Bus
multiple (dual) interfaces using the open drain
option of the CANx_TxD output as shown in
Figure 48. Thanks to the OR-Wired Connection,
only one transceiver is required. In this case the
des ign of t he app licat ion mus t take in account t he
wire length and the noise envir onment.
Multiple CAN Bus
The ST10F269 provides 2 CAN interfaces to
support such kind of bus configuration as shown
in Figure 49.
Fi gure 48 : Single CAN Bus, Dual I nterf aces,
Single Tr an sc e iv er
Fi gure 49 : Connection to Two Different CAN
Buses (e.g. for gateway application)
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver
CAN_H
CAN_H CAN bus
* Open dra in output
+5V
2.7kΩ
**
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver CAN
Transceiver
CAN_H
CAN_H CAN
CAN bus 2
bus 1
ST10F 269 16 - REAL TIME CLOCK
105/184
16 - REAL TIME CLOCK
The Real Time Clock is an independent timer,
which clock is directly derived from the clock
oscillator on XTAL1 input so that it can keep on
running even in Idle or Power down mode (if
enabled to). Registers access is implemented
onto the XBUS. This module is designed for the
foll owi ng purposes:
– Generate the current time and date for the system
– Cyclic time based interrupt, provides Port
2 external interrupts every second and every
n seconds (n is programmable) if enabled.
– 58-bit timer for long term mea suremen t
– Capable to exit the ST10 chip from power down
mode (if PWDCFG of SYSCON set) after a pro-
grammed delay .
The real tim e clock is base on tw o main blocks of
counters. The first block is a prescaler which
generates a ba sic reference clock (for example a
1 second period). This basic reference clock is
coming out of a 20-bit DIVIDER (4-bit MSB
RTCDH counter and 16-bit LSB RTCDL counter).
This 20-bit counter is driven by an input clock
derived from the on-chip high frequency CPU
clock, predivided by a 1/64 fixed counter (see
Figure 51). This 20-bit counter is loaded at each
basic reference clock period with the value of the
20-bit PRESCALER register (4-bit MSB RTCPH
register and 16-bit LSB RTCPL register). The
value of the 20-bit RTCP register determines the
period of the b asic refer ence clo ck.
A timed interr upt reques t (RTCSI) may be sent on
each basic reference clock period. The second
block of the RT C is a 32-bit counter (16-bit RTCH
and 16-bit RTCL). This counter may be initialized
with the current sys tem time. R TCH/RTCL counter
is driven with the basic reference clock signal. In
ord er to provide an alarm func tion the c ontent s of
RTCH/RTCL counter is compared with a 32-bit
alarm register (16-bit RTCAH register and 16-bit
RTCAL register). The alarm register may be
loaded with a reference date. An alarm interrupt
request (RTCAI), may be generated when the
value of RTCH/RTCL counter matches the
reference date of RTCAH/RTCAL register.
The timed RTCSI and the alarm RTCAI interrupt
requests can trigger a fast external interrupt via
EXISEL register of port 2 and wake-up the ST10
chip when running power down mode. Using the
RTCOFF bit of RTCCON register, the user may
switch off the clock oscillator when entering the
power down mode.
Fi gure 50 : ESFRs and Port Pins Associated with the RTC
----- - - -YYYY----
EXISEL
EXIS EL E xternal Interrupt Sourc e S elect io n regist er (Por t 2)
1 second tim ed i nterr upt requ est (RTCS I) trigger s firq [2] and al ar m interr upt requ est (RTCAI ) trigger s firq [3]
RTC dat a and control registers are imp le me nte d onto the XBU S.
----- - - -YYYYYYYY
CCxIC
16 - REAL TIME CL OCK ST10F269
106/184
16.1 - RTC registers
16.1.1 - RTCCON: RT C Control Register
The functions of the RTC are controlled by the
RTCCON control register. If the RTOFF bit is set,
the RTC dividers and counters clock is disabled
and regist ers can be wr itten, when the ST10 chi p
enters power down mode the clock oscillator will
be switch off. The RTC has 2 interrupt sources,
one is triggered every basic clock period, the
other one is the alar m.
RTCCON includes an interrupt request flag and
an interrupt enable bit for each of them. This
register i s read and written vi a the XBUS .
RTCCON (EC00h) XBUS Reset Value: --00h
Notes: 1. As RTC CON regist er is not bit-addres sable, the value of t hese bits mus t be read by check i ng their associated CCx IC register.
The 2 RTC interrupt signals are connected to Port2 in order to trigger an external interrupt that wake up the chip when in power down
Fi gure 51 : RTC Block Diagram
/64
RTCPLRTCPH
RTCH RTCL RTCDH RTCDL
RTCAH RTCAL
Clo ck Oscillator
Reload
=
20 bit DIVIDER32 bit COUNTER
RTCCON
AlarmIT Basic Clock IT
RTCAI RTCSI
Pro gram m abl e AL A RM Regi st er Programmable PRESCALER Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - - - - - RTCOFF - - - RTCAEN RTCAIR RTCSEN RTCSIR
RW RW RW RW RW
RTCOFF 2 R TC Switch Off Bi t
‘0’: clock oscilla tor and RTC keep on running eve n if ST10 in power dow n mode
‘1’: clock oscillator is switch off if ST10 enters power down mode, RTC dividers and
counters are stopped and registers can be written
RTCAEN 2RTC Alarm Interrupt ENable
‘0’: RTCAI is disabled
‘1’: RTCAI is enabled, it is generated ever y n se conds
RTCAIR 1RTC Alarm Interrupt Request flag (wh en the alarm is triggered)
‘0’: the bit was reseted less than a n seconds ago
‘1’: the interru pt was tr igg ered
RTCSEN 2RTC Sec ond inte r r upt EN able
‘0’: RTCSI is disabled
‘1’: R TCSI is enab l ed, it is generated e very second
RTCSIR 1RTC Second Interrupt Request flag (every second )
‘0’: the bit was reseted less than a second ago
‘1’: the interru pt was tr igg ered
16 - REAL TIME CL OCK ST10F269
108/184
16.1.2 - RTCPH & RTCPL: RTC PRESCALER
Registers
The 20-bit programmable prescaler divider is
loaded with 2 registers.
The 4 most significant bit are stored into RTCPH
and the 16 Less significant bit are stored in
RTCPL. In order to keep the system clock, those
registers are not reset.
They are write protected by bit RTOFF of
RTCCON register, write operation is allowed if
RTOF F i s set.
RTCPL (EC06h) XBUS Reset Value: XXXXh
RTCPH (EC08h) XBUS Reset Value: ---Xh
The value stored into RTCPH, RTCPL is called RTCP (coded on 20-bit). The dividing ratio of the
Prescaler divider is: ratio = 64 x (RTCP)
16.1.3 - RTCDH & RTCDL: RTC DIVIDER Counters
Every basic reference clock the DIVIDER counters are reloaded with the value stored RTCPH and
RTCPL registers. To ge t an accurate time me asurement it is poss ible to read the value of the DIVIDER,
reading the RTCDH, RTCDL. Those counters are read only. After any bit changed in the programm able
PRES CA LER register, the new value is loaded in the DIVIDER.
RTCDL (EC0Ah) XBUS Reset Value: XXXXh
RTCDH (EC0Ch) X B US Reset Value: ---Xh
Note: Those registers are not reset, and are read on ly.
1514131211109876543210
RTCPL
RW
1514131211109876543210
RESERVED RTCPH
RW
Fi gure 52 : PRESCALER Regi ster
1514131211109876543210
RTCDL
R
1514131211109876543210
RESERVED RTCDH
R
3 2 1 07 6 5 411 10 9 815 14 13 123 2 1 0
RTCPH
RTCPL
3 2 1 07 6 5 411 10 9 815 14 13 1219 18 17 16
20 bit word counter
ST10F 269 16 - REAL TIME CLOCK
109/184
When R TCD increments to reach 00000h, The 20-bit word st ored into RTCPH, R TCPL regi sters i s loaded
in RTCD.
Bit 15 to bit 4 of RTCPH and RTCDH are not
used. When reading, the return value of those bit
will b e ze ros.
16.1.4 - RTCH & RTCL: RTC Programmable
COUNTER Reg isters
The RTC has 2 x 16-bit programmable counters
which count rate is based on the basic time
reference (for example 1 second). As the clock
oscillator may be kept working, even in power
down mode, the RTC counters m ay be used as a
system clock. In addition RTC counters and
registers are not modified at any system reset.
The only way to force their value is to wr ite them
via the XBUS.
Those counters are write protected as well. The
bit RTOFF of the RTCCON register must be set
(RTC dividers and counters are stopped) to
enable a write operation on RTCH or RTCL.
A write operation on RTCH or RTCL regis ter loads
directly the correspondi ng counter. When reading,
the current value in the counter (system date) is
returned.
The counters keeps on running while the clock
oscillator is working.
RTCL (EC0Eh) XBUS Reset Value: XXXXh
RTCH (EC10h) XBUS Reset Value: XXXXh
Note: Those registers are nor reset
Fi gure 53 : DIVIDE R Count e rs
3 2 1 07 6 5 411 10 9 815 14 13 123 2 1 0
RTCDH
RTCDL
3210765411 10 9 815 14 13 1219 18 17 16
20 bit word internal value of the Prescaler divider
1514131211109876543210
RTCL
RW
1514131211109876543210
RTCH
RW
16 - REAL TIME CL OCK ST10F269
110/184
16.1.5 - RTCAH & RT CAL: RTC ALARM Registers
When the programmable counters reach the 32-bit v alue stored i nto RTCAH & RTCAL register s, an alarm
is trig gered and the interrupt reque st RTAIR is generated. Those registers are not protected.
RTCAL (EC12h ) XBUS Reset Value: XXXXh
RTCAH (EC14h) XBUS Reset Value: XXXXh
Note: Those registers are not reset
16.2 - Programming the RTC
RTC interr upt reques t signals are connected to Port 2, pad 10 (RTCSI) and pad 11 (RTCAI). An alternate
function Port2 is to generate fast interrupts firq[7:0]. To trigger firq[ 2] and f irq[3] t he foll owi ng configurat ion
has to be set .
EXICON ESFR controls the external interrupt edge selection, RTC interrupt requests are rising edge
active.
EXICON (F1C0h) ESFR Reset Value: 0000h
Notes: 1. EX I 2ES and EXI3ES must be configured as "01b" be cause RC T i nterrupt req uest line s ar e rising edge ac tive.
2. Alarm in te rrupt request li ne ( RTCA I) is linked with EXI3E S.
3. Ti med interrupt request line (RTCSI ) i s linked with EXI2E S.
EXI SEL ESF R enables the Port2 alternate sources. RTC interr upts are alter nat e sources 2 and 3.
EXISEL (F1DAh) ESFR Reset Value: 0000h
Note s: 1. Advi se d co nf i gu r a ti o n.
2. Alarm i nterrupt request (RTCAI) is linked with EXI3SS.
3. Ti med interrupt reque st (RT CS I) is linke d wi th EXI2SS.
1514131211109876543210
RTCAL
RW
1514131211109876543210
RTCAH
RW
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES 1 2 EXI2ES 1 3 EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS 2EXI2SS 3EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “altern ate source ”. 1
‘10’: Input from Port 2 pin ORed with “alternate source”. 1
‘11’: Input from Port 2 pin ANDed with “alternate source”.
ST10F 269 16 - REAL TIME CLOCK
111/184
Interrup t control registers are comm on with CAPCOM 1 Unit: CC10IC (RT C SI) and CC11IC (RTCAI).
CCxIC SFR Reset Value: --00h
CC 10IC: FF8Ch/C6h
CC 11IC: FF8Eh/C7h
1514131211109876543210
--------CCxIRCCxIE ILVL GLVL
RW RW RW RW
Source of interrupt Request Flag Enable Flag Interrupt Vector Vector Location Trap Number
External interrupt 2 CC10IR CC10IE CC10INT 00’0068h 1Ah/26
External interrupt 3 CC11IR CC11IE CC11INT 00’006Ch 1Bh/27
17 - WATCHDOG TIMER ST10F269
112/184
17 - WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism
which prevents the microcontroller from
malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a
reset of the chip and can only be disabled in the
time interval until the EINIT (end of initialization)
instruction has been ex ecut ed.
Therefore, the chip start-up procedure is always
monitored. The software must be designed to
service the watchdog timer before it overflows. If,
due to hardware or software related failures, the
software fails to do so, the watchdog timer
overflows and generates an internal hardware
reset. It pu ll s the RSTOUT pin low in order to allow
external hardware component s to be reset.
Each of the different reset sources is indicated in
the WDT CON register.
The indicated bits are cleared with the EINIT
instruction. The origin of the reset can be
ident ified during the initialization phase.
W D TCON (F FAE h / D7h) SF R Reset Value: 00xxh
Notes: 1. More tha n one reset i ndi cation fl ag may be set . After EI NIT, al l flags are cleared.
2. Power-on is detected when a ri sing edge from V DD = 0 V to VDD > 2.0 V is r ecognized on t h e i nt ernal 3.3V su pp ly.
3. These bits c annot be directly m odi f i ed by sof tware.
1514131211109876543210
WDTREL - - PONR LHWR SHWR SWR WDTR WDTIN
RW HR HR HR HR HR RW
WDTIN Watchdog Timer Input Frequency Selection
‘0’: Input Frequency is fCPU/2.
‘1’: Input Frequency is fCPU/128.
WDTR1-3 Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by a hardware reset or by the SRVWDT instruction.
SWR1-3 Software Reset Indication Flag
Set by the SRST execution.
Cleared by the EINIT instruction.
SHWR1-3 Short Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
LHWR1-3 Long Hardware Reset Indication Flag
Set by the input RSTIN.
Cleared by the EINIT instruction.
PONR1- 2-3 Power-On (Asynchr onous) Reset Indication Flag
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruction.
ST10F269 17 - WATCHDO G T IMER
113/184
The PONR flag of WDTCON register is set if the output vol tage of t he internal 3.3V supply falls below the
threshold (typically 2V) of the power-on det ection circuit. This circuit is effici ent to detect major fail ures of
the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not
set. Th is could be the case on fast switch-off / switch-on of the 5V supply. The time needed for such a
seq uence to activa te the PONR flag depends on the value of the capacitor s connected to the supply and
on the exact va lue of the inte rnal thresho ld of the detection circuit.
N o tes : 1. PONR bit m a y n ot be s e t for sh o rt s u ppl y fai lur e .
2. For power-on reset and reset after supply partial failure, asynchronous reset must be used.
In case of bi-d irectional rese t is enabled, a nd i f the RSTIN pin is latched low after the end of the interna l
reset sequence, then a Short hardware reset, a software reset or a watchdog reset will trigger a Long
hardware reset. Thus, Reset Indications flags will be se t to ind icate a Long Hardware Reset.
The Watchdog Timer is 16 -b it, clocked with the system clock divided by 2 or 128. The high Byte of the
watchdog timer register can be set to a pre-specified reload value (stored in W DTREL).
Each t ime it is ser viced by the application software, the high byte of the watchdog timer is reloaded. For
secur ity, rewrite WDTCON each time before the watchdog timer is serv iced
Table 35 shows the watchdog time range for 40MHz CPU clock and Table 36 shows the watchdog time
range for 32MHz C PU clock.
The watchdog time r period is calculated with the following formul a:
Table 34 : WDTCON Bit Value on Differ en t Resets
Reset Source PONR LHWR SHWR SWR WDTR
Power On Reset X X X X
Power on after partial supply failure 1) 2) XXX
Long Hardware Reset X X X
Shor t Hardwar e Reset X X
Software Reset X
Watchdog Reset XX
Table 35 : WDTRE L Reload Value (PQFP1 44 device s)
Reload value in WDTREL Prescaler for fCPU = 40MHz
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh 12.8µs819.2ms
00h 3.276ms 209.7ms
Table 36 : WDTRE L Reload Value (TQFP144 devices)
Reload value in WDTREL Prescaler for fCPU = 32MHz
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh 16.0µs 1.024ms
00h 4.096ms 262.1ms
PWDT 1
fCPU
--------------- 512×1WDTIN]63)256 WDTREL])[
–
(××[+(×=
18 - SYSTEM RE SET ST10F 269
114/184
18 - SYSTEM RESET
System reset initializes the MCU in a predefined
state. There are five wa ys to activ at e a reset s tate . The system start-up configuration is different for
eac h case as shown in Table 37.
Table 37 : Reset Event Definition
18.1 - Long Hardware Reset
The reset is triggered when RSTIN pin is pulled
low, then the MCU is immediately forced in reset
default state. It pulls low RSTOUT pin, it cancels
pending internal hold states if any, it aborts
external bus cycle, it switches buses (data,
address and control signals) and I/O pin driv ers to
high-impedance, it pulls high PORT0 pins and the
reset sequenc e starts.
To get a long hardware r eset , the du ration of the
external RSTIN signal must be longer than 1040
TCL. The level of RPD pin is sampled during the
whole RSTIN pulse duration. A low level on RPD
pin determines an asynchronous reset while a
high level leads to a synchronous reset.
Note A reset can be entered as synchronous
and exit as asynchronous if VRPD voltage
drops below the RPD pin threshold
(typically 2.5V for VDD = 5V) when RSTIN
pin is low or when RSTIN pin is internally
pulled low.
18.1.1 - Asynchronous Reset
Figure 54 and Figure 55 show asynchronous
reset condition (RPD pin is at low level).
Fi gure 54 : Asynchronou s Reset Sequ ence External Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
CPU
=f
XTAL
/ 2), else it is 4 CPU cloc k cycles (8 TCL).
Reset Source Short-cut Conditions
Power-on reset PONR Power-on
Long Hardware reset (synchronous & asynchronous) LHWR t RSTIN > 1040 TCL
Short Hardware reset (synchronous reset) SHWR 4 TCL < t RSTIN < 1038 TCL
Watchdog Timer reset WDTR WDT overflow
Software reset SWR SRST execution
6 or 8 TCL1)
CP U Cl o ck
RSTIN Asynchronous
Reset Condition
RPD
RSTOUT
ALE
PORT0 Reset Configuration 1st Instruction External Fetch
Latching point of PORT0
for system start-u p
configuration
81234 6759
RD
EXTERNAL FETCH
Internal reset
5 TCL
ST10F269 18 - SY STEM RESET
115/184
Fi gure 55 : Asynchronou s Reset Sequ ence Internal Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
CPU
=f
XTAL
/ 2), else it is 4 CPU cloc k cycles (8 TCL).
2) 2.1µs typical value.
Power-on reset
The asy nchronous reset must be used duri ng the
power-on of the MCU. Depending on the crystal
frequency, the on-chip oscillator needs about
10ms to 50ms to stabilize. The logic of the MCU
does not need a stabilized clock signal to detect
an asynchronous reset, so it is suitable for
power-on conditions. To ensure a proper reset
seq uence, the RSTIN pin and the RPD pin must
be held at low level until the MCU clock signal is
stabilized and the system configuration value on
PO RT0 is settled.
Hardware reset
The asynchronous reset must be used to recover
from catastrophic situations of the application. It
may be triggered by the hardware of the applica-
tion. Internal hardware logic and application cir-
cuitry are described in Section 18.6 - and
Figure 58, Figure 59 and Figure 60.
18.1.2 - Synchronous Reset (RSTIN pu lse >
1040TCL and RPD pin at high level)
The sy nchronous reset is a war m re set. It may be
genera ted s ynchro nously t o the CPU clock. To be
detected by the reset logic, the RS TIN pulse must
be low at least for 4 TCL (2 periods of CPU clock).
Then the I/O pins are set to h igh impedance and
RSTOUT
pin is dri ven low. After the
RSTIN
lev el is
detected, a short duration of 12 TCL (6 CPU
clocks) maximum elapses, during which pending
intern al hold states are cancelled and the current
internal access cycle, if any, is completed.
Ext ernal bus cycle is aborted.
The internal pull-down of
RSTIN
pin is activ ated if
bit BDRSTEN of SYSCON register was previously
set by software. This bit is always cleared on
power-on or aft er any reset sequence.
The internal sequence lasts for 1024 TCL (512
periods of CPU clock). After this duration the
pull-down of RSTIN pin for the bidirectional reset
function is released and the RSTIN pin level is
sampled. At this step the sequence lasts 1040
TCL (4 TCL + 12 TCL + 1024 TCL). If the
RSTIN
pin level is low, the reset sequence is extended
until
RSTIN
level becomes high. Refer to
Figure 56
Note If VRPD voltage drops below the RPD pin
threshold (typically 2.5V for VDD = 5V)
when RSTIN pin is low or when RSTIN pin
is internally pulled low, the ST10 reset
circuitry disables the bidirectional reset
function and RSTIN pin is no more pulled
6 or 8 TCL 1)
CP U Cl o ck
RSTIN
Asynchronous
Reset Condition
RPD
RSTOUT
PORT0 Re set C onfiguratio n
INTERNAL FETCH
Internal reset signal
Flash read signal
PLL factor
latch command
Flash under reset for internal charge pump ramping up
1s t fe tch
from Flash
Latching point of PORT0
for PLL configuration
Latching point of PORT0
for remaining bits
123
2.5µs max.2)
18 - SYSTEM RE SET ST10F 269
116/184
low. The reset is processed as an
asynchronous res et.
Fi gure 56 : Synchron ous Reset Sequenc e External Fetch (RSTIN pulse > 1040 TCL)
Note 1) RSTIN r ising ed ge to internal latc h of PORT0 is 3 CPU
clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU =f
XTAL / 2), else it is 4 CPU clock
cycl e s (8 TCL) .
2) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
3) If durin g the res et cond ition ( RSTIN low), VRPD voltage drops be low the thresho ld voltag e (typic ally 2. 5V for 5 V operation), the
ST10 reset ci rcuitry disable s t he bi directional reset fu nction and RS TIN pin is no m ore pulled low.
18.1.3 - Exit of Long Har d w a re Reset
- If the RPD pin level is lo w when the RSTIN pi n
is sampled high, the MCU completes an
asynchrono us reset sequence.
- If the RPD pi n le v el is h ig h when the RSTIN pi n
is sampled high, the MCU completes a
synchronous reset sequence.
The system configuration is latched from PORT0
after a dur ation of 8 TCL / 4 CPU cloc ks (6 TCL / 3
CPU clocks if PLL is bypassed) and in case of
exter nal fetch, ALE, RD and
R/W
pins are driven
to their inactive level. The MCU starts program
execution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Refer to
Table 38 for POR T0 latched configuration.
18.2 - Short Hardware Reset
A short hardware res et is a warm reset. It m ay be
generated synchronously to the CPU clock
(synchronous reset).
The short hardware is triggered when RSTIN
signal duration is shorter or equal to 1038
TC L, th e R PD pin must be pul l ed hi gh.
To proper ly activate the internal reset logic of the
MCU, the
RSTIN
pin must be held low, at least,
during 4 TCL (2 periods of CPU clock). The I/O
pins are set to high impedance and
RSTOUT
pin is
driven low. After
RSTIN
level is detected, a short
duration of 12 TCL (6 CPU clocks) maximum
elapses, during which pending internal hold states
are cancelled and the current internal access
cycle if any is completed. External bus cycle is
aborted. The internal pull-down of
RSTIN
pin is
activated if bit BDRSTEN of SYSCON register
was previously set by software. This bit is always
cleared on power-on or aft er any reset sequence.
The internal reset sequence starts for 1024 TCL
(512 periods of CPU clock).
After that duration the pull-down of RSTIN pin for
the bidi rectional reset function is released and the
RSTIN pin level is sampled high while RPD le v el is
high.
The short hardware reset ends and the MCU
restarts.To be processed as a short hardware
reset, the external RSTIN signal must last a
CPU Clo ck
RSTIN
RPD
RSTOUT
ALE
PORT0
Latching point of PORT0
for system start-up configuration
6 or 8 TCL1)
4 TCL 12 TCL
min. max.
1024 T CL
Reset Conf igurat ion
If VRPD > 2.5V Async hronous
200µA Discharge
3)
RD
432156789
Reset is not entered.
Internal res et si gnal
Internally pulled low 2)
5 TCL
ST10F269 18 - SY STEM RESET
117/184
ma ximum of 1038 TCL (4 T CL + 10 TCL + 10 24
TCL). The system configuration is latched from
PORT0 aft er a duration of 8 TCL / 4 CPU cloc ks (6
TCL / 3 CPU clocks if PLL is bypassed) and in
case of external fetch, ALE, RD a nd
R/W
pins are
driven to their inactive level. Program execution
starts from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timings
of synchronous reset sequence are summarized
in Figure 57. Refer to Table 38 for PORT0 latched
configuration.
No te - If th e
RSTIN
pin level is sampled low, the
reset sequence is extended until
RSTIN
level becomes high leading to a long
hardware reset (synchronous or
asynchronous reset) because RSTIN
signal duration has lasted longer than
1040TCL.
- If the VRPD voltage has dropped below
the RPD pin threshold, the reset is
pro cessed as an asynchronous reset.
Fi gure 57 : Synchronous Warm Reset Sequence External Fetch (4 TCL <
RSTIN pulse < 1038 TCL)
Not e 1) RSTIN assertion can be released there. 2) Maximum internal synchronization is 6 CPU cycles (12
TCL).
3) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
4) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU =f
XTAL / 2), else it is 4 C PU clock cycles ( 8 TCL) .
5) If durin g the res et cond ition ( RSTIN low), VRPD voltage drops be low the thresho ld voltag e (typic ally 2. 5V for 5 V operation), the
ST10 reset ci rcuitry disable s t he bi directional reset fu nction and RS TIN pin is no m ore pulled low.
18.3 - Software Reset
The reset sequence can be triggered at any time
using the protected instruction SRST (software
reset). This instruction can be executed
deliber ately within a program, for e xample to lea ve
bootstrap loader mode, or upon a hardware trap
that reveals a system fa ilure.
Upon execution of the SRST instruction, the
internal reset sequence (1024 TCL) is started.
The microcontroller beh avior is th e same a s for a
short hardware reset, except that only
P0.12...P0.6 bits are latched at the end of the
reset sequence, while previously latched values of
P0.5. ..P0.2 are cleared.
18.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during
the initialization or when it i s not regul arly s erviced
during progr am execution it will overflo w and it will
trigger the reset sequence.
Unlike hardware and software resets, the
watchdog reset completes a ru nning exter nal bus
cycle if this bus cycle either does not use READY,
or if READY is sampled active (low) after the
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0 1 st Ins tr .
Latching point of PORT0
for system start-up configuration
6 or 8 TCL4)
4 TCL 10 TCL 2)
min. min. 1024 T C L
1)
Reset Configuration
If VRPD > 2.5V Asynchronous
200µA Discharge
5)
RD
4321 56789
Reset is not ent ered.
Internal reset signal
Internally pulle d low 3)
5 TCL
18 - SYSTEM RE SET ST10F 269
118/184
programmed wait states. When READY is
sampled inactiv e (high) after the progr ammed wait
states the running external bus cycle is aborted.
Then the internal reset sequence (1024 TCL) is
started. The microcontroller behaviour is the
same as for a short hardware reset, except that
only P0.12...P0.6 bits are latched, while
previously latched values of P0.5...P0.2 are
cleared.
18.5 - RSTOUT, RSTI N , Bidirectional Reset
18.5.1 - RSTOUT Pin
The RST OUT pin is driven activ e (l ow level) at the
beginning of any reset sequence (synchronous/
asynchronous hardware, software and watchdog
timer resets). RSTOUT pin stays active low
beyond the end of the initialization routine, until
the protected EINIT instruction (End of
Initialization) is completed.
18.5.2 - Bidirectional Reset
The bidirectional reset function is enabled by
setting SYSCON.BDRSTEN (bit 3). This function
is disabled by any reset sequence which always
clears the SYSCON.BDRSTEN bit.
It can only be enabled during the initialization
routin e, be fore EIN I T ins truction is comple ted .
If VRPD voltage drops below the RPD pin
threshold (typically 2.5V for VDD = 5V) when
RSTIN pin is low or when RSTIN pin is internally
pulled low, the ST10 reset circuitry disables the
bidirectional reset function and RSTIN pin is no
more pulled low. The reset is processed as an
asynchronous rese t.
The bidirectional reset function is useful for
external peripherals with on-chip memory
because the reset signal output on RSTIN pin is
de-activated before the CPU starts its first
instruct i on f e tch.
18.5.3 - RSTIN pin
When the bidirectional reset function is enabled,
the open-drain of the RSTIN pin is activated,
pulling down the reset signal, for the duration of
the internal reset sequence. See Figure 56 and
Figure 57. At the end of the sequence the
pull-down is released and the RSTIN pin gets
back its input function.
The bidi rectional reset function can be used:
– to convert SW or WD resets to a hardware reset
so that the configuration can be (re-)latched
from PORT 0.
– to make vi sible SW or WDT resets a t RSTIN pin
whenever RSTIN is the only res et signal used by
the application (RSTOUT not used).
– to get a die-activated reset signal before CPU
starts its first instruction fetch.
The configuration latched from PORT0 is
determined by the kind of reset generated by the
application. (Refer to Table 38).
Converting a SW or WDT reset to a hardware
reset allows the PLL to re-lock or the PLL
configuration to be re-latched, provided a SW or
WDT reset is generated by the application
program is case of PLL unlock or input clock fail.
18.6 - Reset Ci rcuitry
The internal reset circuitry is described in
Figure 58.
An internal pull-up resistor is implemented on
RSTIN pin. (50kΩ minimum , to 250kΩ max imum) .
The minimum res et time must be calcul ated using
the lowest value. In addition, a programmable
pull-down (SYSCON.BDRSTEN bit 3) drives the
RSTIN pin according to the internal reset state.
The RSTOUT pin provides a signals to the
application. (Refer to Section 18.5 -).
A weak internal pull-down is connected to the
RPD pin to d ischarge exter nal cap ac itor to VSS at
a rate of 100µA to 200µA. This Pull-down is
turned on when RSTIN pin is low
If bit PWDCFG of SYSCON register is set, an
internal pull-up resistor is activated at the end of
the reset sequence. This pull-up charges the
cap acitor connected to RPD pin.
If the bidirectional reset function is not used, the
simplest way to reset ST10F269 is to connect
external components as shown in Figure 59. It
works with reset from application (hardware or
manual) and with power-on. The value of C1
capacitor, connected on RSTIN pin with internal
pull-up resistor (50kΩ to 250kΩ), must lead to a
charging time long enough to let the internal or
external oscillator and / or the on-chip PLL to
stabil ize.
The R0-C0 components on RPD pin are mainly
implement ed to pro vide a time delay to exit Po wer
down mode (see Chapter : Power Reduction
Modes on page 122). Nevertheless, they drive
RPD pin level during resets and they lead to
different reset modes as explained hereafter. On
power-on, C0 is total discharged, a low level on
RPD pin forces an asynchronous hardware reset.
C0 capacitor starts to charge through R0 and at
the end of reset sequence ST10F269 restarts.
RPD pin threshold is typically 2.5V.
ST10F269 18 - SY STEM RESET
119/184
Dependin g on the delay of the next applied reset,
the MCU can enter a synchronous reset or an
asynchronous reset. If RPD p in is below 2.5V an
asynchronous reset starts, if RPD pin is above
2.5V a synchronous reset starts. (See Section
18.1 - and Sect ion 18.2 -).
Note that an internal pull-down is connected to
RPD pin and can drive a 100µA to 200µA current.
This Pull-down is turned on when RSTIN pin is
low.
To properly use the bidirectional reset features,
the schematic (or equiv alent) of Figure 60 must be
implemented. R1-C1 only work for power-on or
manual reset in the same way as explained
previously. D1 diode brings a faster discharge of
C1 capacitor at power-off during repetitive
switch-on / switch-off sequences. D2 diode
performs an OR-wired connection, it can be
replaced with an open drain buffer. R2 resistor
may be added to increase the pull-up current to
the op en drain in o rder to get a faster rise time on
RSTIN pin when bidirectional func tion i s activated.
The start-up configurations and some system
features are selected on reset sequences as
desc ribed in Tabl e 38 and Tabl e 39.
Table 38 describes what is the system
configuration latched on PORT0 in the five
different reset ways. Table 39 summarizes the
state of bits of PORT0 latched in RP0H,
SYSCON, BU SC O N0 reg isters.
Fi gure 58 : Internal (simplified) Reset Circuitry.
RSTOUT
EINIT Instruction
Trigger
Clr
Clock
Reset State
Machine
Internal
Reset
Signal
Reset Sequence
(512 CPU Clock Cycles)
SRST instruction
watchdog overflow RSTIN
VDD
BDRSTEN
VDD
RPD
Weak pu ll-down
(~200µA)
From/to Ex it
Powerdown
Circuit
Asynchronous
Reset
Clr Q
Set
18 - SYSTEM RE SET ST10F 269
120/184
Fi gure 59 : Min imum Exte r n al Reset Ci r cuitry
Fi gure 60 : External Reset Hardware Circuitry
Table 38 : PORT0 Latched Configuration for the Different Resets
Notes: 1. Not latch ed from PORT0.
2. Onl y RP 0H low byte is used and t he bi t -field s are latched fro m PORT0 h i gh byt e t o RP0H low byt e.
X: Pin is sampled
-: Pin is not sampled
PORT0
Clock Options
Seem. Add. Lines
Chip Selects
WR confide.
Bus Typ e
Reserved
BSL
Reserved
Reserved
Adapt Mode
Emu Mode
Sample event
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
Software Reset - - -XXXXXXX- - - - - -
Watchdog Reset - - - X X X X X X X - - - - - -
Short Hardware Reset - - -XXXXXXXXXXXXX
Long Hardware Reset XXXXXXXXXXXXXXXX
Power-On Reset XXXXXXXXXXXXXXXX
Table 39 : PORT0 Bits Lat ched into t he Different Registers Aft er Reset
PORT0 bit
Nebr. h7 h6 h5 h4 h3 h2 h1 h0 I7 I6 I5 I4 I3 I2 I1 I0
PORT0 bit
Name CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU
RP0H 2X 1X 1X 1X 1X 1X 1X 1X 1CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
SYSCON X 1X 1X 1X 1X 1X 1BYTDIS 3X 1WRCFG 3X 1X 1X 1X 1X 1X 1X 1
BUSCON 0 X 1X 1X 1X 1-BUS
ACT0 4ALE
CTL0 4-BTYPBTYPX
1X 1X 1X 1X 1X 1
Internal
Logic To Clock G enerat or To P ort 4 Logic To Port 6 Logic X 1X 1X 1X 1Internal X 1X 1Internal Internal
+
+
RSTOUT
RSTIN
RPD
C0
R0
VDD
C1
External
Hardware
ST10F269
a) Manual hardware reset 1
b) For auto matic power-up and
a)b)
int er ru ptib le po w er-dow n mo de
D2
RSTOUT RSTIN
RPD
Open - drain
D1
+
C0
R0
VDD
ST10F269
VDD External
Hardware
Inverter
+C1
R1
VDD
Reset Source
External
R2
19 - POWER REDUCTION MODE S ST10F269
122/184
19 - POWER REDUCTI ON MODES
Two different power reduction modes wit h different
level s of power reduction have been imp lement ed
in the ST10F269. In Idle mode only CPU is
stopped, while peripheral still operate. In Power
Down mode both CPU and peripherals are
stopped.
Both mode are software activated by a protected
instructi on and are terminated in diff erent wa ys as
desc ribed in the follo wing secti ons.
Note: All external bus actions are completed
before Idle or Power Down mode is
entered. However, Idle or Power Down
mode i s not entered if READY is enabled,
bu t has n ot been activated (driven low for
negative polarity, or driven high for
positive polarity) during the last bus
access.
19.1 - Idle Mo de
Idle mode is entered by running IDLE protected
instructi on. The CPU operation is stopped and the
peripherals still run.
Idle mode is terminate by any interrupt request.
Whatever the interrupt is serviced or not, the
instruction following the IDLE instruction will be
executed after return from interrupt (RETI)
instruction, then the CPU resumes the normal
program.
Note that a PEC transfer keep the CPU in Idle
mode. If the PEC transfer does not succeed, the
Idle mode is term inated. Watc hdog timer must be
properly programmed to avoid any disturbance
during Idle mode.
19.2 - Power Down Mode
Power Down mode starts by running PWRDN
pro tected i nstr uc tion. Inter nal c lock is s topped, al l
MCU parts are on hold including the watchdog
timer.
There are two different operating Power Down
modes: protected mode and interruptible mode.
The internal RAM contents can be preserved
through the voltage supplied via the VDD pins. To
verify RAM integrity, some dedicated patterns
may be written before entering the Power Down
mode and have to be checked after Power Down
is resumed.
It is mandatory to keep VDD = +5 V ±10% dur in g
power-down mode, because the on-chip
voltage regulator is turned in power saving
mod e and it delivers 2.5V to the core lo gic, but
it must be supplied at nominal VDD = +5V.
19.2.1 - Protected Powe r Down Mode
This mode is selected when PWDCFG (bit 5) of
SYSCON register is cleared. The Protected
Power Down mode is on ly activated if the NMI pin
is pulled low when executing PWRDN instruction
(this means that the PWRD in str uction belo ngs t o
the NMI software routine). This mode is only
deactivated with an external hardware reset on
RSTIN pin.
Note: During power down the on-chip voltage
regulator automatically lowers the internal
logic supply voltage to 2.5V, to save power
and to keep internal RAM and registers
contents.
19.2.2 - Interruptible Power Down Mode
This mode is selected when PWDCFG (bit 5) of
SYSCON register is set (See Chapter : Special
Funct ion Register Overv iew on page 125).
The Interruptible Power Down mode is only
activated if all the enabled Fast Ex ternal I nterrupt
pins are in their inactive level (see EXICON
register descri ption below).
This mode is deactivated with an external reset
applied to RSTIN pin or with an interrupt request
applied to one of the Fast External Interrupt p ins.
To allow the internal PLL and clock to stabilize,
the RSTIN pin must be held low according
the recommendations described in Chapter :
System Reset on page 114.
EXICON (F1C0h / E0h ESFR Reset Value: 0000h
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
ST10F269 19 - POWER R EDUCTION MODE S
123/184
EXxIN inputs are normally sampled interrupt
inputs. However, the Power Down mode circuitry
use s them as level-s ensitive input s.
An EXxIN (x = 3...0) Interrupt Enable bit (bit
CCxIE in respective CCxIC register) need not be
set to bring the device out of Power Down mode.
An external RC circuit must be connected t o RP D
pin, as shown in the Figure 61.
To exit Power Down mode with an external
interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40ns.
This signal enables the internal oscillator and PLL
circuitry, and also turns on the weak pull-down
(see Figure 62).
The discharge of the e xternal capaci tor provides a
delay that allows the oscillator and PLL circuits to
stabilize before the internal CPU and Peripheral
clocks are enabled. When the RPD voltage drops
below the threshold voltage (about 2.5V), the
Schmitt trigger clears Q2 flip-flop, thus enabling
the CPU and Peripheral clocks, and the device
resumes code execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the
respective CCxIC register) before entering Power
Down mode, the device executes the interrupt
ser v i ce rout ine, and the n resum es execution a fter
the PWRDN instruction (see note below).
If the interrupt was disabled, the device executes
the instruction following PWRDN instruction, and
the Interrupt Request Flag (bit CCxIR in the
respective CCxIC register) remains set until it is
cleared by software.
Note: Due to the internal pipeline, the
instruction that follows the PWRDN
instruction is executed before the CPU
performs a call of the interrupt service
routine when exiting power-down m ode
0 1: Interr upt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active leve l)
1 0: Interrupt on negative edge (falling)
Enter Po wer Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1: Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
Fi gure 6 1 : External R0C0 Circuit on RPD Pin For
Exiting Powerdown Mode with External Interrupt
RPD
VDD
C0
R0
220kΩ mi nim um
1µF Typical
ST10F269-Q3
+
19 - POWER REDUCTION MODE S ST10F269
124/184
Fi gure 62 : Simplified Powerdown Exit Circuitry
Fi gure 63 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2)
DQ
Q
VDD
enter cd
external
interrupt
reset
stop pll
stop oscillator
VDD
DQ
Q
cd Syste m clock
CPU and Peripherals cl ocks
RPD
VDD Pull-up
Weak Pull-down
(~ 200µA)
PowerDown
Q1
Q2
CPU clk
Internal
External
RPD
ExitPwrd
XTAL1
Interrupt
(internal)
~ 2.5 V
delay for oscillato r/pll
stabilization
signal
Powerdown
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
125/184
20 - SPECIAL FUNCTION REGISTER OVERVIEW
The following table lists all SFRs which are
implemented in the ST10F269 in alphabetical
order. Bit-addressable SFRs are marked with the
letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with
the letter “E” in column “Physical Address”.
A SFR can be specified by its individual
mnemonic name. Depending on the selected
addressing mode, a SFR can be accessed via its
physical address (using the Data Page Pointers),
or via its short 8-bit address (without using the
Data Page Pointers).
The reset value is defined as following:
X : Means the full nibble is not defined at reset.
x : Means some bits of the nibble are not
defined at reset.
Table 40 : Special Function Regist ers Listed by Name
Name Physical
address 8-bit
address Description Reset
value
ADCIC b FF98h CCh A/D Converter end of Conversion Interrupt Control Register - - 00h
ADCON b FFA0h D0h A/D Converter Control Register 0000h
ADDAT FEA0h 50h A/D Converter Result Register 0000h
ADDAT2 F0A0h E 50h A/D Conv erter 2 Result Register 0000h
ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h
ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h
ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h
ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h
ADEIC b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Register - - 00h
BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0xx0h
BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h
BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h
BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h
BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h
CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h
CC0 FE80h 40h CAPCOM Register 0 0000h
CC0IC b FF78h BCh CAPCOM Register 0 Interrupt Control Register - - 00h
CC1 FE82h 41h CAPCOM Register 1 0000h
CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register - - 00h
CC2 FE84h 42h CAPCOM Register 2 0000h
CC2IC b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register - - 00h
CC3 FE86h 43h CAPCOM Register 3 0000h
CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register - - 00h
CC4 FE88h 44h CAPCOM Register 4 0000h
CC4IC b FF80h C0h CAPCOM Register 4 Interrupt Control Register - - 00h
CC5 FE8Ah 45h CAPCOM Register 5 0000h
CC5IC b FF82h C1h CAPCOM Register 5 Interrupt Control Register - - 00h
CC6 FE8Ch 46h CAPCOM Register 6 0000h
CC6IC b FF84h C2h CAPCOM Register 6 Interrupt Control Register - - 00h
CC7 FE8Eh 47h CAPCOM Register 7 0000h
CC7IC b FF86h C3h CAPCOM Register 7 Interrupt Control Register - - 00h
CC8 FE90h 48h CAPCOM Register 8 0000h
CC8IC b FF88h C4h CAPCOM Register 8 Interrupt Control Register - - 00h
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
126/184
CC9 FE92h 49h CAPCOM Register 9 0000h
CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register - - 00h
CC10 FE94h 4Ah CAPCOM Register 10 0000h
CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register - - 00h
CC11 FE96h 4Bh CAPCOM Register 11 0000h
CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register - - 00h
CC12 FE98h 4Ch CAPCOM Register 12 0000h
CC12IC b FF90h C8h CAPCOM Register 12 Interrupt Control Register - - 00h
CC13 FE9Ah 4Dh CAPCOM Register 13 0000h
CC13IC b FF92h C9h CAPCOM Register 13 Interrupt Control Register - - 00h
CC14 FE9Ch 4Eh CAPCOM Register 14 0000h
CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control Register - - 00h
CC15 FE9Eh 4Fh CAPCOM Register 15 0000h
CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control Register - - 00h
CC16 FE60h 30h CAPCOM Register 16 0000h
CC16IC b F160h E B0h CAPCOM Register 16 Interrupt Control Register - - 00h
CC17 FE62h 31h CAPCOM Register 17 0000h
CC17IC b F162h E B1h CAPCOM Register 17 Interrupt Control Register - - 00h
CC18 FE64h 32h CAPCOM Register 18 0000h
CC18IC b F164h E B2h CAPCOM Register 18 Interrupt Control Register - - 00h
CC19 FE66h 33h CAPCOM Register 19 0000h
CC19IC b F166h E B3h CAPCOM Register 19 Interrupt Control Register - - 00h
CC20 FE68h 34h CAPCOM Register 20 0000h
CC20IC b F168h E B4h CAPCOM Register 20 Interrupt Control Register - - 00h
CC21 FE6Ah 35h CAPCOM Register 21 0000h
CC21IC b F16Ah E B5h CAPCOM Register 21 Interrupt Control Register - - 00h
CC22 FE6Ch 36h CAPCOM Register 22 0000h
CC22IC b F16Ch E B6h CAPCOM Register 22 Interrupt Control Register - - 00h
CC23 FE6Eh 37h CAPCOM Register 23 0000h
CC23IC b F16Eh E B7h CAPCOM Register 23 Interrupt Control Register - - 00h
CC24 FE70h 38h CAPCOM Register 24 0000h
CC24IC b F170h E B8h CAPCOM Register 24 Interrupt Control Register - - 00h
CC25 FE72h 39h CAPCOM Register 25 0000h
CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register - - 00h
CC26 FE74h 3Ah CAPCOM Register 26 0000h
CC26IC b F174h E BAh CAPCOM Register 26 Interrupt Control Register - - 00h
CC27 FE76h 3Bh CAPCOM Register 27 0000h
CC27IC b F176h E BBh CAPCOM Register 27 Interrupt Control Register - - 00h
CC28 FE78h 3Ch CAPCOM Register 28 0000h
CC28IC b F178h E BCh CAPCOM Register 28 Interrupt Control Register - - 00h
CC29 FE7Ah 3Dh CAPCOM Register 29 0000h
CC29IC b F184h E C2h CAPCOM Register 29 Interrupt Control Register - - 00h
Table 40 : Special Function Regist ers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
127/184
CC30 FE7Ch 3Eh CAPCOM Register 30 0000h
CC30IC b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register - - 00h
CC31 FE7Eh 3Fh CAPCOM Register 31 0000h
CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register - - 00h
CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h
CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h
CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h
CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h
CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h
CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h
CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h
CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h
CP FE10h 08h CPU Context Pointer Register FC00h
CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register - - 00h
CSP FE08h 04h CPU Code Segment Pointer Register (read only) 0000h
DP0L b F100h E 80h P0L Direction Control Register - - 00h
DP0H b F102h E 81h P0h Direction Control Register - - 00h
DP1L b F104h E 82h P1L Direction Control Register - - 00h
DP1H b F106h E 83h P1h Direction Control Register - - 00h
DP2 b FFC2h E1h Port 2 Direction Control Register 0000h
DP3 b FFC6h E3h Port 3 Direction Control Register 0000h
DP4 b FFCAh E5h Port 4 Direction Control Register 00h
DP6 b FFCEh E7h Port 6 Direction Control Register 00h
DP7 b FFD2h E9h Port 7 Direction Control Register 00h
DP8 b FFD6h EBh Port 8 Direction Control Register 00h
DPP0 FE00h 00h CPU Data P a ge Pointer 0 Register (10-bit) 0000h
DPP1 FE02h 01h CPU Data P a ge Pointer 1 Register (10-bit) 0001h
DPP2 FE04h 02h CPU Data P a ge Pointer 2 Register (10-bit) 0002h
DPP3 FE06h 03h CPU Data P a ge Pointer 3 Register (10-bit) 0003h
EXICON b F1C0h E E0h External Interrupt Control Register 0000h
EXISEL b F1DAh E EDh External Interrupt Source Selection Register 0000h
IDCHIP F07Ch E 3Eh Device Identifier Register (n is the device revision) 10Dnh
IDMANUF F07Eh E 3Fh Manufacturer Identifier Register 0401h
IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 3040h
IDPROG F078h E 3Ch Programming Voltage Identifier Register 0040h
IDX0 b FF08h 84h MAC Unit Address Pointer 0 0000h
IDX1 b FF0Ah 85h MAC Unit Address Po inter 1 0000h
MAH FE5Eh 2Fh MA C Unit Accumulator - High Word 0000h
MAL FE5Ch 2Eh MAC Unit Accumulator - Low Word 0000h
MCW b FFDCh EEh MAC Unit Control Word 0000h
MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h
MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h
Table 40 : Special Function Regist ers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
128/184
MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h
MRW b FFDAh EDh MAC Unit Repeat Word 0000h
MSW b FFDEh EFh MAC Unit Status Word 0200h
ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h
ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h
ODP4 b F1CAh E E5h Port 4 Open Drain Control Register - - 00h
ODP6 b F1CEh E E7h Port 6 Open Drain Control Register - - 00h
ODP7 b F1D2h E E9h Port 7 Open Drain Control Register - - 00h
ODP8 b F1D6h E EBh Port 8 Open Drain Control Register - - 00h
ONES b FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh
P0L b FF00h 80h PORT0 Low Register (Lower half of PORT0) - - 00h
P0H b FF02h 81h PORT0 High Register (Upper half of PORT0) - - 00h
P1L b FF04h 82h PORT1 Low Register (Lower half of PORT1) - - 00h
P1H b FF06h 83h PORT1 High Register (Upper half of PORT1) - - 00h
P2 b FFC0h E0h Port 2 Register 0000h
P3 b FFC4h E2h Port 3 Register 0000h
P4 b FFC8h E4h Port 4 Register (8-bit) 00h
P5 b FFA2h D1h Port 5 Register (read only) XXXXh
P6 b FFCCh E6h Port 6 Register (8-bit) - - 00h
P7 b FFD0h E8h Port 7 Register (8-bit) - - 00h
P8 b FFD4h EAh Port 8 Register (8-bit) - - 00h
P5DIDIS b FFA4h D2h Port 5 Digital Disable Register 0000h
POCON0L F080h E 40h PORT0 Low Outpout Control Register (8-bit) - - 00h
POCON0H F082h E 41h PORT0 High Output Control Register (8-bit) - - 00h
POCON1L F084h E 42h PORT1 Low Output Control Register (8-bit) - - 00h
POCON1H F086h E 43h PORT1 High Output Control Register (8-bit) - - 00h
POCON2 F088h E 44h Port2 Output Control Register 0000h
POCON3 F08Ah E 45h Port3 Output Control Register 0000h
POCON4 F08Ch E 46h Port4 Output Control Register (8-bit) - - 00h
POCON6 F08Eh E 47h Port6 Output Control Register (8-bit) - - 00h
POCON7 F090h E 48h Port7 Output Control Register (8-bit) - - 00h
POCON8 F092h E 49h Port8 Output Control Register (8-bit) - - 00h
POCON20 F0AAh E 55h ALE, RD, WR Output Control Register (8-bit) 0000h
PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h
PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h
PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h
PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h
PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h
PECC5 FECAh 65h PEC Channel 5 Control Register 0000h
PECC6 FECCh 66h PEC Channel 6 Control Register 0000h
PECC7 FECEh 67h PEC Channel 7 Control Register 0000h
PICON b F1C4h E E2h Port Input Threshold Control Register - - 00h
Table 40 : Special Function Regist ers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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PP0 F038h E 1Ch PWM Module Period Register 0 0000h
PP1 F03Ah E 1Dh PWM Module Period Register 1 0000h
PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h
PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h
PSW b FF10h 88h CPU Program Status Word 0000h
PT0 F030h E 18h PWM Module Up/Down Counter 0 0000h
PT1 F032h E 19h PWM Module Up/Down Counter 1 0000h
PT2 F034h E 1Ah PWM Module Up/Down Counter 2 0000h
PT3 F036h E 1Bh PWM Module Up/Down Counter 3 0000h
PW0 FE30h 18h PWM Module Pulse Width Register 0 0000h
PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h
PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h
PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h
PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h
PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h
PWMIC b F17Eh E BFh PWM Module Interrupt Control Register - - 00h
QR0 F004h E 02h MAC Unit Offset Register QR0 0000h
QR1 F006h E 03h MAC Unit Offset Register QR1 0000h
QX0 F000h E 00h MAC Unit Offset Register QX0 0000h
QX1 F002h E 01h MAC Unit Offset Register QX1 0000h
RP0H b F108h E 84h System Start-up Configuration Register (read only) - - XXh
S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h
S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h
S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register - - 00h
S0RBUF FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) - - XXh
S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register - - 00h
S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register - - 00h
S0TBUF FEB0h 58h Serial Channel 0 Transmit Buffer Register (write only) 0000h
S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register - - 00h
SP FE12h 09h CPU System Stack Pointer Register FC00h
SSCBR F0B4h E 5Ah SSC Baud Rate Register 0000h
SSCCON b FFB2h D9h SSC Control Register 0000h
SSCEIC b FF76h BBh SSC Error Interrupt Control Register - - 00h
SSCRB F0B2h E 59h SSC Receive Buffer (read only) XXXXh
SSCRIC b FF74h BAh SSC Receive Interrupt Control Register - - 00h
SSCTB F0B0h E 58h SSC Transmit Buffer (write only) 0000h
SSCTIC b FF72h B9h SSC Transmit Interrupt Control Register - - 00h
STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h
STKUN FE16h 0Bh CPU Stac k Underflow Pointer Register FC00h
SYSCON b FF12h 89h CPU System Configuration Register 0xx0h 1
T0 FE50h 28h CAPCOM Timer 0 Register 0000h
T01CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h
Table 40 : Special Function Regist ers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
130/184
Notes: 1. T he system configuration i s s el ected du ring re set.
2. Bit WDTR ind i cates a watchdog t imer trig gered reset.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled
interrupt request s may be generat ed by settin g t he XPnIR bits (of XP nI C r egi s ter) of the unused X-p eriph eral node s.
T0IC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register - - 00h
T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h
T1 FE52h 29h CAPCOM Timer 1 Register 0000h
T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register - - 00h
T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h
T2 FE40h 20h GPT1 Timer 2 Register 0000h
T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h
T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register - - 00h
T3 FE42h 21h GPT1 Timer 3 Register 0000h
T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h
T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register - - 00h
T4 FE44h 22h GPT1 Timer 4 Register 0000h
T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h
T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register - - 00h
T5 FE46h 23h GPT2 Timer 5 Register 0000h
T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h
T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register - - 00h
T6 FE48h 24h GPT2 Timer 6 Register 0000h
T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h
T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register - - 00h
T7 F050h E 28h CAPCOM Timer 7 Register 0000h
T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h
T7IC b F17Ah E BEh CAPCOM Timer 7 Interrupt Control Register - - 00h
T7REL F054h E 2Ah CAPCOM Timer 7 Reload Register 0000h
T8 F052h E 29h CAPCOM Timer 8 Register 0000h
T8IC b F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register - - 00h
T8REL F056h E 2Bh CAPCOM Timer 8 Reload Register 0000h
TFR b FFACh D6h Trap Flag Register 0000h
WDT FEAEh 57h Watchdog Timer Register (read only) 0000h
WDTCON b FFAEh D7h Watchdog Timer Control Register 00xxh 2
XP0IC b F186h E C3h CAN1 Module Interrupt Control Register - - 00h 3
XP1IC b F18Eh E C7h CAN2 Module Interrupt Control Register - - 00h 3
XP2IC b F196h E CBh Flash ready/busy interrupt control register - - 00h 3
XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register - - 00h 3
XPERCON F024h E 12h XPER Configuration Register - - 05h
ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h
Table 40 : Special Function Regist ers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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20.1 - I dentificat i on Regist ers
The ST10F269 has four Identification registers,
mapp ed in ESFR space. These registers contain:
– A ma nufacturer identifier,
– A chip identifier, with its revision,
– A internal memory and size identifier and pro-
gramming vol tage description.
Note: 256K and 128K versions of ST10F269 have
the same IDME M corresponding to 256K.
Both versions are based on the sam e device with
the only difference that the two upper banks of
Flash are no t tested o n 128K versions. Therefore,
there is no way to detect by software if a device is
a 128K version or a 256K vers ion .
IDMANUF (F07Eh / 3Fh) 1ESFR Reset Value: 0401h
IDCHIP (F07Ch / 3Eh) 1ESF R Reset Value: 10DXh
IDME M (F07Ah / 3Dh) 1ESFR Reset Value: 3040h
IDPROG (F078h / 3Ch) 1ESFR Reset Value: 0040h
Note : 1. All i dentification words are read only re gi st ers.
1514131211109876543210
MANUF 00001
R
MANUF Manufacturer Identifier - 020h: STMicroelectronics Manufacturer (JTAG worldwide
normalization).
1514131211109876543210
CHIPID REVID
RR
REVID Device Revision I dentifier
CHIPID Devi ce Identifier - 10Dh: ST10F269 identifier.
15 14131211109876543210
MEMTYP MEMSIZE
RR
MEMSIZE Inter nal Me mo ry Size is calculated using the following form ula:
Size = 4 x [MEMS IZE] (in K Byte) - 040h for ST10 F269 (256K Byte)
MEMTYP Inte r nal Memory Type - 3h fo r ST10F269 (Flash memory).
1514131211109876543210
PROGVPP PROGVDD
RR
PROGVDD Program ming VDD Voltage
VDD vol tag e when programming EPROM or FLASH devices is calculated using the
following formu la: VDD = 20 x [PROGVDD] / 2 56 (volts) - 40h for ST10F 269 (5V).
PROGVPP Pro gram ming VPP Voltage (no need of exter na l VPP) - 0 0 h
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
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20.2 - System Configuration Registers
The ST10F269 has registers used for different configuration of the overall system. These registers are
desc ribed belo w.
SYSCON (FF12h / 89h) SF R Reset Value: 0xx0h
Notes: 1. T hese bit are set direct l y or i ndirectly accordin g to PORT0 and EA pi n configuration d uring r eset sequence.
2. Register SYSCON cannot b e changed after execution of the EINIT instruction.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG PWD
CFG OWD
DIS BDR
STEN XPEN VISIBLE XPER-
SHARE
RW RW RW RW1RW1RW RW1RW RW RW RW RW RW RW
XPER-SHARE XBUS Peripheral Share Mode Control
‘0’: External accesses to XBUS peripherals are disabled
‘1’: XBUS peripherals are accessible via the external bus during hold mode
VISIBLE Vis ible Mode Control
‘0’: Accesses to XBUS peripherals are done internally
‘1’: XBUS peripheral accesses are made visible on the external pins
XPEN XBUS Peripheral Enable bit
‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled
‘1’: The on-chip X-Peripherals are enabled.
BDRSTEN Bidirectional Reset Enable
‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin)
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
OWDDIS Oscillator Watchdog Disable Control
‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If
there is no activity on XTAL1 for at least 1 µs, the CPU clock is switched automatically to PLL’s
base frequency (from 2 to 10MHz).
‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The
PLL is turned off to reduce power supply current.
PWDCFG Power Down Mode Configuration Control
‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low,
otherwise the instruction has no effect. Exit power down only with reset.
‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin or with external reset.
CSCFG Chip Select Configuration Control
‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE.
WRCFG Write Configuration Control (Inverted copy of bit WRC of RP0H)
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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BU SCON 0 (FF0Ch / 86h) SFR Reset Value: 0xx0h
BU SCON1 (FF1 4h / 8Ah ) SFR Reset Value: 0000h
BU SCON2 (FF1 6h / 8Bh ) SFR Reset Value: 0000h
BU SCON3 (FF1 8h / 8Ch ) SFR Reset Value: 0000h
‘0’: Pins WR and BHE retain their normal function
‘1’: Pin WR acts as WRL, pin BHE acts as WRH.
CLKEN System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled: pin may be used for general purpose I/O
‘1’: CLKOUT enabled: pin outputs the system clock signal.
BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width)
‘0’: Pin BHE enabled
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
ROMEN Internal Memory Enable (Set according to pin EA during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
SGTDIS Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
ROMS1 Internal Memory Mapping
‘0’: Internal Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Memory area mapped to segment 1 (01’0000H...01’7FFFH).
STKSZ System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN0 CSREN0 RDYPOL0 RDYEN0 - BU S ACT0 ALE CT L0 - BTYP MTTC0 RWDC0 MCTC
RW RW RW RW RW2RW2RW1RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 - BTYP MTTC1 RWDC1 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - BTYP MTTC2 RWDC2 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN3 CSREN3 RDYPOL3 RDYEN3 - BUSACT3 ALECTL3 - BTYP MTTC3 RWDC3 MCTC
RW RW RW RW RW RW RW RW RW RW
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
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BU SCON4 (FF1 Ah / 8Dh) SFR Reset Value: 0000h
Notes: 1. BTYP (b it 6 and 7) are set according to the configuration of the bi t l6 and l7 of PORT0 la tc hed at the end o f t he reset sequence.
2. BUSC ON0 is in itialize d wit h 0000h, if EA pin is high dur ing re set. If EA p in i s low duri ng reset , bit BU S ACT0 and A LECTRL0 are
set ( ’1 ’ ) and bit fiel d BT Y P is l oaded with the bus c onfigu rat i on select ed via PORT0.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 - BTYP MTTC4 RWDC4 MCTC
RW RW RW RW RW RW RW RW RW RW
MCTC Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0: 15 wait states (Nber = 15 - [MCTC])
. . .
1 1 1 1: No wait state
RWDCx Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
MTTCx Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
BTYP Exte rnal Bus Config urati o n
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset.
ALECTLx ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
BUSACTx Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see
ADDRSEL)
RDYENx READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
RDYPOLx Ready Active Level Control
‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on
READY pin,
‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on
READY pin.
CSRENx Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
CSWENx Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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RP0H (F108h / 84h) ESFR Reset Value: --XXH
Not es: 1. RP0H .7 to R P0H .5 bi ts a re l oade d only dur ing a lo ng hardwa re res et. As pu ll-up r esist ors ar e ac tive on e ach Por t P0H pins
during reset, RP 0H default value i s "F F h".
2. These bi ts are set acco rdi ng to Port 0 configuration during any reset sequence.
3. RP 0H is a read only regi ster.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- CLKSEL SALSEL CSSEL WRC
R 1 - 2 R 2R 2R 2
WRC 2Write Configuration Control
‘0’: Pin WR acts as WRL, pin B HE acts as WRH
‘1’: Pins WR and BHE retain their normal function
CSSEL 2Chip Select Line Selection (Number of active CS outputs)
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS line at all
1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)
SALSEL 2Segment Address Line Selection (Number of active segment address outputs)
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 8-bit segment address: A23...A16
1 1: 2-bit segment address: A17...A16 (Default without pull-downs)
CLKSEL 1 - 2 System Clock Selection
000: fCPU = 2.5 x fOSC
001: fCPU = 0.5 x fOSC
010: fCPU = 1.5 x fOSC
011: fCPU = fOSC
100: fCPU = 5 x fOSC
101: fCPU = 2 x fOSC
110: fCPU = 3 x fOSC
111: fCPU = 4 x fOSC
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
136/184
EXICON (F1C0h / E0h ESFR Reset Value: 0000h
EXISEL (F1DAh / EDh) ESFR Reset Value: 0000h
XP 3 I C (F 19 Eh / CF h) 1ESFR Reset Value: --00h
Note: 1 . XP3I C register has the same bit field as xxIC inte rrup t re gis te rs
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1: Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
1 0: Interrupt on negative edge (falling)
Enter Po wer Do wn mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1: Interrupt on any edge (rising or falling)
Always enter P o wer Down mode, exit if EXxIN level changed.
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’: Input from Port 2 pin ANDed with “alternate source”.
EXIxSS Port 2 pin Alternate Source
0P2.8 CAN1_RxD
1P2.9 CAN2_RxD
2P2.10 RTCSI
3P2.11 RTCAI
4...7 P2.12...15 Not used (zero)
1514131211109876543210
--------XP3IR XP3IE XP3ILVL GLVL
RW RW RW RW
ST10F 269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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xxIC (yyyyh / zzh) SFR Area Reset Value: --00h
XPERCON (F02 4h / 12h ) ESFR Res et Value: --05h
1514131211109876543210
--------xxIR xxIE ILVL GLVL
RW RW RW RW
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
1514131211109876543210
-----------
RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN
RW RW RW RW RW
CAN1EN CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XPeripher al and its functions are disabled. P4.5 and P4.6 pins can be
used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if
CAN2EN is also ‘0’.
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XPeripher al and its functions are disabled. P4.4 and P4.7 pins can be
used as general purpose I/Os. Address r ange 00’EE00h-00’EEFFh is only directed to external memory if
CAN1EN is also ‘0’.
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1EN XRAM1 Enable Bit
‘0’: Accesses to external memory within space 00’E000h to 00’E7FFh. The 2K Bytes of internal XRAM1
are disabled.
’1’: Accesses to the internal 2K Bytes of XRAM1.
XRAM2EN XRAM2 Enable Bit
‘0’: Accesses to the external memory within space 00’C000h to 00’DFFFh. The 8K Bytes of internal
XRAM2 are disabled.
’1’: Accesses to the internal 8K Bytes of XRAM2.
RTCEN RTC Enable Bit
’0’: Accesses to the on-chip Real Time Clock are disabled, external access performed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ’0’ also
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
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When both CAN are disabled via XPERCON
setting, then any access in the address range
00’EE00h - 00’EFFFh will be directed to external
memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register. P4.4 and P4.7 can be used as General
Purpose I/O when CAN2 is not enabled, and P4.5
and P4.6 can be used as General Purpose I/O
when CAN1 is not enabled.
The default XPER selection after Reset is
identical to XBUS configuration of ST10C167:
XCAN1 is enabled, XCAN2 is disabled, XRAM1
(2K Byte compatible XRAM) is enabled, XRAM2
(new 8K Byte XRAM) is disabled.
Register XPERCON cannot b e changed after the
global enabling of XPeripherals, i.e. after setting of
bit XPEN in SYSCO N register.
In EMUlation mode, all the XPERipherals are
enabled (XPERCON bit are all set).
W hen the Real Time Clock is disable d (RT CEN =
0), the clock oscillator is switch off if ST10 enters
in power-down mode. Otherwise, when the Real
Time Clock is enabled, the bit RTCOFF of the
RTCCON register allows to choose the
power-do wn mode of the clock oscillator.
’1’: The on-chip Real Time Clock is enabled and can be accessed.
ST10F269 21 - ELECTRICAL CHARACTERISTICS
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21 - ELECTRICAL CHARACTERISTICS
21.1 - Absolute Maximu m Ratings
Note: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this sp ecification is not implied. Exposure t o absolute maximum ra ting condition s for ex tended periods may affect device relia bility.
Dur ing overload condition s (VIN > VDD or VIN < VSS) t he volt ag e on p ins wi th r espe ct to gr ou nd (VSS) must not exceed the values
defined by the Absolu te Ma ximum Rat in gs.
21.2 - Parameter Interpretation
The parameters listed in the following tables represent the characteristics of the ST10F269 and its
demands on the system. Where the ST10F269 logic provides signals with their respective timing
cha racteristics, the symbol “CC” for Controller Characteristics, is included in the “Sym bol” column.
Where the external system must provide signals with their respective timing characteristics to the
ST 10F2 69, the symbol “SR” fo r System R equirement , is included in the “Symbol” column.
21.3 - DC Characteristics
VDD = 5V ± 10%, VSS = 0V , Reset active, fCPU = 4 0MHz with TA = -40 to + 125°C (PQFP144 de vic es) or
fCPU = 32MHz with TA = -40 to + 125°C (TQF P 144 devices)
Symbol Parameter Value Unit
VDD Voltage on VDD pins with respect to ground1-0.5, +6.5 V
VIO Voltage on any pin with respect to ground1-0.5, (VDD +0.5) V
VAREF Voltage on VAREF pin with respect to ground1-0.3, (VDD +0.3) V
IOV Input Current on any pin during overload condition1-10, +10 mA
ITOV Absolute Sum of all input currents during overload condition1|100| mA
Ptot Power Dissipation11.5 W
TAAmbient Temperature under bias -40, +125 °C
Tstg Storage Temperature1-65, +150 °C
Symbol Parameter Test
Conditions Min. Max. Unit
VIL SR Input low voltage – -0.5 0.2 VDD -0.1 V
VILS SR Input low voltage (special threshold) – -0.5 2.0 V
VIH SR Input high voltage
(all except RSTIN and XTAL1) –0.2 VDD +
0.9 VDD + 0.5 V
VIH1 SR Input high voltage RSTIN –0.6 VDD VDD + 0.5 V
VIH2 SR Input high voltage XTAL1 – 0.7 VDD VDD + 0.5 V
VIHS SR Input high voltage (special threshold) – 0.8 VDD
-0.2 VDD + 0.5 V
HYS Input Hysteresis (special threshold) 3– 250 – mV
VOL CC Output low voltage (PORT0, PORT1, Port 4,
ALE, RD, WR , BHE, CLKOUT, RSTOUT)1IOL = 2.4mA –0.45V
21 - ELECTRICAL CHARACTERISTICS ST10F269
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VOL1 CC Output low voltage (all other outputs) 1IOL1 = 1.6mA –0.45V
VOH CC Output high voltage (PORT0, PORT1, Port4,
ALE, RD, WR , BHE, CLKOUT, RSTOUT)1IOH = -500µA
IOH = -2.4mA 0.9 VDD
2.4 –
–V
VOH1 CC Output high voltage (all other outputs) 1/2 IOH = – 250µA
IOH = – 1.6mA 0.9 VDD
2.4 –
–V
V
IOZ1
CC Input leakage current (Port 5) 0V < VIN < VDD – 200 nA
IOZ2
CC Input leakage current (all other) 0V < VIN < VDD –1µA
IOV
SR Overload current 3/4 –5mA
RRST CC RSTIN pull-up resistor 3–50 250 kΩ
IRWH Read / Write inactive current 5/6 VOUT = 2.4V –-40µA
IRWL Read / Write active current 5/7 VOUT = VOLmax -500 – µA
IALEL ALE inactive current 5/6 VOUT = VOLmax 40 – µA
IALEH ALE active current 5/7 VOUT = 2.4V – 500 µA
IP6H Port 6 inactive current 5/6 VOUT = 2.4V –-40µA
IP6L Port 6 active current 5/7 VOUT = VOL1max -500 – µA
IP0H PORT0 configuration current
5/6 VIN = VIHmin –-10µA
IP0L 5/7 VIN = VILmax -100 – µA
IIL
CC XTAL1 input current 0V < VIN < VDD –20µA
gm On-chip oscillator transconductance 35-mA/V
CIO CC Pin capacitance (digital inputs / outputs) 3/5 f = 1MHz,
TA = 25°C –10pF
ICC Power supply current (PQFP144 devices) 8RSTIN = VIH1
fCPU in [MHz] –20 + 2.5 x fCPU mA
Power supply current (TQFP144 devices) – 20 + 2.3 x fCPU mA
IID Idle mode supply current 9RSTIN = VIH1
fCPU in [MHz] –20 + fCPU mA
IPD Power-down mode supply current
10 VDD = 5.5V
TA = 25°C
TA = 85°C
TA = 125°C
–
_
_
15 11
50 11
190 11
µA
µA
µA
Symbol Parameter Test
Conditions Min. Max. Unit
ST10F269 21 - ELECTRICAL CHARACTERISTICS
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Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These
low -noise drive rs deli ver th ei r max i m um current o n ly until the respe ct i ve tar get out put level is reached. After this, the out put curre nt
is reduced. T hi s results in increased im pedan ce of t he driver, which attenuates el ectric al noise from the c onnecte d PCB tracks. The
current sp ecified i n colu m n “T est Co ndi tions” is del i vered in any cas es.
2. This specification is not valid for outputs whic h are switc hed to o pen dr ain mod e. In t his c ase th e r espective out put will float and the
vol ta ge resul t s fr om the external circuitr y.
3. Partially tested, guaranteed by des ign characterization.
4. Ov erload conditions occur if the s tandard operating conditions are ex ceeded, i.e. th e voltage on any pin exceeds the specified
range (i.e. VOV > VDD+0.5V or VOV < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The
supply voltage must remain within the specified limits.
5. This s pecification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for
CS output and i f their open drain function is not enabled .
6. The max i m um current may be drawn while the respect i ve signal l i ne r em ai ns inactive.
7. The mini m um current must be drawn i n order to dr i ve the respe ct i ve signal l i ne active .
8. The powe r sup pl y curren t is a f unct ion of the operating frequency. Th is dep enden cy i s illustrated i n Figur e 65 an d Figur e 65. These
param eters are tested at VDDmax and 40MHz (or 32M Hz) CPU clock with al l out puts disconnected and all i nputs at VIL or VI H. T he
chi p is con f igured wi th a demu ltip lex ed 16- bit bus , dire ct cloc k drive , 5 chip se lect lines a nd 2 segmen t ad dress lin es , EA pin is low
during reset. After reset, PORT 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15
wait- states, R/W dela y, memory tristate wait state, normal ALE. Peripherals are not activated.
9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 65. These
parameters are tested at VDDm ax and 40MHz (or 32MH z) CPU clock with all outputs di sconnec ted and all i nputs at VIL or VIH.
10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0V to 0.1V or at
VDD – 0.1V to VDD, VREF = 0V, all outputs (including pins co nfigured as outp uts) disconnect ed.
11. Typical IPD value is 5µA @ TA=25° C, 20µA @ TA=85°C and 60µA @ TA=125°C.
12. P artially tested, guarant eed by des i gn charact eri zation using 22pF l oading capacitors on crystal pins.
IPD2 Power-down mode supply current (Real time
clock enabled, oscillator enabled)
10
12 VDD = 5.5V
TA = 55°C
fOSC = 25MHz –2 + fOSC / 4 mA
Symbol Parameter Test
Conditions Min. Max. Unit
21 - ELECTRICAL CHARACTERISTICS ST10F269
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Fi gure 64 : Supply / Idle Current as a Function of Operating Frequency (PQFP144 devices)
I [mA]
fCPU [MHz]
10
20
100
10
ICCtyp
IIDmax
ICCmax
IIDtyp
0
0
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40
30
60mA
120mA
00
0
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0
ST10F269 21 - ELECTRICAL CHARACTERISTICS
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Fi gure 65 : Supply / Idle Current as a Function of Operating Frequency (TQFP144 devices)
I [mA]
f
CPU
[MHz]
10
100
50
I
CCtyp
I
IDmax
I
CCmax
I
IDtyp
0
0
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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
20
52mA
93.6mA
00
0
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030
0
ST10F269
144/184
21.3.1 - A/D Converter Ch aracteristics
VDD = 5V ± 10%, VSS = 0 V
,
TA = -40 to +85 °C or -40 to +125°C, 4 .0V
≤
VAREF ≤
VDD + 0.1V; VSS0. 1V ≤
VAGND ≤
VSS + 0. 2V
Notes: 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectiv ely.
2. During the tS sample time the input capacitance Cain can be charged/di scharged by the external source. The internal resistanc e of
the analog source must al l ow t he capacitance to reach i ts final volt age level within the tS sample time. After the end of the tS sample
time, c hanges of the a nalog inp ut voltage have no effect on the conversion result. Values for th e tSC samp le clock depend on the
programming. Referring to the tC conversion time formula of Section 21.3.2 - ‘Conversion Timing Control’ on page 145 and to
Table 4 2 on page 145:
- tS min. = 2 tSC min. = 2 tCC min. = 2 x 24 x TCL = 48 TC L
- tS max = 2 tSC max = 2 x 8 tCC m ax = 2 x 8 x 96 TCL = 1536 T CL
TCL is defined i n S ection 21. 4.2 -, Section 21.4.4 -, an d Sectio n 21.4.5 - ‘Di rect Dri ve’ on page 149:
3. The conversion time formula is:
- tC = 14 tCC + tS + 4 TCL (= 14 tCC + 2 t SC + 4 TCL)
The tC parameter includes the tS sam ple time, the t ime for determ ining the dig ital resul t and the t ime to load th e result reg ister with
the result of th e conversion. Values for the tCC conver si on clock de pend on the programmi ng. Referri ng to Table 42 on page 145:
- tC min. = 14 tCC min. + tS min. + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
- tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 T CL + 1536 TCL + 4 TCL = 288 4 T CL
4. T his parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at VAREF =5.0V,
VAGND =0V, V
CC = 4.9V. It is guaranteed by design characterization for all other
voltages within th e define d voltage range.
‘LSB’ has a value of VAREF / 1024.
The specified TUE is guaranteed only if an overload condition (see
I
OV specification) occurs on maximum 2 not selected analog input
pins and the abs ol ute sum of i nput overload curr ent s o n all analog input pins does no t exc eed 10m A.
6. Th e coup lin g factor is measur ed on a c hanne l w hil e an overl oad c ondi tion oc curs on t he adj acen t no t selec ted c hannel w ith an
absol ute overlo ad current less tha n 10mA.
7. Par t i al l y tes ted, gua ranteed by de si gn characteri zation.
8.To remove noi se and undesirable high freq uency c om ponents from the analog input sig nal, a l ow-pass fi l ter must be connected at
the A DC in put. The c ut -off frequency of t hi s fil t er shoul d avoid 2 opposite transi tions during the ts sam pling t i m e of the ST10 ADC:
- fcut-off
≤
1 / 5 ts t o 1/10 ts
where ts is th e samplin g time of the S T 10 ADC and is not re l ated to the Nyqui st fr equency determined by the tc conversion time .
Table 41 : A/D Converter Characteristics
Symbol Parameter Test Condition Limit Values Unit
minimum maximum
VAREF SR Analog Reference voltage 4.0 VDD + 0.1 V
VAIN SR Analog input voltage 1 - 8 VAGND VAREF V
IAREF CC Reference supp ly current
running mode
power-down mode
7–
–500
1µA
µA
CAIN CC ADC input capacitanc e
Not sampling
Sampling
7–
–10
15 pF
pF
tSCC Sample time 2 - 4 48 TCL 1 536 TCL
tCCC Conversion time 3 - 4 388 TCL 2 884 TCL
DNL CC Differential Nonlinearity 5-0.5 +0.5 LSB
INL CC Integral Nonlinearity 5-1.5 +1.5 LSB
OFS CC Offset Error 5-1.0 +1.0 LSB
TUE CC Total unadjusted error 5-2.0 +2.0 LSB
RASRC SR Internal resistance of analog source tS in [ns] 2 - 7 –(t
S / 150) - 0.25 kΩ
K CC Coupling Factor between inputs 6 - 7 –1/500
ST10F269
145/184
21.3.2 - Conv ersion Timin g Control
When a conversion is started, first the
capacitances of the converter are loaded via the
respective analog input pin to the current analog
input v oltage. The time to load the capacitances is
referred to as the sample time ts. Next the
sample d voltage is conver ted to a digital value in
10 successive steps, which correspond to the
10-bit re solution of the ADC. The next 4 st eps are
used f o r equali zing internal le v els (and ar e kept f or
exact timing matching with the 10-bit A/D
converter module implement ed in the ST10F168).
The current that has to be drawn from the sources
for sampling and changing charges depends on
the tim e that each res pect ive step takes, bec ause
the capacito rs must reach their final voltage leve l
within the given time, at least with a certain
approximation. The maximum current, however,
that a source can deliver, depends on its internal
resistance.
The sample time tS (= 2 tSC) and the conversion
time tc (= 14 tCC + 2 tSC + 4 TCL) can be
programmed relatively to the ST10F269 CPU
clock. This allows adjusting the A/D converter of
the ST10F 269 to the properties of the sy stem:
Fast Conversion can be achieved by
programming the respective times to their
absolute possible minimum. This is preferable for
scanning high frequency signals. The internal
resistance of analog source and analog supply
must be sufficiently low, however.
High Internal Resistance can be achieved by
programming the respective times to a higher
value , or the possible maximum. This is preferable
when using analog sources and s uppl y with a high
intern al resistance in order to keep the current as
low as possible. However the conversion rate in
this case may be considerabl y lower.
The conversion times are programmed via the
upper four bit of regist er ADCON. Bit field ADCTC
(conversion time control) selects the basic
conversion clock tCC, used for the 14 steps of
conv erting. The sample time tS is a multiple of this
conversion time and is selected by bit field
ADSTC (sample time control). The table below
lists the possible combinations. The timings refer
to the unit TCL, where fCPU = 1/2T CL.
A compl ete conversion will take 14
t
CC + 2 t SC + 4 TCL (fastest conversion rate = 4.85µs at 40MHz). This
time includes the conversion itself, the sample time and the time required to transfer the digital value to
the result register.
Table 42 : ADC Sampling and Conversion Timing (PQFP 144 devices)
ADCTC
Conversion Clock tCC
ADSTC
Sample Clock tSC
TCL = 1/2 x fXTAL At fCPU = 40MHz tSC = At f CPU = 40MHz
and ADCTC = 00
00 TCL x 24 0.3µs00 t
CC 0.3µs
01 Reserved, do not use Reserved 01 tCC x 2 0.6µs
10 TCL x 96 1.2 µs10t
CC x 4 1.2µs
11 TCL x 48 0.6 µs11t
CC x 8 2.4µs
ST10F269
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A complete conversion will take 14
t
CC + 2 tSC + 4 TCL (fastest convert ion rate = 6.06µs at 32MHz). This
time includes the conversion itself, the sample time and the time required to transfer the digital value to
the result register.
21.4 - AC characteristics
21.4.1 - Test Wavefo rms
21.4.2 - Definition of Internal Timing
The internal operation of the ST10F269 is
controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for
example pipeline) or external (for example bus
cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
Table 43 : ADC Sampl ing and Conversion Timing (TQFP 144 devic es)
ADCON.15/14
ADCTC
Conversion Clock tCC
ADCON.13/12
ADSTC
Sample Clock tSC
TCL = 1/2 x fXTAL At fCPU = 32MHz tSC = At f CPU = 32MHz
and ADCTC = 00
00 TCL x 24 0.375µs00 t
CC 0.375µs
01 Reserved, do not use Reserved 01 tCC x 2 0.75µs
10 TCL x 96 1.5 µs10t
CC x 4 1.50µs
11 TCL x 48 0.75 µs11t
CC x 8 3.00µs
Fi gure 66 : Input / Output Waveforms
Fi gure 67 : Float Wav e f or ms
2.4V
0.45V
Test Points
0.2VDD+0.9 0.2VDD+0.9
0.2VDD-0.1 0.2VDD-0.1
A
C inputs during test ing are driven at 2.4V f or a logic ‘1’ and 0. 4V f or a logic ‘0’.
T
iming measurem ent s are made at V IH min f or a logic ‘1’ and VIL max for a logic ‘0’ .
Timing
Reference
Points
VLoad +0.1V
VLoad -0.1V
VOH -0.1V
VOL +0.1V
VLoad
VOL
VOH
F or timing purposes a port pin is no longer floating when VLOAD changes of ±10 0mV.
It begins to float when a 100m V change from the loaded VOH/VOL level occur s ( IOH/IOL = 20mA).
ST10F269
147/184
between two consecutiv e edges of the CPU clock,
called “TCL”.
The CPU clock signal can be generated by
different mechanism s. The duration of TCL and its
variation (and also the derived external timing)
depends on the mechanism used to generate
fCPU.
This influen ce must be rega rded when c alcul ating
the t imings for the ST10F269.
The example for PLL operation shown in
Figure 68 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins
P0.15-13 (P 0H.7-5).
Fi gure 68 : Generation Mechanisms for the CPU Clock
0
0
0
0
0
0
0
0
0
TCL TCL
0
0
0
0
0
0
0
0
0
TCL TCL
fCPU
fXTAL
fCPU
fXTAL
Phase locked loop operation
Direct Clock D rive
0
0
0
00
00
00
00
00
00
TCL TCL
fCPU
fXTAL
Prescaler Operation
ST10F269
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21.4.3 - Clock Generation Modes
The Table 44 associates the combinations of these three bits with the r espective clock generation mode.
Notes: 1. The ex t ernal clock input rang e refers to a CPU cloc k range of 1. .. 40MHz.
2. The max i m um i nput frequency depends on t he d ut y cycle of the external cloc k si gnal.
3. Th e maximum inpu t freq uency is 25MHz when u sing an ex terna l cry stal with the int ernal osc illa tor; pro vidin g that internal serial
resista nce of the crystal is less than 40Ω. However, hi gher fr equenci es can be appl i ed with an extern al clock sourc e on pi n XTAL 1,
but in this cas e, th e in put clock signal must reach the defined le vels VIL and VIH2..
.
Notes: 1. The ex t ernal clock input rang e refers to a CPU cloc k range of 1. .. 32MHz.
2. The max i m um i nput frequency depends on t he d ut y cycle of the external cloc k si gnal.
3. Th e maximum inpu t freq uency is 32MHz when u sing an ex terna l cry stal with the int ernal osc illa tor; pro vidin g that internal serial
resista nce of the crystal is less than 40Ω. However, hi gher fr equenci es can be appl i ed with an extern al clock sourc e on pi n XTAL 1,
but in this cas e, th e in put clock signal must reach the defined le vels VIL and VIH2..
Table 44 : CPU Frequency Generation (PQFP144 devices)
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1Notes
111 fXTAL x 4 2.5 to 10MHz Default configuration
110 fXTAL x 3 3.33 to 13.33MHz
101 fXTAL x 2 5 to 20MHz
100 fXTAL x 5 2 to 8MHz
011 fXTAL x 1 1 to 40MHz Direct drive2
010 fXTAL x 1.5 6.66 to 26.66MHz
001 fXTAL x 0.5 2 to 80MHz CPU clock via prescaler3
000 fXTAL x 2.5 4 to 16MHz
Table 45 : CPU Frequency Generation (TQFP144 devices)
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1Notes
111 fXTAL x 4 2.5 to 8MHz Default configuration
110 fXTAL x 3 3.33 to 10.67MHz
101 fXTAL x 2 5 to 16MHz
100 fXTAL x 5 2 to 6.4MHz
011 fXTAL x 1 1 to 32MHz Direct drive2
010 fXTAL x 1.5 6.67 to 21.33MHz
001 fXTAL x 0.5 2 to 64MHz CPU clock via prescaler3
000 fXTAL x 2.5 4 to 12.8MHz
ST10F269
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21.4.4 - Prescaler Operation
W hen pins P 0.15-13 (P0H.7-5) equal ’001’ duri ng
reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2: 1 presc aler.
The frequency of fCPU is half the frequency of
fXTAL and the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the
perio d of the input clock fXTAL.
The timings listed in the AC Characteristics that
refer to TCL therefore ca n be calculated using the
period o f fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
21.4.5 - Direct Drive
W hen pins P 0.15-13 (P0H.7-5) equal ’011’ duri ng
reset the on-chip phase locked loop is disabled
and the CPU clock is directly driven from the
internal oscillator with the input clock signal.
The frequency of fCPU directly follows the
frequenc y of fXTAL so the hi gh and low t ime of fCPU
(i.e. the duration of an individual TCL) is defined
by the duty cycle of the input clock fXTAL.
Therefore, t he tim ings given in this chapt er refer to
the minimum TCL. This minimum value can be
calculated by the following formula:
For two consecutive TCLs, the deviation caused
by the d uty c ycle of fXTAL is compens ated, so the
duration of 2TCL is always 1/fXTAL.
The minimum value TCLmin has to be used only
once for timings that require an odd number of
TCLs (1,3,...). Timings that require an even
number of TCLs (2,4,...) may us e the formula:
Note: The address float timings in Multiplexed
bus mode (t11 and t45) use the maximum
duration of TCL (TCLmax = 1/fXTAL x
DCmax) instead of TCLmin.
If the bit OW DDIS in SYSCON register is
cleared, the PLL runs on its free-running
frequency and deliv ers the clock signal f or
the Oscillato r Watchdog. If bit OWDDIS is
set, then the PLL is switched off.
21.4.6 - Oscillator Watchdog (OWD)
An on-chip watchdog oscillator is implemented in
the ST10F269. This feature is used for safety
operation with external crystal oscillator (using
direct drive mode with or with out prescaler). This
watchdog oscillator operates as following:
The reset default configuration enables the
watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its
free-running frequency, and it increments the
watchdog counter. The PLL free-running
frequency is between 2 and 10MHz. On each
transition of external clock, the watchdog counter
is cleared. If an ext ernal clock failure occurs, then
the watchdog counter overflows (after 16 PLL
clock cycles).
The CPU clock signal will be sw itched to the PLL
free-running clock signal, and the oscillator
watchdog Interrupt Request (XP3INT) is flagged.
The CP U clock will not switch back to the external
clock even if a valid extern al clock exits on XTA L1
pin. Only a hardware reset can switch the CPU
clock source back to direct clock input.
When the OWD is disabled, the CPU clock is
always external oscillator clock and the PLL is
switched off to decrease consumption supply
current.
21.4.7 - Phase Locked Loop
For all other combinations of pins P0.15-13
(P0H.7-5) during reset the on-chip phase locked
loop is enabled and it pro vi des t he CP U cloc k (see
Table 44 and Table 45). The PLL multiplies the
input frequency by the factor F which is selected
via the combination of pins P 0.15-13 (f CPU = fXTAL
x F). With every F’th transition of fXTAL the PLL
circuit synchronizes the CPU clock to the input
clock. This synchronization is done smoothly, so
the CPU clock frequency does not change
abruptly.
Due to this adaptation to the input clock the
frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight va riation causes a jitter
of fCPU which also effects the duration of
individu al TCLs.
The timings listed in the AC Characteristics that
refer to TCLs therefore must be calculated using
the minimum TCL that is possible under the
respective circumstances.
TCLmin 1f⁄XTAL
l
x
l
DCmin
=
DC duty cycle=
2TCL 1 fXTAL
⁄=
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The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes fCPU to keep it
locked on fXTAL. The relative deviation of TCL is
the maximum when it is referred to one TCL
perio d. It decreases ac cording to the form ula and
to the Figure 69 given below . F or N pe ri od s of TC L
the minimum value is computed using the
correspon ding deviation DN:
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a period o f 3 TCL periods
(N = 3):
D3 = 4 - 3/15 = 3.8%
3TCLmin =3TCL
NOM x (1 - 3.8/100)
=3TCL
NOM x 0.962
3TCLmin = 36.075ns (at fCPU = 40MHz )
3TCLmin = 45.1ns (at fCPU = 32MHz)
This is especially important for bus cycles using
wait states and e.g. for the operation of timers,
serial interf aces, etc. F or al l slower operations and
longer periods (e.g. pulse train generation or
measurement, lower Baud rates, etc.) the
deviation caus ed by the PLL jitter is negligible.
21.4.8 - External Clock Drive XTAL1
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C (PQFP 144 devices)
Not es: 1. Theo retic al min imum . The real minim um value depends on the du ty cy cle o f the inpu t clock si gnal . 25MHz is the max imu m input
frequency when using an externa l cry sta l oscillator. However, 40MHz can be applied with an externa l clock source.
2. The i nput clock signal must reach the defined levels V IL and VIH2.
TCLMIN TCLNOM 1DN
100
-------------–
×
=
DN4N15)%[]⁄
–
(±
=
Fi gure 69 : Approxi m ated Maximum PLL Jitter
Parameter Symbol fCPU = fXTAL f
CPU = fXTAL / 2 fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5 Unit
min max min max min max
Oscillator period tOSC SR 25 1– 12.5 – 40 x N 100 x N ns
High time t1SR 10 2–5 2–10 2–ns
Low time t2SR 10 2–5 2–10 2–ns
Rise time t3SR – 3 2–3 2–3 2ns
Fall time t4SR – 3 2–3 2–3 2ns
3216
8
42
±1
±2
±3
±4
Max.jitter [%]
N
This approximated formula is valid f or
1 ≤ N ≤ 40 and 10MHz ≤ fCPU ≤ 40MHz
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VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C (TQFP1 44 devices)
1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 32MHz is t he maximum input frequency
when using an exter nal cry st al oscillator. However, 32MHz c an be appl i ed with an exte rnal clock source.
2. The inpu t c l ock si gnal must reach the define d levels VIL and VIH2.
Fi gure 70 : External Clock Drive XT AL1
21.4.9 - Memory Cycle Variables
The t ables below use three var iable s which are d erived from t he BUSCONx registe rs a nd represent the
special characteristics of the programmed memory cycle. The following table describes, how these
variables are to be computed.
Parameter Symbol fCPU = fXTAL f
CPU = fXTAL / 2 fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5 Unit
Minimum Maximum Minimum Maximum Minimum Maximum
Oscillator period tOSC SR 31.251– 15.625 – 31.25 x N – ns
High time t1SR 12.52–6.25
2– 12.52–ns
Low time t2SR 12.52–6.25
2– 12.52–ns
Rise time t3SR – 3.1252–1.56
2–3.125
2ns
Fall time t4SR – 3.1252–1.56
2–3.125
2ns
Description Symbol Values
ALE Extension tATCL x [ALECTL]
Memory Cycle Time wait states tC2TCL x (15 - [MCTC])
Memory Tri-state Time tF2TCL x (1 - [MTTC])
t1t3t4
VIL
t2tOSC
VIH2
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21.4.10 - M ultiplexed Bus
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +12 5°C , CL = 50pF,
ALE cyc le t ime = 6 T CL + 2 t A + tC + tF ( 75ns at 40MHz CPU clock without w ait states, PQFP144 devices).
Table 46 : Multiple xed Bus Characteristics (PQFP144 devices)
Symbol Parameter
Max. CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
t5CC ALE high time 4 + tA– TCL - 8.5 + tA–ns
t6CC Address setup to ALE 2 + tA– TCL - 10.5 + tA–ns
t7CC Address hold after ALE 14 + tA– TCL - 8.5 + tA–ns
t8CC ALE falling edge to RD, WR
(with RW-delay) 4 + tA– TCL - 8.5 + tA–ns
t9CC ALE falling edge to RD, WR (no
RW-delay) -8.5 + tA–-8.5 + t
A–ns
t10 CC Address float after RD, WR
(with RW-delay) 1–6 – 6ns
t11 CC Address float after RD, WR
(no RW-delay) 1–18.5 – TCL + 6ns
t12 CC RD, W R low time
(with RW-delay) 15.5 + tC– 2 TCL -9.5 + tC–ns
t13 CC RD, W R low time
(no RW-delay) 28 + tC– 3 TCL -9.5 + tC–ns
t14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2 TCL - 19 + tCns
t15 SR RD to valid data in
(no RW-delay) – 18.5 + tC– 3 TCL - 19 + tCns
t16 SR ALE low to valid data in – 18.5
+ tA + tC– 3 TCL - 19
+ tA + tCns
t17 SR Address/Unlatched CS to va lid
data in – 22 + 2tA +
tC
– 4 TCL - 28
+ 2tA + tCns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t19 SR Data float after RD 1–16.5 + t
F– 2 TCL - 8.5 + tFns
t22 CC Data valid to WR 10 + tC– 2 TCL -15 + tC–ns
t23 CC Data hold after WR 4 + tF– 2 TCL - 8.5 + tF–ns
t25 CC ALE rising edge after RD, WR 15 + tF– 2 TCL -10 + tF–ns
t27 CC Address/Unlatched CS hold
after RD, WR 10 + tF– 2 TCL -15 + tF–ns
t38 CC ALE falling edge to Latched CS -4 - tA10 - tA-4 - tA10 - tAns
t39 SR Latched CS low to Valid Data In – 18.5 + tC +
2tA
– 3 TCL - 19
+ tC + 2tAns
t40 CC Latched CS hold after RD, WR 27 + tF– 3 TCL - 10.5 + tF–ns
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Note: 1. Par tially tes ted, gua ranteed by de si gn characteri zation.
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C, CL
= 50pF ,
ALE cycl e time = 6 TCL + 2tA + tC + tF (187.5ns at
32MHz CP U clock without wait states).
Table 47 : Multi plex e d Bus Chara cteristics (TQFP144 devices)
t42 CC ALE fall. edge to RdCS, WrCS
(with RW delay) 7 + tA– T CL - 5.5+ tA–ns
t43 CC ALE fall. edge to RdCS, WrCS
(no RW delay) -5.5 + tA–-5.5 + t
A–ns
t44 CC Address float after RdCS,
WrCS (with RW delay) 1–0 – 0ns
t45 CC Address float after RdCS,
WrCS (no RW delay) 1–12.5 – TCLns
t46 SR RdCS to Valid Data In
(with RW delay) –4 + t
C– 2 TCL - 21 + tCns
t47 SR RdCS to Valid Data In
(no RW delay) – 16.5 + tC– 3 TCL - 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW delay) 15.5 + tC– 2 TCL - 9.5 + tC–ns
t49 CC RdCS, WrCS Low Time
(no RW delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t50 CC Data valid to WrCS 10 + tC– 2 TCL - 15+ tC–ns
t51 SR Data hold after RdCS 0– 0 –ns
t52 SR Data float after RdCS 1–16.5 + t
F– 2 TCL - 8.5+tFns
t54 CC Address hold after
RdCS, WrCS 6 + tF– 2 TCL - 19 + tF–ns
t56 CC Data hold after WrCS 6 + tF– 2 TCL - 19 + tF–ns
Table 46 : Multiple xed Bus Characteristics (PQFP144 devices)
Symbol Parameter
Max. CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
Symbol Parameter
Maximum CPU Clock =
32MHz Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
t5
CC ALE high time 5.625 + tA– TCL - 10 + tA–ns
t6
CC Address setup to ALE 0.625 + tA–TCL - 15+ tA–ns
t7
CC Address hold after ALE 15.625 + tA– TCL - 10 + tA–ns
t8
CC ALE falling edge to RD, WR
(with RW-delay) 5.625 + tA– TCL - 10 + tA–ns
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t9
CC ALE falling edge to RD , WR (no
RW-delay) -10 + tA–-10 + t
A–ns
t10
CC Address float after RD, WR
(with RW-delay) 1–6 – 6ns
t11
CC Address float after RD, WR
(no RW-delay) 1– 21.625 – TCL + 6 ns
t12
CC RD, W R low time
(with RW-delay) 21.25 + tC– 2TCL - 10 + tC–ns
t13
CC RD, W R low time
(no RW-delay) 36.875 + tC– 3TCL - 10 + tC–ns
t14
SR RD to valid data in
(with RW-delay) – 11.25 + tC– 2TCL - 20+ tCns
t15
SR RD to valid data in
(no RW-delay) – 26.875 + tC– 3TCL - 20+ tCns
t16
SR ALE low to valid data in – 26.875 + tA + tC– 3TCL - 20
+ tA + tCns
t17
SR Address/Unlatched CS to valid
data in – 32.5 + 2tA + tC– 4TCL - 30
+ 2tA + tCns
t18
SR Data hold after RD
rising edge 0– 0 –ns
t19
SR Data float after RD 1– 17.25 + tF– 2TCL - 14 + tFns
t22
CC Data valid to WR 11.25 + tC– 2TCL - 20 + tC–ns
t23
CC Data hold after WR 17.25 + tF– 2TCL - 14 + tF–ns
t25
CC ALE rising edge after RD, WR 17.25 + tF– 2TCL - 14 + tF–ns
t27
CC Address/Unlatched CS hold
after RD , WR 17.25 + tF– 2TCL - 14 + tF–ns
t38
CC ALE falling edge to Latched CS -4 - tA10 - tA-4 - tA10 - tAns
t39
SR Latched CS low to Valid Data In – 26.875 + tC + 2tA– 3TCL - 20
+ tC + 2tAns
t40
CC Latched CS hold after RD, WR 32.875 + tF– 3TCL - 14 + tF–ns
t42
CC ALE fall. edge to RdCS, WrCS
(with RW delay) 11.625 + tA–TCL - 4 + tA–ns
t43
CC ALE fall. edge to RdCS, WrCS
(no RW delay) -4 + tA–-4 + t
A–ns
Symbol Parameter
Maximum CPU Clock =
32MHz Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
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1. Part ially tested, guaranted by design charact erization.
t44
CC Address float after RdCS,
WrCS (with RW delay) 1–0 – 0ns
t45
CC Address float after RdCS,
WrCS (no RW delay) 1– 15.625 – TCL ns
t46
SR RdCS to Valid Data In
(with RW delay) – 7.25 + tC– 2TCL - 24 + tCns
t47
SR RdCS to Valid Data In
(no RW delay) – 22 .875 + tC– 3TCL - 24 + tCns
t48
CC RdCS, WrC S Low Time
(with RW delay) 21.25 + tC– 2TCL - 10 + tC–ns
t49
CC RdCS, WrC S Low Time
(no RW delay) 36.875 + tC– 3TCL - 10 + tC–ns
t50
CC Data valid to WrCS 17.25 + tC–2TCL - 14+ t
C–ns
t51
SR Data hold after RdCS 0– 0 –ns
t52
SR Data float after RdCS 1– 11.25 + tF– 2TCL - 20 + tFns
t54
CC Address hold after
RdCS, WrC S 11.25 + tF– 2TCL - 20 + tF–ns
t56
CC Data hold after WrCS 11.25 + tF– 2TCL - 20 + tF–ns
Symbol Parameter
Maximum CPU Clock =
32MHz Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
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Fi gure 71 : External Memory Cycle: Multipl exed Bus, With / Wit hout Read / Write Delay, Normal ALE
Data In
Data Out
Address
Address
t38
t10
Read Cycle
Write Cycle
t5t16
t39
t40
t25
t27
t18
t14
t22
t23
t12
t8
t8
t6m
t19
Address
t17
t6
t7
t9t11
t13
t15
t16
t12
t13
Address
t9
t17
t6
t27
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
Address/Data
RD
WR
WRL
BHE
WRH
Bus (P0)
Address/Data
Bus (P0)
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Fi gure 72 : External Memory Cycl e: Multiplexed Bus, With / Without Read / Write Delay, E xtended ALE
Data Out
Address
Data In
Address
Address
t5t16
t6t7
t39
t40
t14
t8t18
t23
t6
t27
t38
t10 t19
t25
t17
t9t11
t15 t12
t13
t8t10
t9t11
t12
t13
t22
t27
t17
t6
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
RD
WR
WRL
BHE
WRH
Address/Data
Bus (P0)
Address/Data
Bus (P0)
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Fi gure 73 : External Memory Cycle: Multipl exed Bus, With / Wit hout Read / Write Delay, Normal ALE,
Read / Write Chip Select
Read Cycle
Write Cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
Data In
Data Out
Address
Address
t44
t5t16 t25
t27
t51
t46
t50
t56
t48
t42
t42
t6
t52
Address
t17
t6
t7
t43 t45
t49
t47
t16
t48
t49
Address
t43
RdCSx
WrCSx
Address/Data
Bus (P0)
Address/Data
Bus (P0)
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Fi gure 74 : External Memory Cycl e: Multiplexed Bus, With / Without Read / Write Delay, E xtended ALE,
Read / Write Chip Select
Data Out
Address
Data In
Address
Address
t5t16
t6t7
t46
t42
t42
t50
t18
t56
t6
t54
t44 t19
t25
t17
t43 t45
t47
t48
t49
t49
t43
t48
t44
t45
Read Cycle
Write Cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
RdCSx
WrCSx
Address/Data
Bus (P0)
Address/Data
Bus (P0)
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21.4.11 - Demultiplexed Bus
VDD = 5 V ± 10 %, VSS = 0V, TA = -40 to +125°C, CL
= 50pF,
ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at
40MHz CP U clock without wait states), PQFP144
devices.
Table 48 : Demultiplexed Bus Characterist ics (PQFP1 44 device s)
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
t5CC ALE high time 4 + tA–TCL - 8.5 + t
A–ns
t6CC Address setup to ALE 2 + tA– TCL - 10.5 + tA–ns
t80 CC Address/Unlatched CS setup to
RD, WR
(with RW-delay)
16.5 + 2tA– 2 TCL - 8.5 + 2tA–ns
t81 CC Address/Unlatched CS setup to
RD, WR
(no RW-delay)
4 + 2tA– TCL - 8.5 + 2tA–ns
t12 CC RD, WR low time
(with RW-delay) 15.5 + tC– 2 TCL - 9.5 + tC–ns
t13 CC RD, WR low time
(no RW-delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2 TCL - 19 + tCns
t15 SR RD to valid data in
(no RW-delay) – 18.5 + tC– 3 TCL - 19 + tCns
t16 SR ALE low to valid data in – 18.5 + tA +
tC
–3 TCL - 19
+ tA + tCns
t17 SR Add ress/U nlatc hed C S to valid
data in –22 + 2t
A +
tC
–4 TCL - 28
+ 2tA + tCns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t20 SR Data float after RD rising edge
(with RW-delay) 1 3 – 16.5 + tF–2 TCL - 8.5
+ tF + 2tA 1 ns
t21 SR Data float after RD rising edge
(no RW-delay) 1 3 –4 + t
F–TCL - 8.5
+ tF + 2tA 1 ns
t22 CC Data valid to WR 10 + tC– 2 TCL - 15 + tC–ns
t24 CC Data hold after WR 4 + tF– TCL - 8.5 + tF–ns
t26 CC ALE rising edge after RD, W R -10 + tF– -10 + tF–ns
t28 CC Add ress/U nlatc hed C S hold
after RD, WR 20 (no tF)
-5 + tF
(tF > 0)
– 0 (no tF)
-5 + tF
(tF > 0)
–ns
t28h CC Address/U nlatc hed C S hold
after WRH -5 + tF–-5 + t
F–ns
t38 CC ALE falling edge to Latched CS -4 - tA6 - tA-4 - tA6 - tAns
t39 SR Latc hed C S low to Valid Data In – 18.5
+ tC + 2tA–3 TCL - 19
+ tC + 2tAns
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Notes: 1. RW-delay and tA re fer to the next follow i ng bus cycle.
2. R ead data are latched with the same clock ed ge that trigger s the address change and the rising RD edge. Therefore address
changes befor e th e end of R D ha ve no imp act on read cycl es.
3. Par t i al l y tes ted, gua ranteed by de si gn characteri zation.
VDD = 5V ± 10% , VSS = 0V, TA = -40 to +85°C, CL = 50pF,
ALE cycl e time = 4 TC L + 2tA + tC + tF ( 125ns at 32MHz CPU clock wi thout wait states) RW-delay and tA
ref er to the next followi ng b us cycle.
Table 49 : Demultiplexed Bus Characterist ics (TQFP144 devices)
t41 CC Latc hed C S hold after RD, WR 2 + t F– TCL - 10.5 + tF–ns
t82 CC Address setup to RdCS, Wr C S
(with RW-delay) 14.5 + 2tA– 2 TCL - 10.5 +
2tA–ns
t83 CC Address setup to RdCS, Wr C S
(no RW-delay) 2 + 2tA– TCL - 10.5 + 2tA–ns
t46 SR RdCS to Valid Data In
(with RW-delay) –4 + t
C– 2 TCL - 21 + tCns
t47 SR RdCS to Valid Data In
(no RW-delay) – 16.5 + tC– 3 TCL - 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW-delay) 15.5 + tC–2 TCL - 9.5
+ tC–ns
t49 CC RdCS, WrCS Low Time
(no RW-delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t50 CC Data valid to WrCS 10 + tC– 2 TCL - 15 + tC–ns
t51 SR Data hold after RdCS 0– 0 –ns
t53 SR Data float after RdCS
(with RW-delay) 3– 16.5 + tF– 2 TCL - 8.5 + tFns
t68 SR Data float after RdCS
(no RW-delay) 3–4 + t
F– TCL - 8.5 + tFns
t55 CC Address hold after
RdCS, WrCS -8.5 + tF– -8.5 + tF–ns
t57 CC Data hold after WrCS 2 + tF– TCL - 10.5 + tF–ns
Table 48 : Demultiplexed Bus Characterist ics (PQFP1 44 device s)
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
Symbol Parameter
Maximum CPU Clock =
32MHz Variable CPU Clock
1/2 TCL = 1 to 32MHz Unit
Minimum Maximum Minimum Maximum
t5CC ALE high time 5.625 + tA–TCL - 10+ t
A–ns
t6CC Address setup to ALE 0.625 + tA–TCL - 15+ t
A–ns
t80 CC Address/Unlatched CS setup
to RD, WR
(with RW-delay)
21.25 + 2tA– 2TCL - 10 + 2tA–ns
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t81 CC Address/Unlatched CS setup
to RD, WR
(no RW-delay)
5.625 + 2tA–TCL -10 + 2t
A–ns
t12 CC RD, W R low time
(with RW-delay) 21.25 + tC– 2TCL - 10 + tC–ns
t13 CC RD, W R low time
(no RW-delay) 36 .875 + tC– 3TCL - 10 + tC–ns
t14 SR RD to valid data in
(with RW-delay) – 11.25 + tC– 2TCL - 20 + tCns
t15 SR RD to valid data in
(no RW-delay) – 26.875 + tC– 3TCL - 20 + tCns
t16 SR ALE low to valid data in – 26.875 + tA +
tC–3TCL - 20
+ tA + tCns
t17 SR Address/Unlatched CS to
valid data in – 32.5 + 2tA +
tC– 4TCL - 30
+ 2tA + tCns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t20 SR Data float after RD rising
edge (with RW-delay)1 - 3 – 26 + tF– 2TCL - 14
+ tF + 2tA1ns
t21 SR Data float after RD rising
edge (no RW-delay) 1 - 3 – 5.625 + tF–TCL - 10
+ tF + 2tA1ns
t22 CC Data valid to WR 11.25 + tC– 2 TCL- 20 + tC–ns
t24 CC Data hold after WR 5.625 + tF–TCL - 10+ t
F–ns
t26 CC ALE rising edge after RD, WR -10 + tF– -10 + tF–ns
t28 CC Address/Unlatched CS hold
after RD, WR 20 (no tF)
-5 + tF
(tF > 0)
– 0 (no tF)
-5 + tF
(tF > 0)
–ns
t28h CC Address/Unlatched CS hold
after WRH -5 + tF–-5 + t
F–ns
t38 CC ALE falling edge to Latched
CS -4 - tA10 - tA-4 - tA10 - tAns
t39 SR Latched CS low to Valid Data
In – 26.875 + tC+
2tA– 3TCL - 20
+ tC + 2tAns
t41 CC Latched CS hold after RD,
WR 1.625 + tF–TCL - 14 + t
F–ns
t82 CC Address setup to RdCS,
WrCS
(with RW-delay)
17.25 + 2tA– 2TCL - 14 + 2tA–ns
t83 CC Address setup to RdCS,
WrCS
(no RW-delay)
1.625 + 2tA–TCL -14 + 2t
A–ns
t46 SR RdCS to Valid Data In
(with RW-delay) – 7.25 + tC– 2TCL - 24 + tCns
t47 SR RdCS to Valid Data In
(no RW-delay) – 22.875 + tC– 3TCL - 24 + tCns
Symbol Parameter
Maximum CPU Clock =
32MHz Variable CPU Clock
1/2 TCL = 1 to 32MHz Unit
Minimum Maximum Minimum Maximum
ST10F269
163/184
Notes: 1. RW-delay and tA re fer to the next follow i ng bus cycle.
2. R ead data are latched with the same clock ed ge that trigger s the address change and the rising RD edge. Therefore address
changes befor e th e end of R D ha ve no imp act on read cycl es.
3. Partia l l y tested, guaranteed by design characterization.
t48 CC RdCS, WrCS Low Time
(with RW-delay) 21.25 + tC– 2TCL - 10 + tC–ns
t49 CC RdCS, WrCS Low Time
(no RW-delay) 36.875 + tC– 3TCL - 10 + tC–ns
t50 CC Data valid to WrCS 17.25 + tC– 2TCL - 14 + tC–ns
t51 SR Data hold after RdCS 0– 0 –ns
t53 SR Data float after RdCS
(with RW-delay) 3– 21.25 + tF– 2TCL - 10 + tFns
t68 SR Data float after RdCS
(no RW-delay) 3–0 + t
F–TCL - 10 + t
Fns
t55 CC Address hold after
RdCS, WrCS -10 + tF– -10 + tF–ns
t57 CC Data hold after WrCS 1.625 + tF–TCL - 14 + t
F–ns
Symbol Parameter
Maximum CPU Clock =
32MHz Variable CPU Clock
1/2 TCL = 1 to 32MHz Unit
Minimum Maximum Minimum Maximum
ST10F269
164/184
Fi gure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE
Not e : 1 . Un -l a t ched CSx = t41u = t41 TCL =10.5 + tF.
Write Cycle
CLKOUT
ALE
A23-A16
A15-A0 (P1)
BHE
WR
WRL
WRH
Data In
Data Out
t38
t5t16
t39
t41
t18
t14
t22
t12
Address
t17
t13
t15
t12
t13
t21
t20
t81
t80
t26
t24
t17
t6
t41u
t6
t80
t81
t28 (or t28h)
CSx
Read Cycle
Data Bus (P0)
RD
1)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
ST10F269
165/184
Fi gure 76 : External Memory Cycle: Demultiplexed Bus, Wi th / Without Read / Write Delay, Extended
ALE
Address
t5t16
t39
t41
t14
t24
t6
t38
t20
t26
t17
t15
t12
t13
t12
t13
t22
Data In
t18
t21
t6
t17 t28
t28
Data Out
t80
t81
t80
t81
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
RD
WR
WRL
WRH
Data Bus (P0)
(D15-D8) D7-D 0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F269
166/184
Fi gure 77 : External Memory Cycle: Demultipl exed Bus, Wi th / Without Read / Write Delay, Normal ALE,
Read / Write Chip Select
Read Cycle
Write Cycle
CLKOUT
ALE
Data In
Data Out
t5t16
t51
t46
t50
t48
Address
t17
t49
t47
t48
t49
t68
t53
t83
t82
t26
t57
t55
t6
t82
t83
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F269
167/184
Fi gure 78 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read /
Wri te Chip S elec t
Address
t5t16
t46
t57
t6
t53
t26
t17
t47
t48
t49
t48
t49
t50
Data In
t51
t68
t55
Data Out
t82
t83
t82
t83
Read Cycle
Write Cycle
CLKOUT
ALE
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F269
168/184
21.4.12 - CLKOUT and READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF, PQFP1 44 devi ces
Notes: 1. T hese tim i ngs are given for test pur poses onl y, i n order to as sure rec ogniti on at a spec i fic clock ed ge.
2. Demultiplex ed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivat i ng REA DY.
The 2tA and tC re fer to th e next follow i ng bus cycle, tF refer s t o the current bus cyc l e.
Table 50 : CLKOUT and READY Characteristics (PQFP144 devices)
Symbol Parameter
Maximum CPU Clock
= 40 MHz Variable CPU Clock
1/2TCL = 1 to 40 MHz
Unit
Minimum Maximum Minimum Maximum
t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns
t30 CC CLKOUT high time 4 – TCL – 8.5 – ns
t31 CC CLKOUT low time 3 – TCL – 9.5 – ns
t32 CC CLKOUT rise time – 4 – 4 ns
t33 CC CLKOUT fall time – 4 – 4 ns
t34 CC CLKOUT rising edge to
ALE falling edge -2 + tA8 + tA-2 + tA8 + tAns
t35 SR Synchronous READY
setup time to CLKOUT 12.5 – 12.5 – ns
t36 SR Synchronous READY
hold time after CLKOUT 2– 2 –ns
t37 SR Asynchronous READY
low time 35 – 2TCL + 10 – ns
t58 SR Asynchronous READY
setup time 1) 12.5 – 12.5 – ns
t59 SR Asynchronous READY
hold time 1) 2– 2 –ns
t60 SR Async. READY hold time after
RD, WR high ( Demulti plexed
Bus) 2)
00 + 2tA + tC + tF
2)
0 TCL - 12.5
+ 2tA + t C + tF 2) ns
ST10F269
169/184
VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125 °C, CL = 50pF, TQFP 144 devices
Notes: 1. T hese tim i ngs are given for test pur poses onl y, i n order to as sure rec ogniti on at a spec i fic clock ed ge.
Note 2. Dem ultiplexed bus is the worst cas e. For multiplexed bus 2TCL are to be added to the maximum values . This adds e ven more time
for deactivat i ng REA DY.
The 2tA and tC re fer to th e next follow i ng bus cycle, tF refer s t o the current bus cyc l e.
Table 51 : CLKOUT and READY Character istics (TQ FP144 devices)
Symbol Parameter
Maximum CPU Clock
= 32MHz Variable CPU Clock
1/2TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
t29 CC CLKOUT cycle time 31.25 31.25 2TCL 2TCL ns
t30 CC CLKOUT high time 9.625 – TCL – 6 – ns
t31 CC CLKOUT low time 5. 625 – TCL – 10 – ns
t32 CC CLKOUT rise time – 4 – 4 ns
t33 CC CLKOUT fall time – 4 – 4 ns
t34 CC CLKOUT rising edge to
ALE falling edge -3 + tA+7 + tA-3 + tA+7 + tAns
t35 SR Synchronous READY
setup time to CLKOUT 14 – 14 – ns
t36 SR Synchronous READY
hold time after CLKOUT 4– 4 –ns
t37 SR Asynchronous READY
low time 45.25 – 2TCL + 14 – ns
t58 SR Asynchronous READY
setup time 1) 14 – 14 – ns
t59 SR Asynchronous READY
hold time 1) 4– 4 –ns
t60 SR Async. READY hold time after
RD, WR high ( Demulti plexed
Bus) 2)
00 + 2t
A
+ tC + tF 2 0 TCL - 15.625 +
2tA + tC + tF 2ns
ST10F269
170/184
Fi gure 79 : CLKOUT and READY
Notes: 1. Cy cl e a s pr ogrammed, incl udi ng MCTC wai t st ates (Example s hows 0 MCTC WS ).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this s amplin g point generates a READY controlle d wait stat e, READY samp led LOW at this sam pling
poin t t erminates the currently running bus cycle.
4. READY may be de activated i n response to the tr ai l i ng (risi ng) edge of the corresponding com m and (RD or WR ).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to
the command (see N ote 4)).
6. M ul tiplexed bus modes have a MUX wai t s tate adde d after a bus cycle, and an additio nal MTTC wai t st ate may be i nserted here.
F or a multiple x ed bu s wit h MTTC wait state this d ela y is 2 CLK OUT cycles, for a demultiple xed bus without MTTC wa it sta te this delay
is zero.
7. The next exte rnal bus cy cle may start here.
t30
t34
t35 t36 t35 t36
t58 t59 t58 t59
wait state
READY MU X / Tri-state 6)
t32 t33
t29
Runn ing cycle 1)
t31
t37
3) 3)
5)
t60 4)
6)
2)
7)
3) 3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY
ST10F269
171/184
21.4.13 - External Bus Arbitration
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +12 5°C, CL = 50pF (PQFP144 devices)
Note: 1. Par tially tes ted, gua ranteed by de si gn characteri zation
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +12 5°C, CL = 50pF (TQFP144 devices)
Note: 1. Par tially tes ted, gua ranteed by de si gn characteri zation
Symbol Parameter
Maximum CPU Clock
= 40 MHz Va riable CPU Clock
1/2TCL = 1 to 40 MHz
Unit
Minimum Maximum Minimum Maximum
t61 SR HOLD input setup time
to CLKOUT 15 – 15 – ns
t62 CC CLKOUT to HLDA high
or BREQ low delay – 12.5 – 12.5 ns
t63 CC CLKOUT to HLDA low
or BREQ high delay – 12.5 – 12.5 ns
t64 CC CSx release 1– 15 – 15 ns
t65 CC CSx drive -4 15 -4 15 ns
t66 CC Other signals release 1– 15 – 15 ns
t67 CC Other signals drive -4 15 -4 15 ns
Symbol Parameter
Maximum CPU Clock
= 32MHz Variable CPU Clock
1/2TCL = 1 to 32MHz Unit
Minimum Maximum Minimum Maximum
t61 SR HOLD input setup time
to CLKOUT 20 – 20 – ns
t62 CC CLKOUT to HLDA high
or BREQ low delay – 15.625 – 15.625 ns
t63 CC CLKOUT to HLDA low
or BREQ high delay – 15.625 – 15.625 ns
t64 CC CSx release 1–15 – 15ns
t65 CC CSx drive -4 15 -4 15 ns
t66 CC Other signals release 1–15 – 15ns
t67 CC Other signals drive -4 15 -4 15 ns
ST10F269
172/184
.
Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access.
2. T his is the first possibility fo r BREQ to bec ome active.
3. The CS outputs will be resistive high (pull-up) after t64.
Fi gure 80 : External Bus Arbitration (Releasing the Bus)
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)
ST10F269
173/184
Fi gure 81 : External Bus Arbitration (Regaini ng the Bus)
Notes: 1. This is the last chance for BREQ to t rigge r the indi cated regain-sequence. Even if B REQ is ac tivated earli er, the r egain-s equence
is initiated by HOLD going high. Please not e that HO LD may als o be d eac tiva t ed wi thout the ST10F269 requesting the bus.
2. The next ST10F 269 driven bus cycl e m ay st art here.
CLKOUT
HOLD
HLDA
Other
Signals
t62
CSx
(On P6.x)
t67
t62
1)
2)
t65
t61
BREQ
t63
t62
ST10F269
174/184
21.4.14 - High-Speed Synchrono us Seria l Interface (SSC) Timing
21.4.14.1 Master Mode
VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF (PQFP144 devices)
Note: 1. Timin g guaranteed by design.
The for mu la for SSC Clock Cycle time is: t300 = 4 TCL * (<SSCB R > + 1)
Where <SSCBR> represents the content of the SSC B aud rate register, taken as unsigned 16-bit i nteger.
VCC = 5V ±10%, VSS = 0V, CPU clock = 32MHz, TA = -40 to +125°C, CL = 50pF (TQFP 144 devices)
Symbol Parameter Maxim um Baud rate = 10M Baud
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t300 CC SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t301 CC SSC clock high time 40 – t300/2 - 10 –ns
t302 CC SSC clock low time 40 – t300/2 - 10 –ns
t303 CC SSC clock rise time – 10 – 10 ns
t304 CC SSC clock fall time – 10 – 10 ns
t305 CC Write data valid after shift edge – 15 – 15 ns
t306 CC Write data hold after shift edge 1-2 – -2 – ns
t307p SR Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
37.5 – 2TCL+12.5 – ns
t308p SR Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
50 – 4TCL – ns
t307 SR Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
25 – 2TCL – ns
t308 SR Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
0–0–ns
Symbol Parameter Maximum Baud rate=6.25MBd
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Symb
ol
Minimum Maximum Minimum Maximum
t310 SR SSC clock cycle time 125 – 8 TCL 262144 TCL t310
t311 SR SSC clock high time 52.5 – t310/2 - 10 –t311
t312 SR SSC clock low time 52.5 – t310/2 - 10 –t312
t313 SR SSC clock rise time – 10 – 10 t313
t314 SR SSC clock fall time – 10 – 10 t314
t315 CC Write data valid after shift edge – 45.25 – 2 TCL + 14 t315
t316 CC Write data hold after shift edge 0 – 0 – t316
t317p SR
Read data se tu p ti me be fore l atch edge,
phase error de tection on (SSCPE N = 1)
78.125 – 4TCL +
15.625 –t317p
t318p1SR
Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
109.375 – 6TCL +
15.625 –t318p1
t317 SR
Read data se tu p ti me be fore l atch edge,
phase error de tection off (SSCPEN = 0)
6–6–
t317
ST10F269
175/184
Note: 1. Timin g guaranteed by design.
The formula for SSC Clock Cycle ti me is : t300 = 4 TCL * (<SSCBR> + 1)
W here <SSC BR> represen ts the content of the SSC Baud rate register, taken as un signed 16-bit integer
Not es: 1. Th e pha se and po lar ity o f shif t an d la tch ed ge of SC LK is program ma ble. Th is figur e u ses the lea ding cl ock ed ge as shift edge
(dra wn in bold), with lat ch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low -to-high tra nsition (SSC PO =
0b).
2. The bi t timing is repeated for all bi t s to be transmitted or rec ei ved.
21.4.14.2 S lave mode
VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF (PQFP144 devices)
t318 SR
Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
41.25 – 2TCL + 10 – t318
Symbol Parameter Maximum Baud rate=6.25MBd
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Symb
ol
Minimum Maximum Minimum Maximum
Fi gure 82 : SSC Master Timing
t303
t304
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
t305
0
0
0
0
0
0
0
0
0
0
0
0
0
0
t305 t305
00
00
00
00
00
t306
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1st Ou t Bit Last O u t Bit2nd Out Bit
t300
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
t302
t301
1) 2)
t307
0
0
0
0
0
0
0
0
0
0
0
2nd.In Bit
0
0
00
0
0
000
0
00
0000
00
00
000
1st.In Bit
00
00
00
00
00
00
00
00
00
00
00
00
00
t308 t307
0
0
0
0
0
0
0
0
0
0
0
Last.In Bit
t308
SCLK
MTSR
MRST
Symbol Parameter
Maximum Baud rate=10MB d
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t310 SR SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t311 SR SSC clock high time 40 – t310/2 - 10 –ns
t312 SR SSC clock low time 40 – t310/2 - 10 –ns
t313 SR SSC clock rise time – 10 – 10 ns
t314 SR SSC clock fall time – 10 – 10 ns
t315 CC Write data valid after shift edge – 39 – 2 TCL + 14 ns
t316 CC Write data hold after shift edge 0 – 0 – ns
t317p SR Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
62 – 4TCL + 12 – ns
t318p1SR Read data hold time after latch edge,
phase error detection on
(SSCPEN = 1)
87 – 6TCL + 12 – ns
ST10F269
176/184
The for mu la for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCB R > + 1)
Where <SSCBR> represents the content of the SSC B aud rate register, taken as unsigned 16-bit i nteger.
VCC = 5V ±10%, VSS = 0V, CPU clock = 32MHz, TA = -40 to +125°C, CL = 50pF (TQFP144 devices)
The for mu la for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCB R > + 1)
W here <SSC BR> represen ts the content of the SSC Baud rate register, taken as un signed 16-bit integer
t317 SR Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
6–6–ns
t318 SR Read data hold time after latch edge,
phase error detection off
(SSCPEN = 0)
31 – 2TCL + 6 – ns
Symbol Parameter
Maximum Baud rate=10MB d
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
Symbol Parameter
Maximum Baud rate=6.25MBd
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t310 SR SSC clock cycle time 125 – 8 TCL 262144 TCL ns
t311 SR SSC clock high time 52.5 – t310/2 - 10 –ns
t312 SR SSC clock low time 52.5 – t310/2 - 10 –ns
t313 SR SSC clock rise time – 10 – 10 ns
t314 SR SSC clock fall time – 10 – 10 ns
t315 CC Write data valid after shift edge – 45.25 – 2 TCL + 14 ns
t316 CC Write data hold after shift edge 0 – 0 – ns
t317p SR
Read data se tu p ti me be fore l atch edge,
phase error de tection on (SSCPE N = 1)
78.125 – 4TCL +
15.625 –ns
t318p1SR
Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
109.375 – 6TCL +
15.625 –ns
t317 SR
Read data se tu p ti me be fore l atch edge,
phase error de tection off (SSCPEN = 0)
6–6–ns
t318 SR
Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
41.25 – 2TCL + 10 – ns
ST10F269
177/184
Not es: 1. Th e pha se and po lar ity o f shif t an d la tch ed ge of SC LK is program ma ble. Th is figur e u ses the lea ding cl ock ed ge as shift edge
(dra wn in bold), with latch on trailing edg e (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high tra nsition (SSC PO =
0b).
2. The bi t timing is repeated for all bi t s to be transmitted or rec ei ved.
Fi gure 83 : SSC Slave Timing
t313
t314
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
t315
0
0
0
0
0
0
0
0
0
0
0
0
0
0
t315 t315
0
0
0
0
0
0
t316
0
0
0
0
0
0
0
0
0
1st Out Bit Last Out Bit2nd Out Bit
t310
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
t312
t311
1) 2)
t317
0
0
0
0
0
0
00
00
00
00
00
00
2nd.In Bit1st.In Bit
00
00
00
00
00
00
00
00
00
00
00
00
00
00
t318 t317
0
0
0
0
0
0
0
0
0
0
0
0
Last.In Bit
t318
SCLK
MRST
MTSR
22 - PACKAGE MECHANICAL DATA ST10F269
178/184
22 - PACKAGE MECHANICAL DAT A
Note: 1. Packag e di m ensio ns are i n m m . T he di m ensions quoted in inches are rounded.
Fi gure 84 : Package Outline PQFP144 (28 x 28mm )
Dimensions Millimeters 1Inches (approx)
Minimum Typical Maximum Minimum Typical Maximum
A 4.07 0.160
A1 0.25 0.010
A2 3.17 3.42 3.67 0.125 0.133 0.144
B 0.22 0.38 0.009 0.015
c 0.13 0.23 0.005 0.009
D 30.95 31.20 31.45 1.219 1.228 1.238
D1 27.90 28.00 28.10 1.098 1.102 1.106
D3 22.75 0.896
e 0.65 0.026
E 30.95 31.20 31.45 1.219 1.228 1.238
E1 27.90 28.00 28.10 1.098 1.102 1.106
L 0.65 0.80 0.95 0.026 0.031 0.037
L1 1.60 0.063
K 0° (Minimum), 7° (Maximum)
144 109
D3
e
37 72
1
36
B
A1 A2
A
D1
D
73
108
E3
E1
E
0,10 mm
.004 inch
SEATING PLANE
c
L
K
L1
ST10F269 22 - PACKAGE MECHANICAL DATA
179/184
1. P ackage dimensions are in mm. The dimensions quot ed in inc hes are rounded.
Fi gure 85 : Package Outl i ne TQFP144 (20 x 20 x 1.40 mm)
Dimensions Millimeters 1Inches (approx)
Minimum Typical Maximum Minimum Typical Maximum
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.0067 0.0087 0.011
C 0.09 0.20 0.0035 0.008
D 22.00 0.866
D1 20.00 0.787
D3 17.50 0.689
e 0.50 0.020
E 22.00 0.866
E1 20.00 0.787
E3 17.50 0.689
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K0° (Minimum), 7° (Maximum)
c
B
A1 A2
A
L
K
L1
0,25 mm
.010 inch
GAGE PLANE
0.03 inch
SEATING PLANE
0,076 mm
144 109
e
37 72
1
36 73
108
D3
D1
D
E3
E1
E
23 - ORDERING INFORMATION ST10F269
180/184
23 - ORDE RING INFORMATION
Salestype Flash Program
Memory
(Bytes) Temperature range Package
ST10F269Z2Q3 256K -40°C to +125°C PQFP144 (28 x 28 mm)
ST10F269Z2Q6 256K -40°C to +85°C PQFP144 (28 x 28 mm)
ST10F269Z2T3 256K -40°C to +125°C TQFP144 (20 x 20 x 1.40 mm)
ST10F269Z2T6 256K -40°C to +85°C TQFP144 (20 x 20 x 1.40 mm)
ST10F269Z1Q3 128K -40°C to +125°C PQFP144 (28 x 28 mm)
ST10F269Z1Q6 128K -40°C to +85°C PQFP144 (28 x 28 mm)
ST10F269Z1T3 128K -40°C to +125°C TQFP144 (20 x 20 x 1.40 mm)
ST10F269Z1T6 128K -40°C to +85°C TQFP144 (20 x 20 x 1.40 mm)
181/184Septe mber 2003
1 - DESCRIPT IO N
This Errata sheet describes the functional and electrical problems known in the D revision of the
ST10F269Zxxx.
The re vision number can be found in the third line on the ST10F269 package. It looks lik e: ’xxxxxxxxx D’
where "D" identifies the revision number.
2 - FUNCTIONAL PROBLEMS
The following malfunctions are kn own in th is step:
2.1 - PWRDN.1 - Execution of PWRDN Instruction
When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in
SYSCON register) or wh ile at least o ne of the por t 2 pins used to exit from power-down mode (if PWRD-
CFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the
PWRDN instruction is ignored.
However, under the conditions described below, the PWRDN instruction is not ignored, and no further
instr uctions are fet ched from external memory, i.e. the CPU is in a quasi-idle state.
This problem only occurs in the following situations:
a) The instructions following the PWRDN instruction are located in an external memory, and a multi-
plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used.
Or
b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral
(XRAM,CAN), and the instructions following th e PWRDN instruction are located in exter nal memor y.
In t his case, the problem occurs for any bus configuration.
Note: The on-chi p peripherals are still w orking correctly, in particular the Watchdog Timer, i f not disabled,
resets the device upon an overflo w. Interrupts and PEC transfers, however, cannot be processed. In case
NMI is asser t ed low while the device is in this quasi-idle state, power-dow n mode is entered.
No problem occurs if the NMI pin is low (if PW RDCFG = 0) or if all P2 pins used to ex it from power-down
mode are at inact i ve level (if PWRDCFG = 1): the chip norm ally enters powerdown mode.
Workaround:
Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN
instruction, otherwise insert a NOP instruction in front of PWRDN. When a multiplexed bus with memory
tristate wait state is used, t he PWRDN in structi on must be executed from i nternal RAM or XRAM .
ERRATA SHEET
ST10F269Zxxx-D
LIMITATIONS AND CORRECTIONS
2 - FUNCTION AL P RO BLEMS ST10F 269
182/184
2.2 - MAC.9 - CoCM P Instruction Inverted Operand s
The ST10 Family Programming Manual describes the CoCMP instruction as: subtracts a 40-bit signed
operand f rom th 40-bit accumulator content (acc - op2\op1), and updates t he N, Z and C flags in the MSW
register, leaving the accumulator unchanged. On the device the reverse operation (op2\op1 - acc) has
been i mpl em ented in t he M ac Uni t. T herefore, th e N and C flags are set acco rding to the reverse opera-
tion (Z flag is not affected).
Workaround:
Change interpretation of the N and C flags in the MSW register.
Example:
MOV R12, #07h
MOV R13, #06h
MOV R14, #0
CoLOAD R14, R12 ; Accum ul ator = 70000h
CoCMP R14, R13 ; Compares 70000h to 60000h
Here the content of MSW i s 0500h, i.e. C = 1, Z = 0 and N = 1.
To tes t if t he Accumulator was greater t han or equal the compared value, the "normal" test, acc ording to
the descr i ption in the ST10 Programming Ma nual, would be:
JNB M SW.10, Great er ; If C flag cleared, then greater than or equal
Wi th the implementation, this test does not provide the expected result.
To obtain the correct compari so n, use instead:
JB MSW.10, Greater ; C f lag set: 60000h < 70000h (60000h-70000h implemented)
; i.e. the accumulator is greater than or equal compared valu e
2.3 - MAC.10 - E Flag Evaluation for CoSH R and CoASHR Instructions when Saturation Mode is
Enabled
The Logical and the Arithmet ic Right Shif t ins truc tions (CoSHR/CoASHR) are specifif ed not to be aff ected
by the saturation mode (MS bit of the MCW regist er): the shift operation is always made on the 40 bits of
the ac cumulator. The resul t shifted in the accumulator is nev er sat urated. Only when the saturation mode
is enabled, the evaluation of the E Flag (in the MSW register) is erroneous.
Comment to the example:
In this example below (Table 1), the E Flag is kept clea red however MAE is us ed: bit 0 of MAE has be en
shifted into bit 15 of MAH. The MAE part has been used and it contents significant bits but t he E Flag has
not been set .
The conte nt of the flags is given af ter the execution of the instruc tion.
Workaround:
If the MAE flag is used, the saturation mode must be disabled before running Logical and/or Arihmetic
Right Shift instruction s and re-enable just after.
Table 1 : MA C.10 Example
MS Bit is Set, Saturation Mode is Enabled Status of Flags After Instruction Execution
Code Accu mulator Value
(Hexa.) SL E SV C Z N Remark
MOV R5, #5555h -- ---- ---- -------
CoLOAD R5, R5 00 5555 5555 000000Right
NOP 00 5555 5555 000000Right
MOV MSW, #007F h 7F 5555 5555 000000Right
NOP 7F 5555 5555 000000Right
CoSHR #1 3F AAAA AAAA 00*0000*E is wrong
ST10F 269 3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICA TION
183/184
2.4 - ST_PORT.3 - Bad Behavior of Hysteresi s Function on Input Fa lling Edge
In the following conditions, a slow falling edge on a ST10F269 inpu t may generate multiple events :
– A falling edge is occuring.
– A ND the falling edge has a transition time between V ih and Vil longer than the CPU cl ock period.
Workaround:
Add external hardware on the ST10 input in order to have a fast falling edge (lower th an 1/Fcpu).
History of Fixed Function al Problems of the ST10F269Z xxx-D
Su mm ary of Remainin g Functiona l Problems Known on the ST10F269 Zxxx-D
3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION
No t e on on-chi p osc i lla tor
The X TAL2 out put is not designed to provide a val id signal when XTAL1 is supplied by an exter nal clock
signal. It may happen, if the external clock signal is not perfectly symetr ical and cente red on VDD / 2, that
XTAL2 sign al i s not equal to X TAL1. T his i s due to the design of the os cil lator, which has a auto-adapta-
tion gain control dedicated to external crystal.
If an external clock signal is directly provided on XTAL1 pin, then leave XTAL2 pin disconnected to
a ch ieve the lowes t con s umptio n o f the o n- c h ip o s c illator.
4 - ERRATA SHEET VERSION INFORMATION
This document was released in September 2003. It reflects the current silicon status of the
ST10F269Zxxx-D.
Name of the
Modification Short Description Fixed in Step
ST_PORT.2 Wrong Port Direction after Return From Power Down Mode D
Name Short Desc riptio n
PWRDN.1 Execution of PWRDN Instruction
MAC.9 CoCMP Instruction Inverted Operands
MAC.10 E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled
ST_PORT.3 Bad Behavior of Hysteresis Function on Input Falling Edge
Vih
Vil
“0”
PROBLEM
Input signal
(falling edge)
“1”
Internal
signal
t1
(t2 - t1) > 1/Fcpu
t2
ST10F269
184/184
F269-Q3.REF
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