1
FEATURES
3
2
4
61
VCCA VCCB
B
GND
A
DBV PACKAGE
(TOP VIEW) DCK PACKAGE
(TOP VIEW)
3
2
4
61
VCCA VCCB
B
GND
A
3
2
4
61
VCCA VCCB
B
GND
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
DIR DIR DIR
5
55
YZP PACKAGE
(BOTTOM VIEW)
VCCA
A
VCCB
B
GND
1
4
2
3
6
5DIR
C1
B1
A1
C2
B2
A2
DESCRIPTION/ORDERING INFORMATION
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
2
Available in the Texas Instruments NanoFree™ Max Data RatesPackage
420 Mbps (3.3-V to 5-V Translation)Fully Configurable Dual-Rail Design Allows
210 Mbps (Translate to 3.3 V)Each Port to Operate Over the Full 1.65-V to
140 Mbps (Translate to 2.5 V)5.5-V Power-Supply Range
75 Mbps (Translate to 1.8 V)V
CC
Isolation Feature If Either V
CC
Input Is at
Latch-Up Performance Exceeds 100 mA PerGND, Both Ports Are in the High-Impedance
JESD 78, Class IIState
ESD Protection Exceeds JESD 22DIR Input Circuit Referenced to V
CCA
2000-V Human-Body Model (A114-A)Low Power Consumption, 4- µA Max I
CC
200-V Machine Model (A115-A)± 24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)I
off
Supports Partial-Power-Down ModeOperation
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port isdesigned to track V
CCA
. V
CCA
accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to trackV
CCB
. V
CCB
accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectionaltranslation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels ofthe direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits datafrom the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when theA-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logicHIGH or LOW level applied to prevent excess I
CC
and I
CCZ
.
The SN74LVC1T45 is designed so that the DIR input is powered by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both ports are in the high-impedancestate.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
B
DIR 5
4
A3
VCCA VCCB
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as thepackage.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoFree™ WCSP (DSBGA)
Reel of 3000 SN74LVC1T45YZPR _ _ _TA_0.23-mm Large Bump YZP (Pb-free)
Reel of 3000 SN74LVC1T45DBVRSOT (SOT-23) DBV CT1_Reel of 250 SN74LVC1T45DBVT 40 ° C to 85 ° C
Reel of 3000 SN74LVC1T45DCKRSOT (SC-70) DCK
Reel of 250 SN74LVC1T45DCKT TA_SOT (SOT-533) DRL Reel of 4000 SN74LVC1T45DRLR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
(1)
INPUT
OPERATIONDIR
L B data to A busH A data to B bus
(1) Input circuits of the data I/Osalways are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
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Absolute Maximum Ratings
(1)
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CCA
Supply voltage range 0.5 6.5 VV
CCB
V
I
Input voltage range
(2)
0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
0.5 6.5 VA port 0.5 V
CCA
+ 0.5V
O
Voltage range applied to any output in the high or low state
(2) (3)
VB port 0.5 V
CCB
+ 0.5I
IK
Input clamp current V
I
< 0 50 mAI
OK
Output clamp current V
O
< 0 50 mAI
O
Continuous output current ± 50 mAContinuous current through V
CC
or GND ± 100 mADBV package 165DCK package 259θ
JA
Package thermal impedance
(4)
° C/WDRL package 142YZP package 123T
stg
Storage temperature range 65 150 ° C
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
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Recommended Operating Conditions
(1) (2) (3)
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
V
CCI
V
CCO
MIN MAX UNIT
V
CCA
1.65 5.5Supply voltage VV
CCB
1.65 5.51.65 V to 1.95 V V
CCI
× 0.652.3 V to 2.7 V 1.7High-levelV
IH
Data inputs
(4)
Vinput voltage
3 V to 3.6 V 24.5 V to 5.5 V V
CCI
× 0.71.65 V to 1.95 V V
CCI
× 0.352.3 V to 2.7 V 0.7Low-levelV
IL
Data inputs
(4)
Vinput voltage
3 V to 3.6 V 0.84.5 V to 5.5 V V
CCI
× 0.31.65 V to 1.95 V V
CCA
× 0.652.3 V to 2.7 V 1.7High-level DIRV
IH
Vinput voltage (referenced to V
CCA
)
(5)
3 V to 3.6 V 24.5 V to 5.5 V V
CCA
× 0.71.65 V to 1.95 V V
CCA
× 0.352.3 V to 2.7 V 0.7Low-level DIRV
IL
Vinput voltage (referenced to V
CCA
)
(5)
3 V to 3.6 V 0.84.5 V to 5.5 V V
CCA
× 0.3V
I
Input voltage 0 5.5 VV
O
Output voltage 0 V
CCO
V1.65 V to 1.95 V 42.3 V to 2.7 V 8I
OH
High-level output current mA3 V to 3.6 V 244.5 V to 5.5 V 321.65 V to 1.95 V 42.3 V to 2.7 V 8I
OL
Low-level output current mA3 V to 3.6 V 244.5 V to 5.5 V 321.65 V to 1.95 V 202.3 V to 2.7 V 20Data inputsInput transitionΔt/ Δv 3 V to 3.6 V 10 ns/Vrise or fall rate
4.5 V to 5.5 V 5Control inputs 1.65 V to 5.5 V 5T
A
Operating free-air temperature 40 85 ° C
(1) V
CCI
is the V
CC
associated with the input port.(2) V
CCO
is the V
CC
associated with the output port.(3) All unused data inputs of the device must be held at V
CCI
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.(4) For V
CCI
values not specified in the data sheet, V
IH
min = V
CCI
× 0.7 V, V
IL
max = V
CCI
× 0.3 V.(5) For V
CCI
values not specified in the data sheet, V
IH
min = V
CCA
× 0.7 V, V
IL
max = V
CCA
× 0.3 V.
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Electrical Characteristics
(1) (2)
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= 25 ° C 40 ° C to 85 ° CPARAMETER TEST CONDITIONS V
CCA
V
CCB
UNITMIN TYP MAX MIN MAX
V
CCOI
OH
= 100 µA 1.65 V to 4.5 V 1.65 V to 4.5 V
0.1I
OH
= 4 mA 1.65 V 1.65 V 1.2V
OH
V
I
= V
IH
VI
OH
= 8 mA 2.3 V 2.3 V 1.9I
OH
= 24 mA 3 V 3 V 2.4I
OH
= 32 mA 4.5 V 4.5 V 3.8I
OL
= 100 µA 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1I
OL
= 4 mA 1.65 V 1.65 V 0.45V
OL
I
OL
= 8 mA V
I
= V
IL
2.3 V 2.3 V 0.3 VI
OL
= 24 mA 3 V 3 V 0.55I
OL
= 32 mA 4.5 V 4.5 V 0.55I
I
DIR V
I
= V
CCA
or GND 1.65 V to 5.5 V 1.65 V to 5.5 V ± 1 ± 2 µAA port 0 V 0 to 5.5 V ± 1 ± 2I
off
V
I
or V
O
= 0 to 5.5 V µAB port 0 to 5.5 V 0 V ± 1 ± 2A or BI
OZ
V
O
= V
CCO
or GND 1.65 V to 5.5 V 1.65 V to 5.5 V ± 1 ± 2 µAport
1.65 V to 5.5 V 1.65 V to 5.5 V 3I
CCA
V
I
= V
CCI
or GND, I
O
= 0 5.5 V 0 V 2 µA0 V 5.5 V -21.65 V to 5.5 V 1.65 V to 5.5 V 3I
CCB
V
I
= V
CCI
or GND, I
O
= 0 5.5 V 0 V -2 µA0 V 5.5 V 2I
CCA
+ I
CCB
V
I
= V
CCI
or GND, I
O
= 0 1.65 V to 5.5 V 1.65 V to 5.5 V 4 µA(see Table 1)
A port at V
CCA
0.6 V,A port 50DIR at V
CCA
, B port = open
ΔI
CCA
3 V to 5.5 V 3 V to 5.5 V µADIR at V
CCA
0.6 V,DIR B port = open, 50A port at V
CCA
or GNDB port at V
CCB
0.6 V,ΔI
CCB
B port DIR at GND, 3 V to 5.5 V 3 V to 5.5 V 50 µAA port = openC
i
DIR V
I
= V
CCA
or GND 3.3 V 3.3 V 2.5 pFA or BC
io
V
O
= V
CCA/B
or GND 3.3 V 3.3 V 6 pFport
(1) V
CCO
is the V
CC
associated with the output port.(2) V
CCI
is the V
CC
associated with the input port.
Copyright © 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
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Switching Characteristics
Switching Characteristics
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
over recommended operating free-air temperature range, V
CCA
= 1.8 V ± 0.15 V (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
3 17.7 2.2 10.3 1.7 8.3 1.4 7.2A B nst
PHL
2.8 14.3 2.2 8.5 1.8 7.1 1.7 7t
PLH
3 17.7 2.3 16 2.1 15.5 1.9 15.1B A nst
PHL
2.8 14.3 2.1 12.9 2 12.6 1.8 12.2t
PHZ
5.2 19.4 4.8 18.5 4.7 18.4 5.1 17.1DIR A nst
PLZ
2.3 10.5 2.1 10.5 2.4 10.7 3.1 10.9t
PHZ
7.4 21.9 4.9 11.5 4.6 10.3 2.8 8.2DIR B nst
PLZ
4.2 16 3.7 9.2 3.3 8.4 2.4 6.4t
PZH
(1)
33.7 25.2 23.9 21.5DIR A nst
PZL
(1)
36.2 24.4 22.9 20.4t
PZH
(1)
28.2 20.8 19 18.1DIR B nst
PZL
(1)
33.7 27 25.5 24.1
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
over recommended operating free-air temperature range, V
CCA
= 2.5 V ± 0.2 V (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
2.3 16 1.5 8.5 1.3 6.4 1.1 5.1A B nst
PHL
2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6t
PLH
2.2 10.3 1.5 8.5 1.4 8 1 7.5B A nst
PHL
2.2 8.5 1.4 7.5 1.3 7 0.9 6.2t
PHZ
3 8.1 3.1 8.1 2.8 8.1 3.2 8.1DIR A nst
PLZ
1.3 5.9 1.3 5.9 1.3 5.9 1 5.8t
PHZ
6.5 23.7 4.1 11.4 3.9 10.2 2.4 7.1DIR B nst
PLZ
3.9 18.9 3.2 9.6 2.8 8.4 1.8 5.3t
PZH
(1)
29.2 18.1 16.4 12.8DIR A nst
PZL
(1)
32.2 18.9 17.2 13.3t
PZH
(1)
21.9 14.4 12.3 10.9DIR B nst
PZL
(1)
21 15.6 13.5 12.7
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
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Switching Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
over recommended operating free-air temperature range, V
CCA
= 3.3 V ± 0.3 V (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
2.1 15.5 1.4 8 0.7 5.8 0.7 4.4A B nst
PHL
2 12.6 1.3 7 0.8 5 0.7 4t
PLH
1.7 8.3 1.3 6.4 0.7 5.8 0.6 5.4B A nst
PHL
1.8 7.1 1.3 5.4 0.8 5 0.7 4.5t
PHZ
2.9 7.3 3 7.3 2.8 7.3 3.4 7.3DIR A nst
PLZ
1.8 5.6 1.6 5.6 2.2 5.7 2.2 5.7t
PHZ
5.4 20.5 3.9 10.1 2.9 8.8 2.4 6.8DIR B nst
PLZ
3.3 14.5 2.9 7.8 2.4 7.1 1.7 4.9t
PZH
(1)
22.8 14.2 12.9 10.3DIR A nst
PZL
(1)
27.6 15.5 13.8 11.3t
PZH
(1)
21.1 13.6 11.5 10.1DIR B nst
PZL
(1)
19.9 14.3 12.3 11.3
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
over recommended operating free-air temperature range, V
CCA
= 5 V ± 0.5 V (see Figure 1 )
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
1.9 15.1 1 7.5 0.6 5.4 0.5 3.9A B nst
PHL
1.8 12.2 0.9 6.2 0.7 4.5 0.5 3.5t
PLH
1.4 7.2 1 5.1 0.7 4.4 0.5 3.9B A nst
PHL
1.7 7 0.9 4.6 0.7 4 0.5 3.5t
PHZ
2.1 5.4 2.2 5.4 2.2 5.5 2.2 5.4DIR A nst
PLZ
0.9 3.8 1 3.8 1 3.7 0.9 3.7t
PHZ
4.8 20.2 2.5 9.8 1 8.5 2.5 6.5DIR B nst
PLZ
4.2 14.8 2.5 7.4 2.5 7 1.6 4.5t
PZH
(1)
22 12.5 11.4 8.4DIR A nst
PZL
(1)
27.2 14.4 12.5 10t
PZH
(1)
18.9 11.3 9.1 7.6DIR B nst
PZL
(1)
17.6 11.6 10 8.6
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
T
A
= 25 ° C
V
CCA
= V
CCA
= V
CCA
= V
CCA
=TEST
V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 V V
CCB
= 5 VPARAMETER UNITCONDITIONS
TYP TYP TYP TYP
A-port input, B-port output C
L
= 0 pF, 3 4 4 4C
pdA
(1)
f = 10 MHz, pFB-port input, A-port output 18 19 20 21t
r
= t
f
= 1 nsA-port input, B-port output C
L
= 0 pF, 18 19 20 21C
pdB
(1)
f = 10 MHz, pFB-port input, A-port output 3 4 4 4t
r
= t
f
= 1 ns
(1) Power dissipation capacitance per transceiver
Copyright © 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
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TYPICAL CHARACTERISTICS
0
1
2
3
4
5
6
7
8
9
0 5 10 15 20 25 30 35
tPHL
− ns
CL − pF
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35
tPLH
− ns
CL − pF
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPHL
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0
1
2
3
4
5
6
7
8
9
10
0510 15 20 25 30 35
tPLH
− ns
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
CL − pF
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 1.8 V
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 1.8 V
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0 5 10 15 20 25 30 35
tPHL
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35
tPLH
− ns
CL − pF
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPHL
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 3.3 V
VCCB = 5 V
VCCB = 2.5 V
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 2.5 V
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 2.5 V
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0 5 10 15 20 25 30 35
tPHL
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
tPHL
− ns
CL − pF
0 5 10 15 20 25 30 35
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 3.3 V
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 3.3 V
10 Submit Documentation Feedback Copyright © 2003 2009, Texas Instruments Incorporated
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0510 15 20 25 30 35
tPHL
− ns
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
VCCB = 1.8 V
tPLH
− ns
0 5 10 15 20 25 30 35
CL − pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
VCCB = 1.8 V
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 5 V
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCET
A
= 25 ° C, V
CCA
= 5 V
Copyright © 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN74LVC1T45
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2 × VCCO
Open
GND
RL
RL
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2VCCA/2
VCCI/2 VCCI/2 VCCI
0 V
VCCO/2 VCCO/2VOH
VOL
0 V
VCCO/2 VOL + VTP
VCCO/2 VOH − VTP
0 V
VCCI
0 V
VCCI/2 VCCI/2
tw
Input
VCCA
VCCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 , dv/dt 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
2 k
2 k
2 k
2 k
VCCO RL0.15 V
0.15 V
0.3 V
0.3 V
VTP
CL
15 pF
15 pF
15 pF
15 pF
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
Figure 1. Load Circuit and Voltage Waveforms
12 Submit Documentation Feedback Copyright © 2003 2009, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1T45
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1 VCC1 VCC2 VCC2
SYSTEM-1 SYSTEM-2
1
2
3
6
5
4
VCC1 VCC1 VCC2
SYSTEM-1 SYSTEM-2
DIR CTRL
I/O-1
VCC2
I/O-2
Pullup/Down
or Bus Hold(1)
Pullup/Down
or Bus Hold(1)
SN74LVC1T45
www.ti.com
..................................................................................................................................................... SCES515I DECEMBER 2003 REVISED MAY 2009
Figure 2 shows an example of the SN74LVC1T45 being used in a unidirectional logic level-shifting application.
PIN NAME FUNCTION DESCRIPTION
1 V
CCA
V
CC1
SYSTEM-1 supply voltage (1.65 V to 5.5 V)2 GND GND Device GND3 A OUT Output level depends on V
CC1
voltage.4 B IN Input threshold value depends on V
CC2
voltage.5 DIR DIR GND (low level) determines B-port to A-port direction.6 V
CCB
V
CC2
SYSTEM-2 supply voltage (1.65 V to 5.5 V)
Figure 2. Unidirectional Logic Level-Shifting Application
Figure 3 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Since theSN74LVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoidbus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Copyright © 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN74LVC1T45
Enable Times
SN74LVC1T45
SCES515I DECEMBER 2003 REVISED MAY 2009 .....................................................................................................................................................
www.ti.com
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 toSYSTEM-1.
STATE DIR CTRL I/O-1 I/O-2 DESCRIPTION
1 H Out In SYSTEM-1 data to SYSTEM-2SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The2 H Hi-Z Hi-Z
bus-line state depends on pullup or pulldown.
(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or3 L Hi-Z Hi-Z
pulldown.
(1)
4 L Out In SYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74LVC1T45 using the following formulas:t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit isswitched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, thenthe DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the Bport has been disabled, an input signal applied to it appears on the corresponding A port after the specifiedpropagation delay.
14 Submit Documentation Feedback Copyright © 2003 2009, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1T45
PACKAGE OPTION ADDENDUM
www.ti.com 3-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC1T45DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DCKT ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DPKR ACTIVE USON DPK 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DRLR ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1T45YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 3-Mar-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1T45 :
Automotive: SN74LVC1T45-Q1
Enhanced Product: SN74LVC1T45-EP
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1T45DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1T45DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1T45DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1T45DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1T45DCKR SC70 DCK 6 3000 180.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3
SN74LVC1T45DCKT SC70 DCK 6 250 180.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3
SN74LVC1T45DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1T45DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1T45DPKR USON DPK 6 5000 180.0 9.5 1.75 1.75 0.7 4.0 8.0 Q2
SN74LVC1T45DRLR SOT DRL 6 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1T45DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1T45YZPR DSBGA YZP 6 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1
SN74LVC1T45YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-May-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1T45DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC1T45DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1T45DBVT SOT-23 DBV 6 250 202.0 201.0 28.0
SN74LVC1T45DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1T45DCKR SC70 DCK 6 3000 202.0 201.0 28.0
SN74LVC1T45DCKT SC70 DCK 6 250 202.0 201.0 28.0
SN74LVC1T45DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC1T45DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC1T45DPKR USON DPK 6 5000 180.0 180.0 30.0
SN74LVC1T45DRLR SOT DRL 6 4000 180.0 180.0 30.0
SN74LVC1T45DRLR SOT DRL 6 4000 202.0 201.0 28.0
SN74LVC1T45YZPR DSBGA YZP 6 3000 220.0 220.0 34.0
SN74LVC1T45YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-May-2012
Pack Materials-Page 2
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