+
−
75 Ω75 Ω
75 Ω
75 Ω
75 Ω
n Lines
VO(1)
VO(n)
75-Ω Transmission Line
VI
1 kΩ
−15 V
15 V
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS VIDEO DISTRIBUTION AMPLIFIER APPLICATION
0
0.05
0.1
0.15
0.2
0.25
0.3
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Gain − %
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Phase −
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
5
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
1 kΩ
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK
OPERATIONAL AMPLIFIERS
Check for Samples: THS3110 THS3111
1FEATURES DESCRIPTION
23• Low Noise The THS3110 and THS3111 are low-noise,
high-voltage, current-feedback amplifiers designed to
– 2-pA/√Hz Noninverting Current Noise operate over a wide supply range of ±5 V to ±15 V for
– 10-pA/√Hz Inverting Current Noise today's high performance applications.
– 3-nV/√Hz Voltage Noise The THS3110 features a power-down pin (PD) that
• High Output Current Drive: 260 mA puts the amplifier in low-power standby mode, and
• High Slew Rate: 1300 V/μslowers the quiescent current from 4.8 mA to 270 μA.
– (RL= 100 Ω, VO=8VPP)These amplifiers provide well-regulated ac
• Wide Bandwidth: 90 MHz (G = 2, RL= 100 Ω)performance characteristics. The unity-gain
bandwidth of 100 MHz allows for good distortion
• Wide Supply Range: ±5 V to ±15 V characteristics below 10 MHz. Coupled with a high
• Power-Down Feature: (THS3110 Only) 1300-V/μs slew rate, the THS3110 and THS3111
amplifiers allow for high output voltage swings at high
APPLICATIONS frequencies.
• Video Distribution The THS3110 and THS3111 are offered in the
• Power FET Driver SOIC-8 (D) and the MSOP-8 (DGN) packages with
• Pin Driver PowerPAD™.
• Capacitive Load Driver space
space
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
8
7
6
5
NC
VIN −
VIN +
VS−
NC
VS+
VOUT
NC
NC =NoInternalConnection
NOTE:Thedevicewiththepower-downoptiondefaultstotheONstateifnosignalisappliedtothePDpin.Additionally,theREFpin
functionalrangeisfromV to(V 4V).
S S+-
-
1
2
3
4
8
7
6
5
REF
VIN−
VIN+
VS−
VS+
VOUT
NC
NC=NoInternalConnection
PD
THS3110 THS3111
D,DGNTOPVIEW D,DGNTOPVIEW
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICE
TAPLASTIC SMALL OUTLINE SOIC (D) PLASTIC MSOP (DGN) (2) SYMBOL
THS3110CD THS3110CDGN
0°C to +70°C BJB
THS3110CDR THS3110CDGNR
THS3110ID THS3110IDGN
–40°C to +85°C BIR
THS3110IDR THS3110IDGNR
THS3111CD THS3111CDGN
0°C to +70°C BJA
THS3111CDR THS3111CDGNR
THS3111ID THS3111IDGN
–40°C to +85°C BIS
THS3111IDR THS3111IDGNR
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATINGS TABLE POWER RATING
TJ= +125°C
PACKAGE θJC (°C/W) θJA (°C/W) TA= +25°C TA= +85°C
D-8(1) 38.3 95 1.05 W 421 mW
DGN-8(2) 4.7 58.4 1.71 W 685 mW
(1) These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the θJA is 95°C/W with
power rating at TA= +25°C of 1.05 W.
(2) These data were taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch × 3 inch (76,2 mm × 76,2 mm) PCB. For
further information, refer to the Application Information section of this data sheet.
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........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Dual supply ±5 ±15
Supply voltage V
Single supply 10 30
Commercial 0 +70
Operating free-air temperature, TAIndustrial –40 +85 °C
Operating junction temperature, continuous operating temperature, TJ–40 +125
Normal storage temperature, TSTG –40 +85
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature, unless otherwise noted. UNIT
Supply voltage, VS– to VS+ 33 V
Input voltage, VI± VS
Differential input voltage, VID ± 4 V
Output current, IO(2) 300 mA
Continuous power dissipation See Dissipation Ratings Table
Maximum junction temperature, TJ(3) +150°C
Maximum junction temperature, continuous operation, long term reliability, TJ(4) +125°C
Commercial 0°C to +70°C
Operating free-air temperature, TAIndustrial –40°C to +85°C
Storage temperature, Tstg –65°C to +125°C
ESD ratings: HBM 900
CDM 1500
MM 200
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3110 and THS3111 may incorporate a PowerPAD on the underside of the chip. This feature acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
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SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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ELECTRICAL CHARACTERISTICS
VS= ±15 V, RF= 1 k Ω,RL= 100 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE MIN/TYP/
PARAMETER TEST CONDITIONS UNIT
0°C to –40°C to MAX
+25°C +25°C +70°C +85°C
AC PERFORMANCE
G = 1, RF= 1.5 kΩ, VO= 200 mVPP 100
G = 2, RF= 1 kΩ, VO= 200 mVPP 90
Small-signal bandwidth, –3 dB G = 5, RF= 806 Ω, VO= 200 mVPP 87 MHz TYP
G = 10, RF= 604 Ω, VO= 200 mVPP 66
0.1-dB bandwidth flatness G = 2, RF= 1.15 kΩ, VO= 200 mVPP 45
Large-signal bandwidth G = 5, RF= 806 Ω, VO= 4 VPP 95
G = 1, VO= 4-V step, RF= 1.5 kΩ800
Slew rate (25% to 75% level) V/μs TYP
G = 2, VO= 8-V step, RF= 1 kΩ1300
Recommended maximum SR for
Slew rate 900 V/μs MAX
repetitive signals(1)
Rise and fall time G = –5, VO= 10-V step, RF= 806 Ω8 ns TYP
Settling time to 0.1% G = –2, VO= 2 VPP step 27 ns TYP
Settling time to 0.01% G = –2, VO= 2 VPP step 250
Harmonic distortion
RL= 100 Ω52
2nd harmonic distortion G = 2, RL= 1 kΩ53
RF= 1 kΩ,dBc TYP
VO= 2 VPP,RL= 100 Ω48
f = 10 MHz
3rd harmonic distortion RL= 1 kΩ68
Input voltage noise f > 20 kHz 3 nV/√Hz TYP
Noninverting input current noise f > 20 kHz 2 pA/√Hz TYP
Inverting input current noise f > 20 kHz 10 pA/√Hz TYP
NTSC 0.011%
Differential gain G = 2, PAL 0.013%
RL= 150 Ω, TYP
NTSC 0.029°
RF= 1 kΩ
Differential phase PAL 0.033°
DC PERFORMANCE
Transimpedance VO= ±3.75 V, gain = 1 1 0.75 0.5 0.5 MΩMIN
Input offset voltage 3 10 12 12 mV MAX
VCM = 0 V
Average offset voltage drift ±10 ±10 μV/°C TYP
Noninverting input bias current 1 4 6 6 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Inverting input bias current 1.5 15 20 20 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Input offset current 2.5 15 20 20 μA MAX
VCM = 0 V
Average offset current drift ±30 ±30 nA/°C TYP
INPUT CHARACTERISTICS
Input common-mode voltage range ±13.3 ±13 ±12.5 ±12.5 V MIN
Common-mode rejection ratio VCM = ±12.5 V 68 62 60 60 dB MIN
Noninverting input resistance 41 MΩTYP
Noninverting input capacitance 0.4 pF TYP
OUTPUT CHARACTERISTICS
RL= 1 kΩ±13.5 ±13 ±12.5 ±12.5
Output voltage swing V MIN
RL= 100 Ω±13.4 ±12.5 ±12 ±12
Output current (sourcing) RL= 25 Ω260 200 175 175 mA MIN
Output current (sinking) RL= 25 Ω260 200 175 175 mA MIN
Output impedance f = 1 MHz, closed loop 0.15 ΩTYP
(1) For more information, see the Application Information section of this data sheet.
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........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
VS= ±15 V, RF= 1 k Ω,RL= 100 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE MIN/TYP/
PARAMETER TEST CONDITIONS UNIT
0°C to –40°C to MAX
+25°C +25°C +70°C +85°C
POWER SUPPLY
Specified operating voltage ±15 ±16 ±16 ±16 V MAX
Maximum quiescent current 4.8 6.5 7.5 7.5 mA MAX
Minimum quiescent current 4.8 3.8 2.5 2.5 mA MIN
Power-supply rejection (+PSRR) VS+ = 15.5 V to 14.5 V, VS– = 15 V 75 65 60 60 dB MIN
Power-supply rejection (–PSRR) VS+ = 15 V, VS– = –15.5 V to –14.5 V 69 60 55 55 dB MIN
POWER-DOWN CHARACTERISTICS (THS3110 Only)
VS+– 4 V MAX
REF voltage range (2) VS– V MIN
PD ≤
Enable V MIN
REF+ 0.8
Power-down voltage level(2) PD ≥REF
Disable V MAX
+ 2
Power-down quiescent current PD ≥REF + 2 V 270 450 500 500 μA MAX
VPD = 0 V, REF = 0 V, 11
PD pin bias current μA TYP
VPD = 3.3 V, REF = 0 V 11
Turn-on time delay 90% of final value 4 μs TYP
Turn-off time delay 10% of final value 6
Input impedance 3.4 || 1.7 kΩ|| pF TYP
(2) For detailed information on the behavior of the power-down circuit, see the Saving Power with Power-Down Functionality and
Power-Down Reference Pin Operation sections in the Application Information section of this data sheet.
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SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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ELECTRICAL CHARACTERISTICS
VS= ±5 V, RF= 1.15 Ω, RL= 100 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE MIN/TYP/
PARAMETER TEST CONDITIONS UNIT
0°C to –40°C to MAX
+25°C +25°C +70°C +85°C
AC PERFORMANCE
G = 1, RF= 1.5 kΩ, VO= 200 mVPP 85
G = 2, RF= 1.15 kΩ, VO= 200 mVPP 78
Small-signal bandwidth, –3 dB G = 5, RF= 806 Ω, VO= 200 mVPP 80 MHz TYP
G = 10, RF= 604 Ω, VO= 200 mVPP 60
0.1-dB bandwidth flatness G = 2, RF= 1.15 kΩ, VO= 200 mVPP 15
Large-signal bandwidth G = 5, RF= 806 Ω, VO= 4 VPP 80
G = 1, VO= 4-V step, RF= 1.5 kΩ640
Slew rate (25% to 75% level) V/μs TYP
G = 2, VO= 4-V step, RF= 1 kΩ700
Recommended maximum SR for
Slew rate 900 V/μs MAX
repetitive signals(1)
Rise and fall time G = –5, VO= 5-V step, RF= 806 Ω7 ns TYP
Settling time to 0.1% G = –2, VO= 2 VPP step 20 ns TYP
Settling time to 0.01% G = –2, VO= 2 VPP step 200
Harmonic distortion
RL= 100 Ω55
2nd harmonic distortion G = 2, RL= 1 kΩ56
RF= 1 kΩ,dBc TYP
VO= 2 VPP,RL= 100 Ω45
f = 10 MHz
3rd harmonic distortion RL= 1 kΩ62
Input voltage noise f > 20 kHz 3 nV/√Hz TYP
Noninverting input current noise f > 20 kHz 2 pA/√Hz TYP
Inverting input current noise f > 20 kHz 10 pA/√Hz TYP
NTSC 0.011%
Differential gain G = 2, PAL 0.015%
RL= 150 Ω, TYP
NTSC 0.020°
RF= 1 kΩ
Differential phase PAL 0.033°
DC PERFORMANCE
Transimpedance VO= ±1.25 V, gain = 1 1 0.75 0.5 0.5 MΩMIN
Input offset voltage 6 10 12 12 mV MAX
VCM = 0 V
Average offset voltage drift ±10 ±10 μV/°C TYP
Noninverting input bias current 1 4 6 6 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Inverting input bias current 1 8 10 10 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Input offset current 1 6 8 8 μA MAX
VCM = 0 V
Average offset current drift ±20 ±20 nA/°C TYP
INPUT CHARACTERISTICS
Input common-mode voltage range ±3.2 ±2.9 ±2.8 ±2.8 V MIN
Common-mode rejection ratio VCM = ±2.5 V 65 62 58 58 dB MIN
Noninverting input resistance 35 MΩTYP
Noninverting input capacitance 0.5 pF TYP
OUTPUT CHARACTERISTICS
RL= 1 kΩ±4 ±3.8 ±3.6 ±3.6
Output voltage swing V MIN
RL= 100 Ω±3.8 ±3.7 ±3.5 ±3.5
Output current (sourcing) RL= 10 Ω220 150 125 125 mA MIN
Output current (sinking) RL= 10 Ω220 150 125 125 mA MIN
Output impedance f = 1 MHz, closed loop 0.15 ΩTYP
(1) For more information, see the Application Information section of this data sheet.
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........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
VS= ±5 V, RF= 1.15 Ω, RL= 100 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE MIN/TYP/
PARAMETER TEST CONDITIONS UNIT
0°C to –40°C to MAX
+25°C +25°C +70°C +85°C
POWER SUPPLY
Specified operating voltage ±5 ±4.5 ±4.5 ±4.5 V MIN
Maximum quiescent current 4 6 7 7 mA MAX
Minimum quiescent current 4 3.2 2 2 mA MIN
Power-supply rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS– = 5 V 71 62 57 57 dB MIN
Power-supply rejection (–PSRR) VS+ = 5 V, VS– = –5.5 V to –4.5 V 66 57 52 52 dB MIN
POWER-DOWN CHARACTERISTICS (THS3110 Only)
VS+ –4 V MAX
REF voltage range(2) VS– V MIN
PD ≤REF
Enable V MIN
+ 0.8
Power-down voltage level(2) PD ≥REF
Disable V MAX
+ 2
Power-down quiescent current PD ≥REF + 2 V 200 450 500 500 μA MAX
VPD = 0 V, REF = 0 V, 11
PD pin bias current μA TYP
VPD = 3.3 V, REF = 0 V 11
Turn-on time delay 90% of final value 4 μs TYP
Turn-off time delay 10% of final value 6
Input impedance 3.4 || 1.7 kΩ|| pF TYP
(2) For detailed information on the behavior of the power-down circuit, see the Power-Down and Power-down Reference sections in the
Application Information section of this data sheet.
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SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
±15-V Graphs
Noninverting small-signal gain frequency response 1, 2
Inverting small-signal gain frequency response 3
0.1-dB flatness 4
Noninverting large-signal gain frequency response 5
Inverting large-signal gain frequency response 6
Frequency response capacitive load 7
Recommended RISO vs Capacitive load 8
2nd harmonic distortion vs Frequency 9
3rd harmonic distortion vs Frequency 10
Harmonic distortion vs Output voltage swing 11, 12
Slew rate vs Output voltage step 13, 14, 15, 16
Noise vs Frequency 17
Settling time 18, 19
Quiescent current vs Supply voltage 20
Output voltage vs Load resistance 21
Input bias and offset current vs Case temperature 22
Input offset voltage vs Case temperature 23
Transimpedance vs Frequency 24
Rejection ratio vs Frequency 25
Noninverting small-signal transient response 26
Inverting large signal transient response 27
Overdrive recovery time 28
Differential gain vs Number of loads 29
Differential phase vs Number of loads 30
Closed loop output impedance vs Frequency 31
Power-down quiescent current vs Supply voltage 32
Turn-on and turn-off time delay 33
±5-V Graphs
Noninverting small-signal gain frequency response 34
Inverting small-signal gain frequency response 35
0.1-dB flatness 36
Noninverting large-signal gain frequency response 37
Inverting large-signal gain frequency response 38
Slew rate vs Output voltage step 39, 40, 41, 42
2nd harmonic distortion vs Frequency 43
3rd harmonic distortion vs Frequency 44
Harmonic distortion vs Output voltage swing 45, 46
Noninverting small-signal transient response 47
Inverting small-signal transient response 48
Overdrive recovery time 49
Rejection ratio vs Frequency 50
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-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
G = 1, RF = 1.5 kΩ
G = 10, RF = 604 Ω
G = 5, RF = 806 Ω
G = 2, RF = 1.15 kΩ
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
0
1
2
3
4
5
6
7
8
9
1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
RF = 649 Ω
Gain = 2,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
RF = 1.15 kΩ
RF = 1.5 kΩ
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 100 M 1 G
f - Frequency - Hz
Inverting Gain - dB
G = -10, RF = 649 ΩRL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
G = -1, RF = 1 kΩ
G = -5, RF = 909 Ω
G = -2, RF = 1.1 kΩ
-4
-2
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
G = -5, RF = 806 Ω
G =-1, RF = 1 kΩ
RL = 100 Ω,
VO = 2 VPP,
VS = ±15 V
Inverting Gain - dB
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
100 k 1 M 10 M 100 M
Gain = 2,
RF = 1.15 kΩ,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
f - Frequency - Hz
Noninverting Gain - dB
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
G = 5, RF = 806 Ω
G = 2, RF = 1 kΩ
RL = 100 Ω,
VO = 4 VPP,
VS = ±15 V
0
10
20
30
40
50
60
10 100
CL - Capacitive Load - pF
Recommended R Ω
Gain = 5,
RL = 100 Ω,
VS = ±15 V
ISO -
-2
0
2
4
6
8
10
12
14
16
10 M 100 M
Capacitive Load - MHz
Signal Gain - dB
Gain = 5,
RL = 100 Ω
VS = ±15 V
R(ISO) = 39.2 Ω
CL = 47 pF
R(ISO) = 28 Ω
CL = 100 pF
R(ISO) = 54.9 Ω
CL = 10 pF
R(ISO) = 54.9 Ω, CL = 22 pF
200 M
‘
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±15 V
100 k
-100
G = -2, RF = 1 kΩ
RL = 1 kΩ,
G = 5, RF = 806 Ω
G = 2, RF = 1 kΩ
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THS3111
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........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±15 V)
space
NONINVERTING SMALL-SIGNAL NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL
0.1-dB FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 4. Figure 5. Figure 6.
RECOMMENDED RISO 2nd HARMONIC DISTORTION
FREQUENCY RESPONSE vs vs
CAPACITIVE LOAD CAPACITIVE LOAD FREQUENCY
Figure 7. Figure 8. Figure 9.
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-100
-95
-90
-85
-80
-75
-70
0 1 2 3 4 5 6 7 8 9 10
Harmonic Distortion - dBc
VO - Output Voltage Swing - VPP
Gain = 2,
RF = 1 kΩ,
RL = 100Ω,
f= 1 MHz
VS = ±15 V
HD3
HD2
-70
-65
-60
-55
-50
-45
-40
0 1 2 3 4 5 6 7 8 9 10
Harmonic Distortion - dBc
VO - Output Voltage Swing - VPP
Gain = 2,
RF = 1 kΩ,
RL = 100 Ω,
f = 8 MHz
VS = ±15 V
HD3
HD2
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±15 V
100 k
-100
G = -2,
RF = 1 kΩ
RL = 1 kΩ,
G = 5, RF = 806 Ω
G = 2,
RF = 1 kΩ
0
200
400
600
800
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Gain = 1
RL = 100 Ω
RF = 1.5 kΩ
VS = ±15 V
Fall
Rise
0
200
400
600
800
1000
1200
1400
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Fall
Rise
Gain = 1
RL = 1 kΩ
RF = 1.5 kΩ
VS = ±15 V
0
200
400
600
800
1000
1200
1400
0 1 2 3 4 5 6 7 8 9 10
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Fall
Rise
Gain = 2
RL =100 Ω
RF =1 kΩ
VS = ±15 V
-1.5
-1
-0.5
0
0.5
1
1.5
0 2 4 6 8 10 12 14 16 18
t - Time - ns
- Output Voltage - VVO
Gain = -2
RL = 100 Ω
RF = 1.1 kΩ
VS = ±15 V
Rising Edge
Falling Edge
1
10
100
10 100 1 k 10 k 100 k
f - Frequency - Hz
- Current Noise -
Vn
In
- Voltage Noise -
pA/ Hz
nV/ Hz
In+
Vn
In-
0
200
400
600
800
1000
1200
1400
1600
0 1 2 3 4 5 6 7 8 9 10
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Fall
Rise
Gain = 2
RL =1 kΩ
RF =1 kΩ
VS = ±15 V
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (±15 V) (continued)
space
3rd HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 10. Figure 11. Figure 12.
SLEW RATE SLEW RATE SLEW RATE
vs vs vs
OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP
Figure 13. Figure 14. Figure 15.
SLEW RATE NOISE
vs vs
OUTPUT VOLTAGE STEP FREQUENCY SETTLING TIME
Figure 16. Figure 17. Figure 18.
10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
0 2 4 6 8 10 12 14 16 18 20
t - Time - ns
- Output Voltage - VVO
Gain = -2
RL = 100 Ω
RF = 1.1 kΩ
VS = ±15 V
Rising Edge
Falling Edge
0
1
2
3
4
5
6
2 3 4 5 6 7 8 9 10 11 12 13 14 15
- Quiescent Current - mAIQ
VS - Supply Voltage - ±V
TA = 25 °C
TA = -40 °C
TA = 85 °C
-40
0
0.5
1
1.5
2
2.5
3
3.5
4
-30-20-10 0 10 20 30 40 50 60 70 80 90
VS = ±5 V
VS = ±15 V
TC - Case Temperature - °C
- Input Offset Voltage - mV
VOS
110
100
90
80
70
60
50
40
30
20
10
0
TransimpedanceGain dB-
Frequency MHz-
0.1 110 100 1000
V = 15Vand 5V
S± ±
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±15 V) (continued)
space
QUIESCENT CURRENT OUTPUT VOLTAGE
vs vs
SETTLING TIME SUPPLY VOLTAGE LOAD RESISTANCE
Figure 19. Figure 20. Figure 21.
INPUT BIAS AND
OFFSET CURRENT INPUT OFFSET VOLTAGE TRANSIMPEDANCE
vs vs vs
CASE TEMPERATURE CASE TEMPERATURE FREQUENCY
Figure 22. Figure 23. Figure 24.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
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0 10 20 30 40 50 60 70 80
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
t - Time - ns
- Output Voltage - VVO
Output
Input
Gain = -5,
RL = 100 Ω,
RF = 909 Ω,
VS = ±15 V
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 10 20 30 40 50 60 70 80
t - Time - ns
- Output Voltage - VVO
Output
Input
Gain = 2,
RL = 100 Ω,
RF = 1 kΩ,
VS = ±15 V
0
10
20
30
40
50
60
100 k 1 M 10 M 100 M
70
CMRR VS = ±15 V
Rejection Ratio - dB
f - Frequency - Hz
PSRR-
PSRR+
-20
-15
-10
-5
0
5
10
15
20
0 0.2 0.4 0.6 0.8 1-5
-2.5
0
2.5
5
t - Time - µs
- Input Voltage - VVI
Gain = 4,
RL = 100 Ω,
RF = 681 Ω,
VS = ±15 V
- Output Voltage - VVO
0
0.05
0.1
0.15
0.2
0.25
0.3
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Gain - %
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Phase -
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
5
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (±15 V) (continued)
space
REJECTION RATIO
vs NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL
FREQUENCY TRANSIENT RESPONSE TRANSIENT RESPONSE
Figure 25. Figure 26. Figure 27.
DIFFERENTIAL GAIN DIFFERENTIAL PHASE
vs vs
OVERDRIVE RECOVERY TIME NUMBER OF LOADS NUMBER OF LOADS
Figure 28. Figure 29. Figure 30.
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Product Folder Link(s): THS3110 THS3111
−0.5
0
0.5
1
1.5
0 0.1 0.2 0.3 0.4 0.5 −1
0
1
2
3
4
5
6
t − Time − ms
− Output Voltage Level − VVO
Powerdown Pulse
PowerDown Pulse − V
Output Voltage
0.6 0.7
Gain = 5,
VI = 0.1 Vdc
RL = 100 Ω
VS = ±15 V and ±5 V
0
50
100
150
200
250
300
350
3 5 7 9 11 13 15
TA = -40°C
VS - Supply Voltage - ±V
Powerdown Quiescent Current -
TA = 85°C
Aµ
TA = 25°C
0.01
0.1
1
10
100
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Gain = 2,
RF = 1 kΩ,
RF = 100 Ω,
VS = ±15 V
ZO- Closed-Loop Output Impedance - Ω
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±15 V) (continued)
space
CLOSED-LOOP OUTPUT POWER-DOWN QUIESCENT
IMPEDANCE CURRENT
vs vs TURN-ON AND TURN-OFF
FREQUENCY SUPPLY VOLTAGE TIME DELAY
Figure 31. Figure 32. Figure 33.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
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100 M
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 1 G
f - Frequency - Hz
Inverting Gain - dB
G = -1, RF = 1 kΩ
G = -10, RF = 649 Ω
G = -5, RF = 909 Ω
G = -2, RF = 1.1 kΩ
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
100 M
−4
−2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 1 G
f − Frequency − Hz
Noninverting Gain − dB
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
G = 10, RF = 604 Ω
G = 5, RF = 806 Ω
G = 2, RF = 1.15 kΩ
G = 1, RF = 1.5 kΩ
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
100 k 1 M 10 M 100 M
Gain = 2,
RF = 1.15 kΩ,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
f - Frequency - Hz
Noninverting Gain - dB
-4
-2
0
2
4
6
8
10
12
14
16
110 M 100 M 1 G
f - Frequency - Hz
G = -5, RF = 909 Ω
G =-12, RF = 1 kΩ
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
Inverting Gain - dB
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
G = 5, RF = 806 Ω
G = 2, RF = 1.15 kΩ
VO = 4 VPP,
RL = 100 Ω,
VS = ±5 V
0
100
200
300
400
500
600
700
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Gain = 1
RL = 100 Ω
RF = 1.5 kΩ
VS = ±5 V
Fall
Rise
0
100
200
300
400
500
600
700
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Gain = 1
RL = 1 kΩ
RF = 1.5 kΩ
VS = ±5 V Fall
Rise
0
100
200
300
400
500
600
700
800
0123456
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Gain = 2
RL = 1 kΩ
RF = 1 kΩ
VS = ±5 V Fall
Rise
0
100
200
300
400
500
600
700
800
0 1 2 3 4 5 6
SR - Slew Rate - V/
VO - Output Voltage -VPP
sµ
Gain = 2
RL = 100 Ω
RF = 1 kΩ
VS = ±5 V
Fall
Rise
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (±5 V)
space
NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE FREQUENCY RESPONSE 0.1-dB FLATNESS
Figure 34. Figure 35. Figure 36.
SLEW RATE
NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL vs
FREQUENCY RESPONSE FREQUENCY RESPONSE OUTPUT VOLTAGE STEP
Figure 37. Figure 38. Figure 39.
SLEW RATE SLEW RATE SLEW RATE
vs vs vs
OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP
Figure 40. Figure 41. Figure 42.
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Product Folder Link(s): THS3110 THS3111
-100
-95
-90
-85
-80
-75
-70
-65
0 1 2 3 4 5 6 7
Harmonic Distortion - dBc
VO - Output Voltage Swing - VPP
HD2
Gain = 2,
RF = 1.15 kΩ
RL = 100 Ω,
f= 1 MHz
VS = ±5 V
HD3
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
100 k
-100
G = -2, RF = 1 kΩ
RL = 1 kΩ,
G = 5, RF = 681 Ω
G = 2, RF = 681 Ω
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
100 k
-100
G = -2, RF = 1 kΩ
RL = 1 kΩ,
G = 5,
RF = 681 Ω
G = 2,
RF = 681 Ω
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 10 20 30 40 50 60 70 80
t - Time - ns
- Output Voltage - VVO
Gain = 2
RL = 100 Ω
RF = 1.15 kΩ
VS = ±5 V
Input
Output
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
0 10 20 30 40 50 60 70 80
t - Time - ns
- Output Voltage - VVO
Output
Input
Gain = -5,
RL = 100 Ω,
RF = 909 Ω,
VS = ±5 V
-90
-80
-70
-60
-50
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - VPP
HD2
Gain = 2,
RF = 1 kΩ
RL = 100 Ω,
f= 8 MHz
VS = ±5 V
HD3
-5
-4
-3
-2
-1
0
1
2
3
4
5
0.2 0.4 0.6 0.8 1 -1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
t - Time - µs
- Input Voltage - VVI
Gain = 4,
RL = 100 Ω,
RF = 909 Ω,
VS = ±5 V
- Output Voltage - VVO
0
0
10
20
30
40
50
60
70
100 k 1 M 10 M 100 M
VS = ±5 V
Rejection Ratio - dB
f - Frequency - Hz
PSRR-
CMRR
PSRR+
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±5 V) (continued)
space
2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
Figure 43. Figure 44. Figure 45.
HARMONIC DISTORTION
vs NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL
OUTPUT VOLTAGE SWING TRANSIENT RESPONSE TRANSIENT RESPONSE
Figure 46. Figure 47. Figure 48.
REJECTION RATIO
vs
OVERDRIVE RECOVERY TIME FREQUENCY
Figure 49. Figure 50.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): THS3110 THS3111
_
+
THS3110
RF
1 kΩ
49.9 Ω
0.1 µF 6.8 µF
-VS
-15 V
RG
50 Ω Source
+
VI
0.1 µF 6.8 µF
+
+VS
15 V
49.9 Ω
50 Ω LOAD
1 kΩ
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
APPLICATION INFORMATION
MAXIMUM SLEW RATE FOR REPETITIVE
SIGNALS
The THS3110 and THS3111 are recommended for
high slew rate pulsed applications where the internal
nodes of the amplifier have time to stabilize between
pulses. It is recommended to have at least 20-ns
delay between pulses.
The THS3110 and THS3111 are not recommended
for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/μs. Using the
part in these applications results in excessive current
draw from the power supply and possible device
damage.
For applications with high slew rate, repetitive signals,
the THS3091 and THS3095 (single), or THS3092 and
THS3096 (dual) are recommended. Figure 51. Wideband, Noninverting Gain
Configuration
WIDEBAND, NONINVERTING OPERATION
The THS3110 and THS3111 are unity-gain stable, Current-feedback amplifiers are highly dependent on
100-MHz, current-feedback operational amplifiers, the feedback resistor RFfor maximum performance
designed to operate from a ±5-V to ±15-V power and stability. Table 1 shows the optimal gain setting
supply. resistors RFand RGat different gains to give
maximum bandwidth with minimal peaking in the
Figure 51 shows the THS3111 in a noninverting gain frequency response. Higher bandwidths can be
of 2-V/V configuration typically used to generate the achieved, at the expense of added peaking in the
performance curves. Most of the curves were frequency response, by using even lower values for
characterized using signal sources with 50-Ωsource RF. Conversely, increasing RFdecreases the
impedance, and with measurement equipment bandwidth, but stability is improved.
presenting a 50-Ωload impedance.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3110 AND THS3111 RFAND RGVALUES FOR MINIMAL PEAKING WITH RL= 100 Ω
GAIN (V/V) SUPPLY VOLTAGE (V) RG(Ω) RF(Ω)
±15 — 1.5 k
1±5 — 1.5 k
±15 1 k 1 k
2±5 1.15 k 1.15 k
±15 200 806
5±5 200 806
±15 66.5 604
10 ±5 66.5 604
±15 1 k 1 k
–1 ±5 1 k 1 k
–2 ±15 and ±5 549 1.1 k
–5 ±15 and ±5 182 909
–10 ±15 and ±5 64.9 649
16 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
_
+
THS3110
49.9 Ω
50 Ω Source
VI
+VS
RF
1 kΩ
RG
1 kΩ
+VS
2
+VS
2
_
+
THS3110
549 Ω
50 Ω Source
VI
VS
RF
1.1 kΩ
+VS
2+VS
2
56.2 Ω
RG
RT
RT
49.9 Ω
49.9 Ω
50 Ω LOAD
50 Ω LOAD
_
+
THS3110
RG
549 Ω
0.1 µF 6.8 µF
-VS
-15 V
50 Ω Source
+
VI
0.1 µF 6.8 µF
+
+VS
15 V
RF
1.1 kΩ
RM
56.2 Ω
49.9 Ω
50 Ω LOAD
+
-
75 Ω75 Ω
75 Ω
75 Ω
75 Ω
n Lines
VO(1)
VO(n)
75-Ω Transmission Line
VI
1 kΩ
-15 V
15 V
1 kΩ
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
WIDEBAND, INVERTING OPERATION
Figure 52 shows the THS3111 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 51 are
retained in an inverting circuit configuration.
Figure 53. DC-Coupled, Single-Supply Operation
Figure 52. Wideband, Inverting Gain
Configuration Video Distribution
The wide bandwidth, high slew rate, and high output
SINGLE-SUPPLY OPERATION drive current of the THS3110 and THS3111 match
The THS3110 and THS3111 have the capability to the demands for video distribution for delivering video
operate from a single-supply voltage ranging from signals down multiple cables. To ensure high signal
10 V to 30 V. When operating from a single power quality with minimal degradation of performance, a
supply, biasing the input and output at mid-supply 0.1-dB gain flatness should be at least 7x the
allows for the maximum output voltage swing. The passband frequency to minimize group delay
circuits shown in Figure 53 shows inverting and variations from the amplifier. A high slew rate
noninverting amplifiers configured for single supply minimizes distortion of the video signal, and supports
operations. component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality.
Figure 54. Video Distribution Amplifier
Application
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS3110 THS3111
_
+
VS
-VS
49.9 Ω
806 Ω
Ferrite Bead
1 µF
200 Ω
VS
100 Ω LOAD
0
10
20
30
40
50
60
10 100
CL - Capacitive Load - pF
Recommended R Ω
Gain = 5,
RL = 100 Ω,
VS = ±15 V
ISO -
_
+
VS
-VS
49.9 Ω
806 Ω
5.11 Ω
1 µF
200 Ω
VS
100 Ω LOAD
RISO
_
+
VS
-VS
49.9 Ω
5.11 Ω
1 µF
200 Ω
VS
27 pF 806 Ω
RF
RG750 Ω100 Ω LOAD
RIN
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
Driving Capacitive Loads frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
Applications such as FET drivers and line drivers can high frequency. Use a ferrite chip with similar
be highly capacitive and cause stability problems for impedance to RISO, 20 Ωto 50 Ω, at 100 MHz and
high-speed amplifiers. low impedance at dc.
Figure 55 through Figure 61 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier feedback path. See Figure 55 for
recommended resistor values versus capacitive load.
Figure 57. Ferrite Bead to Isolate Capacitive Load
Figure 58 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
Figure 55. Recommended RISO vs Capacitive capacitor. The resistor RIN in series with the negative
Load input is used to stabilize the amplifier and should be
equal to the recommended value of RFat unity gain.
Replacing RIN with a ferrite of similar impedance at
Placing a small series resistor, RISO, between the about 100 MHz as shown in Figure 59 gives similar
amplifier output and the capacitive load, as shown in results with reduced dc offset and low frequency
Figure 56, is an easy way of isolating the load noise. (See the Additional Reference Material section
capacitance. for expanding the usability of current-feedback
amplifiers.)
Figure 56. Resistor to Isolate Capacitive Load
Using a ferrite chip in place of RISO, as shown in
Figure 57, is another approach of isolating the output Figure 58. Feedback Technique with Input
of the amplifier. The ferrite impedance characteristic Resistor for Capacitive Load
versus frequency is useful to maintain the low
18 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
_
+
VS
-VS
49.9 Ω
5.11 Ω
1 µF
200 Ω
VS
27 pF 806 Ω
RF
RGFB 100 Ω LOAD
FIN
_
+
VS
-VS
_
+
VS
-VS-VS
VS
301 Ω
301 Ω
66.5 Ω
5.11 Ω
5.11 Ω
_
+
VS
-VS
806 Ω
5.11 Ω
200 Ω
VS
_
+
VS
-VS
806 Ω
5.11 Ω
200 Ω
24.9 Ω
24.9 Ω
1 nF
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
Figure 61 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
Figure 59. Feedback Technique with Input Ferrite
Bead for Capacitive Load
Figure 60 shows how to use two amplifiers in parallel
to double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load Figure 61. PowerFET Drive Circuit
faster like when driving large FET transistors.
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
The THS3110 features a power-down pin (PD) which
lowers the quiescent current from 4.8 mA down to
270 μA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
REF pin voltage in the absence of an applied voltage,
putting the amplifier in the normal on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
Figure 60. Parallel Amplifiers for Higher Output rails and are given in the specification tables. Below
Drive the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS3110 THS3111
0
200
400
600
800
1000
1200
1400
1600
1800
2000
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Powerdown Output Impedance - Ω
Gain = 2
RF = 1 kΩ
VS = ±15 V and ±5 V
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
Figure 62 shows the total system output impedance POWER-DOWN REFERENCE PIN
which includes the amplifier output impedance in OPERATION
parallel with the feedback plus gain resistors, which In addition to the power-down pin, the THS3110
cumulate to 1870 Ω.Figure 51 shows this circuit features a reference pin (REF) which allows the user
configuration for reference. to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤REF + 0.8 V for enable
PD ≥REF + 2.0 V for disable
where the usable range at the REF pin is
VS– ≤VREF ≤(VS+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
Figure 62. Power-Down Output Impedance vs thresholds to Vmidrail + 0.8 V and Vmidrail +2V
Frequency respectively.
As with most current feedback amplifiers, the internal POWER-DOWN THRESHOLD VOLTAGE LEVELS
architecture places some limitations on the system SUPPLY REFERENCE PIN ENABLE DISABLE
when in power-down mode. Most notably is the fact VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V)
that the amplifier actually turns ON if there is a ±0.7 V ±15, ±5 0.0 0.8 2.0
or greater difference between the two input nodes ±15 2.0 2.8 4
(V+ and V–) of the amplifier. If this difference ±15 –2.0 –1.2 0
exceeds ±0.7 V, the output of the amplifier creates an ±5 1.0 1.8 3
output voltage equal to approximately [(V+ – V–) –
0.7 V] × Gain. Also, if a voltage is applied to the ±5 –1.0 –0.2 1
output while in power-down mode, the V– node +30 15 15.8 17
voltage is equal to VO(applied) × RG/(RF+ RG). For low +10 5.0 5.8 7
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the Note that if the REF pin is left unterminated, it floats
aforementioned behavior. to the positive rail and falls outside of the
recommended operating range given above (VS– ≤
The time delays associated with turning the device on VREF ≤VS+ – 4 V). As a result, it no longer serves as
and off are specified as the time it takes for the a reliable reference for the PD pin and the
amplifier to reach either 10% or 90% of the final enable/disable thresholds given above no longer
output voltage. The time delays are in the order of apply. If the PD pin is also left unterminated, it also
microseconds because the amplifier moves in and out floats to the positive rail and the device is disabled. If
of the linear mode of operation in these transitions. balanced, split supplies are used (±VS) and the REF
and PD pins are grounded, the device is enabled.
20 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
PRINTED-CIRCUIT BOARD LAYOUT • Connections to other wideband devices on the
TECHNIQUES FOR OPTIMAL board may be made with short direct traces or
PERFORMANCE through onboard transmission lines. For short
connections, consider the trace and the input to
Achieving optimum performance with a the next device as a lumped capacitive load.
high-frequency amplifier, such as the THS3110 and Relatively wide traces [0.05 inch (1,3 mm) to 0.1
THS3111, requires careful attention to board layout inch (2,54 mm)] should be used, preferably with
parasitic and external component types. ground and power planes opened up around
Recommendations that optimize performance include: them. Estimate the total capacitive load and
• Minimize parasitic capacitance to any ac ground determine if isolation resistors on the outputs are
for all of the signal I/O pins. Parasitic capacitance necessary. Low parasitic capacitive loads (< 4 pF)
on the output and input pins can cause instability. may not need an RSsince the THS3110 and
To reduce unwanted capacitance, a window THS3111 are nominally compensated to operate
around the signal I/O pins should be opened in all with a 2-pF parasitic load. Higher parasitic
of the ground and power planes around those capacitive loads without an RSare allowed as the
pins. Otherwise, ground and power planes should signal gain increases (increasing the unloaded
be unbroken elsewhere on the board. phase margin). If a long trace is required, and the
• Minimize the distance [< 0.25 inch (6,35 mm)] 6-dB signal loss intrinsic to a doubly-terminated
from the power-supply pins to high frequency transmission line is acceptable, implement a
0.1-μF and 100-pF decoupling capacitors. At the matched impedance transmission line using
device pins, the ground and power plane layout microstrip or stripline techniques (consult an ECL
should not be in close proximity to the signal I/O design handbook for microstrip and stripline layout
pins. Avoid narrow power and ground traces to techniques). A 50-Ωenvironment is not necessary
minimize inductance between the pins and the onboard, and in fact, a higher impedance
decoupling capacitors. The power-supply environment improves distortion as shown in the
connections should always be decoupled with distortion versus load plots. With a characteristic
these capacitors. Larger (6.8 μF or more) board trace impedance based on board material
tantalum decoupling capacitors, effective at lower and trace dimensions, a matching series resistor
frequency, should also be used on the main into the trace from the output of the
supply pins. These may be placed somewhat THS3110/THS3111 is used as well as a
farther from the device and may be shared among terminating shunt resistor at the input of the
several devices in the same area of the PC board. destination device. Remember also that the
terminating impedance is the parallel combination
• Careful selection and placement of external of the shunt resistor and the input impedance of
components preserve the high-frequency the destination device: this total effective
performance of the THS3110 and THS3111. impedance should be set to match the trace
Resistors should be a very low reactance type. impedance. If the 6-dB attenuation of a
Surface-mount resistors work best and allow a doubly-terminated transmission line is
tighter overall layout. Again, keep their leads and unacceptable, a long trace can be
PC board trace length as short as possible. Never series-terminated at the source end only. Treat
use wirewound-type resistors in a high-frequency the trace as a capacitive load in this case. This
application. Because the output pin and inverting does not preserve signal integrity as well as a
input pins are the most sensitive to parasitic doubly-terminated line. If the input impedance of
capacitance, always position the feedback and the destination device is low, there is some signal
series output resistors, if any, as close as possible attenuation due to the voltage divider formed by
to the inverting input pins and output pins. Other the series output into the terminating impedance.
network components, such as input termination
resistors, should be placed close to the • Socketing a high-speed part like the THS3110 and
gain-setting resistors. Even with a low parasitic THS3111 is not recommended. The additional
capacitance shunting the external resistors, lead length and pin-to-pin capacitance introduced
excessively high resistor values can create by the socket can create an extremely
significant time constants that can degrade troublesome parasitic network which can make it
performance. Good axial metal-film or almost impossible to achieve a smooth, stable
surface-mount resistors have approximately 0.2 frequency response. Best results are obtained by
pF in shunt with the resistor. For resistor values soldering the THS3110/THS3111 parts directly
greater than 2.0 kΩ, this parasitic capacitance can onto the board.
add a pole and/or a zero that can affect circuit
operation. Keep resistor values as low as
possible, consistent with load driving
considerations.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS3110 THS3111
0.205
(5,21)
0.060
(1,52)
0.013
(0,33)
0.017
(0,432)
0.025
(0,64)
0.094
(2,39)
0.040
(1,01)
0.035
(0,89)
0.030
(0,76)
0.075
(1,91)
0.010
vias
(0,254)
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
PowerPAD DESIGN CONSIDERATIONS PowerPAD LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern as shown in
The THS3110 and THS3111 are available in a Figure 64. There should be etch for the leads as
thermally-enhanced PowerPAD family of packages. well as etch for the thermal pad.
These packages are constructed using a downset
leadframe upon which the die is mounted (see
Figure 63a and Figure 63b). This arrangement results
in the lead frame being exposed as a thermal pad on
the underside of the package (see Figure 63c).
Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be
achieved by providing a good thermal path away from
the thermal pad. Note that devices such as the
THS311x have no electrical connection between the
PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the Dimensions are in inches (mm).
package into either a ground plane or other heat
dissipating device. Figure 64. DGN PowerPAD PCB Etch and
Via Pattern
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of 2. Place five holes in the area of the thermal pad.
surface mount with the, heretofore, awkward These holes should be 0.01 inch (0,254 mm) in
mechanical methods of heatsinking. diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3110/THS3111 IC. These additional vias
may be larger than the 0.01-inch (0,254 mm)
diameter vias directly under the thermal pad.
They can be larger because they are not in the
thermal pad area to be soldered so that wicking
Figure 63. Views of Thermal Enhanced Package is not a problem.
4. Connect all holes to the internal ground plane.
Although there are many ways to properly heatsink Note that the PowerPAD is electrically isolated
the PowerPAD package, the following steps illustrate from the silicon and all leads. Connecting the
the recommended approach. PowerPAD to any potential voltage such as VS–,
is acceptable as there is no electrical connection
space to the silicon.
space 5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
space connection methodology. Web connections have
space a high thermal resistance connection that is
useful for slowing the heat transfer during
space soldering operations. This makes the soldering of
space vias that have plane connections easier. In this
application, however, low thermal resistance is
space desired for the most efficient heat transfer.
space Therefore, the holes under the
THS3110/THS3111 PowerPAD package should
space make their connection to the internal ground
plane with a complete connection around the
space
22 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
T =125 C
J°
T Free-AirTemperature C
A- - °
P =
DMax
T T-
Max A
qJA
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
entire circumference of the plated-through hole. Maximum power dissipation levels are depicted in
Figure 65 for the available packages. The data for the
6. The top-side solder mask should leave the PowerPAD packages assume a board layout that
terminals of the package and the thermal pad follows the PowerPAD layout guidelines referenced
area with its five holes exposed. The bottom-side above and detailed in the PowerPAD application note
solder mask should cover the five holes of the (literature number SLMA002). Figure 65 also
thermal pad area. This prevents solder from illustrates the effect of not soldering the PowerPAD to
being pulled away from the thermal pad area a PCB. The thermal impedance increases
during the reflow process. substantially which may cause serious heat and
7. Apply solder paste to the exposed thermal pad performance issues. Be sure to always solder the
area and all of the IC terminals. PowerPAD to the PCB for optimum performance.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3110 and THS3111 incorporate automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately +160°C. When the junction
temperature reduces to approximately +140°C, the
amplifier turns on again. But, for maximum
performance and reliability, the designer must take
care to ensure that the design does not exceed a
junction temperature of +125°C. Between +125°C Results are with no airflow and PCB size = 3 in × 3 in (7,62 mm ×
7,62 mm); θJA = 58.4°C/W for MSOP-8 with PowerPAD (DGN); θJA
and +150°C, damage does not occur, but the = 95°C/W for SOIC-8 High-K Test PCB (D); θJA = 158°C/W for
performance of the amplifier begins to degrade and MSOP-8 with PowerPAD, without solder.
long term reliability suffers. The thermal
characteristics of the device are dictated by the Figure 65. Maximum Power Distribution
package and the PC board. Maximum power vs Ambient Temperature
dissipation for a given package can be calculated
using the following formula. When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
(1) dissipation, but also dynamic power dissipation. Often
Where: times, this is difficult to quantify because the signal
• PDMax is the maximum power dissipation in the pattern is inconsistent, but an estimate of the RMS
amplifier (W) power dissipation can provide visibility into a possible
• TMax is the absolute maximum junction problem.
temperature (°C)
• TAis the ambient temperature (°C) DESIGN TOOLS
•θJA =θJC +θCA Evaluation Fixtures, Spice Models, and
•θJC is the thermal coefficient from the silicon Application Support
junctions to the case (°C/W)
•θCA is the thermal coefficient from the case to Texas Instruments is committed to providing its
ambient air (°C/W) customers with the highest quality of applications
support. To support this goal an evaluation board has
For systems where heat dissipation is more critical, been developed for the THS3110 and THS3111
the THS3110 and THS3111 are offered in an operational amplifiers. The board is easy to use,
MSOP-8 with PowerPAD package offering even allowing for straightforward evaluation of the device.
better thermal performance. The thermal coefficient The evaluation board can be ordered through the
for the PowerPAD packages are substantially Texas Instruments web site, www.ti.com, or through
improved over the traditional SOIC. your local Texas Instruments sales representative.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): THS3110 THS3111
TP2GND
J2
+
C2
VS−
J7
C4 C6
C1
J1
+
FB1
C5 C3
FB2
VS−
VS+
VS+
R4
J4
Vin+
R8A
2
3
6
7
41
J8
Vs+
R2
Z2
J7
R1
J6
Vout
Vs −
R3
J5
Vin−
_
+
PD
8
R8B
R5 Z1
TP1
R6
0
R7BR7A
REF
1
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF-amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS3111 is available through the Texas
Instruments web site (www.ti.com). The product
information center (PIC) is also available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. They are not intended to model
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in their small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
Figure 67. THS3110 EVM Board Layout
(Top Layer)
NOTE: The Edge number for the THS3111 is
6445587.
Figure 66. THS3110 EVM Circuit Configuration
Figure 68. THS3110 EVM Board Layout
(Bottom Layer)
24 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
THS3110
THS3111
www.ti.com
........................................................................................................................................ SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009
Table 2. Bill of Materials
THS3110DGN and THS3111DGN EVM
REFERENCE PCB MANUFACTURER'S
ITEM DESCRIPTION SMD SIZE DESIGNATOR QTY PART NUMBER (1)
1 Bead, ferrite, 3 A, 80 Ω1206 FB1, FB2 2 (Steward) HI1206N800R-00
Capacitor 6.8 μF, tantalum,
2 D C1, C2 2 (AVX) TAJD685K035R
35 V, 10%
3 Open 0805 R5, Z1 2
Capacitor 0.1 μF, ceramic, X7R, 50
4 0805 C3, C4 2 (AVX) 08055C104KAT2A
V
Capacitor 100 pF, ceramic, NPO,
5 0805 C5, C6 2 (AVX) 08051A101JAT2A
100 V
6 Resistor, 0 Ω, 1/8 W, 1% 0805 R6(2) 1 (Phycomp) 9C08052A0R00JLHFT
7 Resistor, 750 Ω, 1/8 W, 1% 0805 R3, R4 2 (Phycomp) 9C08052A7500FKHFT
8 Open 1206 R7A, Z2 2
9 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R2, R8A 2 (Phycomp) 9C12063A49R9FKRFT
10 Resistor, 53.6 Ω, 1/4 W, 1% 1206 R1 1 (Phycomp) 9C12063A53R6FKRFT
11 Open 2512 R7B, R8B 2
Header, 0.1" (2,54 mm) CTRS,
12 3 Pos. JP1(2) 1 (Sullins) PZC36SAAN
0.025" (6,35 mm) SQ pins
13 Shunts JP1(2) 1 (Sullins) SSC02SYAN
Jack, banana receptance,
14 J1, J2, J3 3 (SPC) 813
0.25" (6,35 mm) dia. hole
15 Test point, red J7(2), J8(2), TP1 3 (Keystone) 5000
16 Test point, black TP2 1 (Keystone) 5001
17 Connector, SMA PCB jack J4, J5, J6 3 (Amphenol) 901-144-8RFX
Standoff, 4-40 hex,
18 4 (Keystone) 1808
0.625" (15,875 mm) length
Screw, Phillips, 4-40,
19 4 SHR-0440-016-SN
0.250" (6,35 mm)
20 IC, THS3110 U1 1 (TI) THS3110DGN
21 Board, printed-circuit (THS3110) 1 (TI) EDGE # 6445586
22 IC, THS3111 U1 1 (TI) THS3111DGN
23 Board, printed-circuit (THS3111) 1 (TI) EDGE # 6445587
(1) Manufacturer part numbers are used for test purposes only.
(2) Applies to the THS3110DGN EVM only.
ADDITIONAL REFERENCE MATERIAL
• PowerPAD Made Easy, application brief (SLMA004)
• PowerPAD Thermally-Enhanced Package, technical brief (SLMA002)
• Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
• Current Feedback Analysis and Compensation (SLOA021)
• Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
• Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
• Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): THS3110 THS3111
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2008) to Revision E ...................................................................................................... Page
• Changed Power-Down Characteristics, Power-down quiescent current test conditions of VS= ±15 V Electrical
Characteristics ...................................................................................................................................................................... 5
• Changed Power-Down Characteristics, PD pin bias current parameter of VS= ±15 V Electrical Characteristics ............... 5
• Changed Power-Down Characteristics, Power-down quiescent current test conditions of VS= ±5 V Electrical
Characteristics ...................................................................................................................................................................... 7
• Changed Power-Down Characteristics, PD pin bias current parameter of VS= ±5 V Electrical Characteristics ................. 7
• Added caption title to Figure 56 .......................................................................................................................................... 18
• Added caption title to Figure 57 .......................................................................................................................................... 18
• Added caption title to Figure 58 .......................................................................................................................................... 18
• Added caption title to Figure 59 .......................................................................................................................................... 19
• Added caption title to Figure 60 .......................................................................................................................................... 19
• Changed the first sentence of the second paragraph of Saving Power with Power-Down Functionality section .............. 19
Changes from Revision C (February, 2007) to Revision D ............................................................................................ Page
• Changed VS= ±15 V Transimpedance specifications from 1.5 MΩ(typ) to 1 MΩ(typ); 1 MΩ(at +25°C) to 0.75 MΩ;
0.7 MΩ(over temperature) to 0.5 MΩ.................................................................................................................................. 4
• Changed VS= ±15 V Input offset voltage specifications from 1.5 mV (typ) to 3 mV (typ); 6 mV (at +25°C) to 10 mV;
8 mV (over temperature) to 12 mV ....................................................................................................................................... 4
• Changed VS= ±15 V +PSRR specifications from 83 dB to 75 dB (typ); from 75 dB to 65 dB (at +25°C); from 70 dB
(over temperature) to 60 dB .................................................................................................................................................. 5
• Changed VS= ±15 V –PSRR specifications from 78 dB to 69 dB (typ); from 70 dB to 60 dB (at +25°C); from 66 dB
(over temperature) to 55 dB .................................................................................................................................................. 5
• Changed VS= ±5 V Transimpedance specifications from 1.6 MΩ(typ) to 1 MΩ(typ); 1 MΩ(at +25°C) to 0.75 MΩ;
0.7 MΩ(over temperature) to 0.5 MΩ.................................................................................................................................. 6
• Changed VS= ±5 V Input offset voltage specifications from 3 mV (typ) to 6 mV (typ); 6 mV (at +25°C) to 10 mV; 8
mV (over temperature) to 12 mV .......................................................................................................................................... 6
• Changed VS= ±5 V +PSRR specifications from 80 dB to 71 dB (typ); from 72 dB to 62 dB (at +25°C); from 67 dB
(over temperature) to 57 dB .................................................................................................................................................. 7
• Changed VS= ±5 V –PSRR specifications from 75 dB to 66 dB (typ); from 67 dB to 57 dB (at +25°C); from 62 dB
(over temperature) to 52 dB .................................................................................................................................................. 7
• Corrected Typical Characteristic figure numbering errors from previous version ................................................................ 9
• Updated ±15 V Transimpedance vs Frequency characteristic graph ................................................................................. 11
26 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3110 THS3111
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS3110DGN PREVIEW MSOP-
PowerPAD DGN 8 TBD Call TI Call TI
THS3110DGNR PREVIEW MSOP-
PowerPAD DGN 8 TBD Call TI Call TI
THS3110ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3110IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111DGN PREVIEW MSOP-
PowerPAD DGN 8 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS3111DGNR PREVIEW MSOP-
PowerPAD DGN 8 TBD Call TI Call TI
THS3111ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3111IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS3110IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS3110IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS3111CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS3111CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS3111IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS3111IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS3110IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS3110IDR SOIC D 8 2500 367.0 367.0 35.0
THS3111CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS3111CDR SOIC D 8 2500 367.0 367.0 35.0
THS3111IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS3111IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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