_<SC GG nerahi Description The MAX696/697 supervisory circuits reduce the complexity and number of components required for pawer supply monitoring and battery control functions if microprocessor systems. These include yvP reset and backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warn- ing. The MAX696/697 significantly improves system reliability and accuracy compared to that obtained with separate ICs or discrete components. The MAX696 and MAX697 are supplied in 16 pin packages and pertorm six functions: 1. A Reset output during power-up, power-down and brownout conditions. The threshold for this low line reset is adjustable by an external voltage divider. 2. A Reset pulse if the optional watchdog timer has not been toggled within a specified time. 3. Individual outputs for low tine and watchdog fault conditions. 4, The Reset time may be left at its default value of 50 ms. or may be varied with an external capacitor or clock pulses. 5. A separate 1.3 volt threshald detector for power fail warning, low battery detection, ar to monitar a power supply other than Voc. The MAX696 also has battery backup switching for CMOS RAM, CMOS micreprocessor, or other low power logic. The MAX697 lacks baticry backup switching, but has write protection pins (CE\y and CEgy7) for CMOS RAM or EPROM. In addition, it consumes less than 250 microamperes. _. Applications Computers Controllers Intelligent Instruments Automotive Systems Critical uP Power Monitoring Pin Configurations Top View 6} RESET G] AESET aESET RESET woo ele ASP wo tom mAxeo? Pal [Ew ave CEgur Wo! wo! a PFI PFA PFI eh Xr MAAAL/VI Microprocessor Supervisory Circuits _. Features @ Adjustable Low Line monitor and Power Down Reset # Power OK/Reset Time Delay @ Watchdog Timer100ms, 1.6 sec, or adjustable # Minimum Component Count @ 1A Standby Current @ Battery Backup Power Switching (MAX696) @ Onboard Gating of Chip Enable Signals (MAX697) # Separate Monitor for Power Fail or Low Battery Warning __ Ordering Information | ___PART TEMP. RANGE PACKAGE MAXB96C/D Octo +76C Dice MAX696CPE OC to #70G 16 Lead Plastic DIP MAXG96CWE OC to #70C 16 Lead Wide SO MAXG96EPE = -40C 10 +85C 16 Lead Plastic DIP MAXB96EJE - -40C to +85C 16 Lead CERDIP MAX69GEWE -40C to +85G 16 Lead Wide SO MAX696MJE _-S6G to 7125C 16 Lead CERDIP MAx6a7C/D OC te +70C Dice MAX697 CPE OC to +70C 16 Lead Plastic DIP MAX697 CWE OC to +70G 16 Lead Wide SO MAXB97EPE = -40C to. +85C 16 Lead Plastic DIP MAX697EJE - -40C to +B5C 18 Lead CERDIP MAX6Q7EWE _-40C 10 +85G 1B Lead Wide SO MAX6S7MJE 55C to 125C 16 Lead GERDIP __ _____ Typical Operating Circuit [ ~~ ~| pa 75 Yer Your CMOS TAM PGWER | Vaart PAK set uP RESET | = | MAx06 SYSTEM LINE a = a ey LLIN RESET uf REBET Pr FFG uP NMI 3 won vo L UH MAX686 Typical Application SU AXKI SI __. Maxim Integrated Products 1 Cail toll free 1-800-998-8800 for free samples or literature. 69/969XVWMAX696/697 Microprocessor Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect ta GND) VOC cnet eee e nee e eee tees -0.3 to 6.0V VBATT veer evens cee eee eee ee eens -0.3V to &.0V All Other inputs {Note 4) ........ Input Gurrent Vec Veart GND Output Current VOUT cece ccc eee eee All Other Outputs 22.06.02 eee ee Aate-of-Rise, Vpatt, Vee oe ee eee . short circuit protected 2omA 100V us Operating Temperature Range GC osutfia po. ccc ee eet cee OE to 70S E Suffix 20 cee eee .. 40C to +86C M suffix . 86C to +125C Power Dissipation 16 Pin Plastic DIP (Derate 7MW/"G above #70C) 00... 600mWw 16 Pin Small Outline (Derate 7mW/C above +70C) 600mW 16 Pin CERDIP (Derate 10mWiC above +85C} .-..2...--...-. 6OOMW Storage Temperature Range ..........- 64C ta +160C Lead Temperature (Soldering, 10 seconds) ........ 300C Stresses above those listed under "Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings ory and functional operation of the device at inese ar any other conditions above those indicated 1 the operational sections of the specidicanons 18 fot impled, Exposure ia absolute maximum fating conditions for axtended periods may affect device refadulity ELECTRICAL CHARACTERISTICS Voc = full operating range, Veatt = 2.8V, Ts = 25C, unless otherwise noted > PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage Range Ta = Full MAX696 Voc 3.0 5 MAX696 Vaart 20 Voo ay] Vv MAX697 Voc 3.0 a5 Supply Current (MAX687) Ta = Full 460 300 uA BATTERY BACKUP SWITCHING (MAX696) lout = ima, Ta = Full Veo -0.3 Vee -01 Vour Output Voltage lout - 50mA, Ta = Full Ver -0 5 Vec -0.25 v - Let -0.2, Vour in Battery Backup Mode mt anal Moo part -0 Vaate -0.1 Veart -0.02 Vv lout = Ima 15 4 | Supply Current (excludes lout) loyr = SOMA a5 7 mA . Veo = OV, Vaart = 2.8V, Ta = 25C 0.6 1 Supply Current in Battery Backup Mode Vou = OV, Vaart = 2.8V, Ta = Full 10 BA 5.5 > Veo > VeattG.3V Battery Standby Leakage Current Ta = 25C -100 +20 n& Ta = Full -1 +0.02 ua Battery Switchover Threshold Power Up 70 mV Voc-Veart Power Down 50 Battery Switchover Hysteresis 20 mv BATT ON Ouiput Voltage Isink = 1.6m a4 Vv BATT GN Output Short BATT ON = Vour = 2.4V Sink Gurrent 7 mA Circuit Current BATT ON = Vout, Veo - OV 0.5 2.5 25 pa a RESET AND WATCHDOG TIMER Low Line Voltage Threshold {LLyy) Veo = 75V, +3V, Ta = Full 1.25 130 1.45 | v 2 MIAAILSVIMicroprocessor Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) (Vec = full operating range, Veatt ~ 2.8V. Ta = 25C, unless otherwise noted ) PARAMETER CONDITIONS MIN TYP MAX | UNITS Reset Timeout Delay Figure 6. OSG SEL HIGH, Vex = SV 35 50 70 ms Watchdog Timeout Period, Long Period. Vcc SV 1.0 16 225 sec Internal Oscillator Short Pernod, Voc = SV 70 100 140 ms Watchdog Timeout Period, Lang Period 4032 4097 Clock External Clack Short Period 960 1025 Cycles Minimum WDI Input Pulse Width Vir = 04, Vin = SAV, Vero = 5V 260 ns == leink = S00uA, Voc = 2V, Vaart = 0 0.4 Note 3) RESET Output Voltage lame - 1.6MA, 3V < Veg < 5.5V a4 v Isqurce = THA, Veo = SV 350 INE Isiwx = GOOUA, T, - Full o4 LOW LINE and WDO Output Voltage source = Ut, Voc = SV, Ta - Full a5 Vv Output Short Circuit Current RESET , RESET, WOO, LOW LINE 1 3 25 wa WOI Input Threshold Voc 2 5V (Note 2} Logic Low 0.8 v Logic High (MAX696) 3.5 Logic High (MAX697) 3.8 WDI = Vout 20 50 WDI Input Current WDI = QV 50 15 HA POWER FAIL DETECTOR PFI Input Threshald Veco = 3V, 5V 1.2 13 14 v PFl-LlLin Threshold Difference Veo = 3V, 5V +15 +50 mV PFI Input Current +0.01 +25 n& MAx697 -25 +0.01 +25 Luin Input Current nA MAX696 -600 +0.01 +25 Breer Isink = 1.6mA 0.4 Vv PFO Output Voltage source - 1A, Voc = 5V 35 Vv PFO Short Gircuit Source Current PFI = OV, PFO = OV 1 3 25 HA CHIP ENABLE GATING (MAX6S7} ar Vie 0.8 CE IN Thresholds Vie, Vee = BV 40 Vv CE (N Pullup Current 3 pa _. IsinK = 1.6m4 04 CE OUT Output Voltage Isource 800uA Ver -0.5V Vv Isounce = 1uA, Voc - OV Vee -0.05 CE Propagation Delay Veg = 5 80 150 ns OSCILLATOR OSC IN Input Current +2 BA OSC SEL Input Pullup Current 5 BA OSC IN Frequency Range OSC SEL = OV 0 250 kHz OSC IN Frequency OSC SEL - OV kHz with External Capacitor Cosc = 47pF 4 Note 1: Note 2: VIA ALE! The input voltage limits on PFl and WDI may be exceeded providing the input current ts Wmiled to less than 10mA. WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and Vec Is in the operating voltage range. WDI is internally biased to 38% of Voc with an impedance of approximately 125 kilofms. Note 3: Ta = Full Operating Range. 269/969XVWMAX696/697 Microprocessor Supervisory Circuits _. Pin Description NAME PIN MAX696 MAX697 FUNCTION Veo 3 The +5 input. Veatt Backup battery input. Cannect to Ground if a backup battery is not used. Vout The higher of Vec or Vaart is Internally switched to Vout. Connect Your to Vee if Vout and Vest are not used OV ground reference for all signals. 15 RESET goes low whenever LLjy falls belaw 1.3 volts or Voe falls below the Vaatt input voltage. RESET remains low for 5Oms after LLin goes above 1.3 volts RESET also goes low for 50ms if the Watchdog Timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted as shown in Table 1. WDI abl The watchdog input, WOI, is a three level input. If WDI remains either high or law for longer than the watchdog timeout period, RESET pulses law and WDO goes low. The Watchdog Timer is disabled when WDI is left floating or is driven to mid-supply. The timer resets with each transition at the Watchdog Timer Input. PFI is the non-inverting input to the Power Fail Comparator When PFI is less than 13, PFO goes low. Connect PFI te GND or Your when not used See Figure 1. 7 TT oh PFO is the output of the Power Fail Comparator It goes low when PFI 1s less than 1.3. The comparator is turned off and PFO goes low when Vcc is below Vpart. CE IN 13 The input te the CE gating circuit. Connect to GND or Vour if not used. CE OUT 12 CE OUT goes low only when CE IN is low and LL 1s above 1.3V. See Figure 5. BATT ON BATT ON goes high when Vout is internally switched to the Vaart input It goes low when Vaur is internally switched to Vec. The output typically sinks 7mA and can directly drive the base of an external PNP transistor to increase the output current above the 50mA rating of Vaur. LOW LINE LOW LINE goes low when LLin falls belaw 1.3 volts. It returns high as soon as LLiy rises above 1.3 volts. See Figure 5, Reset Timing. RESET 16 RESET is an active high output. It is the inverse RESET O$c SEL When OSC SEL is unconnected or driven high. the internal oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, 1s enabled. OSC SEL has a 3yA internal pullup. See Table 1 OSC IN OSC IN sets the Reset delay timing and Watchdog timeout period when OSC SEL floats or is driven law The timing can also be adjusted by connecting an external capacitor to this pin. See Figure 7, When OSC SEL is high, OSC IN selects between fast and slow Watchdog timeout periods. = Q G 14 14 The Watchdog Quiput, WDO, goes low if WD remains either high or low for longer than the Watchdog timeout periad. WDO is set high by the next transition at WDI. If WDI 1s unconnected or at mid-supply, WDO remains high. WDO also goes high when LOW LINE goes low. 12 NO CONNECT. Leave this pin open. 19 LOW LINE INPUT. LLiy is the CMOS input te_a comparator whose other input is a precision 1.3 volt reference. The output is LOW LINE and is also connected to the reset pulse generator. See Figure 2 Used during Maxim manufacture only. Always ground this pin. /bkisidcisvi_ -__s __ sda pieal Applications MAX696 A typical connection for the MAX696 is shown in Figure 1. CMOS RAM is powered from Voyr. Vout is internally connected to Voc when power is present, or 10 Vaat7 when Ver is less than the battery voltage. Vout Can supply 50mA from Vee, but if mare current is required, an external PNP transistor can be added. When Vee is higher than Vear7, the BATT ON out- put goes low, providing 7A of base drive for the external transistor. When Vcc is tower than Vaart. an internal 2009 MOSFET connects the backup battery to Vout. The quiescent current in the battery backup mode is T#wA maximum when Vor is between OV and Vearr -700mv. Reset Output A voltage detector monitors Vop and generates a RESET output to hold the microprocessors RESET tine low when_LLy, is below 1.34. An internal mone- stable holds RESET low far 50ms after LU, rises above 1.3V. This prevents repeated toggling of RESET even if the Voc power drops out and recovers with each power line cycle. The crystal oscillator normally used to generate the clock for microprocessors takes several milliseconds to start. Since most microprocessors need several clock cycles to reset, RESET must be held low until the microprocessor clock oscillator has started. The power-up RESET pulse lasts 50ms to allow for this oscillator start-up time. An inverted, active high, RESET output is aiso supplied. Microprocessor Supervisory Circuits Power Fail Detector The MAX696 issues a non-maskable interrupt (NMIj to the microprocessor when a power failure occurs. The power line ig monitored via two external resistors connected to the Power Fail Input (PFI). When the voltage at PFI falls below 1.3V, the Power Fail Output (PEG) drives the processor's NMI input low. An earlier power fail warning can be generated if the unregulated DC input of the regulator is available for monitoring. Watchdog Timer The microprocessor drives the WATCHDOG INPUT (WDI} with an 1/0 line. When OSC IN and OSC SEL are unconnected, the microprocessor must toggle the WODI pin once every 1.6 seconds to verify proper soft- ware execution. If a hardware or software failure occurs such that WDI is not toggled, the MAX696 will issue a S0ms RESET pulse after 1.6 seconds. This typically restarts the microprocessors power-up routine. A new RESET pulse is issued every 1.6 seconds until WDI is again strobed. The WATCHDOG OUTPUT (WDO) goes low if the watchdog timer_is not serviced within s timeout period. Once WDO goes low it_remains low until a transition occurs at WDI while RESET is high. The watchdog timer feature can be disabled by leaving WODI unconnected. OSC IN and OSC SEL also allow other watchdog timing options, as shown in Table 1 and Figure 7. MAX697 The MAX697 is nearly identical to the MAX696. The MAX697 lacks the battery backup feature, so it does not have the Vaart, Your, or BATT ON pins. This allows the MAX697 to consume less than 250 micro- amperes, and it allows the inclusion of RAM write protection pins. See Figure 2. +5 Ver WUT Ola Vout CMOS RAM | u wol vg MEAN __|io FEO Wm lis RESET RESET eset 2 MICROPROCESSOR 4 | Vcc BATT ON LT Vaart = 4 BATTERY ) PFI sels = MAX696 om 4 ~ ose in 3 wo cownecrion | ] 086 SEL i "WOME = WHO $ RESET 8 t + SYSTEM STATUS INDICATORS AUDIBLE ALARM OTHER SYSTEM RESET SQUATES 1 Figure 1, MAX696 Typical Application sl AX bl L69/969XVWMAX696/697 Microprocessor Supervisory Circuits MAX696 SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 1.80 1 125 1 : - 12a 1.00 +--+! 100 75 Veo MODE sd mn So SUPPLY CURRENT [mA] a SUPPLY CURRERKT [+A] BATTERY MODE ra) SUPPLY VOLTAGE : MAX697 \ SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE Ty - 2ST | | 200 SUPPLY CURRENT (A) SUPPLY VOLTAGE RESET TIMEOUT DELAY ASA FUNCTION OF SUPPLY VOLTAGE AESET TIMEQUT DELAY [mS] SUPPLY VOLTAGE __ VIA XI 4___ _ Detailed Description Battery-Switchover and Voy, (MAX696) The battery switchover circuit compares Veg to the Veatt input, and connects V5.7 to whichever is higher. Switchover occurs when Ve is 50mV greater than Veatt a8 Voc falls, and when Voc is 70mV more than VeaTt 48 Veg rises (See Figure 3). The switchover comparator has 20mY of hysteresis to prevent repeaied, rapid switching if Veo falls very slowly or remains nearly equal to the battery voltage. When Vee is higher than Vearr, Voc is internally switched to Veyr7 via @ low saturation PNP transistor. Vour has SOMA output current capability. Use an external PNP pass transistor in parallel with the inter- nal transistor if the output current requirement at Vayr exceeds 50mA or if a lower Vee-Voyr voltage differential is desired. The BATT Ny output can directly drive the base of the external transistor. It should be noted that the MAX696 need only supply the average current drawn by the CMOS RAM if there is adequate filtering. Many RAM data sheets specify a 75am maximum supply current, but this peak current spike lasts only 100ns. A O.1yF bypass capacitor at Vout supplies the high instantaneous current, while Vout need only supply the average load current, which is much less. A capacitance of O1yF or greater must be connected to the Vgy7 terminal to ensure stability. A 2000 MOSFET connects the V, input to Vout during battery backup. This MOSFET has very fow input-to-autput differential (dropout voltage} at the Microprocessor Supervisory Circuits low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. When Veco equals Vgar7 the supply current is typically T2uA. When Vee is between OV and (Vpazt -700mV) the typical supply current is onty 600nA typical, 1A maximum. The MAX696 operates with battery voltages from 2.0V to 4.25V. The battery voltage should not be within 0.5V of Voc or switchover may occur High value capacitors, either standard electrolytic or the farad- size double layer capacitors, can also be used for short-term memory backup. The capacitor charging voltage should include a diade to limit the fully charged voltage to approximately 0.5V tess than Vec. The charging resistor for rechargeable batteries should be connected to Vay7 since this eliminates the discharge path that exists if the resistor is connected to Vee. A small leakage current of typically 10nA (20nA max) flows out of the Vary terminal. This current varies with the amount of current that is drawn fram Voy7 but its polarity is such that the backup battery is always slightly charged, and is never discharged while Vcc is in its operating voltage range. This extends the shelf. life of the backup battery by compensating for its selt-discharge curreni. Also note that this current poses no problem when lithium batteries are used for backup since the maximum current (20nA) is safe for even the smallest lithium cells. If the battery-switchover section is not used, connect Veatt to GND and connect Voz to Voc. Table 2 shows the state of the inputs and output In the low power battery backup mode. Vpart IMAXG96I , BATT OW (MAxE96) Yee Od 2 OO Vour IMAXE96] Wz (MAX697] CHUP-ENABLE INPUT LLia # LOW LINE RESET GENERATOR AESET 16 pm RESET J > CHIP EMABLE DUTPUT (MAX 697) Py ry 18 ij Os IN TIMEBASE FOR RESET osc se >t aad WATCHODG it WATCHDOG WATCHDOG INFLIT = WATCHDOG TRANSITION DETECTOR TIMER p= WATCHOOG OUTPUT POWER Fail | 9 INPLIT ; Lagu = 19 7 POWER FAIL OUTPUT 4 [SROUND Figure 2. MAX896/697 Block Diagram SVLA ALI 69/969XVNMAX696/697 Microprocessor Supervisory Circuits Reset Output RESET is an active low output which goes low when- ever LL), falls below 1.3 voits. It will remain low until Lh yy rises above 1.312 voits for 50 milliseconds. (See Figures 4 and 5.} The guaranteed minimum and maximum low line thresholds of the MAX696/697 are 1.2 and 14 volts. The Lliy comparator has approximately 12mV of hysteresis. The response time of the reset voltage comparator is about 100 microseconds. LL, should be bypassed to ensure that glitches do not activate RESET output. RESET also goes low if the Watchdog Timer is en- abled and WDI remains either high or jow longer than the watchdog timeout period. RESET has an internal 3A pullup, and can aither connect to an open collector Reset bus or directly drive a CMOS gate without an external pullup resistor. CE Gating and _ sO AM Write Protection The MAX697 uses two pins to control the Chip Enable or Write inputs of CMOS RAMs. When LLiy is > 1.3V, CE QUT is a buffered replica of TE IN, with a 50ns propagation delay. if LL, input falls below +.3V (1.2 min., 7.4 max.) an internal gate forces SE OUT high. independent of CE IN. The CE output is also forced high when Vec is less than Vaart. (See Figure 4.) GE OUT typically drives the CE, CS or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when Ve, is at an invalid level. Similar protection of EEPROMs can be achieved by using the CE OUT to drive the Store or Write inputs of an EEPROM, EAROM, or NOVRAM. If the 50ns typical propagation delay of GE OUT is tao long, connect CE IN to GND and use the resulting CE OUT to cantrola high speed external logic gate. A secand alternative is to AND the LOW LINE output with the CE or WR signal. An external logic gate and the RESET output of the MAX696/697 can also be used for CMOS RAM write protection. 4.25V Comparator and Power Fail Warning The Power Fail Input (PFl) is compared to_an internal 1.3V reference. The Power Fail Output (PFO) goes low when the voltage at PFI is less than 1.3V. Typically PFI is driven by an external voltage divider which senses either the unregulated DC input to the system's Veo redulator or the regulated output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.3V_several milliseconds before the LLiy falls below 1.3V PFO is normally used to interrupt the microprocessor so that data can be stored in RAM before LL, falls below 1.3V and the RESET output goes low. The Power Fail Detector can also monitor the backup battery to warn of a low battery condition. Ta conserve battery power, the Power Fail Detector comparator is turned off and PFO is forced low when Vec is lower than the Vpaq7 input voltage. I ] | Wop Qe He = | +5W | | Kk To CMOS 14 RAM AND | 4 Vout T REALTIME - P CHANNEL ! oye fay MOSFET I | HASE DRIVE i= ! I | I RATT ON | Vaart LL * [oo 4 {MANEOI, MAX893, MAXEQS ONLY] | WW | BATTERY INPUT - | (70 INTERNAL . SW ig MODE SHUTDOWN | > SELECT SIGNAL WHEN Veatr <= Veo + O.7 | Lo _ _ Figure 3. MAX696 Battery-Switchovar Biock Diagram 8 _ MIAXAILSVIMicroprocessor Supervisory Circuits (MAxGo?7| CE IM = W _ Ct OUT (MAxGd7) v en 5 ee EE | POWER-ON | a FESET \ 5 RESET Ltiy * [=> Bic ; | | RESET Me on = RESET : . WATCHDOG ' FROM ' (130 WATCHORG UMEA 10 Hl | 2 CLOCK = _____= FRIM TIMEBASE SECVION | Poo eo _ Figure 4. Reset Block Diagram CT | | | t Il | t I i i I | | Luin av bata 13V 1.312 | | 1 | | | ! | I | ' | | Hl 1 | - | . ! RESET \ 50ms 5Oms fy OUTPUT \ __! | | LOW LINE OUTPUT | [MAX6Q7) CE IN IMAXBQ7) CE OUT | | Figure 5, MAX697 Reset Timing MMA XIE ee a Z69/969XViNMAX696/697 Microprocessor Supervisory Circuits Watchdog Timer and Oscillator The watchdog circuit monitors the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within the selected timeout period, a 50 milliseconds RESET pulse is generated. Since many systems cannot service the watchdog timer immediately after a reset, the MAX696/697 has a longer timeout period after a reset is issued. The normal timeout period becomes effective following the first transition of WDI after RESET has gone high. The watchdog timer is restarted at the end of Reset. whether the Reset was caused by lack of activity on WDI or by LLy falling below 1.3V. H WDI remains either high or low, reset pulses will be issued every 1.6 seconds. The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). The Watchdog Output WDO goes low if the watchdog timer times out, and it remains low until set_high by the next transition on the watchdog input) WBO is also set high when LL), goes below 1.3V. The watchdog timeout period defaults to 1.6 secands and the reset pulse width defaults to 50ms. The MAX696 and MAX697 allow these times to be adjusted per Table 1. The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100ms watchdog timeout periods. In either case, immediately after a reset the timeout period is 1.6 seconds. This gives the microprocessor time to reinitialize the system. WD transmissions while RESET is low are ignored. If OSC IN is low, then the 100ms watchdog period becomes effective after the first transition of WDI. The software should be written such that the I/O port driving WDI is left in its power- up reset state until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout period of 7Oms. Application Hints Adding Hysteresis to the Power Fall Comparator Since the power fail comparator circuit is non- inverting, hysteresis can be added by connecting a resistor between the PFO output and the PFI input as shown in Figure 7. When PFO is low, resistor R3 sinks current from the Summing junction at the PFI pin, When PFO is high, the series combination of R3 and R4 source current into the PFI summing junction. Alternate Watchdog Input Drive Circuits The Watchdog feature can be enabled and disabled under program control by driving WDI with a 3-state buffer (Figure 8). The drawback to this circuit is that a software fault may erroneously 3-state the buffer, thereby preventing the MAX690 from detecting that the microprocessor is no longer working. In most cases a better method is to extend the watchdog period rather than disabling the watchdog. See Figure 9. When the control input is high, the OSC SEL pin is low and the watchdog timeout is set by the external capacitor. A 0.01uF capacitor sets a watchdog timeout delay of 100 seconds. When the control input is low, the OSC SEL pin is driven high, selecting the internal oscillator. The 100ms or the 1.6 sec period is chosen, depending on which diode in Figure 9 is used. 10.24 kH2 FROM INTEAWAL OSCILLATOR B PRESCALER | tq EXTERNALLY SET FREQUENCY FROM WATCHDOG INPUT 06 <}__ OSC IN PIN . WATCHDOG TIMEQUT T ice 2 HI IF WATCHDOG OUT SELEC ? INPUT 1S FLOATING | ; RESET WATCHOUG WATCHDOG . counter JP erTED | TIMEQUT qigf}] SELECTOR . > Ro glosl? Al ost LOGIC = oy i TRANSITION END OF WATCHODE QE TECTOR | + TIMEOUT PERIOD _ Wy + ' FOR EACH TRANSITION SL =a biel S R $ J B LOW LINE RESET LONG/SHORT J iqw| wATCHDOG THLE LLiy -. 1.3) FLIP FLOP FF LINE| FAULT FF | T 0 i q | RESET RESET i WATCHDOG OUTPUT Figure 6 Watchdog Timer Block Diagram 10 SVIAXALSVIMicroprocessor Supervisory Circuits Table 1. MAX696 and MAX697 Reset Pulse Width and Watchdog Timeout Selections OSC SEL WATCHDOG TIMEOUT PERIOD RESET (Note 3) OSC IN NORMAL IMMEDIATELY TIMEOUT AFTER RESET PERIOD Low External Clock Input 1024 clks 4036 clks 512 clks Low External Capacitor 40ams Bsec . c 200ms c 47pf 47 pt 47 pt High/Floating Low 100ms 1.6 sec 50ms | High/Floating Floating 1.6 sec 1.6 sec 5oms | Note 1: When the MAX696/097 OSC SEL pin is law, OSC IN can be driver by an external clack signal, or an external capacitor can be connected between OSC IN and GND The nominal internal oscillator frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is FosctHz} = 184,006 Cose(PF} Note 2: See Electrical Characteristics Table for minumum and maximum timing values. Note 3: "HIGH" for the OSC SEL pin should be connected to Vout, not Vac (on MAX696}. T - 15 +oV ' 7805 wee yee a MAXO96 10k? MA X697 RI 4 = Tok 7 PFO PFI oH Ra L a2 13kO a00ks) = ae _|[ ey, TO yP al Rl iy = 91254 Ww= 130 (1 a5 * ag YL = 79ov - ; SM iv 13) RI AYSTERESIS = 1.23V v= 180 (1 * go - Pay aRS Re Rl HYSTERESIS = SV Bi ASSUMING R4- A } ; Figure 7 Adding Hysteresis to the Power Fail Valtage Comparator /VIAXI VI WATCHDOG STROBE WATCHODG DISABLE : L. Figure &. Disabling the Watchdog Under Program Control *ov ! Vee AAAI et MAX696 MAXG97 wo mm = a Le TIMEDUT 18 SELECTED Su LOW = INTERNAL | WATCHOOG TIMEQUT Ver: p--+ OSC SEL | \ I | ees ei sei |= EXTERNAL | " WATCHDOG = 7% rd MAX696 TIMEQUT gy ay MAX697 | it CONNECT FOR | YT ose in 100ms TIMEOUT GND WHEN INTERNAL CONNECT FOR 14 sec INTERNAL = TIMFQUT Figure 9. Selecting Internai or External Watchdog Timeout 269/969XVWMAX696/697 Microprocessor Supervisory Circuits Table 2. Input and Output Status in Battery Backup Mode | Vaatt, Vout RESET RESET LOW LINE BATT ON WODI WDO PFI PFO GE IN CE OUT OSC IN OSC SEL Veo Vaar7 is connected to Vo.1 via internal MOSFET. [MAX696 only) Logic law Logic high. The open circuit output voltage is equal to Veut Logic low Logic high (MAX696 only) WD is internally discannected from its internal pullup and does not source or sink current as long as its input voltage is between GND and Vout The input voltage does nat affect supply current. Logic high The Power Fail Comparator is turned off and the Power Fail Input voltage has no effect on the Power Fail Output. Logic low CE IN is Internally disconnected from its internal pullup and does not source or sink current as long as its Input voltage is between GND and Vou, The input vallage does not affect supply current (MAX697 only} Logie high (MAX697 only) OSG IN is ignored. OSC SEL is ignored. Approximately 12uA is drawn from the Vaar~ input when Vee is between Vaatr + TOOmV and Vaart - 7D0mV. The supply current is 1A maximum when Ver is less than Vaart - 7OOmMV Chip Topography MAX697 MAX696 Vout RESET RESET TEST RESET RESET Vaart I Veo woo Lun 016" ra (295mm) f ; GND Ni si valk a (|= BATT ON ae aes : : | I tl | ha Th wal DSC IN OSC PFI PFO LOW LINE OSC IN OSC PFI PFO | SEL SEL ooaa" . ____ _ 0.084 J (2.3mm) - ~~ asm) Mayim cannot assume responsibility for use of any cirewiry other than circuttry entirely embodied in a Maxim product No circia! patent licenses am implied Maum reserves the right ta change the circudry and specifications without notice at any be, 12 Maxim integrated Products, 120 San Gabrie! Drive, Sunnyvale, CA 94086 (408) 737-7400 1989 Maxim Integraled Products Printed USA sel AXL-1 iS a registered trademark of Maxim Integrated Products.