SMSC COM20022I Page 1 Revision 09-27-07
DATASHEET
COM20022I
10 Mbps ARCNET
(ANSI 878.1) Controller
with 2Kx8 On-Chip
RAM
Datasheet
Product Features
New Features
− Data Rates up to 10 Mbps
− Selectable 8/16 Bit Wide Bus With Data Swapper
− Programmable DMA Channel
− Programmable Reconfiguration Times
− 48 Pin TQFP Package; Lead-Free RoHS
Compliant Package also available
Ideal for Industrial/Factory/Building Automation
and Transportation Applicati ons
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Media Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microproc essors
Automatically Detects Type of Microcontroller
Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
Eight, 256 Byte Pages Allow Four Pages TX and
RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler and Clock Multiplier for
Adjusting Network Speed
Operating Temperature Rang e of -40 oC to +85oC
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star,
Tree, Bus...)
CMOS, Single +5V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Packets Mode
Flexible Media Interface:
− Traditional Hybrid Interface For Long Distances up
to Four Miles at 2.5Mbps
− RS485 Differential Driver Interface For Low Cost,
Low Power, High Reliability
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 2 SMSC COM20022I
DATASHEET
ORDERING INFORMATION
Order Numbers:
COM20022ITQFP for 48 pin TQFP package
COM20022I-HT for 48 pin, TQFP Lead-Free RoHS Compliant package
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2007 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLI ED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO
HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 3 Revision 09-27-07
DATASHEET
Table of Contents
Chapter 1 General Description................................................................................................................6
Chapter 2 Pin Configuration....................................................................................................................7
Chapter 3 Description of Pin Functions ..................................................................................................8
Chapter 4 Protocol Description.............................................................................................................11
4.1 Network Protocol........................................................................................................................................11
4.2 Data Rates.................................................................................................................................................11
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps....................................................................................12
4.3 Network Reconfiguration............................................................................................................................12
4.4 Broadcast Messages..................................................................................................................................13
4.5 Extended Timeout Function .......................................................................................................................13
4.5.1 Response Time...................................................................................................................................13
4.5.2 Idle Time .............................................................................................................................................13
4.5.3 Reconfiguration Time..........................................................................................................................13
4.6 Line Protocol..............................................................................................................................................14
4.6.1 Invitations To Transmit........................................................................................................................14
4.6.2 Free Buffer Enquiries..........................................................................................................................14
4.6.3 Data Packets.......................................................................................................................................14
4.6.4 Acknowledgements.............................................................................................................................15
4.6.5 Negative Acknowledgements..............................................................................................................15
Chapter 5 System Description ..............................................................................................................16
5.1 Microcontroller Interface.............................................................................................................................16
5.1.1 Selection of 8/16-Bit Access ...............................................................................................................19
5.1.2 DMA Transfers To And From Internal RAM........................................................................................19
5.1.3 DMA Operation ...................................................................................................................................20
5.1.4 DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ........................................................24
5.1.5 DMA Data Transfer Sequence (Memory to I/O: Write A Packet).........................................................24
5.1.6 High Speed CPU Bus Timing Support ................................................................................................24
5.2 Transmission Media Interf ace ....................................................................................................................25
5.2.1 Traditional Hybrid Interface.................................................................................................................26
5.2.2 Backplane Configuration.....................................................................................................................26
5.2.3 Differential Driver Configuration..........................................................................................................28
5.2.4 Programmable TXEN Polarity.............................................................................................................28
Chapter 6 Functional Description..........................................................................................................30
6.1 Microsequencer..........................................................................................................................................30
6.2 Internal Registers.......................................................................................................................................32
6.2.1 Interrupt Mask Register (IMR).............................................................................................................32
6.2.2 Data Register......................................................................................................................................33
6.2.3 Tentative ID Register ..........................................................................................................................33
6.2.4 Node ID Register.................................................................................................................................33
6.2.5 Next ID Register..................................................................................................................................34
6.2.6 Status Register....................................................................................................................................34
6.2.7 Diagnostic Status Register..................................................................................................................34
6.2.8 Command Register.............................................................................................................................34
6.2.9 Address Pointer Registers ..................................................................................................................34
6.2.10 Configuration Register.....................................................................................................................35
6.2.11 Sub-Address Register .....................................................................................................................35
6.2.12 Setup 1 Register..............................................................................................................................35
6.2.13 Setup 2 Register..............................................................................................................................35
6.3 Bus Control Register..................................................................................................................................36
6.4 DMA Count Register ..................................................................................................................................36
6.5 Internal RAM ..............................................................................................................................................47
6.5.1 Sequential Access Memory.................................................................................................................47
6.5.2 Access Speed.....................................................................................................................................47
6.6 Software Interface......................................................................................................................................47
6.6.1 Selecting RAM Page Size...................................................................................................................48
6.6.2 Transmit Sequence.............................................................................................................................49
6.6.3 Receive Sequence..............................................................................................................................50
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
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6.7 Command Chaining....................................................................................................................................51
6.7.1 Transmit Command Chaining .............................................................................................................51
6.7.2 Receive Command Chaining ..............................................................................................................52
6.8 Reset Details..............................................................................................................................................53
6.8.1 Internal Reset Logic............................................................................................................................53
6.9 Initialization Sequence ...............................................................................................................................53
6.9.1 Bus Determination...............................................................................................................................53
6.10 Improved Diagnostics.............................................................................................................................54
6.10.1 Normal Results:...............................................................................................................................54
6.10.2 Abnormal Results:...........................................................................................................................55
6.11 Oscillator.................................................................................................................................................55
Chapter 7 Operational Description........................................................................................................56
7.1 Maximum Guaranteed Ratings* .................................................................................................................56
7.2 DC Electrical Characteristics......................................................................................................................56
Chapter 8 Timing Diagrams..................................................................................................................59
Chapter 9 Package Outline...................................................................................................................78
Chapter 10 Appendix A...........................................................................................................................79
10.1 NOSYNC Bit...........................................................................................................................................79
10.2 EF Bit......................................................................................................................................................79
Chapter 11 Appendix B: Example of Interface Circuit Diagram to ISA Bus...........................................82
List of Figures
Figure 2.1 - COM20022I Pin Configuration....................................................................................................................7
Figure 3.1 - COM20022I Operation..............................................................................................................................10
Figure 5.1 - Multiplexed, 8051-Like Bus Interface with RS-485 Inte rface.......................................................................17
Figure 5.2 - Non-M u lti plex ed, 68 01-L ike B us I nte rfa c e w i th RS- 4 8 5 I n ter fac e ...............................................................18
Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes...............................................................................21
Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing)......................................................................22
Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................23
Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ........................................................................................23
Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode .......................................................................................25
Figure 5.8 - COM200 2 2I Networ k Using RS-4 85 Di fferent ial Trans ceivers....................................................................27
Figure 5.9 - Dipu l se Wa ve f o rm f or Data of 1-1-0...........................................................................................................27
Figure 5.10 - Inte r nal Bl ock D iagram.............................................................................................................................28
Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing................................................................................36
Figure 6.2 - Sequential Ac c e s s Op erati o n.....................................................................................................................46
Figure 6.3 - RAM Buffer Packet Configuration.............................................................................................................49
Figure 6.4 - Command Chaining Status Register Queue.............................................................................................51
Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ........................................................................59
Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ........................................................................60
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle..........................................................................61
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................62
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................63
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................64
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................65
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................66
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................67
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle...............................................................68
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle...............................................................69
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle...............................................................70
Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................71
Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................72
Figure 8.15 - TTL Input Timing on XTAL1 Pin..............................................................................................................73
Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................73
Figure 8.17 - DMA Timing (Intel Mode 80XX)..............................................................................................................74
Figure 8.18 - DMA Timing (Motorola Mode 68XX).......................................................................................................75
Figure 9.1 - COM20022I 48 Pin TQFP Package Outline..............................................................................................78
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 5 Revision 09-27-07
DATASHEET
Figure 10.1 - Effect of the EF Bit on the TA/RI Bit........................................................................................................81
List of Tables
Table 5.1 - Typical Media .............................................................................................................................................29
Table 6.1 - Read Register Summary............................................................................................................................31
Table 6.2 - Write Register Summary............................................................................................................................32
Table 6.3 - Status Register...........................................................................................................................................37
Table 6.4 - Diagnostic S t atu s Re g ist er..........................................................................................................................38
Table 6.5 - Comma n d Re g ist er.....................................................................................................................................39
Table 6.6 - Address Pointe r High Register....................................................................................................................40
Table 6.7 - Address Pointe r Low Registe r.....................................................................................................................41
Table 6.8 - Sub Add r ess R e gi ste r.................................................................................................................................41
Table 6.9 - Configurati on Re gister................................................................................................................................42
Table 6.10 - Setup 1 Regis ter.......................................................................................................................................43
Table 6.11 - Setup 2 Regis ter.......................................................................................................................................44
Table 6.12 - Bus Co ntr ol Re gister.................................................................................................................................45
Table 6.13 - DMA Cou nt R e g i ster.................................................................................................................................46
Table 8.1 - D M A T imi ng................................................................................................................................................76
Table 9.1 - COM20022I 48 Pin TQFP Package Parameters........................................................................................78
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes,
please refer to the ARCNET Local Area Network Standard, or the ARCNET Designer's
Handbook, available from Datapoint Corporation.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 6 SMSC COM20022I
DATASHEET
Chapter 1 General Description
SMSC's COM20022I is a member of the family of Embedded ARCNET Controllers from Standard
Microsystems Corporation. The device is a general purpose communications controller for networking
microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments
using an ARCNET protocol engine. The small 48 pin package, flexible microcontroller and media
interfaces, eight- page mess age support, and extended te mperature range of the COM20022I mak e it the
only true net work controller optimized for use in i ndustrial, embe dded, and automotive applications. U sing
an ARCNET protocol engine i s the ideal solution for embedded control applicatio ns because it provides a
deterministic token-passing protocol, a highly reliable and proven networking scheme, and a data rate of
up to 10 Mbps when using the COM20022I. A token-passing protocol provides predictable response times
because each network event occurs within a predetermined time interval, based upon the number of
nodes on the network. The deterministic nature of ARCNET is essential in real time applications. The
integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the 10 Mbps maximum data
rate, and the internal diagnostics make the COM20022I the highest performance embedded
communications device available. With only one COM20022I and one microcontroller, a complete
communications node may be implemented.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 7 Revision 09-27-07
DATASHEET
Chapter 2 Pin Configuration
COM20022
48 Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
AD0
AD1
D10
AD2
D11
D3
VDD
D4
D5
VSS
D6
VSS
13 14 15 16 17 18 19 20 21 22 23 24
D7
D12
D13
D14
D15
N/C
VDD
XTAL1
XTAL2
nPULSE1
VSS
VSS
25
36
35
34
33
32
31
30
29
28
27
26
nPULSE2
BUSTMG
N/C
RXIN
nTXEN
nRESET
VDD
DREQ
nINTR
nDACK
nCS
VSS
373839404142434445464748
TC
D9
D8
A2/ALE
A1
A0/nMUX
VDD
nIOCS16
nREFEX
nRD/nDS
nWR/DIR
VSS
Ordering Information:
PACKAGE TYPE: TQFP
TEMP RANGE: (Blank) = Commercial: 0°C to +70°C
I = Industrial: -40°C to +85°C
DEVICE TYPE: 20022 = Universal Local Area Network Controller
(with 2K x 8 RAM)
COM20022
Figure 2.1 - COM20022I Pin Configuration
COM20022I
48 Pin TQFP
Ordering Information:
COM20022I
PACKAGE TYPE: TQFP
TEMP RANGE: (Blank) = Commercial 0°C to + 70°
1 = Industrial: -40°C to +85°C
DEVICE TYPE: 20022I = Universal Local Area Network Controller
(with 2K x 8 RAM)
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 8 SMSC COM20022I
DATASHEET
Chapter 3 Description of Pin Functions
PIN NO NAME SYMBOL I/O DESCRIPTION
MICROCONTROLLER INTERFACE
44,45,
46 Address 0-2 A0/nMUX
A1
A2/ALE
IN
IN
IN
On a non-multiplexed mode, A0-A2 are addr ess input bits.
(A0 is the LSB) On a multiplexed address/data bus, nMUX
tied Low, A1 is left open, and ALE is tied to the Address
Latch Enable signal. A1 is connected to an internal p ull-up
resistor.
1,2,4,
7,9,
10,12, 13
Data 0-7 AD0-AD2,
D3-D7 I/O On a non-multiplexed bus, these signals are used as the
lower byte data bus lines. On a multiplexe d address/data
bus, AD0-AD2 act as the address lines (latched b y ALE)
and as the low data lines. D3-D7 are always used for data
only. These signals are connected to internal pull-up
resistors.
47, 48,
3,5,
14-17
Data 8-15 D8-D15 I/O D8-D15 are always used as the higher byte data bus lines
only for 16bit internal RAM access. W hen the 16bit access
is disabled, these signals are always Hi-Z. Enabling or
disabling the 16bit access is programmable. A data
swapper is built in. These signals are co nnected to internal
pull-up resistors.
37 nWrite/
Direction nWR/DIR IN nWR is for 80xx CPU, nWR is Write signal input. Active
Low.
DIR is for 68xx CPU, DIR is Bus Direction signal input.
(Low: Write, High: Read.)
39 nRead/
nData Strobe nRD/nDS IN nRD is for 80xx CPU, nRD is Read signal input. Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal input.
Active Low.
31 nReset In nRESET IN Hardware reset signal. Active Low.
34 nInterrupt nINTR OUT Interrupt signal output. Active Lo w.
36 nChip Select nCS IN Chip Select input. Active Low.
42 nI/O
16 Bit
Indicator
nIOCS16 OUT
This signal is an active Low signa l which indicates
accessing 16bit data only b y CPU. This signal becomes
active when CPU accesses to data register only if W16 bit
is 1. This signal is same as on ISA Bus signal, but it’s not
OPEN-DRAIN. An external OPEN-DRAIN Buffer is needed
when this signal connects to the ISA Bus.
26 Read/Write
Bus Timing
Select
BUSTMG IN Read and Write Bus Access Timing mode selecting signal.
Status of this signal effects CPU and DMA Timing.
L: High speed timing mode (onl y for non-multiplexed bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
33 DMA
Request DREQ OUT
DMA Request signal. Active polarity is programmable.
Default is active high.
35 DMA Ack nDACK IN DMA Acknowledge signal. Active Lo w. When BUSTMG is
High, this signal is connected to internal p ul l-up registers
38 Terminal
Count TC IN
Terminal Count signal. Active polarity is programmable.
Default is active high. When BUSTMG is High, this signal is
connected to the internal pull-up resistor.
40 Refresh
Execution nREFEX IN Refresh execution signa l. Falling edge detection. This
signal is connected to the internal pull- up resistor.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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SMSC COM20022I Page 9 Revision 09-27-07
DATASHEET
PIN NO NAME SYMBOL I/O DESCRIPTION
TRANSMISSION MEDIA INTERFACE
24
25
nPulse 1
nPulse 2
nPULSE1
nPULSE2
OUT
I/O
In Normal Mode, these active low signals carry the transmit
data information, encoded in puls e format as DIPULSE
waveform. In Backplane Mode, the nPULSE1 signal driver
is programmable (push/pull or open-drain), while the
nPULSE2 signal provides a clock with frequency of doubled
data rate. nPULSE1 is connected to a weak internal pull-up
resistor on the open/drain driver in backplane mode.
28 Receive In RXIN IN This signal carries the receive data information from the line
transceiver.
29 nTransmit
Enable nTXEN OUT
Transmission Enable sig na l. Active polarity is
programmable through the nPULSE2 pin.
nPULSE2 floating before power-up;
nTXEN active lo w
nPULSE2 grounded before power-up;
nTXEN active high (this opti on is only available in Back
Plane mode)
21
22 Crystal
Oscillator XTAL1
XTAL2 IN
OUT An external crystal should be connected to these p ins.
Oscillation frequency range is from 10 MHz to 20 MHz. If
an external TTL clock is used instead, it must be connected
to XTAL1 with a 390ohm pull-up resistor, and XTAL2 should
be left floating.
8,20,
32,43 Power
Supply VDD PWR +5 Volt power supply pins.
6,11,
18,23,
30,41
Ground VSS PWR Ground pins.
19,27 N/C N/C Non-connection
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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Invitation
to Transmit to
this ID?
YN
F ree Buffer
Enq uiry to
this ID? SOH?
YN
YN
RI?
Write SID
to Bu ffer
DID
=0?
DID
=ID?
Write Buff er
with Packe t
CRC
OK?
LENGTH
OK?
DID
=0?
DID
=ID?
SEND AC K
N
Y
N
Y
N
YN
Broadcast
Enabled? N
Y
N
No Acti vity
for 20.5
uS?
Y
N
Set NID=ID
Start Tim er:
T=(255-ID)
Activity
On Line? Y
N
T=0?
Set R I
RI?
Transmit
NAK
Transmit
ACK
Set NID=ID
Write ID to
RAM Buff e r
Send
Reconfigure
Burst
Power On
Reconfigure
Timer has
Timed Out
Start
Reconfiguration
Timer (210 mS)*
TA?
Broadcast? Transmit
Free Buff er
Enquiry No
Activity
Pass the
Token
Set TA
Y
N
ACK?
NAK?
1
No
Activity NY
Increment
NID
Send
Packet
W a s Packet
Broadcast?
No
Activity
N
ACK? Set TMA
Set TA
x 36.5 us
for 18.7
us?
for 18.7
us?
for 18.7
us?
YN
N
Y
YNNY
N
N
N
N
1
Y
Y
Y
YY
Y
Y
N
Y
Read Node ID
ID refers to the identification number of the ID assigned to this node.
NID refers to the next identification number that r ece iv es the token
after this ID passes it.
-
-
-
-
SID refer s to the source ide ntification.
DID refers to the destination identification.
SOH refer s to the start of header character; preceeds all data packets.
-
YN
* Reconfig timer is programmable via setup2 register bits 1, 0.
Note - All time values are valid for 10Mbps.
Figure 3.1 - COM20022I Operation
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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SMSC COM20022I Page 11 Revision 09-27-07
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Chapter 4 Protocol Description
4.1 Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network
configuration and management of the network protocol are handled entirely by the COM20022I's internal
microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet
and its destination ID into the COM20022I's internal RAM buffer, and issuing a command to enable the
transmitter. When the COM20022I next receives the token, it verifies that the receiving node is ready by
first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge
message, the data packet is transmitted foll owed by a 16-bit CRC. If the receivin g node c ann ot accept the
packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the
transmitter passes the token. Once it has b een established that the receiving node c an accept the pac ket
and transmission is complete, the receiving node verifies the packet. If the packet is received
successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received
successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful
delivery of the packet. An interrupt mask permits the COM20022I to generate an interrupt to the processor
when selected status bits become true. Figure 2.1 is a flow chart illustrating the internal operation of the
COM20022I connected to a 20 MHz crystal oscillator.
4.2 Data Rates
The COM20022I is capable o f supporting data rates from 156.25 Kbps to 10 Mbps. T he following protocol
description assumes a 10 Mbps data rate. To attain the faster data rates, the clock frequency may be
doubled or quadrupled by the internal clock multipl ier (see next section). F or slower data rates, an internal
clock divider scales down the clock frequency. Thus all timeout values are scaled as shown in the
following table:
Example:
IDLE LINE Timeout @ 10 Mbps = 20.5 μs. IDLE LINE Timeout for 156.2 Kbps is 20.5 μs * 64 = 1.3 ms
INTERNAL CLOCK
FREQUENCY CLOCK PRESCALER D AT A RATE TIMEOUT SCALING FACTOR
(MULTIPLY BY)
80 MHz Div. by 8 10 Mbps 1
40 MHz Div. by 8 5 Mbps 2
20 MHz Div. by 8
Div. by 16
Div. by 32
Div. by 64
Div. by 128
2.5 Mbps
1.25 Mbps
625 Kbps
312.5 Kbps
156.25 Kbps
4
8
16
32
64
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
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4.2.1 Selecting Clock Frequencies Above 2.5 Mbps
To realize a 10 Mbps network, an external 80 MHz clock must be input. However, since 80 MHz is the
frequency of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher
frequency clocks are generated from the 20 MHz crystal as selected through two bits in the Setup2
register, CKUP[1,0] as shown belo w. The selected clock is supplied to the ARCNET controller.
CKUP1 CKUP0 CLOCK FREQUENCY (DATA RATE)
0 0 20 MHz (Up to 2.5Mbps) Default (Bypass)
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 80 MHz (Only 10Mbps)
This clock multiplier is powered-down (bypassed) on default. After changin g the CKUP1 and CKUP0 bits,
the ARCNET core operation is stopped and the internal PLL in the clock generator is awakened and it
starts to generate the 40 MHz or 80 MHz. The lock out time of the internal PLL is 8uSec typically. After
more than 8 μsec (this wait time is defined as 1 msec in th is data sheet), it is necessary to write comman d
data '18H' to the command register to re-start the ARCNET core operation. This clock generator is calle d
“clock multiplier”.
Changing the CKUP1 and C KUP0 bits must be one time or less after releasing a hardware reset.
The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.
4.3 Network Reconfiguration
A significant advantage of the COM20022I is its ability to adapt to changes on the network. Whenever a
new node is activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new
COM20022I is turned on (creating a new active node on the network), or if the COM20022I has not
received an INVITAT ION TO TRANSMIT for 210mS, or if a software reset occurs, the COM20022I causes
a NETWORK RECONFIGURATION by sending a RECO NFIGURE BURST consisting of eight marks an d
one space repeated 765 times. T he purpose of t his burst is to terminate all activity on the net work. Since
this burst is longer than any other type of transmission, the burst will interfere with the next INVITATION
TO TRANSMIT, destroy the token and keep an y other node from assuming control of the line.
When any COM20022I senses an idle line for greater than 20.5μS, which occurs only when the token Is
lost, each COM20022I starts an internal timeout e qual to 36.5μs times the quantity 25 5 minus its own ID.
The COM20022I starts network reconfig urati on by sendi ng an inv itatio n to transmit first to itself and then to
all other nodes by decrementing the destination Node ID. If the timeout expires with no line activity, the
COM20022I starts sending INVITATION TO TRANSMIT with the Destination ID (DID) equal to the
currently stored NID. Within a given network, only one COM20022I will timeout (the one with the highest
ID number). After sending the INVITATION TO TRANSMIT, the COM20022I waits for activity on the line.
If there is no activity for 18.7μS, the COM20022I increments the NID value and transmits another
INVITATION TO TRANSMIT using the NID equal to th e DID. If activit y appears before t he 18.7μS timeout
expires, the COM20022I releases control of the line. During NETWORK RECONFIGURATION,
INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).
Each COM20022I on the network will finally have saved a NID value equal to the ID of the COM20022I
that it released control to. At this point, control is passed dir ectly from one nod e to the next with no wasted
INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK
RECONFIGURATION occurs. When a node is po wered off, the previous node attempts to pass the token
to it by issuing an INVITATION TO TRANSMIT. Since this node does not respond, the previous node
times out and transmits another INVITATION TO TRANSMIT to an incremented ID and eventually a
response will be received.
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The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the
propagation delay between nodes, and the highest ID number on the network, but is typically within the
range of 6 to 15.3 mS.
4.4 Broadcast Messages
Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network
simultaneously. ID zero is reserved for this feature and no node on the n etwork can be assigned ID z ero.
To broadcast a message, the transmitting node's processor simply loads the RAM buffer with the data
packet and sets the DID equal to zero. Figure 5.7 illustrates the position of each byte in the packet with
the DID residing at addr ess 0X01 or 1 He x of the curr ent p age s electe d in t he "E na ble T r ansmit from Pag e
fnn" command. Each individual node has the ability to ignore broadcast messages by setting the most
significant bit of the "Enable Receive to Page fnn" command (see T able 6.5) to a logic "0".
4.5 Extended Timeout Function
There are three timeouts associated with the COM20022I operation. The values of these timeouts are
controlled by bits 3 and 4 of the Configurati on Register and bit 5 of the Setup 1 Register.
4.5.1 Response Time
The Response Time determines the maximum propagation delay allowed between any two nodes, and
should be chosen to b e larg er than th e round trip pr o pagatio n dela y between the two furthest nodes o n the
network plus the maximum turn around time (the time it takes a particular COM20022I to start sending a
message in response to a re ceived message) which is approximately 3. 2 μS. The round trip propagation
delay is a function of the tra nsmission media and network topology. For a typical system using RG62 co ax
in a baseband system, a one way cable propagation delay of 7.75 μS translates to a distance of about 1
mile. The flow chart in Figure 3.1Figur e 2.1 u ses a valu e of 18.7 μS (7.75 + 7.75 + 3.2) to determine if an y
node will respond.
4.5.2 Idle Time
The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 3.1Fig ure 2.1 illustrates that
during a NETWORK RECONFIGURATION one node will continually transmit INVITATIONS TO
TRANSMIT until it encounters an active node. All other nodes on the network must distinguish between
this operation and an e ntirely idle line. During NETWORK RECONFIGURATION, activity will appear on the
line every 20.5 μS. This 20.5 μS is equal to the Response Time of 18.7 μS plus the time it takes the
COM20022I to start retransmitting another message (usually another INVITATION TO TRANSMIT).
4.5.3 Reconfiguration Time
If any node does not receive the token within the Reconfiguration T ime, the node will init iate a NETWORK
RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate
over longer distances than the 1 mile stated earlier. The logic levels on these bits control the maximum
distances over which the COM20022I can operate by controlling the three timeout values described above.
For proper network operation, all COM20022I's connected to the same network must have the same
Response Time, Idle Time, and Reconfi guration Time.
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4.6 Line Protocol
The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval
and ended with a stop interval. Unlike asynchronous protocols, there is a constant amount of time
separating each data byte. On a 10 Mbps network, each byte takes exactly 11 clock intervals of 100ns
each. As a result, one byte is transmitted every 1.1 μS and the time to transmit a message can be
precisely determined. The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line
activity and a logic "1" is defined as a negative pulse of 50nS duration. A transmission starts with an
ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent,
with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of
transmission can be performed as described bel ow:
4.6.1 Invitations To Transmit
An Invitation To Transmit is used to pass the token from o ne node to another and is sent by the following
sequence:
An ALERT BURST
An EOT (End Of Transmission: ASCII code 04H)
Two (repeated) DID (Destination ID) characters
ALERT
BURST EOT DID DID
4.6.2 Free Buffer Enquiries
A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the
following sequence:
An ALERT BURST
An ENQ (ENQuiry: ASCII code 85H)
Two (repeated) DID (Destination ID) characters
ALERT
BURST ENQ DID DID
4.6.3 Data Packets
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:
An ALERT BURST
An SOH (Start Of Header--ASCII code 01H)
An SID (Source ID) character
Two (repeated) DID (Destination ID) characters
A single COUNT character which is the 2's complement of the number of da ta bytes to follow if a short
packet is sent, or 00H followed by a COUNT character if a long packet is sent.
N data bytes where COUNT = 256-N (or 512-N for a long p acket)
Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1.
ALERT
BURST SOH SID DID DID COUNT data data CRC CRC
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4.6.4 Acknowledgements
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE
BUFFER ENQUIRIES and is sent by the following sequenc e:
An ALERT BURST
An ACK (ACKnowledgement--ASCII code 86H) character
ALERT BURST ACK
4.6.5 Negative Acknowledgements
A Negative Ackno wledgement is used as a negative response to FREE B UFFER ENQUIRIES and is sent
by the following sequence:
An ALERT BURST
A NAK (Negative Acknowledgement--ASCII code 15H) character
ALERT BURST NAK
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Chapter 5 System Description
5.1 Microcontroller Interface
The top halves of F igure 5.1 and F igure 5. 2 illustrate typic al COM20022I interfaces to the microcontr oller s.
The interfaces consist of a 8-bit data bus, an address bus and a control bus. In order to support a wide
range of microcontrollers without requiring glue logic and without increasing the number of pins, the
COM20022I automatically detects and adapts to the type of microcontroller being used. Upon hardware
reset, the COM20022I first determines whether the read and write c ontrol signals are separate READ and
WRITE signals (like the 80XX) or DIRECT ION and DAT A STROBE (like the 6 8XX). To de termine the type
of control signals, the device requires the software to execute at least one writ e access to external memory
before attempting to access t he COM20022I. The device defaults to 80 XX-like signals. Once the type of
control signals are determined, the COM20022I remains in this interface mode until the next hardware
reset occurs. The second determination the COM20022I makes is whether the bus is multiplexed or non-
multiplexed. To determine the type of bus, the device requires the software to write to an odd memory
location followed by a read from an odd location before attempting to access the COM20022I. The signal
on the A0 pin during the odd location access tells the COM20022I the type of bus. Since multiplexed
operation requires A0 to be active low, activity on the A0 line tells the COM20022I that the bus is non-
multiplexed. The device defaults to multiplexed operation. Both determinations may be made
simultaneously by performing a WRITE followed by a READ operation to an odd location within the
COM20022I Address space 20022 registers. Once the type of bus is determined, the COM20022I
remains in this interface mode until har dware reset occurs.
Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be
changed until hardware reset. Refer to Description of Pin Functions section for details on the related
signals. All accesses to the i nternal RAM and th e interna l registers are c ontrolled b y the COM20022I. T he
internal RAM is accessed via a pointer-based scheme (refer to the Sequential Access Memory section),
and the internal registers are accessed via d irect addr essi ng. Man y peripherals ar e not fa st enough to ta ke
advantage of high-speed microcontrollers. Since microcontrollers do not typically have READY inputs,
standard peripherals cannot extend cycles to extend the access time. The access time of the COM20022I,
on the other hand, is so fast that it does not need to limit the speed of the microcontroller. The
COM20022I is designed to be flexibl e so that it is independent of the microcontroller speed.
The COM20022I provides for no wait state arbitration via direct addressing to its internal registers and a
pointer based addr essing scheme to access its internal RA M. The pointer may be us ed in auto-increme nt
mode for typical sequential buffer emptying or loading, or it can be taken out of auto-increment mode to
perform random accesses to the RAM. The data within the RAM is accessed through the data register.
Data being read is prefetched from memory and placed into the data register for the microcontroller to
read. It is important to notice that only by writing a new address pointer ( writing to an address pointer lo w),
one obtains the contents of COM200 22I internal RAM. Performing only read from t he Data Register does
not load new data from the internal RAM. During a write operation, the data is stored in the data register
and then written into memory. Whenever the pointer is loaded for reads with a new value, data is
immediately prefetched to prepare for the first read operation.
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DATASHEET
A
D0-AD7
nINT1
RESET
nRD
nWR
A
15
A
D0-AD2, D3-D7
nCS
nRESET
nRD/nDS
nWR/DIR
nINTR
A
2/BALE
A
LE
XTAL1
XTAL2
GND
RXIN
nPULSE1
nPULSE2
nTXEN
8051
COM2002I
Differential Driver
Configuration
Media Interface
may be replaced
with Figure A, B or C.
*
RXIN
nPULSE1
nPULSE2
TXEN
GND
+5V
100 Ohm
BACKPLANE CONFIGURATION
FIGURE A
RXIN
nPULSE1
FIGURE B
Receiver
HFD3212-002
2
+5V
7
6
Transmitter
HFE4211-014
+5V
3
2 Fiber Interface
(ST Connectors)
2
6
7
NOTE: COM20022I must be in backplane
75176B or
Equiv.
A
0/nMUX
27 pF 27 pF
XTAL2
XTAL1
20 MHz
XTAL
Figure 5.1 - Multiplexed, 8051-Like Bus Interface with RS-485 Interface
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D0-D7
nIRQ1
nRES
nIOS
R/nW
A
7
D0-D7
A
0/nMU
X
A
0
XTAL1
XTAL2
A
1
A
1
nCS
nRESET
nRD/nDS
nWR/nDIR
nINTR
A
2/BALE
A
2
RXIN
nPULSE1
nPULSE2
TXEN
GND
Differential Driver
Configuration
6801
COM20022I
Media Interface
may be replaced
with Figure A, B or C.
*
75176B or
Equiv.
XTAL1 XTAL2
27 pF 27 pF
20MHz
XTAL
RXIN
nPULSE1
nPULSE2
nTXEN
GND
Traditional Hybrid
Configuration
RXIN
nPULSE1
nPULSE2
17, 19,
4, 13, 14
5.6K
1/2W
5.6K
1/2W
0.01 uF
1KV
12
11
-5V
0.47
uF 10
uF
+
3
0.47
uF
+
+5V
uF
10
6
FIG URE C
HYC9088
HYC9068 or
N/C
*Valid for 2.5 Mbps only.
Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface
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5.1.1 Selection of 8/16-Bit Access
The interface to the internal RAM is software selectable as either 8 or 16-bit. This feature is new to the
COM20022I. The D15-D8 pins are the upper-byte data bus pins. The nIOCS16 pin is the 16-bit I/O access
enable output pin. T his pin is active low for a 16-bit RAM access by the CPU (not a DMA access).
The 16-bit access mode is enabled and disabled through the W16 bit located in the Bus Control Register
at bit 7. The SWAP bit is used to swap the upper and lower data bytes in 16-bit mode, as shown in the
table below. The SWAP bit is located at bit 0 of Address Lo w Pointer. This location is same as the A0 bit;
when 16 bit access is enabled (W16 =1), the A0 bit becomes the SWAP bit.
DETECTED HOST I/F MODE SWAP BIT (NOTE) D15-D8 PINS D7-D0 PINS
Intel 80xx Mode
(RD,WR Mode) 0
1 Odd
Even Even
Odd
Motorola 68xx Mode
(DIR, DS Mode) 0
1 Even
Odd Odd
Even
Note: The SWAP bit is undefined after a hardware reset
As shown on the table above, even address data is to/from D7-D0 pins and odd address data is to/from
D15-D8 pins when detected host interfac e mode is Intel 80xx mod e and the SWAP bit is not set. The od d
address data is to/from the D7-D0 pins and the even address data is t o/from D15-D8 pins when detected
host interface mode is Motorola 68xx mode and the SW AP bit is not set.
When disabling 16- bit access, the D15-D8 pi ns are always Hi-Z. The D15-D8 pi ns are Hi-Z when enabling
16-bit access except for internal RAM access.
W16 bit and SWAP bit influence both the CPU cycle and DMA cycle.
5.1.2 DMA Transfers To And From Internal RAM
The COM20022I supports DMA transfers to and from the internal RAM. This feature is new to the
COM20022I. The software selectable 8/16 bit interface to the RAM pertains to DMA transfers. When the
W16 bit=0, the microcontroller interface and DMA transfers are both 8-bit data transfers to/from internal
RAM. When W16=1 the y are both 16-bit data transfers. An 8-bit microcontroller interface and 16-bit DMA
data transfer cannot be selected; they must be the same width data transfers to/from internal RAM.
The data swapping op eration on 16-bit data transfers also pertains to both.
The DMA interface consists of several added pins. The DREQ pin is the DMA Request output pin. The
active polarity of this pin is programmable; the default is active-hi gh. T he nDACK pi n is the active-low DMA
acknowledge input pin. T he TC pin is the external terminal count input pin. T his pin determines when the
nDACK pin is active. It’s active polarity is pro grammable; the default is active-high. The n REF EX pin is the
active-low refresh execution pulse input pin.
The DMA interface is controlled by the follo wing bits. The DMAEND bit se lects whether or not to mask the
interrupt upon finishing th e DMA. This bit is located at bit 4 of the M ask re gister. T he DM AEN bit is used t o
disable/enable the assertion of the DMA Request (DREQ pin) after writing the Address Pointer Low
register. This bit is located in t he Address Pointer High regis ter, bit 3. The following bits ar e located in the
Bus Control Register: DRPOL, TCPOL and DMAMD[1,0]. The DRQPOL bit sets the active polarity of the
DREQ pin; the TCPOL bit sets the active polarity of the TC pin; the DMAMD[1,0] bits select the data
transfer mode of the DMA.
The ITCEN/RTRG bit has on e of two functions, depending on the DMA transfer mode selected. ITCEN is
the Internal Terminal Counter Enable. It is used to select whether the DMA is terminated by external TC
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only or by either internal or external TC. ITCEN is for Non-Burst or Burst mode. RTRG selects the re-
trigger mode as either external or internal. It is for the t wo Programmable-Burst modes.
The TC8/RSYN/GTTM bit has one of three functions, depe nding on the D MA transfer mode s elected. T C8
is bit 8 of the Terminal Count. It is the MSB of the 9 bi t Terminal Co unt setting register (the other 8 bits ar e
in the DMA Count register). TC8 is for Non-Burst or Burst mode. RSYN is the Refresh Synchronous bit.
This bit is used to select whether the DMA is started immed iately or after Refresh execution. GTT M is the
Gate Time bit. This bit selects whether the Gate Time is 350nS (min) or 750nS (min). RSYN and GTTM
are for the two Programmable-Burst modes. RSYN is for External Re-Trigger mode; GTTM is for internal
Re-Trigger mode.
Located in the DMA Count Register, the TC7-TC0 /TIM7-TIM0 /CYC7-CYC0 bits have one of three
functions depending on the DM A transfer mode. TC7-TC0 are for non-burst or bur st mode. These are the
lower 8 bits of the Terminal Count setting register (the MSB is in the Bus Control Register). The TIM7-
TIM0 bits are for setting the time of the continuous DMA transfer in Programmable-Burst by Timer mode.
The CYC7-CYC0 bits are for setting the time of the continuous DMA transfer in Programmable-Burst by
Cycle mode.
5.1.3 DMA Operation
The DMA interface operates in one of four transfer modes: Non-Burst, Burst, Programmable-Burst (by
timer) and Programmable-Burst (b y cycle counter). T he data transfer mo de of the DMA i s selected thro ugh
the DMAMD[1,0] bits in the Bus Control register, bits [3,2]. These modes are descr ibed below.
Non-Burst mode is a Single Transfer mode wherein, the DREQ pin is asserted after writing the Address
Pointer Low Register when DMAEN=1. Actually, DREQ pin is asserted 4TARB time after writing the
Address Pointer Low Register when DMAEN = 1 (refer to F igure 5.3). T his mode op erates as follows:
1. The nDACK pin is asserted by the DMA Controller detecting the DREQ pin asserted.
2. The DREQ pin is deasserted by the COM20022I detecti ng the nDACK pin asserted.
3. The nDACK pin is deasserted by the DMA Controller detecting the DREQ pin deasserted after
executing the present read or write cycle.
4. The DREQ pin is asserted by the COM20022I detecting the DACK pin deasserted.
Repeat above 4 steps until the TC pin goes active. This mode is called "Cycle steal mod e".
Burst mode is a Demand Transfer mode. In this mod e, the DREQ pin is asserted after writing the Addr ess
Pointer Low Register when DMAEN=1. Actually, DREQ pin is asserted 4TARB time after writing the
Address Pointer Low Register when DMAEN = 1 (refer to Figure 5.3). The DACK pin is asserted by the
DMA Controller detecting the DREQ pin asserted. The DREQ pin stays asserted until the TC pin goes
High.
Programmable-Burst mode is a Demand Transfer mode with temporary DREQ deassertion for a Refresh
cycle. The DREQ pin is asserted after writing the Address Pointer L ow Register when DMAEN=1 (refer to
Figure 5.3). The DACK pin is asserted by the DMA Controller detecting the DREQ pin asserted. If the
continuous DMA operation time is longer than the set Refresh period, then DREQ is deasserted. The
DREQ is held deasserted after negating nDACK for the Gate time. After the Gate time, the DREQ pin is
asserted again. The DREQ pin stays asserted until the TC pin goes High. In Programmable-Burst mode,
the gating can be by timer or by cycle counter.
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DATASHEET
DREQ
nWR
DMAEN bit
Writing Address
Pointer Low
minimum 4TARB
TARB is the ARBITRATION Clock Period. It depends on the TOPR and
SLOW- ARB bit. TOPR is the period of operation clock frequency (output
of the clock multiplier). It depends on the CKUP1 and CKUP0 bits.
TARB = TOPR @ SLOW-ARB = 0
TARB = 2 TOPR @ SLOW-ARB = 1
Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes
As an example of gatin g by cycle, in an ISA bus system, the Refresh period is 15μS. Contin uous transfer
by DMA must be less than 15μS to prevent blocking by the Refresh cycle. A DMA cycle of consecutive
DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5μS. The Refresh
execution time is 500nS. This computes to 15μS - 2.5μS - 500nS = 12μS or 12 cycles. Therefore the
DREQ pin must be negated ever y 12 cycles. Figure 5.4 ill ustrates the rough timing of the Programmable-
Burst mode DMA transfer.
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Figure 5.4 - Programmable Burst Mode DMA Transfer (Ro ugh Timing)
The timing of the Non-Burst mode DMA data transfer is found i n the Timing Diagrams section of this data
sheet. The basic sequence o f operation is as follows:
nDACK becomes active (low) upon DREQ becoming active (hig h) and catching the host bus (AEN=1).
DREQ becomes inactive after nDACK and read/write signal become active.
DREQ becomes active after nDACK or read/write signal becomes inactive.
DREQ becomes inactive after TC and the read/write signal assert (when nDACK=0). In this case,
DREQ doesn't become active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ=0 and the present cycle finishes.
Gate
Time
DREQ
(Active-High)
nDACK
(Active-Low)
Transfer term
(Counti ng Read/Write pulse
or counting internal timer) Restart
Transfer
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The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing
The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet.
The basic sequence of operation is as follows:
nDACK becomes active (low) upon DREQ becoming active (hig h) and catching the host bus (AEN=
“1”).
DREQ becomes inactive after TC asserts ( when nDACK= “0”). In this case, DREQ doesn't become
active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ= 0 and the present cycle finishes.
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing
DREQ
nDACK
TC
Read/Write
Signal
DREQ
nDACK
TC
Read/Write
Signal
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The following sequences show the data transfer for a DMA read and a DMA write. The transfer of data
between system memory and internal RAM functions as a memory to I/O DMA transfer. Since it is treated
as an I/O device, the COM20022I has to create the RAM address. Therefore the COM20022I’s address
pointers must be programmed before starting the DMA transfers.
5.1.4 DMA Data Transfer Sequence (I/O to Memory: Read A Packet)
step1: Set DMA-controller (ex. 8237)
step2: Set DRQPOL, TCPOL, DMAMD1 and DMAMD0 bits
>>Finished DMA SETUP
>>A packet received
step3: Set address, byte count and etc. of DMA controller
step4: Set pointer High and Low (RDDATA=1,AUTOINC=1, DMAEN=0)
step5: Read SID, DID, CP in the received packet
step6: Set DMAEN=1 (RDDATA=1, AUTOINC=1)
step7: DMAEND=1 in Mask REG.
step8: Set pointer = CP
>>DREQ is asserted by step8
>>Interrupt occurs upon finishi ng DMA
5.1.5 DMA Data Transfer Sequence (Memory to I/O: Write A Packet)
step1: Set DMA-controller (ex. 8237)
step2: Set DRQPOL, TCPOL, DMAMD1 and DMAMD0 bits
>>Finished DMA SETUP
step3: Set address, byte count and etc. of DMA controller
step4: Set pointer High and Low (RDDATA=0,AUTOINC=1, DMAEN = 0)
step5: Write SID,DID,CP in the sending packet
step6: Set DMAEN=1 (RDDATA=0, AUTOINC=1)
step7: DMAEND=1 in Mask REG.
step8: Set pointer = CP
>>DREQ is asserted by step8
>>Interrupt occurs upon finishing DMA transfer
step9: Write Enable T r ansmit command to command register
5.1.6 High Speed CPU Bus Timing Support
High speed CPU bus support was ad ded to the COM20 022I. T he reasoning beh ind this is as follo ws: With
the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable
before the read signal is acti ve and remain after the read signal is inactive. But the H igh Speed CPU bus
timing doesn't adhere to these timings. For example, a RISC type single chip microcontroller (like the
HITACHI SH-1 series) changes I/O address at the same time as the read signal. Therefore, several
external logic ICs would be required to connect to this microcontroller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal
DIAG register read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read
(nRD) signals. The decoder will generate a noise spike at the above tight timing. The DIAG register is
cleared by the spike signal without reading it self. This is u nexpected oper ation. Read ing the internal RAM
and Next Id Register have the same mechanism as reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU
interface to support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address
(A2-A0) and Chip Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal
delayed nRD signal. The internal real read signal is the more delayed nRD signal. But the rising edge of
nRD doesn't delay. By this modification, the internal real address and Chip Select are stable while the
internal real read signal is active. Refer to Figure 5.7 on the following page.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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SMSC COM20022I Page 25 Revision 09-27-07
DATASHEET
Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled.
Also, the nRD signal is not delayed, because the above sampling and delaying paths decrease the data
access time of the read cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which
generates the clearing pulse for the Diagnostic register and generates the starting pulse of the RAM
Arbitration. Typical delay time between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is
around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some
wait cycles to extend the width without any impact on performance.
The BUSTMG pin is used to s upport this f unction. It is used to E nable/Dis able the High Speed CP U Read
and Write function. It is defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are
enabled; BUSTMG = 1, the High S peed CPU Read an d Writ e oper ations ar e disable d if the RB UST MG bit
is 0. If BUSTMG = 1 and RBUST M G = 1, High Speed CP U Read o per ati ons are e nab led (see defi nitio n of
RBUSTMG bit below).
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as:
RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled.
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
BUSTMG PIN RBUSTMG BIT BUS TIMING MODE
0 X High Speed CPU Read and Write
1 0 Normal Speed CPU Read and Write
1 1 High Speed CPU Rea d and Normal Speed CPU Write
5.2 Transmission Media Interface
The bottom halves of Figure 5.1 and Figure 5.2 illustrate the COM20022I interface to the transmission
media used to connect the node to the net work. Table 5.1 lists different types of cable which are su itable
for ARCNET applications. The user may interface to the cable of choice in one of three ways:
A2-A0, nCS
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
VALID
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5.2.1 Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid
Interface is recommended if the n ode is to b e pl aced in a n et work with other Hybrid-Interf aced no des. T he
Traditional Hybrid Interface is for use with nodes operating at 2.5 Mbps on ly. The transformer coupling of
the Hybrid offers isolation for the safety of the system and offers high Common Mode Rejection. The
Traditional Hybrid Interface us es circuits lik e SMSC's HYC9 068 or HYC90 88 to transfer t he pu lse- encoded
data between the cable and the COM20022I. The COM20022I transmits a logic "1" by generating two
100nS non-overlapping negative pulses, nPULSE1 and nPULSE2. Lack of pulses indicates a logic "0".
The nPULSE1 and nPULSE2 sign als are sent to the Hybrid, which creates a 200nS dipulse signal on th e
media. A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse
appearing on the media is coupled through the RF transformer of the LAN Driver, which produces a
positive pulse at the RXIN pi n of the COM20022I. The pulse on the RXI N pin represen ts a logic "1". Lack
of pulse represents a logic "0". Typically, RXIN pulses occur at multiples of 400 nS. The COM20022I ca n
tolerate distortion of plus or minus 100nS and still correctly capture and convert the RXIN pulses to NRZ
format. Figure 5.4 illustrates the ev ents which occur in transmission or reception of data consisting of 1,
1, 0.
5.2.2 Backplane Configuration
The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications
like backplanes and instrumentation. T his mode is advant ageous bec aus e it saves components, cost, and
power.
Since the Backplane Configuration encodes data differently than the traditional Hybrid Configuration,
nodes utilizing the Backplane Configuration cannot communicate directly with nodes utilizing the
Traditional Hybrid Configuration. The Backplane Configuration does not isolate the node from the media
nor protects it from Common Mode noise, but Common Mode Noise is less of a problem in short
distances.
The COM20022I supplies a programmable output driver for Backplane Mode operation. A push/pull or
open drain driver can be selected by programming the P1MODE bit of the Setup 1 Register (see regist er
descriptions for details). The COM20022I defaults to an open dra in output.
The Backplane Configuration provides for direct connection between the COM20022I and the media. Only
one pull-up resistor (in ope n drain configuration of the output driver) is re quired somewhere on the media
(not on each individual node). The nPULSE1 signal, in this mode, is an open drain or push/pull driver and
is used to directly drive th e media. It issues a 200 nS n egativ e pulse to tra ns mit a logic " 1". Note that when
used in the open-drain mode, the COM20022I does not have a fail/safe input on the RXIN pin. The
nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of the
resistor required on the media for open drain mode.
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Figure 5.8 - COM20022I Network Using RS-485 Differential Transceivers
Figure 5.9 - Dipulse Waveform for Data of 1-1-0
In typical applications, the serial backplane is terminated at both ends and a bias is provided by the
external pull-up resistor.
The RXIN signal is directly connecte d to the cable vi a an internal Schmitt trigg er. A negative pulse on thi s
input indicates a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane
applications, RXIN is connected to nPULSE 1 to make the serial backplane data line. A ground line (from
the coax or twisted pair) should run in parallel with the signal. For applications requiring different treatment
of the receive signal (like filtering or squelching), nPULSE1 and RXIN remain as independent pins.
External differential drivers/receivers for increased range an d common mode noise rejection, for exampl e,
would require the signals to be independent of one another. When the device is in Backplane Mode, the
clock provided by the nPULSE2 signal may be used for encoding the data into a different encoding
scheme or other synchronous operations needed on the serial data stream.
20MHZ
CLOCK
(FO R R E F.
ONLY)
nPULSE1
nPULSE2
DIPULSE
RXIN
10
100ns
100ns
200ns
400ns
1
COM20022I COM20022I COM20022I
+VCC
RBIAS +VCC +VCC
RBIAS RBIAS
RT RT
75176B or
Equiv.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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5.2.3 Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled
configuration recommended for applications like car-area networks or other cost-sensitive applications
which do not require direct compatibility with existing ARCNET nodes and do not require isolation. The
Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid
Configuration. Like the Backplane Config uration, the Differentia l Driver Configuration does not iso late the
node from the media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable
and the COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is
active. The nPULSE1 sign al issues a 200nS (at 2.5Mbps) negative pu lse to transmit a logic "1". Lack of
pulse indicates a logic "0". T he RXIN signal r eceiv es t he dat a, the tr ansmitt er portio n of t he COM200 22I is
disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive.
5.2.4 Programmable TXEN Polarity
To accommodate transceivers with active high ENABLE pins, the COM20022I contains a programmable
TXEN output. T o program the TXEN pin for an active high pulse, the nPULSE2 p in should be connected
to ground. To retain the normal active low polarity, nPULSE2 should be left open. The polarity
determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2
pin should remain grounded at all times if an active high polarity is desired.
Figure 5.10 - Internal Block Diagram
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
STATUS/
COMMAND
REGISTER
RESET
LOGIC
RECONFIGURATION
TIMER NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
ADDRESS
DECODING
CIRCUITRY 2K x 8
AD0-AD2,
BUS
ARBITRATION
CIRCUITRY
nPULSE1
nPULSE2
nTXEN
nINTR
nRESET
RAM
A0/nMUX
A1
A2/BALE
nRD/nDS
nWR/DIR
nCS
D3-D15
RXIN
nIOCS16
XTAL1
XTAL2
DMA
DREQ
nDACK
TC
nREFEX
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DATASHEET
Table 5.1 - Typ ic al Med i a
CABLE TYPE NOMINAL
IMPEDANCE ATTENUATION PER 1000 FT.
AT 5 MHZ
RG-62 Belden #86262 93Ω 5.5dB
RG-59/U Belden #8910 8 75Ω 7.0dB
RG-11/U Belden #8910 8 75Ω 5.5dB
IBM Type 1* Belden #89688 150Ω 7.0dB
IBM Type 3* Telephone Twisted Pair Belden #1155A 100Ω 17.9dB
COMCODE 26 AWG Twisted Pair Part #105- 064-703 105Ω 16.0dB
Note*: Non-plenum-rated cables of this type are also available.
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Chapter 6 Functional Description
6.1 Microsequencer
The COM20022I contains an internal microsequencer which performs all of the control operations
necessary to carry out th e ARCNET protocol. It consists of a cl ock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20022I derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20022I. The 20 MHz
clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which the
instructions are executed. The microprogram is stored in the ROM and the instructions are fetched and
then placed into the instruction registers. One register holds the opcode, while the other holds the
immediate data. Once the in struction is f etched, it is d ecoded by the internal instruction decoder, at which
point the COM20022I proceeds to execute the instruction. When a no-op instruction is encountered, the
microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is
complete. When a jump instruction is encountered, the program counter is loaded with the jump address
from the ROM. The COM20022I contains an internal reconfiguration timer which interrupts the
microsequencer if it has t imed out. At this point the program counter is cleared and the MYRECON bit of
the Diagnostic Status Register is set.
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Table 6.1 - Read Register Summary
REGISTER
MSB READ
LSB
ADDR
STATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/
TTA 00
DIAG.
STATUS MY-
RECON DUPID RCV-
ACT TOKEN EXC-
NAK TENTID NEW
NEXTID X 01
ADDRESS
PTR HIGH RD-
DATA AUTO-
INC X X
DMA-
EN A10 A9 A8 02
ADDRESS
PTR LOW A7 A6 A5 A4 A3 A2 A1
A0/
SWAP 03
DATA* D7 D6 D5 D4 D3 D2 D1 D0 04
SUB ADR (R/W)* 0 0 0 (R/W)*
SUB-
AD2 SUB-
AD1 SUB-
AD0 05
CONFIG-
URATION RESET CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-
AD1 SUB-
AD0 06
TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 07-0
NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 07-1
SETUP1 P1
MODE FOUR
NAKS X RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB 07-2
NEXT ID NXT
ID7 NXT
ID6 NXT
ID5 NXT
ID4 NXT
ID3 NXT
ID2 NXT
ID1 NXT
ID0 07-3
SETUP2 RBUS-
TMG X CKUP1 CKUP0 EF NO-
SYNC RCN-
TM1 RCM-
TM2 07-4
BUS
CONTROL W16 X ITCEN/
RTRG TC8/
RSYN/
GTTM
DMA-
MD1 DMA-
MD0 TCPOL DRQ-
POL 07-5
DMA
COUNT TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
TC4/
TIM4/
CYC4
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TC1/
TIM1/
CYC1
TC0/
TIM0/
CYC0
07-6
Note*: This bit can be written and read.
*DATA REGISTER AT 16 BIT ACCESS
REGISTER BIT
15 BIT
14 BIT
13 BIT
12 BIT
11 BIT
10 BIT
9 BIT
8 BIT
7 BIT
6 BIT
5 BIT
4 BIT
3 BIT
2 BIT
1 BIT
0 ADDR
DATA D
15 D
14 D
13 D
12 D
11 D
10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04
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Table 6.2 - Write Register Summary
ADDR
MSB WRITE
LSB
REGISTER
00 RI/TR1 0 0 DMA
END EXCNAK RECON NEW
NEXTID TA/
TTA INTERRUPT
MASK
01 C7 C6 C5 C4 C3 C2 C1 C0
COMMAND
02 RD-
DATA AUTO-
INC 0 0 DMAEN A10 A9 A8
ADDRESS
PTR HIGH
03 A7 A6 A5 A4 A3 A2 A1
A0/
SWAP ADDRESS
PTR LOW
04 D7 D6 D5 D4 D3 D2 D1 D0 DATA*
05 (R/W)* 0 0 0 (R/W)*
SUB-
AD2 SUB-
AD1 SUB-
AD0 SUBADR
06 RESET CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-
AD1 SUB-
AD0 CONFIG-
URATION
07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID
07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID
07-2 P1-
MODE FOUR
NAKS 0 RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB SETUP1
07-3 0 0 0 0 0 0 0 0 TEST
07-4 RBUS-
TMG 0 CKUP1 CKUP0 EF NO-
SYNC RCN-
TM1 RCN-
TM0 SETUP2
07-5 W16 0 ITCEN/
RTRG TC8/
RSYN/
GTTM
DMA-
MD1 DMA-
MD0 TC-
POL DRQ-
POL BUS
CONTROL
07-6 TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
TC4/
TIM4/
CYC4
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TC1/
TIM1/
CYC1
TC0/
TIM0/
CYC0
DMA COUNT
Note*: This bit can be written and read.
*DATA REGISTER AT 16 BIT ACCESS
REGISTER BIT
15 BIT
14 BIT
13 BIT
12 BIT
11 BIT
10 BIT
9 BIT
8 BIT
7 BIT
6 BIT
5 BIT
4 BIT
3 BIT
2 BIT
1 BIT
0 ADDR
DATA D
15 D
14 D
13 D
12 D
11 D
10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04
6.2 Internal Registers
The COM20022I contains 1 6 internal registers. Table 6.1 and Table 6. 2 illustrate the COM200 22I register
map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20022I is capable of gener ating an interru pt signal when certain s tatus bit s become t rue. A write
to the IMR spec ifies which stat us bits will be enabled to generat e an interrupt . The bit posit ions in the IMR
are in the same position as their corresponding status bits in the Status Register and Diagnostic Status
Register. A logic "1" i n a partic ular posit ion en ables the corr espon ding i nterrupt . The St atus bits cap able of
generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I), New Next
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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DATASHEET
ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. DMAEND bit is
inverted DMAEN bit on ADDRESS PTR High register. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the int errupt signal. An RI or TA int errupt is masked when th e corresponding mask b it is reset to
logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
New Next ID interrupt is cleared by reading the Next ID Register. If the DMAEND bit is not masked, the
interrupt occurs by finishing the DMA operation. The Interrupt Mask Register defaults to the value 0000
0000 upon hard ware reset.
6.2.2 Data Register
This read/write 8-bit register is used as the channel throug h which the data t o and from the RAM passes.
The data is placed in or retrieved from the address location presently specified by the address pointer.
The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the
Data Register is loaded with the contents of COM20022I Internal Memory upon writing Address Pointer
low only once.
The SWAP bit is used to swap the upper and lower data byte. The SWAP bit is located at bit 0 of
ADDRESS PTR_LOW register. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit.
6.2.3 Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer t o the Configur ation Register a nd SUB ADR Regi ster). The Tentat ive ID Regist er
can be used while the node is on-line to build a network map of those nodes existing on the network. It
minimizes the nee d for operator int eraction with th e network. T he node determines t he existence of other
nodes by plac ing a Node ID value in the Tent ative ID Register an d waiting to see if the Tentat ive ID bit of
the Diagnostic Status Register gets set. The network map developed by this method is only valid for a
short period of time, since nodes may join or depart from the network at any time. When using the
Tentative ID feature, a node cannot detect the existence of the next logical node to which it passes the
token. The Ne xt ID Register will hold the ID value of that n ode. The T entative ID Regist er defaults to t he
value 0000 0000 upon hardware reset only.
6.2.4 Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Node ID Register
contains the unique value which identifies this particular node. Each node on the network must have a
unique Node ID value at all times. The Duplicate ID bit of the Diagnostic Status Register helps the user
find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the
DUPID bit. The core of the COM20022I does not wake up until a Node ID other than zero is written into
the Node ID Regist er. D urin g t his time, no m icroco de is e xecuted, no t okens are pass ed b y this nod e, a nd
no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID
Register, the c ore wakes up but will not join t he net work until the T XEN bit of the Configurat ion Registe r is
set. While the Transmitter is disabled, the Receiv er portion of the device is still functio nal and will provide
the user with useful information about the network. T he Node ID Register defaults to the value 0000 0000
upon hardware reset only.
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6.2.5 Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Next ID Register
holds the value of the Node ID to which the COM20022I will pass the token. When used in conjunction
with the Tentative ID Register, the Next ID Register can provide a complete network map. The Next ID
Register is updated e ach time a nod e ent ers/leav es the n etwork or when a net work reconfigurat i on occu rs.
Each time the microsequencer updates the Next ID Register, a New Next ID interrupt is generated. This
bit is cleared by readi ng the Next ID Register. Default value is 0000 0000 upon hardware or software reset .
6.2.6 Status Register
The COM20022I Stat us Register is an 8-bit read-only regi ster. All of the bits, except for bits 5 and 6, are
software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the
Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20022I, the
COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these
bits exist in an d are controlle d by the Conf iguration R egister. T he Status Regist er conte nts are defin ed as
in Table 6.3, but are defined differently during the Command Chaining operation. Please refer to the
Command Chaining secti on for the definition of t he Status Register during Command Cha ining operation.
The Status Register def aults to the value 1XX1 0001 upon either hardware or soft ware r eset.
6.2.7 Diagnostic Status Register
The Diagnostic Status Register contains seven read-only bits which help t he user troubleshoot the network
or node operation. Various combinations of these bits and the TXEN bit of the Configuration Register
represent different situations. All of these bits, exce pt the Excessive NAcK bit and the New Next ID bit, are
reset to logic "0" upon reading the Diagnostic Status Register or upon software or hardware reset. The
EXCNAK bit is reset by the "POR Clear Flags" command or upon software or hardware reset. The
Diagnostic Status Register defaults to the value 0000 000X upon either hardware or software reset.
6.2.8 Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any
combinations of written data other than those listed in Table 6.5 are not permitted and may result in
incorrect chip and/or network operation.
6.2.9 Address Pointer Registers
These read/ wri te registers are each 8-bits wide and are used for addressing the internal RAM. New pointer
addresses should be written by first writing to the High Register and then writing to the Low Register
because writing t o t he Low Register loads the address. The contents of the Address Pointer High and L ow
Registers are undefined upon hardware reset . Writing to Address Pointer l ow loads the address.
The DMAEN bit (new to the COM20022I) is located at bit 3 of the ADDRESS PTR HIGH register. The
DMAEN bit is used to Disable/Enable the assertion of the DMA Request (DREQ pin) after writing the
Add res s P oin te r Lo w r egi ste r. The SWAP bit (new to the COM2 0022I) is located at bit 0 of Address Point er
Low register. The SWAP bit is used to swap the upper and lower data byte. When 16 bit access is enabled,
(W16=1), A0 becomes the SWAP bi t.
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6.2.10 Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the
COM20022I. The Configuration Register defaults to the value 0001 1000 upon hardware reset only.
SUBAD0 and SUBAD1 point to the selection in Register 7.
6.2.11 Sub-Address Register
The sub-a ddress register is new to the COM200 22I, previou sly a reserved re gister. Bits 2, 1 and 0 are use d
to select one of the registers assigned to address 7h. S UBAD1 a nd SU BAD0 . They are ex actl y same as
those in the Configuration register. If the SUBAD1 and SUBAD0 bits in the Configuration register are
changed, the SUBAD1and S U BAD0 in th e S ub-Ad dress regist er are also chan ge d. SUBAD2 is a ne w sub-
address bit. It Is used t o access the 3 ne w Set Up registers, SETUP2, BUS CONT ROL and DMA COUNT.
These registers are selected by setting SUBAD2=1. The SUBAD2 bit is cleared automatically by writing
the Configurat ion register.
Write Bits[7:3] to ‘0’ for proper operation.
6.2.12 Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (see the bit definitions of the Configuration Register). The Setup 1 Register allows the user to
change the network speed (data rate) or the arbitration speed independently, invoke the Receive All feature
and change the nPULSE1 driver type. The data rate may be slowed to 156.25Kbps and/or the arbitration
speed may be slowed by a factor of two. The Setup 1 Register defaults to the value 0000 0000 upon
hardw are re se t only .
6.2.13 Setup 2 Register
The Setup 2 Register is new to the COM20022I. It is an 8-bit read/write register accessed when the Sub
Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). T his
register contains bits f or various functions. The CKUP 1,0 bits select the clock to be gen erated f rom the 20
MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus
support. The EF bit is used t o enable the n ew timing for cert ain functions in t he COM20022I (if EF = 0, the
timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to enable
the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM
initialization sequence to be writte n. If set, the li ne does not have t o be idle for the in itialization seque nce
to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for
shorter time periods has the benef it of shortened n etwork reconfigurat ion periods. T he time periods sh own
in the table on the following page are lim ited by a maximum number of nodes in the network. These time-
out period valu es are for 10Mbps. For other dat a rates, scale the time-out period time values accordingl y;
the maximum node cou nt remains the same.
RCNTM1 RCNTM0 TIME-OUT PERIOD MAX NODE COUNT
0 0 210 mS Up to 255 nodes
0 1 52.5 mS Up to 64 nodes
1 0 26.25 mS Up to 32 nodes
1 1 13.125 mS* Up to 16 nodes (Note 6.1)
Note 6.1 The node ID value 255 must exist in the net wor k for the 13.125 mS time-out to be valid.
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6.3 Bus Control Register
The Bus Control Register is new to the COM20022I. It is an 8-bit read/write register accessed when the
Sub Address Bit s SUBAD[2:0] are set up acc ordingly (see the bit defin itions of the Sub Address Register).
This register contains bits for control of the DMA functionality. The DRQPOL bit is used to set the active
polarity of the DREQ pin. The TCPOL bit is used to set t he active polarity of T C pin.
The DMAMD[0,1] bits select the data transfer mode of the DMA, either non-burst, burst, Programmable-
Burst by timer or programmable burst by cycle counter.
This transfer mode inf luences to the timing the DREQ pin. The use of the ITCEN/RTRG bit transfer mode
dependent. ITCEN is the Internal Terminal Counter Enable. It is used to select whether the DMA is
terminated by external TC or by either internal or external TC. ITCEN is for Non-Burst or Burst mode.
RTRG selects the re-trigger mode as either external or internal. It is for the two Programmable-Burst
modes. If RTRG = 0, the deasserted DREQ pin is reasserted on the falling edge of the nREFEX pin. If
RTRG = 1, the deassert ed DREQ pin is reasserted by the t imeout of the internal timer (350 ns or 7 50 ns,
as selected by the GTTM bit.) See Figure below.
RTRG=0
nREFEX 350/750ns
DREQ
nDACK
nWR/nRD
RTRG=1
DREQ
nDACK
nWR/nRD
Figure 6.1 - Illustration of the Effe ct of RTRG Bit on DMA Timing
The use of the TC8/RSYN/GTTM bit is also transfer mode dependent. TC8 is bit 8 of the Terminal Count
register. RSYN is the r efresh synchronous bi t; it is used to select whether the DMA is start ed immediately
or after Refresh execution. GTTM is the Gate Time bit; it is used to select the gate time of the
Programmable-Burst t ransfer.
TC8 is for Non-Burst or Burst mode. RSYN a nd GTTM are for the two Programmabl e-Burst modes.
The W16 bit is used to enab le/disable the 16 bit access.
6.4 DMA Count Register
The DMA COUNT Register is new to t he COM20022I. It is an 8-bit read/write register accessed when the
Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register).
This register contains bits for control of the DMA functionality. The TC7-TC0 /TIM7-TIM0 /CYC7-CYC0
bits have one of three functions depending on the DMA transfer mode. TC7-TC0 are for Non-Burst or
Burst mode. These are the lower 8 bits of the Terminal Count setting register (the MSB is in the Bus
Control Register). The TIM7-TIM0 bits are for setting the time of the continuous DMA transfer in
Programmable-Burst by Timer mode. The CYC7-CYC0 bits are for setting the cycle count value of the
continuous DMA transfer in Programmable-Burst by cycle mode.
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Table 6.3 - Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Receiver
Inhibited RI This bit, if high, indicates that the receiver is not enabled bec ause either
an "Enable Receive to Page fnn" command was never issued, or a packet
has been deposited into the RAM buffer page fnn as specified by the last
"Enable Receive to Page fnn" command. No messages will be received
until this command is issue d, and once the message has been received,
the RI bit is set, thereby inhibiting the receiver. The RI bit is cleared by
issuing an "Enable Receive to Page fnn" command. This bit, when set,
will cause an interrupt if the corresponding bit of t he Interrupt Mask
Register (IMR) is also set. When this bit is set and another station
attempts to send a packet to this station, this station will send a NAK.
6,5 (Reserved) These bits are undef ined.
4 Power On Reset POR This bit, if high, indicates t hat the COM20022I has been reset by either a
software reset, a hardware reset, or writing 00H to the Node ID Register.
The POR bit is cleared by the "Clear Flags" command.
3 Test TEST This bit is intended for test and diagnostic purposes. I t is a logic "0" under
normal operating conditi ons.
2 Reconfiguration RECON This bit, if high, indicates that the Line Idle Timer has timed out beca use
the RXIN pin was idle for 20. 5μS. The RECON bit is cleared during a
"Clear Flags" command. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set. The interrupt service routine
should consist of examining t he MYRECON bit of the Diagnostic Status
Register to determine whether there are consecut ive reconfigurations
caused by this node.
1
Transmitter
Message
Acknowledged
TMA This bit, if high, indicates that the packet transmitted as a result of an
"Enable Transmit f r om Page fnn" command has been ack nowledged.
This bit should onl y be considered valid af ter the TA bit (bit 0) is set.
Broadcast messages are never acknowledged. The TMA bit is cleared by
issuing the "Enable Transmit from Page fnn" command.
0 Transmitter
Available TA This bit, if high, indicates that the transmitter is available for transmitting.
This bit is set when the last byte of scheduled packet has been
transmitted out, or upon execution of a "Disable Transmitter" command.
The TA bit is cleared by issui ng the "Enable Transmit from Page fnn"
command after the node next receives the token. This bit, when set, will
cause an interrupt if t he corresponding bit in t he IMR is also set.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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Table 6.4 - Diagnostic Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 My Reconfiguration MY-
RECON This bit, if high, indicates that a past reconfiguration was caused by this
node. It is set when the Lost Token Timer times out, and should be
typically read following an interrupt caused by RECON. Refer to the
Improved Diagnostics sectio n for further detail.
6 Duplicate ID DUPID This bit, if high, indic at es that the value in the Node ID Register matches
both Destination ID characters of the token and a response to t his token
has occurred. Trailing zero's are also verified. A logic "1" on this bit
indicates a duplicate Node ID, thus t he user should write a ne w value int o
the Node ID Register. This bit is only useful for duplicate ID detection
when the device is off line, that is, when the transmitter is disabled. When
the device is on line this bit will be set every time the device gets the
token. This bit is reset automatically upon re ading the Diagnostic St atus
Register. Refer to the Im proved Diagnostics section f or f urther detail.
5 Receive
Activity RCVACT This bit, if high, indicates that data activity (logic "1") was detected on the
RXIN pin of the device. Refer to the Improved Dia gnostics section for
further detail.
4 Token Seen TOKEN This bit, if high, indic ates that a token has been seen on the network, sent
by a node other than this one. Refer to the Improved Diagnostic section
for further detail.
3 Excessive NAK EXCNAK This bit, if high, indicat es t hat either 128 or 4 Negative Acknowledgements
have occurred in response to the Free Buffer Enquiry. This bit is cleared
upon the "POR Clear Flags" comman d. Reading the Diagnostic Status
Register does not clear this bit. This bit, when set, will cause an interrupt
if the corresponding bit in the IMR is also set. Refer to the Improved
Diagnostics section for further detail.
2 Tentative ID TENTID This bit, if high, indicates that a response to a token whose DID mat c hes
the value in the Tent ative ID Register has occurred. The second DID and
the trailing zero's are not checked. Since each no de sees every token
passed around the network, this feature can be used with the device on-
line in order to build and update a network map. Refer to the Improved
Diagnostics section for further detail.
1 New Next ID NEW
NXTID This bit, if high, indicates that the Next ID Register has been updated and
that a node has either joined or left the network. Reading the Diagnostic
Status Register does not clear this bit. This bit, when set, will cause an
interrupt if the corresponding bit in the IMR is also set. The bit is cleared
by reading the Next ID Register.
1,0 (Reserved) These bits are undef ined.
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Table 6.5 - Comma n d Regis t e r
DATA COMMAND DESCRIPTION
0000 0000 Clear
Transmit
Interrupt
This command is used only in the Command Chaining operation. Please
refer to the Command Chai ning section for definition of this command.
0000 0001 Disable
Transmitter This command will cancel a ny pending transmit command (transmission
that has not yet started) and will set the T A (Transmitter Available) status
bit to logic "1" when the COM20022I next receives the token.
0000 0010 Disable
Receiver This command will cancel any pending receiv e command. If the
COM20022I is not yet receiving a packet, the RI (Receiver Inhibited) bit
will be set to logic "1" the next time the token is received. If packet
reception is already underway, reception will run to its norm al
conclusion.
b0fn n100 Enable
Receive to
Page fnn
This command allows the COM20022I to receive data packets into RAM
buffer page fnn and resets the RI status bit to logic "0". The values
placed in the " nn" bits indicate t he page that the dat a will be received
into (page 0, 1, 2, or 3). If the value of "f" is a logic "1 ", an offset of 256
bytes will be added to that page specified in "nn", allowing a finer
resolution of the buffer. Refer to the Selectin g RAM Page Size section
for further detail. I f t he value of "b" is logic "1", the device will also
receive broadcasts (transmissions to ID zero). The RI status bit is set to
logic "1" upon successful reception of a message.
00fn n011 Enable
Transmit from
Page fnn
This command prepares t he COM20022I to begin a transmit seque nce
from RAM buffer page fnn the next time it receives t he token. The
values of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3).
If "f" is logic "1", an of fset of 256 bytes is the start of the page specified in
"nn", allowing a finer resolution of the buffer. Refer to the Selecti ng RAM
Page Size section for furt her detail. When this command is loaded, the
TA and TMA bits are reset t o logic "0". The TA bit is set t o logic "1" upon
completion of the transmit sequence. T he TMA bit will have been set by
this time if the device has received an ACK from the dest ination node.
The ACK is strictly hardware level, sent by the receiving node before it s
microcontroller is even aware of message receptio n. Refer to Figure 3.1
for details of the transmit sequence and it s relation to the TA and TMA
status bits.
0000 c101 Define
Configuration This command defines th e maximum length of packets t hat may be
handled by the device. If "c" is a logic "1", the devic e handles both long
and short packets. If "c" is a logic "0", the device handles only short
packets.
000r p110 Clear Flags This command resets certain status bits of the COM200 22I. A logic "1"
on "p" resets the POR status bit and the EXCNAK Diagnosti c status bit.
A logic "1" on "r" resets the RECON status bit.
0000 1000 Clear
Receive
Interrupt
This command is used only in the Command Chaining operation. Please
refer to the Command Chai ning section for definition of this command.
0001 1000 Start Internal
Operation This command restarts the stopped internal operation after changin g
CKUP1 or CKUP0 bit.
0001 0000 Clear Mask bit of
DMAEND This command resets a mask bit of the DMAEND. It is for clearing
interrupt by DMA transfer finished.
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Table 6.6 - Address Pointer High Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Data RDDATA This bit tells the COM20022I whether the following access will b e
a read or write. A logic "1" prepares the device for a read, a logic
"0" prepares it for a write.
6 Auto Increment AUTOINC This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic increment of
the pointer afte r each access, while a logic "0" disab les this
function. Please ref er t o the Sequential Access Memory section
for further detail.
5-4 (Reserved) These bits are und efined.
3 DMA Enable DMAEN This bit is used to Disable/Ena ble the assertion of the DMA
Request (DREQ pin) after writing the Address Pointer Low
register. DMAEN=0: Disable (Default). DMAEN=1: Enable the
assertion of the DREQ pin after writing the Address Pointer Low
register. Writing DMAEN=0 d uring the DMA operation will negate
the DREQ pin immediatel y. The DMA operation is terminated
immediately after the next DACK pin negation. The inverting
signal of DAMEN is the I nt errupt source signal DMAEND. The
DMAEN bit is cleared automatically by finishing the DMA. If the
DMAEND bit in the Mask regis ter is not masked, the Interrupt
occurs by finishing the DMA operation.
2-0 Address 10-8 A10-A8 These bits hold the upp er three address bits which provide
addresses to RAM.
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Table 6.7 - Address Pointer Low Register
BIT BIT NAME SYMBOL DESCRIPTION
7-0 Address 7-0 A7-A0
SWAP
These bits hold t he lower 8 address bits which provide the
addresses to RAM.
When 16 bit access is enabled, (W16=1), A0 becomes the SWAP
bit. Swap bit is undefined after a hardware reset. The swap bit
must be set before W16 bit is set to “1”. The swap bit is used to
swap the upper and lower data byte. The swap bit influences
both CPU cycle and DMA cyc le. See Table Below.
Detected Host Interface
Mode Swap Bit D15-D8
Pin D7-D0 Pin
Intel 80xx Mode 0 Odd Even
(RD, WR Mode) 1 Even Odd
Motorola 68xx Mode 0 Even Odd
(DIR, DS Mode) 1 Odd Even
Table 6.8 - Sub Address Register
BIT BIT NAME SYMBOL DESCRIPTION
7-3 Reserved These bits are undefined.
2,1,0 Sub Address 2,1,0 SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0 0 0 Tentative ID \ (Same
0 0 1 Node ID \ as in
0 1 0 Setup 1 / Config
0 1 1 Next ID / Register)
1 0 0 Setup 2
1 0 1 Bus Control
1 1 0 DMA Count
1 1 1 Reserved
SUBAD1 and SUBAD0 are e xactly the same as e xist in the
Configuration Register. SUBAD2 is cleared aut omatically by writing
the Configuration Register.
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Table 6.9 - Configuration Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Reset RESET A software reset of the COM2002 2I is executed by writing a logic
"1" to this bit. A software reset does not reset the microcontroller
interface mode, nor does it affect the Configu r ation Register. The
only registers that t he software reset affect are the Status
Register, the Next I D Register, and the Diagnostic Status
Register. This bit must be brought back to logic "0" to release the
reset.
6 Command
Chaining Enabl e CCHEN
This bit, if high, enables the Command Chaining operation of the
device. Please refer to t he Command Chaining section f or f urther
details. A low level on this bit ensures software compatibility with
previous SMSC ARCNET devices.
5 Transmit Enable TXEN When low, this bit disables transmissions by keep ing nPULSE1,
nPULSE2 if in non-Backpl ane Mode, and nTXEN pin inactive.
When high, it enables the above signals to be activated duri ng
transmissions. This bit defaults low upon reset. This bit is
typically enabled once the Node ID is determined, and never
disabled during normal operation. Please ref er t o the Improved
Diagnostics section for details on evaluati ng network activity.
4,3 Extended
Timeout 1,2 ET1, ET2 These bits allow the network to operat e over longer distances
than the default maximum 1 mile by controlling the Response,
Idle, and Reconfiguration Times. All nodes should be configured
with the same timeout values for proper network oper ation. For
the COM20022I with a 20 MHz crystal oscillator, the bit
combinations follow:
ET2
0
0
1
1
ET1
0
1
0
1
Response
Time (μS)
298.4
149.2
74.7
18.7
Idle Time
(μS)
328
164
82
20.5
Reconfig
Time
(mS)
420
420
420
210
Note: These values are for 10Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
2 Backplane BACK-
PLANE
A logic "1" on this bit puts t he device into Backplane Mode
signaling which is used for Open Drain and Differential Driver
interfaces.
1,0 Sub Address 1,0 SUBAD 1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD1 SUBAD0 Register
0 0 Tentative ID
0 1 Node ID
1 0 Setup 1
1 1 Next ID
See also the Sub Addr ess Register.
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Table 6.10 - Setup 1 Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used in
Backplane Mode. When hi gh, a push/pull output is used. When
low, an open drain output is used. T he default is open drain.
6 Four NACKS FOUR
NACKS This bit, when set, will cause the EXNACK bit in the Diagnostic
Status Register to set after four NACKs to Free Buffer Enquiry are
detected by the COM20022I. This bit, when reset , will set the
EXNACK bit aft er 128 NACKs to Free Buffer Enquiry. The default
is 128.
5 Reserved Do not set.
4 Receive All RCVALL This bit, when set, allows the COM20022I to receive all valid data
packets on the network, regardless of their destination ID. This
mode can be used to implement a network monitor with the
transmitter on- or off - line. Note that ACKs are only sent for
packets received with a destination ID equal to the COM20022I's
programmed node ID. This feature can be used to put the
COM20022I in a 'listen-only' mode, where the transmit ter is
disabled and the COM20022I is not passing tokens. Defaults low.
3,2,1 Clock Prescaler Bits
3,2,1 CKP3,2,1 These bits are used to determine the data rate of t he COM20022I.
The following table is for a 20 MHz crystal: (Clock Multiplier is
bypassed)
CKP3
0
0
0
0
1
CKP2
0
0
1
1
0
CKP1
0
1
0
1
0
DIVISOR
8
16
32
64
128
SPEED
2.5Mbs
1.25Mbs
625Kbs
312.5Kbs
156.25Kbs
Note: The lowest data rate achievable by the COM20022I is
156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multi plier
output clock sp eed gr eater tha n 20 MHz, CKP3, CKP2 and
CKP1 must all be zero.
0 Slow Arbitration
Select SLOWARB This bit, when set, will divide the arbit r ation clock by 2. Memor y
cycle times will increase when slow arbitration is select ed.
Note: For clock multiplier output clock speeds greater than 40
MHz, SLOWARB must be set. Defaults to low.
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Table 6.11 - Setup 2 Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Bus Timing
Select RBUSTMG This bit is used to Disabl e/Enable the High Spee d CPU Read
function for High Spee d CPU bus support. RBUSTMG=0: Disable
(Default), RBUST MG=1: Enable. That is, if BUST MG (pin 26) = 1
and RBUSTMG = 1, High Speed CPU Read operations are
enabled. It does not influence write operation. High speed CPU
Read operation is onl y for non-multiplexed b us.
6 Reserved This bit is undefined.
5,4 Clock Multiplier CKUP1, 0 Higher frequency clocks are generated from the 20 MHz crystal
through the selection of these two bits as shown. This clock
multiplier is powere d-down on default. Af ter changing the CKUP1
and CKUP0 bits, the ARCNET core operati on is stopped and the
internal PLL in the clock mult iplier is awakened and it starts to
generate the 40 MHz. T he lock out time of the internal PLL is 8μSec
typically. After 1 mS it is necessary to write comman d dat a '18H' to
command register for re-starting the ARCNET core operation. EF
bit must be ‘1’ if the data rate is over 5Mbps.
CAUTION: Changing the CKUP1 and CKU P 0 bits must be one
time or less after releasing a hardware reset.
CKUP1 CKUP0 Clock Frequency (Data Rate)
0 0 20 MHz (Up to 2.5Mbps) Def ault
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 80 MHz (Only 10Mbps)
Note: After changing the CKUP1 or CKUP0 bits, it is necessary to
write a command data '18H' to the command register.
Because after changing the CKUP [1, 0] bits, the internal
operation is stopped temporarily. The writing of the
command is to start the operation.
These initializi ng steps are shown below.
1. Hardware reset (Power ON)
2. Change CKUP [1, 0] bit
3. Wait 1mSec (wait until stable oscillation)
4. Write command '18H' (start internal operation)
5. Start initializin g routine (Execute existing soft ware)
3 Enhanced Functions EF This bit is used to enable the new enhanced functions in the
COM20022I. EF = 0: Disable (Default), EF = 1: Enable. If EF = 0,
the timing and function is the same as in the COM20020, Revision
B. See appendix “A”. EF bit must be ‘1’ if the data rate is over
5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
2 No Synchronous NOSYNC This bit is used to enable t he SYNC command during init ialization.
NOSYNC= 0, Enable (Default) The line must be idle for the RAM
initialization se quence to be written. NOSYNC= 1, Disable:) The line
does not have to be idle f or the RAM initialization sequence to be
written. See ap pendix “A”.
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BIT BIT NAME SYMBOL DESCRIPTION
1,0 Reconfiguration Timer
1, 0 RCNTM1,0 These bits are used to program the reconfiguration timer as a
function of maximum node count. These bits set the time out period
of the reconfiguration timer as shown below. The time out periods
shown are for 10 Mbps.
RCNTM1 RCNTM0 Time Out Period Max Node Count
0 0 210 mS Up to 255 nodes
0 1 52.5 mS Up to 64 nodes
1 0 26.25 mS Up to 32 nodes
1 1 13.125 mS* Up to 16 nodes
Note*: The node ID value 255 must exist in the network for 13.125
mS timeout to be valid.
Table 6.12 - Bus Control Register
BIT BIT NAME SYMBOL DESCRIPTION
7 16 Bit Access W16 This bit is used to Disable/Enable the 16 bit access. It influences
both CPU cycle and DMA cyc le. W16= 0: Disable (Default); W16=
1: Enable
6 Reserved This bit is undefined.
5 Internal Terminal
Counter Enable;
Re-Trigger mode
ITCEN/
RTRG The function of this bit is mode dependent. ITCEN is for Non-Burst
or Burst mode. RTRG is f or the two Programmable-Burst modes.
ITCEN = 0: T erminate the DMA only by External T C. ITCEN = 1:
Terminate the DMA by Internal or External TC.
RTRG = 0: External Re-Trigger mode; Negated DREQ pin is Re-
asserted by falling e dge of nREFEX pin. RTRG = 1: Internal Re-
Trigger mode; Negated DREQ pin is Re-asserted by timeout of
internal gate timer (350ns/750ns).
4 Terminal Count
Bit 8
Refresh Synchr onous
Gate Time
TC8/
RSYN/
GTTM
The function of t his bit is mode dependent. T C8 is for Non-burst or
burst mode. RSYN and GTTM are for t he two Programmable-Burst
modes. RSYN is for External Re-Trigger mode. GTTM is for internal
Re-Trigger mode.
Non-burst or burst mode:
TC8: Bit 8 (MSB) of 9 bit T erminal Count setting register. The other
8 bits are in the DMA Count regist er. Terminal Count setting register
is ignored when ITCEN = 0.
Programmable-Burst and External Re-Trigger mode:
RSYN = 0: DMA is started Immedi ately.
RSYN = 1: DMA is started after Refr esh execution.
Programmable-Burst and Internal Re-Trigger mode:
GTTM = 0: Gate Time is 350nS (min)
GTTM = 1: Gate Time is 750nS (min)
3,2 DMA Transfer Mode DMAMD1,D
MAMD0 These bits select the data transf er mode of the DMA. These transfer
modes influence t he timing of asserting/negating the DREQ pin.
DMAMD1 DMAMD0 Transfer Mode
0 0 Non-Burst (Default)
0 1 Burst
1 0 Programmable-Burst by Timer
1 1 Programmable-Burst by Cycle Counter
1 TC Polarity TCPOL This bit sets t he Active polarity of TC pin.
TCPOL = 0: Active High (Default), TCPOL = 1 Active Low
0 DREQ Polarity DRQPOL This bit sets the Active polarity of DREQ pin.
DRQPOL = 0: Active High (Default), DRQPOL = 1 Active Low
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Table 6.13 - DM A Count Register
BIT BIT NAME SYMBOL DESCRIPTION
7-0 Terminal Count
Timer Mode
Cycle Mode
TC7-TC0
TIM7-TIM0
CYC7-CYC0
TC7-TC0: Used f or non-burst or burst mode. These are the lower 8
bits of the Terminal Count setting register. T he MSB (TC8) is in the
Bus Control Register. The Terminal Count setting range is from 1 to
512 counts (TC8 - TC0 all zeroes mea ns 512 counts).
TIM7-TIM0: Used for Programmable-Burst by Timer mode. These bits
are for setting the term of the continuous DMA transfer. The time
range is from 100nS to 25.6 μS. The step is 100nS (TIM7-TIM0 all
zeroes means 25.6μs).
CYC7-CYC0: Used for Progr ammable-Burst by Cycle mode. These
bits are for setting the term of the continuous DMA transfer. The cycle
range is from 2 to 256 cycles. CYC7-CYC0 all zeroes means 256
cycles. (1 is illegal)
Address P ointer Register
Low
2K x 8
RAM
11
Data Register
8
I/O Address 04H
I/O Address 03H
11-Bit Counter
Memory
Address Bus
Memory
D ata B us
D0-D7
High
I/O Address 02H
INTERNAL
Figure 6.2 - Sequential Access Operation
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6.5 Internal RAM
The integration of the 2K x 8 RAM in the CO M20022I repre sents significa nt real estate s avings. T he most
obvious benefit is t he 4 8 pin p ackag e in which the device is now placed (a direct r esult of t he int egr ation of
RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and
multiplexed address/data bus and control functions which were necessary to interface to the RAM. The
integration of RAM represents significant cost savings because it isolates the system designer from the
changing costs of ext ernal RAM and it minim izes reliabilit y problems, assembl y time and costs, and layo ut
complexity.
6.5.1 Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory,
the internal RAM is in directly accessed thro ugh the Address Hig h and Low Pointer Re gisters. The data i s
channeled to a nd from t he microcontro ller via the 8-bit dat a register. F or examp le: a packet in the int ernal
RAM buffer is read by the microcontroller by writing the corresponding address into the Address Pointer
High and Low Registers (offsets 02H and 03H). Note that the High Register should be written first,
followed by the Low Register, because writing to the Low Register loads the address. At this point the
device accesses that location and places the corresponding data into the data register. The
microcontroller then reads the data register (offs et 04H) to obtain the data at the specif ied location. If the
Auto Increment bit is set to logic "1", the device will automatically increment the address and place the
next byte of da ta into the data regist er, again to be read by the microcontr oller. This process is cont inued
until the entire packet is read out of RAM. Refer to Figure 5.6 for an illustr ation of the Sequential Access
operation. When switching between reads and writes, the pointer must first be written with the starting
address. At least one cycle time should separate the pointer being loaded and the first read (see timing
parameters).
6.5.2 Access Speed
The COM20022I is abl e to ac commod ate ve r y fast access c ycles to its re gisters a nd buf f ers. Arbitr atio n t o
the buffer does not slow down the cycle because the pointer based access method allows data to be
prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the
temporary register and then written to memory.
For systems which do not require quick access t ime, the arbitration clock may be slowed down by setting
bit 0 of the Setup1 R egister e qual to lo gic "1 ". Since the S lo w Arbitration f eature divides t he input cl ock b y
two, the duty cycle of the input clock may be relaxed.
6.6 Software Interface
The microcontroller interfaces to the COM20022I via software by accessing the various registers. These
actions are described in t he Internal Registers section. The software flow for accessing the data buffer is
based on the Sequential Access scheme. The basic sequence is as follows:
Disable Interrupts
Write to Pointer Register High (specifying Auto-I ncrement mode)
Write to Pointer Register Low (this loads the address)
Enable Interrupts
Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
The pointer may now be read to determine how many transfers were completed.
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The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is
generally limited t o the initialization sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the
transmit and receive sequences and to know how the internal RAM buffer is properly set up. The
sequence of events that tie these actions together is discussed as follows.
6.6.1 Selecting RAM Page Size
During normal operat ion, the 2K x 8 of RAM is divided into four pages of 512 bytes e ach. The page to be
used is specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies
page 0, 1, 2, or 3. T his allows the user to have constant control over the allocat ion of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn " command word) is set
to logic "1", an offset of 256 bytes is added to the page specified. For example: to transmit from the second
half of page 0, the command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing
0010 0011 to the Command Register. This allows a finer resolution of the buffer pages without affecting
software compatibility. This scheme is useful for applications which frequently use packet sizes of 256
bytes or less, especially f or microcontroller s ystems with limited memor y capacit y. The remaini ng portions
of the buffer pages which are not allocated for current transmit or receive packets may be used as
temporary storage f or previous network data, packet s to be sent later, or as extra memor y for the system,
which may be indirect ly accessed.
If the device is configured to handle both long and short packets (see "Define Configuration" command),
then receive p ages sh ould alwa ys be 51 2 b ytes lo ng bec ause th e user never k nows what t he lengt h of the
receive packet will be. In this case, t he transmit pages ma y be made 256 bytes lo ng, leaving at le ast 512
bytes free at any given time. Even if the Command Chaining operation is being used, 512 bytes is still
guaranteed to be free because Command Chaining only requires two pages for transmit and two for
receive (in this case, two 256 byte pages for transmit and two 512 byte pages for receive, leaving 512
bytes free). Please note that it is the responsibility of software to reserve 512 bytes for each receive page if
the device is conf igured to handle lon g packet s. The COM20022I does n ot check pa ge bound aries durin g
reception. If the device is configured to handle only short packets, then both transmit and receive pages
may be allocated as 256 bytes long, freeing at least 1KByte at any given time.
Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because
Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four
256 byte pages, leaving 1K free).
The general rule whic h may be applied to det ermine where in RAM a page begins is as follows:
Address = (nn x 512) + (f x 256).
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SID
DID
COUNT = 256-N
NO T U SED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
NO T US ED
SID
DID
0
COUNT = 512-N
NOT USED
D ATA BYTE 1
D ATA BYTE 2
DATA BYTE N-1
DATA BYTE N
SHORT PACKET
FORMAT LONG PACKET
FORMAT
A
DDRESS ADDRESS
0
1
2
COUNT
255
511
N = DATA PACKET LENGTH
SID = SOURCE ID
DID = DESTINATION ID
(DI D = 0 FO R BROADCASTS)
0
1
2
COUNT
511
3
Figure 6.3 - RAM Buffer Packet Configuratio n
6.6.2 Transmit Sequence
During a transmit seque nce, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and
writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long
packets are enabl ed, the COM20022I interprets the packet as either a long or short pack et, depending on
whether the buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in
Figure 5.7 Address 0 contains the Source Identifier (SID); Address 1 contains the Destination Identifier
(DID); Address 2 (COUNT) contains, for short packets, the value 256-N, where N represents the number
of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long
packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the
number of inform ation bytes in t he message. T he SID in Address 0 is used by the rec eiving node t o reply
to the transmitting n ode. The COM20022I pu ts the local ID in this locat ion, therefore it is not necessary to
write into this locati on. Please note that a short packet may co ntain between 1 and 253 data bytes, while a
long packet may contain between 257 and 508 data bytes. A minimum value of 257 exists on a long
packet so that the COUNT is expressible in eight bits. This leaves three exception packet lengths which
do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of these
lengths must be sent, t he user must add dummy bytes to t he packet in order to make the packet fit into a
long packet.
Once the pac ket is writt en i nto the buf fer, the micro cont roll er a waits a log ic "1" on t he T A bit , indi cati ng th at a
previous transmit command has concluded and another may be issued. Each time the message is loaded
and a transmit command issued, it will take a variable amount of time before the message is transmitted,
depending on the traffic on the network and the location of the token at the time the transmit command was
issued. T he conclu sion of t he T ransmit C ommand will gene rate an i nterru pt if t he Interr upt Mask allo ws it. I f
the device is conf igu red for th e C ommand Chaining opera tion, please see the Command Chaining se ction for
further detail on the transmit sequence. Once the TA bit becomes a logic "1", t he microcontroller may issue
the "Enable Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the
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message is not a BROADCAST, the COM20022I automatically sends a FREE BUFFER ENQUIRY to the
destination node in order to send the message. At this point, one of four possibilities may occur.
The first possibility is if a free buffer is available at the destination node, in which case it responds with an
ACKnowledgement. At this point, the COM2002 2 I fetche s the da ta from the Tran smi t Buffer and performs the
transmit sequence. If a successful transmit sequence is completed, the TMA bit and the TA bit are set to
logic "1". If the packet was not transmitted successfully, TMA will not be set. A successful transmission
occurs when the receiving node responds to the packet with an ACK. An unsuccessful transmission occurs
when the receivin g node doe s not re sp ond to the pa cke t.
The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative
AcKnowledgement. A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the
token is passed on from the transmitting node to the next node. The next time the transmitter receives the
token, it will again transmit a FREE BUFFER ENQUIRY. If a NAK is again received, the token is again
passed onto the next node. The Excessive NAK bit of the Diagnostic Status Register is used to prevent an
endless sending of FBE's and NAK's. If no limit of FBE-NAK sequences existed, the transmitting node would
continue issuing a Free Buffer Enquiry , even though it would continuously recei ve a NAK as a respon se . The
EXCNAK bit generates an interrup t (if enabled) in order to tell the mi crocontroll er to disab le the tran smitter via
the "Disable Transmitter" command. This causes the transmission to be abandoned and the TA bit to be set
to a logic "1 " when the node ne xt rec eives t he to ken, whil e th e TMA bit rem ains at a l ogic " 0". Pl eas e refer to
the Improved Diagnostics section for further detail on the EXCNAK bit.
The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node
does not respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0".
The user should determine whether the node should try to reissue the transmit command.
The fourth possibility is if a non-traditional response is received (some pattern other than ACK or NAK, such
as noise). In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the
next node to time out, thus genera ting a network recon figura tion .
The "Disable Transmitter" command may be used to cancel any pending transmit command when the
COM20022I next receives the token. Normally, in an active network, this command will set the TA status bit
to a logic "1" when the t oken is rece ived. If th e "Disabl e Transmitt er" comman d does not ca use the TA bit to
be set in the time it takes the token to make a round trip through the network, one of three situations exists.
Either the node is disconnected from the network, or there are no other nodes on the network, or the external
receive circuitry has failed. These situations can be determined by either using the improved diagnostic
features of the COM20022I or using another software timeout which is greater than the worst case time for a
round trip token pass, which occurs w hen all nod es transmi t a maximu m length me ssage.
6.6.3 Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous
receptio n has co ncluded. T he microco ntroll er will be i nterrupted if the corresponding bit in the Interrupt Mask
Register is set to logic "1". Otherwise, the microcontroller must periodically check the Status Register. Once
the microcontroller is alerted to the fact that the previous reception has concluded, it may issue the "Enable
Receive to Page fnn" command, which resets the RI bit to logic "0" and selects a new page in the RAM
buffer. Ag ain, the appropr iate buffer size is specified in t he "Define Conf iguration" co mmand. Typic ally, the
page which just received the data packet will be read by the microcontroller at this point. Once the "Enable
Receive to Page fnn" co mmand is issue d, the microcon troller attend s to other dutie s.
There is no way of kno wing how lon g the new rece ption wil l take, si nce anot her node may t ransmit a packet
at any time. When another node does transmit a packet to this node, and if the "Define Configuration"
command has enabled the reception of long packets, the COM20022I interprets the packet as either a long
or short packet, depending on whether the content of the buffer location 2 is zero or non-zero. The format of
the buffer is shown in Figure 5.7. Address 0 contains the Source Identifier (SID), Address 1 contains the
Destinat ion Identifi er (DID), and A ddress 2 cont ains, for short packets, the v alue 256-N, where N repr esents
the message length, or for long packets, the value 0, indicating that it is indeed a long packet. In the latter
case, Addr ess 3 cont ains th e value 512- N, wher e N repres ents the message l ength. Not e that on rec eptio n,
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the COM20022I deposits packets into the RAM buffer in the same format that the transmitting node arranges
them, which allows for a message to be received and then retransmitted without rearranging any bytes in the
RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected
buffer, the COM20022I sets the RI bit to logic "1" to signal the microcontroller that the reception is complete.
Figure 6.4 - Command Chaining Status Register Queue
6.7 Command Chaining
The Command Ch aining operation allo ws consecutive transmissions and receptions to occur without h ost
microcontroller intervention.
Through the us e of a dua l t wo-level FI FO, commands to be transmit ted an d received, as well as the stat us
bits, are pipelined.
In order for the COM20022I to be compatible with previous SMSC ARCNET device drivers, the device
defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the
Command Chaining Mode must be enabled via a logic "1 " on bit 6 of the Configuration Register.
In Command Chaining, the Status Register a ppears as in Figure 6.4.
The following is a list of Command C haining guidelines for the software pr ogrammer. F urther detail can be
found in the Transmit Command Chainin g and Receive Command Chaining sections.
The device is designed such that the interrupt se rvice routine latency does not affect performance.
Up to two outstanding tra nsmissions and two outstanding receptions can be pending at any given
time. The commands may b e given in any order.
Up to two outstanding transmit interrupts and two outstanding receiv e interrupts are stored by the
device, along wit h t heir respective status bit s .
The Interrupt Mask bits act on TTA (Rising Transition on Transmitt er Available) for transmit operations
and TRI (Rising Transition of Receiver Inhibited) for receive operat ions. TTA is set upon completion
of a packet transmission only. TRI is set upon completion of a packet reception only. Typically there is
no need to mask the TT A and TRI bits after clearing the interrupt.
The traditional TA and RI bits are still available to reflect the present status of the device.
6.7.1 Transmit Command Chaining
When the processor issues the f irst "Enable T ransmit t o Page fnn" command, the COM20 022I respon ds in
the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified
page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really
meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for the
device in the Command Chaining mode. In the Command Chaining Mode, at any time after the first
command is issued, the processor can issue a second "Enable Transmit from Page fnn" command. The
COM20022I stores the fact that the second transmit command was issued, along with the page number .
TRI RI TA POR TEST RECON
TMA TTA
TMA TTA
TRI
MSB LSB
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After the first transmission is completed, the COM20022I updates the Status Register by setting the TTA
bit, which generates an interrupt. The interrupt service routine should read the Status Register. At this
point, the TT A bit will be found t o be a logic "1" and t he TMA (Transmit Message Acknowledge) bit will tell
the processor whether the transmission was successful. After reading the Status Register, the "Clear
Transmit Interrupt" command is issued, thus resetting the TTA bit and clearing the interrupt. Note that only
the "Clear Transmit Interrupt" command will clear the TTA bit and the interrupt. It is not necessary,
however, to clear the bit or the int errupt right away because the status of the transmit operation is double
buffered in order to retain the results of the first transmission for analysis by the processor. This
information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note
that the interrupt will remain active until the command is issued, and the second interrupt will not occur
until the first interrupt is acknowledged. The COM20022I guarantees a minimum of 200nS (at EF=1)
interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether
the appropriate transmission was a success. The TMA bit should only be considered valid after the
corresponding TTA bit has been set to a logic "1". The TMA bit never causes an interrupt.
When the token is received again, the second transmission will be automatically initiated after the first is
completed by using the stored "Enable Transmit from Page fnn" command. The operation is as if a new
"Enable Transmit from Page fnn" command has just been issued. After the first Transmit status bits are
cleared, the Status Register will again be updated with the results of the second transmission and a
second interrupt resulting from the second transmission will occur. The COM20022I guarantees a
minimum of 200ns (at EF= 1) int errupt inactive time interval before the following edge.
The Transmitter Available (T A) bit of the I nterrupt Mask Register no w masks only the TT A bit of the Stat us
Register, not the T A bit as in the non-c haining mode. Sinc e the TTA bit is only set upon t ransmission of a
packet (not by RESET), and since the TTA bit ma y easily be reset by issuing a "Clear Transmit Interrupt"
command, there is no need to use the TA bit of the Interrupt Mask Register to mask interrupts generated
by the TTA bit of the Status Register.
In Command Chai ning mo de, t he "Disab le T r ansmitter" c om m and will ca nc el the oldest tr ansmissi on. T his
permits canceling a pack et destined for a node not ready to receive. If both packets should be canceled,
two "Disable Transmitter" commands should be issued.
6.7.2 Receive Command Chaining
Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable
Receive from Page fnn" commands.
After the first packet is rece iv ed into t he f irst specifi ed page , t he T RI bit of t he Stat us Re g ister will be set to
logic "1", causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the
interrupt service routi ne will read th e Status Register. At thi s point, the RI bit will be foun d to be a logic "1" .
After reading the Status Re gister, the "Clear Receiv e Interrupt" command should b e issued, thus resetting
the TRI bit and cleari ng the interrupt. Note that onl y the "Clear Receive Int errupt" command will clear the
TRI bit and the int errupt. It is not necessary, ho wever, to clear the bit or the interrupt right away becaus e
the status of the rece ive operation is double buffered in order to retain the results of the first recepti on for
analysis by the processor, therefore the information will remain in the Status Register until the "Clear
Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive
Interrupt" command is issued, and the second interrupt will be stored until the first interrupt is
acknowledged. A minimum of 200nS (at EF=1) interrupt inactive time interval between interrupts is
guaranteed.
The second reception will occur as soon as a second packet is sent to the node, as long as the second
"Enable Receive to Page fnn" command was issued. The operation is as if a new "Enable Receive to
Page fnn" command has just been issued. After the first Receive status bits are cleared, the Status
Register will again be updated with the results of the second reception and a second interrupt resulting
from the second reception will occur.
In the COM20022I, the Receive Inhibit (RI) bit of the Interrupt Mask Register no w masks only the TRI bit of
the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon
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reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a "Clear
Receive Interrupt" command, there is no need to use the RI bit of the Interrupt Mask Register to mask
interrupts generated by the TRI bit of the Status Register. In Command Chaining mode, the "Disable
Receiver" command will cancel the oldest reception, unless the reception has already begun. If both
receptions should be canceled, two "Disable Receiver" commands should be issued.
6.8 Reset Details
6.8.1 Internal Reset Logic
The COM20022I includ es special reset circuitry to guar antee smooth operation during r eset. Special care
is taken to assure proper operation in a variety of systems and modes of operation. The COM20022I
contains digital filter circuitry and a Schmitt Trigger on the nRESET signal to reject glitches in order to
ensure fault-free operation.
The COM20022I supports two reset options; software and hardware res et. A software reset is generated
when a logic "1" is written to bit 7 of the Configuration Register. The device remains in reset as long as
this bit is set. The software reset does not affect the microcontroller interface modes determined after
hardware reset, nor does it affect the contents of the Address Pointer Registers, the Configuration
Register, or the Setup1 Register. A hardware reset occurs when a low signal is asserted on the nRESET
input. The mini mum reset pulse width is 5TXTL. This pulse width is used b y the internal d igital filter, which
filters short glitches to allow only valid resets to occur.
Upon reset, the tr ansmitter portion of the device is disab led and the i nternal regist ers assume thos e states
outlined in the Internal Registers section. After the nRESET signal is removed the user may write to the
internal registers. Since writing a no n-zero value to t he Node ID Regist er wakes up the COM20022I core,
the Setup1 Register sho uld be written before the No de ID Register. Once the Node I D Register is written
to, the COM20022I r eads the value and executes t wo write c ycles to the RAM buff er. Address 0 is writte n
with the data D1H and addres s 1 is written with the Node ID. The dat a patt ern D1H was c hosen ar bitraril y,
and is meant to provide ass urance of proper microsequencer operatio n.
6.9 Initialization Sequence
6.9.1 Bus Determination
Writing to and reading from an odd address location from the COM20022I's address space causes the
COM20022I to determi ne the appropri ate bus interf ace. When t he COM20022I is po wered on the int ernal
registers may be written to. Since writin g a non-z ero valu e to the No de I D Register wakes up the c ore, the
Setup1 Register should be written to bef ore the Node ID Register. Until a non-zer o value is placed into the
NID Register, no microcode is executed, no tokens are passed by this node, and no reconfigurations are
generated by t his node. Once a non-z ero value is placed in the register, t he core wakes up, but the node
will not attempt to join the network until t he TX Enable bit of the Conf iguration Re gister is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first
observe the Receive Activit y and the T oken Seen bits of the Diag nostic Stat us Register t o verify the he alth
of the receiver and the network.
Next, the uniq ueness of the Node ID value plac ed in the Node ID Register is det ermined. The TX Enabl e
bit should sti ll be a logic "0" until it is ensure d that the No de ID is unique. If this node ID already exists, the
Duplicate ID bit of the Diagnostic Status Register is set after a maximum of 210mS (or 420mS if the ET1
and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the
COM20022I compares the value in the Node ID Register with the DID's of the token, and determines
whether there is a response to it. Onc e the Diagnostic St atus Register is read, the DUPID bit is cleared.
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The user may then attempt a new ID value, wait 210mS before checking the Duplic ate ID bit, and repeat
the process until a uni que Node ID is found. At this point, the T X Enable bit may be set to allo w the node
to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the
MYRECON bit of the Diagnost ic Status Register.
The Tentative ID Regist er may be used to b uild a net work map of all the nodes on t he network, even o nce
the COM20022I has joined the network. Once a value is placed in the Tentative ID Register, the
COM20022I looks for a response to a t oken whose DID matches the T entative ID Register. The soft ware
can record this information and continue placing Tentative ID values into the register to continue building
the network map. A complete network map is only valid until nodes are added to or deleted from the
network. Note t hat a node can not detect the existence of t he next lo gical node on the network when using
the Tentative ID. To determine the next logical node, the s oftware should read the Next ID Regist er.
6.10 Improved Diagnostics
The COM20022I allows the user to better manage the operation of the network through the use of the
internal Diagnost ic Status Register.
A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this
node expired, causi ng a reconfigur ation b y this node. After t he Reconfigu ration (RECON ) bit of the Stat us
Register interrupts t he microcontroller, the interrupt servic e routine will typically read the MYRECON bit of
the Diagnostic Status Register. Reading the Diagnostic Status Register resets the MYRECON bit.
Successive occurrences of a logic "1" on the MYRECON bit ind icates that a probl em exist s with this n ode.
At that point, the transmitter s hould be disabl ed so that the entire net work is not held do wn while the node
is being evalua ted.
The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with
the same ID does not exist on the network. Once it is determined that the ID in the Node ID Register is
unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic
transmit function. This allows the node t o join the network.
The Receive Activity (RCVACT) bit of the Diagnostic Status Register will be set to a logic "1" whenever
activity (logic "1") is detected on the RXIN pin.
The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network
(except those t okens transmitted b y this node).
The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual
events are occurring on th e net work, the use r may fin d it val uable t o us e the T XEN bit of the Confi gurat ion
Register to qualify events. Different combinations of the RCVACT, TOKEN, and TXEN bits, as shown
indicate different situations:
6.10.1 Normal Results:
RCVACT=1, TOKEN=1, TXEN=0: The nod e is not part of the network. The n etwork is operati ng properl y
without this node.
RCVACT=1, TOKEN=1, TXEN=1: The node sees rece ive activity and sees the t oken. The basic transmit
function is enabled. Network and node are operat ing properl y.
MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node network.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
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DATASHEET
6.10.2 Abnormal Results:
RCVACT=1, TOKEN=0, T XEN=X: The node se es receive activity, but d oes not see the token. Eit her no
other nodes exist on the net work, some type of data corruption exists, the media driver is malfunctioning,
the topology is set up incorrectl y, there is noise on the network, or a reconfigurat ion is occurring.
RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled.
The transmitter and/ or receiver are not functioning properl y.
RCVACT=0, TOKEN=0, TXEN=0: No receive activity and basic transmit function disabled. This node is
not connected to the network.
The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in
software. This f unction is necessary to limit the number of ti mes a sender issues a FBE to a node with no
available buffer. When the destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs,
the EXCNAK bit of the sender is set, ge nerating an interrupt . At this point the soft ware may abandon t he
transmission via the "D isable Transmitter" command. This sets t he TA bit to logic "1" when the node next
receives the token, to allow a different transmission to occur. T he timeout value for the EXNACK bit (128
or 4) is determined by the FOUR-NAKS bit on the Setup1 Register.
The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the
wraparound counter of t he EXCNAK bit. When the EXCNAK bit goes h igh, indicating 128 or 4 NAKs, the
"POR Clear Flags" command may be issued to reset the bit so that it will go high again after another
count of 128 or 4. The software may c ount the number of ti mes the EXCNAK bit goes hi gh, and once the
final count is reached, the "Disable Tr ansmitter" command may be issued.
The New Next ID bit permits the software to detect the withdrawal or addition of no des to the network.
The Tentative I D bit allows the user to build a network map of those node s existing on the network. This
feature is useful because it minimizes the need for human intervention. When a value placed in the
Tentative ID Register matches the Node ID of another node on the net work, the TENTID bit is set, telling
the software that this NODE ID already exists on the network. The software should periodically place
values in the Tentative I D Register and monitor the New Next ID bit to maint ain an updated network map.
6.11 Oscillator
The COM20022I contains circuitry which, in conjunction with an external parallel resonant crystal or TTL
clock, forms an oscillator.
If an external crystal is used, two capac itors are needed (one from each leg of the cryst al to ground). No
external resist or is required, since t he COM20022I contai ns an internal re sistor. The crystal must have an
accuracy of 0.020% or bet ter. The oscillation f requency range is from 10 MHz to 20 MHz.
The crystal must have an acc urac y of 0. 010 % or bet ter when the internal clock mult ipl ier is turne d o n. T he
oscillation frequency must be 20MHz when the internal clock multiplier is turned on.
The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock
for other devices.
The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a
390Ω pull-up resistor is required on XT AL1, while XTAL2 should be left unconnected.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 56 SMSC COM20022I
DATASHEET
Chapter 7 Operational Description
7.1 Maximum Guaranteed Ratings*
Operating Temperature Range...............................................................................................-40oC to +85oC
Storage Temperature Range ................................................................................................-55oC to +150oC
Lead Temperature (soldering, 10 seconds) .......................................................................................+325 oC
Positive Voltage on any pin, with respect to ground ........................................................................VDD+0.3V
Negative Voltage on any pin, with respect to ground............................................................................. -0.3V
Maximum VDD .......................................................................................................................................... +7V
*Stresses above those listed may cause p ermanent damage to the dev ice. This is a stress rating only and
functional oper ation of the device at these or any oth er condition ab ove those indicated in the operatio nal
sections of this specificat ion is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes or "glitches" on their outputs when the AC power is switched on or off. In addition, voltage
transients on t he AC po wer line may app ear on the DC output. I f this possibil ity exists it is suggested t hat
a clamp circuit be used.
7.2 DC Electrical Characteristics
VDD=5.0V±10%
COM20022I: TA=0oC to +70oC, COM20022II: TA=-40oC to +85oC
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Input Voltage 1
(All inputs except A2,
XTAL1, nRESET, nRD,
nWR, nREFEX and RXIN)
High Input Voltage 1
(All inputs except A2,
XTAL1, nRESET, nRD,
nWR, nREFEX and RXIN)
VIL1
VIH1
2.0
0.8 V
V
TTL Levels
TTL Levels
Low Input Voltage 2
(XTAL1)
High Input Voltage 2
(XTAL1)
VIL2
VIH2
4.0
1.0 V
V
TTL Clock Input
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 57 Revision 09-27-07
DATASHEET
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low to High Threshold
Input Voltage
(A2, nRESET, nRD, nWR,
nREFEX and RXIN)
High to Low Threshold
Input Voltage
(A2, nRESET, nRD, nWR,
nREFEX and RXIN)
VILH
VIHL
1.8
1.2
V
V
Schmitt Trigger,
All Values at VDD =
5V
Low Output Voltage 1
(nPULSE1 in Push/Pull
Mode, nPULSE2,
nTXEN, DREQ, nIOCS16)
High Output Voltage 1
(nPULSE1 in Push/Pull
Mode, nPULSE2,
nTXEN, DREQ, nIOCS16)
VOL1
VOH1
VOH1C
2.4
0.8 x VDD
0.4
V
V
ISINK=4mA
ISOURCE=-2mA
ISOURCE=-200µA
(except DREQ,
nIOCS16)
Low Output Voltage 2
(D0-D15)
High Output Voltage 2
(D0-D15)
VOL2
VOH2
2.4
0.4 V
V
ISINK=16mA
ISOURCE=-12mA
Low Output Voltage 3
(nINTR)
High Output Voltage 3
(nINTR)
VOL3
VOH3
2.4
0.8 V
V
ISINK=24mA
ISOURCE=-10mA
Low Output Voltage 4
(nPULSE1 in Open-Drain
Mode)
VOL4 0.5 V ISINK=48mA
Open Drain Driver
Dynamic VDD Supply
Current IDD1
IDD2 45
65 mA
mA 5 Mbps
10 Mbps
All Outputs Open
Input Pull-up Current
(nPULSE1 in Open-Drain
Mode, A1, AD0-AD2,
D3-D15, nREFEX, (nDACK
and TC in BUSTMG = H))
Input Leakage Current
(All inputs except A1,
AD0-AD2, D3-D15,
XTAL1, XTAL2, nREFEX,
(nDACK and TC in BUSTMG =
H))
IP
IL
80 200
±10
μA
μA
VIN=0.0V
VSS < VIN < VDD
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 58 SMSC COM20022I
DATASHEET
CAPACITANCE (TA = 25C; fC = 1MHz; VDD = 0V)
Output and I/O pins capacitive load specified as follows:
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Input Capacitance CIN 5.0 pF
Output Capacitance 1
(All outputs except XTAL2,
nPULSE1 in Push/Pul l
Mode)
Output Capacitance 2
(nPULSE1, in BackPlane
Mode Only - Open
Drain)
COUT1
COUT2
45
400
pF
pF
Maximum Capacitive
Load which can be
supported by each
output.
0.4V
AC Measurements are taken at the following points:
Inputs:
2.4V
1.4V 50%
50%
0.4V
2.4V
1.4V
0.8V
Outputs:
2.0V
0.8V
2.0V
Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin.
Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".
t
t
t
t
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 59 Revision 09-27-07
DATASHEET
Chapter 8 Timing Diagrams
Figure 8.1 - Multiplexed Bus, 68XX-Like Con trol Signals; Read Cycle
AD0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D15
DIR t9 t10
nDS
t11
t12
t13 t14
Note 2
nIOCS16 Pre vious Value Invalid Valid Value
t15 t16
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
Address Setup to ALE Low
Address Hold from AL E Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
nDS High to Data High Impedance
Cycle Time (nDS Lo w to Next Time Low)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High W i dth
ALE Low Width
nDS Low Width
nDS High Widt h
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Dela y from ALE Low
20
10
10
10
15
0
4TARB*
10
10
20
20
60
20
0
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: BUST MG p in = HIGH and RBUSTMG bit = 0
40
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
The Microcontroller typically accesses the COM20022 on every other cycle.
The refo re, the cycle t ime specified in the microcontroller 's da tasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 60 SMSC COM20022I
DATASHEET
Figure 8.2 - Multiplexed Bus, 80XX-Like Con trol Signals; Read Cycle
ALE High Width
ALE Low Width
nRD L ow Wi dth
nRD High Width
nWR to nRD Low
nIOCS 1 6 Hold De l ay from ALE Low
nIOCS16 Output Delay from ALE Low
AD0-AD2, VALID
nCS
t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D15
nRD t9
t10
nWR t13 t11 t12
nIOCS16 Previous V alue Invalid Valid Value
t15
t14
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
nRD High to Data High Impedance
Cycle Time (nRD Low to Next Time Low)
20
10
10
10
15
0
4TARB*
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
M US T BE : B US TMG pin = HI GH and RBUS TMG bit = 0
20
20
60
20
20
040
The Microcontroller typically accesses the COM20022 on every other cycle.
The r efore, t h e cycle time sp ecifi e d in t h e microc o ntro l ler's d a t asheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 61 Revision 09-27-07
DATASHEET
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle
AD0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D15
DIR
t9 t10
Note 2
t8**
nDS
t11
t12
t13 t14
t16
nIOCS16 Previous Value Invalid Valid Value
t15
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
20
10
10
10
15
10
4TARB*
10
10
20
20
20
20
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
DIR Setup to nDS Active
DIR Hold from nDS Inactive
30
MUST BE: BUSTMG pin = HIGH
ALE High Width
ALE L ow Width
nDS Low Width
nDS High Widt h
nIOCS16 Hold D elay from ALE Low
nIOCS16 Output Delay from ALE Low
Cycle Time (nDS to Next )**
40
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
Any cycle occurri ng after a write to Addre ss Point er Low Register requires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Note 2:
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Write cycle for Address Po inter Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 62 SMSC COM20022I
DATASHEET
Figure 8.4 - Multiplexed Bus, 80XX-Like Con trol Signals; Write Cycle
A
D0-AD2, VALID
nCS t1
t3
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D15
Note 2
t8**
nWR
t9
t10
nRD t13 t11 t12 t8
nIOCS16 Previous Value Invalid Va lid Value
t14
Note 3 t15
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
20
10
10
10
15
10
4TARB*
20
20
20
20
20
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Va lid Data Setup to nDS High
Data Hold from nDS High 30
ALE High Width
ALE Low Wid th
nWR Low Width
nWR High Width
nRD to nWR Low
nIOCS16 Hold Delay from AL E Low
nIOCS16 Outpu t De lay from ALE Low
Cycle Time (nWR to Next )**
MUST BE: BUSTMG pin = HIGH
40
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
Any cycle occurring after a write to Address Poin ter Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Note 2:
**
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 63 Revision 09-27-07
DATASHEET
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D15
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
nIOCS16
t11
VALID VALUE
t12
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
15
10
5**
0
nS
nS
nS
nS
nS
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to n RD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low t o Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
4TARB*
0
60
20
20
40**
20
nS
nS
nS
nS
nS
nS
CASE 1: BU ST MG pin = HIG H and RBUST MG bit = 0
nRD Lo w W idt h
nRD High Width
nWR to nRD Low
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High 0**** 40***
The Microcontroller typically accesses the COM20022 on ev ery other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
TARB is the Arbitra tion Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLO W ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
nCS may become active after control be comes a ct ive, but the a cces s tim e ( t6 )
will now be 45nS measured from the leading edge of nCS.
**
t11 is measured from the latest active (valid) timing among nCS, A0-A2.
***
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
****
Note 2: Read cycle for Address Pointer Low/High Regist ers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD .
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 64 SMSC COM20022I
DATASHEET
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D15
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
nIOCS16
t11
VALID VALUE
t12
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
-5
0
-5
0
nS
nS
nS
nS
nS
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
4TARB*+30
0
100
30
20
60**
20
nS
nS
nS
nS
nS
nS
nRD Low Width
nRD High Width
nWR to nRD Low
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
CASE 2: BUS TM G pin = LO W or RBUST MG bit = 1
0**** 40***
The Microcontroller typically accesses the COM20022 on ev ery other cycle.
Therefo re, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
t6 is measured from the late st activ e (valid) ti ming among nCS, nRD, A0-A2.
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bit s
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trai ling edge of nRD to the
leading edg e of the ne xt nRD.
Notes 2 and 3 are applied t o an access to Data Register by DMA transfer.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trai ling edge of nWR to the
leading edge of nRD.
t11 is measured from the latest active (valid) timing amon g nCS, A0-A2.
***
t12 is measured from the earliest inactiv e (invalid) tim ing among nCS, A0-A2.
****
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 65 Revision 09-27-07
DATASHEET
A0-A2
VALID DATA
VALID
D0-D15
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
nIOCS16
t12
VALID VALUE
t13
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
15
10
5**
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Ti me (nDS L ow to Next Time Low)
DIR Hold from nDS Inactive 4TARB*
nS
nS
nS
nS
nS
nS
t8 nS
nDS Low to Valid Data 40**
t9
t10
t11
t12
t13
nS
nS
nS
nS
nS
nDS High to Data High Impedence
nDS Low Width
nDS High Width
nIOCS16 Output Dela y from nCS Low
nIOCS16 Hold Delay from nCS High
20
10
10
0
60
20
CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0
0**** 40***
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be d ouble d whe n consideri ng b ack-t o-ba ck COM 20022 cycl es.
Note 1:
nCS may become active after control becomes active, but the access time (t8) will
now be 45nS measured from the lead ing edge of nCS.
**
*** t12 is measured from the latest active (v al id) timing among nCS, A0-A2.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depen ds on CK UP1 and CK UP0 bits
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
****
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing e dg e o f nDS to
the leading edge of the ne xt nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 66 SMSC COM20022I
DATASHEET
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D15
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
nIOCS16
t12
VALID VALUE
t13
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
-5
0
-5
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Activ e
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Ina ctive 4TARB*+30
nS
nS
nS
nS
nS
nS
t8 nSnDS Low to Valid Data 60**
t9
t10
t11
t12
t13
nS
nS
nS
nS
nS
nDS High to Data High Impedence
nDS Low Width
nDS High Width
nIOCS16 Output Delay from nCS Lo w
nIOCS16 Hold Delay from nCS High
20
10
10
0
100
30
CAS E 2 : B USTM G pin = LO W or RBUSTM G bit = 1
0**** 40***
The Microcont rolle r typically ac cesses the COM20022 on every other cycle.
Theref ore , the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
** t8 is measured from the latest active (va l id) timing among nCS, nDS, A0-A2.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
*** t12 is measured from the latest active (valid) timing among nCS, A0-A2.
t13 is measured from the earliest inactive (invalid) timing amo ng nCS, A0-A2.
****
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 67 Revision 09-27-07
DATASHEET
Figure 8.9 - Non-Multiplexed Bus, 80XX-L i ke Control Signals; Write Cycle
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD to n WR Lo w
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
A0-A2
VALID DATA
VALID
D0-D15
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
Note 3
t5**
nIOCS16 VALID VALUE
t11 t12
t1
t3
t5
t6
t7
t8
t9
t10
t11
t12
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR High
min
15
5
10
20
20
20
max
4TARB*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold fro m nWR Inactive 10 nS
CASE 1: BUSTMG pin = HIGH
Cycle Time (nWR to Next )**
0***** 40****
***: nCS may become activ e after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20022 on e very other cycle.
Ther efore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimu m o f 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitr at ion Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
t12 is measured from th e earliest inactive (invalid) timing among n CS, A0-A2.
*****
Write cycle for Address Pointer Low Register occurring after a w rite to Data
Register requires a minim um of 5T ARB from the trai lin g edge o f nWR to the
leading edge of the next nWR.
Notes 2 and 3 are applied to an a ccess to Data Register by DMA transfer.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
**
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 68 SMSC COM20022I
DATASHEET
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
A0-A2
VALID DATA
VALID
D0-D15
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
nIOCS16 VALID VALUE
t11 t12
t5**
Note 3
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Note 2:
**
Write cycle for Add re ss Poi n te r Low Register occurring a f te r a write to Da ta
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Note 3: Write cycle for Address Pointer Low Regist er occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLO W ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
**** t11 is measured from th e la t est active (valid ) tim i n g a m o ng nCS, A0- A2.
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
*****
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD to nWR Low
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
t1
t3
t5
t6
t7
t8
t9
t10
t11
t12
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup t o n WR Hig h
min
0
0
10
65
30
20
max
4TARB*
30
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold from nWR Inactive 0 nS
Cycle Time (nWR to Next )
CASE 2: BUSTMG pin = LOW
0***** 40****
**
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 69 Revision 09-27-07
DATASHEET
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
A0-A2
VALID DATA
VALID
D0-D15
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
nIOCS16 VALID VALUE
t12 t13
t6**
Parameter min max units
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS to Next T i me )**
DIR Hold from nDS Inactive
Valid Data Set up to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
nIOCS16 Output De lay from nCS Low
nIOCS16 Hol d Delay from nCS High
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
15
10
5
0
10
4TARB*
10
30***
10
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
CASE 1: BUSTMG pin = HIGH
0***** 40****
The Microcontroller typically accesses the COM20022 on e v ery other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
**Note 2: Any cycle occurring after a write t o the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to th e leading edge
of the next nDS.
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
****: t12 is measured from the latest active (valid) timing among nCS, A0-A2.
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
*****:
Write cycle fo r Addres s Pointer Low Re g isters occurring a fter an a cce ss to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading ed ge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 70 SMSC COM20022I
DATASHEET
A0-A2
VALID DAT A
VALID
D0-D15
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
nIOCS16 VALID VALUE
t12 t13
t6**
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
0
0
0
0
10
4TARB*
10
30
10
65
30
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
CASE 2: BUSTMG pin = LOW
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS to Next )**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold fro m nDS High
nDS Low Width
nDS High Width
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay fr om nCS Hi gh 0***** 40****
The M i cr ocontroller typically accesses the COM20022 on eve ry other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to th e leading edge
of the next nDS.
TARB is the Arbitration Clock Period
TARB is iden tical to Topr if S LOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
**** t12 is measured from the latest active (valid) timing among nCS , A0-A2.
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
*****
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 71 Revision 09-27-07
DATASHEET
Figure 8.13 - Normal Mode Transmit or Receive Timing
(These signals are to and from the h ybrid)
nPULSE2
t1
t3
t7
t8
Parameter
nPULSE1, nPULSE2 Pulse Width
nPULSE1, nPULSE2 Overlap
RXIN P eriod
RXIN Inactive Pulse Width
min
100
-10
max units
nS
nS
nPULSE1
t1
t6 RXIN Active Pulse Width
t2
t2 nPULSE1, nPULSE2 Period nS
t1
t3
400
0+10
typ
RXIN
t6
t7
10 400
nTXEN
nS
nS
t2
t4 t5
LAST BIT
(400 nS BIT TIME)
t4 nTXEN Low to nPULSE1 Low 850 950 nS
t5 Beginning of Last Bit Time to nTXEN High 250 350 nS
100
t8
20 nS
Note: Use Only 2.5 Mbps
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 72 SMSC COM20022I
DATASHEET
nPULSE1 t2 t3
RXIN t10
t11
nPULSE2 t5 t6
(Internal Clk)
t4
Parameter min typ max units
t2
t3
t4
t5
t6
t7
t8
t10
t11
t12
nPULSE1 Pulse Width
nPULSE1 Period
nPULSE2 Low to nPUL SE1 Low
nPULSE2 High Time
nPULSE2 Low Time
nPULSE2 Period
nPULSE2 High to nTXEN High
RXIN Active Pulse Width
RXIN Period
nS
nS
nS
nS
nS
nS
nS
nS
nS
200*
400*
100*
100*
200*
200*
400*
50
50
-25
10
t1
t7
nTXEN
t9 t8
LAST BIT
(400 nS BIT TIME)
t1 nPULSE2 High to nTXEN Low -25 50 nS
(First Rising Edge on nPUL SE 2 af te r La st Bit Time )
t9 nTXEN Low to first nPULSE1 Low** 650 750 nS
t13
t12
-25
RXIN Inactive Pulse Width 20 nS
t13 Beginning Last Bit Time to nTXEN High** 450 nS
Abov e v a lues are for 2.5 Mbps.
Other Dat a Rates are sh own b el ow.
550
TDR is the Data Rate Period
*t5, t6 = TDR/4
*t2, t7, t10 = TDR/2
*t3, t11 = TDR
**t9 = x TDR +/- 50 nS
7
4
**t13 = x TDR +/- 50 nS
5
4
Figure 8.14 - Backplane Mode Transmit or Recei ve Timing
(These signals are to and from the differential driver or the cable)
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 73 Revision 09-27-07
DATASHEET
t1
t3
Parameter
Input Clock High Time
Input Clock Period*
min
20
50
max units
nS
nS
XTAL1
t1
t4 Input Clock Frequency* 100
t2 Input Clock Low Time nS
t3
20
typ
10
t2
20 MHz
t5 Frequency Accuracy* -200 200 ppm
Note*: Input clock frequency must be 20 MHz ( 100ppm or better) to use the internal Clock Multiplier .
+
-
t4and t5are applie d to cry stal oscillaton.
4.0V 1.0V 50% of VDD
Figure 8.15 - TTL Input Timing on XTAL1 Pin
t1
Parameter
nRESET Pulse Width***
min max units
nRESET
t1
t2 nINTR High t o Next nINTR Lo w
typ
t2
nINTR
5TXTL*
EF = 0
EF = 1 TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note **: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
Figure 8.16 - Reset and Interrupt Timing
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 74 SMSC COM20022I
DATASHEET
VALID VALID
nCS
nREFEX
DREQ
nDACK
TC
nWR
nRD
DATA
(D15-D0)
t10
t19
t3
t2 t21
t24
t6
t20 t19 t20
t3
t7*
t25
t24
t25
t5
t4
t15
t16
t11
t12
t8 t9
t14 t13
t17 t18
Write LO W-POINTER
when DMAEN=1
Note*: t7 is measured from the latest active timing among TC, Write/Read.
t26
t1
Figure 8.17 - DMA Timing (Intel Mode 80XX)
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 75 Revision 09-27-07
DATASHEET
Note*: t7 is measured from the latest active timing among TC, Write/Read.
VALID VALID
nCS
nREFEX
DREQ
nDACK
TC
DIR
nDS
DATA
(D15-D0)
t10
t19
t3
t2 t21
t24
t6
t20 t19 t20
t3
t7*
t25
t24
t25
t5
t4
t15
t16
t11
t12
t8 t9
t14 t13
t17 t18
Write LOW-POINTER
when DMAEN=1
t22 t23 t22 t23
VALID VALID
t26
t1
Figure 8.18 - DMA Timing (Motorola Mode 68XX)
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 76 SMSC COM20022I
DATASHEET
Table 8.1 - DM A Timing
PARAMETER MIN TYP MAX
UNIT NOTE
t1 nDACK Inactive Pulse Width 30 ns
t2 The First DREQ Assertion Delay After Writin g Low
Pointer 4 Tarb 5
Tarb 5Tarb
+40ns Note 1
t3 DREQ Assert Delay from nREFEX Active at
Programmable Burst Tr ansfer Mode 0 40 ns Note 3
t4 DREQ Assertion Delay from Write/ Read Inactive at Non-
Burst Transfer Mode 0 40 ns Note 4
t5 GTTM
bit =0 7Txtl 8Txtl
+40ns Note 2
DREQ Assertion Delay from nDACK
Inactive due to T imeout of Gate Timer
at Programmable Burst Transf er Mode GTTM bit=1 15Txtl 16Txtl
+40ns
t6 DREQ Negation Delay from Write/Read Active 0 40 ns Note 4
t7 DREQ Negation Delay from TC and Write/Read Act ive 0 40 ns Note 4
t8 Data Access Time from Read Act ive 40 ns Not e 4
t9 Data Float Delay from Read Inactive 0 20 ns Note 4
t10 nREFEX Active Pulse W idth 20 ns
t11 Write Active Pulse Width CASE 1W 20 ns Note
4,5
CASE 2W 65 ns
t12 Read Active Pulse Width CASE 1R 60 ns Note
4,5
CASE 2R 100 ns
t13 Active Pulse Overlap Width between TC and Write/Read 20 ns Note 4
CASE1w/1R 20 ns t14 Write/Read I nactive Pulse Width CASE2w/2R 30 ns Note
4,5
t15 Write Cycle Int erval Period 4Tarb Note
1,4
CASE1R 4Tarb t16 Read Cycle Int erval Period CASE2R 4Tarb+3
0nS Note
1,4,5
t17 Data Setup to Write Inactive 30 ns Note 4
t18 Data Hold From Write Inactive 10 ns Note 4
t19 nCS High Setup to nDACK Active 20 ns
t20 nCS High Hold f r om nDACK Inactive 20 ns
t21 DREQ Active Setup to nDAC K Active 20 ns
t22 DIR Setup to nDS Low (Motorola mode only) 10 ns
t23 DIR Hold from nDS High (Motorola mode only) 10 ns
t24 nDACK Setup to Wr ite/Read Active 30 ns Note 4
t25 nDACK Hold Aft er Write/Read Inactive 5 ns Note 4
t26 nREFEX Inactive Time 3Txtl Note 2
Notes:
1. Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit.
SLOWARB must set to “1” if the data rate is over 5 Mbps. (i.e. 10 Mbps)
Tarb is Topr at SLOWARB=0 and T arb is 2Topr at SLOWARB=1.
Topr is the period of Operation Clock Frequency. It depends on the CKUP1 and CKUP0 bits.
2. Txtl is a period of external XTAL oscillation f requency.
3. The nREFEX pin must not be Low while nDACK is Low.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 77 Revision 09-27-07
DATASHEET
4. “Write” means write signal and “Read” means read signal. “Write/Read” means write or read si gnal.
At INTEL MODE, write signal i s nWR and read signal is nRD.
At MOTOROLA MODE, write signal is nDS when DIR is Low and the read signal is nDS when DIR is High.
5. Conditions of CASE1W, CASE2W, CASE1R and CASE2R are sho wn below;
CASE1W : BUSTMG pin = High
CASE2W : BUSTMG pin = Low
CASE1R : BUSTMG pin = High and RBUSTMG bit = 0
CASE2R : BUSTMG pin = Low or RBUSTMG bit = 1
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Revision 09-27-07 Page 78 SMSC COM20022I
DATASHEET
Chapter 9 Package Outline
Figure 9.1 - COM20022I 48 Pin TQFP Package Outline
Table 9.1 - COM20022I 48 Pin TQFP Package Parameters
MIN NOMINAL MAX REMARK
A ~ ~ 1.6 Overall Package Height
A1 0.05 0.10 0.15 Standoff
A2 1.35 1.40 1.45 Body Thickness
D 8.80 9.00 9.20 X Sp an
D/2 4.40 4.50 4.60 1/2 X Span Measure from Centerline
D1 6.90 7.00 7.10 X body Size
E 8.80 9.00 9.10 Y Span
E/2 4.40 4.50 4.60 1/2 Y Span Measure from Centerline
E1 6.90 7.00 7.10 Y body Size
H 0.09 ~ 0.20 Lead Frame Thickness
L 0.45 0.60 0.75 Lead Foot Length from Centerline
L1 ~ 1.00 ~ Lead Length
e 0.50 Basic Lead Pitch
θ 0o ~ 7o Lead Foot Angle
W 0.17 ~ 0.27 Lead Width
R1 0.08 ~ ~ Lead Shoulder Radius
R2 0.08 ~ 0.20 Lead Foot Radius
ccc ~ ~ 0.0762 Coplanarity (Assemblers)
ccc ~ ~ 0.08 Coplanarity (Test House)
Notes:
1. Controlling Unit: millimeter
2. Tolerance on the position of the leads is ± 0.04 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm.
4. Dimension for f oot length L measur ed at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm.
5. Details of pin 1 ident ifier are optional but must be located within the zone indicated.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I Page 79 Revision 09-27-07
DATASHEET
Chapter 10 Appendix A
This appendix describes the function of the NOSYNC and EF bits.
10.1 NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by
enabling or disabling the SYNC command during initialization. It is defined as follows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line
has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not
have to be idle for the RAM ini tialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes the Node ID, the COM20022I will write "D1"h data to Address
000h and Node-ID to Address 001h of its internal RAM within 3uS. These values are read as part of the
diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will
report it as a device diagnostic failure. These writes are controlled by a micro-program which sometimes
waits if the line is active; SYNC is the micro-program command that causes the wait. When the micro-
program waits, the initial RAM write does not occur, which causes the diagn ostic error. T hus in this case,
if the line is not idle, the initialization sequence may not be written, which will be reported as a device
diagnostic failure.
However, the initialization sequence and diagnostics of the COM20022I should be independent of the
network status. This is accomplished through some additional logic to decode the program counter,
enabled by the NOSYNC bit. When it finds that the micro-p rogram is in th e initializ ation r outin e, it disabl es
the SYNC command. In t his case, the initialization will not be held up b y the line status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to
be written.
10.2 EF Bit
The EF bit controls sever al modifications to int ernal operation timing and logic. It is defined as follows:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the
new internal operati on timing (the timing is the same as i n the COM20020 Rev. B); EF=1: Enable t he new
internal operation timing.
The EF bit controls the f ollowing timing/logic refinements in the COM20022I:
a) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt and
Clear Flag command and by reading the Next-ID register. This minimum disable time is changed by the
Data Rate. For exampl e, it is 200nS at 2.5Mbps and 50nS at 10Mbps. The 50nS width will be t oo short to
for the Interrupt to be seen.
Setting the EF bit will change the minimum disable time to always be more than 200nS even if the Data
Rate is 10Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The
frequency of this clock is always 20MHz even if the data rate is 10Mbps.
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b) Synchronize the Pre-Scalar Out put
The Pre-Scalar is used to change t he data rate. T he output clock is selected by CKP3- 1 bits in the Setup1
register. The CKP3-1 bits are changed by writing the Setup1 register from outside the CPU. It's not
synchronized between the CPU and COM20022I. Thus, changing the CKP2-0 timing does not synchronize
with the internal clocks of Pre-Scalar, and changing CKP2-0 may cause spike noise to appear on the
output clock line.
Setting the EF bit will include flip-flops inserted between the Setup1 register and Pre-Scalar for
synchronizing the CKP2-0 with Pre-Scalar’s internal clocks.
Never change the CKP2-0 when the data rate is over 5 Mbps. They must all be zero.
c) Shorten The Write Interval Time To T he Command Register
The COM20022I limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rat e. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25
Kbps. This 1.6 μS is very long for CPU.
Setting the EF bit will change the clock source f rom OSCK clock (8 times frequency of d ata rate) to XTAL
clock which is not changed b y the data rate, such that the minimum interval time becomes 100 nS.
d) Eliminate The Wr ite Prohibition Period For T he Enable Tx/Rx Commands
The COM20022I has a write prohibition period for writing the Enable Transmit/Receive Commands. This
period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by
setting the TA/RI bit with an internal pulse signal. It is 3.2 μS at 156.25 Kbps. This period may be a
problem when using interrupt processing. The interrupt occurs when the RI bit returns to High. The CPU
writes the next Enable Receive Command to the other page immediately. In this case, the interval time
between the interrupt and writing Comm and is shorter than 3.2 μS.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for
setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1 on the fol lowing
page.
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
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Tx/Rx comp leted
TA/RI bit
Internal Setting Pulse
nINTR pin
prohibition period
EF=1
Tx/Rx completed
TA/RI bit
Internal Setting Pulse
nINTR pin
EF=0
Figure 10.1 - Effect of the EF Bit on the TA/RI Bit
The EF bit also controls t he resolution of the following issues from the COM20020 Rev B:
a) Network MAP Generation
Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent no de. Every
time the Tentative-I D register is written, the effect of the old Tentat ive-ID remains active for a while, which
results in an incorrect network map. It can be avoided by a carefully coded software routine, but this
requires the programmer to have deep knowledge of how the COM20022I works. Duplicate-ID is mainly
used for generating the Network MAP. This has the same issue as Tentative-ID.
A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when
the COM20022I detects a write operation to Tentative-ID or Node-ID register. With this change,
programmers can use the Tentat ive-ID or Duplicate-I D for generating the network MAP without any issues.
This change is Enabled/Disabled by the EF bit.
b) Mask Register Reset
The Mask register is reset by a soft reset in the COM20020 Rev. A, but is not reset in Rev. B. The Mask
register is related to the Status and Diagnostic register, so it should be reset by a soft reset. Otherwise,
every time the soft reset happens, the COM20020 Rev. B generates an unnecessary interrupt since the
status bits RI and TA are back to one by the soft reset .
This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft
reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to Hi gh in
the Configurat ion register. This solution is Enabled/Disabled by the EF bit.
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Chapter 11 Appendix B: Example of Interface
Circuit Diagram to ISA Bus
ISA Bus
A
EN
SA15-
SD15-
nIOR
nIOW
SA2-
IRQm
nIOCS16
DRQn
nDACK
TC
nREFRES
RESETDR
12
12 bit
Comparator
LS688x
nG
P P=Q QI/O Address Seeting (DIP
16 bit
Transceiver
LS245x
A
B
DIR nG
3
D15-D0
nRD
nWR
A
2-A0
nINTR
nIOCS16
DREQ
nDACK
TC
nREFEX
nRESET
nCS
16
3
Schmitt-Trigger
Open-Collector
12 COM2002I
5V
16
A
