74LCX08MT - Fairchild Semiconductor

March 1995

Revised February 2005

74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

74LCX08

Low Voltage Quad 2-Input AND Gate

with 5V Tolerant Input s

General Descript ion

The LCX08 contains four 2-input AND gates. The inputs

tolerate voltage s up to 7 V allowing th e inter face of 5V sys-

tems to 3V systems.

The 74LVX08 is fabricat ed with advanced CMO S technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■5V tolerant inputs

■2.3V–3.6V VCC specifications provided

■5.5 ns tPD max (VCC

3.3V), 10

A ICC max

■Power down high impedance inputs and outputs

■

24 mA output drive (VCC

3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up performance exceeds JEDEC 78 conditions

■ESD performance :

Human body model

2000V

Machine model

150V

■Leadless Pb-Free DQFN package

Ordering Code:

Devices also available in Tape and Reel. Specify by appe nding the s uffix let t er “X” to th e ordering co de.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Fre e product (per JEDE C J- ST D -020B). Device is av ailable in Tape an d R eel only.

Note 2: DQFN packag e av ailable in Tape and Reel only.

Order Number Package

Number Package Description

74LCX08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX08MX_NL

(Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX08BQX

(Note 2) MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LCX08MTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

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74LCX08

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagrams

Pin Assignments for SOIC, SOP, and TSSOP

Pad Assignment s for DQFN

(To p View)

Pin Names Description

An, BnInputs

OnOutputs

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74LCX08

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions (Note 5)

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The para metric value s defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The “Recom-

mended Operating Conditions” table will define the con dit ions for ac t ual devic e operation.

Note 4: IO Absolu te Maximu m Rating must be observed.

Note 5: Unused input s m ust be he ld H I GH or LOW. They may not f l oat.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



7.0 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Voltage



0.5 to VCC



0.5 Output in HI GH or LOW State (Note 4) V

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA



50 VO

VCC

IODC Output Source/Sink Current

50 mA

ICC DC Supply Current per Supply Pin

100 mA

IGND DC Ground Current per Ground Pin

100 mA

TSTG Storage Temperatur e



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 05.5V

VOOutput Voltage HIGH or LOW State 0 VCC V

IOH/IOL Output Curr en t VCC

3.0V



3.6V

24 mAVCC

2.7V



3.0V

VCC

2.3V



2.7V

TAFree-Air Operating Temperature



40 85

V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3



2.7 1.7 V

2.7



3.6 2.0

VIL LOW Level Input Voltage 2.3



2.7 0.7 V

2.3



3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A2.3



3.6 VCC



0.2

IOH = -8 mA 2.3 1.8

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL

100

A2.3



3.6 0.2

IOL = 8mA 2.3 0.6

IOL

12 mA 2.7 0.4

IOL

16 mA 3.0 0.4

IOL

24 mA 3.0 0.55

IIInput Leakage Current 0

5.5V 2.3



3.6

5.0

IOFF Power-Off Leakage Current VI or VO

5.5V 0 10

ICC Quiescent Supply Current VI

VCC or GND 2.3



3.6 10

3.6V

5.5V 2.3



3.6

ICC Increase in ICC per Input VIH

VCC



0.6V 2.3



3.6 500

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74LCX08

AC Electrical Characteristics

Note 6: Skew is de fi ned as th e absolut e valu e of the difference between the actual propagation delay f or any t w o separat e outpu ts of t he same device. The

specif ic ation ap plies to an y o ut puts switch ing in the same direc t ion, either HIGH-to-LOW (tOSHL) or LOW-to-HI GH (t OSLH).

Dynamic Switching Characteristics

Capacitance

Symbol Parameter



C to



C, RL

500

Units

VCC

3.3V

0.3V VCC

2.7V VCC

2.5V

0.2V

50 pF CL

30 pF

Min Max Min Max Min Max

tPHL Propagation Delay 1.5 5.5 1.5 6.2 1.5 6.6 ns

tPLH 1.55.51.56.21.56.6

tOSHL Output to Output Skew (Note 6) 1.0 ns

tOSLH 1.0

Symbol Parameter Conditions VCC TA

CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3 0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3



0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5



0.6

Symbol Parameter Conditions Typical Units

CIN Input Capaci tance VCC

Open, VI

0V or VCC 7pF

COUT Output Capacitance VCC

3.3V, VI

0V or VCC 8pF

CPD Power Dissipation Capacitance V CC

3.3V, VI

0V or VCC, f

10 MHz 25 pF

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74LCX08

AC Loading and Waveforms Generic for LCX Family

FIGURE 1. AC Test Circuit

(CL incl udes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay, Pulse Width and trec Waveforms

3-STATE Output High Enable and

Disable TImes for Logic

3-STATE Output Low Enable and

Disable Times for Logic

Setup Time, Hold TIme and Recovery TI me for Logic

trise and tfall

FIGURE 2. Waveform s

(Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC

3.3

0.3V

VCC x 2 at VCC

2.5

0.2V

tPZH,tPHZ GND

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL



0.3V VOL



0.3V VOL



0.15V

VyVOH



0.3V VOH



0.3V VOH



0.15V

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74LCX08

Schematic Diagram Generic for LCX Family

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74LCX08

Tape and Reel S pecification

Tape Format for DQFN

TAPE DIMENSIONS inches (millimeters)

REEL DIMENSIONS inches (millimeters)

Packa ge Tap e Numb er Cavity Cove r Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

BQX Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Tape SizeABCDNW1W2

12 mm 13.0 0.059 0.512 0.795 2.165 0.488 0.724

(330.0) (1.50) (13.00) (20.20) (55.00) (12.4) (18.4)

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74LCX08

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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74LCX08

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74LCX08

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm

Packag e Num b er MLP01 4A

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74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC14

Fairchild does not assum e any responsibility for use of any circuitry des cribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in t he labe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.