Intel® Itanium™ Processor at 800 MHz
and 733 MHz Datasheet
Product Features
■W ide parallel hardware bas ed on Itanium™
architecture for high performance
—Fifteen execution units
—Cache hints for L1, L2, and L3 caches
for reduced memory latency
—256 gen eral an d floating-point registers
with rotating registers
—Register stack engine for effective
management of processor resources
—Support for predication and speculation
—Full speed 4-MB or 2-MB L3 cache
—On-die L1 and L2 caches
■Extensive RAS features for mi ssion-critical
applications
—Full SMBu s compatibility
—Enhanced Machine Check Architecture
with ECC and parity error recovery
—Built-in processor information ROM
—Built-in programmable EEPROM
■High bandwid th system bus for
multiprocessor scalability
—2.1 GB/s bandwidth
—64-bit wide system bus
—44 bits of physical memory addressing,
and 54 bits of virtual addressing
—U p to four proc esso rs on the same
system bus at 266 MHz data frequency
—Expandabl e to systems with multiple
system buses
—Compatible with I ntel® 460GX chipset
■Features to support flexible platform
environments
—Hardware compatible with IA-32
binaries
—Bi-endian support
—Processor Abstraction Layer eliminates
processor dependencies
Document Number: 249634-001
May 2001
The Intel® Itanium™ processor, the first in a family of processors based on Itanium architecture,
is designed to address the needs of high-performance servers and workstations. The Itanium
architecture goes beyond RISC and CISC approaches by pairing massive processing resources
with intelligent compilers that enable parallel execution explicit to the processor. Its large internal
resources combine with p redication and s peculation to enab le optimization f or high performance
applications running on Windows* Advanced Server Limited Edition, Windows* XP 64-bit
Edition, Linux, AIX* 5L, HP-UX* 11 i v1.5 and other Itanium-based operating systems. The
Itanium processor is designed to support very large scale systems, including those employing
several thousand processors, to provide the processing power and performance head room for
back-office data-intensive servers, internet
servers, and large data set computation inten-
sive appl ications fo r high -end workstations.
SMBus co mpatibility and comprehensive
Reliability, Availability and Serviceability
(RAS) features make the Itanium processor
ideal for applications that demand continuous
operation. In addition, the Itanium processor is
fully compatible, in hardwar e, with IA-32
instruction binaries to preserve existing
software investments. For high performance
servers and workstations, the Itanium pro-
cessor offers outstanding performance and
reliability for today ’s applications and the
scalability to addres s the growing e-business
needs of tomorrow.
ii Itanium® Procesor at 800 MHz and 733 MHz Datasheet
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserv es these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Itanium™ processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’ s website at http://dev eloper.intel.com/design/litcentr.
Intel, Itanium, Pentium, and Xeon are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
Copyright © 2001, Intel Corporation
*Other names and brands may be claimed as the property of others.
I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel. Implementation of
the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics, N.V. and North American
Phillips Corporation.
Itanium® Procesor at 800 MHz and 733 MHz Datasheet iii
Contents
1 Introduction......................................................................................................................1-1
1.1 Intel® Itanium™ Processor 4 MB Cartridge.......................................................1-1
1.2 Intel® Itanium™ Processor 2 MB Cartridge.......................................................1-1
1.3 Intel® Itanium™ Processor System Data Bus....................................................1-2
1.4 Processor Abstraction Layer..............................................................................1-2
1.5 Mixing Processors of Different Frequencies and Cache Sizes ..........................1-2
1.6 Terminology........................................................................................................1-3
1.7 References.........................................................................................................1-3
2 Electrical Specifications...................................................................................................2-1
2.1 Intel® Itanium™ Processor System Bus............................................................2-1
2.1.1 System Bus Power Pins........................................................................2-1
2.1.2 System Bus Reserved Pins...................................................................2-1
2.2 System Bus Signals ...........................................................................................2-1
2.2.1 Signal Groups........................................................................................2-1
2.2.2 Signal Descriptions................................................................................2-2
2.3 Cartridge Specifications .....................................................................................2-3
2.4 Signal Specifications..........................................................................................2-4
2.4.1 DC Specificat ion s.. ...... ....... ...... ...... ....... ...... ....... ...... ....... ................... ...2-4
2.4.2 AC Specifications for the System Bus...................................................2-6
2.4.3 AC Specifications for Clock, Test Access Port, and
System Management Bus...................................................................2-12
2.4.4 Maximum Ratings................................................................................2-13
2.5 Power Pod Connector Signals .........................................................................2-14
2.6 Intel® Itanium™ Processor System Bus Clock and Processor Clocking.........2-17
2.7 Signal Quality and Noise Margin......................................................................2-20
2.8 Recommended Connections for Unused Pins .................................................2-21
3 Pinout Specifications.......................................................................................................3-1
4 Mechanical Specifications...............................................................................................4-1
4.1 Cartridge Features .............................................................................................4-1
4.1.1 Cartridge Top Surface Features............................................................4-1
4.1.2 Cartridge Bottom Surface Features.......................................................4-2
4.1.3 Power Connector...................................................................................4-3
4.2 Cartridge Mechanical Dimensions......................................................................4-5
5 Thermal Specifications....................................................................................................5-1
5.1 Thermal Circuit...................................................................................................5-1
5.1.1 Thermal Alert.........................................................................................5-1
5.1.2 Thermal Trip..........................................................................................5-2
5.2 Cartridge Thermal Specifications and Considerations .......................................5-2
5.2.1 Thermal Plate Temperature ..................................................................5-2
5.2.2 Thermal Budget.....................................................................................5-2
5.2.3 Cartridge Temperature Deviation..........................................................5-3
iv Itanium® Procesor at 800 MHz and 733 MHz Datasheet
6 System Management Feature Specifications..................................................................6-1
6.1 System Management Features and Components..............................................6-1
6.2 System Management Interface ..........................................................................6-2
6.2.1 SMBus Signals......................................................................................6-2
6.2.2 SMBus Device Addressing....................................................................6-2
6.3 PIROM and Scratch EEPROM...........................................................................6-4
6.3.1 Proces sor Inform ati on ROM.. ................... ...... ....... ...... ....... ...... ....... ......6-4
6.3.2 Scratch EEPROM .................................................................................6-7
6.3.3 Processor Information ROM and Scratch EEPROM
Supported SMBUS Transactions ..........................................................6-7
6.4 Thermal Sensing Device....................................................................................6-8
6.4.1 Thermal Sensing Device Supported SMBus Transactions ...................6-9
6.4.2 Thermal Sensing Device Registers.....................................................6-10
Figures 1-1 Intel® Itanium™ Processor 4 MB Cartridge Block Diagram...............................1-1
1-2 Intel® Itanium™ Processor 2 MB Cartridge Block Diagram...............................1-2
2-1 Common Clock Timing Definition Overview.......................................................2-6
2-2 Common Clock Mode Valid Delay Timings........................................................2-7
2-3 Common Clock Mode Setup and Hold Timings .................................................2-8
2-4 Source Synchronous Timing Definition Overview..............................................2-9
2-5 TVBS and TVAS Timing Diagram....................................................................2-10
2-6 Source Synchronous Mode Data Setup and Hold Timings..............................2-11
2-7 Bus Clock to Strobe Delay Timing ...................................................................2-11
2-8 System Clock Waveform..................................................................................2-12
2-9 SMSC Clock Waveform ...................................................................................2-13
2-10 Intel® Itanium™ Processor Power Tab Connection (Top View)......................2-15
2-11 Intel® Itanium™ Processor Power Tab Connection (Bottom View).................2-15
2-12 Example Schematic for System Bus Multiplier Pin Sharing.............................2-18
2-13 System Bus Reset and Configuration Timings for Cold Reset.........................2-19
2-14 System Bus Reset and Configuration Timings for Warm Reset ......................2-20
2-15 Example Data Signal Waveform at Intel® Itanium™ Processor Receiv er Pad2-21
3-1 Intel® Itanium™ Processor PAC418 Cartridge Pin Locations (Top View).........3-1
4-1 Intel® Itanium™ Processor PAC418 Top Isometric View..................................4-2
4-2 Intel® Itanium™ Processor PAC418 Bottom Isometric View.............................4-2
4-3 Power Tab Location on PAC418 Cartridge Substrate........................................4-3
4-4 Power Tab Location on PAC418 Cartridge Substrate, Detail C.........................4-4
4-5 Power Tab Location on PAC418 Cartridge Substrate, Detail D.........................4-5
4-6 Intel® Itanium™ Processor PAC418 Cartridge Mechanical Drawings
(Sheet 1 of 3) .....................................................................................................4-6
4-7 Intel® Itanium™ Processor PAC418 Cartridge Mechanical Drawings
(Sheet 2 of 3) .....................................................................................................4-7
4-8 Intel® Itanium™ Processor PAC418 Cartridge Mechanical Drawings
(Sheet 3 of 3) .....................................................................................................4-8
5-1 Intel® Itanium™ Processor Thermal Features...................................................5-1
5-2 Processor Tplate Temperature Measurement Location.....................................5-3
6-1 System Management Components on the Intel® Itanium™
Proces sor Cartr idge .................... ................... ....... ...... ....... ...... ....... ...... ....... ......6-1
6-2 Logical Schematic of SMBus Circuitry ...............................................................6-3
Itanium® Procesor at 800 MHz and 733 MHz Datasheet v
Tables 2-1 Intel® Itanium™ Processor System Bus Signal Groups ....................................2-2
2-2 Signal Descriptions.............................................................................................2-3
2-3 Intel® Itanium™ Processor 2-MB and 4-MB Cartridge Specification.................2-3
2-4 AGTL+ Signals DC Specifications......................................................................2-5
2-5 PWRGOOD Signal DC Specifications................................................................2-5
2-6 System Bus Clock Differential HSTL DC Specifications ....................................2-5
2-7 TAP Connection Signals DC Specifications.......................................................2-5
2-8 SMBus Signals DC Specifications......................................................................2-5
2-9 LVTTL DC Specifications...................................................................................2-6
2-10 AGTL+ Address/Control Signal Group Common Clock AC Timing
Specifications.....................................................................................................2-8
2-11 AGTL+ Data Signal Group Common Clock AC Timing Specifications...............2-8
2-12 AGTL+ Asynchronous Interrupt Signal Group Common Clock AC
Specifications.....................................................................................................2-9
2-13 AGTL+ Data Signal Group Source Synchronous AC Timing Specifications....2-11
2-14 System Bus Clock Differential HSTL AC Specifications...................................2-12
2-15 TAP Signal AC Specifications..........................................................................2-13
2-16 SMBus Signal AC Specifications......................................................................2-13
2-17 Intel® Itanium™ Processor Absolute Maximum Ratings..................................2-14
2-18 Intel® Itanium™ Processor Power Pod Connector Signals .............................2-14
2-19 Processor Core Voltage Identification Code ....................................................2-16
2-20 Cache Voltage Identification Code...................................................................2-16
2-21 Power Pod Slew Rate Requirements...............................................................2-17
2-22 Intel® Itanium™ Processor System Bus Ratios Supported .............................2-18
2-23 Signal Quality Specifications for System Bus Signals at Intel®
Itanium™ Processor Receiver Pad..................................................................2-21
2-24 Connection for Unused Pins.............................................................................2-21
3-1 Pin/Signal Information Sorted by Pin Name.......................................................3-2
3-2 Pin/Signal Information Sorted by Pin Location.................................................3-11
4-1 Intel® Itanium™ Processor PAC418 Cartridge Dimensions ..............................4-9
5-1 Intel® Itanium™ Processor Thermal Design Specifications...............................5-2
5-2 Example Thermal Solution Performance for the 4MB Intel®
Itanium™ Processor Cartridge at Thermal Plate Power of 130W......................5-3
6-1 System Management Interface Signal Descriptions...........................................6-2
6-2 Thermal Sensing Device SMBus Addressing on the Intel®
Itanium™ Processor Cartridge...........................................................................6-3
6-3 EEPROM SMBus Addressing on the Intel® Itanium™
Processor Cartridge ...........................................................................................6-4
6-4 Processor Information ROM Format ..................................................................6-4
6-5 Current Address Read SMBus Packet...............................................................6-8
6-6 Random Address Read SMBus Packet .............................................................6-8
6-7 Byte Write SMBus Packet..................................................................................6-8
6-8 Write Byte SMBus Packet..................................................................................6-9
6-9 Read Byte SMBus Packet..................................................................................6-9
6-10 Send Byte SMBus Packet..................................................................................6-9
6-11 Receive Byte SMBus Packet..............................................................................6-9
6-12 ARA SMBus Pac ket ................. ....... ...... ...... ....... ...... ....... ...... ....... ................... ...6-9
6-13 Command Byte Bit Assignment........................................................................6-10
6-14 Thermal Sensing Device Status Register.........................................................6-11
vi Itanium® Procesor at 800 MHz and 733 MHz Datasheet
6-15 Thermal Sensing Device Configuration Register.............................................6-11
6-16 Thermal Sensing Device Conversion Rate Register........................................6-12
Itanium® Procesor at 800 MHz and 733 MHz Datasheet vii
Revision History
Version
Number Description Date
001 Initia l Releas e of this docum ent. May 2001
viii Itanium® Procesor at 800 MHz and 733 MHz Datasheet
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 1-1
Introduction 1
The Intel® Itanium™ processor is the first member of a family of processors based on the 64-bit
Itanium architecture. The Itanium architecture provides high performance and 64-bit architecture
in addition to full binary compatibility with IA-32 software. This document provides the electrical,
mechanical, thermal and system m anagem ent feature specification s for the I ntel Itanium p rocess or
cartridge for use while designin g systems with the Intel Itanium processor.
Note: This document contain s data that is su bject to change. Intel shall have no responsibility for
conflicts or incompatibilities arising from future changes to the data contained in this document.
1.1 Intel® Itanium™ Processor 4 MB Cartridge
The Intel Itanium processor 4 MB cartridge contains the processor core and 4 MB of Level 3 (L3)
cache (four 1 MB Intel Cache SRAM). The high speed L3 cache bus is completely isolated in the
Intel Itanium processor cartridge. Figure 1-1 shows the block diagram for the In tel It anium
processor 4 MB cartridge.
1.2 Intel® Itanium™ Processor 2 MB Cartridge
The Intel Itanium p rocessor 2 MB cartridge contains the processor co re and 2 MB of L3 cache (two
1 MB Intel Cache SRAMs). The high speed L3 cache bus is completely isolated in the Intel
Itanium processor cartridge. Figure 1-2 shows the block diagram for the Intel Itanium processor
2 MB cartridge.
Figure 1-1. Intel® Itanium™ Processor 4 MB Cartridge Block Diagram
000576a
Processor Core
CSRAM
Address
Command
Response
CSRAM
CSRAM CSRAM
System Bus
DATA
[0:63] DATA
[64:127]
Introduction
1-2 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
1.3 Intel® Itanium™ Processor System Data Bus
The system bus signals use an enhanced version of the low voltage GTL+ (Gunning Transceiver
Logic) signaling technology used by the Pentium® III and Pent ium III Xeon™ processors. For the
highest performance, the system bus supports source synchronous data transfers. The system bus
signals require external termination on each end of the signal trace to help supply the high signal
level and to control reflecti ons o n the tr ans m ission line. Maximum system data bus throughput is
2.1 GB/sec.
1.4 Processor Abstraction Layer
The Itanium processor cartridge functionality requires the Processor Abstraction Layer (PAL)
firmware. This PAL f irmware r esides in the system flash memory and is part of the Intel Itanium
architecture. This firmware provides an abstraction level between the processor hardware
implementation, the system s oftware and platform firmware to maintain a sing le software interf ace
for multiple imp lementations of the processor silicon steppings. PAL firmware encapsulates those
processor functions that may change from one implementation to another so that the System
Abstraction Layer (SAL) can maintain a consistent view of the processor.
SAL consists of the platform dependent firmware. SAL is the Basic Input/Output System (BIOS)
required to boot the operating system (OS). The Intel® Itanium™ Architecture Software
Developer’s Manual, Vol. 2: System Architecture describes the PAL interface in detail.
1.5 Mixing Processors of Different Frequencies and
Cache Sizes
All Itanium processors on the same system bus are required to have the same cache size ( either 2 M
or 4 M) and identical core frequency. Mixing components of different core frequencies and cache
sizes is not sup por ted and ha s not been validated by Intel. Operating system support for multi-
processing with mixed components should also be considered.
While Intel has done nothing to specifically prevent processors within a multi-processor
environment from operating at differing frequencies and differing cache sizes, there may be
Figure 1-2. Intel® Itanium™ Processor 2 MB Cartridge Block Diagram
000577
Processor Core
CSRAM
Address
Command
Response
CSRAM
System Bus
DATA
[0:63] DATA
[64:127]
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 1-3
Introduction
uncharacterized errata that exist in such configurations. Customers would be fully responsible for,
and may wish to perform, validation of system configurations with mixed components other than
the supported configurati ons described above.
1.6 Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when RESET# is low, a processor reset has been requested. When NMI is high, a non-
maskable interrupt has occurred . In the cas e of lines where th e name does n ot imply an active state
but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the
signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also
refers to a hex ‘A’ (H= High logic level, L= Low logic level).
The term ‘system bus’ refers to the interface between the processor, system core logic and other
bus agents. The system bus is a multiprocessing interface to processors, memory and I/O. The L3
cache does NOT connect to the system bus, and is not accessib le by other agents on the system bus .
Cache coherency is maintained with other agents on the system bus through the MESI cache
protocol as supported by the HIT# and HITM# bus signals.
The term “Intel Itanium processor” refers to the cartridge package which interfaces to a host
system board through a PAC418 connector. Intel Itanium processors include a processor core, an
L3 cache, and variou s system management features . The Intel Itanium processor inclu des a thermal
plate for a cooling solution attachment.
A signal name has all capitalized letter s, e.g. VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain subscript, e.g.,
VCCcore, or a capitalized abbreviated subscript, e.g. TCO.
1.7 References
The reader of this specification should also be fam iliar with material and concep ts presented in the
following documents and tools:
•Intel® Itanium™ Processor Hardware Developer’s Manual (Document Number: 248701)
•Intel® Itanium™ Processor Specification Update (Document Number: 249720)
•PAC418 VLIF Socket and Cartridge Ejector Design Specifications
•PAC418 Cartridge/Power Pod Retention Mechanism and Triple Beam Design Guide
•Itanium™ Processor Heatsink Guidelines
•Itanium™ Pro cessor VTT Voltage Regulation Specification
•Intel® Itanium™ Architecture Software Developer’s Manual, Volume 1-4 (Document
Numbers: 245317, 245318, 245319, and 245320)
Note: Contact your Intel representative for the latest revision of the documents without document
numbers.
Introduction
1-4 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-1
Electrical Specifications 2
This chapter describes the electrical specifications of the Intel Itanium processor 4-MB and 2-MB
cartridges.
2.1 Intel® Itanium™ Processor System Bus
Most Intel Itanium processor signals use a variation of the Pentium III processor and Pentium III
Xeon process or AGTL+ signalin g technol ogy. The termination volta ge, VCTERM, is generated on
the baseboard and is the system bus high reference voltage. The buffers that drive most of the
system bus signals on the Intel Itanium processor are actively driven to VCTERM during the low-
to-high transitio n to im pro ve rise times and reduce noise. These signals sho uld still be considered
open-drain and require term ination to VCTERM which provides the high signal level. This
specification is slightly different from the standard AGTL+ specification.
AGTL+ inputs use dif ferential receivers which require a r eference signal (VREF). VREF is used b y
the receivers to determine if a signal is a logical 0 or a logical 1. The Intel Itanium processor uses
separate address, control and data VREFs which are generated on the baseboard. Termination is
used to pull the bus up to the high voltage level and to contr ol signal integ ri ty on the transm ission
line. The baseboard contains termination resistors that provide termination for each of the Intel
Itanium processor system bus signals. These specifications assume the equivalent of five AGTL+
loads (four processors and one chipset) to ensure the proper timings on rising and falling edges.
2.1.1 System Bus Power Pins
There are 26 VCTERM PAC418 input pins to provide power to the driver buffers and termination
during a low-to-high signal transition. There are 140 VSS pins which, in addition to the
VSSprocessor input at the power tab connector , p rovide ground to the pro cessor and cache. Power for
the processor core, cache core and cache I/O is provided through the power tab connector by
VCCprocessor and VCCcache. Two 3.3V pins are provided on the system bus for use by the SMBus.
3.3V, VCTERM, and VSS must remain electrically separated from one another.
2.1.2 System Bus Reserved Pins
All pins designated as “N/C” or “No Connect” should remain unconnected. Pins designated as
“PU[2:0]” or “PD[3:0]” should be connected via a resistor to VCTERM or VSS, respectively (see
Section 2.8 for details). The pins must be strapped to the appropriate voltage for normal operation.
2.2 System Bus Signals
2.2.1 Signal Groups
Table 2-1 contai ns Intel Itaniu m proces sor sys tem bus s ignals t hat have been combin ed into groups
by buffer type and whether they are inputs, outputs or bidirectional.
Electrical Specifications
2-2 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
All system bus outputs should be treated as open drain and require a high level source provided
externally by the termination resistor .
AGTL+ inputs have dif ferential input b uffers which use 2/3 VCTERM as a ref erence level. AGTL+
output signals require termination to VCTERM. In this document, “AGTL+ Input Signals” refers to
the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+
Output Signals” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
The Power Good s ignal and TAP (Test Access Port) Connection Input si gnals use a non -differ ential
receiver with levels that are similar to AGTL+. No reference voltage is required for these signals.
The TAP Connection Output signals are AGTL+ output signals.
The HSTL Clock signals are the differential clock inputs for the Intel Itanium processor. The
System Management Bus (SMBus) signals and LVTTL Power Pod signals are driven using the
3.3V CMOS logic lev e ls listed in Table 2-8 and Table 2-9, respectively. Please refer to
Section 2.2.2 for de scriptions for the “Other” and “Reserved” signals.
Please refer to the Intel® Itanium™ Processor Hardware Developer’s Manual for recommended
terminations for all system bus sig nals .
2.2.2 Signal Descriptions
The Intel® Itanium™ Processor Hardware Developer’s Manual document cont ains functional
descriptions of all system bus signals and LVTTL Powerpod signals. Further descriptions of the
System Management signals are contained in Chapter 6. The signals listed under the group
“Power” and “Other” are described here.
Table 2-1. Inte l® Itanium™ Processor System Bus Signal Groups
Group Name Signals
AGTL+ Input Signals BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[7:0]#, IDS#,
RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Asynchronous Interrupt Input Signalsa
a. The AGTL+ asynchronous interrupt signals have special setup and hold timings that differ from those of standard AGTL+. See
Table 2-12 for more information.
A20M#, DRATE#, IGNNE#, INIT#, LINT[1,0], PMI#,
TRISTATE#
AGTL+ Output Signals FERR#, THERM TRIP#
AGTL+ I/O Signals A[43:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#,
BPM[5:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#,
DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,
SBSY#, STBN[3:0]#, STBP[3:0]#, TND#
Power Good Signal PWRGOOD
HSTL Clock Signals BCLKN, BCLKP
TAP Connection Input Signals TCK, TDI, TMS, TRST#
TAP Connection Output Signals TDO
System Management Signals 3.3V, SMA[2:0], SMSC, SMSD, SMWP,
THRMALERT#
Power Signals GND, VCTERM, VREFA[1:0], VREFC[1:0],
VREFDL[1:0], VREFDR[1:0]
LVTTL Power Pod Signals OUTEN, PPODGD#
Other TUNER[2:1], PROCPRES#
Reserved N/C , PD[3:0 ], P U [2:0]
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-3
Electrical Specifications
2.3 Cartridge Specifications
Table 2-3 list the DC voltage, current and power specificatio ns for the Intel Itanium processor
2-MB and 4-MB cartridges. The voltage and current specifications are defined at the Intel Itanium
processor PAC418 cartridge pins.
Operational specification s listed in Table 2-3 throu gh Table 2-16 are only valid while meeting
specifications for case temperature, clock frequency, and input voltages.
Note: Care should be taken to read all notes associated with each parameter.
Table 2-2. Signal Descriptions
Group Name Signals
GND System ground
N/C No connection can be made to these pins.
PD[3:0] These pins must be connected to VSS through a 1 KΩ
resistor.
PU[2:0] PU2 and PU0 must be connected to VCTERM through a
1 KΩ resistor. PU1 must be connected to VCTERM
through a 100 Ω resistor.
TUNER[2:1]
A reference resistor must be connected between each
pin to GND. The reference resistors determine driver
buffer impedance and slew rate settings for the
processor.
PROCPRES# This pin must be connected to VCTERM through a 10
KΩ resistor on the system board.
VCTERM System bus termination voltage (see Table 2-3)
VREFA[1:0] Reference voltage inputs to the address signal receiver
buffers.
VREFC[1:0] Referenc e voltage inputs to the control signal receiver
buffers.
VREFDL[1:0], VREFDR[1:0] Reference voltage inputs to the data signal receiver
buffers.
Table 2-3. Intel® Itanium™ Processor 2-MB and 4-MB Cartridge Specification
Symbol Parameter Min Typ Max Unit Notes
VCCcore_st Static tolerance for
VCCcore VIDprocessor -5% VIDprocessor VIDprocessor +5% V
VCCcore_tr Transient tolerance
for VCCcore VIDprocessor -6% VIDprocessor VIDprocessor +7% V
VCCcache_st Static tolerance for
VCCcache VIDcache -5% VIDcache VIDcache + 5% V
VCCcache_tr Transient tolerance
for VCCcore VIDcache -6% VIDcache VIDcache + 7% V
VCTERM Termination voltage 1.5-1.5% 1.5 1.5+1.5% V
3.3V VCC for SMBus
components 3.14 3.30 3.47 V
Electrical Specifications
2-4 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
2.4 Signal Specifications
2.4.1 DC Specifications
This section describes the DC specifications of the system bus signals. The processor signals DC
specifications are defined at the Intel Itanium processor core. Each signal trace between the Intel
Itanium processor PAC418 cartridge pin and the processor core carries a small amount of current
and has a finite resistance. The signal current produces a voltage drop between the cartridge pin
and the core. Simulations should be run in accordance with these specifications to the processor
core.
Table 2-4 through Table 2-9 describe the DC specifications for the AGTL+, PWRGOOD, HSTL
Clock, TAP Connection, System Management, and LVTTL signals. Please refer to the Intel®
Itanium™ Processor Hardware Developer’s Manual for the TAP connection signals DC
specifications at the debug port. The signals VREFA[1:0], VREFC[1:0], VREFDL[1:0] and
VREFDR[1:0] are collectively referred to as VREF.
VREFA[1:0],
VREFC[1:0],
VREFDL[1:0]
VREFDR[1:0]
Reference voltage 2/3*VCTERM V
ICCcore Curr ent for the
processor core 1.0 71.4 A a, b, c
ICCcache Curr ent for the
cache 1.0 16.5 A a, b, c
ICCTERM Termination voltage
current 0.25 0.5 A d
PSprocessor Power supply slew
rate at the processor
power connector tab
0.4 A/ns
PScache Power supply slew
rate at the cache
power tab connector
0.1 A/ns
PSCTERM Termination voltage
slew rate at the
PAC418 pins
0.05 A/ns
PWRmax Maximum 2M
cartridge power
Maxi mum 4M
cartridge power
116
130
Wc
PWRTDP Thermal design
power
4MB Cartridge
2MB Cartridge
116-130
130
116
We
a. Maximum current (ICC) specifications are intended for system power supply design. The maximum current is defined based on
worst-case VCC, temperature and software application mix.
b. Maximum ICCcore and ICCcache do not occur simultaneously.
c. For all core frequencies.
d. Current drawn by the I/O stage of the processor through the VCTERM pin, not through the termination resistor.
e. Maximum thermal design power is an estimate of the power dissipation for the Intel® Itanium™ processor while executing a
worst-case application mix under nominal VCC and worst-case temperature.
Table 2-3. Inte l® Itanium™ Processor 2-MB and 4-MB Cartridge Specification (Cont’d)
Symbol Parameter Min Typ Max Unit Notes
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-5
Electrical Specifications
Table 2-4. AGTL+ Signals DC Specifications
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 VREF – 200 mV V
VIH Input High Voltage VREF + 200 mV VCTERMmax V
VOL Output Low Voltage 0.6 V a
a. Parameter measured into a 20-ohm resistor to VCTERM.
IOL Output Low Current @ 0.5V 50 mA
ILLeakage Current ± 100 µA b
b. At 1.5V ± 3%.
CAGTL+ AGTL+ Pin Capacitance 7 pF c
c. Total of I/O buffer with ESD structure, package parasitics and capacitance for socket.
Table 2-5. PWRGOOD Signal DC Specifications
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 0.35 V
VIH Input High Voltage 1.2 VCTERMmax V
Table 2-6. System Bus Clock Differential HSTL DC Specifications
Symbol Parameter Min Typ Max Unit Notes
VIH Input High Voltage 0.78 1.7 V Min=VX,min+0.1
VIL Input Low Voltage –0.3 0.58 V Max=VX,min-0.1
VXInput Crossover Voltage 0.68 0.9 V
Table 2-7. TAP Connection Signals DC Specifications
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 0.5 V
VIH Input High Voltage 1.2 VCTERMmax V
VOL Output Low Voltage 0.3 V a
a. Parameter measured into a 20-ohm resistor to VCTERM.
IOL Output Low Current 16.5 19.8 mA
Table 2-8. SMBus Signals DC Specifications
Symbol Parameter Min Typ Max Unit Notes
VIL Input Low Voltage –0.3 0.3*3.3V V
VIH Input High Voltage 0. 7*3.3V 3.465 V Max=3.3+5%
VOL Output Low V oltage 0.4 V
I3.3V 3. 3V Supply Current 5.0 10.0 mA
IOL Output Low Current 3 mA a
a. T he value specified for IOL applies to all signals except for THRMALERT#.
IOL2 Output Low Current 6 mA b
b. T he value specified for IOL2 applies only to THRMALERT# which is an open drain signal.
ILI Input Leakage Current 10 µA
ILO Output Leakage Current 10 µA
Electrical Specifications
2-6 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
a
2.4.2 AC Specific ations for the System Bus
The system address bus operates at a clock frequency of 133 MHz. The system data bus uses
source synchronous clocking, allowing 266 MHz operation.
The AC timing specifications in this section are shown with respect to the pins of the component.
The intent is to provide a method for verifying the component’s I/O timings in a real system. These
specifications reflect the I/O timing specifications against which the actual component can be
tested in a system environment under worst case conditions.
2.4.2.1 Common Clock AC Timing Specifications
The common clock timing specifications for the system bus consists of three parts: clock to driver
output del ay (TCO), flight time (Tflight), and receiver setup an d h old to b us clock (Tsetup and Thold).
These timing parameters reference the driver and receiver components at the pin and are intended
for verifying the component’s I/O timings in a real system.
Figure 2-1 illustrates these timing specifications.
2.4.2.1.1 Clock to Driver Output Delay
The clock to driver output delay (TCO) is defined as the time between the differential bus clock
crossing at the input pin (at the driving agent) relative to the signal crossing a voltage reference,
VREF, at the output pin ( of the driv ing agent) at an edge rate def ined by the enviro nment conditi ons.
Table 2-9. LVTTL DC Specifications
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 3.63 V Max=3.3+10%
VOL Output Low Voltage 0.4 V
VOH Output High Voltage 2.4 V
Figure 2-1. Common Clock Timing Definition Ov erview
000446b
System Network
Package
Trace
Driver
Package
Trace Receiver
Clock at
artridge
Pins
Output
Latch
Clock at
Cartridge
Pins
Input
Latch
Tflight
Itanium™ Processor
Driver I/O Receiver I/O
System Network
TCO Tsetup_clk Thold_clk
Itanium Processor
,
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-7
Electrical Specifications
Figure 2-2 illustrates the TCO timin g definition, and Table 2-10 and Table 2-11 list the TCO values
for the common clock system bus signals. TCO,min represents the delay under fast conditions and
TCO,max represents the delay under slo w conditions.
2.4.2.1.2 Flight Time
The flight time (Tflight) is defined as the time between the signal crossing a reference voltage,
VREF, at the output pin (of the driving agent) relative to the sig nal crossing VREF at the input pin
(of the receiving agent). Flight time is a system dependent timing based on the specific PCB
technology, the interface routing topology, and applicable connectors.
2.4.2.1.3 Receiver Setup and Hold to Bus Clock
The receiver setup and hold to bus clock (Tsetup and Thold) is defined by the signal at the input pin
(of the receiving agent) crossing a reference voltage, VREF, relati ve to the differential bus clock
crossing at the input pin (of the receiving agent). Tsetup and Thold each include the internal clock
skew and tester guardband.
Figure 2-3 illustrates the Tsetup and Thold timing definition, and Table 2-10, Table 2-11, and
Table 2-12 list the Tsetup and Thold values for the common clock system bus signals. Tsetup
represents the worst case setup time requirement under slow conditions. Thold represents the worst
case hold time requirement under fast conditions.
Table 2-10 show the common clock AC timing parameters that the actual component is tested to in
a system environment under worst case conditions. These parameters are intended to provide a
method for verifying the component’s I/O timings in an actual system. All timings are specified in
nanosecond s (ns) to the pi n of the componen t at a rated load of 20 Ω. The voltage reference is VREF.
Figure 2-2. Common Clock Mode Valid Delay Timings
000617b
BCLKN
TCO
BCLKP
VREF
TCO
Vhigh
Vlow
TPW
ValidSignal
T
CO = Clock-to-output delay
T
PW = Pulse width
V
REF = VREF f or AGTL + signal group
V
high = AGTL + signals must achieve a DC high level of at least VREF +200 mV
V
low = AGTL + signals must achieve a DC low level of at least VREF –200 m V
Electrical Specifications
2-8 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
Figure 2-3. Common Clock Mode Setup and Hold Timings
000623b
Table 2-10. AGTL+ Address/Control Signal Group Common Clock AC Timing Specifications
Symbol Parameter Min Max Unit Figure Notes
TCO Output H → L Clock to
Output Delay 0.43 3.46 ns 2-2 a
a. Delay timings are specified into an idealized 20-ohm resistor to VCTERM.
TCO,BNR# Output H → L Clock to
Output Delay 0.43 3.96 ns 2-2 b
b. Delay timings are specified into an idealized 20-ohm resistor to VCTERM, for BNR# signal only.
TCO Output L → H Clock to
Output Delay 0.64 3.14 ns 2-2 a
Tsetup Input Setup Time before
BCLK 1.62 ns 2-3
Thold Input Hold Time after
BCLK 1.00 ns 2-3
Table 2-11. AGTL+ Data Signal Grou p Common Clock AC Timing Specifications
Symbol Parameter Min Max Unit Figure Notes
TCO Output H → L Clock to
Output Delay 0.53 2.85 ns 2-2 a
a. Delay timings are specified into an idealized 20-ohm resistor to VCTERM.
TCO Output L → H Clock to
Output Delay 0.71 3.01 ns 2-2 a
Tsetup Input Setup Time before
BCLK 1.62 ns 2-3
Thold Input Hold Time after
BCLK 1.00 ns 2-3
BCLKN
Setup time
Hold time
VREF for AGTL+ signal group A
=
=
=
Tsetup
BCLKP
VREF Valid
Signal
Thold
Tsetup
Thold
VREF
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-9
Electrical Specifications
2.4.2.2 Source Synchronous AC Timing Specifications
The source synchronous timing specifications for the system bus consists of three parts: driver
valid before and after stro be (TVBS and TVAS), delta f light tim e (∆Tflight), and receiver setup and
hold to strobe (Tsetup and Thold). These three timing parameters reference the driver and receiver
components at the pin and are intended for verifying the component’s I/O timings in a real system.
Figure 2-4 illustrates these timing specifications.
2.4.2.2.1 Driver Vali d Be fore and After Strobe
The driver valid before and after strobe (TVBS and TVAS) is defined as the time between the signal
crossing a reference voltage, VREF, at the output pin (of the driving agent) relative to the
differential strobe crossing at the output pin (of the driving agent).
Figure 2-5 illustrates the TVBS and TVAS timing definition and Table 2-13 lists the TVBS and TVAS
values for the so urce synchron ous system bus sign als. TVBS an d TVAS represen t the worst case data
valid before and after strobe times u nder fast conditions.
Table 2-12. AGTL+ Asynchronous Interrupt Signal Group Common Clock AC Specifications
Symbol Parameter Min Max Unit Figure Notes
Tsetup Input Setup T ime before
BCLK 1.034 ns 2-3 a
a. These signals can be driven asynchronously, but to guarantee determinism, these setup and hold times must be met at the
processor.
Thold Input Hold Time after
BCLK 1.000 ns 2-3 a
TPW Input Pulse Width 1 BCLK
Figure 2-4. Source Synchronous T iming Definition Overview
000965a
System Network
Package
Trace
Driver
Package
Trace Receiver
Strobes at
Cartridge
Pins
Output
Latch
Strobes at
Cartridge
Pins
Input
Latch
Itanium™ Processor
Driver I/O Receiver I/O
System Network
T ,
VBS Tsetup_stb Thold_stb
Itanium Processor
TVAS ,
Electrical Specifications
2-10 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
2.4.2.2.2 Delta Flight Time
The delta flight time (∆Tflight) i s a system dependent t iming base d on the maximum timing
difference between the data and strobe signal flight times due to the specific PCB technology, the
interface routing topology, and applicable connectors. The data signal flight time is measured from
the data signal crossing a reference volta ge, VREF, at the output pin (of the driving agent) relative to
the data si gn al cro ssi ng V REF at the input pin (of the receiv ing ag ent). The strobe si gn al flight time
is measured from the strobe signal crossing a reference voltage, VREF, at the output pin (of the
driving agent) relative to the strobe signal crossing VREF at the input pin (of the receiving agent).
2.4.2.2.3 Receiver Setup and Hold to Strobe
The receiver setup and hold to strobe (Tsetup and Thold) is defined by the signal at the input pin (of
the receiving agent) crossing a reference voltage, VREF, relativ e to the differential strob e cross ing
at the input pin (of the receiving agent). Tsetup and Thold each include the internal clock skew and
tester guardband.
Figure 2-6 illustrates the Tsetup and Thold timing definit ion, and Table 2-13 lists the T setup and Thold
values for the source synchronous system bus signals. Tsetup represents the worst cas e setup time
requirement under slow conditions. Thold represents the worst case hold time requirement under
fast conditions.
Table 2-13 shows the source synchronous AC timing parameters under worst case conditions in a
tester environment. These parameters are intended to provide a method for verifying the
component’s I/O timings in a r eal system. All timings are specified to the pin of the co mponent at a
rated load of 20Ω. The voltage reference is VREF.
Figure 2-5. TVBS and TVAS Timing Diagram
000624a
TVBS
STBN#
STBP#
Signal
TVBS Data output valid before strobe
TVAS Data output valid after strobe
V for AGTL+ signal group
VREF
AGTL+ signals must achieve a DC high level of at least V +200 mV
Vhigh
=
=
=
=
=
Vlow AGTL+ signals must achieve a DC low level of at least V –200 mV=
VREF
REF
REF
REF
Valid
TVAS
Vhigh
Vlow
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-11
Electrical Specifications
Figure 2-6. Source Synchronous Mode Data Setup a nd Hold Timings
000625b
Table 2-13. AGTL+ Data Signal Group Source Synchronous AC Timing Specifications
Symbol Parameter Min Unit Figure Notes
TVBS Data Output H → L Valid
Before S trobe 1.56 ns 2-5 a
a. Valid timings for these signals are specified into an idealized 20-ohm resistor to VCTERM. Data/strobe offset is 1.875 ns (one
quarter clock cycle) at the latch output.
TVBS Data Output L → H Valid
Before S trobe 1.28 ns 2-5 a
TVAS Data Output H → L Valid
After Strobe 1.40 ns 2-5 a
TVAS Data Output L → H Valid
After Strobe 1.60 ns 2-5 a
Tsetup Data Input Setup T ime Before
Strobe 0.63 ns 2-6
Thold Data Input Hold Time After
Strobe 0.59 ns 2-6
Tbclk_strobe Clock to Strobe Delay Time TCO_MIN +
(1/4*Tperiod)
ns 2-7 b, c
b. The strobe signals are generated from the bus clock signals.
c. These Tco,min and Tco,max specifications are for data signals and are found in Table 2-11.
Figure 2-7. Bus Clock to Strobe Delay Timing
000616
Tsetup
STBN#
STBP#
Signal
Tsetup Data output valid before strobe
Thold Data output valid after strobe
V for AGTL+ signal group
VREF
=
=
=
VREF
REF
Valid
Thold
Tbclk_strobe
CLKN
BCLKP
STBN#
STBP#
Electrical Specifications
2-12 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
2.4.3 AC Specifications for Clock, Test Access Port, and System
Management Bus
Table 2-14 through Table 2-16 list the AC specifications for the Itanium processor’s clock, te s t
access port, and system management bus (timing diagrams begin with Figure 2-8). The Itanium
processor uses a differential HSTL clocking scheme with a f requ ency of 1 33 MHz. The test acces s
port (TAP) interface is used fo r sys tem level debug and operates at speeds up to 16 MHz. Th e TAP
signals’ AC specifications at the processor are listed in Table 2-16. The system management bus
(SMBus) is a standard I2C interface which supports operation of up to 100 kHz.
Table 2-14. System Bus Clock Differential HSTL AC Specifications
Symbol Parameter Min Typical Max Unit Figure Notes
Tperiod BCLK Period 7.5 7.65 ns 2-8 a, b
a. The internal core clock frequency is derived from the bus clock.
b. The period specified here is the average period. A given period may vary from this specification as governed by the Input Jitter
specification (Tjitter,i).
fBCLK BCLK Frequency 130.72 133.33 MHz c
c. Data is transferred at twice this frequency in source synchronous mode.
Tjitter,i BCLK Input Jitter 100 ps 2-8 d, e, f, g
d. Input clock jitter is measured at the cross point of the rising edge of BCLKP and the falling edge of BCLKN. The specification
corresponds to the cycle-to-cycle (peak to peak) jitter (i.e. the Nth cycle to the N+1th cycle at any bus cycle N).
e. The measurement should be done at the location closest to the corresponding pins of the microprocessor cartridge.
f. The system clock driver’s close loop jitter bandwidth must be less than 500 KHz (at -20 dB) and preferably less than 100 KHz.
The bandwidth is defined as the clock driver’s output frequency-attenuation plot measured at the -20dB attenuation point.
g. The measurement should be performed with a dedicated jitter measurement instrument (examples: Wavecrest Corp.’s DTS
system or the Amherst’s M1 system). Measurements performed with an oscilloscope using the infinite persistence method may
yield poor results.
Thigh B CLK High Time 3.375 4.125 ns 2-8
Tlow BC LK Low Time 3.375 4.125 ns 2-8
Trise BCLK Rise Time 0.6 1.2 ns 2-8 20–80%
Tfall BCLK Fall Time 0.6 1.2 ns 2-8 2 0–80%
VPP Minimum Input
Swing 600 mV 2-8 h
h. VPPmin is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
Figure 2-8. System Clock Waveform
000615a
80%
Trise
Trise Rise Time
Tfall Fall Time
High Time
Thigh Low Time
Tlow
=
=
=
=
20%
Tfall
Thigh Tlow
Tperiod
Tjitter, i
BCLKN
BCLKP
VPP
=
Tperiod Period
Tjitter, i Long Term Peak-to-Peak Input Jitter
Peak-to-Peak Swing
=
=
=
VPP
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-13
Electrical Specifications
2.4.4 Maximum Ratings
Table 2-17 contains Intel Itanium processor stress ra tings. Functional operation at the absolute
maximum and minimum is neither implied nor guaranteed. The processor should not receive a
clock while subjected to thes e cond itions. Function al operating cond itions are given in the AC and
DC tables. Extended exposure to the ma ximum rating s ma y affect device reliability. Furthermore,
although the pro cess or cont ains prot ecti ve circui try t o res ist damag e from st ati c electr ic dis charge,
one should always take precautions to avoid high static voltages or electric fields.
Table 2-15. TAP Signal AC Specifications
Symbol Parameter Min Max Unit Notes
TCO Clock to Output delay 1.0 10.0 ns a
a. Referenced to TCK falling edge.
TDOdelay TDO on/off delay 25.0 ns a
Tsetup Input setup time for TDI, TMS, and TRST# 5.0 ns b
b. Referenced to TCK rising edge.
Thold Input hold time for TDI, TMS, and TRST# 5.0 ns b
Table 2-16. SMBus Signal AC Specifications
Symbol Parameter Min Max Unit Notes
fSMSC SMSC Clock Frequency 100 kHz
TSMSC SM SC Clo ck Period 10 µs
Thigh SMSC Clock High Time 4.0 µs a
a. Please refer to Figure 2-9.
Tlow SMSC Clock Low Time 4.7 µs a
Trise SMSC Clock Rise Time 1.0 µs a
Tfall SMSC Clock Fall Time 0.3 µs a
Tvalid SMBus Output Valid Delay 1.0 µ s
Tsetup SMBus Input Setup Time 250 ns
Thold SMBus Input Hold Time 0 ns
Tfree Bus Free Tim e 4.7 µs b
b. Bus Free Time is the minimum time allowed between request cycles.
Figur e 2-9. SMSC Clock Waveform
000618
SMSC
Trise
Thigh
Tfall Tlow
Trise Rise Time
Tfall Fall Time
=
=
Thigh High Time
Tlow Low Time
=
=
90% Vcc V (3.3 V)
cc
75% Vcc
25% Vcc
Electrical Specifications
2-14 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
2.5 Power Pod Connector Signals
Power delivery for the Intel Itanium processor cartridge is from a DC-DC converter called the
“power pod”. The power pod consists of a DC-DC converter and a semi-flexible connector which
delivers the voltage to the cartridge.
Table 2-18 lists all of the signals which are part of the Intel Itanium processo r cartridge po wer pod
connector.
The operating voltage of the pr oces sor cor e and of th e L 3 cache die d iffer from each other. Both of
these voltages, VCCproce ssor and VCCcache, are supplied by the power pod through the power tab
connector on the Intel Itanium processor PAC418 cartridge. Figure 2-10 and Figure 2-11 are top
and bottom views of the power tab connector, respectively. Processor ground connection,
VSSprocessor, is provided on the power tab connector as well.
Table 2-17. Int el® Itanium™ Processor Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
Tstorage Processor S torage Temperature 5.0 45.0 °Ca
Tshipping Processor Shipping Temperature –40.0 75.0 °Ca
a. The PAC418 package and integrated vapor chamber technology has been designed and tested to withstand up to 50 freeze/
thaw cycles.
VCCprocessor Any VCCprocessor voltage with
respe ct to G N D –0.35 2.1 V b
b. Operating voltage is the voltage to which the component is designed to operate. See Table 2-6 throughTable 2-9 inclusive.
VCCcache Any VCCcache voltage with
respe ct to G N D –0.5 2.8 V b
VREF Any VREF voltage with respect to
GND –0.3 1.046
(2/3VCTERMmax) V
3.3V Any 3.3V supply voltage with
respe ct to G N D –0.3 5.5 V
VCCprocessor
–VCCcache
Cache supply voltage with
respect to processor supply
voltage
– 1.7 2.23 V c
c. This parameter specifies that the processor will not be immediately damaged by either supply being disabled.
Table 2-18. Int el® Itanium™ Processor Power Pod Connector Signals
Group Name Signals
Power Pod Connector OUTEN, PROCPRES#, PPODGD#, SenseCacheVCC, SenseCacheVSS,
SenseProcVCC, SenseProcVSS, VCC_PROCESSOR, VCC_CACHE,
VID_P RO C ES SO R [ 3:0] , VI D _C ACHE[3:0], VS S_PROCES SO R
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-15
Electrical Specifications
The Intel Itanium processor cartridge power pod connector contains VID voltage identification
signals which program th e DC-DC converter in the power pod to provide voltage s which are
required by various components in the cartridge. The VID signals are needed to support voltage
specification variations on the Intel Itanium processor cartridge.
Figure 2-10. Intel® It anium™ Processor P o wer Tab Connec tion (Top View)
The processor substrate is shown with cartridge package removed. 000466
Figure 2-11. Intel® Itanium™ Processor Power Tab Connection (Bottom View)
The processor substrate is shown with cartridge package removed. 000467a
VSSProcessor
VCCProcessor
3210*3210
VCCCache
RESERVED
VIDProcessor
4 Bits ( MSB... L SB)
RESERVED
VIDCache
4 Bits ( MSB... L SB)
SenseProcVCC
PROCPRES#
SenseProcVSS
SenseCacheVCC
SenseCacheVSS
PPODGD#
OUTEN
RESERVED
Electrical Specifications
2-16 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
The VID signals are static and are either an open circuit or a short to ground. The combination of
open and short cir cuits defines the voltages required by the Intel Itanium processor cartridge.
Warning: If the power pod cannot supply the voltag e s r equested by the components in the Intel Itanium
processor cartridge, then it must disable itself.
The voltages specified by the various VID signal combinations for the processor core and cache
core are listed in Table 2-19 and Table 2-20, respectively. A ‘1’ in this tabl e refers to an open
circuit and a ‘0’ refers to a short to ground. The VID settings and processor and cache core voltages
are recorded in the EEPROM and can be accessed by the SMBus (see Chapter 6 for more
information).
Table 2-19. Processor Core Voltage Identification Code
VID_PROCESSOR[3:0] VCCprocessor
(VDC)
VID_PROCESSOR3 VID_PROCESSOR2 VID_PROCESSOR1 VID_PROCESSOR0
1 1 1 1 Output off
1 1 1 0 1.250
1 1 0 1 1.275
1 1 0 0 1.300
1 0 1 1 1.325
1 0 1 0 1.350
1 0 0 1 1.375
1 0 0 0 1.400
0 1 1 1 1.425
0 1 1 0 1.450
0 1 0 1 1.475
0 1 0 0 1.500
0 0 1 1 1.525
0 0 1 0 1.550
0 0 0 1 1.575
0 0 0 0 1.600
Table 2-20. Cache Voltage Identification Code
VID_CACHE[3:0] VCCcache
(VDC)
VID_CACHE3 VID_CACHE2 VID_CACHE1 VID_CACHE0
1 1 1 1 Output off
10011.650
10001.700
01111.750
01101.800
01011.850
01001.900
00111.950
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-17
Electrical Specifications
Table 2-21 sho ws the sl ew rat e requirements for both outputs of the power pod.
2.6 Intel® Itanium™ Processor System Bus Clock and
Processor Clocking
The BCLKN and BCLKP inputs control the operating frequency of the Intel Itanium processor
system bus interface. All Intel Itanium processor system bus timing parameters are specified with
respect to the falling edge of BCLKN and risin g edge of BC LKP. The Intel Itanium processor core
to bus ratio must be configured during system reset by using the A20M#, IGNNE#, and LINT[1:0]
pins (See Table 2-22). The value on these pins during the system reset sequence determines the
multiplier that the phase lock loop (P LL) will use for the internal core clock. See Figure 2-13 for
the timing relation ship between the s ys tem bus mul tipl ier sig nals , system rese t sig nal and normal
processor operation.
Because the signals A20M#, IGNNE#, and LINT[1:0] pins have different uses after a system reset
is complete, these signals must be multip lexed for conf iguration during reset and for normal use
after reset. The circuit in Figure 2-12 suggested one way to use the system reset signal and a
multiplexer to share these configuration signals. Note that this system reset signal must be driven 2
clock cycles longer than the processor reset signal to meet the timing requirements in Figure 2-13.
The level trans lators af ter the multipl exer transl ates 3.3V o utput levels to the cor rect AGTL+ levels
(1.5V) required by the Intel Itaniu m pr oces sors.
Table 2-22 lists the system bus ratio defined for the Intel Itanium processor family.
0 0 1 0 2.000
0 0 0 1 2.050
0 0 0 0 2.100
Table 2-20. Cache Voltage Identification Code (Cont’d)
VID_CACHE[3:0] VCCcache
(VDC)
VID_CACHE3 VID_CACHE2 VID_CACHE1 VID_CACHE0
Table 2-21. Power Pod Slew Rate Requirements
Output Peak Slew Rate at the Power Pod Connector
VCCprocessor 400 A/µs
VCCcache 100 A/µs
Electrical Specifications
2-18 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
The Itanium processor core to bus ratio is configured during system reset by using the A20M#,
IGNNE# and LINT[1:0] pins. These bus ratio configuration pins are required be to be stable and
valid during the duration of the reset sequence as defined below.
Cold Reset Sequence:
•The bus ratio configuration pins (A20M#, IGNNE#, LINT1, and LINT0) must be stable and
valid at least 1 BCLK before the assertion edge o f PWR GOOD.
•TRISTATE# must be disabled 1 BCLK before the assertion of PWRGOOD and held disabled
for at least 115 micros econds.
•RESET# must be asserted before PWRGOOD is asserted.
•The duration from the assertion of PWRGOOD to the deassertion of RESET# must be 1
millisecond minimum.
•After RESET# is deasser ted, the bus r atio configuration pins must remain valid fo r 2 BCLKs
(minimum) to 16 BCLKs (maximum).
•BCLK is shown as a time reference to the BCLK period. It is not a requirement that this is
BCLKN or BCLKP signal.
Figure 2-13 outlines the timing relationship between the bus ratio configuration pins, RESET# and
PWRGOOD for cold reset.
Figure 2-12. Example Schematic for System Bus Multiplier Pin Sharing
000800b
Table 2-22. Int el® Itanium™ Processor System Bus Ratios Supported
Ratio of Bus
Frequency to Core
Frequency LINT1 LINT0 IGNNE# A20M#
2/11 0(L) 0(L) 0(H) 0(H)
2/12 0(L) 1(H) 1(L) 1(L)
Reserved All other combinations
A20M#
IGNNE#
LINT0
LINT1
10 k
8
3.3V
100
8
System RESET#
Mux
A20M#
IGNNE#
LINT0
LINT1
50
8
V
CTERM
Four Itanium™
Processors V
CTERM
50
8
Level
Translators
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-19
Electrical Specifications
Warm Reset Sequence:
•PWRGOOD remains high throughout the entire sequence as power is already available and
stable to the processor.
•The bus ratio configuration pins (A20M#, IGNNE#, LINT1, and LINT0) must be stable and
valid at least 1 BCLK before the assertion edge of RESET#.
•The duration from the assertion of RESET# to the deassertion of RESET# must be 1
microsecond minimum.
•After RESET# is deasserted, the bus clock ratio configuration pins must remain valid for 2
BCLKs (minimum) to 16 BCLKs (maximum).
•BCLK is shown as a time reference to the BCLK period. It is not a requirement that this is
BCLKN or BCLKP signal.
Figure 2-14 outlines the timing relationship between the bus ratio configuration pins, RESET# and
PWRGOOD for warm reset
Figure 2-13. System Bus Reset and Configuration Timings for Cold Reset
TA = Input set up time before BCLK (defined in Table 2-12)
TB = 1 ms minimum for Cold Reset
TC = 1 BCLK
TD = 2 bclks minimum, 16 bclks maximum
TE = 4 bclks minimum
TF = 115 us minimum 000859a
BCLK
PWRGOOD
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
TB
TRISTATE#
TC
TA
TD
TE
Configuration
(except A20M#,
IGNNE#, LINT[1:0])
TF
Electrical Specifications
2-20 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
2.7 Signal Quality and Noise Margin
The Intel Itanium processor has overshoot/undershoot requirements for system bus signals. A
waveform ex hibiting undershoot/o versh oot is illustrated in Figure 2-15. These requirements
stipulate that a signal at the output of the driver buffer and input of the receiver buffer must not
exceed a maximum absolute overshoot voltage limit and a minimum absolute undershoot voltage
limit. There is also a time dependent, non-linear overshoot requirement above VCTERM and an
undershoot requirement below GND which is dependent on the amplitude and duration of the
overshoot/u nder shoot. The maximum specification s for signal quality is listed in Table 2-23.
Exceeding these limits may cause damage to the Intel Itanium processor.
Figure 2-14. System Bus Reset and Configuration Timings for Warm Reset
TA = Input set up time before BCLK (defined in Table 2-12)
TB = 1 us minimum for Warm Reset
TC = 1 BCLK
TD = 2 bclks minimum, 16 bclks maximum
TE = 4 bclks minimum
TF = 2 bclks minimum, 16 bclks maximum 000777a
BCLK
PWRGOOD
RESET#
Configuration
(A20M#, IGNN E#,
LINT[1:0])
Configuration
(e xcept A20M#,
IGNNE#, LIN T [1 :0 ])
TBTD
TETF
TCTA
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 2-21
Electrical Specifications
2.8 Recommended Connections for Unused Pins
Pins that are unused in an application environment (as opposed to testing environment) should be
connected to the states listed in Table 2-24. Pins that must be used in an application are stated as
such and do not have a recommended state for unused connection.
Figure 2-15. Example Data Signal Waveform at Intel® Itanium™ Processor Receiver Pad
000588
Table 2-23. Signal Quality Specifications for System Bus Signals at Intel® Itanium™
Processor Receiver Pad
Parameter Description Specification Units
VMAX Maximum absolute voltage for system bus
signals at the inputs of receiver buffers 2.1 V
VMIN Minimum absolute voltage for system bus signals
at the inputs of receiver buffers –0.35 V
VCTERM
Maximum
Absolute
Overshoot
Maximum
Absolute
Undershoot
Time-dependent
Overshoot
Time-dependent
Undershoot
VREF
VOL
GND
VMIN
VMAX
Table 2-24. Connection for Unused Pins
Pins / Pin Groups Recommended
Connections Notes
AGTL+ pins H b
HSTL Clock Signals Must be used
TAP Signals
TCK L b
TRST# H b
TDI H b
TDO H b
TMS H b
Electrical Specifications
2-22 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
a. All 3.3V pins must be connected to either 3.3V or GND, at the same time.
b. L = GND, H = VCTERM.
c. THRMALERT# should be pulled up to 3.3V through a resistor. If the system does not supply 3.3V for system management, then
this signal should be left unconnected.
d. PU1 should be pulled up through a 100 ohm resistor.
e. PU0 and PU2 should be pulled up through 1 kohm resistors.
PWRGOOD Signal
PWRGOOD Must be used
System Management Signals
3.3V GND a
SMA N/C
SMSC N/C
SMSD N/C
SMWP N/C
THRMALERT# H c
All Power Signals Must be used
Power Signals
All Power Signals Must be used
LVTTL Power Pod Signals
OUTEN Must be used
PPODGD# Must be used
Other Signals
PROCPRES# Must be used
TUNER[1:0] Must be used
Reserved Pins
N/C N/C
PD[3:0] L b
PU[2:0] H d, e
Table 2-24. Connection for Unused Pins (Cont’d)
Pins / Pin Grou ps Recommended
Connections Notes
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-1
Pinout Specifications 3
This chapter describes the Intel Itanium processor signals and the Intel Itanium processor cartridge
pinout. Please note that the “N/C” pins are reserved pins and must remain unconnected. The Intel
Itanium processor cartridge uses a JEDEC standard pin naming convention.
In this chapter, pin names are the actual names given to each physical pin of the processor. System
bus signal names are the names associated with the functions of those pins. For those pins
associated with multi function s, their pin names and system bus signal names are not necessarily
identical.
Figure 3-1. Intel® Itanium™ Processor PAC418 Cartridge Pin Locations (Top View)
135791113151719212325272931333537
2468101214161820222426283032343638
GND PROCPRES#OUTEN N/C N/C GND AP1# A12# A18# A25# A27# A29# A31# A33# A35# A37# A39# A41# GND
AoooooooooooooooooooA
3.3V SMA0 PPODGD# N/C GND AP0# A11# A17# A23# A24# A26# A28# A30# A32# A34# A36# A38# A40# A43#
BoooooooooooooooooooB
3.3V SMA1 GND GND N/C GND GND GND GND GND GND GND GND GND GND GND GND GND A42#
CoooooooooooooooooooC
SMWP SMA2 N/C IGNNE# GND A06# A10# A16# A22# D31# D29# D27# D25# DEP2# STBN1# D23# D21# D19# D17#
DoooooooooooooooooooD
SMSD VCTERM N/C VCTERM LINT1 GND GND GND GND VCTERM GND VCTERM GND VCTERM GND GND GND GND GND
EoooooooooooooooooooE
SMSC N/C THERMTRIP#LINT0 GND A05# A09# A15# A21# D30# D28# D26# D24# DEP3# STBP1# D22# D20# D18# D16#
FoooooooooooooooooooF
GND THRMALERT# GND GND N/C GND GND GND GND VCTERM GND VCTERM GND VCTERM GND GND GND GND GND
GoooooooooooooooooooG
N/C PD0 N/C A20M# GND A04# A08# A14# A20# D15# D13# D11# D09# STBP0# DEP1# D07# D05# D03# D01#
HoooooooooooooooooooH
N/C VCTERM N/C VCTERM FERR# GND GND GND GND VCTERM GND VCTERM GND VCTERM GND GND GND GND GND
JoooooooooooooooooooJ
N/C N/C N/C N/C GND A03# A07# A13# A19# D14# D12# D10# D08# STBN0# DEP0# D06# D04# D02# D00#
KoooooooooooooooooooK
GND N/C GND N/C GND GND GND GND GND VREFDR1 GND VREFDR0 GND VREFA1 GND VREFA0 GND GND GND
LoooooooooooooooooooL
GND N/C GND N/C GND BR2# DBSY# DRDY# REQ1# VREFDL1 GND VREFDL0 GND VREFC1 GND VREFC0 GND GND GND
ADoooooooooooooooooooAD
N/C N/C TRISTATE# N/C HITM# HIT# REQ4# DEFER# TRDY# D48# D50# D52# D54# STBN3# DEP7# D56# D58# D60# D62#
AEoooooooooooooooooooAE
PD1 VCTERM N/C VCTERM GND GND GND GND GND VCTERM GND VCTERM GND VCTERM GND GND GND GND GND
AFoooooooooooooooooooAF
N/C N/C TRST# N/C BR0# REQ3# RS2# LOCK# ADS# D49# D51# D53# D55# STBP3# DEP6# D57# D59# D61# D63#
AGoooooooooooooooooooAG
GND N/C GND PMI# GND GND GND GND GND VCTERM GND VCTERM GND VCTERM GND GND GND GND GND
AHoooooooooooooooooooAH
TUNER2 N/C TDI N/C BR1# RSP# RS0# REQ0# BNR# D32# D34# D36# D38# DEP4# STBP2# D40# D42# D44# D46#
AJoooooooooooooooooooAJ
PD2 VCTERM N/C VCTERM GND GND GND GND GND VCTERM GND VCTERM GND VCTERM GND GND GND GND GND
AKoooooooooooooooooooAK
TUNER1 N/C TDO N/C BR3# RP# REQ2# BPRI# BERR# D33# D35# D37# D39# DEP5# STBN2# D41# D43# D45# D47#
ALoooooooooooooooooooAL
PD3 N/C GND TMS GND GND GND GND GND GND GND GND GND GND GND GND GND GND BCLKN
AMoooooooooooooooooooAM
N/C N/C TCK N/C PU0 RS1# BINIT# RESET# GSEQ# BPM4# BPM2# BPM0# IDS ID6 ID4 ID2 SBSY# DRATE# BCLKP
ANoooooooooooooooooooAN
GND PU1 PWRGOOD INIT# GND PU2 GND GND GND BPM5# BPM3# BPM1# TND# ID7 ID5 ID3 ID1 ID0 GND
APoooooooooooooooooooAP
2468101214161820222426283032343638
135791113151719212325272931333537
Power Pod
Pinout Specifications
3-2 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
Table 3-1. Pin/Signal Information Sorted by Pin Name
Pin Name System Bus Signal Name Pin Location Input/Output
3.3V C01 IN
3.3V B02 IN
A03# AA03#/EXF0#/DPS# K12 IN/OUT
A04# AA04#/EXF1#/DEN# H12 IN/OUT
A05# AA05#/EXF2#/OWN# F12 IN/OUT
A06# AA06#/EXF3#/FCL#/SPLCK# D12 IN/OUT
A07# AA07#/EXF4# K14 IN/OUT
A08# AA08#/BE0# H14 IN/OUT
A09# AA09#/BE1# F14 IN/OUT
A10# AA10#/BE2# D14 IN/OUT
A11# AA11#/BE3# B14 IN/OUT
A12# AA12#/BE4# A15 IN/OUT
A13# AA13#/BE5# K16 IN/OUT
A14# AA14#/BE6# H16 IN/OUT
A15# AA15#/BE7# F16 IN/OUT
A16# AA16#/DID0# D16 IN/OUT
A17# AA17#/DID1# B16 IN/OUT
A18# AA18#/DID2# A17 IN/OUT
A19# AA19#/DID3# K18 IN/OUT
A20# AA20#/DID4# H18 IN/OUT
A20M# A20M# H08 IN
A21# AA21#/DID5# F18 IN/OUT
A22# AA22#/DID6# D18 IN/OUT
A23# AA23#/DID7# B18 IN/OUT
A24# AA24#/ATTR0# B20 IN/OUT
A25# AA25#/ATTR1# A19 IN/OUT
A26# AA26#/ATTR2# B22 IN/OUT
A27# AA27#/ATTR3# A21 IN/OUT
A28# AA28#/ATTR4# B24 IN/OUT
A29# AA29#/ATTR5# A23 IN/OUT
A30# AA30#/ATTR6# B26 IN/OUT
A31# AA31#/ATTR7# A25 IN/OUT
A32# AA32#/AB32# B28 IN/OUT
A33# AA33#/AB33# A27 IN/OUT
A34# AA34#/AB34# B30 IN/OUT
A35# AA35#/AB35# A29 IN/OUT
A36# AA36#/AB36# B32 IN/OUT
A37# AA37#/AB37# A31 IN/OUT
A38# AA38#/AB38# B34 IN/OUT
A39# AA39#/AB39# A33 IN/OUT
A40# AA40#/AB40# B36 IN/OUT
A41# AA41#/AB41# A35 IN/OUT
A42# AA42#/AB42# C37 IN/OUT
A43# AA43#/AB43# B38 IN/OUT
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-3
Pinout Specifications
ADS# ADS# AG18 IN/OUT
AP0# AP0# B12 IN/OUT
AP1# AP1# A13 IN/OUT
BCLKN BCLKN AM37 IN
BCLKP BCLKP AN38 IN
BERR# BERR# AL18 IN/OUT
BINIT# BINIT# AN14 IN/OUT
BNR# BNR# AJ18 IN/OUT
BPM0# BPM0# AN24 IN/OUT
BPM1# BPM1# AP23 IN/OUT
BPM2# BPM2# AN22 IN/OUT
BPM3# BPM3# AP21 IN/OUT
BPM4# BPM4# AN20 IN/OUT
BPM5# BPM5# AP19 IN/OUT
BPRI# BPRI# AL16 IN
BR0# BREQ0# AG10 IN/OUT
BR1# BREQ1# AJ10 IN
BR2# BREQ2# AD11 IN
BR3# BREQ3# AL10 IN
D00# D00# K38 IN/OUT
D01# D01# H38 IN/OUT
D02# D02# K36 IN/OUT
D03# D03# H36 IN/OUT
D04# D04# K34 IN/OUT
D05# D05# H34 IN/OUT
D06# D06# K32 IN/OUT
D07# D07# H32 IN/OUT
D08# D08# K26 IN/OUT
D09# D09# H26 IN/OUT
D10# D10# K24 IN/OUT
D11# D11# H24 IN/OUT
D12# D12# K22 IN/OUT
D13# D13# H22 IN/OUT
D14# D14# K20 IN/OUT
D15# D15# H20 IN/OUT
D16# D16# F38 IN/OUT
D17# D17# D38 IN/OUT
D18# D18# F36 IN/OUT
D19# D19# D36 IN/OUT
D20# D20# F34 IN/OUT
D21# D21# D34 IN/OUT
D22# D22# F32 IN/OUT
D23# D23# D32 IN/OUT
D24# D24# F26 IN/OUT
D25# D25# D26 IN/OUT
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-4 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
D26# D26# F24 IN/OUT
D27# D27# D24 IN/OUT
D28# D28# F22 IN/OUT
D29# D29# D22 IN/OUT
D30# D30# F20 IN/OUT
D31# D31# D20 IN/OUT
D32# D32# AJ20 IN/OUT
D33# D33# AL20 IN/OUT
D34# D34# AJ22 IN/OUT
D35# D35# AL22 IN/OUT
D36# D36# AJ24 IN/OUT
D37# D37# AL24 IN/OUT
D38# D38# AJ26 IN/OUT
D39# D39# AL26 IN/OUT
D40# D40# AJ32 IN/OUT
D41# D41# AL32 IN/OUT
D42# D42# AJ34 IN/OUT
D43# D43# AL34 IN/OUT
D44# D44# AJ36 IN/OUT
D45# D45# AL36 IN/OUT
D46# D46# AJ38 IN/OUT
D47# D47# AL38 IN/OUT
D48# D48# AE20 IN/OUT
D49# D49# AG20 IN/OUT
D50# D50# AE22 IN/OUT
D51# D51# AG22 IN/OUT
D52# D52# AE24 IN/OUT
D53# D53# AG24 IN/OUT
D54# D54# AE26 IN/OUT
D55# D55# AG26 IN/OUT
D56# D56# AE32 IN/OUT
D57# D57# AG32 IN/OUT
D58# D58# AE34 IN/OUT
D59# D59# AG34 IN/OUT
D60# D60# AE36 IN/OUT
D61# D61# AG36 IN/OUT
D62# D62# AE38 IN/OUT
D63# D63# AG38 IN/OUT
DBSY# DBSY# AD13 IN/OUT
DEFER# DEFER# AE16 IN
DEP0# DEP0# K30 IN/OUT
DEP1# DEP1# H30 IN/OUT
DEP2# DEP2# D28 IN/OUT
DEP3# DEP3# F28 IN/OUT
DEP4# DEP4# AJ28 IN/OUT
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-5
Pinout Specifications
DEP5# DEP5# AL28 IN/OUT
DEP6# DEP6# AG30 IN/OUT
DEP7# DEP7# AE30 IN/OUT
DRATE# DRATE# AN36 IN
DRDY# DRDY# AD15 IN/OUT
FERR# FERR# J09 OUT
GND GND A11 IN
GND GND B10 IN
GND GND A01 IN
GND GND C05 IN
GND GND C07 IN
GND GND C11 IN
GND GND C13 IN
GND GND C15 IN
GND GND C17 IN
GND GND C19 IN
GND GND C21 IN
GND GND C23 IN
GND GND C25 IN
GND GND C27 IN
GND GND C29 IN
GND GND C31 IN
GND GND C33 IN
GND GND C35 IN
GND GND A37 IN
GND GND D10 IN
GND GND E11 IN
GND GND E13 IN
GND GND E15 IN
GND GND E17 IN
GND GND E21 IN
GND GND E25 IN
GND GND E29 IN
GND GND E31 IN
GND GND E33 IN
GND GND E35 IN
GND GND E37 IN
GND GND F10 IN
GND GND G01 IN
GND GND G05 IN
GND GND G07 IN
GND GND G11 IN
GND GND G13 IN
GND GND G15 IN
GND GND G17 IN
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-6 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
GND GND G21 IN
GND GND G25 IN
GND GND G29 IN
GND GND G31 IN
GND GND G33 IN
GND GND G35 IN
GND GND G37 IN
GND GND H10 IN
GND GND J11 IN
GND GND J13 IN
GND GND J15 IN
GND GND J17 IN
GND GND J21 IN
GND GND J25 IN
GND GND J29 IN
GND GND J31 IN
GND GND J33 IN
GND GND J35 IN
GND GND J37 IN
GND GND K10 IN
GND GND L01 IN
GND GND L05 IN
GND GND L09 IN
GND GND L11 IN
GND GND L13 IN
GND GND L15 IN
GND GND L17 IN
GND GND L21 IN
GND GND L25 IN
GND GND L29 IN
GND GND L33 IN
GND GND L35 IN
GND GND L37 IN
GND GND AD01 IN
GND GND AD05 IN
GND GND AD09 IN
GND GND AD21 IN
GND GND AD25 IN
GND GND AD29 IN
GND GND AD33 IN
GND GND AD35 IN
GND GND AD37 IN
GND GND AF09 IN
GND GND AF11 IN
GND GND AF13 IN
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-7
Pinout Specifications
GND GND AF15 IN
GND GND AF17 IN
GND GND AF21 IN
GND GND AF25 IN
GND GND AF29 IN
GND GND AF31 IN
GND GND AF33 IN
GND GND AF35 IN
GND GND AF37 IN
GND GND AH01 IN
GND GND AH05 IN
GND GND AH09 IN
GND GND AH11 IN
GND GND AH13 IN
GND GND AH15 IN
GND GND AH17 IN
GND GND AH21 IN
GND GND AH25 IN
GND GND AH29 IN
GND GND AH31 IN
GND GND AH33 IN
GND GND AH35 IN
GND GND AH37 IN
GND GND AK09 IN
GND GND AK11 IN
GND GND AK13 IN
GND GND AK15 IN
GND GND AK17 IN
GND GND AK21 IN
GND GND AK25 IN
GND GND AK29 IN
GND GND AK31 IN
GND GND AK33 IN
GND GND AK35 IN
GND GND AK37 IN
GND GND AP01 IN
GND GND AM05 IN
GND GND AM09 IN
GND GND AM11 IN
GND GND AM13 IN
GND GND AM15 IN
GND GND AM17 IN
GND GND AM19 IN
GND GND AM21 IN
GND GND AM23 IN
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-8 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
GND GND AM25 IN
GND GND AM27 IN
GND GND AM29 IN
GND GND AM31 IN
GND GND AM33 IN
GND GND AM35 IN
GND GND AP37 IN
GND GND AP09 IN
GND GND AP13 IN
GND GND AP15 IN
GND GND AP17 IN
GSEQ# GSEQ# AN18 IN
HIT# HIT# AE12 IN/OUT
HITM# HITM# AE10 IN/OUT
ID0# IDA0#/IP0# AP35 IN
ID1# IDA1#/IP1# AP33 IN
ID2# IDA2#/DHIT# AN32 IN
ID3# IDA3#/IDB3# AP31 IN
ID4# IDA4#/IDB4# AN30 IN
ID5# IDA5#/IDB5# AP29 IN
ID6# IDA6#/IDB6# AN28 IN
ID7# IDA7#/IDB7# AP27 IN
IDS# IDS# AN26 IN
IGNNE# IGNNE# D08 IN
INIT# INIT# AP07 IN
LINT0 INT F08 IN
LINT1 NMI E09 IN
LOCK# LOCK# AG16 IN/OUT
N/C A07
N/C A09
N/C AM03
N/C AD03
N/C AE02
N/C AF05
N/C AG02
N/C AH03
N/C J05
N/C F04
N/C AN02
N/C B08
N/C C09
N/C D06
N/C E05
N/C G09
N/C H02
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-9
Pinout Specifications
N/C H06
N/C J01
N/C K02
N/C K04
N/C K06
N/C K08
N/C L03
N/C L07
N/C AD07
N/C AE04
N/C AE08
N/C AG04
N/C AG08
N/C AJ04
N/C AJ08
N/C AK05
N/C AL04
N/C AL08
N/C AN04
N/C AN08
OUTEN OUTEN A05 IN
PD0 H04
PD1 AF01
PD2 AK01
PD3 AM01
PMI# PMI# AH07 IN
PPODGD# PPODGD# B06 OUT
PROCPRES# CPUPRES# A03 OUT
PU0 AN10
PU1 AP03
PU2 AP11
PWRGOOD PWRGOOD AP05 IN
REQ0# REQA0#/LEN0# AJ16 IN/OUT
REQ1# WSNP#, D/C#/LEN1# AD17 IN/OUT
REQ2# REQA2#/ REQB2# AL14 IN/OUT
REQ3# ASZ0#/DSZ0# AG12 IN/OUT
REQ4# ASZ1#/DSZ1# AE14 IN/OUT
RESET# RESET# AN16 IN
RP# RP# AL12 IN/OUT
RS0# RS0# AJ14 IN
RS1# RS1# AN12 IN
RS2# RS2# AG14 IN
RSP# RSP# AJ12 IN
SBSY# SBSY# AN34 IN/OUT
SMA0 SMA0 B04 IN
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-10 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
SMA1 SMA1 C03 IN
SMA2 SMA2 D04 IN
SMSC SMSC F02 IN
SMSD SMSD E01 IN/OUT
SMWP SMWP D02 IN
STBN0# STBN0# K28 IN/OUT
STBN1# STBN1# D30 IN/OUT
STBN2# STBN2# AL30 IN/OUT
STBN3# STBN3# AE28 IN/OUT
STBP0# STBP0# H28 IN/OUT
STBP1# STBP1# F30 IN/OUT
STBP2# STBP2# AJ30 IN/OUT
STBP3# STBP3# AG28 IN/OUT
TCK TCK AN06 IN
TDI TDI AJ06 IN
TDO TDO AL06 OUT
THERMTRIP# THERMTRIP# F06 OUT
THRMALERT# THRMALERT# G03 OUT
TMS TMS AM07 IN
TND# TND# AP25 IN/OUT
TRDY# TRDY# AE18 IN
TRISTATE# TRISTATE# AE06 IN
TRST# TRST# AG06 IN
TUNER1 AL02 IN
TUNER2 AJ02 IN
VCTERM VCTERM E03 IN
VCTERM VCTERM E07 IN
VCTERM VCTERM E19 IN
VCTERM VCTERM E23 IN
VCTERM VCTERM E27 IN
VCTERM VCTERM G19 IN
VCTERM VCTERM G23 IN
VCTERM VCTERM G27 IN
VCTERM VCTERM J03 IN
VCTERM VCTERM J07 IN
VCTERM VCTERM J19 IN
VCTERM VCTERM J23 IN
VCTERM VCTERM J27 IN
VCTERM VCTERM AF03 IN
VCTERM VCTERM AF07 IN
VCTERM VCTERM AF19 IN
VCTERM VCTERM AF23 IN
VCTERM VCTERM AF27 IN
VCTERM VCTERM AH19 IN
VCTERM VCTERM AH23 IN
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-11
Pinout Specifications
VCTERM VCTERM AH27 IN
VCTERM VCTERM AK03 IN
VCTERM VCTERM AK07 IN
VCTERM VCTERM AK19 IN
VCTERM VCTERM AK23 IN
VCTERM VCTERM AK27 IN
VREFA0 L31 IN
VREFA1 L27 IN
VREFC0 AD31 IN
VREFC1 AD27 IN
VREFDL0 AD23 IN
VREFDL1 AD19 IN
VREFDR0 L23 IN
VREFDR1 L19 IN
Table 3-2. Pin/Signa l Information Sorted by Pin Location
Pin Name System Bus Signal Name Pin Location Input/Output
GND GND A01 IN
PROCPRES# CPUPRES# A03 OUT
OUTEN OUTEN A05 IN
N/C A07
N/C A09
GND GND A11 IN
AP1# AP1# A13 IN/OUT
A12# AA12#/BE4# A15 IN/OUT
A18# AA18#/DID2# A17 IN/OUT
A25# AA25#/ATTR1# A19 IN/OUT
A27# AA27#/ATTR3# A21 IN/OUT
A29# AA29#/ATTR5# A23 IN/OUT
A31# AA31#/ATTR7# A25 IN/OUT
A33# AA33#/AB33# A27 IN/OUT
A35# AA35#/AB35# A29 IN/OUT
A37# AA37#/AB37# A31 IN/OUT
A39# AA39#/AB39# A33 IN/OUT
A41# AA41#/AB41# A35 IN/OUT
GND GND A37 IN
3.3V B02 IN
SMA0 SMA0 B04 IN
PPODGD# PPODGD# B06 OUT
N/C B08
GND GND B10 IN
AP0# AP0# B12 IN/OUT
A11# AA11#/BE3# B14 IN/OUT
A17# AA17#/DID1# B16 IN/OUT
Table 3-1. Pin/Signal Information Sorted by Pin Name (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-12 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
A23# AA23#/DID7# B18 IN/OUT
A24# AA24#/ATTR0# B20 IN/OUT
A26# AA26#/ATTR2# B22 IN/OUT
A28# AA28#/ATTR4# B24 IN/OUT
A30# AA30#/ATTR6# B26 IN/OUT
A32# AA32#/AB32# B28 IN/OUT
A34# AA34#/AB34# B30 IN/OUT
A36# AA36#/AB36# B32 IN/OUT
A38# AA38#/AB38# B34 IN/OUT
A40# AA40#/AB40# B36 IN/OUT
A43# AA43#/AB43# B38 IN/OUT
3.3V C01 IN
SMA1 SMA1 C03 IN
GND GND C05 IN
GND GND C07 IN
N/C C09
GND GND C11 IN
GND GND C13 IN
GND GND C15 IN
GND GND C17 IN
GND GND C19 IN
GND GND C21 IN
GND GND C23 IN
GND GND C25 IN
GND GND C27 IN
GND GND C29 IN
GND GND C31 IN
GND GND C33 IN
GND GND C35 IN
A42# AA42#/AB42# C37 IN/OUT
SMWP SMWP D02 IN
SMA2 SMA2 D04 IN
N/C D06
IGNNE# IGNNE# D08 IN
GND GND D10 IN
A06# AA06#/EXF3#/FCL#/SPLCK# D12 IN/OUT
A10# AA10#/BE2# D14 IN/OUT
A16# AA16#/DID0# D16 IN/OUT
A22# AA22#/DID6# D18 IN/OUT
D31# D31# D20 IN/OUT
D29# D29# D22 IN/OUT
D27# D27# D24 IN/OUT
D25# D25# D26 IN/OUT
DEP2# DEP2# D28 IN/OUT
STBN1# STBN1# D30 IN/OUT
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-13
Pinout Specifications
D23# D23# D32 IN/OUT
D21# D21# D34 IN/OUT
D19# D19# D36 IN/OUT
D17# D17# D38 IN/OUT
SMSD SMSD E01 IN/OUT
VCTERM VCTERM E03 IN
N/C E05
VCTERM VCTERM E07 IN
LINT1 NMI E09 IN
GND GND E11 IN
GND GND E13 IN
GND GND E15 IN
GND GND E17 IN
VCTERM VCTERM E19 IN
GND GND E21 IN
VCTERM VCTERM E23 IN
GND GND E25 IN
VCTERM VCTERM E27 IN
GND GND E29 IN
GND GND E31 IN
GND GND E33 IN
GND GND E35 IN
GND GND E37 IN
SMSC SMSC F02 IN
N/C F04
THERMTRIP# THERMTRIP# F06 OUT
LINT0 INT F08 IN
GND GND F10 IN
A05# AA05#/EXF2#/OWN# F12 IN/OUT
A09# AA09#/BE1# F14 IN/OUT
A15# AA15#/BE7# F16 IN/OUT
A21# AA21#/DID5# F18 IN/OUT
D30# D30# F20 IN/OUT
D28# D28# F22 IN/OUT
D26# D26# F24 IN/OUT
D24# D24# F26 IN/OUT
DEP3# DEP3# F28 IN/OUT
STBP1# STBP1# F30 IN/OUT
D22# D22# F32 IN/OUT
D20# D20# F34 IN/OUT
D18# D18# F36 IN/OUT
D16# D16# F38 IN/OUT
GND GND G01 IN
THRMALERT# THRMALERT# G03 OUT
GND GND G05 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-14 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
GND GND G07 IN
N/C G09
GND GND G11 IN
GND GND G13 IN
GND GND G15 IN
GND GND G17 IN
VCTERM VCTERM G19 IN
GND GND G21 IN
VCTERM VCTERM G23 IN
GND GND G25 IN
VCTERM VCTERM G27 IN
GND GND G29 IN
GND GND G31 IN
GND GND G33 IN
GND GND G35 IN
GND GND G37 IN
N/C H02
PD0 H04
N/C H06
A20M# A20M# H08 IN
GND GND H10 IN
A04# AA04#/EXF1#/DEN# H12 IN/OUT
A08# AA08#/BE0# H14 IN/OUT
A14# AA14#/BE6# H16 IN/OUT
A20# AA20#/DID4# H18 IN/OUT
D15# D15# H20 IN/OUT
D13# D13# H22 IN/OUT
D11# D11# H24 IN/OUT
D09# D09# H26 IN/OUT
STBP0# STBP0# H28 IN/OUT
DEP1# DEP1# H30 IN/OUT
D07# D07# H32 IN/OUT
D05# D05# H34 IN/OUT
D03# D03# H36 IN/OUT
D01# D01# H38 IN/OUT
N/C J01
VCTERM VCTERM J03 IN
N/C J05
VCTERM VCTERM J07 IN
FERR# FERR# J09 OUT
GND GND J11 IN
GND GND J13 IN
GND GND J15 IN
GND GND J17 IN
VCTERM VCTERM J19 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-15
Pinout Specifications
GND GND J21 IN
VCTERM VCTERM J23 IN
GND GND J25 IN
VCTERM VCTERM J27 IN
GND GND J29 IN
GND GND J31 IN
GND GND J33 IN
GND GND J35 IN
GND GND J37 IN
N/C K02
N/C K04
N/C K06
N/C K08
GND GND K10 IN
A03# AA03#/EXF0#/DPS# K12 IN/OUT
A07# AA07#/EXF4# K14 IN/OUT
A13# AA13#/BE5# K16 IN/OUT
A19# AA19#/DID3# K18 IN/OUT
D14# D14# K20 IN/OUT
D12# D12# K22 IN/OUT
D10# D10# K24 IN/OUT
D08# D08# K26 IN/OUT
STBN0# STBN0# K28 IN/OUT
DEP0# DEP0# K30 IN/OUT
D06# D06# K32 IN/OUT
D04# D04# K34 IN/OUT
D02# D02# K36 IN/OUT
D00# D00# K38 IN/OUT
GND GND L01 IN
N/C L03
GND GND L05 IN
N/C L07
GND GND L09 IN
GND GND L11 IN
GND GND L13 IN
GND GND L15 IN
GND GND L17 IN
VREFDR1 L19 IN
GND GND L21 IN
VREFDR0 L23 IN
GND GND L25 IN
VREFA1 L27 IN
GND GND L29 IN
VREFA0 L31 IN
GND GND L33 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-16 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
GND GND L35 IN
GND GND L37 IN
GND GND AD01 IN
N/C AD03
GND GND AD05 IN
N/C AD07
GND GND AD09 IN
BR2# BREQ2# AD11 IN
DBSY# DBSY# AD13 IN/OUT
DRDY# DRDY# AD15 IN/OUT
REQ1# WSNP#, D/C# /L EN1# AD17 IN/OUT
VREFDL1 AD19 IN
GND GND AD21 IN
VREFDL0 AD23 IN
GND GND AD25 IN
VREFC1 AD27 IN
GND GND AD29 IN
VREFC0 AD31 IN
GND GND AD33 IN
GND GND AD35 IN
GND GND AD37 IN
N/C AE02
N/C AE04
TRISTATE# TRISTATE# AE06 IN
N/C AE08
HITM# HITM# AE10 IN/OUT
HIT# HIT# AE12 IN/OUT
REQ4# ASZ1#/DSZ1# AE14 IN/OUT
DEFER# DEFER# AE16 IN
TRDY# TRDY# AE18 IN
D48# D48# AE20 IN/OUT
D50# D50# AE22 IN/OUT
D52# D52# AE24 IN/OUT
D54# D54# AE26 IN/OUT
STBN3# STBN3# AE28 IN/OUT
DEP7# DEP7# AE30 IN/OUT
D56# D56# AE32 IN/OUT
D58# D58# AE34 IN/OUT
D60# D60# AE36 IN/OUT
D62# D62# AE38 IN/OUT
PD1 AF01
VCTERM VCTERM AF03 IN
N/C AF05
VCTERM VCTERM AF07 IN
GND GND AF09 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-17
Pinout Specifications
GND GND AF11 IN
GND GND AF13 IN
GND GND AF15 IN
GND GND AF17 IN
VCTERM VCTERM AF19 IN
GND GND AF21 IN
VCTERM VCTERM AF23 IN
GND GND AF25 IN
VCTERM VCTERM AF27 IN
GND GND AF29 IN
GND GND AF31 IN
GND GND AF33 IN
GND GND AF35 IN
GND GND AF37 IN
N/C AG02
N/C AG04
TRST# TRST# AG06 IN
N/C AG08
BR0# BREQ0# AG10 IN/OUT
REQ3# ASZ0#/DSZ0# AG12 IN/OUT
RS2# RS2# AG14 IN
LOCK# LOCK# AG16 IN/OUT
ADS# ADS# AG18 IN/OUT
D49# D49# AG20 IN/OUT
D51# D51# AG22 IN/OUT
D53# D53# AG24 IN/OUT
D55# D55# AG26 IN/OUT
STBP3# STBP3# AG28 IN/OUT
DEP6# DEP6# AG30 IN/OUT
D57# D57# AG32 IN/OUT
D59# D59# AG34 IN/OUT
D61# D61# AG36 IN/OUT
D63# D63# AG38 IN/OUT
GND GND AH01 IN
N/C AH03
GND GND AH05 IN
PMI# PMI# AH07 IN
GND GND AH09 IN
GND GND AH11 IN
GND GND AH13 IN
GND GND AH15 IN
GND GND AH17 IN
VCTERM VCTERM AH19 IN
GND GND AH21 IN
VCTERM VCTERM AH23 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-18 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
GND GND AH25 IN
VCTERM VCTERM AH27 IN
GND GND AH29 IN
GND GND AH31 IN
GND GND AH33 IN
GND GND AH35 IN
GND GND AH37 IN
TUNER2 AJ02 IN
N/C AJ04 IN
TDI TDI AJ06 IN
N/C AJ08
BR1# BREQ1# AJ10 IN
RSP# RSP# AJ12 IN
RS0# RS0# AJ14 IN
REQ0# REQA0#/LEN0# AJ16 IN/OUT
BNR# BNR# AJ18 IN/OUT
D32# D32# AJ20 IN/OUT
D34# D34# AJ22 IN/OUT
D36# D36# AJ24 IN/OUT
D38# D38# AJ26 IN/OUT
DEP4# DEP4# AJ28 IN/OUT
STBP2# STBP2# AJ30 IN/OUT
D40# D40# AJ32 IN/OUT
D42# D42# AJ34 IN/OUT
D44# D44# AJ36 IN/OUT
D46# D46# AJ38 IN/OUT
PD2 AK01
VCTERM VCTERM AK03 IN
N/C AK05
VCTERM VCTERM AK07 IN
GND GND AK09 IN
GND GND AK11 IN
GND GND AK13 IN
GND GND AK15 IN
GND GND AK17 IN
VCTERM VCTERM AK19 IN
GND GND AK21 IN
VCTERM VCTERM AK23 IN
GND GND AK25 IN
VCTERM VCTERM AK27 IN
GND GND AK29 IN
GND GND AK31 IN
GND GND AK33 IN
GND GND AK35 IN
GND GND AK37 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 3-19
Pinout Specifications
TUNER1 AL02
N/C AL04
TDO TDO AL06 OUT
N/C AL08
BR3# BREQ3# AL10 IN
RP# RP# AL12 IN/OUT
REQ2# REQA2#/ REQB2# AL14 I N/OUT
BPRI# BPRI# AL16 IN
BERR# BERR# AL18 IN/OUT
D33# D33# AL20 IN/OUT
D35# D35# AL22 IN/OUT
D37# D37# AL24 IN/OUT
D39# D39# AL26 IN/OUT
DEP5# DEP5# AL28 IN/OUT
STBN2# STBN2# AL30 IN/OUT
D41# D41# AL32 IN/OUT
D43# D43# AL34 IN/OUT
D45# D45# AL36 IN/OUT
D47# D47# AL38 IN/OUT
PD3 AM01
N/C AM03
GND GND AM05 IN
TMS TMS AM07 IN
GND GND AM09 IN
GND GND AM11 IN
GND GND AM13 IN
GND GND AM15 IN
GND GND AM17 IN
GND GND AM19 IN
GND GND AM21 IN
GND GND AM23 IN
GND GND AM25 IN
GND GND AM27 IN
GND GND AM29 IN
GND GND AM31 IN
GND GND AM33 IN
GND GND AM35 IN
BCLKN BCLKN AM37 IN
N/C AN02
N/C AN04
TCK TCK AN06 IN
N/C AN08
PU0 AN10
RS1# RS1# AN12 IN
BINIT# BINIT# AN14 IN/OUT
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Pinout Specifications
3-20 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
RESET# RESET# AN16 IN
GSEQ# GSEQ# AN18 IN
BPM4# BPM4# AN20 IN/OUT
BPM2# BPM2# AN22 IN/OUT
BPM0# BPM0# AN24 IN/OUT
IDS# IDS# AN26 IN
ID6# IDA6#/IDB6# AN28 IN
ID4# IDA4#/IDB4# AN30 IN
ID2# IDA2#/DHIT# AN32 IN
SBSY# SBSY# AN34 IN/OUT
DRATE# DRATE# AN36 IN
BCLKP CLK AN38 IN
GND GND AP01 IN
PU1 AP03
PWRGOOD PWRGOOD AP05 IN
INIT# INIT# AP07 IN
GND GND AP09 IN
PU2 AP11
GND GND AP13 IN
GND GND AP15 IN
GND GND AP17 IN
BPM5# BPM5# AP19 IN/OUT
BPM3# BPM3# AP21 IN/OUT
BPM1# BPM1# AP23 IN/OUT
TND# TND# AP25 IN/OUT
ID7# IDA7#/IDB7# AP27 IN
ID5# IDA5#/IDB5# AP29 IN
ID3# IDA3#/IDB3# AP31 IN
ID1# IDA1#/IP1# AP33 IN
ID0# IDA0#/IP0# AP35 IN
GND GND AP37 IN
Table 3-2. Pin/Signal Information Sorted by Pin Location (Cont’d)
Pin Name System Bus Signal Name Pin Location Input/Output
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 4-1
Mechanical Specifications 4
This chapter provides the mechanical specifications of the Intel Itanium processor PAC418 (418
pin array cartridge) package.
4.1 Cartridge Features
The PAC418 package contains the Intel Itanium processor core, L3 cache, and other passive
components. The PAC418 cartridge connects to the motherboard through a PAC418 socket. The
Intel Itanium processor 4-MB and 2-MB cartridges have identical footprints and are mechanically
identical. The top of the cartridge is the thermal plate to which a coolin g solution is attached. This
side of the cartridge has two sets of holes, one set for retention mechanism attachment and another
set for cooling solution attachment. The bottom side of the cartridge contains the pin array, pin
shroud, and the alignment pegs/keys. One end of the cartridge has the power tab interface to
connect with the Power Pod. The other end of the cartridge has an identification label. Table 4-1
contains the dimensions for the PAC418 cartridge.
4.1.1 Cartridge Top Surface Features
Figure 4-1 shows the top view of the Intel Itanium processor PAC418 cartridge. The diagram
illustrates the cartridge cooling solution and retention mechanism attachment feature details on the
thermal plate (the retentio n mechanism is the mechanical compo nent designed to hold the s ocketed
processor and power pod to the baseboard and socket and the thermal plate is the surface used to
connect a heatsink or other thermal solution to the processor). Four holes with M2.5x0.45 threads
are used to attach the cartridge cooling solution to the thermally active region of the cartridge
which is represented by the hashed region in Figure 4-7. Please refer to Itanium™ Processor
Heatsink Guid elines for more information on the heatsink specifications.
Also shown in Figure 4-1 is the retention mechanism attachment through holes which are used to
interface with the mechanical support posts on the retention mechanism. Please refer to PAC418
Cartridge/Power Pod Retention Mechanism and Triple Beam Design Specifications for more
information on the retention mechanism . A plastic frame surrounds the sides of the cartridge and
the pin s hroud surro unds th e cartridge p ins. The po wer tab ( the power connec tor loca ted on one end
of the cartridge which connects to the power pod) is used to interface with the Power Pod which
supplies power to the components inside the PAC418 cartridge.
Mechanical Specifications
4-2 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
4.1.2 C artridge Bottom Surface Features
Figure 4-2 shows the bo ttom view of the PAC418 cartridg e. The cartr idge pins are s urrounded b y a
pin shroud which protects the pins. The shroud is taller than the PAC418 pins so the cartridge can
rest on t he shro ud without damage t o the pi n s. Two alignment p e gs/keys extend from the shroud to
ensure correct cartridge pin and socket alignment during the socketing process. The pegs/keys are
slightly offset with respect to one another and serve as a keying feature. Please refer to PAC418
VLIF Socket and Cartridge Ejector Design Specifications for more information on the pin shroud
and cartridge pin alignment.
Figure 4-1. Intel® Itanium™ Processor PAC418 Top Isometric View
000665a
Power Tab
hermal Plat e
Retentio n Me ch anis m
Attach Holes (4)
Frame
Pin Shroud
Thermal Solution
Attach Holes (4)
Figure 4-2. Intel® Itanium™ Processor PAC418 Bottom Isometric View
000666b
Pin Array
Package S pring C lip
Retention Mech anism
Attach Holes (4)
Ali gnm ent Peg/Key
Power Tab
Thermal Plate
Alignment Peg/Key
Pin Shroud
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 4-3
Mechanical Specifications
4.1.3 Power Connector
The Power Pod will deliver power to the PAC418 cartridge through the power tab. Figure 4-3
through Figure 4-8 illustrate the dimensions and char acteristics of the power tab area located on the
PAC418 cartridge substrate.
Figure 4-3. Power Tab Location on PAC418 Cartridge Substrate
Bottom view of substrate (cartridge body not shown for clarity).
Dimensions are in millimeters.
*Refer to Figure 4-7.
**Refer to Figure 4-8.000461
1.428 0.800 ±0.300
30° ±10°
30° ±10°
(1.300)
(0.650)
See Detail D**
(20.700)
See Detail C*
(2.920)
(1.000)
(2.480)
Mechanical Specifications
4-4 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
Figure 4-4. Power Tab Location on PAC418 Cartridge Substrate, Detail C
Dimensions are in millimeters. 000460a
12.564 ±0.130
( 1.300 ) 0.650
22.710 ±0.05
46.96 ±0.08
( 44.56 )
–E–
48.260+0.150, –0.300
2.540
6.240
( 3.700 )
Detail C
2X 30° ±10°
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 4-5
Mechanical Specifications
4.2 Cartridge Mechanical Dimensions
Figure 4-6, Figure 4-7, and Figure 4-8 show the top, bottom, side, and both end views of the Intel
Itanium processor PAC418 cartridge. Figure 4-1 and Figure 4-2 show the top and bottom isometric
views of the cartridge with key features identified.
The following notes apply to Figure 4-6, Figure 4-7, and Figure 4-8. Unless otherwise specified:
1. Interpret dimensions and tolerances in accordance with ASME Y14.5M-1994.
2. Dimensions are in INCHES.
3. Tolerance: .XX±.01, .XXX±.005, Angles: ±3 degrees.
Table 4-1 contains detailed cartridge dimensions to be used in conjunction of Figure 4-6 through
Figure 4-8.
The following notes apply to Table 4-1 unless otherwise specified.
1. [ ] brackets signify a basic dimension, a dimension from which other dimensions are based.
2. ( ) brackets signify a reference dimension, a dimension that is used as reference information.
3. Dimensions that are not enclosed in brackets are actual dimensions with tolerances.
Figure 4-5. Power Tab Location on PAC418 Cartridge Substrate , Detail D
Dimensions are in millimeters. 000464
Detail D
1.150
0.430
20.700
19X 0 .86 0±0.050
20X 2.920±0.050
1.000 2.480±0.050
18X 1.150
Mechanical Specifications
4-6 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
Figure 4-6. Intel® Itanium™ Processor PAC418 Cartridge Mechanical Drawings (Sheet 1 of 3)
000817c
0.050
A
0.276 ± 0. 012
0.349
Substrate End to
Powe r Po d Hard Stop
Section F - F 0.5 03 ±0.007
0.698 ±0.012
(0.048) X
X
AA
2.864 ±0.010
F
Ø 0.010 M A
418X Ø 0.018 ±0.001
B M C M
0.197
(0.104)
1.315 ±0 .007 0.939 ±0.007
AA
2X
0.160
0.137
5.100 ± 0. 007
F
0.650
J
0.100
Bottom View
Side Vi ew
AA
Power Tab
Side Vi ew H
876543
D
C
B
876543
D
C
B
I
NOTE:
Indicated Dimensions are Referenced from Label Surface
I
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 4-7
Mechanical Specifications
Figure 4-7. Intel® Itanium™ Processor PAC418 Cartridge Mechanica l Drawings (Sheet 2 of 3)
000651c
Top View
Bo tto m V iew
Side View
Label Side View
4X (R0.125)
2X 0.071±0. 002
1.850
±0.012
2.305 ±0.010
2.612
2.510
3.948
0.386
2.093
4.746
0.100
3.221
0.836
0.964 3.349
View X - X
4.425 ±0.0 10
2X (Full Radius)
(0.042)
4X (R .144)
0.518
0.010
0.017
E
B
0.006 A
C
4X Ø 0.200
Ø 0.024 M A B M C M
Ø 0.010 M A
0.024 A E
2.060
1.900 +0.006
–0.012
Ø 0.010 M A H J
4X M 2.5 Insert
0.024 A E
2.125
Thermal Plate
Cooling
Solution
Attach Area
Entire Area
Indicated Area
(S e e c artri d ge m a r k diagram
in this chapter for details.)
1.490
1.766
0.330
765432
765432
A
B
C
D
A
B
C
D
I
NOTE:
Indicated Dimensions are Referenced from Label Surface
I
Mechanical Specifications
4-8 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
\
Figure 4-8. Intel® Itanium™ Processor PAC418 Cartridge Mechanical Drawings (Sheet 3 of 3)
000818a
DETAIL A
0.080
0.043 ± 0.012
0.056 ± 0.006
SUB THK
0.068
D
A
0.024 D
B
A
87
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 4-9
Mechanical Specifications
Table 4-1. Intel® Itanium™ Processor PAC418 Cartridge Dimensions
Dimension Description Drawing Location
(Sheet #- Coordinates) Value
(Inches) Metric Reference
Value (mm)
Cartridge Length (including label) 1 -B5 5.100±. 007 129.54±.18
Pin Protector Length (Outer) 2-C4 4.425±.010 112.40±.25
Cartridge Width 1-C3 2.864±.0010 72.75±.25
Pin Protector Widt h (Outer) 2-C2 2.305±.010 58.55±.25
Cartridge Thickness 1-B3 0.698±.012 17.73±.30
Body Thickness 1-A3 0.503±.007 12.78±.18
Cartridge RM Attach Hole Spacing
Length (Basic) 2-B4 [4.746] [120.55]
Cartridge RM Attach Hole Spacing
Width (Basic) 2-A3 [2.510] [63.75]
Cartridge RM Attach Hole Diameter 2-D3 0.200±.005 5.08±.13
Cartridge RM Attach Hole True
Position wrt Datums A, B, and C 2-D3 0.024 0.61
Cartridge RM Attach Hole True
Positi o n wrt Datum A 2-D3 0.010 0.25
Thermal Solution Attachment Insert
Thread Size (Reference) 2-B5 M2.5x0.45 M2.5x0.45
Thermal Solution Attachment Insert
True Position 2-B5 0.010 0.25
Maximum The rmal Solution Sc rew
Engagement Depth from Top Surface
of Cartridge (Reference)
(0.394) (10.01)
Pin Row Group Center Spacing
(Basic) 1-C6 [0.650] [16.51]
Pin Pitch Row to Row (Basic) 1-D6 [0.050] [1.27]
Pin Prot ector to Pin CL Spacing
(Reference) 1-D5 (0.104) (2.64)
Top Alignment Key to Pin Protector 1-D6 1.315± .007 33.40±.18
Top Alignment Key to Pin Protector
Feature 1-D4 0.939±.007 23.85±.18
Pin Pitch Within Row (Basic) 1-D5 [0.100] [2.54]
Pin Protector Wall Width 1-D5 0.197±.005 5.00±.13
Thermal Solution Attachment Hole to
RM Attach Hole (Basic) 2-B4 [1.490] [37.85]
Thermal Solution Attachment Hole
Spacing Length (Basic) 2-B5 [1.766] [44.86]
Thermal Solution Attachment Hole
Spacing Width (Basic) 2-A3 [2.612] [66.34]
Top Alignment Key to RM Attach Hole
(Basic) 2-D4 [3.221] [81.81]
Bottom Key to RM Attach Hole
(Basic) 2-C4 [3.349] [85.06]
Top Alignment Key to Pin 1 (Basic) 2-D4 [0.836] [21.23]
Bottom Alignment Key to Pin 1
(Basic) 2-C4 [0.964] [24.49]
Alignment Key Width 2-D7 0.071± .002 1.80±. 05
Alignment Key Width T rue Position 2-D7 0.006 .15
Alignment Key to RM Attach Hole
(Basic) 2-D3 [0.330] [8.38]
Alignment Key to Pin 1 (Basic) 2-D3 [0.100] [2.54]
Mechanical Specifications
4-10 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
Alignment Key to Alignment Key 2-D3 1. 850±.012 46.99±.30
Pin Diameter 1-D 4 0. 018±.001 0.46±.025
Pin Tip True Position 1-D4 0.010 0.25
Thermal Solution Attach Area Length
(Basic) 2-A5 [3.948] [100.28]
Thermal Solution Attach Area Width
(Basic) 2-A6 [2.093] [53.16]
Thermal Solution Attach Area Length
Offset (Basic) 2-A3 [0.518] [13.16]
Thermal Solution Attach Area Width
Offset (Basic) 2-A6 [0.386] [9.80]
Power Pod Connector Opening
Height wrt Datum A 1-B6 0.276±.012 7.01±.30
Power Pod Connector Opening Width 2-D7 2.125±. 005 53.98±.13
Power Pod Connector Opening Width
True Position 2-D7 0.024 0.61
Power Pod Connector Rail to Rail 2-C7 2.060±.005 52.32±.13
Power Pod Connector Rail wrt
Substrate True Position 2-C7 0.024 0.61
Power Tab Substrate Width 2-C6 1.900+.006,-.012 48.26+.15,-.30
Substrate End to Power Pod
Connector Hard Stop 1-A6 0.349±.005 8.86±.13
Cartridge Radius (Reference) 2-D6 (0.125) (3.18)
Pin Protector Radius (Reference) 2-C6 (0.144) (3.66)
Alignment Key Radius (Reference) 2-C5 Full Radius Full Radius
Pin Protector Wall Width (Reference) 2-C5 (0.042) (1.07)
Pin Length wrt Datum A (Max/Min) 1-B3 0.160/0.137 4.06/3.48
Pin Protector Height to Pin Tip
(Reference) 1-B3 (0.048) (1.22)
Cartridge Top Surface Flatness 2-A6 0.017 0.38
Cartridge Top Surface Thermal
Solution Attach Area Flatness 2-B6 0.010 0.25
Power Tab Substrate Thickness 3-B8 0.056±.006 1.42± .15
Datum D to Datum A (Basic) 3-B8 [0.068] [1.73]
Datum D to Datum A Profile
Tolerance 3-B7 0.024 0.61
Datum D to Power Pod Connector
Rail 3-B8 0.043±.012 1.09±.30
Power Pod Connector Rail Thickness 3-A7 0.080±.005 2.03±.13
Table 4-1. Inte l® Itanium™ Processor PAC418 Cartridge Dimensions (Cont’d)
Dimension Description Drawi ng Loc ation
(Sheet #- Coordinates) Value
(Inches) Metric Reference
Value (mm)
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 5-1
Thermal Specifications 5
This chapter provides a description of the thermal diode features and thermal data relating to the
Intel Itanium processor.
5.1 Thermal Circuit
The Intel Itanium processor has an internal thermal circuit which senses when a certain
temperature is reached on the die. This circuit is used for thermal trip. In addition, an on-chip
thermal diode is available for use by the thermal sensing device on the Intel Itanium processor
cartridge. Figure 5-1 highlights the relative po sitio n s o f the Intel Itanium processor thermal
features.
5.1.1 Thermal Alert
THRMALERT# is a programmable therm al alert signal which is one of the In tel Itanium processor
cartridge system management features. THRMALERT# is asserted when the measured
temperature from the processor thermal diode equals or exceeds the temperature threshold data
programmed in t he hi gh-temp (Thigh) register on the sensor (see Chapter 6 for more detail s). This
signal can be used by the platform to implement thermal regulation features such as generating an
external interrupt to tell the system management software that the processor core die temperature is
increasing.
Figure 5-1. Intel® Itanium™ Processor Thermal Features
000400
Die Temperature
Time
Thermal Alert
(Programmable temperature setting
through the system management bus.)
Thermal Trip
Thermal Specifications
5-2 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
5.1.2 Thermal Trip
The Intel Itanium processor protects itself from catastrophic overheating by use of an internal
thermal sensor. The sensor trip-p oint is set well ab ove th e normal operatin g temperature to ensure
that there are no false trips. The Intel Itanium pro cessor will stop all execution when the junction
temperature exceeds a safe operating level. Data will be lost if the Intel Itanium pr ocessor goes into
thermal trip (signaled to the system by the THRMTRIP# pin). Once thermal trip is activated, the
Intel Itanium processor remains stopped until RESET# is asserted. If the die temperatu r e has
dropped below the trip level, a RESET# pulse can be us ed to reset the processor. If the temperature
has not dropped below the trip level, the processor will continue to drive THRMTRIP# and remain
stopped.
5.2 Cartridge Thermal Specifications and
Considerations
This section lists th e thermal parameters of the Intel Itanium processo r cartridge. Systems should
be designed to dissipate a maximum power consumption of 130W from each Intel Itanium
processor cartridge.
5.2.1 Thermal Plate Temperature
To ensure functional and reliable Intel Itanium processor operation, the thermal plate temperature
(Tplate) must be maintain ed within the Tplate temperature specifications in Table 5-1.
5.2.2 Thermal Budget
All process or th ermal solutions should attach to the therm a l plate.
The thermal solutio n must adequately control the thermal plate temperature below the m a ximum
and above the minimum specified in Table 5-1. The performance of any thermal sol ution is defined
as the thermal resistance between the thermal plate and the ambient air around the processor (ΘPA).
The lower the thermal resistance between the thermal plate and the ambient air, the more efficient
the the r mal solut i o n. T he required ΘPA is dependent upon the maximum allowed thermal plate
temperature (Tplate), the local ambient temperature (TLA), and the maximum cartridge power
(PMAX).
ΘPA= (Tplate–TLA)/PMAX
Table 5-1. Inte l® Itanium™ Processor Thermal Design Specifications
Processor Core
Frequency
(MHz)
L3 Cache
Size (MB) Max Total Cartridge
Power (PMAX)Minimum Tplate (°C) Maximum Tplate (°C)
733 / 800 MHz 2 116.0W 5.0 66.0
4 130.0W 5.0 66.0
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 5-3
Ther mal Specifications
The ΘPA value is made up of two primar y com pon ents: the thermal res is tance between the thermal
plate and heatsink (ΘPA) and the thermal resistance between the heatsink and the ambient air
around the processor (ΘHA). One factor to consider in decreasing ΘPA is the thermal interface
between the thermal plate and the cooling solution. The other controllable factor (ΘHA) is resultant
in the design of the heatsink and airflow around the heatsink. Heatsink design constraints are also
provided in Itanium™ Processor Heatsink Guidelines.
The maximum Tplate and the thermal plate power are listed in Table 5-1. TLA is a function of the
syste m de s ig n. Table 5-2 provides the resultant thermal solution performance for a 733 MHz/
800 MHz Intel Itanium processor at different ambient air temperatures around the processor.
5.2.3 Cartridge Temperature Deviation
The maximum temperature deviation (∆TMAX) across the top surface of the cartridge in the
thermal active area is 10°C.
Figure 5-2. Processor Tplate Temperature Measurement Location
Top view of PAC418 cartridge shown.
All dimensions are shown in inches (millimeters).
For reference of Tplate measurement location only. 000685a
1.238
(31.445)
0.386
(9.804)
TPLATE Measurement Location 2.093
(53.162)
3.948
(100.279)
0.634
(16.104)
1.432
(36.373)
Power Pod
Connector Side
Table 5-2. Example Thermal Solution Performance for the 4MB Intel® Itanium™ Process or
Cartridge at Thermal Plate Power of 130W
Thermal Solution (Perform ance) Local Ambient Temperature (TLA)
35°C 40°C 45°C
ΘPA (°C/W) 0.24 0.20 0.16
Thermal Specifications
5-4 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 6-1
System Management Feature
Specifications 6
This Intel Itanium processor includes a System Management Bus (SMBus) interface. This chapter
describes the features of the SMBus and SMBus components.
6.1 System Management Features and Components
The Intel Itanium processor have sever a l built- in components to aid in the system m anage m e nt.
These components include a thermal sensor (digital thermometer), a Processor Information
EEPROM (PIROM) and a Scratch EEPROM as shown in Figure 6-1. The PIROM is programmed
by Intel with information specific to manufacturing and features of the Itanium processor cartr idge.
This information is permanently wr ite- protected. The Scratch EEPROM is available for the OEM
system designers to use at their discretion. The thermal sensor can be used in conjunction with the
information in the PIROM and/or the Scratch EEPROM for system th ermal m onito ring and
management. The thermal sensor on the cartridge provides an accurate means of acquiring the
relative junction temperature of the processor core die. The ther mal sensing dev ice is connected to
the anode and cathode of the processor’s on-die thermal diode .
Figure 6-1. System Manage ment Components on the Intel® Itanium™ Processor Cartridge
000401
On-die
Thermal
Diode
Processor Core
SMSC SMSD SMWP
Processor
Information
EEPROM
THRMALERT#
A/D
Scratch
EEPROM
Processor Cartridge
SMBus Connection to System Controller
System Management Feature Specifications
6-2 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
6.2 System Manag ement Interface
6.2.1 SMBus Signals
Table 6-1 lists the System Management Interface signals and their descriptions. These signals are
used by the system to access the system management components via the SMBus. The SMBus
implementation on the Itanium processor cartridge uses the clock and data signals of the SMBus
specifications in Table 2-16.
Figure 6-2 is a logical schematics of SMBus circuitry on the Intel Itanium processor cartridge and
shows how the various system management components are connected to the SMBus. The
reference to the System Board at the lower left corner of the figure shows how SMBus address
configuration for multiple Itanium processors can be realized with resistor stuffing options.
Note: Actual implem entation of SMBus on the OEM platform s may differ from this implem entation.
This figure is meant to be used in general understanding of the Itanium proces sor SMBus
architecture.
6.2.2 SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory components claim those of the form
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to VSS (‘0’) for the Scratch EEPRO M and
pulled to 3.3V (‘1’) for the Processor Information ROM. The “XX” bits are defined by the
processor slot via the SMA0 and SMA1 pins on the Intel Itanium processor cartridge connector.
These address pins are pulled down weakly (10 kΩ) to ensure that the memory components are in a
known state in systems which do not support the SMBus, or only support a partial implementation.
The “Z” bit is the read/write bit for the serial bus transactio n.
The thermal sensing device internally decodes one of three upper address patterns from the bus of
the form “0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The device’s addressing, as
implemented, uses SMA2 and SMA1 and includes a Hi-Z state for the SMA2 address pin.
Therefore the thermal sensing device supports six unique resulting addresses. To set the Hi-Z state
for SMA2, the pin must b e left floating. The system should drive SMA1 and SMA0, and will be
pulled lo w (if not d riven) by th e 10 kΩ pull-down resistor on the processor substrate. Attempting to
drive either of these signals to a Hi-Z state would cause ambiguity in the memory device address
decode, po ssibly re sulting i n the devices not respond ing, th us timing o ut or han ging the SM Bus. As
before, the “Z” bit is the read/write bit for the serial bus transaction.
Figure 6-2 shows a logical diagram of the pin connections. Table 6-2 and Table 6-3 describe the
address pin connections and how they affect the addressing of the devices.
Table 6-1. System Management Interface Signal Descriptions
Signal Name Pin Count Description
3.3V 2 Voltage supply for EEPROMs and thermal sensor
SMA[2:0] 3 S yst em Mana gement address bus
SMSC 1 System Management bus clock
SMSD 1 System Management serial address/data bus
SMWP 1 S crat ch EEP RO M write protect
THRMALERT# 1 Temperature alert from the thermal sensor
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 6-3
System Management Feature Specifications
Note: Addresses of the form “0000XXXXb” are Reserved and should not be generated by an SMBus
master. Also, system management software must be aware of the cartridge number-dependent
changes in the address for the thermal sensing device.
Figure 6-2. Logical Schematic of SMBus Circuitry
000580
Table 6-2. Thermal Sensing Device SMBus Addressing on the Intel® Itanium™ Processor
Cartridge
Address (Hex) Upper Addressa
a. Upper address b its a r e decoded in conjunction with th e select pins.
Cartridge Select 8-bit Address Word on Serial Bus
SMA1 SMA2 b[7:0]
3Xh 0011 0 0 0011000Xb
0011 1 0 0011010Xb
5Xh 0101 0 Zb
b. A t r i-s tate or “Z” state on this pin is achieved by leaving this pin unconnected.
0101001Xb
0101 1 Zb0101011Xb
9Xh 1001 0 1 1001100Xb
1001 1 1 1001110Xb
Processor
Information
ROM
A0
A1
A2
SC
SD
VCC
10K 10K
3.3V
Scratch
EEPROM
A0
A1
A2
SD
WP
VCC SC
10K
10K
10K
Thermal
Sensing
Device
VCC
A0
A1
SC
SD
STBY
ALERT
Itanium™ P rocesso r Cartrid ge
SMA0
SMA1
SMA23.3V SMSD
SMSC THRMALERT#
Stuffing
Options
3.3V
Core
THERMDA
THERMDC
System B o ard
Note:
Actual implementation may v ary. For us e in
general understanding of the architecture.
10K
SMWP
0.1µF1µF
10K
1µF
330
8
System Management Feature Specifications
6-4 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
6.3 PIROM and Scratch EEPROM
6.3.1 Processor Information ROM
An electrically programmed read-only memory provides information about the Intel Itanium
processor cartridge. The checksum bits for each category provide error correction and serve as a
mechanism to check whether data is corrupted or not. This informati on is p erman en tly write-
protected. Table 6-4 shows the data fields and formats provided in the memory.
Note: The data, in byte format, is written and read serially with the most significant bit first.
Table 6-3. EEPROM SMBus Addressing on the Intel® Itanium™ Processor Cartridge
Address
(Hex)
Upper
Addressa
a. Thou gh th i s ad dre ssing sche me i s ta rg ete d for up t o 4- way M P sy stem s, mo re pro cesso rs can be suppor ted by usi n g a m ulti -
plexed (or separate) SMBus implementation.
Cartridge Select M emo ry
Device
Select
Read/
Write Device
Addressed
Bits 7–4(SMA1)
Bit 3 (SMA0)
Bit 2 Bit 1 Bit 0
A0h/A1h 1010 0 0 0 X Scratch EEPROM 1
A2h/A3h 1010 0 0 1 X Processor Information ROM 1
A4h/A5h 1010 0 1 0 X Scratch EEPROM 2
A6h/A7h 1010 0 11 X Processor Information ROM 2
A8h/A9h 1010 1 0 0 X Scratch EEPROM 3
AAh/ABh 1010 1 0 1 X Processor Information ROM 3
ACh/ADh 1010 1 1 0 X Scratch EEPROM 4
AEh/AFh 1010 1 1 1 X Processor Information ROM 4
Table 6-4. Processor Information ROM Format
Offset/Section # of Bits Function Notes Values
HEADER: 00h 8 Data Format
Revision Two 4-bit hex digits
01h-02h 16 EEPROM Si ze Size in bytes, 16 bit
binary number 128 bytes = 0080h, LSB at
the lower address
03h 8 Processor Data
Address Byte pointer, 00h if not
present 0Eh
04h 8 Processor Core
Data Address Byte pointer, 00h if not
present 16h
05h 8 L3 Cache Data
Address Byte pointer, 00h if not
present 26h
06h 8 Cartridge Data
Address Byte pointer, 00h if not
present 33h
07h 8 Part Number Data
Address Byte pointer, 00h if not
present 3Bh
08h 8 Thermal Reference
Data Address Byte pointer, 00h if not
present 61h
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 6-5
System Management Feature Specifications
09h 8 Feature Data
Address Byte pointer, 00h if not
present 65h
0Ah 8Other Data Address Byte pointer, 00h if not
present 79h
0Bh-0Ch 16 Reserved R e se rved fo r fu t u r e
use
0Dh 8 Checksum 1 byte checksum
PROC ES SO R : 0Eh
0Eh-13h 48 S-Spec/QDF
Number Six 8-bit ASCII
characters 00VXYZa
14h[1:0] 2Sample/Production 00b = Sample only
all others =
Productions
14h[7:2] 6Reserved Re s e rved fo r fu t u r e
use
15h 8 Checksum 1 byte checksum
CORE: 16h
16h 8 Architectur e
Revision From CPUIDb
17h 8 Proces sor Core
Family From CPUIDb
18h 8 Proces sor Core
Model From CPUIDb
19h 8 Proces sor Core
Stepping (Revision) From CPUIDb
1Ch-1Ah 24 Reserved Reserved fo r fu ture
use
1Dh-1Eh 16 Maximum Core
Frequency in MHz, 16 bit binary
number i.e. 800MHz = 0320h, LSB
at the lower address
1Fh-20h[3:0] 12 Maximum System
Bus Frequency in MHz, 12 bit binary
number i.e. 133Mhz = 085h, LSB
at the lower address
20h[7:4]-22h[3:0] 16 Processor Core
Voltage Voltage in mV, 16 bit
binary number i.e. 1.6V = 0640h, LSB at
the lower address
22h[7:4]-23h[3:0] 8 Core Voltage
Tolerance, High Power Pod tolerance in
mV, +
23h[7:4]-24h[3:0] 8 Core Voltage
Tolerance, Low Power Pod tolerance in
mV, –
24h[7:4]-25h[3:0] 8Reserved R e se rved fo r fu ture
use
25h[7:4]-26h[3:0] 8 Checksum 1 byte checksum
L3 CACHE: 26h
26h[7:4]-2Ah[3:0] 32 Reserved Reserved fo r fu t u r e
use
2A[7:4]-2Ch[[3:0] 16 L3 Cache Size in Kbytes, a 16 bit
binary number
2MB = 0800h,
4MB = 1000h, LSB written
at the lower address
2Ch[7:4] 4 Number of SRAM
Components One 4-bit hex digit
2Dh[3:0] 4Reserved R e se rved fo r fu t u r e
use
Table 6-4. Processor Information ROM Format (Cont’d)
Offset/Section # of Bits Function Notes Values
System Management Feature Specifications
6-6 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
2Dh[7:4]-2Fh[3:0] 16 L3 Cache V oltage Voltage in mV, 16 bit
binary number LSB at the lower address
2Fh[7:4]-30h[3:0] 8 L3 Cache V oltage
Tolerance, High Power Pod tolerance in
mV, +
30h[7:4]-31h[3:0] 8 L3 Cache Volt age
Tolerance, Low Power Pod tolerance in
mV, –
31h[7:4] 4 Cache Stepp ing ID One 4-bit hex digit
32h[3:0] 4Reserved Reserve d fo r future
use
32h[7:4]-33h[3:0] 8 Checks um 1 byte checksum
CARTRIDGE: 33h
33h[7:4]-37h[3:0] 32 Cartridge Revision Four 8-bit ASCII
characters VXYZc
37h[5:4] 2 Substrate Revision
Software ID 2-bit revision number
37h[7:6]-3Ah[5:0] 24 Reserved Re served fo r futur e
use
3Ah[7:6]-3Bh[5:0] 8 Checksum 1 byte checksum
PART NUMBERS: 3Bh
3Bh[7:6]-42h[5:0] 56 Processor Part
Number Seven 8-bit ASCII
characters ABCVXYZd
42h[7:6]-48h[3:0] 46 Reserved Reserved
48h[7:4]-60h[3:0] 192 Reserved Reserve d fo r future
use
60h[7:4]-61h[3:0] 8 Checks um 1 byte checksum
THERMAL REF: 61h
61h[7:4]-62h[3:0] 8 Upper Temp
Reference Byte See Section 6.4 e
62h[7:4]-64h[3:0] 16 Reserved Reserve d fo r future
use
64h[7:4]-65h[3:0] 8 Checks um 1 byte checksum
FEATURES: 65h
65h[7:4]-69h[3:0] 32 IA-32 Processor
Core Feature Flags From CPUIDb32 bit binary number , LSB
is written at the lowest
address
69h[7:4]-71h[3:0] 64 Reserved Reserve d fo r future
use
71h[7:4]-75h[3:0]
32
Cartridge Feature
Flags
Other bits = unused
[4] = Upper temp
reference byte
[3] = unused
[2] = SCRATCH
EEPROM present
[1] = Core VID present
[0] = L3 cache VID
present
1= present, 0= not present
75h[7:4] 4 Number of Devices
in TAP Chain One 4-bit hex digit 3 = 2M cart, 5 = 4M cart
77h-76h 16 Reserved Reserve d fo r future
use
78h 8 Checks um 1 byte checksum
Table 6-4. Processor Information ROM Format (Cont’d)
Offset/Section # of Bits Function Notes Values
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 6-7
System Management Feature Specifications
6.3.2 Scratch EEPROM
Also available on the SMBus interface on the cartridge is an EEPROM which may be used for
other data at the system vendor’s discretion. The data in this EEPR OM, once programm e d, can be
write-protected by asserting the active-high SMWP signal.
6.3.3 Processor Information ROM and Scratch EEPROM
Supported SMBUS Transactions
The PIROM and Scratch EEPROM respond to three of the SMBus read packet types: current
address read, random address read, and sequential read.
Table 6-5 shows the format of the current address read SMBus packet. Table 6-6 shows the format
of the random read SMBus packet.
Sequential reads may begin with a cur rent address read or a random a ddress read . After the SMBus
host controller receives the data word, it responds with an acknowledge. This will continue until
the SMBus host controller responds with a negative acknowledge and a stop. In the tables, ‘S’
represents the SM Bus start bit, ‘P’ represents a stop bit, ‘R’ represents a read, ‘W’ represents a
write bit, ‘A’ represents an acknowledge, and ‘///’ represents a negative acknowledge. The shaded
bits are transmitted by the Pro cessor Information ROM or Scratch EEPROM and the bits that are
not shaded are trans mitted by th e SMBus host con troller. In the tables the data address es indicate 8
bits. The SMBus host controller should transmit 8 bits, but as there are only 128 addresses, the
most signif icant bit is a don’t care.
The Scratch EEPROM responds to two write packet types: byte write and page write.
Table 6-7 shows the format of the byte write SMBus packet. Th e page write operates the s ame way
as the byte write except that the SMBus Host con troller does not send a stop after the fir st data byte
and acknowledge. The Scratch EEPROM internally increments its address. The SMBus host
controller continue s to transmit data bytes until it termin ates the sequence with a stop. All data
bytes will result in an acknowled ge from the Scratch EEPROM. If more than eight bytes are
written, the internal address will “roll over” and the previous data will be overwritten.
Performing a write with no data loads the address from which data should be read.
OTHER: 79h
7Fh-79h 56 Reserved Res e rved fo r fu ture
use
a. 00VXYZ, character 0 is written at the lowest address and character Z is written at the highest address. If the number of characters
is greater than four, then the first character is omitted. For example, S-Spec “SL4LT” is recorded as “L4LT” and the first character
“S” is omitted: ADDRESS VALUE
13h L
12h 4
11h L
10h T
0Fh 0
0Eh 0
b. Refer to the IA-64 Arch itectu re S oftwa re Deve lope r’s Manual for details on CPUID registers.
c. VXYZ, character V is written at the lowest address and character Z is written at the highest address.
d. ABCVXYZ, character A is written at the lowest address and character Z is written at the highest address.
e. This value has no unit(s) and is not a specific junction temperature.
Table 6-4. Processor Information ROM Format (Cont’d)
Offset/Section # of Bits Function Notes Values
System Management Feature Specifications
6-8 Intel® Itanium ™ Processor at 800 MHz and 733 MHz Datasheet
The internal address counter keeps track of the address accessed during the last read or write
operation, incremented by one. Address “roll over” during reads is from the last byte of the last
eight byte page to the first byte of the first page. “Roll over” during writes is from the last byte of
the current eight byte page to the first byte of the same page.
6.4 Thermal Sensing Device
The Intel Itanium processor cartridge’s thermal sensing device provides a means of acquiring
thermal data from the processor. The accuracy of the thermal reading is expected to be better than
±3°C. The thermal sens ing device is composed o f control logic, SMBus interface logic, a p recision
analog to digital converter, and a precision current source. The thermal sensing device drives a
small current through a thermal diode located on the processor core and measures the voltage
generated across the therm al diode by the current. With this in f orm ation, the thermal sensing
device computes a byte of temperature data. Software running on the processor or on a micro-
controller can use the temperature data from the thermal sensing device to thermally manage the
system.
The thermal sensing device provides a register with a data byte (7 bits plus sign) which contains a
value correspon ding to the sampl ed out put of the t hermal dio de in the In tel Itanium processo r core.
The value of the byte read from the thermal sensor gives an accurate reading of processor core
temperature at the time of the reading. This data can be used in conjunction with the Upper
Temperature Reference byte (provided in the Processor Information ROM) for thermal
management purposes. The temperature data from the thermal sensor can be read out digitally
using an SMBus read command (see Section 6.4.1). The thermal sensor starts detecting when
SMBus power is applied to the processor, and resets itself at power-up.
The thermal sensing d evice also contains alarm registers to store u pper and lower thermal r eference
threshold data. These values can be individually programmed on the thermal sensor. If the
measured value equ als or exceeds the alarm threshol d value, the appropriate bit is set in the ther mal
sensing device status register, which is also brought out to the system bus via the THRMALERT#
signal (see Section 5.1.1 for more details). At power -up , the appropri ate alarm register values need
to be program med into the thermal sensing device via the SMBus. It is recommended that the up per
thermal reference threshold byte (provided in the Processor Information ROM) be used for setting
the upper threshold value in the alarm register.
Table 6-5. Current Address Read SMBus Packet
S Device Address R/W# AData /// P
1 7 bits 1 18 bits 1 1
Table 6-6. Random Address Read SMBus Packet
SDevice
Address R/W# AData
Address AS
Device
Address R/W# AData /// P
17 bits 018 bits1 1 7 bits 1 18 bits 1 1
Table 6-7. Byte Write SMBus Packet
SDevice
Address R/W# A Data Address ADataAP
17 bits0
18 bits1 8 bits 11
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 6-9
System Management Feature Specifications
Note: The upper temperature reference byte in the PIROM is unitless and is not any specific junction
temperature. It is a value to be used as a reference. By using a value, in the Thigh register, that is
smaller than the upper temperature reference byte by a number of 10, the THRMALERT# signal
will be tri pped 10°C earlier than by using the reference byte unmodified.
When polling the thermal sensing device on the cartridge to read the processor temperatures, it is
recommended that the polling frequency be every 0.5 to 1 second.
6.4.1 Thermal Sensing Device Supported SMBus Transactions
The thermal sen sing device res ponds to five of the SMBus packet types: write b yte, read byte, send
byte, receive byte, and ARA (Alert Response Address). Table 6-8 through Table 6-12 diagram the
five packet typ es. In th ese tables, ‘S’ represents the SMBus start bit, ‘P’ represents a st op bit, ‘Ack’
represents an acknowledge, and ‘///’ represents a negative acknowledge. The shaded bits are
transmitted by th e therma l sensor and the unshaded bits are transmitted by th e SMBus host
controller.
The send byte packet is used only for sending one-shot commands. The receive byte packet
accesses the regis ter commanded by the last read byte packet. If a receive byte pack et was preceded
by a write byte or send byte packet more recently than a read byte packet, then the behavior is
undefined.
Table 6-8. Write Byte SMBus Packet
S Address Write Ack Command Ack Data Ack P
17 bits 1 1 8 bits 1 8 bits 11
Table 6-9. Read Byte SMBus Packet
S Address Write Ack Command Ack S Address Read Ack Data /// P
17 bits 1 1 8 bits 1 1 7 bits 1 18 bit s 1 1
Table 6-10. Send Byte SMBus Packet
S Address Write Ack Command Ack P
17 bits 1 18 bits 1
Table 6-11. Receive Byte SMBus Packet
S Address Read Ack Data /// P
17 bits 1 18 bits 1 1
Table 6-12. ARA SMBus Packet
S ARA Read Ack Address /// P
1 0001 100 1 11001 1011 1 1
System Management Feature Specifications
6-10 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
Table 6-13 shows the encoding of the command byte. All of the commands are for reading or
writing registers in the thermal sensor except the one-shot command (OSHT). The one-shot
command forces the immediate start of a new voltage-to-temperature conversion cycle. If a
conversion is in progr ess when the one-shot comm and is received, then the command is ignored. If
the thermal sensing device is in standby mode when the one-shot command is received, a
conversion is performed and the sensor return s to standby mode. If the thermal sensor is in auto-
convert mode and is between conversions, then the conversion rate timer resets, and the next
automatic conversion takes place after a full delay elapses.
The default command after reset is the reserved value (00h). After reset, receive byte packets will
return invalid data unti l anoth e r command is sen t to the thermal sensing device.
6.4.2 T hermal Sensing Device Registers
The system management software can configure and control the thermal sensor by writing to and
interacting with different registers in the thermal sensor. These registers include a Thermal
Reference register, two Thermal Limit registers, a Status register, a Configuration register, a
Conversion Rate register, an d other reserve d registers. The follow i ng subs ections describe the
registers in detail.
6.4.2.1 Thermal Reference Registers
The thermal sensing device has an internal thermal reference register which contains the thermal
reference value read by the thermal sensing device connected to the processor core thermal diode.
This value ranges from +127 to –128 decimal and is expressed as a two’s complement, eight-bit
number. These registers are saturating, i.e. values above 127 are represented at 127 decimal, and
values below –128 are represented as –128 decimal.
Table 6-13. Command Byte Bit Assignment
Register Command Reset State Function
RESERVED 00h N/A Reserv ed for future use
RRT 01h N/A Read processor core thermal data
RS 02h N/A Read status byte (flags, busy signal)
RC 03h 0000 0000 Read configuration byte
RCR 04h 0000 0010 Read conversion rate byte
RESERVED 05h 0111 1111 Reserved for future use
RESERVED 06h 1100 1001 Reserv ed for future use
RRHL 07h 0111 1111 Read process or core thermal diode THIGH limit
RRLL 08h 1100 1001 Read process or core thermal diode TLOW limit
WC 09h N/A Write configuration byte
WCR 0Ah N/A Write conversion rate byte
RESERVED 0Bh N/A Reserved for future use
RESERVED 0Ch N/A Reserved for future use
WRHL 0Dh N/A Write processor core thermal diode THIGH limit
WRLL 0Eh N/A Write processor core thermal diode TLOW limit
OSHT 0Fh N/ A One shot command (use send byte packet)
RESERVED 10h - FFh N /A Reserved for future use
Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet 6-11
System Management Feature Specifications
6.4.2.2 Thermal Limit Registers
The thermal sensing device has two thermal limit registers; they define high and low limits for the
processor core thermal diode. The encoding for these registers is the same as for the thermal
reference register. If the diode thermal value equals or exceeds one of its limits, then its alarm bit in
the Status Register is triggered. This indication is also brought out to the system bus via the
THRMALERT# signal.
6.4.2.3 Status Register
The status re gister shown in Table 6-14 indicates which (if any) ther mal value thresholds hav e been
exceeded. It also indicates if a conversion is in progress or if an open circuit has been detected in
the processor core thermal diode connection. Once set, alarm bits stay set until they are cleared by
a status register read. A successful read to the status register will clear any alarm bits that may have
been set, unless the alarm condition persists. Note that the THRMALERT# interrupt signal is
latched and is not automatically cleared when the status flag bit is cleared. The latch is cleared by
sending th e ARA (0001100) on the SMBus.
6.4.2.4 Configuration Register
The configuration register controls the operating mode (standby vs. auto-convert) of the thermal
sensing de vice. Table 6-15 shows the format of the configuration register. If the RUN/STOP bit is
set (high) then the thermal sensing device immediately stops converting and enters standby mode.
The thermal sensing device will still perform analog-to-digital conversions in standby mode when
it receives a one-shot command. If the RUN/STOP bit is clear (low) then the therm al sensor en ters
auto-conversion mode. The thermal sensor starts operati ng in free running mode, auto-converting
at 0.25 Hz after power-up.
Table 6-14. Thermal Sensing Device Status Register
Bit Name Function
7 (MSB) BUS Y A one indicates that the device’s analog to digital converter is busy converting.
6 RESERVED Reserved for future use.
5 RESERVED Reserved for future use.
4 RHIGH A one indicates that the processor core thermal diode high temperature alarm
has activated.
3RLOW
A one indicates that the processor core thermal diode low temperature alarm
has activated.
2 OPEN A one indicates an open fault in the connection to the processor core diode.
1 RESERVED Reserved for future use.
0 (LSB) RESERVED Reserved for future use.
Table 6-15. Thermal Sensing Device Configuration Register
Bit Name Reset
State Function
7 (MSB) RESERVED 0 Reserved for future use.
6 RUN/STOP 0 Standby mode control bit. If high, the device immediately stops
converting, and enters standby mode. If low , the device converts in
either one-shot or auto-convert mode, see Section 6.4.2.5
5–0 RESERVED 0 Reserv ed for futu re use.
System Management Feature Specifications
6-12 Intel® Itanium™ Processor at 800 MHz and 733 MHz Datasheet
6.4.2.5 Conversion Rate Register
The contents of the conversion rate register determine the nominal rate at which analog-to-digital
conversions happen when the thermal sensing device is in auto-convert mode. Table 6-16 shows
the mapping between conversion rate register values and the conversion rate. As indicated in
Table 6-13, the conversion rate register is set to its default state of 02h (0.25 Hz nominally) when
the thermal sensing device is powered up. There is a ±25% error toleran ce between the conversio n
rate indicated in the conversion rate register and the actual conversion rate.
Table 6-16. Thermal Sensing Device Conversion Rate Register
Register Contents Conversion Rate (Hz)
00h 0.0625
01h 0.125
02h 0.25
03h 0.5
04h 1
05h 2
06h 4
07h 8
08h to FFh Reser ved for fut ure u se